Composite electrode, and light-emitting diode having composite electrode and preparation method therefor

Abstract

Provided are a composite electrode, and a light-emitting diode having the composite electrode and a preparation method therefor, relating to the technical field of semiconductors. The light-emitting diode comprises an epitaxial layer and the composite electrode. The composite electrode comprises an adhesion barrier layer and a solder layer sequentially stacked on the epitaxial layer; the solder layer comprises at least two solder sub-layers sequentially stacked; each solder sub-layer is a gold-tin alloy layer; in each solder sub-layer, the mass ratio of gold element to tin element increases progressively in the direction away from the adhesion barrier layer; and in two adjacent solder sub-layers, the maximum mass ratio of gold element to tin element in the solder sub-layer closer to the adhesion barrier layer is greater than the minimum mass ratio of gold element to tin element in the solder sub-layer farther from the adhesion barrier layer. The present disclosure can effectively improve the soldering and packaging reliability of the light-emitting diode.

Description

Composite electrode, light-emitting diode with composite electrode and its preparation method

[0001] This application claims priority to Chinese Patent Application No. 202410515163.7, filed on April 26, 2024, entitled "Light Emitting Diode with Composite Electrode and Method for Fabrication Thereof", the entire contents of which are incorporated herein by reference. Technical Field

[0002] This disclosure belongs to the field of semiconductor technology, and specifically relates to a composite electrode, a light-emitting diode having the composite electrode, and a method for preparing the same. Background Technology

[0003] A light-emitting diode (LED) is a semiconductor diode that can convert electrical energy into light energy.

[0004] In related technologies, light-emitting diodes (LEDs) mainly consist of an epitaxial layer and electrodes. The electrodes are electrically connected to the epitaxial layer, allowing external current to be introduced into the epitaxial layer, thus energizing it and causing it to emit light. Currently, there is a gold-tin electrode, which is an AuSn alloy structure. During packaging and soldering, the gold-tin electrode itself can act as solder, has a high reflow temperature, and can withstand high temperatures, making it suitable for use in high-end LEDs.

[0005] However, during the fabrication of gold-tin electrodes, the actual gold-tin mass ratio is not constant. As the thickness of the gold-tin electrode increases, the proportion of gold continuously increases, while the proportion of tin continuously decreases. The increased gold content leads to a higher melting point of the gold-tin electrode, further causing soldering abnormalities such as cold solder joints and desoldering, thus affecting the reliability of LED packaged devices. Summary of the Invention

[0006] This disclosure provides a composite electrode, a light-emitting diode having the composite electrode, and a method for fabricating the same.

[0007] On one hand, embodiments of this disclosure provide a light-emitting diode, including an epitaxial layer and a composite electrode;

[0008] The composite electrode is electrically connected to the epitaxial layer. The composite electrode includes an adhesion barrier layer and a solder layer sequentially stacked on the epitaxial layer. The solder layer includes at least two sequentially stacked solder sub-layers. Each solder sub-layer is a gold-tin alloy layer, and the mass ratio of gold to tin in each solder sub-layer changes from small to large along the direction away from the adhesion barrier layer. Among two adjacent solder sub-layers, the maximum mass ratio of gold to tin in the solder sub-layer closer to the adhesion barrier layer is greater than the minimum mass ratio of gold to tin in the solder sub-layer farther from the adhesion barrier layer.

[0009] Optionally, the maximum mass ratio of gold to tin in the weld sublayer furthest from the adhesion barrier layer is less than the maximum mass ratio of gold to tin in the other weld sublayers.

[0010] Optionally, the maximum mass ratio of gold to tin in each of the weld sublayers is less than 6.

[0011] Optionally, the maximum mass ratio of gold to tin in the weld sublayer furthest from the adhesion barrier layer is less than 5.

[0012] Optionally, the thickness of the weld sublayer furthest from the adhesion barrier layer is 1 / 3 to 1 / 5 of the total thickness of the weld layer.

[0013] Optionally, the welding layer includes two welding sub-layers, the welding sub-layer closer to the adhesion barrier layer is the first sub-layer, and the welding sub-layer farther from the adhesion barrier layer is the second sub-layer, the thickness of the second sub-layer being less than the thickness of the first sub-layer.

[0014] Optionally, the thickness of the first sublayer is d1, and the thickness of the second sublayer is d2, where d2 ≤ d1 / 2.

[0015] Optionally, the adhesion barrier layer includes an adhesion layer and a barrier layer;

[0016] The adhesion layer is one or more of Cr and Ti metals;

[0017] The barrier layer is one or more of the following metals: Ti, Ni, Pt, and Au.

[0018] Optionally, the adhesion barrier layer is a CrPtAu alloy structural component or a TiNiPtNi alloy structural component.

[0019] Optionally, each of the welded sub-layers uses a gold-tin alloy target as the vapor deposition target, and the mass ratio of gold to tin in the gold-tin alloy target is 3 to 5.

[0020] On the other hand, embodiments of this disclosure provide a method for fabricating a light-emitting diode, the method comprising: forming an adhesion barrier layer on one side of an epitaxial layer; and sequentially forming at least two solder sub-layers on one side of the adhesion barrier layer to obtain a solder layer, wherein each solder sub-layer is a gold-tin alloy layer, and the mass ratio of gold to tin in each solder sub-layer varies from small to large along the direction away from the adhesion barrier layer, and in two adjacent solder sub-layers, the maximum mass ratio of gold to tin in the solder sub-layer closer to the adhesion barrier layer is greater than the minimum mass ratio of gold to tin in the solder sub-layer farther from the adhesion barrier layer.

[0021] Optionally, each of the welded sub-layers uses a gold-tin alloy target as the vapor deposition target, and the mass ratio of gold to tin in the gold-tin alloy target is 3 to 5.

[0022] Optionally, the maximum mass ratio of gold to tin in the weld sublayer furthest from the adhesion barrier layer is less than the maximum mass ratio of gold to tin in the other weld sublayers.

[0023] Optionally, the maximum mass ratio of gold to tin in each of the weld sublayers is less than 6.

[0024] Optionally, the maximum mass ratio of gold to tin in the weld sublayer furthest from the adhesion barrier layer is less than 5.

[0025] Optionally, the thickness of the weld sublayer furthest from the adhesion barrier layer is 1 / 3 to 1 / 5 of the total thickness of the weld layer.

[0026] Optionally, at least two weld sublayers are sequentially formed on one side of the adhesion barrier layer, including:

[0027] Prepare the first sublayer of at least two said weld sublayers;

[0028] Prepare a second sublayer of at least two said weld sublayers, the thickness of the second sublayer being less than the thickness of the first sublayer.

[0029] Optionally, the thickness of the first sublayer is d1, and the thickness of the second sublayer is d2, where d2 ≤ d1 / 2.

[0030] In another aspect, a composite electrode is provided, comprising an adhesion barrier layer and a solder layer stacked sequentially, wherein the solder layer comprises at least two solder sub-layers stacked sequentially, each of the solder sub-layers being a gold-tin alloy layer, and the mass ratio of gold to tin in each solder sub-layer changing from small to large along the direction away from the adhesion barrier layer; in two adjacent solder sub-layers, the maximum mass ratio of gold to tin in the solder sub-layer closer to the adhesion barrier layer is greater than the minimum mass ratio of gold to tin in the solder sub-layer farther from the adhesion barrier layer.

[0031] Optionally, the maximum mass ratio of gold to tin in the weld sublayer furthest from the adhesion barrier layer is less than the maximum mass ratio of gold to tin in the other weld sublayers. Attached Figure Description

[0032] To more clearly illustrate the technical solutions in the embodiments of this disclosure, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0033] Figure 1 is a phase diagram of gold-tin binary alloys in related technologies;

[0034] Figure 2 is a schematic diagram of the structure of a light-emitting diode provided in an embodiment of this disclosure;

[0035] Figure 3 is a schematic diagram of the structure of the welding layer provided in an embodiment of this disclosure;

[0036] Figure 4 is a graph showing the change of K value between the gold-tin electrode in the related art and the composite electrode in this embodiment;

[0037] Figure 5 is a schematic diagram of another structure of the light-emitting diode provided in an embodiment of this disclosure;

[0038] Figure 6 is a flowchart of a method for fabricating a light-emitting diode according to an embodiment of this disclosure;

[0039] Figure 7 is a flowchart of another method for fabricating a light-emitting diode provided in an embodiment of this disclosure.

[0040] The symbols in the diagram represent the following meanings:

[0041] 10. Epitaxial layer;

[0042] 110. First semiconductor layer; 120. Light-emitting layer; 130. Second semiconductor layer;

[0043] 20. Composite electrode;

[0044] 210, Adhesion barrier layer; 211, Adhesion layer; 212, Barrier layer; 220, Welding layer; 221, Welding sublayer;

[0045] 30. Substrate;

[0046] 40. Transparent conductive layer;

[0047] 50. Silver mirror layer;

[0048] 60. Protective layer;

[0049] 70. First insulating layer;

[0050] 810, Primary P electrode; 820, Primary N electrode;

[0051] 90. Second insulation layer. Detailed Implementation

[0052] To make the objectives, technical solutions, and advantages of this disclosure clearer, the embodiments of this disclosure will be described in further detail below with reference to the accompanying drawings.

[0053] A light-emitting diode (LED) is a semiconductor diode that can convert electrical energy into light energy.

[0054] In related technologies, light-emitting diodes (LEDs) mainly consist of an epitaxial layer and electrodes. The electrodes are electrically connected to the epitaxial layer, allowing external current to be introduced into the epitaxial layer, thus energizing it and causing it to emit light. Currently, there is a gold-tin electrode, which is an AuSn alloy structure. During packaging and soldering, the gold-tin electrode itself can act as solder, has a high reflow temperature, and can withstand high temperatures, making it suitable for use in high-end LEDs.

[0055] Figure 1 shows the phase diagram of a gold-tin binary alloy. As can be seen from Figure 1, when the mass ratio of Au to Sn in the AuSn alloy is 80:20, the AuSn alloy has the lowest melting point, approximately 280℃. It consists of a gold-tin mesophase (AuSn) and a close-packed hexagonal phase (Au5Sn), exhibiting excellent welding process performance and welding strength. In other words, the ideal mass ratio of Au to Sn in the AuSn alloy is 4, which is the ideal K value.

[0056] The gold-tin electrode is deposited using electron beam evaporation. A high-energy electron beam is generated by an electron gun and, under the constraint of a magnetic field, the electron beam strikes the gold-tin alloy target, heating the target to the evaporation temperature. The atoms in the target evaporate in a vacuum, fly to the wafer surface, and condense to form the gold-tin electrode.

[0057] However, during the fabrication of gold-tin electrodes, as the thickness of the gold-tin electrodes on the wafer surface gradually increases, the actual gold-tin mass ratio changes (the actual gold-tin mass ratio is K, K = Au wt% / Sn wt%). As the evaporation process proceeds and the thickness of the gold-tin electrodes gradually increases, the proportion of Au continuously increases, while the proportion of Sn continuously decreases. Table 1 shows a schematic table of K values ​​for different positions of the gold-tin electrodes in related technologies, with positions 1 to 7 arranged sequentially along the direction away from the epitaxial layer.

[0058] Table 1

[0059] As can be seen, the K value changed from 4.00 at position 1 to 6.55 at position 7. As shown in Figure 1, as the K value increases, the melting point of the AuSn alloy increases significantly, which will lead to welding abnormalities such as cold solder joints and desoldering during packaging and soldering, affecting the reliability of the LED package device.

[0060] To address the aforementioned technical problems, this disclosure provides a light-emitting diode (LED). Figure 2 is a schematic diagram of the LED structure. Referring to Figure 2, in this embodiment, the LED includes an epitaxial layer 10 and a composite electrode 20. The composite electrode 20 is electrically connected to the epitaxial layer 10. The composite electrode 20 includes an adhesion barrier layer 210 and a solder layer 220 sequentially stacked on the epitaxial layer 10. The solder layer 220 includes at least two sequentially stacked solder sublayers 221. Each solder sublayer 221 is a gold-tin alloy layer, and the mass ratio of gold to tin in each solder sublayer 221 changes from small to large along the direction away from the adhesion barrier layer 210. Among two adjacent solder sublayers 221, the maximum mass ratio of gold to tin in the solder sublayer 221 closer to the adhesion barrier layer 210 is greater than the minimum mass ratio of gold to tin in the solder sublayer 221 farther from the adhesion barrier layer 210.

[0061] The light-emitting diode provided in this embodiment includes an epitaxial layer 10 and a composite electrode 20. External current can be introduced into the epitaxial layer 10 through the composite electrode 20, thereby energizing the epitaxial layer 10 to emit light. The composite electrode 20 includes an adhesion barrier layer 210 and a solder layer 220, wherein the adhesion barrier layer 210 serves to adhere and block current, and the solder layer 220 serves to provide a soldering base during packaging.

[0062] The solder layer 220 includes at least two sequentially stacked solder sub-layers 221. The mass ratio of gold to tin in each solder sub-layer 221 increases from small to large along the direction away from the adhesion barrier layer 210. In adjacent solder sub-layers 221, the maximum mass ratio of gold to tin in the solder sub-layer 221 closer to the adhesion barrier layer 210 is greater than the minimum mass ratio in the solder sub-layer 221 farther from the adhesion barrier layer 210. That is, in the solder layer 220, the mass ratio of gold to tin increases from small to large along the direction away from the adhesion barrier layer 210, then decreases, and then increases again, and so on.

[0063] In related technologies, the mass ratio of gold to tin in a single-layer solder layer varies from small to large along the direction away from the adhesion barrier layer. With the same solder layer thickness, the mass ratio of gold to tin on the outermost side of the solder layer provided in this embodiment is lower than that in related technologies. This avoids an increase in melting point due to excessive imbalance in the mass ratio between Au and Sn, thus preventing soldering abnormalities such as cold solder joints and desoldering, and improving the reliability of the LED packaged device.

[0064] Optionally, the maximum mass ratio of gold to tin in the solder sublayer 221 furthest from the adhesion barrier layer 210 is lower than the maximum mass ratio of gold to tin in other solder sublayers 221. The solder sublayer 221 furthest from the adhesion barrier layer 210, i.e., the last solder sublayer, serves as the most direct soldering basis during encapsulation soldering. Minimizing the maximum mass ratio of gold to tin in the last solder sublayer 221 helps to make the K value of this solder sublayer 221 approach the ideal K value.

[0065] Optionally, the maximum mass ratio of gold to tin in the solder sublayer 221 furthest from the adhesion barrier layer 210 is less than 5. That is, the K value of the last solder sublayer 221 is less than 5, which is close to the aforementioned ideal K value.

[0066] Optionally, the maximum mass ratio of gold to tin in each weld sublayer 221 is less than 6. By limiting the K value of each weld sublayer 221, the melting point of the composite electrode can be limited, thereby avoiding welding abnormalities such as incomplete soldering and desoldering.

[0067] In this embodiment, the vapor deposition target for each weld sublayer 221 is a standard vapor deposition target, which is an AuSn alloy target. That is, each weld sublayer 221 uses one AuSn alloy target as the vapor deposition target. The mass ratio of Au to Sn in the AuSn alloy target is 3 to 5.

[0068] By dividing the solder layer 220 into at least two solder sub-layers 221, and the evaporation time of the solder sub-layers 221 will be less than the total evaporation time of the solder layer 220, the change time of the mass ratio between Au and Sn in the solder sub-layers 221 can be reduced. This allows the mass ratio between Au and Sn in each solder sub-layer 221 to be kept within the standard range, and there will be no increase in melting point due to excessive imbalance of the mass ratio between Au and Sn. This avoids soldering abnormalities such as cold solder joints and desoldering, and improves the reliability of the LED package device.

[0069] In this embodiment, the thickness of the weld sublayer 221 furthest from the adhesion barrier layer 210 is 1 / 3 to 1 / 5 of the total thickness of the weld layer 220.

[0070] The solder sublayer 221 furthest from the adhesion barrier layer 210 is the last solder sublayer 221 deposited by vapor deposition, and it serves as the most direct base for soldering during encapsulation. Therefore, the K value of this solder sublayer 221 needs to be as close as possible to the ideal K value. In the above implementation, the thickness of this solder sublayer 221 is designed to be 1 / 3 to 1 / 5 of the total thickness of the entire solder layer 220. This makes the solder sublayer 221 thinner, the vapor deposition time shorter, and the change time of the mass ratio between Au and Sn in the solder sublayer 221 shorter, which is beneficial for making the K value of the solder sublayer 221 close to the ideal K value.

[0071] Figure 3 is a schematic diagram of the structure of the welding layer 220 provided in the embodiment of this disclosure. Referring to Figure 3, in this embodiment, the welding layer 220 includes two welding sub-layers 221. The welding sub-layer 221 closer to the adhesion barrier layer 210 is the first sub-layer, and the welding sub-layer 221 farther away from the adhesion barrier layer 210 is the second sub-layer. The thickness of the second sub-layer is less than the thickness of the first sub-layer.

[0072] In the above implementation, the welding layer 220 is divided into a first sub-layer and a second sub-layer. On the one hand, this can bring the K value closer to the ideal K value. On the other hand, it can simplify the structure of the welding layer 220, thereby simplifying the preparation process of the welding layer 220 and improving the preparation efficiency.

[0073] Of course, in other embodiments, the number of welding sublayers 221 can be increased according to actual needs, such as three or four, and this disclosure does not limit this.

[0074] The following explanation uses the example of weld layer 220, which includes two weld sublayers 221.

[0075] In this embodiment, the thickness of the first sub-layer is d1, the thickness of the second sub-layer is d2, and d2≤d1 / 2.

[0076] In the above implementation, limiting the thickness of the second sublayer, that is, limiting the evaporation time of the second sublayer, results in a shorter change time for the mass ratio between Au and Sn of the standard evaporation target, which is beneficial for making the K value of the second sublayer close to the ideal K value.

[0077] Table 2 is a schematic table of K values ​​at different positions of the composite electrode 20 in the embodiments of this disclosure. Positions 1 to 7 are arranged sequentially along the direction away from the epitaxial layer 10. Positions 1 to 7 counted in Table 2 correspond one-to-one with positions 1 to 7 counted in Table 1, that is, they are at the same positions in the thickness direction of the welding layer 220.

[0078] Table 2

[0079] As can be seen, positions 1 to 4 are all located within the first sublayer, and positions 5 to 7 are all located within the second sublayer (see the solid black dots in Figure 3). The K value of the first sublayer changes from 3.79 at position 1 to 5.70 at position 4. However, since the second sublayer is deposited using a completely new standard vapor deposition target, the K value of the second sublayer decreases to 3.72 at position 5, and gradually increases to 4.55 as the vapor deposition progresses, approaching the ideal K value.

[0080] Figure 4 shows the K-value variation between the gold-tin electrode in related technologies and the composite electrode 20 in this embodiment. As can be seen from Figure 4, the K-value of the gold-tin electrode gradually increases, and the difference between it and the ideal K-value also gradually increases. After the K-value of the composite electrode 20 increases to a certain extent, it decreases again under the action of replacing it with a brand-new standard vapor deposition target, thus keeping the difference between it and the ideal K-value relatively small.

[0081] In this embodiment, the adhesion barrier layer 210 includes an adhesion layer 211 and a barrier layer 212. The adhesion layer 211 is one or more of Cr and Ti metals, and the barrier layer 212 is one or more of Ti, Ni, Pt, and Au metals.

[0082] For example, the adhesion barrier layer 210 is a CrPtAu alloy structural component or a TiNiPtNi alloy structural component.

[0083] The composite electrode 20 has been introduced above. The other thin film layers of the light-emitting diode will be introduced below.

[0084] Figure 5 is a schematic diagram of another structure of a light-emitting diode. In this embodiment, the epitaxial layer 10 includes a first semiconductor layer 110, a light-emitting layer 120, and a second semiconductor layer 130 stacked sequentially. The first semiconductor layer 110 is of a first conductivity type, and the second semiconductor layer 130 is of a second conductivity type, and the second conductivity type is different from the first conductivity type.

[0085] When the light-emitting diode is working, an electron transition occurs between the first semiconductor layer 110 and the second semiconductor layer 130, and the light-emitting layer 120 emits light.

[0086] For example, the first semiconductor layer 110 is an N-type gallium nitride layer, the light-emitting layer 120 is a quantum well layer, and the second semiconductor layer 130 is a P-type gallium nitride layer.

[0087] In this embodiment, there are two composite electrodes 20. One composite electrode 20 serves as a secondary N-electrode and is electrically connected to the second semiconductor layer 130, while the other composite electrode 20 serves as a secondary P-electrode and is electrically connected to the first semiconductor layer 110. Both composite electrodes 20 have the same thickness.

[0088] In this embodiment, the light-emitting diode also includes a substrate 30, which provides a basis for the growth of the epitaxial layer 10.

[0089] For example, substrate 30 is a sapphire substrate, a silicon substrate, or other light-emitting diode substrate material.

[0090] Of course, in other embodiments, the light-emitting diode may not have a substrate 30, and this disclosure does not limit this.

[0091] In this embodiment, the light-emitting diode further includes a transparent conductive layer 40, which covers one side of the epitaxial layer 10.

[0092] The transparent conductive layer 40 is transparent and conductive. When the light-emitting layer 120 emits light, the light can pass smoothly through the transparent conductive layer 40, thereby improving the light extraction efficiency of the light-emitting diode and thus increasing its brightness. Simultaneously, the transparent conductive layer 40 is conductive and can provide current to the epitaxial layer 10.

[0093] For example, the transparent conductive layer 40 is an indium tin oxide (ITO) layer, which is formed by sputtering on the epitaxial layer 10 using magnetron sputtering technology. ITO has both optical transparency and high conductivity. When the light-emitting layer 120 emits light, the light can pass smoothly through the transparent conductive layer 40. The high conductivity ensures that the current can be effectively transferred to the light-emitting layer 120, thereby improving the luminous efficiency of the light-emitting diode.

[0094] In this embodiment, the light-emitting diode further includes a silver mirror layer 50 and a protective layer 60. The silver mirror layer 50 is located on the side of the transparent conductive layer 40 facing away from the epitaxial layer 10 and is used to reflect light. The protective layer 60 covers the silver mirror layer 50 and is used to protect the silver mirror layer 50 from oxidation.

[0095] In this embodiment, the light-emitting diode further includes a first insulating layer 70, which covers the protective layer 60 and the epitaxial layer 10 and serves as an insulating protection layer.

[0096] In this embodiment, the light-emitting diode further includes a primary P electrode 810, a primary N electrode 820, and a second insulating layer 90.

[0097] A primary P electrode 810 passes through the first insulating layer 70 and is connected to the silver mirror layer 50. A primary N electrode 820 passes through the first insulating layer 70 and is connected to the first semiconductor layer 110. A second insulating layer 90 covers the primary P electrode 810 and the primary N electrode 820. A secondary P electrode passes through the second insulating layer 90 and is connected to the primary P electrode 810. A secondary N electrode passes through the second insulating layer 90 and is connected to the primary N electrode 820.

[0098] For example, the primary P electrode 810 and the primary N electrode 820 are made of one or more of the following metals: Cr, Al, AlCu, Ti, Ni, Pt, Au, etc.

[0099] For example, the second insulating layer 90 is a DBR layer or a SiO2 layer. The DBR layer is a stack formed of SiO2 and Ti3O5.

[0100] Figure 6 is a flowchart of a method for fabricating a light-emitting diode (LED) according to an embodiment of this disclosure, used to fabricate the LED shown in Figure 1. In this embodiment, the fabrication method includes:

[0101] In step 601, an adhesion barrier layer 210 is formed on one side of the epitaxial layer 10.

[0102] In step 602, at least two welding sublayers 221 are sequentially formed on one side of the adhesion barrier layer 210.

[0103] Each of the weld sublayers is a gold-tin alloy layer, and the mass ratio of gold to tin in each weld sublayer changes from small to large along the direction away from the adhesion barrier layer. Among two adjacent weld sublayers, the maximum mass ratio of gold to tin in the weld sublayer closer to the adhesion barrier layer is greater than the minimum mass ratio of gold to tin in the weld sublayer farther from the adhesion barrier layer.

[0104] The welding layer 220 is prepared in step 602, and the composite electrode 20 is prepared in steps 601 and 602.

[0105] Optionally, the vapor deposition target of each weld sublayer 221 is a standard vapor deposition target, which is an AuSn alloy, and the mass ratio between Au and Sn in the standard vapor deposition target is 3 to 5. Each weld sublayer 221 constitutes a weld layer 220.

[0106] Since each solder sublayer 221 is deposited with a brand-new standard vapor deposition target and its deposition time is short, the mass ratio between Au and Sn in each solder sublayer 221 can be kept within the standard range. There will be no increase in melting point due to excessive imbalance in the mass ratio between Au and Sn, thereby avoiding soldering abnormalities such as cold solder joints and desoldering, and improving the reliability of the LED package device.

[0107] Figure 7 is a flowchart of another method for fabricating a light-emitting diode (LED) according to an embodiment of this disclosure, used to fabricate the LED shown in Figure 5. In this embodiment, the fabrication method includes:

[0108] Step 701: Provide a substrate 30.

[0109] For example, the substrate 30 is a sapphire substrate 30, a silicon substrate 30, or other light-emitting diode substrate 30 materials.

[0110] Step 702: Grow epitaxial layer 10.

[0111] For example, a first semiconductor layer 110, a light-emitting layer 120, and a second semiconductor layer 130 are sequentially grown using metal-organic chemical vapor deposition (MOCVD). The first semiconductor layer 110 has a first conductivity type, and the second semiconductor layer 130 has a second conductivity type different from the first conductivity type. An energy transition occurs between the first semiconductor layer 110 and the second semiconductor layer 130, causing the light-emitting layer 120 to emit light.

[0112] For example, the first semiconductor layer 110 is an N-type gallium nitride layer, the light-emitting layer 120 is a quantum well layer, and the second semiconductor layer 130 is a P-type gallium nitride layer.

[0113] Step 703: Grow a transparent conductive layer 40 on one side of the epitaxial layer 10.

[0114] For example, an indium tin oxide (ITO) thin film is deposited on the epitaxial layer 10 using magnetron sputtering or electron beam evaporation, and part of the ITO thin film is removed using photolithography and chemical wet etching processes to form a transparent conductive layer 40.

[0115] Step 704: Prepare a silver mirror layer 50 on one side of the transparent conductive layer 40.

[0116] For example, a silver mirror layer 50 is sputtered on an epitaxial wafer using magnetron sputtering or electron beam evaporation, and the material is one or a combination of materials such as Ag, Ni, Ti, and TiW.

[0117] Step 705: Prepare a protective layer 60 on one side of the silver mirror layer 50.

[0118] Step 706: Prepare a first insulating layer 70 on one side of the protective layer 60.

[0119] Step 707: Etch the first through hole and the second through hole in the first insulating layer 70.

[0120] Step 708: Prepare a primary P electrode 810 to pass through the first through hole and connect to the protective layer 60, and prepare a primary N electrode 820 to pass through the second through hole and connect to the first semiconductor layer 110.

[0121] Step 709: Prepare a second insulating layer 90, and etch a third through hole and a fourth through hole in the second insulating layer 90.

[0122] Step 710: Prepare a secondary P electrode to be connected to the primary P electrode 810 through the third through hole, and prepare a secondary N electrode to be connected to the primary N electrode 820 through the fourth through hole.

[0123] For example, the fabrication of a secondary P electrode includes:

[0124] Step 7101: Prepare the adhesion barrier layer 210.

[0125] Step 7102: At least two welding sub-layers 221 are sequentially prepared on one side of the adhesion barrier layer 210, and the vapor deposition target of each welding sub-layer 221 is a standard vapor deposition target, which is an AuSn alloy target, and the mass ratio between Au and Sn in the standard vapor deposition target is 3 to 5. Each welding sub-layer 221 constitutes a welding layer 220.

[0126] For example, the thickness of the weld sublayer 221 furthest from the adhesion barrier layer 210 is set to 1 / 3 to 1 / 5 of the total thickness of the weld layer 220.

[0127] For example, when the number of welded sublayers 221 is 2, step 7102 is implemented through the following steps:

[0128] Step 71021: Prepare the first sublayer. All vapor deposition targets are standard vapor deposition targets.

[0129] Step 71022: Replace with a brand new standard vapor deposition target and prepare a second sublayer. The thickness of the second sublayer is less than that of the first sublayer.

[0130] For example, the thickness of the first sublayer is d1, the thickness of the second sublayer is d2, and d2 ≤ d1 / 2.

[0131] Since each solder sublayer 221 is deposited with a brand-new standard vapor deposition target and its deposition time is short, the mass ratio between Au and Sn in each solder sublayer 221 can be kept within the standard range. There will be no increase in melting point due to excessive imbalance in the mass ratio between Au and Sn, thereby avoiding soldering abnormalities such as cold solder joints and desoldering, and improving the reliability of the LED package device.

[0132] Unless otherwise defined, the technical or scientific terms used herein shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” “third,” and similar terms used in this patent application specification and claims do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Similarly, the terms “an” or “a” and similar terms do not indicate a quantity limitation, but rather indicate the presence of at least one. The terms “comprising” or “including” and similar terms mean that the elements or objects preceding “comprising” or “including” encompass the elements or objects listed following “comprising” or “including” and their equivalents, and do not exclude other elements or objects. The terms “connected” or “linked” and similar terms are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. The terms “upper,” “lower,” “left,” “right,” etc., are used only to indicate relative positional relationships; when the absolute position of the described objects changes, the relative positional relationship may also change accordingly.

[0133] The above description is merely an optional embodiment of this disclosure and is not intended to limit this disclosure. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this disclosure should be included within the protection scope of this disclosure.

Claims

1. A light-emitting diode, comprising an epitaxial layer (10) and a composite electrode (20); The composite electrode (20) is electrically connected to the epitaxial layer (10). The composite electrode (20) includes an adhesion barrier layer (210) and a solder layer (220) stacked sequentially on the epitaxial layer (10). The solder layer (220) includes at least two solder sub-layers (221) stacked sequentially. Each solder sub-layer (221) is a gold-tin alloy layer. The mass ratio of gold to tin in each solder sub-layer (221) changes from small to large along the direction away from the adhesion barrier layer (210). Among two adjacent solder sub-layers (221), the maximum mass ratio of gold to tin in the solder sub-layer (221) closer to the adhesion barrier layer (210) is greater than the minimum mass ratio of gold to tin in the solder sub-layer (221) away from the adhesion barrier layer (210).

2. The light-emitting diode according to claim 1, wherein, The maximum mass ratio of gold to tin in the weld sublayer (221) furthest from the adhesion barrier layer (210) is less than the maximum mass ratio of gold to tin in the other weld sublayers (221).

3. The light-emitting diode according to claim 1, wherein, The maximum mass ratio of gold to tin in each of the aforementioned weld sublayers (221) is less than 6.

4. The light-emitting diode according to claim 1, wherein, The maximum mass ratio of gold to tin in the weld sublayer (221) furthest from the adhesion barrier layer (210) is less than 5.

5. The light-emitting diode according to claim 1, wherein, The thickness of the weld sublayer (221) furthest from the adhesion barrier layer (210) is 1 / 3 to 1 / 5 of the total thickness of the weld layer (220).

6. The light-emitting diode according to claim 1, wherein, The weld layer (220) includes two weld sub-layers (221), the weld sub-layer (221) closer to the adhesion barrier layer (210) is the first sub-layer, and the weld sub-layer (221) farther away from the adhesion barrier layer (210) is the second sub-layer, the thickness of the second sub-layer being less than the thickness of the first sub-layer.

7. The light-emitting diode according to claim 6, wherein, The thickness of the first sublayer is d1, and the thickness of the second sublayer is d2, where d2 ≤ d1 / 2.

8. The light-emitting diode according to any one of claims 1 to 7, wherein, Each of the welding sub-layers (221) uses a gold-tin alloy target as the vapor deposition target, and the mass ratio of gold to tin in the gold-tin alloy target is 3 to 5.

9. The light-emitting diode according to any one of claims 1 to 7, wherein, The adhesion barrier layer (210) includes an adhesion layer (211) and a barrier layer (212); The adhesion layer (211) is one or more of Cr and Ti metals; The barrier layer (212) is one or more of the following metals: Ti, Ni, Pt, and Au.

10. The light-emitting diode according to claim 9, wherein, The adhesion barrier layer (210) is a CrPtAu alloy structural component or a TiNiPtNi alloy structural component.

11. A method for fabricating a light-emitting diode, comprising: An adhesion barrier layer (210) is formed on one side of the epitaxial layer (10); At least two solder sub-layers (221) are sequentially formed on one side of the adhesion barrier layer (210) to obtain a solder layer (220). Each solder sub-layer (221) is a gold-tin alloy layer, and the mass ratio of gold to tin in each solder sub-layer (221) changes from small to large along the direction away from the adhesion barrier layer (210). Among two adjacent solder sub-layers (221), the maximum mass ratio of gold to tin in the solder sub-layer (221) closer to the adhesion barrier layer (210) is greater than the minimum mass ratio of gold to tin in the solder sub-layer (221) away from the adhesion barrier layer (210).

12. The preparation method according to claim 11, wherein, Each of the welding sub-layers (221) uses a gold-tin alloy target as the vapor deposition target, and the mass ratio of gold to tin in the gold-tin alloy target is 3 to 5.

13. The preparation method according to claim 11 or 12, wherein, The maximum mass ratio of gold to tin in the weld sublayer (221) furthest from the adhesion barrier layer (210) is less than the maximum mass ratio of gold to tin in the other weld sublayers (221).

14. The preparation method according to claim 11 or 12, wherein, The maximum mass ratio of gold to tin in each of the aforementioned weld sublayers (221) is less than 6.

15. The preparation method according to claim 11 or 12, wherein, The maximum mass ratio of gold to tin in the weld sublayer (221) furthest from the adhesion barrier layer (210) is less than 5.

16. The preparation method according to claim 11 or 12, wherein, The thickness of the weld sublayer (221) furthest from the adhesion barrier layer (210) is 1 / 3 to 1 / 5 of the total thickness of the weld layer (220).

17. The preparation method according to claim 16, wherein, The step of sequentially preparing at least two welding sublayers (221) on one side of the adhesion barrier layer (210) includes: Prepare the first sublayer of at least two of the weld sublayers (221); Prepare a second sublayer of at least two said weld sublayers (221), the thickness of the second sublayer being less than the thickness of the first sublayer.

18. The preparation method according to claim 17, wherein, The thickness of the first sublayer is d1, and the thickness of the second sublayer is d2, where d2 ≤ d1 / 2.

19. A composite electrode, comprising: An adhesion barrier layer (210) and a solder layer (220) are stacked sequentially. The solder layer (220) includes at least two solder sub-layers (221) stacked sequentially. Each solder sub-layer (221) is a gold-tin alloy layer. The mass ratio of gold to tin in each solder sub-layer (221) changes from small to large along the direction away from the adhesion barrier layer (210). Among two adjacent solder sub-layers (221), the maximum mass ratio of gold to tin in the solder sub-layer (221) closer to the adhesion barrier layer (210) is greater than the minimum mass ratio of gold to tin in the solder sub-layer (221) farther from the adhesion barrier layer (210).

20. The composite electrode according to claim 19, wherein, The maximum mass ratio of gold to tin in the weld sublayer (221) furthest from the adhesion barrier layer (210) is less than the maximum mass ratio of gold to tin in the other weld sublayers (221).

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