Method for preparing semiconductor structure and semiconductor structure thereof

Abstract

A method for preparing a semiconductor structure and a semiconductor structure thereof. The method comprises: providing a substrate and forming a stacked structure on the substrate, the stacked structure being formed by stacking a first dielectric layer and a second dielectric layer; forming a first opening, a plurality of first openings being arranged at intervals in a second direction; forming initial active pillars; forming second openings, each second opening being located between adjacent initial active pillars, and the size of each second opening in the second direction being smaller than the distance between the adjacent initial active pillars; removing portions of the initial active pillars to form active pillars; forming word line structures, the word line structures being arranged on one side of the active pillars; forming bit line structures, the bit line structures being electrically connected to one end of the active pillars; and forming capacitor structures, each capacitor structure being electrically connected to the other end of each active pillar.

Description

A method for preparing a semiconductor structure and the semiconductor structure thereof.

[0001] Cross-references

[0002] This application claims priority to Chinese Patent Application No. 202410510599.7, filed on April 25, 2024, entitled "A method for preparing a semiconductor structure and the semiconductor structure thereof", the entire contents of which are incorporated herein by reference. Technical Field

[0003] This disclosure relates to the field of semiconductors, and in particular to a method for preparing a semiconductor structure and the semiconductor structure thereof. Background Technology

[0004] The development of dynamic memory (DRAM) pursues performance indicators such as high speed, high integration density, and low power consumption. As the size of semiconductor device structures shrinks, the technological barriers encountered by existing structures are becoming increasingly apparent. Therefore, developing more novel structures based on existing structures is a powerful means to break through existing technological barriers.

[0005] The emergence of three-dimensional dynamic random access memory (3D DRAM) has met the above requirements. However, the existing 3D DRAM manufacturing process is complex, affecting the performance and yield of the semiconductor structure. Summary of the Invention

[0006] This disclosure provides a method for preparing a semiconductor structure and the semiconductor structure thereof, which at least helps to simplify the manufacturing process and improve the performance and yield of semiconductor memory devices.

[0007] According to some embodiments of this disclosure, one aspect of this disclosure provides a method for fabricating a semiconductor structure, including:

[0008] Provide a substrate; form a stacked structure on the substrate, the stacked structure being formed by stacking a first dielectric layer and a second dielectric layer in a third direction, the third direction being perpendicular to the surface of the substrate;

[0009] At least one first opening is formed, the first opening extending from the top of the stacked structure to the top of the substrate along the third direction, and a plurality of the first openings are spaced apart along a second direction, the second direction being parallel to the surface of the substrate and perpendicular to the third direction;

[0010] An initial active column is formed, which fills the first opening;

[0011] A second opening is formed, the second opening is located between adjacent initial active pillars, the size of the second opening along the second direction is smaller than the distance between adjacent initial active pillars, a first gap exists between the second opening and the initial active pillars, and the second opening extends from the top of the stacked structure to the top of the substrate along the third direction;

[0012] A portion of the initial active pillars is removed to form active pillars, which are spaced apart along the second direction and the third direction;

[0013] A word line structure is formed, wherein the word line structure is disposed on one side of the active column and extends along the third direction;

[0014] A bitline structure is formed, wherein the bitline structure is electrically connected to one end of the active post, and the bitline structure extends along the second direction;

[0015] A capacitor structure is formed, which is electrically connected to the other end of the active post. The capacitor structure extends along a first direction, which is perpendicular to the plane formed by the third direction and the second direction.

[0016] In some embodiments, the two ends of the second opening along the first direction are aligned with the two ends of the initial active post along the first direction; or one end of the second opening along the first direction is aligned with the end of the initial active post closest to the edge of the stacked structure, and the other end of the second opening extends along the first direction to the other edge of the stacked structure.

[0017] In some embodiments, removing a portion of the initial active pillar to form the active pillar specifically includes: exposing the stacked structure surrounding the initial active pillar through a second opening, etching away the first dielectric layer on the sidewall of the initial active pillar to form a notch, the notch exposing the sidewall of the initial active pillar, the notch being spaced apart along the third direction;

[0018] The initial active post is etched through the notch to form the active post, the active post forms a gap along the third direction, and the sidewall of the active post is covered by the second dielectric layer; the notch, the gap and the second opening together constitute the third opening.

[0019] In some embodiments, after forming the active pillar and before forming the word line structure, the method further includes: forming a third dielectric layer that fills the third opening;

[0020] A fourth opening is formed, the fourth opening being adjacent to one side of the active column and exposing part of the sidewall of the active column, the fourth opening having a second spacing with the non-adjacent active column, the fourth opening extending along the third direction to the bottom of the stacked structure; the word line structure is formed in the fourth opening.

[0021] In some embodiments, forming a bit line structure specifically includes: removing the second dielectric layer at one end of the active pillar to form a first notch; doping one end of the active pillar through the first notch to form a first doped region; forming the bit line structure in the first notch, wherein the bit line structure is electrically connected to the first doped region.

[0022] In some embodiments, forming a capacitor structure specifically includes: removing the second dielectric layer at the other end of the active pillar to form a second notch; doping the other end of the active pillar through the second notch to form a second doped region; and forming the capacitor structure in the second notch, wherein the capacitor structure is electrically connected to the second doped region.

[0023] In some embodiments, the initial active pillar is generated by an epitaxial process, and the cross-section of the active pillar along the second direction may be quadrilateral or hexagonal.

[0024] Another aspect of this disclosure provides a semiconductor structure, including:

[0025] A substrate; a plurality of character line structures perpendicular to the substrate, the character line structures being spaced apart along a second direction;

[0026] Multiple active columns extend along a first direction. The active columns are spaced apart in a second direction and a third direction. The third direction is perpendicular to the first direction and the second direction. The word line structure is located on the side close to the active columns.

[0027] Multiple bit line structures are provided, the bit line structures extending along the second direction and spaced apart along the third direction, and the bit line structures are electrically connected to one end of the active post.

[0028] Multiple capacitor structures are provided, which extend along the first direction and are spaced apart along the second and third directions, and are electrically connected to the other end of the active post.

[0029] In some embodiments, a plurality of active posts spaced apart along the second direction are all electrically connected to the same bit line structure, and each active post is electrically connected to a capacitor structure; the active posts electrically connected to the same bit line structure, the capacitor structure electrically connected to the active posts, and the bit line structure are all located in the same layer.

[0030] In some embodiments, the system further includes: a first doped region located at one end of the active pillar and electrically connected to the bit line structure; and a second doped region located at the other end of the active pillar and electrically connected to the capacitor structure.

[0031] In some embodiments, it further includes: a channel region disposed near the word line structure, the channel region being located on the active pillar between the first doped region and the second doped region and near the word line structure.

[0032] In some embodiments, the cross-section of the active column along the second direction may be quadrilateral or hexagonal.

[0033] The technical solution provided in this disclosure provides a stacked structure, in which a first opening and a second opening are formed. An initial active pillar is formed in the first opening, and the initial active pillar is etched through the second opening to form active pillars that are evenly spaced along the second and third directions. This simplifies the formation process of the active pillars compared to the prior art. Furthermore, this method allows for the subsequent formation of source / drain regions, bit line structures, and word line structures using self-alignment, further simplifying the process. This process simplification improves the yield of the semiconductor structure and enhances the device performance. Attached Figure Description

[0034] One or more embodiments are illustrated by way of example with corresponding pictures in the accompanying drawings. These illustrations do not constitute a limitation on the embodiments. Unless otherwise stated, the pictures in the accompanying drawings do not constitute a limitation on scale. In order to more clearly illustrate the technical solutions in the embodiments of this disclosure or the conventional technology, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0035] Figure 1 is a flowchart of a semiconductor structure fabrication method provided in an embodiment of this disclosure;

[0036] Figures 2 to 14 are top views of the process flow diagram of a semiconductor structure provided in an embodiment of this disclosure.

[0037] Figures 2A, 3A, 4A, 8A, 11A, 12A, 13A, and 14A are schematic diagrams of cross-sectional structures taken along the A-A' direction in Figures 2, 3, 4, 8, 11, 12, 13, and 14, respectively.

[0038] Figures 2B, 3B, 4B, 5B, 6B, 7B, 8B, 9B, 10B, 11B, 12B, 13B, and 14B are schematic diagrams of cross-sectional structures taken along the B-B' direction in Figures 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, and 14, respectively.

[0039] Figures 5A, 6A, 7A, 8C, 9A, and 10A are schematic diagrams of cross-sectional structures taken along the C-C' direction in Figures 5, 6, 7, 8, 9, and 10, respectively.

[0040] Figures 15 to 24 are top views of the process flow diagrams of a semiconductor structure provided in another embodiment of this disclosure.

[0041] Figures 18A, 21A, 22A, 23A, and 24A are schematic diagrams of cross-sectional structures taken along the A-A' direction in Figures 18, 21, 22, 23, and 24, respectively.

[0042] Figures 15B, 16B, 17B, 18B, 19B, 20B, 21B, 22B, 23B, and 24B are schematic diagrams of cross-sectional structures taken along the B-B' direction of Figures 15, 16, 17, 18, 19, 20, 21, 22, 23, and 24, respectively.

[0043] Figures 15A, 16A, 17A, 18C, 19A, and 20A are schematic diagrams of cross-sectional structures taken along the C-C' direction of Figures 15, 16, 17, 18, 19, and 20, respectively.

[0044] Figure 25 is a three-dimensional schematic diagram of a semiconductor structure provided in an embodiment of the present disclosure; wherein Figure 25a is a three-dimensional schematic diagram of the overall structure, and Figure 25b is a disassembly schematic diagram of Figure 25a. Detailed Implementation

[0045] The technical solutions of this disclosure will be further described in detail below with reference to the accompanying drawings and embodiments. Although exemplary embodiments of this disclosure are shown in the drawings, it should be understood that this disclosure can be implemented in various forms and should not be limited to the embodiments described herein. Rather, these embodiments are provided to enable a more thorough understanding of this disclosure and to fully convey the scope of this disclosure to those skilled in the art.

[0046] The present disclosure is described in more detail below by way of example with reference to the accompanying drawings. The advantages and features of the present disclosure will become clearer from the following description and claims. It should be noted that the drawings are in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of the present disclosure.

[0047] It is understood that the meanings of “on”, “above” and “above” in this disclosure should be interpreted in the broadest sense, such that “on” means not only that it is “on” something without any intervening feature or layer (i.e., directly on something), but also that it is “on” something with an intervening feature or layer.

[0048] In the embodiments of this disclosure, the terms "first," "second," "third," etc., are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence.

[0049] In embodiments of this disclosure, the term "layer" refers to a portion of material comprising a region having thickness. A layer may extend over the entirety of a lower or upper structure, or may have a range smaller than that of the lower or upper structure. Furthermore, a layer may be a region of a homogeneous or heterogeneous continuous structure with a thickness less than the thickness of the continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure, or a layer may be located between any horizontal faces at the top and bottom surfaces of the continuous structure. A layer may extend horizontally, vertically, and / or along an inclined surface. A layer may include multiple sublayers.

[0050] It should be noted that the technical solutions described in the embodiments of this disclosure can be combined arbitrarily without conflict.

[0051] Figure 1 is a flowchart of a semiconductor structure fabrication method provided in an embodiment of this disclosure; Figures 2 to 14 are top views of the process flow diagrams of a semiconductor structure provided in an embodiment of this disclosure; Figures 2A, 3A, 4A, 8A, 11A, 12A, 13A, and 14A are schematic cross-sectional views taken along the A-A' direction in Figures 2, 3, 4, 8, 11, 12, 13, and 14, respectively; Figures 2B, 3B, 4B, 5B, and 6B... Figures 7B, 8B, 9B, 10B, 11B, 12B, 13B, and 14B are schematic diagrams of cross-sectional structures taken along the B-B' direction of Figures 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, and 14, respectively; Figures 5A, 6A, 7A, 8C, 9A, and 10A are schematic diagrams of cross-sectional structures taken along the C-C' direction of Figures 5, 6, 7, 8, 9, and 10, respectively.

[0052] The preparation method includes at least the following steps: S10 providing a substrate; S20 forming a stacked structure on the substrate, the stacked structure being formed by stacking a first dielectric layer and a second dielectric layer in a third direction, the third direction being perpendicular to the substrate surface; S30 forming at least one first opening, the first opening extending from the top of the stacked structure to the top of the substrate along the third direction, a plurality of first openings being spaced apart along a second direction, the second direction being parallel to the substrate surface and perpendicular to the third direction; S40 forming initial active pillars, the initial active pillars filling the first openings; S50 forming a second opening, the second opening being located between adjacent initial active pillars, the second opening extending along the second direction... The dimension of the first opening is smaller than the distance between adjacent initial active pillars. The second opening extends from the top of the stacked structure to the top of the substrate along the third direction. In S60, a portion of the initial active pillars is removed to form active pillars, which are spaced apart along the second and third directions. In S70, a word line structure is formed, which is disposed on one side of the active pillars and extends along the third direction. In S80, a bit line structure is formed, which is electrically connected to one end of the active pillars and extends along the second direction. In S90, a capacitor structure is formed, which is electrically connected to the other end of the active pillars and extends along the first direction, which is perpendicular to the plane formed by the third and second directions.

[0053] The following description, in conjunction with the accompanying drawings, will provide a more detailed account of an embodiment of this disclosure.

[0054] Please refer to Figures 2, 2A, and 2B. A substrate 10 is provided, and a stacked structure 101 is formed on the substrate 10. The stacked structure 101 is formed by stacking a first dielectric layer 102 and a second dielectric layer 103 in a third direction Z, which is perpendicular to the surface of the substrate 10. The thicknesses of the first dielectric layer 102 and the second dielectric layer 103 in the third direction Z may be equal or unequal. In this embodiment, the thicknesses of the first dielectric layer 102 and the second dielectric layer 103 in the third direction Z are equal.

[0055] The substrate material can be silicon (Si), germanium (Ge), silicon-germanium (GeSi), or silicon carbide (SiC); it can also be silicon-on-insulator (SOI), germanium-on-insulator (GOI); or other materials, such as gallium arsenide or other group III-V compounds. In this embodiment, the substrate material is silicon. The substrate is doped with certain impurity ions as needed; these impurity ions can be N-type or P-type impurity ions. The first dielectric layer 102 and the second dielectric layer 103 have different material compositions, and the second dielectric layer 103 may have etching selectivity with respect to the first material 106. The first dielectric layer 102 may be one or more of the following materials: silicon dioxide (SiO2), phosphosilicate glass, borosilicate glass, borosilicate-phosphosilicate glass, fluorosilicate glass, titanium dioxide (TiO2), hafnium oxide (HfO2), zirconium dioxide (ZrO2), hafnium dioxide (HfO2), tantalum oxide (TaO2), magnesium oxide (MgO), aluminum oxide (Al2O3), etc. The second dielectric layer 103 may be one or more of the following materials: silicon nitride (Si3N4), oxynitride (SiON), silicon carbide nitride (SiCN), silicon oxycarbonate (SiOCN), etc. In one embodiment, the first dielectric layer 102 may include silicon dioxide, and the second dielectric layer 103 may include silicon nitride. The methods for forming the first dielectric layer 102 and the second dielectric layer 103 include, but are not limited to, the following methods: the first dielectric layer 102 and the second dielectric layer 103 can be formed using one of the following processes: atomic layer deposition (ALD), plasma enhanced atomic layer deposition (PEALD), chemical vapor deposition (CVD), and plasma enhanced chemical vapor deposition (PECVD).

[0056] Referring to Figures 3, 3A, and 3B, at least one first opening 201 is formed. The first opening 201 extends from the top of the stacked structure 101 to the top of the substrate 10 along a third direction Z. Multiple first openings 201 are spaced apart along a second direction Y, which is parallel to the surface of the substrate 10 and perpendicular to the third direction Z. The first opening 201 is offset to one side of the stacked structure 101, as shown in Figures 3 and 3A. The first opening 201 can also be offset to the right of the stacked structure 101 in the first direction X. However, the first opening 201 cannot be located at the central axis of the stacked structure 101. Offset to one side allows for more space to be reserved for the subsequent formation of the capacitor structure. The distance of the first opening 201 offset to one side can be set according to process requirements. The first opening 201 can be formed using a dry etching process.

[0057] Next, referring to Figures 4, 4A and 4B, an initial active pillar 301 is formed, which fills the first opening 201. The initial active pillar 301 can be formed by epitaxial growth, specifically by using the silicon substrate 10 as the silicon source for epitaxial growth to form the initial active pillar 301.

[0058] Referring next to Figures 5, 5A, and 5B, a second opening 202 is formed. The second opening 202 is located between adjacent initial active pillars 301. The dimension of the second opening 202 along the second direction Y is smaller than the distance between adjacent initial active pillars 301. One end of the second opening 202 along the first direction X is aligned with the end of the initial active pillar 301 closest to the edge of the stacked structure 101. The other end of the second opening 202 extends along the first direction X to the other edge of the stacked structure 101. That is, as shown in Figure 5, the stacked structure 101 has a left edge and a right edge in the first direction X, and the initial active pillars 301 have a left side and a right side in the first direction X. The leftmost side of the second opening 202 in the first direction X is aligned with the left side of the initial active pillar 301, and the rightmost side of the second opening 202 in the first direction X is aligned with the right edge of the stacked structure 101. Of course, the leftmost and rightmost sides of the second opening 202 in the first direction X can be aligned with the left and right sides of the initial active pillar 301, which will be described in detail in the next embodiment. In this embodiment, one end of the second opening 202 along the first direction X is aligned with the end of the initial active pillar 301 closest to the edge of the stacked structure 101, and the other end of the second opening 202 extends along the first direction X to the other edge of the stacked structure 101.

[0059] There is a first gap M between the second opening 202 and the initial active column 301. The second opening 202 extends from the top of the stacked structure 101 to the top of the substrate 10 along the third direction Z. The second opening 202 is located between two adjacent initial active columns 301 but does not expose the sidewall of the initial active column 301. As shown in Figure 5B, there are stacked structures 101 with a thickness of M on both the left and right sides of the initial active column 301. The stacked structure 101 is composed of a first dielectric layer 102 and a second dielectric layer 103 stacked together. The existence of the first gap M can provide a basis for the subsequent generation of active columns.

[0060] Next, referring to Figures 6, 6A and 6B, the first dielectric layer 102 on the sidewall of the initial active pillar 301 is removed by etching through the second opening 202 to form a notch 401. The notch 401 exposes the sidewall of the initial active pillar 301. The notch 401 is formed on both sides of the initial active pillar 301 and spaced apart along the third direction. The notch 401 allows the second opening 202 to be further enlarged to form a second opening enlarged hole 202'.

[0061] Referring to Figures 7, 7A, and 7B, the initial active pillar 301 is etched through the notch 401 to form an active pillar 302. The active pillar 302 forms a gap 402 along the third direction Z. The sidewalls of the active pillar 302 in the second direction Y are all covered by the second dielectric layer 103. As shown in Figure 5B, there is a second dielectric layer 103 of thickness M on both the left and right sides of the initial active pillar 301. The presence of the second dielectric layer 103 can protect the initial active pillar 301 and prevent damage to the sidewalls during the etching process of the initial active pillar 301 to form the active pillar 302. In addition, the second dielectric layer 103 also provides self-alignment for the etching process of forming the active pillar 302. Due to the different etching selectivity ratio between the second dielectric layer 103 and the initial active pillar 301, the etching solution only etches the initial active pillar 301 and does not etch the second dielectric layer 103, so that the initial active pillar 301 is etched to form the active pillar 302. In some embodiments, a silicon (Si) and silicon germanium (SiGe) stack can be formed first, and then the SiGe can be completely removed to generate an active pillar.

[0062] Referring to Figures 5, 5A, and 5B, and Figures 7, 7A, and 7B, the notch 401, the gap 402, and the second opening 202 together constitute the third opening 203. The cross-section of the active pillar 302 along the second direction can be quadrilateral or hexagonal. As shown in Figure 7B, the cross-section of the active pillar 302 along the second direction is hexagonal. This is mainly because the second dielectric layer 103 blocks the process and the etching selectivity between the second dielectric layer 103 and the initial active pillar 301 is different. During the etching process, the initial active pillar 301 between the two second dielectric layers 103 is preferentially etched. As the etching progresses, the etching rate will slow down accordingly, so that the initial active pillar 301 forms a certain slope and eventually forms a hexagon as shown in Figure 7B. Of course, if the apex corners of the hexagons away from the two ends of the second dielectric layer 103 are further etched, they can also be removed to further form quadrilaterals. Preferably, the cross-section of the active pillar 302 along the second direction is hexagonal because in the subsequent process of forming bit line structures and capacitor structures at both ends of the active pillar, the hexagon can provide more process space to increase the contact area and further reduce the contact resistance. Additionally, it should be noted that the dashed box K11 in the enlarged view of Figure 7 indicates that the gap 402 was formed due to the removal of the initial active column 301 at the top. The active column 302 below can be seen through the gap 402. The active column 302 shown in the dashed box K11 is the active column in the next layer.

[0063] Referring to Figures 8, 8A, 8C, and 8B, a third dielectric layer 501 is formed in the third opening 203, filling the third opening 203. The dashed box K12 indicates the position of the active pillar 302 below the third dielectric layer 501 after the third dielectric layer 501 is formed at the top. As shown in Figure 8A, a second dielectric layer 103 exists on both the left and right sides of the active pillar 302, and a third dielectric layer 501 exists above and below the active pillar 302. A first dielectric layer 102 exists on both the left and right sides of the third dielectric layer 501. The first dielectric layer 102 and the third dielectric layer 501 can be made of the same material or different materials, preferably the same material. If the first dielectric layer 102 and the third dielectric layer 501 are made of different materials, it is necessary to ensure that the etching options for the first dielectric layer 102, the third dielectric layer 501, and the second dielectric layer 103 are relatively large.

[0064] Referring to Figures 9, 9A and 9B, a fourth opening 204 is formed. The fourth opening 204 is adjacent to one side of the active column 302 and exposes part of the sidewall of the active column 302. The fourth opening 204 has a second spacing N between it and the non-adjacent active column 302. The fourth opening 204 extends along the third direction Z to the bottom of the stacked structure 101.

[0065] Referring to Figures 10, 10A, and 10B, a word line structure 601 is formed in the fourth opening 204. The word line structure 601 contacts one sidewall of the active pillar 302, as shown in the figures. In other embodiments, the word line structure 601 may also contact the left sidewall of the active pillar 302. This mainly depends on the position of the fourth opening 204. Setting the word line structure 601 on the left or right side of the active pillar 302 does not affect the performance of the word line structure itself. The layout is mainly based on the performance requirements of the overall structure. It should be noted that before forming the word line structure 601, a gate dielectric layer is also formed in the fourth opening 204, that is, there is a gate dielectric layer between the word line structure 601 and the active pillar 302.

[0066] Next, referring to Figures 11, 11A and 11B, the second dielectric layer 103 at one end of the active post 302 is removed to form a first notch 205; as shown in Figure 11A, the second dielectric layer 103 on the left side of the active post 302 is removed to form a first notch 205.

[0067] Referring to Figures 12, 12A and 12B, one end of the active pillar 302 is doped through the first notch 205 to form a first doped region 701. A bit line structure 801 is formed in the first notch 205, and the bit line structure 801 is electrically connected to the first doped region 701.

[0068] Next, referring to Figures 13, 13A and 13B, the second dielectric layer 103 at the other end of the active post 302 is removed to form the second notch 206; as shown in Figure 13A, the second dielectric layer 103 on the right side of the active post 302 is removed to form the second notch 206.

[0069] Referring next to Figures 14, 14A, and 14B, the other end of the active pillar 302 is doped through the second notch 206 to form a second doped region 702. A capacitor structure 901 is formed in the second notch 206, and the capacitor structure 901 is electrically connected to the second doped region 702. The capacitor structure 901 and the bit line structure 801, which are electrically connected to the same active pillar 302, are both located in the same layer, and the word line structure 601 is located on one side of the active pillar 302.

[0070] This application utilizes a first dielectric layer and a second dielectric layer to form a stacked structure. By creating a first opening in the stacked structure, an initial active pillar is formed in the first opening using a substrate through epitaxy. The initial active pillar is then etched through a second opening to form an active pillar. The second dielectric layer on both sides of the active pillar is then etched away to form a first notch and a second notch, and bit line structures and capacitor structures are formed in the first and second notches, respectively. In addition to reducing process time, lowering process complexity, and improving process accuracy, this application also utilizes self-aligned etching to remove the second dielectric layer to form the first and second notches, and to form bit line structures and word line structures in the first and second notches, thereby improving the yield of the semiconductor structure and enhancing device performance.

[0071] Figures 15 to 24 are top views of the process flow diagrams of a semiconductor structure provided in another embodiment of this disclosure. Figures 18A, 21A, 22A, 23A, and 24A are schematic diagrams of cross-sectional structures taken along the A-A' direction in Figures 18, 21, 22, 23, and 24, respectively; Figures 15B, 16B, 17B, 18B, 19B, 20B, 21B, 22B, 23B, and 24B are schematic diagrams of cross-sectional structures taken along the B-B' direction in Figures 15, 16, 17, 18, 19, 20, 21, 22, 23, and 24, respectively; Figures 15A, 16A, 17A, 18C, 19A, and 20A are schematic diagrams of cross-sectional structures taken along the C-C' direction in Figures 15, 16, 17, 18, 19, and 20, respectively.

[0072] Since some process steps in this embodiment are the same as or corresponding to those in the previous embodiment, the parts that are the same as or corresponding to those in the previous embodiment can be referred to the corresponding descriptions of the foregoing embodiments. The differences between this embodiment and the previous embodiment will be described in more detail below with reference to the accompanying drawings.

[0073] Please refer to Figures 15, 15A, and 15B for details. A second opening 202 is formed, which is located between adjacent initial active pillars 301. The size of the second opening 202 along the second direction Y is smaller than the distance between adjacent initial active pillars 301. Unlike the previous embodiment, in this embodiment, the two ends of the second opening 202 along the first direction X are aligned with the two ends of the initial active pillars 301 along the first direction X. That is, as shown in Figure 15, the initial active pillars 301 have a left side and a right side in the first direction X. The leftmost side of the second opening 202 in the first direction X is aligned with the left side of the initial active pillar 301, and the rightmost side of the second opening 202 in the first direction X is aligned with the right side of the initial active pillar 301.

[0074] There is a first gap M between the second opening 202 and the initial active column 301. The second opening 202 extends from the top of the stacked structure 101 to the top of the substrate 10 along the third direction Z. The second opening 202 is located between two adjacent initial active columns 301 but does not expose the sidewall of the initial active column 301. As shown in Figure 15B, there are stacked structures 101 with a thickness of M on both the left and right sides of the initial active column 301. The stacked structure 101 is composed of a first dielectric layer 102 and a second dielectric layer 103 stacked together. The existence of the first gap M can provide a basis for the subsequent generation of active columns.

[0075] Referring next to Figures 16, 16A and 16B, the first dielectric layer 102 on the sidewall of the initial active pillar 301 is removed by etching through the second opening 202 to form a notch 401. The notch 401 exposes the sidewall of the initial active pillar 301. The notch 401 is formed on both sides of the initial active pillar 301 and is spaced apart along a third direction. The notch 401 allows the second opening 202 to be further enlarged to form a second opening enlarged hole 202'.

[0076] Referring to Figures 17, 17A, and 17B, the initial active pillar 301 is etched through the notch 401 to form the active pillar 302. The active pillar 302 forms a gap 402 along the third direction Z. The sidewalls of the active pillar 302 in the second direction Y are all covered by the second dielectric layer 103. As shown in Figure 15B, there is a second dielectric layer 103 with a thickness of M on both the left and right sides of the initial active pillar 301. The presence of the second dielectric layer 103 can protect the initial active pillar 301 and prevent damage to the sidewalls during the etching process of the initial active pillar 301 to form the active pillar 302. In addition, the second dielectric layer 103 also provides self-alignment for the etching process of forming the active pillar 302. Due to the different etching selectivity ratio between the second dielectric layer 103 and the initial active pillar 301, the etching solution only etches the initial active pillar 301 and does not etch the second dielectric layer 103, so that the initial active pillar 301 is etched to form the active pillar 302. Referring then to Figures 15, 15A and 15B, and then to Figures 17, 17A and 17B, the notch 401, the gap 402 and the second opening 202 together constitute the third opening 203. The cross-section of the active pillar 302 along the second direction can be quadrilateral or hexagonal. As shown in Figure 17B, the cross-section of the active pillar 302 along the second direction is hexagonal. This is mainly because the second dielectric layer 103 blocks the process and the etching selectivity between the second dielectric layer 103 and the initial active pillar 301 is different. During the etching process, the initial active pillar 301 between the two second dielectric layers 103 is preferentially etched. As the etching progresses, the etching rate will slow down accordingly, causing the initial active pillar 301 to form a certain slope and eventually form a hexagon as shown in Figure 17B. Of course, if the etching is further carried out, the apex corners of the hexagons away from the two ends of the second dielectric layer 103 can also be removed to further form a quadrilateral. Preferably, the cross-section of the active pillar 302 along the second direction is hexagonal because in the subsequent process of forming bit line structures and capacitor structures at both ends of the active pillar, the hexagon can provide more process space to increase the contact area and further reduce the contact resistance. Additionally, it should be noted that in the enlarged view of Figure 17, the dashed box K11 indicates that the gap 402 is formed due to the removal of the initial active column 301 at the top. Through the gap 402, the active column 302 below can be seen. The active column 302 shown in the dashed box K11 is the active column in the next layer.

[0077] Referring to Figures 18, 18A, 18C, and 18B, a third dielectric layer 501 is formed in the third opening 203, filling the third opening 203. The dashed box K12 indicates the position of the active pillar 302 below the third dielectric layer 501 after the third dielectric layer 501 is formed at the top. As shown in Figure 18A, a second dielectric layer 103 exists on both the left and right sides of the active pillar 302, and a third dielectric layer 501 exists above and below the active pillar 302. A first dielectric layer 102 exists on both the left and right sides of the third dielectric layer 501. The first dielectric layer 102 and the third dielectric layer 501 can be made of the same material or different materials, preferably the same material. If the first dielectric layer 102 and the third dielectric layer 501 are made of different materials, it is necessary to ensure that the etching options for the first dielectric layer 102, the third dielectric layer 501, and the second dielectric layer 103 are relatively large.

[0078] Referring to Figures 19, 19A and 19B, a fourth opening 204 is formed. The fourth opening 204 is adjacent to one side of the active column 302 and exposes part of the sidewall of the active column 302. The fourth opening 204 has a second spacing N between it and the non-adjacent active column 302. The fourth opening 204 extends along the third direction Z to the bottom of the stacked structure 101.

[0079] Referring to Figures 20, 20A, and 20B, a word line structure 601 is formed in the fourth opening 204. The word line structure 601 contacts one sidewall of the active pillar 302, as shown in the figure. In other embodiments, the word line structure 601 may also contact the left sidewall of the active pillar 302. This mainly depends on the position of the fourth opening 204. Setting the word line structure 601 on the left or right side of the active pillar 302 does not affect the performance of the word line structure itself. The layout is mainly based on the performance requirements of the overall structure. It should be noted that before forming the word line structure 601, a gate dielectric layer is also formed in the fourth opening 204, that is, there is a gate dielectric layer between the word line structure 601 and the active pillar 302.

[0080] Next, referring to Figures 21, 21A and 21B, the second dielectric layer 103 at one end of the active post 302 is removed to form the first notch 205; as shown in Figure 21A, the second dielectric layer 103 on the left side of the active post 302 is removed to form the first notch 205.

[0081] Referring to Figures 22, 22A and 22B, one end of the active pillar 302 is doped through the first notch 205 to form a first doped region 701. A bit line structure 801 is formed in the first notch 205, and the bit line structure 801 is electrically connected to the first doped region 701.

[0082] Next, referring to Figures 23, 23A and 23B, the second dielectric layer 103 at the other end of the active post 302 is removed to form the second notch 206; as shown in Figure 23A, the second dielectric layer 103 on the right side of the active post 302 is removed to form the second notch 206.

[0083] Referring next to Figures 24, 24A, and 24B, the other end of the active pillar 302 is doped through the second notch 206 to form a second doped region 702. A capacitor structure 901 is formed in the second notch 206, and the capacitor structure 901 is electrically connected to the second doped region 702. The capacitor structure 901 and the bit line structure 801, which are electrically connected to the same active pillar 302, are both located in the same layer, and the word line structure 601 is located on one side of the active pillar 302.

[0084] This application utilizes a first dielectric layer and a second dielectric layer to form a stacked structure. A first opening is created in the stacked structure, and an initial active pillar is formed in the first opening via epitaxy using a substrate. The initial active pillar is then etched through a second opening to form an active pillar. The second dielectric layer on both sides of the active pillar is then etched away to form a first notch and a second notch, and bit line structures and capacitor structures are formed in the first and second notches, respectively. This method has at least the following advantages: First, this application utilizes a stacked structure of a first dielectric layer and a second dielectric layer, which can be formed using conventional deposition processes. The process is easy to control and takes less time. Second, this application only requires epitaxial growth of the initial active pillar in the first opening using a silicon substrate, eliminating the need for both Si and SiGe epitaxial growth, thus reducing process time and complexity. Third, this application utilizes a large etching selectivity between the first and second dielectric layers for etching and self-alignment to form capacitor and bit line structures, simplifying the process and making it easier to control, further improving process accuracy. This application utilizes a stacked structure to provide support during the formation of active pillars, eliminating the need for additional support layers to support the remaining materials, thus simplifying the process. In addition to the formation of active pillars, the subsequent formation of bit line structures and capacitor structures also does not require additional processes to provide support, thereby shortening the overall process time. This simplification of the process improves the efficiency and yield of semiconductor device manufacturing.

[0085] Figure 25 is a perspective view of a semiconductor structure provided in an embodiment of the present disclosure. Figure 25a is a perspective view of the overall structure. In order to clearly show the part that is blocked in Figure 25a, Figure 25a is disassembled and shown in Figure 25b. Please refer to Figure 25 for details. The semiconductor structure of this application includes: a substrate 10; a plurality of word line structures 601 perpendicular to the substrate 10, the word line structures 601 being spaced apart along a second direction Y; a plurality of active pillars 302 extending along a first direction X, the active pillars 302 being spaced apart in both the second direction Y and a third direction Z, the third direction Z being perpendicular to the first direction X and the second direction Y; the word line structures 601 being disposed on the side closest to the active pillars 302; a plurality of bit line structures 801 extending along the second direction Y and spaced apart along the third direction Z, the bit line structures 801 being electrically connected to one end of the active pillars 302; and a plurality of capacitor structures 901 extending along the first direction X and spaced apart along both the second direction Y and the third direction Z, the capacitor structures 901 being electrically connected to the other end of the active pillars 302. As shown in Figure 25a, the word line structure is set on one side of the active column 302, and from the front view, the word line structure obscures the active column 302. In order to clearly show the obscured active column 302 in Figure 25a, Figure 25a is now disassembled to form Figure 25b. It should be noted that the word line structure 601 in Figure 25b is far away from the active column only to make it easier to clearly show the obscured part in Figure 25a. In the actual structure, the word line structure 601 is set close to the active column 302, as shown in Figure 25a.

[0086] In some embodiments, specifically referring to Figures 14A and 25, a plurality of active posts 302 spaced apart along the second direction Y are all electrically connected to the same bit line structure 801, and each active post 302 is electrically connected to a capacitor structure 901; the active posts 302 electrically connected to the same bit line structure 801, the capacitor structure 901 electrically connected to the active posts 302, and the bit line structure 801 are all located in the same layer; specifically, as shown in Figure 14A, the same layer means that the capacitor structure 901 and the bit line structure 801 electrically connected to the same active post 302 are all located in the same layer.

[0087] In some embodiments, the semiconductor structure further includes a first doped region 701 and a second doped region 702. The first doped region 701 is located at one end of the active pillar 302 and is electrically connected to the bit line structure 801; the second doped region 702 is located at the other end of the active pillar 302 and is electrically connected to the capacitor structure 901. It should be noted that the first doped region 701 and the second doped region 702 in this embodiment are only schematic, and the lengths of the first doped region 701 and the second doped region 702 can be set according to process requirements.

[0088] In some embodiments, the semiconductor structure further includes a channel region 20 disposed near the word line structure 601. The channel region 20 is located on the active pillar 302 between the first doped region 701 and the second doped region 702 and is close to the word line structure 601. Specifically, the location of the channel region 20 is shown in the dashed box in FIG25a.

[0089] In some embodiments, the cross-section of the active post 302 along the second direction Y can be quadrilateral or hexagonal. Referring to Figure 14B, in this embodiment, the cross-section of the active post 302 along the second direction is preferably hexagonal. The hexagonal shape can provide more process space for the active post 302, the capacitor structure 901, and the bit line structure 801 to increase the contact area and further reduce the contact resistance.

[0090] The semiconductor structure in this application can be a three-dimensional dynamic random access memory (3D DRAM), specifically a 3D DRAM including multiple layers of horizontal memory cells (MHC). The semiconductor structure in this application has a simplified fabrication process, and the performance of the semiconductor device is improved.

[0091] The various semiconductor structures illustrated in this specific embodiment can be used in electronic devices with storage functions. These electronic devices can be terminal devices, such as mobile phones, tablets, and smart bracelets, or personal computers (PCs), servers, workstations, etc. The storage function in these electronic devices can be implemented using the following types of memory: Dynamic Random Access Memory (DRAM), Ferroelectric Random Access Memory (FRAM), Phase Change Memory (PCM), Magnetic Random Access Memory (MRAM), or Resistive Random Access Memory (RRAM).

[0092] Those skilled in the art will understand that the above embodiments are specific examples of implementing this disclosure, and in practical applications, various changes in form and detail may be made without departing from the spirit and scope of this disclosure. Any person skilled in the art can make their own modifications and alterations without departing from the spirit and scope of this disclosure; therefore, the scope of protection of this disclosure should be determined by the scope defined in the claims.

Claims

1. A method for fabricating a semiconductor structure, characterized in that, include: Provide a base (10); A stacked structure (101) is formed on the substrate (10), the stacked structure (101) being formed by stacking a first dielectric layer (102) and a second dielectric layer (103) in a third direction (Z), the third direction (Z) being perpendicular to the surface of the substrate (10); At least one first opening (201) is formed, the first opening (201) extends from the top of the stacked structure (101) to the top of the substrate (10) along the third direction (Z), and a plurality of first openings (201) are spaced apart along a second direction (Y), the second direction (Y) is parallel to the surface of the substrate (10) and perpendicular to the third direction (Z); An initial active column (301) is formed, which fills the first opening (201); A second opening (202) is formed between adjacent initial active pillars (301). The size of the second opening (202) along the second direction (Y) is smaller than the distance between adjacent initial active pillars (301). A first gap (M) exists between the second opening (202) and the initial active pillars (301). The second opening (202) extends from the top of the stacked structure (101) to the top of the substrate (10) along the third direction (Z). A portion of the initial active column (301) is removed to form an active column (302), the active columns (302) being spaced apart along the second direction (Y) and the third direction (Z); A word line structure (601) is formed, the word line structure (601) is disposed on one side of the active column (302) and extends along the third direction (Z); A bit line structure (801) is formed, the bit line structure (801) being electrically connected to one end of the active post (302), and the bit line structure (801) extending along the second direction (Y); A capacitor structure (901) is formed, which is electrically connected to the other end of the active post (302). The capacitor structure (901) extends along a first direction (X), which is perpendicular to the plane formed by the third direction (Z) and the second direction (Y).

2. The method for preparing a semiconductor structure according to claim 1, characterized in that, The two ends of the second opening (202) along the first direction (X) are aligned with the two ends of the initial active column (301) along the first direction (X); Alternatively, one end of the second opening (202) along the first direction (X) is aligned with the end of the initial active column (301) closest to the edge of the stacked structure (101), and the other end of the second opening (202) extends along the first direction (X) to the other edge of the stacked structure (101).

3. The method for preparing a semiconductor structure according to claim 2, characterized in that, Removing a portion of the initial active column (301) to form the active column (302) specifically includes: The second opening (202) exposes the stacked structure (101) surrounding the initial active pillar (301), and the first dielectric layer (102) of the sidewall of the initial active pillar (301) is etched away to form a notch (401) that exposes the sidewall of the initial active pillar (301), and the notch (401) is spaced along the third direction (Z). The initial active post (301) is etched through the notch (401) to form the active post (302), the active post (302) forms a gap (402) along the third direction (Z), and the sidewall of the active post (302) is covered by the second dielectric layer (103); The notch (401), the gap (402), and the second opening (202) together constitute the third opening (203).

4. The method for preparing a semiconductor structure according to claim 3, characterized in that, After the formation of the active column (302) and before the formation of the word line structure (601), the method further includes: A third dielectric layer (501) is formed, wherein the third dielectric layer (501) fills the third opening (203); A fourth opening (204) is formed, the fourth opening (204) being adjacent to one side of the active column (302) and exposing a portion of the sidewall of the active column (302), the fourth opening (204) having a second spacing (N) between itself and the non-adjacent active column (302), the fourth opening (204) extending along the third direction (Z) to the bottom of the stacked structure (101); The word line structure (601) is formed in the fourth opening (204).

5. The method for preparing a semiconductor structure according to claim 4, characterized in that, The formation of the bitline structure (801) specifically includes: Remove the second dielectric layer (103) at one end of the active post (302) to form a first notch (205); One end of the active pillar (302) is doped through the first notch (205) to form a first doped region (701); The bit line structure (801) is formed in the first notch (205) and is electrically connected to the first doped region (701).

6. The method for preparing a semiconductor structure according to claim 5, characterized in that, The formation of the capacitor structure (901) specifically includes: Remove the second dielectric layer (103) at the other end of the active post (302) to form a second notch (206); The other end of the active pillar (302) is doped through the second notch (206) to form a second doped region (702); The capacitor structure (901) is formed in the second notch (206) and is electrically connected to the second doped region (702).

7. The method for preparing a semiconductor structure according to claim 1, characterized in that, The initial active pillar (301) is generated by an epitaxial process, and the cross-section of the active pillar (302) along the second direction (Y) can be quadrilateral or hexagonal.

8. A semiconductor structure, characterized in that, include: Base (10); A plurality of word line structures (601) perpendicular to the base (10), the word line structures (601) being spaced apart along a second direction (Y); Multiple active columns (302) are provided, the active columns (302) extend along a first direction (X), the active columns (302) are spaced apart in a second direction (Y) and a third direction (Z), the third direction (Z) is perpendicular to the first direction (X) and the second direction (Y), and the word line structure (601) is provided on the side close to the active columns (302); Multiple bit line structures (801) are provided, which extend along the second direction (Y) and are spaced apart along the third direction (Z), and are electrically connected to one end of the active post (302). Multiple capacitor structures (901) are provided, which extend along the first direction (X) and are spaced apart along the second direction (Y) and the third direction (Z). The capacitor structures (901) are electrically connected to the other end of the active post (302).

9. The semiconductor structure according to claim 8, characterized in that, The multiple active posts (302) spaced apart along the second direction (Y) are all electrically connected to the same bit line structure (801), and each active post (302) is electrically connected to a capacitor structure (901); the active posts (302) electrically connected to the same bit line structure (801), the capacitor structure (901) electrically connected to the active posts (302), and the bit line structure (801) are all located in the same layer.

10. The semiconductor structure according to claim 8, characterized in that, Also includes: The first doped region (701) is located at one end of the active pillar (302) and is electrically connected to the bit line structure (801); The second doped region (702) is located at the other end of the active pillar (302) and is electrically connected to the capacitor structure (901).

11. The semiconductor structure according to claim 10, characterized in that, Also includes: A channel region is disposed near the word line structure (601), the channel region being located on the active pillar (302) between the first doped region (701) and the second doped region (702) and near the word line structure (601).

12. The semiconductor structure according to claim 8, characterized in that, The cross-section of the active column (302) along the second direction (Y) can be quadrilateral or hexagonal.

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