Multilayer ceramic electronic component

Abstract

Provided is a multilayer ceramic electronic component comprising a pair of spacers connected to an external electrode for which measures have been taken against "acoustic noise", wherein the adhesion between a multilayer ceramic capacitor and the pair of spacers is improved to prevent the pair of spacers from falling out. A multilayer ceramic electronic component 100 according to the present invention comprises: a laminate having a first surface and a second surface facing each other in a direction perpendicular to a mounting surface, a third surface and a fourth surface facing each other in a first direction orthogonal to the direction perpendicular to the mounting surface, a fifth surface and a sixth surface facing each other in a second direction orthogonal to the first direction and the direction perpendicular to the mounting surface; a multilayer ceramic capacitor having a first external electrode disposed on the third surface and the second surface of the laminate, and a second external electrode disposed on the fourth surface and the second surface of the laminate; a first spacer disposed on the first external electrode; a second spacer disposed on the second external electrode; and a third spacer disposed, between the first spacer and the second spacer, on the second surface, and constituted by an insulating material having a composition containing carbon. When a region in which the laminate and the first spacer overlap when viewed in the direction perpendicular to the mounting surface is defined as a first region, a non-filled region in which the insulating material constituting a first insulating material layer does not exist is present in the first region, and the non-filled rate of the first region is 41% or less.

Description

Multilayer ceramic electronic components

[0001] The present invention relates to a multilayer ceramic electronic component.

[0002] In recent years, multilayer ceramic capacitors, which are chip-type electronic components, have come to be widely used in electronic devices. As the performance of electronic devices using such multilayer ceramic capacitors continues to improve, the performance of multilayer ceramic capacitors, such as their miniaturization and increased capacitance, is also rapidly improving.

[0003] A multilayer ceramic capacitor has an inner layer portion in which dielectric layers and internal electrodes are alternately stacked. Dielectric layers are arranged on the top and bottom of the inner layer portion to form a rectangular parallelepiped laminate, which serves as an outer layer portion. External electrodes are provided on both longitudinal end faces of the laminate, forming a multilayer ceramic capacitor. In a multilayer ceramic capacitor, capacitance is generated when the internal electrodes face each other via the dielectric layers. It is known that vibrations occur in the multilayer ceramic capacitor due to the piezoelectric phenomenon, and when these vibrations are transmitted to the substrate, they cause what is known as "noise."

[0004] To suppress the occurrence of "squeak noise," for example, it is effective to separate the multilayer ceramic capacitor from the substrate. For this reason, for example, a multilayer ceramic electronic component is known that includes bumps (spacers) formed on the side of the multilayer ceramic capacitor that is mounted on the substrate so as to cover part of the external electrodes.

[0005] For example, Patent Document 1 describes a multilayer ceramic electronic component having bumps made of a substrate material such as alumina, which has high rigidity and a high Young's modulus. Also, Patent Document 2 describes a multilayer ceramic electronic component in which spacers are formed by applying a spacer-forming paste onto a multilayer ceramic capacitor and then performing a heat treatment.

[0006] U.S. Patent No. 10,542,626 International Publication No. 2018 / 101405

[0007] However, if the adhesive strength between the spacer and the multilayer ceramic capacitor is weak, there is a risk that the multilayer ceramic capacitor and the spacer may separate due to, for example, an impact.

[0008] Therefore, an object of the present invention is to provide a multilayer ceramic electronic component that is provided with a pair of spacers connected to external electrodes that have been designed to reduce acoustic noise, and that can improve the adhesive strength between the pair of spacers and the multilayer ceramic capacitor and prevent the spacers from coming off.

[0009] The multilayer ceramic electronic component according to the present invention comprises a multilayer ceramic capacitor including a laminate having a first surface and a second surface that face each other in a direction perpendicular to the mounting surface, a third surface and a fourth surface that face each other in a first direction orthogonal to the direction perpendicular to the mounting surface, and a fifth surface and a sixth surface that face each other in a second direction orthogonal to the direction perpendicular to the mounting surface and the first direction, first external electrodes arranged on the third surface and the second surface of the laminate, and second external electrodes arranged on the fourth surface and the second surface of the laminate, a first spacer arranged on the first external electrodes, and a second external electrode arranged on the fourth surface and the second surface of the laminate. The semiconductor device is characterized in that it comprises a second spacer arranged on the terminal electrode, and a third spacer arranged on the second surface between the first spacer and the second spacer and composed of an insulating material containing carbon, and has a first insulating material layer between the laminate and the first spacer, the first insulating material layer containing at least the insulating material derived from the third spacer, and when the area where the laminate and the first spacer overlap when viewed in a direction perpendicular to the mounting surface is defined as a first area, the first area has an unfilled area where the insulating material that constitutes the first insulating material layer is not present, and the unfilled rate of the first area is 41% or less.

[0010] A multilayer ceramic electronic component according to the present invention comprises a first spacer arranged on a first external electrode, a second spacer arranged on a second external electrode, and a third spacer arranged on a second surface between the first spacer and the second spacer and made of an insulating material containing carbon. A first insulating material layer containing at least the insulating material derived from the third spacer is provided between the laminate and the first spacer. When a region where the laminate and the first spacer overlap when viewed in a direction perpendicular to the mounting surface is defined as a first region, the first region includes an unfilled region where the insulating material constituting the first insulating material layer is absent. The unfilled ratio of the first region is 41% or less, thereby improving the adhesive strength between at least the first spacer and the multilayer ceramic capacitor and preventing the spacer from coming off.

[0011] According to the present invention, it is possible to provide a multilayer ceramic electronic component that includes a pair of spacers connected to external electrodes that have been designed to reduce acoustic noise, and that can improve the adhesive strength between the pair of spacers and the multilayer ceramic capacitor and prevent the spacers from coming off.

[0012] The above and other objects, features, and advantages of the present invention will become more apparent from the following detailed description of the preferred embodiments of the present invention, which proceeds with reference to the accompanying drawings.

[0013] FIG. 1 is an external perspective view showing a multilayer ceramic electronic component according to an embodiment of the present invention. FIG. 2 is a front view showing a multilayer ceramic electronic component according to an embodiment of the present invention. FIG. 3 is a bottom view of the multilayer ceramic electronic component according to an embodiment of the present invention. FIG. 4 is a front view and a bottom view illustrating a connection portion between a first spacer (second spacer) and a third spacer of the multilayer ceramic electronic component according to an embodiment of the present invention. FIG. 5 is a cross-sectional view taken along line V-V in FIG. 2. FIG. 6 is a cross-sectional view taken along line VI-VI in FIG. 3. FIG. 7 is a view showing a mounted state of the multilayer ceramic electronic component according to an embodiment of the present invention.

[0014] 1. Multilayer Ceramic Electronic Component A multilayer ceramic electronic component 100 according to the present invention will be described with reference to FIGS. 1 to 6. FIG. 1 is an external perspective view showing a multilayer ceramic electronic component according to an embodiment of the present invention. FIG. 2 is a front view showing a multilayer ceramic electronic component according to an embodiment of the present invention. FIG. 3 is a bottom view of the multilayer ceramic electronic component according to an embodiment of the present invention. FIG. 4 is a front view and a bottom view illustrating a connection portion between a first spacer (second spacer) and a third spacer of the multilayer ceramic electronic component according to an embodiment of the present invention. FIG. 5 is a cross-sectional view taken along line V-V in FIG. 2. FIG. 6 is a cross-sectional view taken along line VI-VI in FIG. 3. FIG. 7 is a view showing a mounted state of the multilayer ceramic electronic component according to an embodiment of the present invention.

[0015] A multilayer ceramic electronic component 100 according to the present invention comprises a multilayer ceramic capacitor 10 having a laminate 12 and two external electrodes 30 a, 30 b, a first spacer 52 connected to one of the external electrodes 30 a, a second spacer 54 connected to the other external electrode 30 b, and a third spacer 56 disposed between the first spacer 52 and the second spacer 54.

[0016] (Laminate) The laminate 12 has a plurality of dielectric layers 14 stacked together and a plurality of internal electrodes 16 stacked on the dielectric layers 14. The laminate 12 has a first surface 12a and a second surface 12b facing a direction x perpendicular to the mounting surface, a third surface 12c and a fourth surface 12d perpendicular to the direction x perpendicular to the mounting surface and facing a first direction y, and a fifth surface 12e and a sixth surface 12f perpendicular to the direction x perpendicular to the mounting surface and the first direction y and facing a second direction z. In this embodiment, the first surface 12a side of the laminate 12 is the non-mounting surface side, and the second surface 12b side of the laminate 12 is the mounting surface side. In this case, the direction x perpendicular to the mounting surface is the height direction of the laminate 12. Note that the second direction z, which is the direction connecting the fifth surface 12e and the sixth surface 12f of the laminate 12, may also be the height direction.

[0017] The laminate 12 has a hexahedral shape. Furthermore, it is preferable that the corners and ridges of the laminate 12 are rounded. The corners refer to the portions where three adjacent faces of the laminate 12 intersect, and the ridges refer to the portions where two adjacent faces of the laminate 12 intersect. Furthermore, unevenness may be formed on some or all of the first face 12a and the second face 12b, the third face 12c and the fourth face 12d, and the fifth face 12e and the sixth face 12f.

[0018] The laminate 12 has an inner layer portion 18 in which a plurality of inner electrodes 16 face each other. In other words, in the inner layer portion 18, the first inner electrode 16a and the second inner electrode 16b face each other.

[0019] The laminate 12 is located on the first surface 12a side and has a first outer layer portion 20a formed from a plurality of dielectric layers 14 located between the first surface 12a and the outermost surface of the inner layer portion 18 on the first surface 12a side and an extension of that outermost surface.

[0020] Similarly, the laminate 12 has a second outer layer portion 20b located on the second surface 12b side and formed from a plurality of dielectric layers 14 located between the second surface 12b and the outermost surface of the inner layer portion 18 on the second surface 12b side and an extension of that outermost surface.

[0021] (Dielectric Layer) The ceramic material constituting the dielectric layer 14 may be, for example, a dielectric ceramic composed of a main component such as BaTiO3, CaTiO3, SrTiO3, or CaZrO3. Alternatively, a material containing these main components and added with a secondary component such as a Mn compound, an Fe compound, a Cr compound, a Co compound, or a Ni compound may be used.

[0022] The thickness of the dielectric layer 14 is preferably 0.5 μm or more and 10 μm or less. The number of the dielectric layers 14, including the first outer layer portion 20 a and the second outer layer portion 20 b, is preferably 10 or more and 700 or less.

[0023] (Internal Electrode) The internal electrode 16 includes a plurality of first internal electrodes 16a and a plurality of second internal electrodes 16b.

[0024] The first internal electrodes 16a are disposed on the plurality of dielectric layers 14 and are exposed on the third surface 12c.

[0025] The second internal electrodes 16b are disposed on the plurality of dielectric layers 14 and are exposed on the fourth surface 12d.

[0026] The first internal electrode 16a includes a first opposing electrode portion 26a that faces the second internal electrode 16b, and a first extraction electrode portion 28a that is extracted from the first opposing electrode portion 26a to the third surface 12c of the laminate 12. An end of the first extraction electrode portion 28a of the first internal electrode 16a is extracted to the surface of the third surface 12c of the laminate 12, forming an exposed portion.

[0027] The second internal electrode 16b includes a second opposing electrode portion 26b that faces the first internal electrode 16a, and a second extraction electrode portion 28b that is extracted from the second opposing electrode portion 26b to the fourth surface 12d of the laminate 12. The second extraction electrode portion 28b of the second internal electrode 16b has an end that is extracted to the surface of the fourth surface 12d of the laminate 12, forming an exposed portion.

[0028] The shapes of the first opposing electrode portion 26a of the first internal electrode 16a and the second opposing electrode portion 26b of the second internal electrode 16b are not particularly limited, but are preferably rectangular, although the corners may be rounded or angled (tapered).

[0029] The shapes of the first lead electrode portion 28a of the first internal electrode 16a and the second lead electrode portion 28b of the second internal electrode 16b are not particularly limited, but are preferably rectangular, although the corners may be rounded or angled (tapered).

[0030] The width of the first opposing electrode portion 26a of the first internal electrode 16a and the second opposing electrode portion 26b of the second internal electrode 16b may be the same as the width of the first extraction electrode portion 28a of the first internal electrode 16a and the second extraction electrode portion 28b of the second internal electrode 16b, or one of them may be formed to have a narrower width.

[0031] In this embodiment, the opposing electrode portions 26 of the internal electrodes 16 face each other via the dielectric layer 14, thereby forming capacitance and exhibiting the characteristics of a capacitor.

[0032] The first internal electrode 16a and the second internal electrode 16b can be made of an appropriate conductive material, for example, a metal such as Ni, Cu, Ag, Pd, or Au, or an alloy containing at least one of these metals, such as an Ag-Pd alloy.

[0033] Furthermore, by including an Sn layer at the interface between the first internal electrode 16a and the second internal electrode 16b and the dielectric layer 14, it is possible to alleviate electric field concentration at the interface between the internal electrode 16 and the dielectric layer 14, leading to improved high-temperature load reliability. In this case, even if the Sn layer is included only at the interface between the dielectric layer 14 and either the first internal electrode 16a or the second internal electrode 16b, it can be sufficiently effective.

[0034] The thickness of each of the first internal electrode 16a and the second internal electrode 16b is preferably, for example, 0.2 μm or more and 2.0 μm or less. The number of internal electrodes 16 is preferably 10 or more and 700 or less.

[0035] (External Electrode) The external electrode 30 includes a first external electrode 30a and a second external electrode 30b.

[0036] The first external electrode 30a is connected to the first internal electrode 16a and is disposed on the third surface 12c. It may also be disposed on part of the first surface 12a, part of the second surface 12b, part of the fifth surface 12e, and part of the sixth surface 12f. In this embodiment, the first external electrode 30a extends from the third surface 12c to part of the first surface 12a, part of the second surface 12b, part of the fifth surface 12e, and part of the sixth surface 12f.

[0037] The second external electrode 30b is connected to the second internal electrode 16b and is disposed on the fourth surface 12d. It may also be disposed on a part of the first surface 12a, a part of the second surface 12b, a part of the fifth surface 12e, and a part of the sixth surface 12f. In this embodiment, the second external electrode 30b extends from the fourth surface 12d to a part of the first surface 12a, a part of the second surface 12b, a part of the fifth surface 12e, and a part of the sixth surface 12f.

[0038] The first external electrode 30 a and the second external electrode 30 b have an underlying electrode layer 32 disposed on the surface of the laminate 12 and a plating layer 34 disposed so as to cover the underlying electrode layer 32 .

[0039] (Base Electrode Layer) The base electrode layer 32 is disposed on the third surface 12c and the fourth surface 12d. Furthermore, on the first external electrode 30a side and the second external electrode 30b side, the base electrode layer 32 may also be disposed on parts of the first surface 12a and the second surface 12b, parts of the fifth surface 12e, and parts of the sixth surface 12f. In this embodiment, on the first external electrode 30a side and the second external electrode 30b side, the base electrode layer 32 is formed so as to extend from the third surface 12c and the fourth surface 12d to parts of the first surface 12a and the second surface 12b, parts of the fifth surface 12e, and parts of the sixth surface 12f.

[0040] The base electrode layer 32 includes a first base electrode layer 32a and a second base electrode layer 32b.

[0041] The base electrode layer 32 includes at least one selected from a baked layer, a conductive resin layer, a thin film layer, and the like.

[0042] (In the case of a baking layer) The baking layer contains a glass component and a metal. The glass component of the baking layer contains, for example, at least one selected from B, Si, Ba, Mg, Al, and Li. The metal of the baking layer contains, for example, at least one selected from Cu, Ni, Ag, Pd, an Ag—Pd alloy, Au, etc.

[0043] The baked layer may be a multi-layer. The baked layer is formed by applying and baking a conductive paste containing glass and metal to the laminate 12. The baked layer may be formed by simultaneously firing a laminated chip having the internal electrodes 16 and the dielectric layer 14 with the conductive paste applied to the laminated chip, or by firing a laminated chip having the internal electrodes 16 and the dielectric layer 14 to obtain the laminate 12, and then applying and baking the conductive paste to the laminate 12. When simultaneously firing a laminated chip having the internal electrodes 16 and the dielectric layer 14 with the conductive paste applied to the laminated chip, it is preferable to form the baked layer by adding a dielectric material instead of the glass component and baking it.

[0044] The thickness in the first direction y connecting the third surface 12c and the fourth surface 12d at the center of the height direction connecting the first surface 12a and the second surface 12b of the first baking layer located on the third surface 12c (i.e., the thickness of the base electrode layer at the center of the third surface 12c) is preferably, for example, 3 μm or more and 160 μm or less.

[0045] The thickness in the first direction y connecting the third surface 12c and the fourth surface 12d at the center of the height direction connecting the first surface 12a and the second surface 12b of the second baking layer located on the fourth surface 12d (i.e., the thickness of the base electrode layer at the center of the fourth surface 12d) is preferably, for example, 3 μm or more and 160 μm or less.

[0046] Furthermore, it is preferable that the thickness in the height direction connecting the first surface 12a and the second surface 12b at the center of the first direction y connecting the third surface 12c and the fourth surface 12d of the first baking layer located on a part of the first surface 12a and a part of the second surface 12b is, for example, 3 μm or more and 40 μm or less.

[0047] Furthermore, it is preferable that the thickness in the height direction connecting the first surface 12a and the second surface 12b at the center of the first direction y connecting the third surface 12c and the fourth surface 12d of the second baking layer located on a part of the first surface 12a and a part of the second surface 12b is, for example, 3 μm or more and 40 μm or less.

[0048] (In the case of conductive resin layer) When a conductive resin layer is provided as the base electrode layer 32, the conductive resin layer may be disposed so as to cover the baked layer. Alternatively, the conductive resin layer may be disposed directly on the laminate 12 without providing a baked layer. The conductive resin layer may completely cover the base electrode layer 32, or may cover only a portion of the base electrode layer 32. Alternatively, the conductive resin layer may be formed of multiple layers.

[0049] The conductive resin layer contains, for example, a thermosetting resin and a metal component.

[0050] Specific examples of the thermosetting resin include various known thermosetting resins such as epoxy resin, phenolic resin, urethane resin, silicone resin, polyimide resin, etc. Among these, epoxy resin is one of the most suitable resins because of its excellent heat resistance, moisture resistance, adhesion, etc.

[0051] The conductive resin layer preferably contains a curing agent together with the thermosetting resin. When an epoxy resin is used as the base resin, various known compounds such as phenol-based, amine-based, acid anhydride-based, imidazole-based, active ester-based, and amide-imide-based compounds can be used as the curing agent.

[0052] The metal contained in the conductive resin layer can be Ag, Cu, Ni, Sn, Bi, or an alloy containing any of these. Alternatively, a metal powder with an Ag coating on its surface can be used. When using a metal powder with an Ag coating on its surface, it is preferable to use Cu, Ni, Sn, Bi, or an alloy powder thereof as the metal powder. The reason for using Ag conductive metal powder as the metal contained in the conductive resin layer is that Ag has the lowest resistivity among metals, making it suitable as an electrode material, and Ag is a noble metal that does not oxidize and has high weather resistance. Furthermore, it is possible to use an inexpensive base metal while maintaining the above-mentioned properties of Ag. Furthermore, Cu or Ni that has been subjected to an oxidation prevention treatment can also be used as the metal contained in the conductive resin layer. Alternatively, a metal powder with an Sn, Ni, or Cu coating on its surface can also be used as the metal contained in the conductive resin layer. When using a metal powder with an Sn, Ni, or Cu coating on its surface, it is preferable to use Ag, Cu, Ni, Sn, Bi, or an alloy powder thereof as the metal powder.

[0053] The metal contained in the conductive resin layer can be spherical, flat, or the like, but it is preferable to use a mixture of spherical metal powder and flat metal powder. The metal contained in the conductive resin layer is primarily responsible for the electrical conductivity of the conductive resin layer. Specifically, contact between conductive fillers (metal contained in the conductive resin layer) forms an electrical path inside the conductive resin layer.

[0054] Since the conductive resin layer contains a thermosetting resin, it is more flexible than a base electrode layer made of, for example, a plating film or a fired conductive paste, and therefore functions as a buffer layer to prevent cracks in the multilayer ceramic capacitor even when the multilayer ceramic capacitor is subjected to a physical impact or an impact due to a thermal cycle.

[0055] The thickness of the thickest part of the conductive resin layer is preferably, for example, 10 μm or more and 150 μm or less.

[0056] (In the case of a thin film layer) The thin film layer is formed by a thin film forming method such as sputtering or vapor deposition, and is a layer of 1 μm or less in thickness on which metal particles are deposited.

[0057] (Plating Layer) The plating layer 34 includes a first plating layer 34a and a second plating layer 34b. The first plating layer 34a is disposed so as to cover the first base electrode layer 32a. The second plating layer 34b is disposed so as to cover the second base electrode layer 32b.

[0058] The plating layer 34 contains at least one selected from the group consisting of Cu, Ni, Sn, Ag, Pd, an Ag—Pd alloy, and Au.

[0059] The plating layer 34 may be formed of multiple layers. Preferably, it has a two-layer structure of Ni plating and Sn plating. The Ni plating layer can prevent the base electrode layer 32 from being eroded by solder when mounting the multilayer ceramic electronic component 100. The Sn plating layer also improves the wettability of the solder when mounting the multilayer ceramic electronic component 100, facilitating mounting.

[0060] The thickness of each plating layer 34 is preferably 2 μm or more and 15 μm or less.

[0061] The external electrode 30 may be formed using only the plating layer 34 without providing the base electrode layer 32. A structure in which the plating layer 34 is provided without providing the base electrode layer 32 will be described below.

[0062] For each of the first external electrode 30a and the second external electrode 30b, the plating layer 34 may be formed directly on the surface of the laminate 12 without providing the base electrode layer 32. That is, the multilayer ceramic capacitor 10 may have a structure including the plating layer 34 that is directly connected to the first internal electrode 16a and the second internal electrode 16b. In such a case, the plating layer 34 may be formed after a catalyst is disposed on the surface of the laminate 12 as a pretreatment.

[0063] When a plating layer is formed directly on the laminate 12 without providing the base electrode layer 32, the reduction in the thickness of the base electrode layer 32 can be converted into a lower profile, i.e., a thinner body, or into the thickness of the laminate 12, i.e., the thickness of the inner layer portion 18 (effective layer portion), thereby improving the design freedom of thin chips.

[0064] Furthermore, the plating layer 34 preferably includes a lower-layer plating electrode formed on the surface of the laminate 12 and an upper-layer plating electrode formed on the surface of the lower-layer plating electrode.

[0065] The lower layer plating electrode and the upper layer plating electrode each preferably contain at least one metal selected from, for example, Cu, Ni, Sn, Pb, Au, Ag, Pd, Bi, or Zn, or an alloy containing such a metal.

[0066] The lower layer plated electrode is preferably formed using Ni, which has solder barrier properties, and the upper layer plated electrode is preferably formed using Sn or Au, which has good solder wettability.

[0067] Furthermore, for example, when the first internal electrode 16 a and the second internal electrode 16 b are formed using Ni, it is preferable that the lower-layer plated electrode be formed using Cu, which has good bonding properties with Ni. Note that the upper-layer plated electrode may be formed as needed, and the first external electrode 30 a and the second external electrode 30 b may each be composed of only the lower-layer plated electrode.

[0068] The plating layer 34 may have an upper layer plating electrode as the outermost layer, or another plating electrode may be formed on the surface of the upper layer plating electrode.

[0069] The thickness of each plating layer 34, which is disposed without providing a base electrode layer 32, is preferably 1 μm or more and 15 μm or less. The plating layer 34 preferably does not contain glass. The metal content per unit volume of the plating layer 34 is preferably 99% by volume or more.

[0070] The dimension of the multilayer ceramic capacitor 10 in the first direction y is defined as the L dimension. The L dimension is preferably 0.2 mm or more and 10 mm or less. The dimension of the multilayer ceramic capacitor 10 in the second direction z is defined as the W dimension. The W dimension is preferably 0.1 mm or more and 5 mm or less. The dimension of the multilayer ceramic capacitor 10 in the height direction is defined as the T dimension. The T dimension is preferably 0.1 mm or more and 5 mm or less. More preferably, the L dimension is preferably 1.0 mm or more and 2.1 mm or less. The W dimension is preferably 0.5 mm or more and 1.3 mm or less. The T dimension is preferably 0.5 mm or more and 1.3 mm or less.

[0071] (Spacer) The multilayer ceramic electronic component 100 includes a multilayer ceramic capacitor 10 and a spacer 50. The spacer 50 includes a first spacer 52 that covers at least a portion of the first external electrode 30a, a second spacer 54 that covers at least a portion of the second external electrode 30b, and a third spacer 56 that covers a portion of the laminate 12, a portion of the first spacer 52, and a portion of the second spacer 54. In this embodiment, the first spacer 52, the second spacer 54, and the third spacer 56 are described separately from one another, but there are cases in which the first spacer 52, the second spacer 54, and the third spacer 56 are integrated and cannot be distinguished from one another.

[0072] 7 , when the multilayer ceramic electronic component 100 is mounted on a mounting substrate 60, the first spacer 52 and the second spacer 54 are electrically and mechanically connected to the land electrodes 64 a, 64 b via the solder 62. At this time, the solder 62 forms fillets along the first spacer 52 and the first external electrode 30 a, and along the second spacer 54 and the second external electrode 30 b. Note that fillets formed by the solder 62 may be formed only on the first spacer 52 or the second spacer 54. When fillets are formed only on the first spacer 52 and the second spacer 54, the amount of wetting of the solder 62 onto the multilayer ceramic capacitor 10 can be reduced, thereby suppressing acoustic noise.

[0073] (First Spacer and Second Spacer) The first spacer 52 is disposed between the first external electrode 30a and the mounting surface S and is connected to the first external electrode 30a. The second spacer 54 is disposed between the second external electrode 30b and the mounting surface S and is connected to the second external electrode 30b.

[0074] The shapes of the first spacer 52 and the second spacer 54 are not particularly limited. In other words, the shapes of the first spacer 52 and the second spacer 54 may be, for example, substantially hexahedral. In the following description, the shapes of the first spacer 52 and the second spacer 54 will be described as being hexahedral.

[0075] The first spacer 52 has a first surface 52a and a second surface 52b facing in a direction x perpendicular to the mounting surface, a third surface 52c and a fourth surface 52d perpendicular to the direction x perpendicular to the mounting surface and facing in a first direction y, and a fifth surface 52e and a sixth surface 52f perpendicular to the direction x perpendicular to the mounting surface and the first direction y and facing in a second direction z. In this case, the first spacer 52 may have a truncated quadrangular pyramid shape such that the area of ​​the first surface 52a is smaller than the area of ​​the second surface 52b.

[0076] The second surface 52b of the first spacer 52 is positioned on the mounting surface S side. The first surface 52a of the first spacer 52 is connected to the first external electrode 30a. Furthermore, the edge portion of the first spacer 52 that is closest to the center of the multilayer ceramic capacitor 10 in the first direction y is positioned closer to the center than the end portion of the first external electrode 30a that is closest to the center of the multilayer ceramic capacitor 10 in the first direction y. Furthermore, the ridge portion of the first spacer 52 where the first surface 52a and the fourth surface 52d of the first spacer 52 intersect is positioned closer to the center in the first direction y than the end portion of the first external electrode 30a that is closest to the center of the multilayer ceramic capacitor 10 in the first direction y. Therefore, the first spacer 52 has, on the first surface 52a, a portion that contacts the first external electrode 30a and a portion that extends from the portion that contacts the first external electrode 30a toward the center in the first direction y.

[0077] The second spacer 54 has a first surface 54a and a second surface 54b facing in a direction x perpendicular to the mounting surface, a third surface 54c and a fourth surface 54d perpendicular to the direction x perpendicular to the mounting surface and facing in a first direction y, and a fifth surface 54e and a sixth surface 54f perpendicular to the direction x perpendicular to the mounting surface and the first direction y and facing in a second direction z. In this case, the second spacer 54 may have a truncated quadrangular pyramid shape such that the area of ​​the first surface 54a is smaller than the area of ​​the second surface 54b.

[0078] The second surface 54b of the second spacer 54 is located on the mounting surface S side. The first surface 54a of the second spacer 54 is connected to the second external electrode 30b. Furthermore, the edge portion of the second spacer 54 that is closest to the center of the multilayer ceramic capacitor 10 in the first direction y is located closer to the center than the end portion of the second external electrode 30b that is closest to the center of the multilayer ceramic capacitor 10 in the first direction y. Furthermore, the ridge portion of the second spacer 54 where the first surface 54a and the fourth surface 54d intersect is located closer to the center in the first direction y than the end portion of the second external electrode 30b that is closest to the center of the multilayer ceramic capacitor 10 in the first direction y. Therefore, the second spacer 54 has, on the first surface 54a, a portion that contacts the second external electrode 30b and a portion that extends from the portion that contacts the second external electrode 30b toward the center in the first direction y.

[0079] By arranging the first spacer 52 and the second spacer 54 between the multilayer ceramic capacitor 10 and the mounting surface S, the distance between the inner layer portion 18, which is the capacitance forming portion of the multilayer ceramic capacitor 10, and the mounting surface S can be increased, thereby suppressing "squeak".

[0080] At this time, depending on the dimension in the direction x perpendicular to the mounting surface of the multilayer ceramic capacitor 10, the dimension t sFor example, when the dimension L of the multilayer ceramic capacitor 10 in the first direction y is 1.6 mm, the dimension W of the multilayer ceramic capacitor 10 in the second direction z is 0.8 mm, and the dimension T of the multilayer ceramic capacitor 10 in the height direction is 0.8 mm, the dimension t of the first spacer 52 and the second spacer 54 in the direction x perpendicular to the mounting surface is s is preferably about 160 μm. For example, when the dimension L of the multilayer ceramic capacitor 10 in the first direction y is 2.0 mm and the dimension W of the multilayer ceramic capacitor 10 in the second direction z is 1.25 mm, the dimension t of the multilayer ceramic electronic component 100 in the direction x perpendicular to the mounting surface is preferably about 1.60 mm. Furthermore, the first spacer 52 and the second spacer 54 may have portions with irregularities. When the first spacer 52 and the second spacer 54 have portions with irregularities due to their shapes, the dimension t of the first spacer 52 and the second spacer 54 in the direction x perpendicular to the mounting surface is preferably about 1.60 mm. s It is preferable that the minimum thickness of the first spacer 52 is about 50 μm. The various dimensions are defined by the longest dimension in the first direction y, the second direction z, and the direction x perpendicular to the mounting surface. It is preferable that the distance between the first spacer 52 and the second spacer 54 in the first direction y is 0.400 mm or more.

[0081] The first spacer 52 and the second spacer 54 contain metal powder. The metal powder may contain, for example, Sn and one of Cu, Ni, or an alloy of Cu and a metal component (e.g., Ni). In addition, Ag or a resin component (e.g., rosin) may be included, and the Cu and Ni may be coated with Ag. This allows the multilayer ceramic electronic component 100 to be mounted on a substrate while maintaining a desired shape during soldering because it has a melting point that does not melt even when soldered and does not deform due to heat. Furthermore, the present invention is not limited to this, and the spacer may contain other metal components. Because the first spacer 52 and the second spacer 54 contain Sn and one of Cu, Ni, or an alloy of Cu and a metal component (e.g., Ni), metal bonding between the first spacer 52 and the second spacer 54 and the external electrodes 30a, 30b of the multilayer ceramic capacitor 10 is facilitated.

[0082] In addition to the above, the first spacer 52 and the second spacer 54 may contain phenolic resin as a resin component. In this case, the phenolic resin coats the metal powder particles and is scattered so as to fill the gaps between the particles. The inclusion of phenolic resin provides good heat resistance, so the amount of vaporization can be reduced during the heat treatment process when forming the spacers. This reduces voids within the spacers. Furthermore, without being limited to this, epoxy resin or rosin may also be contained in addition to phenolic resin.

[0083] The first spacer 52 and the second spacer 54 may also be configured to contain metal powder in resin. If the resin component is contained in a larger amount than the metal powder, the resin component can buffer vibrations of the multilayer ceramic capacitor 10, thereby reducing vibrations transmitted to the substrate. In this case, the surfaces of the first spacer 52 and the second spacer 54 may be plated.

[0084] In this embodiment, the first spacer 52 and the second spacer 54 contain Cu, Ni, and Sn as metal components, and also contain phenol resin as a resin component.

[0085] The components of the first spacer 52 and the second spacer 54 can be detected, for example, as follows. The multilayer ceramic electronic component 100 is cross-polished perpendicular to the mounting surface S to ½ W of the second direction z to expose a cross-section (LT plane) in the direction x perpendicular to the mounting surface and the first direction y. The components of the first spacer 52 and the second spacer 54 can be detected by qualitative analysis using EDX with an FE-SEM (SU8230, manufactured by Hitachi High-Technologies Corporation) obtained by cross-polishing. The cross-section obtained by cross-polishing can be magnified 50 times with a microscope (BX-51, manufactured by Olympus Corporation) and photographed with a microscope digital camera (DP22, manufactured by Olympus Corporation) to observe the metal types in the first spacer 52 and the second spacer 54, or, if plating is present on the first spacer 52 and the second spacer 54, the difference in the metal type of the plating. Furthermore, without being limited to this, by taking photographs using a microscope (Axio (registered trademark)-Imager-MAT manufactured by ZEISS) at a total magnification of 100 times or more and 500 times or less, it is also possible to observe the difference in the metal type within the first spacer 52 and the second spacer 54, or the difference in the metal type of plating if plating is present on the first spacer 52 and the second spacer 54. In addition to this, cross-section polishing may be performed up to ½W in the second direction z.

[0086] (Third Spacer) The third spacer 56 is connected to a portion of the laminate 12, a portion of the first spacer 52, and a portion of the second spacer 54. More specifically, the third spacer 56 covers the fourth surface 52d of the first spacer 52, which is defined as the first spacer inner surface. The third spacer 56 has a first connection region 52d1 connected to the fourth surface 52d of the first spacer 52 (the first spacer inner surface). The third spacer 56 also covers the fourth surface 54d of the second spacer 54, which is defined as the second spacer inner surface. The third spacer 56 has a second connection region 54d1 connected to the fourth surface 54d of the second spacer 54 (the second spacer inner surface). The third spacer 56 preferably covers 50% or more of the area of ​​the fourth surface 52d of the first spacer 52, and preferably covers 50% or more of the area of ​​the fourth surface 54d of the second spacer 54. In this case, the third spacer 56 preferably continuously covers the surface of the laminate 12. However, this is not limited thereto, and the third spacer 56 may be arranged discontinuously in the longitudinal direction (first direction y) of the multilayer ceramic capacitor 10. This allows the distance between the center of the multilayer ceramic electronic component 100 in the first direction y, where vibration occurs most, and the multilayer ceramic electronic component 100 to be increased, thereby reducing the possibility of contact between the mounting substrate and the multilayer ceramic electronic component 100.

[0087] The third spacer 56 may cover the fifth surface 52e and the sixth surface 52f of the first spacer 52 and the fifth surface 54e and the sixth surface 54f of the second spacer 54. Alternatively, the third spacer 56 may cover the fifth surface 52e and the sixth surface 52f of the first spacer 52 and the fifth surface 54e and the sixth surface 54f of the second spacer 54 continuously to the fifth surface 12e and the sixth surface 12f of the multilayer ceramic capacitor 10. This configuration provides insulation by the third spacer 56, allowing the multilayer ceramic electronic component 100 to be arranged in close proximity. While the location of the multilayer ceramic capacitor 10 covered by the third spacer 56 is not particularly limited, it is preferable that the third spacer 56 not cover the non-mounting surface (first surface 12a) of the multilayer ceramic electronic component 100 in order to distinguish the mounting surface (second surface 12b).

[0088] Furthermore, it is preferable that the color of the multilayer ceramic electronic component 100 be different when viewed from the bottom surface (mounting surface) than when viewed from the top surface (non-mounting surface). The different colors make it easier to select the direction when mounting the component on a substrate, and can reduce the number of times the multilayer ceramic electronic component 100 is mounted on a surface other than the surface on which it should be mounted.

[0089] The third spacer 56 includes, for example, carbon, Co, Al, Cu, N, or Cr. In addition, the third spacer 56 may include an epoxy resin, a hardener, or another organic solvent.

[0090] Furthermore, without being limited thereto, the third spacer 56 may be made of an insulating paste. For example, if the third spacer 56 contains a large amount of carbon, the hue of the third spacer can be made closer to black. Also, if the third spacer 56 contains a large amount of Co, Al, or Cr, the hue of the third spacer 56 can be made closer to blue. In addition, the hue can be changed by using various other materials.

[0091] The content of the various materials for changing the hue is preferably 0.1 wt % to 5.0 wt % based on the solid content of the third spacer 56, i.e., the amount of solid content excluding solvent (epoxy resin, phenolic resin), additives (coupling agent, catalyst), and inorganic materials (silica, alumina)). If the weight ratio is too small, the hue change may be insufficient, and the image may not be correctly recognized during image processing. Furthermore, if the weight ratio is too large, the third spacer 56 may cause electrical conduction between the first external electrode 30a and the second external electrode 30b, or between the first spacer 52 and the second spacer 54. Depending on the distribution of the various materials, there may be areas with partially different hues. However, even in such cases, directional selection is possible as long as the hues are sufficiently different. It is preferable that the hue be different over at least half of the area of ​​the region between the first spacer 52 and the second spacer 54 on the mounting surface.

[0092] To distinguish between the portion where the third spacer 56 is present and the other portions, a method for measuring the hue of the mounting surface side and the non-mounting surface side of the multilayer ceramic electronic component 100 will be described. The first surface 12a, which is the non-mounting surface side, and the second surface 12b, which is the mounting surface side, of the multilayer ceramic electronic component 100 are measured using a digital microscope (Keyence Corporation, VHX-6000) (RGB measurement). The measurement conditions are brightness set to auto "100," gain set to auto "100," and ring removal set to "medium" for reflection removal. The mounting surface side is measured on 1 / 2W of the multilayer ceramic electronic component 100, 1 / 2L of the multilayer ceramic electronic component 100, the contact point between the first spacer 52 and the laminate 12, and the contact point between the second spacer 54 and the laminate 12. Furthermore, on the non-mounting surface, measurements are made on ½ W of the multilayer ceramic electronic component 100, ½ L of the multilayer ceramic electronic component 100, near the contact points between the first external electrode 30 a and the laminate 12, and near the contact points between the second external electrode 30 b and the laminate 12. When the mounting surface and non-mounting surface of the multilayer ceramic electronic component 100 are measured, a difference in hue is defined as being 10 or more in any of the R, G, and B values. In this case, a difference in hue at even one of the measurement points is considered to be a difference in hue.

[0093] (Insulating Material Layer) A first insulating material layer 70 made of an insulating material containing carbon is disposed between the laminate 12 and the first spacer 52. The first insulating material layer 70 contains the insulating material derived from the third spacer 56 and the insulating material derived from the first spacer 52. Note that the first insulating material layer 70 is mostly made of the insulating material derived from the third spacer 56.

[0094] As shown in FIG. 4 , when the overlapping region between the laminate 12 and the first spacer 52 is defined as a first region 80 as viewed in the direction x perpendicular to the mounting surface, the first region 80 includes a non-filled region 74 where the insulating material constituting the first insulating material layer 70 is not present. In other words, the non-filled region 74 is a region that does not contain carbon. The ratio of the area occupied by the non-filled region 74 to the area of ​​the first region 80 (hereinafter referred to as the non-filling ratio) is preferably 41% or less. The non-filling ratio is more preferably 29% or less. This improves the bonding strength between the multilayer ceramic capacitor 10 and the first spacer 52. Therefore, the multilayer ceramic capacitor 10 and the first spacer 52 can be prevented from coming off.

[0095] A second insulating layer 72 containing carbon is disposed between the laminate 12 and the second spacer 54. The second insulating layer 72 contains the insulating material derived from the third spacer 56 and the insulating material derived from the second spacer 54. The second insulating layer 72 is mostly composed of the insulating material derived from the third spacer 56.

[0096] As shown in FIG. 4 , when the overlapping region between the laminate 12 and the second spacer 54 is defined as a second region 82 in the direction x perpendicular to the mounting surface, the second region 82 includes a non-filled region 74 where the second insulating material layer 72 is not present. In other words, the non-filled region 74 is a region that does not contain carbon. The ratio of the area occupied by the non-filled region 74 to the area of ​​the second region 82 (hereinafter referred to as the non-filling ratio) is preferably 41% or less. The non-filling ratio is more preferably 29% or less. This improves the bonding strength between the multilayer ceramic capacitor 10 and the second spacer 54. Therefore, the multilayer ceramic capacitor 10 and the second spacer 54 can be prevented from coming off.

[0097] The non-filling ratios of the first region 80 and the second region 82 are defined as follows. After the first spacer 52 and the second spacer 54 are dissolved from the multilayer ceramic electronic component 100, an image is taken in low vacuum mode with a JEOL Ltd. field emission-scanning electron microscope (FE-SEM), and elemental analysis is performed using EDX. The imaging conditions for the FE-SEM low vacuum mode are an acceleration voltage of 5.00 kV and a measurement magnification of 80 to 120 times. In this embodiment, a mapping image obtained when the detected element is C (carbon) is subjected to binarization analysis using image processing software to identify the non-filling region 74, which is a region that does not contain carbon, and the regions of each insulating material layer that contain carbon. Then, the non-filling rate, which is the ratio of the sum of the areas of the non-filled areas 74 to the area of ​​the first area 80, is calculated, and the non-filling rate, which is the ratio of the sum of the areas of the non-filled areas 74 to the area of ​​the second area 82, is calculated.

[0098] 4, the unfilled ratio on the first spacer 52 side can be calculated as the ratio of the sum of the areas a1 of the unfilled regions 74 to the area A1 of the first regions 80. Similarly, the unfilled ratio on the second spacer 54 side can be calculated as the ratio of the sum of the areas a2 of the unfilled regions 74 to the area A2 of the second regions 82.

[0099] The combined region of the first insulating material layer 70 located on the first region 80 side and the non-filled regions 74 located inside the first insulating material layer 70 is divided into three equal parts in the second direction z, and the regions are defined as a first outer region 70a, a central region 70b, and a second outer region 70c from the fifth surface side. The ratio of the sum of the areas a1 of the non-filled regions 74 located inside the first outer region 70a to the area of ​​the first outer region 70a is defined as the porosity of the first outer region 70a, the ratio of the sum of the areas a1 of the non-filled regions 74 located inside the central region 70b to the area of ​​the central region 70b is defined as the porosity of the central region 70b, and the ratio of the sum of the areas a1 of the non-filled regions 74 located inside the second outer region 70c to the area of ​​the second outer region 70c is defined as the porosity of the second outer region 70c. In this case, it is preferable that the porosity of the central region 70b is greater than the porosity of the first outer region 70a. Furthermore, the porosity of the central region 70b may be greater than the porosity of the second outer region 70c. This has the effect of increasing the porosity of the center portion in the second direction z of the central region 70b, i.e., the region where the first insulating material layer 70 located on the first region 80 side is present, and decreasing the porosity on both end sides, thereby improving the adhesive strength. The first outer region 70a, central region 70b, and second outer region 70c are identified as regions divided by lines l1 and l2, which divide the dimension w1 of the longest portion in the second direction z of the region where the first insulating material layer 70 located on the first region 80 side is present into thirds.

[0100] The combined region of the second insulating material layer 72 located on the second region 82 side and the non-filled regions 74 located inside the second insulating material layer 72 is divided into three equal parts in the second direction z, and the regions are defined as a first outer region 72a, a central region 72b, and a second outer region 72c from the fifth surface side. The ratio of the sum of the areas a2 of the non-filled regions 74 located inside the first outer region 72a to the area of ​​the first outer region 72a is defined as the porosity of the first outer region 72a, the ratio of the sum of the areas a2 of the non-filled regions 74 located inside the central region 72b to the area of ​​the central region 72b is defined as the porosity of the central region 72b, and the ratio of the sum of the areas a2 of the non-filled regions 74 located inside the second outer region 72c to the area of ​​the second outer region 72c is defined as the porosity of the second outer region 72c. In this case, it is preferable that the porosity of the central region 72b is greater than the porosity of the first outer region 72a. Furthermore, the porosity of the central region 72b may be greater than the porosity of the second outer region 72c. This has the effect of increasing the porosity of the center portion in the second direction z of the central region 72b, i.e., the region where the second insulating material layer 72 located on the second region 82 side is present, and decreasing the porosity on both end sides, thereby improving the adhesive strength. The first outer region 72a, central region 72b, and second outer region 72c are identified as regions divided by lines l3 and l4, which divide into thirds the dimension w2 of the longest portion in the second direction z of the region where the second insulating material layer 72 located on the second region 82 side is present.

[0101] The length w1 of the longest portion in the second direction z of the first insulating material layer 70 is longer than the length w3 of the longest portion in the second direction z of the third region 84. Similarly, the length w2 of the longest portion in the second direction z of the second insulating material layer 72 is longer than the length w3 of the longest portion in the second direction z of the third region 84. This makes it possible to reduce the area of ​​the entire surface of the laminate 12 covered by the third region 84, making it easier to recognize the difference in brightness between the exposed and unexposed portions of the laminate 12 and facilitating directional selection by camera recognition during mounting.

[0102] The sum of the areas a1 of the non-filled regions 74 located in the first outer region 70a and the second outer region 70c may be smaller than the sum of the areas a1 of the non-filled regions 74 located in the central region 70b. This reduces the area of ​​the non-filled regions 74, increasing the proportion of the insulating material component and allowing the vicinity of the ridge line portion, where the area where the first spacer 52 and the first external electrode 30a are in contact with each other, to be more reinforced with the insulating material, thereby enabling the insulating material to be effectively formed with a small amount of insulating material.

[0103] Similarly, the sum of the areas a2 of the non-filled regions 74 located in the first outer region 72a and the second outer region 72c may be smaller than the sum of the areas a2 of the non-filled regions 74 located in the central region 72b. This reduces the area of ​​the non-filled regions 74, increasing the proportion of the insulating material component and allowing the vicinity of the ridge line, where the area where the second spacer 54 and the second external electrode 30b are in contact, to be more reinforced with the insulating material, thereby enabling the insulating material to be effectively formed with a small amount of material.

[0104] The shortest length m between the third surface 12c of the laminate 12 and the edge of the first outer region 70a on the third surface 12c side 11 is the shortest length m between the third surface 12c of the laminate 12 and the edge of the central region 70b on the third surface 12c side. 12 It is preferable that the length of the third spacer 56 is shorter than the length of the first insulating layer 70. The shape of the end of the first insulating layer 70 located on the first region 80 side, on the third surface 12c side of the laminate 12, is curved toward the third surface 12c. The areas of the first outer region 70a and the second outer region 70c are preferably larger than those of the central region 70b. This allows the third spacer 56 to further reinforce the vicinity of the ridge line where the contact area between the first spacer 52 and the first external electrode 30a is small, and therefore the third spacer 56 can be effectively formed with a small amount of spacer.

[0105] The shortest length m between the fourth surface 12d of the laminate 12 and the edge of the second outer region 72c on the fourth surface 12d side 21 is the shortest length m between the third surface 12c of the laminate 12 and the edge of the central region 72b on the fourth surface 12d side. 22It is preferable that the length of the third spacer 56 is shorter than the length of the second insulating layer 72. The shape of the end of the second insulating layer 72 located on the second region 82 side, on the fourth surface 12d side of the laminate 12, is curved toward the fourth surface 12d. The areas of the first outer region 72a and the second outer region 72c are preferably larger than those of the central region 72b. This allows the third spacer 56 to further reinforce the vicinity of the ridge line where the area of ​​contact between the second spacer 54 and the second external electrode 30b is small, and therefore the third spacer 56 can be effectively formed with a small amount of spacer.

[0106] The third spacer 56 also has a third region 84 between the first region 80 and the second region 82. The thickness t of the third region 84 in the direction x perpendicular to the mounting surface is preferably greater than the thickness t of the third region 84 in the direction x perpendicular to the mounting surface of the first spacer, on which the first connection region 52d is disposed. Similarly, the thickness t of the third region 84 in the direction x perpendicular to the mounting surface of the third region 84 is preferably greater than the thickness t of the third region 84 in the direction x perpendicular to the mounting surface of the second spacer, on which the second connection region 54d is disposed. This improves self-alignment after connection with solder.

[0107] The multilayer ceramic electronic component 100 shown in FIG. 1 includes a first spacer 52 disposed on the first external electrode 30 a, a second spacer 54 disposed on the second external electrode 30 b, and a third spacer 56 disposed on the second surface 12 b between the first spacer 52 and the second spacer 54 and made of an insulating material containing carbon. Between the laminate 12 and the first spacer 52, a first insulating material layer 70 containing at least the insulating material derived from the third spacer 56 is provided. When the region where the first spacer 52 and the first spacer 52 overlap when viewed in the direction x perpendicular to the mounting surface is defined as the first region 80, the first region 80 has an unfilled region where the insulating material that constitutes the first insulating material layer 70 is not present, and the unfilled rate of the first region 80 is 41% or less. Therefore, at least the adhesive strength between the first spacer 52 and the multilayer ceramic capacitor 10 can be improved, and therefore, the first spacer 52 can be prevented from coming off the multilayer ceramic capacitor 10.

[0108] 2. Method for Manufacturing Multilayer Ceramic Electronic Components Next, a method for manufacturing multilayer ceramic electronic components will be described.

[0109] First, a conductive paste for the dielectric sheet and the internal electrodes is prepared. The conductive paste for the dielectric sheet and the internal electrodes contains a binder and a solvent. Known binders and solvents can be used.

[0110] Next, a dielectric sheet on which no internal electrode pattern is printed and a dielectric sheet on which a conductive paste for the internal electrodes is printed in a predetermined pattern by, for example, screen printing or gravure printing are prepared, thereby preparing a dielectric sheet on which a first internal electrode pattern is printed and a dielectric sheet on which a second internal electrode pattern is printed.

[0111] Next, a predetermined number of dielectric sheets on which no internal electrode pattern is printed are laminated, and dielectric sheets on which the first internal electrode pattern and the second internal electrode pattern are printed are laminated in order thereon to form a portion that will become the inner layer portion 18. Furthermore, a predetermined number of dielectric sheets on which no internal electrode pattern is printed are laminated on the portion that will become the inner layer portion 18 to produce a laminated sheet.

[0112] Next, the laminated sheet is pressed in the lamination direction by means of a hydrostatic press or the like to produce a laminated block.

[0113] Next, the laminated block is cut to a predetermined size to cut out laminated chips, and at this time, the corners and ridges of the laminated chips may be rounded by barrel polishing or the like.

[0114] Next, the laminated chip is fired to produce the laminate 12. The firing temperature depends on the materials of the dielectric layers 14 and the internal electrodes 16, but is preferably 900°C or higher and 1400°C or lower.

[0115] Next, a conductive paste that will become the base electrode layer 32 is applied to the third surface 12c and the fourth surface 12d of the laminate 12 to form the base electrode layer 32. In this embodiment, a baked layer is formed as the base electrode layer 32. When forming the baked layer, a conductive paste containing a glass component and a metal is applied by a method such as dipping, and then a baking process is performed to form the base electrode layer 32. The temperature of the baking process at this time is preferably 700°C or higher and 900°C or lower.

[0116] When the base electrode layer 32 is formed of a conductive resin layer, the conductive resin layer can be formed by the following method. The conductive resin layer may be formed on the surface of a baked layer, or the conductive resin layer may be formed directly on the laminate without forming a baked layer.

[0117] The conductive resin layer is formed by applying a conductive resin paste containing a thermosetting resin and a metal component onto the baking layer or the laminate, followed by heat treatment at a temperature of 250°C to 550°C to thermally cure the thermosetting resin and form the conductive resin layer. The heat treatment is preferably performed in an N2 atmosphere. Furthermore, to prevent scattering of the thermosetting resin and oxidation of the various metal components, the oxygen concentration is preferably kept below 100 ppm.

[0118] When the base electrode layer 32 is formed as a thin film layer, the base electrode layer 32 can be formed by a thin film formation method such as sputtering or vapor deposition. The base electrode layer 32 formed as a thin film layer is a layer of metal particles deposited to a thickness of 1 μm or less.

[0119] Furthermore, the plating layer 34 may be provided on the exposed portion of the internal electrode 16 of the laminate 12 without providing the base electrode layer 32. In this case, the plating layer 34 can be formed by the following method.

[0120] The third surface 12c and the fourth surface 12d of the laminate 12 are plated to form a base plated electrode on the exposed portion of the internal electrode 16. Either electrolytic plating or electroless plating may be used for the plating process. However, electroless plating requires pretreatment using a catalyst or the like to improve the plating deposition rate, which has the disadvantage of complicating the process. Therefore, electrolytic plating is usually preferred. Barrel plating is preferably used as the plating method. If necessary, an upper plated electrode may be formed on the surface of the lower plated electrode in the same manner.

[0121] Thereafter, plating layers 34 are formed on the surfaces of the base electrode layer 32, the conductive resin layer or the lower-layer plated electrode, and the upper-layer plated electrode. In this embodiment, Ni and Sn plating layers are formed on the baked layers disposed on the first to sixth surfaces 12a to 12f. The Ni and Sn plating layers are formed sequentially by, for example, barrel plating. As a result, the first external electrode 30a is formed to cover the third surface 12c as well as the first, second, fifth, and sixth surfaces 12a, 12b, 12e, and 12f, and the second external electrode 30b is formed to cover the fourth surface 12d as well as the first, second, fifth, and sixth surfaces 12a, 12b, 12e, and 12f.

[0122] In this manner, the multilayer ceramic capacitor 10 is manufactured.

[0123] Next, a method for arranging the first spacers 52 and the second spacers 54 in the multilayer ceramic capacitor 10 will be described.

[0124] First, the spacer manufacturing pastes are placed on the external electrodes 30 of the multilayer ceramic capacitor 10, which are placed on a support substrate, by screen printing, dispensing, or the like. The first external electrode 30a and the first spacer manufacturing paste, and the second external electrode 30b and the second spacer manufacturing paste are aligned, and the first spacer manufacturing paste and the second spacer manufacturing paste are applied to the multilayer ceramic capacitor. Then, in the spacer placement process, the amount of paste can be changed or the mask design can be modified to form first spacers 52 and second spacers 54 in the desired shape and placement.

[0125] Thereafter, heat treatment is performed to form the first spacers 52 and the second spacers 54. The non-filling ratio in the first region 80 and the second region 82 can be adjusted by adjusting the temperature and time of the heat treatment. For example, if the heat treatment conditions are gradually increased from 120° C. to 300° C. up to the Top temperature, the non-filling ratio in the first region 80 and the second region 82 can be set to approximately 30% to 40%. In this case, the volatilization amount and viscosity of the insulating material can be adjusted by increasing the heat treatment temperature or extending the heat treatment time.

[0126] Next, a method for arranging the third spacer 56 in the multilayer ceramic capacitor 10 will be described.

[0127] When the third spacer 56 is disposed after the first spacer 52 and the second spacer 54 are formed, the third spacer 56 can be disposed as follows. First, the multilayer ceramic capacitor 10 on which the first spacer 52 and the second spacer 54 are disposed is aligned so that the first spacer 52 and the second spacer 54 face upward. At this time, the surface of the multilayer ceramic capacitor 10 on which the first spacer 52 and the second spacer 54 are disposed may be cleaned with a solvent. This removes obstacles disposed on the surface, thereby reducing the number of obstacles that prevent particles from entering between the laminate 12 and the first spacer 52, and between the laminate 12 and the second spacer 54 in the direction perpendicular to the mounting surface S. Furthermore, in the subsequent process of forming the third spacer, by increasing the amount of insulating material that constitutes the third spacer 56 that penetrates between the laminate 12 and the first spacer 52, and between the laminate 12 and the second spacer 54 in the direction perpendicular to the mounting surface S, the non-filling rate of the non-filled area 74 in the first region 80 and the second region 82 can be reduced.

[0128] Next, a paste for manufacturing the third spacers 56 is prepared. The paste for manufacturing the third spacers 56 is composed of an insulating paste. The color of the third spacers 56 can be changed by adding various materials as additives.

[0129] Next, with respect to the multilayer ceramic capacitor 10 on which the first spacers 52 and second spacers 54 have been arranged, a third spacer 56 is formed between the first spacer 52 and the second spacer 54 using a dispenser or squeegee printing. Here, the amount of the third spacer manufacturing paste that wets the first spacers 52 and the second spacers 54 can be changed by adjusting the amount of the paste.

[0130] Furthermore, the insulating material constituting the third spacer 56 is allowed to penetrate between the laminate 12 and the first spacer 52 and between the laminate 12 and the second spacer 54, thereby forming the first insulating layer 70 and the second insulating layer 72. At this time, the penetration can be achieved by evacuating after placing the paste for manufacturing the third spacer. The amount of penetration can be controlled by changing the vacuuming time and pressure.

[0131] Thereafter, the chip on which the third spacer is formed is heated for 20 minutes to 80 minutes at a temperature of 100° C. to 200° C. At this time, the central portions of the interfaces in the first direction y between the first spacer 52 and the second spacer 54 and the laminate 12 are covered with obstacles to allow the insulating material to penetrate, thereby reducing the amount of insulating material that penetrates into the central regions of the first region 80 and the second region 82, and thereby forming a difference in non-filling rate.

[0132] Through the above steps, the multilayer ceramic electronic component 100 of this embodiment is manufactured.

[0133] 3. Experimental Example Next, in order to confirm the effects of the multilayer ceramic electronic component according to the present invention described above, multilayer ceramic electronic components were fabricated as experimental samples according to the above-described manufacturing method, with the unfilled ratios being varied, and the bonding strength was evaluated by a lateral push test.

[0134] (1) Specifications of the multilayer ceramic capacitors fabricated as samples in the experimental examples Using the manufacturing method according to the above embodiment, multilayer ceramic capacitors were fabricated as samples of the comparative example and the multilayer ceramic electronic components of Examples 1 to 4. Dimensions of the multilayer ceramic capacitor (design values): L x W x T = 1.6 mm x 0.8 mm x 0.8 mm Ceramic material: BaTiO3 Internal electrode material: Ni Base electrode layer of the external electrode: Conductive metal (Cu) and glass component Plating layer Two layers formed: Ni plating layer and Sn plating layer Ni plating layer thickness: Approximately 3 μm Sn plating layer thickness: Approximately 5 μm

[0135] (2) Specifications of Spacers of Multilayer Ceramic Electronic Components as Samples of Experimental Examples Using the manufacturing method according to the above embodiment, spacers of multilayer ceramic electronic components were formed as samples of the Comparative Example and Examples 1 to 4. - Dimensions of the first and second spacers in the first direction: 0.85 mm ± 0.05 mm - Dimensions of the first and second spacers in the second direction: 0.45 mm ± 0.05 mm - Dimensions of the first and second spacers in the height direction: 0.15 mm ± 0.05 mm - Composition of the first and second spacers: 31.5 wt% Cu-10 wt% Ni powder with a D50 of 5 μm, 58.5 wt% solder powder with a Sn-3 wt% Ag-0.5 wt% Cu composition, and 10 wt% phenolic resin, solvent, and additives - Composition of the third spacer (insulating material): epoxy resin, phenolic resin, additives (coupling agent, catalyst), inorganic substances (silica, alumina)

[0136] In this experimental example, a first spacer 52 and a second spacer 54 were arranged on the multilayer ceramic capacitor 10. Then, a third spacer 56 was arranged so that the area covering the first spacer 52 was 70% ± 5% of the area of ​​the fourth surface 52d of the first spacer 52. Furthermore, the third spacer 56 was arranged so that the area covering the second spacer 54 was 70% ± 5% of the area of ​​the fourth surface 54d of the second spacer 54. Furthermore, the third spacer 56 was arranged so as to be continuous on the surface of the laminate 12.

[0137] In the comparative example sample, the first insulating layer 70 is not formed between the laminate 12 and the first spacer 52, and the second insulating layer 72 is not formed between the laminate 12 and the second spacer 54. On the other hand, in each of the samples of Examples 1 to 4, the non-filling ratios in the first region 80 and the second region 82 were changed as shown in Table 1.

[0138] (2) Method for Calculating the Non-Filling Ratio The non-filling ratios of the first region 80 and the second region 82 in each sample were calculated as follows. First, the first spacer 52 and the second spacer 54 were dissolved from the multilayer ceramic electronic component of each sample. Images were then taken in low vacuum mode using a JEOL Field Emission-Scanning Electron Microscope (FE-SEM) manufactured by JEOL Ltd., and elemental analysis was performed using EDX. The imaging conditions in vacuum mode for the FE-SEM were an acceleration transmission of 5.00 kV and a measurement magnification of 120x. Next, a binarization analysis was performed using image processing software on the mapping image when the detected element was C (carbon), identifying the non-filling region 74, which is a region that does not contain carbon, and the region that contains carbon. The non-filling ratio was then calculated as the ratio of the total area of ​​the non-filling region 74 to the area of ​​the first region 80.

[0139] Specifically, the non-filling rate on the first spacer 52 side was calculated as the ratio of the sum of the areas a1 of the non-filling regions 74 to the area A1 of the first regions 80. The non-filling rate on the second spacer 54 side was calculated as the ratio of the sum of the areas a2 of the non-filling regions 74 to the area A2 of the second regions 82.

[0140] (3) Method of Bonding Strength Test As an experimental example, each sample in which the non-filling rate of the first region 80 was changed as shown in Table 1 was placed with the first surface 12a facing downward. Then, a pressing tool was placed 0.03 mm above the second surface 12b in a direction perpendicular to the second surface 12b, and the bonding strength was evaluated by a lateral pressing test in which the spacer was pressed laterally from the center toward the outside in the first direction y.

[0141] (4) Results Table 1 shows the results of the adhesion test, which shows the relationship between the force at which the first spacer 52 and the multilayer ceramic capacitor 10 were separated and the non-filling ratio, when the adhesion strength was evaluated by a lateral push test for each sample of multilayer ceramic electronic components according to the comparative example and examples 1 to 4. Here, the adhesion strength is shown as a relative evaluation to the force at which the first spacer 52 and the multilayer ceramic capacitor 10 were separated for the sample of the comparative example.

[0142]

[0143] According to Table 1, the results of evaluating the adhesion strength by the lateral push test confirmed that, as shown in Examples 1 to 4, the adhesion strength increases as the non-filling rate decreases.

[0144] The above results suggest that by reducing the non-filling rate in the first region 80, the bonding strength between the multilayer ceramic capacitor 10 and the first spacer can be improved.

[0145] As described above, the embodiment of the present invention has been disclosed in the above description, but the present invention is not limited to this.

[0146] In other words, various modifications can be made to the above-described embodiments in terms of mechanism, shape, material, quantity, position, arrangement, etc. without departing from the scope of the technical idea and purpose of the present invention, and these modifications are included in the present invention.

[0147] <1> A multilayer ceramic capacitor including: a laminate having first and second surfaces that face each other in a direction perpendicular to a mounting surface, third and fourth surfaces that face each other in a first direction orthogonal to the direction perpendicular to the mounting surface, and fifth and sixth surfaces that face each other in a second direction orthogonal to the direction perpendicular to the mounting surface and the first direction; first external electrodes arranged on the third and second surfaces of the laminate; and second external electrodes arranged on the fourth and second surfaces of the laminate; a first spacer arranged on the first external electrodes; a second spacer arranged on the second external electrodes; and a third spacer arranged on the second surface between the first spacer and the second spacer, the third spacer being made of an insulating material containing carbon in its composition; and a first insulating material layer including at least the insulating material derived from the third spacer is provided between the laminate and the first spacer, a multilayer ceramic electronic component, wherein when a region where the laminate and the first spacer overlap when viewed in a direction perpendicular to the mounting surface is defined as a first region, the first region has a non-filled region where no insulating material constituting the first insulating material layer is present, and the non-filling ratio of the first region is 41% or less.

[0148] <2> When the longest part of the multilayer ceramic electronic component in the second direction, which is a combined region of the first insulating material layer located on the first region side and the non-filled region located inside the first insulating material layer, is divided into thirds, the respective regions are defined as a first outer region of the first region, a central region of the first region, and a second outer region of the first region, and the ratio of the sum of the areas of the non-filled regions located inside the first outer region of the first region to the area of ​​the first outer region of the first region is defined as the porosity of the first outer region of the first region, the ratio of the sum of the areas of the non-filled regions located inside the central region of the first region to the area of ​​the central region of the first region is defined as the porosity of the central region of the first region, and the ratio of the sum of the areas of the non-filled regions located inside the second outer region of the first region to the area of ​​the second outer region of the first region is defined as the porosity of the second outer region of the first region, The multilayer ceramic electronic component according to <1>, wherein the porosity of the first outer region of the first region and the porosity of the second outer region of the first region are smaller than the porosity of the central region of the first region.

[0149] <3> The multilayer ceramic electronic component according to <1> or <2>, wherein, when a region defined by the first insulating material layer located on the first region side and the non-filled region located inside the first insulating material layer is divided into thirds with the longest portion of the multilayer ceramic electronic component in the second direction, the respective regions are defined as a first outer region of the first region, a central region of the first region, and a second outer region of the first region, the sum of the areas of the non-filled regions located in the first outer region of the first region and the second outer region of the first region is smaller than the sum of the areas of the non-filled regions located in the central region of the first region.

[0150] <4> The multilayer ceramic electronic component according to any one of <1> to <3>, wherein, when a region defined by combining the first insulating material layer located on the first region side and the non-filled region located inside the first insulating material layer is divided into thirds with the longest portion of the multilayer ceramic electronic component in the second direction, the respective regions are defined as a first outer region of the first region, a central region of the first region, and a second outer region of the first region, the lengths of the first outer region of the first region and the second outer region of the first region in the first direction are longer than the length of the central region of the first region in the first direction.

[0151] <5> The multilayer ceramic electronic component according to any one of <1> to <4>, wherein, when a region defined by combining the first insulating material layer located on the first region side and the non-filled region located inside the first insulating material layer is divided into thirds with the longest portion of the multilayer ceramic electronic component in the second direction, the respective regions are defined as a first outer region of the first region, a central region of the first region, and a second outer region of the first region, and the areas of the first outer region of the first region and the second outer region of the first region are larger than the area of ​​the central region of the first region.

[0152] <6> The multilayer ceramic electronic component according to <1>, further comprising: a second insulating material layer between the laminate and the second spacer, the second insulating material layer including at least an insulating material derived from the third spacer; when a region where the laminate and the second spacer overlap as viewed in a direction perpendicular to the mounting surface is defined as a second region, the second region includes a region where the insulating material constituting the second insulating material layer is absent; and the non-filling ratio of the second region is 41% or less.

[0153] <7> When the combined region of the second insulating material layer located on the second region side and the non-filled region located inside the second insulating material layer is defined as a first outer region of the second region, a central region of the second region, and a second outer region of the second region, the longest portion of the multilayer ceramic electronic component in the second direction is divided into thirds, and the respective regions are defined as a first outer region of the second region, a central region of the second region, and a second outer region of the second region, and the ratio of the sum of the areas of the non-filled regions located inside the first outer region of the second region to the area of ​​the first outer region of the second region is defined as the porosity of the first outer region of the second region, the ratio of the sum of the areas of the non-filled regions located inside the central region of the second region to the area of ​​the central region is defined as the porosity of the central region of the second region, and the ratio of the sum of the areas of the non-filled regions located inside the second outer region of the second region to the area of ​​the second outer region of the second region is defined as the porosity of the second outer region, The multilayer ceramic electronic component according to <6>, wherein the porosity of the first outer region of the second region and the porosity of the second outer region of the second region are smaller than the porosity of the central region of the second region.

[0154] <8> The multilayer ceramic electronic component according to <6> or <7>, wherein, when a region defined by the second insulating material layer located on the second region side and the non-filled region located inside the second insulating material layer is divided into thirds with the longest portion of the multilayer ceramic electronic component in the second direction, the respective regions are defined as a first outer region of the second region, a central region of the second region, and a second outer region of the second region, the total area of ​​the non-filled region located in the first outer region of the second region and the second outer region of the second region is smaller than the total area of ​​the non-filled region located in the central region of the second region.

[0155] <9> The multilayer ceramic electronic component according to any one of <6> to <8>, wherein, when a region defined by combining the second insulating material layer located on the second region side and the non-filled region located inside the second insulating material layer is divided into thirds with the longest portion of the multilayer ceramic electronic component in the second direction, the respective regions are defined as a first outer region of the second region, a central region of the second region, and a second outer region of the second region, the lengths of the first outer region of the second region and the second outer region of the second region in the second direction are longer than the length of the central region of the first region in the first direction.

[0156] <10> The multilayer ceramic electronic component according to any one of <6> to <9>, wherein, when a region defined by combining the second insulating material layer located on the second region side and the non-filled region located inside the second insulating material layer is divided into thirds having the longest portion in the second direction of the multilayer ceramic electronic component, the respective regions are defined as a first outer region of the second region, a central region of the second region, and a second outer region of the second region, and the areas of the first outer region of the second region and the second outer region of the second region are larger than the area of ​​the central region of the second region.

[0157] <11> The multilayer ceramic electronic component according to any one of <6> to <10>, wherein the third spacer has a third region that is a region between the first region and the second region.

[0158] <12> The multilayer ceramic electronic component according to <11>, wherein the first spacer has a first spacer inner side surface that faces the second external electrode, the second spacer has a second spacer inner side surface that faces the first external electrode, the third spacer has a first connection region connected to the first spacer inner side surface and a second connection region connected to the second spacer inner side surface, and a thickness of the third region in a direction perpendicular to the mounting surface is greater than a thickness of the third region in a direction perpendicular to the first spacer inner side surface on which the first connection region is arranged.

[0159] <13> The multilayer ceramic electronic component according to <12>, wherein a thickness of the third region in a direction perpendicular to the mounting surface is greater than a thickness of the third region in a direction perpendicular to an inner side surface of the second spacer on which the second connection region is arranged.

[0160] <14> The multilayer ceramic electronic component according to any one of <11> to <13>, wherein the length of the longest part in the second direction of the first insulating layer is longer than the length of the longest part in the second direction of the third region.

[0161] <15> The multilayer ceramic electronic component according to <14>, wherein the length of the longest portion in the second direction of the second insulating layer is longer than the length of the longest portion in the second direction of the third region.

[0162] REFERENCE SIGNS LIST 100 Multilayer ceramic electronic component 10 Multilayer ceramic capacitor 12 Laminate 12a First surface 12b Second surface 12c Third surface 12d Fourth surface 12e Fifth surface 12f Sixth surface 14 Dielectric layer 16 Internal electrode 16a First internal electrode 16b Second internal electrode 18 Internal layer portion 20a First outer layer portion 20b Second outer layer portion 26 Counter electrode portion 26a First counter electrode portion 26b Second counter electrode portion 28 Lead electrode portion 28a First lead electrode portion 28b Second lead electrode portion 30 External electrode 30a First external electrode 30b Second external electrode 32 Base electrode layer 32a First base electrode layer 32b Second base electrode layer 34 Plating layer 34a First plating layer 34b Second plating layer 50 Spacer 52 First spacer 52a First surface of first spacer 52b Second surface of first spacer 52c Third surface of first spacer 52d Fourth surface of first spacer 52e Fifth surface of first spacer 52f Sixth surface of first spacer 54 Second spacer 54a First surface of second spacer 54b Second surface of second spacer 54c Third surface of second spacer 54d Fourth surface of second spacer 54e Fifth surface of second spacer 54f Sixth surface of second spacer 56 Third spacer 60 Mounting substrate 62 Solder 64a, 64b Land electrodes 70 First insulating material layer 72 Second insulating material layer 74 Non-filled region 80 First region 82 Second region 84 Third region x Direction perpendicular to the mounting surface y First direction z Second direction (longitudinal direction) T Height dimension of the multilayer ceramic capacitor W Height dimension of the multilayer ceramic capacitor in the second direction L Height dimension of the multilayer ceramic capacitor in the first direction T Height dimension of the first spacer and the second spacer S Mounting surface

Claims

1. A multilayer ceramic capacitor comprising: a laminate having a first surface and a second surface that face each other in a direction perpendicular to a mounting surface, a third surface and a fourth surface that face each other in a first direction orthogonal to the direction perpendicular to the mounting surface, and a fifth surface and a sixth surface that face each other in a second direction orthogonal to the direction perpendicular to the mounting surface and the first direction; first external electrodes arranged on the third surface and the second surface of the laminate; and second external electrodes arranged on the fourth surface and the second surface of the laminate; a first spacer arranged on the first external electrodes; a second spacer arranged on the second external electrodes; and a third spacer arranged on the second surface between the first spacer and the second spacer, the third spacer being made of an insulating material containing carbon in its composition; and a first insulating material layer between the laminate and the first spacer, the first insulating material layer containing at least the insulating material derived from the third spacer; a multilayer ceramic electronic component, wherein when a region where the laminate and the first spacer overlap when viewed in a direction perpendicular to the mounting surface is defined as a first region, the first region has a non-filled region where no insulating material constituting the first insulating material layer is present, and the non-filling ratio of the first region is 41% or less.

2. Regarding the region consisting of the first insulating material layer located on the side of the first region and the non-filled region located inside the first insulating material layer, when the longest part of the multilayer ceramic electronic component in the second direction is divided into thirds, the respective regions are defined as a first outer region of the first region, a central region of the first region, and a second outer region of the first region, and the ratio of the sum of the areas of the non-filled regions located inside the first outer region of the first region to the area of ​​the first outer region of the first region is defined as the porosity of the first outer region of the first region, the ratio of the sum of the areas of the non-filled regions located inside the central region of the first region to the area of ​​the central region of the first region is defined as the porosity of the central region of the first region, and the ratio of the sum of the areas of the non-filled regions located inside the second outer region of the first region to the area of ​​the second outer region of the first region is defined as the porosity of the second outer region of the first region, 2. The multilayer ceramic electronic component according to claim 1, wherein the porosity of the first outer region and the second outer region of the first region is smaller than the porosity of the central region of the first region.

3. A multilayer ceramic electronic component according to claim 1 or 2, wherein, for a region comprising the first insulating material layer located on the side of the first region and the non-filled region located inside the first insulating material layer, when the longest part of the multilayer ceramic electronic component in the second direction is divided into three equal parts, the respective regions are defined as a first outer region of the first region, a central region of the first region, and a second outer region of the first region, and the total area of ​​the non-filled region located in the first outer region of the first region and the second outer region of the first region is smaller than the total area of ​​the non-filled region located in the central region of the first region.

4. A multilayer ceramic electronic component according to any one of claims 1 to 3, wherein, when the longest part of the multilayer ceramic electronic component in the second direction, defined as the combined region of the first insulating material layer located on the side of the first region and the non-filled region located inside the first insulating material layer, is divided into thirds, the respective regions are defined as a first outer region of the first region, a central region of the first region, and a second outer region of the first region, the shortest length between the third surface of the laminate and the edge of the first outer region of the first region on the third surface side is shorter than the shortest length between the third surface of the laminate and the edge of the central region of the first region on the third surface side.

5. A multilayer ceramic electronic component according to any one of claims 1 to 4, wherein, when the longest part of the multilayer ceramic electronic component in the second direction, which is the combined region of the first insulating material layer located on the side of the first region and the non-filled region located inside the first insulating material layer, is divided into thirds, the respective regions are defined as a first outer region of the first region, a central region of the first region, and a second outer region of the first region, and the areas of the first outer region of the first region and the second outer region of the first region are larger than the area of ​​the central region of the first region.

6. A multilayer ceramic electronic component according to claim 1, wherein a second insulating layer containing at least the insulating material derived from the third spacer is disposed between the laminate and the second spacer, and when the overlapping region of the laminate and the second spacer as viewed in a direction perpendicular to the mounting surface is defined as a second region, the second region includes a region where the insulating material constituting the second insulating layer is absent, and the non-filling ratio of the second region is 41% or less.

7. With respect to the region consisting of the second insulating material layer located on the second region side and the non-filled region located inside the second insulating material layer, when the longest part of the multilayer ceramic electronic component in the second direction is divided into thirds, the respective regions are defined as a first outer region of the second region, a central region of the second region, and a second outer region of the second region; the ratio of the sum of the areas of the non-filled regions located inside the first outer region of the second region to the area of ​​the first outer region of the second region is defined as the porosity of the first outer region of the second region; the ratio of the sum of the areas of the non-filled regions located inside the central region of the second region to the area of ​​the central region is defined as the porosity of the central region of the second region; and the ratio of the sum of the areas of the non-filled regions located inside the second outer region of the second region to the area of ​​the second outer region of the second region is defined as the porosity of the second outer region of the second region.

7. The multilayer ceramic electronic component according to claim 6, wherein the porosity of the first outer region of the second region and the porosity of the second outer region of the second region are smaller than the porosity of the central region of the second region.

8. A multilayer ceramic electronic component according to claim 6 or 7, wherein, with respect to a region formed by combining the second insulating material layer located on the side of the second region and the non-filled region located inside the second insulating material layer, when the longest portion of the multilayer ceramic electronic component in the second direction is divided into three equal parts, the respective regions are defined as a first outer region of the second region, a central region of the second region, and a second outer region of the second region, the total area of ​​the non-filled region located in the first outer region of the second region and the second outer region of the second region is smaller than the total area of ​​the non-filled region located in the central region of the second region.

9. A multilayer ceramic electronic component according to any one of claims 6 to 8, wherein, when the longest part of the multilayer ceramic electronic component in the second direction, defined as the combined region of the second insulating material layer located on the second region side and the non-filled region located inside the second insulating material layer, is divided into thirds, the respective regions are defined as a first outer region of the second region, a central region of the second region, and a second outer region of the second region, the shortest length between the fourth surface of the laminate and the edge on the fourth surface side of the second outer region of the second region is shorter than the shortest length between the fourth surface of the laminate and the edge on the fourth surface side of the central region of the second region.

10. A multilayer ceramic electronic component according to any one of claims 6 to 9, wherein, for a region comprising the second insulating material layer located on the side of the second region and the non-filled region located inside the second insulating material layer, when the longest portion of the multilayer ceramic electronic component in the second direction is divided into three equal parts, the respective regions are defined as a first outer region of the second region, a central region of the second region, and a second outer region of the second region, and the areas of the first outer region of the second region and the second outer region of the second region are larger than the area of ​​the central region of the second region.

11. A multilayer ceramic electronic component according to any one of claims 6 to 10, wherein the third spacer has a third region that is a region between the first region and the second region.

12. A multilayer ceramic electronic component as described in claim 11, wherein the first spacer has a first spacer inner surface that faces the second external electrode, the second spacer has a second spacer inner surface that faces the first external electrode, the third spacer has a first connection region connected to the first spacer inner surface and a second connection region connected to the second spacer inner surface, and the thickness of the third region in a direction perpendicular to the mounting surface is greater than the thickness of the third region in a direction perpendicular to the first spacer inner surface on which the first connection region is located.

13. The multilayer ceramic electronic component according to claim 12, wherein the thickness of the third region in a direction perpendicular to the mounting surface is greater than the thickness of the third region in a direction perpendicular to the inner surface of the second spacer on which the second connection region is arranged.

14. A multilayer ceramic electronic component according to any one of claims 11 to 13, wherein the length of the longest portion in the second direction of the first insulating layer is longer than the length of the longest portion in the second direction of the third region.

15. The multilayer ceramic electronic component according to claim 14, wherein the length of the longest portion in the second direction of the second insulating layer is longer than the length of the longest portion in the second direction of the third region.

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