Display panel and display apparatus

Abstract

A display panel and a display apparatus. The display panel comprises at least one semiconductor layer, a first scanning signal line and a second capacitor. The at least one semiconductor layer comprises a first channel portion and a first electrically conductive portion; the first scanning signal line overlaps with the first electrically conductive portion to form a first capacitor, and overlaps with the first channel portion to form a first transistor; the second capacitor comprises a first electrically conductive block and a second electrically conductive block, the second electrically conductive block being arranged between the first electrically conductive block and the semiconductor layer comprising the first channel portion, and the second electrically conductive block being connected to the first electrically conductive portion, wherein in an orthographic projection onto a reference plane, the first electrically conductive block covers the part of the second electrically conductive block that is disposed within the outer boundary of the first electrically conductive block; and / or the second capacitor further comprises a third electrically conductive block, wherein the third electrically conductive block is arranged on the side of the first electrically conductive block away from the second electrically conductive block, the third electrically conductive block at least partially overlaps with the first electrically conductive block, and the third electrically conductive block is connected to the first electrically conductive portion.

Description

Display panel and display device Technical Field

[0001] This disclosure relates to the field of display technology, and more particularly to a display panel and display device. Background Technology

[0002] With the development of display technology, display devices (such as mobile phones, laptops, or tablets) are increasingly used in people's lives. Among them, organic light-emitting diode (OLED) display devices have received widespread attention due to their advantages such as active light emission, wide viewing angle, high contrast, fast response speed, low power consumption, and ultra-thin design.

[0003] Summary of the Invention

[0004] On one hand, a display panel is provided. The display panel includes at least one semiconductor layer, a first scan signal line, and a second capacitor. The at least one semiconductor layer includes a first channel portion and a first conductive portion. The first scan signal line overlaps with the first conductive portion to form a first capacitor, and overlaps with the first channel portion to form a first transistor; the second capacitor includes a first conductive block and a second conductive block, the second conductive block being disposed between the first conductive block and the semiconductor layer including the first channel portion, and the second conductive block being connected to the first conductive portion; wherein, in an orthographic projection onto a reference plane, the first conductive block covers a portion of the second conductive block disposed within the outer boundary of the first conductive block; and / or, the second capacitor further includes a third conductive block, the third conductive block being disposed on the side of the first conductive block away from the second conductive block, and the third conductive block at least partially overlapping the first conductive block; the third conductive block being connected to the first conductive portion.

[0005] In some embodiments, the second conductive block includes a first main body and a first connecting portion. The orthographic projection of the first main body on the reference plane is disposed within the outer boundary of the orthographic projection of the second conductive block on the reference plane; the first connecting portion is connected to the first main body; at least a portion of the orthographic projection of the first connecting portion on the reference plane is disposed outside the outer boundary of the orthographic projection of the second conductive block on the reference plane, and is connected to the first conductive portion.

[0006] In some embodiments, the orthographic projection of the third conductive block on the reference surface is disposed within the range of the orthographic projection of the first conductive block on the reference surface; the display panel further includes a first connecting line, one end of which is connected to the first conductive part, and the other end of which is connected to the third conductive block.

[0007] In some embodiments, the third conductive block includes a second main body and a second connecting portion. The orthographic projection of the second main body on the reference plane is disposed within the outer boundary of the orthographic projection of the second conductive block on the reference plane; the second connecting portion is connected to the second main body; the second connecting portion is disposed on the periphery of the second main body; the display panel further includes a first connecting line, one end of the first connecting line being connected to the first conductive portion and the other end being connected to the second connecting portion.

[0008] In some embodiments, at least a portion of the orthographic projection of the second connection portion on the reference plane is disposed outside the outer boundary of the orthographic projection of the first conductive block on the reference plane, and the portion of the second connection portion disposed outside the outer boundary of the first conductive block is connected to the first conductive portion.

[0009] In some embodiments, the orthographic projection of the first connecting portion on the reference surface is offset from the orthographic projection of the second connecting portion on the reference surface; the first connecting line is disposed on the side of the third conductive block away from the second conductive block, and the first connecting line is also connected to the first connecting portion.

[0010] In some embodiments, the first conductive block is provided with a first through hole penetrating the first conductive block, and the third conductive block extends into the first through hole and connects with the second conductive block.

[0011] In some embodiments, the third conductive block includes a second main body and a second connecting portion. The orthographic projection of the second main body on the reference surface is disposed within the outer boundary of the orthographic projection of the second conductive block on the reference surface; the second main body extends into the first through hole and connects to the second conductive block; the second connecting portion is connected to the second main body, and at least a portion of the orthographic projection of the second connecting portion on the reference surface is disposed outside the outer boundary of the orthographic projection of the second conductive block on the reference surface; the display panel further includes a first connecting line, one end of which is connected to the first conductive portion, and the other end of which is connected to the second connecting portion.

[0012] In some embodiments, the at least one semiconductor layer further includes a second channel portion; the display panel further includes a second scan signal line; the second scan signal line overlaps with the second channel portion to form a second transistor; the second scan signal line includes a first straight segment and a first bent segment. The first straight segment extends along a first direction; in orthographic projection onto the reference surface, along the first direction, the first straight segment is disposed on one side of the connecting portion; along a second direction, the first straight segment is disposed between the main body portion and the first scan signal line; the first direction intersects the second direction; in orthographic projection onto the reference surface, the first bent segment bends toward the side of the first straight segment away from the main body portion.

[0013] In some embodiments, the first scan signal line includes a first trace segment. The orthographic projection of the first trace segment onto the reference plane coincides with the orthographic projection of the first conductive portion onto the reference plane, and the linewidth of the first trace segment is less than or equal to 2.5 μm.

[0014] In some embodiments, the display panel includes a pixel circuit. The pixel circuit includes a driving transistor, the driving transistor including a fourth channel portion; the orthographic projection of the fourth channel portion onto the reference plane coincides with the orthographic projection portion of the second conductive block onto the reference plane, and the portion of the second conductive block that coincides with the fourth channel portion forms the gate of the driving transistor.

[0015] In some embodiments, the pixel circuit further includes a compensation transistor; a first terminal of the compensation transistor is connected to a second terminal of the driving transistor, and the second terminal is connected to the gate of the driving transistor; wherein the first conductive portion forms the second terminal of the compensation transistor.

[0016] In some embodiments, the display panel further includes a pixel circuit, the pixel circuit including a data writing transistor; the data writing transistor is connected to a data signal terminal; wherein, the first transistor is the data writing transistor, and the portion of the first scan signal line that overlaps with the first channel portion forms the gate of the data writing transistor.

[0017] In some embodiments, the display panel further includes a pixel circuit, the pixel circuit further includes a first reset transistor, the first terminal of the first reset transistor is connected to a first initialization signal terminal; the first reset transistor includes a third channel portion, the orthographic projection of the third channel portion on the reference plane coincides with the orthographic projection portion of the first scan signal line on the reference plane, and the portion of the first scan signal line that coincides with the third channel portion forms the gate of the first reset transistor.

[0018] On the other hand, a display device is provided. The display device includes a display panel as described in any of the above embodiments. Attached Figure Description

[0019] To more clearly illustrate the technical solutions in this disclosure, the accompanying drawings used in some embodiments of this disclosure will be briefly described below. Obviously, the drawings described below are only drawings of some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings. In addition, the drawings described below can be regarded as schematic diagrams and are not intended to limit the actual size of the product, the actual flow of the method, the actual timing of the signals, etc. involved in the embodiments of this disclosure.

[0020] Figure 1 is a structural diagram of a display device according to some embodiments;

[0021] Figure 2 is another structural diagram of a display device according to some embodiments;

[0022] Figure 3 is a structural diagram of a display device according to some embodiments, including a display panel and a driving circuit board;

[0023] Figure 4 is a structural diagram of a display panel according to some embodiments;

[0024] Figure 5 is a cross-sectional view along the cutting line AA in Figure 4;

[0025] Figure 6 is another structural diagram of a display panel according to some embodiments;

[0026] Figure 7 is another structural diagram of a display panel according to some embodiments;

[0027] Figure 8 is a structural diagram of a second conductive block according to some embodiments, including a first main body and a first connecting part;

[0028] Figure 9 is another structural diagram of a display panel according to some embodiments;

[0029] Figure 10 is a structural diagram of a first conductive block having a first through hole according to some embodiments;

[0030] Figure 11 is another structural diagram of a display panel according to some embodiments;

[0031] Figure 12 is another structural diagram of a display panel according to some embodiments;

[0032] Figure 13 is another structural diagram of a display panel according to some embodiments;

[0033] Figure 14 is another structural diagram of a display panel according to some embodiments;

[0034] Figure 15 is a structural diagram of a pixel circuit according to some embodiments;

[0035] Figure 16 is another structural diagram of a display panel according to some embodiments;

[0036] Figure 17 is another cross-sectional view along the cutting line AA in Figure 4. Detailed Implementation

[0037] The technical solutions in some embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments provided in this disclosure are within the scope of protection of this disclosure.

[0038] Unless the context otherwise requires, throughout the specification and claims, the term "comprise" and its other forms, such as the third-person singular "comprises" and the present participle "comprising," are interpreted as open-ended and encompassing, meaning "including, but not limited to." In the description of the specification, terms such as "one embodiment," "some embodiments," "exemplary embodiments," "example," "specific example," or "some examples," etc., are intended to indicate that a particular feature, structure, material, or characteristic associated with that embodiment or example is included in at least one embodiment or example of this disclosure. The illustrative representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics mentioned may be included in any suitable manner in any one or more embodiments or examples.

[0039] Hereinafter, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of embodiments of this disclosure, unless otherwise stated, "a plurality of" means two or more.

[0040] In describing some embodiments, the terms "coupled" and "connected," and their derivative expressions, may be used. The term "connected" should be interpreted broadly; for example, a "connection" can be a fixed connection, a detachable connection, or an integral part; it can be a direct connection or an indirect connection via an intermediate medium. The term "coupled," for example, indicates that two or more components have direct physical or electrical contact. The term "coupled" or "communicatively coupled" may also refer to two or more components that do not have direct contact with each other but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the content of this document.

[0041] "At least one of A, B and C" has the same meaning as "at least one of A, B or C", both including the following combinations of A, B and C: only A, only B, only C, combinations of A and B, combinations of A and C, combinations of B and C, and combinations of A, B and C.

[0042] "A and / or B" includes the following three combinations: A only, B only, and a combination of A and B.

[0043] As used herein, depending on the context, the term “if” may optionally be interpreted as meaning “when”, “in the event of”, “in response to determination”, or “in response to detection”. Similarly, depending on the context, the phrase “if it is determined that…” or “if [the stated condition or event] is detected” may optionally be interpreted as meaning “in the event of determination that…”, “in response to determination that…”, “when [the stated condition or event] is detected”, or “in response to the detection of [the stated condition or event]”.

[0044] The use of “applies to” or “configured to” in this article implies an open and inclusive language that does not preclude applicability to or configuration to devices that perform additional tasks or steps.

[0045] In addition, the use of “based on” implies openness and inclusivity, because processes, steps, calculations or other actions “based on” one or more of the stated conditions or values ​​may in practice be based on additional conditions or values ​​beyond those stated.

[0046] As used herein, “about,” “approximately,” or “approximately” includes the stated value and the average value within an acceptable range of deviation from the given value, wherein the acceptable range of deviation is determined by a person skilled in the art taking into account the measurement under discussion and the error associated with the measurement of the given quantity (i.e., the limitations of the measurement system).

[0047] As used herein, “parallel,” “perpendicular,” and “equal” include the described situation and situations that are similar to the described situation, within an acceptable range of deviation, which is determined by those skilled in the art taking into account the measurement under discussion and the error associated with the measurement of a particular quantity (i.e., the limitations of the measurement system). For example, “parallel” includes absolute parallelism and approximate parallelism, where an acceptable range of deviation for approximate parallelism may be, for example, within 5°; “perpendicular” includes absolute perpendicularity and approximate perpendicularity, where an acceptable range of deviation for approximate perpendicularity may also be, for example, within 5°; “equal” includes absolute equality and approximate equality, where an acceptable range of deviation for approximate equality may be, for example, a difference between the two equals being less than or equal to 5% of either one.

[0048] It should be understood that when a layer or element is referred to as being on another layer or substrate, it can mean that the layer or element is directly on the other layer or substrate, or that there is an intermediate layer between the layer or element and the other layer or substrate.

[0049] This document describes exemplary embodiments with reference to cross-sectional views and / or plan views, which are idealized exemplary drawings. In the drawings, the thickness of layers and the area of ​​regions are enlarged for clarity. Therefore, variations in shape relative to the drawings are contemplated due to, for example, manufacturing techniques and / or tolerances. Thus, exemplary embodiments should not be construed as being limited to the shapes of the regions shown herein, but rather include shape deviations due to, for example, manufacturing processes. For example, etched areas shown as rectangular would typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to show the actual shapes of the areas of the device, nor are they intended to limit the scope of the exemplary embodiments.

[0050] As shown in Figures 1 and 2, some embodiments of this disclosure provide a display device 1000, which can be any device that displays either moving (e.g., video) or fixed (e.g., still image) text or images.

[0051] For example, the display device 1000 can be any product or component with display function, such as a television, laptop computer, tablet computer, mobile phone, personal digital assistant (PDA), navigator, wearable device, augmented reality (AR) device, virtual reality (VR) device, in-vehicle display, or flight display.

[0052] In some examples, as shown in Figure 1, the display device 1000 can be a portable display product. For example, the display device 1000 can be a mobile phone as shown in Figure 1.

[0053] In some other examples, as shown in Figure 2, the display device 1000 can be a wearable device. For example, the display device 1000 can be a watch as shown in Figure 2.

[0054] In some embodiments, as shown in FIG3, the display device 1000 includes a display panel 100, a driving circuit board 200, a housing 300, and a cover plate 400.

[0055] The display panel 100 has a light-emitting side 100A and a non-light-emitting side 100B. The light-emitting side 100A refers to the side of the display panel 100 that can emit light (the upper side of the display panel 100 in Figure 3), and the non-light-emitting side 100B refers to the other side opposite to the light-emitting side 100A (the lower side of the display panel 100 in Figure 3).

[0056] The driving circuit board 200 is located on the non-light-emitting side of the display panel 100 and is connected to the display panel 100 to provide light-emitting signals to the display panel 100.

[0057] The housing 300 can be a box-shaped structure with an opening. The display panel 100 and the driving circuit board 200 can be disposed inside the housing 300. The cover plate 400 is disposed on the light-emitting side of the display panel 100 and is located at the opening of the housing 300.

[0058] As shown in Figure 3, the longitudinal section of the housing 300 can be U-shaped, for example. The display panel 100 and the driving circuit board 200 are disposed inside the housing 300, and the cover plate 400 is disposed at the opening of the housing 300.

[0059] The aforementioned display panel 100 comes in various types, and can be selected and configured according to actual needs.

[0060] For example, the display panel 100 described above may be an organic light-emitting diode (OLED) display panel, a quantum dot light-emitting diode (QLED) display panel, an active matrix organic light-emitting diode (AMOLED) display panel, a liquid crystal display (LCD) display panel, or a mini / micro light-emitting display (MLED) display panel, etc. The embodiments disclosed herein do not impose specific limitations.

[0061] The following description uses the above-mentioned display panel 100 as an OLED display panel as an example to illustrate some embodiments of this disclosure.

[0062] In some embodiments, as shown in Figures 4 and 5, the display panel 100 includes a reference surface and a plurality of sub-pixels 20.

[0063] The reference surface can be made of polymer resin or glass. Exemplarily, the reference surface can be flexible, and the material used includes polymer resins such as polyethersulfone (PES), polyarylate (PAR), polyetherimide (PEI), polyethylene naphthalate (PEN), polyethylene terephthalate (PET), polyphenylene sulfide (PPS), polyimide (PI), polycarbonate (PC), and cellulose acetate propionate (CAP). Exemplarily, the reference surface can be rigid, including glass materials containing SiO2 as a main component.

[0064] As shown in Figure 4, multiple sub-pixels 20 are disposed on a reference plane. These sub-pixels 20 can be arranged in multiple rows and columns, for example. Each row of sub-pixels 20 includes at least two sub-pixels 20 arranged along a first direction X, and each column of sub-pixels 20 includes at least two sub-pixels 20 arranged along a second direction Y. The first direction X intersects the second direction Y; for example, the first direction X is perpendicular to the second direction Y.

[0065] The aforementioned plurality of sub-pixels 20 may include a first sub-pixel with a first emission color, a second sub-pixel with a second emission color, and a third sub-pixel with a third emission color. The first, second, and third colors are three primary colors. For example, the first color may be red, the second color blue, and the third color green; however, this embodiment does not impose specific limitations.

[0066] In some embodiments, as shown in Figures 4 and 5, each sub-pixel 20 includes a pixel circuit 21 and a light-emitting device 22 disposed on a reference surface.

[0067] In some embodiments, the pixel circuit 21 includes a plurality of transistors 211 and a storage capacitor 212 (C).

[0068] The transistors used in the circuits provided in some embodiments of this disclosure can be thin-film transistors, field-effect transistors, or other switching devices with the same characteristics. In some embodiments of this disclosure, thin-film transistors are used as an example for illustration.

[0069] For example, transistor 211 is an oxide thin-film transistor, which has a higher carrier mobility, thus improving the response speed of transistor 211.

[0070] In some embodiments, as shown in FIG5, transistor 211 includes an active portion 2111, a source 2112, a drain 2113, and a gate 2114, with the source 2112 and drain 2113 respectively in contact with the active portion 2111. Storage capacitor 212 includes two plates disposed opposite to each other.

[0071] It should be noted that the source 2112 and drain 2113 mentioned above can be interchanged, that is, 2112 in Figure 5 represents the drain and 2113 represents the source.

[0072] In some examples, the active portion 2111 includes a source portion, a drain portion, and a channel portion, with the channel portion disposed between the source portion and the drain portion, the source portion being in contact with the source, and the drain portion being connected to the drain.

[0073] In some embodiments, as shown in FIG5, the light-emitting device 22 includes a first electrode 221, a light-emitting functional layer 222, and a second electrode 223. The first electrode 221 may be electrically connected to, for example, the source 2112 or drain 2113 of a plurality of transistors 211 that serve as driving transistors. FIG5 illustrates the electrical connection between the first electrode 221 and the drain 2113 of the transistor 211. The material of the first electrode 221 includes indium tin oxide (ITO) or silver (Ag). The material of the second electrode includes aluminum (Al), Ag, or magnesium (Mg).

[0074] It should be noted that the first electrode 221 is the anode of the light-emitting device 22, and the second electrode 223 is the cathode of the light-emitting device 22; or, the first electrode 221 is the cathode of the light-emitting device 22, and the second electrode 223 is the anode of the light-emitting device 22. The following example, using the first electrode 221 as the anode of the light-emitting device 22 and the second electrode 223 as the cathode of the light-emitting device 22, provides an exemplary description of the embodiments of this disclosure.

[0075] For example, as shown in FIG5, the second electrode 223 (cathode) is a monolayer structure.

[0076] The aforementioned light-emitting functional layer 222 may include only the light-emitting layer, or it may include at least one of the following in addition to the light-emitting layer: an electron transport layer (ETL), an electron injection layer (EIL), a hole transport layer (HTL), and a hole injection layer (HIL).

[0077] In some embodiments, as shown in FIG5, the display panel 100 further includes an encapsulation layer 30. The encapsulation layer 30 is disposed on the side of the plurality of sub-pixels 20 away from the reference surface, and the encapsulation layer 30 is used to encapsulate the light-emitting device 22 to improve the lifespan of the light-emitting device 22. The encapsulation layer 30 can be an encapsulation film or an encapsulation substrate, and the embodiments disclosed herein are not specifically limited thereto.

[0078] For example, the encapsulation layer 30 may include a single encapsulation film, or it may include two or more encapsulation films stacked together. For instance, as shown in FIG5, the encapsulation layer 30 includes a first inorganic encapsulation layer 31, a first organic encapsulation layer 32, and a second inorganic encapsulation layer 33 stacked along a direction perpendicular to and away from the reference plane. The materials of the first inorganic encapsulation layer 31 and the second inorganic encapsulation layer 33 include any one or more of silicon nitride, silicon oxynitride, or silicon oxide. The material of the first organic encapsulation layer 32 includes a polymer resin, such as polyimide.

[0079] In some embodiments, as shown in FIG6, the display panel 100 further includes at least one semiconductor layer 40, which includes a first channel portion 41 and a first conductive portion 42. The first conductive portion 42 may be either the source portion or the drain portion described above.

[0080] In some examples, the display panel 100 includes only one semiconductor layer 40, that is, the display panel 100 includes a first semiconductor layer, the first semiconductor layer including a first channel portion 41 and a first conductive portion 42.

[0081] In other examples, as shown in Figure 6, the display panel includes two semiconductor layers 40, that is, the display panel 100 includes a first semiconductor layer and a second semiconductor layer. A first channel portion 41 is disposed on the first semiconductor layer, and a first conductive portion 42 is disposed on the second semiconductor layer; or, the first channel portion 41 is disposed on the second semiconductor layer, and the first conductive portion 42 is disposed on the first semiconductor layer.

[0082] For example, the first semiconductor layer is a low-temperature polycrystalline silicon (LTPS) semiconductor layer, and the second semiconductor layer is an oxide semiconductor layer. In this way, LTPS transistors and oxide transistors can be integrated on a single display panel 100. By utilizing the advantages of both (LTPS transistors have advantages such as high mobility and fast charging, while oxide transistors have advantages such as low leakage current), the power consumption of the display panel 100 can be reduced, and the display quality of the display panel 100 can be improved.

[0083] As shown in Figure 6, the display panel 100 also includes a first scan signal line 60. The first scan signal line 60 is connected to the pixel circuit 21. The first scan signal line 60 overlaps with the first conductive portion 42 to form a first capacitor 1, and overlaps with the first channel portion 41 to form a first transistor 2. The first scan signal line 60 is used to control the conduction and cutoff of the first transistor 2.

[0084] As shown in Figure 6, the display panel 100 also includes a second capacitor 50 (e.g., a storage capacitor 212 in the pixel circuit 21). The second capacitor 50 includes a first conductive block 51 and a second conductive block 52. The second conductive block 52 is disposed between the first conductive block 51 and the semiconductor layer 40 including the first channel portion 41, and the second conductive block 52 is connected to the first conductive portion 42. That is, the first capacitor 50 and the second capacitor 50 are connected in parallel.

[0085] In related technologies, display panels suffer from severe lateral crosstalk and poor brightness uniformity, resulting in poor display performance. Through research, the inventors discovered that the first conductive block has a through-hole, and the display panel also includes a connecting line. One end of the connecting line is connected to the first channel portion, and the other end passes through the through-hole and connects to the second conductive block. The through-hole in the first conductive block results in a small overlap area between the first and second conductive blocks, leading to a smaller capacitance in the second capacitor. With the total capacitance of the first and second capacitors remaining constant, the smaller capacitance of the second capacitor results in a larger capacitance of the first capacitor, thus causing a larger voltage drop on the first scan signal, leading to severe lateral crosstalk and poor brightness uniformity in the display panel.

[0086] To solve the above-mentioned technical problems, as shown in FIG6, some embodiments of the present disclosure provide a display panel 100, in which a first conductive block 51 covers a portion of a second conductive block 52 disposed within the outer boundary of the first conductive block 51 in a projection onto a reference plane.

[0087] In other words, compared to the first conductive block in related technologies, some embodiments of this disclosure do not provide through holes in the portion of the first conductive block 51 that forms the second capacitor 50. This increases the relative area of ​​the two plates of the second capacitor 50, thereby increasing its capacitance. At this time, while keeping the total capacitance of the first capacitor 1 and the second capacitor 50 constant, the capacitance of the first capacitor 1 can be reduced, thereby reducing the voltage drop of the first scan signal line 60, reducing lateral crosstalk of the display panel 100, and improving the brightness uniformity of the display panel 100, which is beneficial for improving the display effect of the display panel 100.

[0088] It is understandable that, and it should be noted, the reference plane is the plane on which the display surface of the display panel 100 is located.

[0089] In some other embodiments, as shown in FIG7, the second capacitor 50 further includes a third conductive block 53. The third conductive block 53 is disposed on the side of the first conductive block 51 away from the second conductive block 52; the third conductive block 53 at least partially overlaps with the first conductive block 51, and the third conductive block 53 is connected to the first conductive portion 42.

[0090] In this configuration, the third conductive block 53 and the second conductive block 52 are connected, and together they form one plate of the second capacitor 50, thereby increasing the relative area of ​​the two plates of the second capacitor 50. At this time, while the total capacitance of the first capacitor 1 and the second capacitor 50 remains unchanged, the capacitance of the first capacitor 1 can be reduced, thereby reducing the voltage drop of the first scan signal line 60, reducing lateral crosstalk of the display panel 100, and improving the brightness uniformity of the display panel 100, which is beneficial to improving the display effect of the display panel 100.

[0091] In some embodiments, as shown in FIG8, the second conductive block 52 includes a first main body portion 521 and a first connecting portion 522. The orthographic projection of the first main body portion 521 on the reference plane is disposed within the outer boundary of the orthographic projection of the second conductive block 52 on the reference plane. The first connecting portion 522 is connected to the first main body portion 521, and at least a portion of the orthographic projection of the first connecting portion 522 on the reference plane is disposed outside the outer boundary of the orthographic projection of the second conductive block 52 on the reference plane, and is connected to the first conductive portion 42.

[0092] In some implementations, as shown in Figure 7, the orthographic projection of the third conductive block 53 on the reference plane is set within the range of the orthographic projection of the first conductive block 51 on the reference plane.

[0093] Based on this, the display panel 100 also includes a first connecting line 70, one end of which is connected to the first conductive part 42, and the other end is connected to the third conductive block 53, so that the third conductive block 53 and the first conductive part 42 are connected.

[0094] In other embodiments, as shown in FIG9, the third conductive block 53 includes a second main body portion 531 and a second connecting portion 532. The orthographic projection of the second main body portion 531 onto the reference plane is disposed within the outer boundary of the orthographic projection of the second conductive block 52 onto the reference plane. The second connecting portion 532 is connected to the second main body portion 531 and is disposed on the periphery of the second main body portion 531.

[0095] Based on this, the display panel 100 also includes a first connecting line 70, one end of which is connected to the first conductive part 42, and the other end is connected to the second connecting part 532, so that the third conductive block 53 and the first conductive part 42 are connected.

[0096] In some embodiments, as shown in FIG9, at least a portion of the orthographic projection of the second connecting portion 532 on the reference plane is disposed outside the outer boundary of the orthographic projection of the first conductive block 51 on the reference plane, and the portion of the second connecting portion 532 disposed outside the outer boundary of the first conductive block 51 is connected to the first conductive portion 42.

[0097] By configuring it in this way, the relative area of ​​the third conductive block 53 and the second conductive block 52 can be increased, further increasing the relative area of ​​the two plates of the second capacitor 50 and increasing the capacitance of the second capacitor 50. At this time, while the total capacitance of the first capacitor 1 and the second capacitor 50 remains unchanged, the capacitance of the first capacitor 1 can be reduced, thereby reducing the voltage drop of the first scan signal line 60, reducing the lateral crosstalk of the display panel 100 and improving the brightness uniformity of the display panel 100, which is beneficial to improving the display effect of the display panel 100.

[0098] In some embodiments, as shown in FIG9, the orthographic projection of the first connecting portion 522 on the reference plane is offset from the orthographic projection of the second connecting portion 532 on the reference plane. The first connecting line 70 is also connected to the first connecting portion 522.

[0099] In this way, the film layer between the second conductive block 52 and / or the third conductive block 53 and the first conductive block 51 is reduced, which can decrease the distance between the second conductive block 52 and / or the third conductive block 53 and the first conductive block 51, reduce the distance between the two plates of the second capacitor 50, and further increase the capacitance of the second capacitor 50. At this time, with the total capacitance of the first capacitor 1 and the second capacitor 50 remaining unchanged, the capacitance of the first capacitor 1 can be reduced, thereby reducing the voltage drop of the first scan signal line 60, reducing the lateral crosstalk of the display panel 100 and improving the brightness uniformity of the display panel 100, which is beneficial to improving the display effect of the display panel 100.

[0100] In some embodiments, as shown in FIG10, the first conductive block 51 is provided with a first through hole 511 penetrating the first conductive block 51. As shown in FIG11, the third conductive block 53 extends into the first through hole 511 and connects with the second conductive block 52. In this way, the second conductive block 52 and the third conductive block 53 can be connected.

[0101] In some embodiments, as shown in FIG11, the third conductive block 53 includes a second main body portion 531 and a second connecting portion 532. The orthographic projection of the second main body portion 531 onto the reference plane is disposed within the outer boundary of the orthographic projection of the second conductive block 52 onto the reference plane. The second main body portion 531 extends into the first through hole 511 and connects to the second conductive block 52. The second connecting portion 532 is connected to the second main body portion 531, and at least a portion of the orthographic projection of the second connecting portion 532 onto the reference plane is disposed outside the outer boundary of the orthographic projection of the second conductive block 52 onto the reference plane.

[0102] Based on this, the display panel 100 also includes a first connecting line 70, one end of which is connected to the first conductive part 42, and the other end is connected to the second connecting part 532. In this way, the first conductive part 42, the second conductive block 52, and the third conductive block 53 can be connected.

[0103] In some embodiments, as shown in FIG12, the second conductive block 52 includes a first main body portion 521 and a first connecting portion 522. The orthographic projection of the first main body portion 521 onto the reference plane is disposed within the outer boundary of the orthographic projection of the second conductive block 52 onto the reference plane. At least a portion of the orthographic projection of the first connecting portion 522 onto the reference plane is disposed outside the outer boundary of the orthographic projection of the second conductive block 52 onto the reference plane. A third conductive block 53 extends into the first through hole 511 and connects to the first main body portion 521.

[0104] Based on this, the display panel 100 also includes a first connecting line 70, one end of which is connected to the first conductive part 42, and the other end is connected to the first connecting part 522. In this way, the first conductive part 42, the second conductive block 52, and the third conductive block 53 can be connected.

[0105] In some embodiments, as shown in FIG6, at least one semiconductor layer 40 further includes a second channel portion 43. The display panel also includes a second scan signal line 80, which is connected to the pixel circuit 21. The second scan signal line 80 overlaps with the second channel portion 43 to form a second transistor 3. The second scan signal line 80 is used to control the conduction or cutoff of the second transistor 3.

[0106] For example, the second channel portion 43 may be disposed in the same layer as the first channel portion 41, or the second channel portion 43 may be disposed in the same layer as the first conductive portion 42. For example, as shown in FIG6, the second channel portion 43 and the first conductive portion 42 are disposed in the same layer.

[0107] As shown in Figures 13 and 14, the second scan signal line 80 includes a first straight segment 81 and a first bent segment 82. The first straight segment 81 extends along a first direction X. In orthographic projection onto a reference plane, along the first direction X, the first straight segment 81 is disposed on one side of the connecting portion (first connecting portion 522 or second connecting portion 532), and along the second direction Y, the first straight segment 81 is disposed between the main body portion (first main body portion 521 or second main body portion 531) and the first scan signal line 60. The first bent segment 82 bends toward the side of the first straight segment 81 away from the main body portion to avoid the connecting portion. In this way, the size of the pixel circuit 21 along the second direction Y can be reduced, thereby increasing the number of pixel circuits 21, which is beneficial to improving the resolution of the display panel 100.

[0108] In some embodiments, as shown in Figures 13 and 14, the first scan signal line 60 includes a first trace segment 61, the orthographic projection of the first trace segment 61 on the reference plane coincides with the orthographic projection of the first conductive portion 42 on the reference plane, and the line width of the first trace segment 61 is less than or equal to 2.5 μm.

[0109] By setting it in this way, the relative area between the first scan signal line 60 and the first conductive part 42 can be reduced, the capacitance of the first capacitor 1 can be reduced, thereby reducing the voltage drop of the first scan signal line 60, reducing the lateral crosstalk of the display panel 100 and improving the brightness uniformity of the display panel 100, which is beneficial to improving the display effect of the display panel 100.

[0110] For example, the line width of the third trace segment is 2.5μm, 2μm, 1.4μm or 0.9μm.

[0111] In some implementations, taking the pixel circuit 21 as a 7T1C structure as an example, some embodiments of this disclosure are illustrated by way of example. As shown in FIG15, the pixel circuit 21 includes a driving transistor T1, a compensation transistor T2, a data writing transistor T3, a first reset transistor T4, a second reset transistor T5, a first light-emitting transistor T6, a second light-emitting transistor T7, and a first storage capacitor C1.

[0112] In this configuration, the control gate of the driving crystal T1 is connected to the first node N1, the first terminal is connected to the second node N2, and the second terminal is connected to the third node N3. The first terminal of the compensation transistor T2 is connected to the third node N3, the second terminal is connected to the first node N1, and the control gate is connected to the first scan signal terminal GATE1. The first terminal of the data writing transistor T3 is connected to the data signal terminal DATA, the second terminal is connected to the second node N2, and the control gate is connected to the second scan signal terminal GATE2. The first reset transistor T4 has its first terminal connected to the first initialization signal terminal VINIT1, its second terminal connected to the anode of the light-emitting device 22, and its control gate connected to the first reset signal terminal RESET1. The first terminal of the second reset transistor T5 is connected to the second initialization signal terminal VINIT2, the second terminal is connected to the first node N1, and the control gate is connected to the second reset signal terminal RESET2. The first light-emitting transistor T6 has its first terminal connected to the first voltage signal terminal VDD, its second terminal connected to the second node N2, and its control gate connected to the light-emitting signal terminal EM. The first electrode of the second light-emitting transistor T7 is connected to the third node N3, the second electrode is connected to the anode of the light-emitting device 22, and the control electrode is connected to the light-emitting signal terminal EM.

[0113] Furthermore, as shown in Figure 15, the cathode of the light-emitting device 22 is connected to the second voltage signal terminal VSS. The output level of the second voltage signal terminal VSS is lower than the output level of the first voltage signal terminal VDD.

[0114] In some embodiments, as shown in FIG16, the driving transistor T1 includes a fourth channel portion T13. The orthographic projection of the fourth channel portion T13 onto the reference plane coincides with the orthographic projection of the second conductive block 52 onto the reference plane. The portion of the second conductive block 52 that coincides with the fourth channel portion T13 forms the gate of the driving transistor T1. The fourth channel portion T13 is disposed on the first semiconductor layer 101.

[0115] Based on this, as shown in FIG16, the first conductive part 42 forms the second electrode of the compensation transistor T2.

[0116] In some embodiments, the first transistor 2 is a data writing transistor T3, and the portion of the first scan signal line 60 that overlaps with the first channel portion 41 forms the gate of the data writing transistor T3.

[0117] By setting it up in this way, when all sub-pixels have the same gray level, the difference between the data signals written by the driving transistors T1 of the multiple pixel circuits 21 can be reduced, thereby improving the brightness uniformity of the display panel 100.

[0118] In some embodiments, as shown in FIG16, the first reset transistor T4 includes a third channel portion T43. The orthographic projection of the third channel portion T43 on the reference plane coincides with the orthographic projection of the first scan signal line 60 on the reference plane. The portion of the first scan signal line 60 that coincides with the third channel portion T43 forms the gate of the first reset transistor T4.

[0119] By setting it in this way, the difference in potential between the anodes of the light-emitting devices 22 of the multiple sub-pixels 20 can be reduced, thereby improving the brightness uniformity of the display panel 100.

[0120] In some examples, the first reset signal terminal RESET1 and the first scan signal terminal GATE1 in a pixel circuit 21 are connected to the same first scan signal line 60. In other examples, as shown in FIG16, the sub-pixels 20 are arranged in an array with multiple rows and columns, and the first scan signal terminal GATE1 in a pixel circuit 21 and the first reset signal terminal RESET1 in a pixel circuit 21 in the previous row are connected to the same first scan signal line 60.

[0121] The first conductive layer 103, the second conductive layer 104, the third conductive layer 105, the fourth conductive layer 106, and the fifth conductive layer 107 are illustrated below with reference to the film layers included in the display panel 100.

[0122] In some embodiments, as shown in FIG5, the pixel circuit 21 includes a low-temperature polycrystalline silicon thin-film transistor and an oxide thin-film transistor. In this case, along a direction perpendicular to the reference plane and away from the reference plane, the display panel 100 further includes a low-temperature polycrystalline silicon semiconductor layer ACT1, a first gate insulating layer GI1, a first gate conductive layer GT1, a second gate insulating layer GI2, a second gate conductive layer GT2, a first interlayer insulating layer ILD1, an oxide semiconductor layer ACT2, a third gate insulating layer GI3, a third gate conductive layer GT3, a second interlayer insulating layer ILD2, a first source / drain conductive layer SD1, a first planarization layer PLN1, a second source / drain conductive layer SD2, and a second planarization layer PLN2.

[0123] In this configuration, the first channel portion 41 is disposed on the low-temperature polysilicon semiconductor layer ACT1, the second conductive block 52 and the first scan signal line 60 are disposed on the first gate conductive layer GT1, the first conductive block 51 is disposed on the second gate conductive layer GT2, the first conductive portion 42 and the second channel portion 43 are disposed on the oxide semiconductor layer ACT2, the third conductive block 53 and the second scan signal line 80 are disposed on the third gate conductive layer GT3, and the first connecting line 70 is disposed on the first source-drain conductive layer SD1.

[0124] In some embodiments, as shown in FIG17, the pixel circuit 21 includes only low-temperature polycrystalline silicon thin-film transistors. In this case, along a direction perpendicular to and away from the reference plane, the display panel 100 further includes a low-temperature polycrystalline silicon semiconductor layer ACT1, a first gate insulating layer GI1, a first gate conductive layer GT1, a second gate insulating layer GI2, a second gate conductive layer GT2, a third gate insulating layer GI3, a third gate conductive layer GT3, a first interlayer insulating layer ILD1, a first source-drain conductive layer SD1, a first planarization layer PLN1, a second source-drain conductive layer SD2, and a second planarization layer PLN2.

[0125] In this configuration, the first channel portion 41, the second channel portion 43, and the first conductive portion 42 are disposed on the low-temperature polycrystalline silicon semiconductor layer ACT1, the second conductive block 52 and the first scan signal line 60 are disposed on the first gate conductive layer GT1, the first conductive block 51 is disposed on the second gate conductive layer GT2, the third conductive block 53 and the second scan signal line 80 are disposed on the third gate conductive layer GT3, and the first connecting line 70 is disposed on the first source-drain conductive layer SD1.

[0126] In the description of this specification, specific features, structures, materials, or characteristics may be combined in any suitable manner in one or more embodiments or examples.

[0127] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. A display panel, comprising: At least one semiconductor layer, including a first channel portion and a first conductive portion; The first scan signal line overlaps with the first conductive portion to form a first capacitor, and overlaps with the first channel portion to form a first transistor; The second capacitor includes a first conductive block and a second conductive block, the second conductive block being disposed between the first conductive block and a semiconductor layer including the first channel portion, and the second conductive block being connected to the first conductive portion; In the orthographic projection onto the reference plane, the first conductive block covers the portion of the second conductive block disposed within the outer boundary of the first conductive block; and / or, the second capacitor further includes a third conductive block disposed on the side of the first conductive block away from the second conductive block, and the third conductive block at least partially overlaps with the first conductive block; the third conductive block is connected to the first conductive portion.

2. The display panel according to claim 1, wherein, The second conductive block includes: The first main body portion is disposed within the outer boundary of the orthographic projection of the second conductive block on the reference surface, as shown in the orthographic projection of the second conductive block on the reference surface. A first connecting portion is connected to the first main body portion; at least a portion of the orthographic projection of the first connecting portion on the reference surface is disposed outside the outer boundary of the orthographic projection of the second conductive block on the reference surface, and is connected to the first conductive portion.

3. The display panel according to claim 2, wherein, The orthographic projection of the third conductive block on the reference plane is located within the range of the orthographic projection of the first conductive block on the reference plane. The display panel also includes: A first connecting line; one end of the first connecting line is connected to the first conductive part, and the other end is connected to the third conductive block.

4. The display panel according to claim 2, wherein, The third conductive block includes: The second main body portion, in the orthographic projection of the reference plane, is disposed within the outer boundary of the orthographic projection of the second conductive block on the reference plane; The second connecting part is connected to the second main body part; the second connecting part is disposed on the periphery of the second main body part. The display panel also includes: A first connecting line; one end of the first connecting line is connected to the first conductive part, and the other end is connected to the second connecting part.

5. The display panel according to claim 4, wherein, At least a portion of the second connecting portion is disposed outside the outer boundary of the orthographic projection of the first conductive block on the reference plane, and the portion of the second connecting portion disposed outside the outer boundary of the first conductive block is connected to the first conductive portion.

6. The display panel according to claim 5, wherein, The orthographic projection of the first connecting part on the reference plane is offset from the orthographic projection of the second connecting part on the reference plane; The first connecting line is disposed on the side of the third conductive block away from the second conductive block, and the first connecting line is also connected to the first connecting part.

7. The display panel according to claim 1, wherein, The first conductive block has a first through hole penetrating through the first conductive block, and the third conductive block extends into the first through hole and connects with the second conductive block.

8. The display panel according to claim 7, wherein, The third conductive block includes: The second main body portion, in its orthographic projection on the reference plane, is disposed within the outer boundary of the orthographic projection of the second conductive block on the reference plane; the second main body portion extends into the first through hole and connects with the second conductive block; The second connecting part is connected to the second main body part, and at least a portion of the orthographic projection of the second connecting part on the reference surface is disposed outside the outer boundary of the orthographic projection of the second conductive block on the reference surface. The display panel also includes: A first connecting line, one end of which is connected to the first conductive part, and the other end of which is connected to the second connecting part.

9. The display panel according to any one of claims 2 to 8, wherein, The at least one semiconductor layer further includes a second channel portion; The display panel further includes: A second scan signal line overlaps with the second channel portion to form a second transistor; the second scan signal line includes: A first straight line segment extends along a first direction; in the orthographic projection onto the reference plane, the first straight line segment is disposed on one side of the connecting portion along the first direction; along a second direction, the first straight line segment is disposed between the main body portion and the first scan signal line; the first direction intersects the second direction; The first bending segment; in the orthographic projection onto the reference plane, the first bending segment bends toward the side of the first straight segment away from the main body.

10. The display panel according to any one of claims 1 to 9, wherein, The first scan signal line includes: The first trace segment, when projected onto the reference plane, coincides with the projected image of the first conductive part onto the reference plane, and the line width of the first trace segment is less than or equal to 2.5 μm.

11. The display panel according to any one of claims 1 to 10, comprising: A pixel circuit includes a driving transistor; the driving transistor includes a fourth channel portion. The orthographic projection of the fourth channel portion onto the reference plane coincides with the orthographic projection of the second conductive block onto the reference plane, and the portion of the second conductive block that coincides with the fourth channel portion forms the gate of the driving transistor.

12. The display panel according to claim 11, wherein, The pixel circuit also includes: A compensation transistor; the first terminal of the compensation transistor is connected to the second terminal of the driving transistor, and the second terminal is connected to the gate of the driving transistor; wherein the first conductive portion forms the second terminal of the compensation transistor.

13. The display panel according to any one of claims 1 to 12, further comprising: The pixel circuit includes a data writing transistor; the data writing transistor is connected to a data signal terminal; wherein, the... The first transistor is the data write transistor, and the portion of the first scan signal line that overlaps with the first channel portion forms the gate of the data write transistor.

14. The display panel according to any one of claims 1 to 13, further comprising: The pixel circuit further includes a first reset transistor, the first terminal of which is connected to a first initialization signal terminal; the first reset transistor includes a third channel portion, the orthographic projection of the third channel portion on the reference plane coincides with the orthographic projection portion of the first scan signal line on the reference plane, and the portion of the first scan signal line that coincides with the third channel portion forms the gate of the first reset transistor.

15. A display device comprising a display panel as claimed in any one of claims 1 to 14.

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