Method for manufacturing semiconductor device and semiconductor device

Abstract

The present disclosure relates to a method for manufacturing a semiconductor device and a semiconductor device. The method for manufacturing a semiconductor device comprises: providing a semiconductor substrate in which a trench is formed; using a femtosecond laser beam to irradiate a second portion of the semiconductor substrate adjacent to a first portion of the trench, so that the second portion of the semiconductor substrate is non-thermally melted; and once femtosecond laser beam irradiation has been completed, performing thermal oxidation treatment on the semiconductor substrate, so as to form an oxide layer on the second portion of the semiconductor substrate.

Description

Method for manufacturing semiconductor device and semiconductor device

[0001] Cross-reference to related applications

[0002] This application is based on and claims priority to CN application No. 202410533992.8, filed on April 29, 2024, the disclosure of which is incorporated herein in its entirety. TECHNICAL FIELD

[0003] The present disclosure relates generally to the field of semiconductor, and more particularly, to a method for manufacturing semiconductor device and semiconductor device. BACKGROUND

[0004] Compared with silicon (Si), silicon carbide (SiC) as a representative of the third generation semiconductor material has more superior electrical properties such as large band gap, high critical breakdown field, high thermal conductivity, high carrier saturation drift velocity, and strong radiation resistance. With the electrical properties of SiC, semiconductor devices more suitable for application fields such as high voltage, high temperature, high frequency, and strong radiation can be developed, among which, SiC metal oxide semiconductor field effect transistor (MOSFET) is more concerned.

[0005] SiC MOSFET commonly used in high-voltage low-power scenarios is divided into trench type SiC MOSFET and planar type SiC MOSFET. The planar type SiC MOSFET with vertical structure has a JFET region, which makes the output direct current resistance of the semiconductor device larger, limiting the power threshold of the semiconductor device. In addition, the planar type SiC MOSFET has a channel mobility degradation problem caused by channel ion implantation. Compared with the traditional planar type SiC MOSFET, the trench type SiC MOSFET has no JFET region, can avoid the parasitic JFET effect (such as the additional resistance generated by the JFET region), can realize improved wafer density, and also has higher blocking voltage, better switching characteristics, and lower on-state loss, and other improved electrical properties.

[0006] SUMMARY

[0007] A brief summary of the disclosure is presented below to provide a basic understanding of some aspects of the disclosure. This summary is not an extensive overview of the disclosure. It is not intended to identify key or critical elements of the disclosure or to delineate the scope of the disclosure. Its sole purpose is to present some concepts of the disclosure in a simplified form as a prelude to the more detailed description that is presented later.

[0008] According to a first aspect of the disclosure, a method for manufacturing a semiconductor device is provided. The method includes: providing a semiconductor substrate in which a trench is formed; irradiating a second portion of the semiconductor substrate that is adjacent to a first portion of the trench with a femtosecond laser beam such that the second portion of the semiconductor substrate undergoes non-thermal melting; and after the irradiation of the femtosecond laser beam is completed, performing a thermal oxidation process on the semiconductor substrate such that the second portion of the semiconductor substrate forms an oxide layer.

[0009] In some embodiments, in an intact crystal structure of the semiconductor substrate, an oxidation rate of a crystal face where the first portion of the trench is located is lower than an oxidation rate of a crystal face where a third portion of the trench that is different from the first portion is located.

[0010] In some embodiments, the femtosecond laser beam is a first femtosecond laser beam, and the method further includes: before the thermal oxidation process is performed on the semiconductor substrate, irradiating a fourth portion of the semiconductor substrate that is adjacent to the third portion of the trench with a second femtosecond laser beam such that the fourth portion of the semiconductor substrate undergoes non-thermal melting; after the irradiation of the first femtosecond laser beam and the second femtosecond laser beam is completed, performing the thermal oxidation process on the semiconductor substrate such that the second portion and the fourth portion of the semiconductor substrate form the oxide layer, wherein the irradiation of the first femtosecond laser beam and the irradiation of the second femtosecond laser beam are configured such that a depth of a region in the second portion of the semiconductor substrate where non-thermal melting occurs is greater than a depth of a region in the fourth portion of the semiconductor substrate where non-thermal melting occurs.

[0011] In some embodiments, the method satisfies at least one of: a duration of the irradiation of the first femtosecond laser beam is greater than a duration of the irradiation of the second femtosecond laser beam; or an intensity of the first femtosecond laser beam is greater than an intensity of the second femtosecond laser beam; or the first femtosecond laser beam and the second femtosecond laser beam are irradiated in a pulsed form, and a pulse frequency of the first femtosecond laser beam is greater than a pulse frequency of the second femtosecond laser beam.

[0012] In some embodiments, the first portion of the trench is a bottom surface of the trench, and the third portion of the trench is a side surface of the trench.

[0013] In some embodiments, the semiconductor substrate includes silicon carbide.

[0014] In some embodiments, the femtosecond laser beam is provided by a femtosecond laser.

[0015] In some embodiments, a ratio of the non-thermal melting process energy contribution to the thermal melting process energy contribution of the second portion of the semiconductor substrate during irradiation by the femtosecond laser beam exceeds a preset ratio.

[0016] In some embodiments, the preset ratio is determined based on a value of the ratio of the non-thermal melting process energy contribution to the thermal melting process energy contribution at a maximum slope of a trend of the ratio with respect to a variation of a laser parameter of the femtosecond laser beam.

[0017] In some embodiments, the laser parameter of the femtosecond laser beam is configured to be no less than a first laser parameter threshold at which the second portion of the semiconductor substrate starts to melt.

[0018] In some embodiments, the laser parameter of the femtosecond laser beam is configured to be no more than a second laser parameter threshold at which the second portion of the semiconductor substrate completely melts.

[0019] In some embodiments, the laser parameter of the femtosecond laser beam is configured to make the ratio of the non-thermal melting process energy contribution to the thermal melting process energy contribution as large as possible.

[0020] In some embodiments, the first laser parameter threshold and the second laser parameter threshold are determined based on a carrier number density balance of the semiconductor substrate, a carrier system energy conservation of the semiconductor substrate, and a lattice system energy balance of the semiconductor substrate.

[0021] In some embodiments, the carrier number density balance of the semiconductor substrate requires the carrier system energy conservation of the semiconductor substrate requires the lattice system energy balance of the semiconductor substrate requires the second portion of the semiconductor substrate starts to melt requires L (T m -T0) = pC L (T Lm -T0) + N C E g the second portion of the semiconductor substrate completely melts requires L (T m -T0) + L m = pC L (T Lm -T0) + N C E g wherein N CWhere α is the carrier concentration, t is time, α1 is the single-photon absorption coefficient, I is the intensity of the femtosecond laser beam, hv is the photon energy corresponding to the wavelength of the femtosecond laser beam, β is the two-photon absorption coefficient, δ is the collisional ionization coefficient, γ is the Auger recombination coefficient, and U... C α is the total energy of the charge carrier system. FCA K is the free carrier absorption coefficient. B τ is the Boltzmann constant. C T is the carrier-lattice relaxation time. C T is the carrier temperature. L U is the lattice temperature. L Let κ be the total energy of the lattice system, z be the spatial coordinate, and κ be the total energy of the L Where ρ is the lattice thermal conductivity, ρ is the density of the semiconductor substrate, and C is the density of the semiconductor substrate. L For lattice heat capacity, T m T is the melting point of the semiconductor substrate at room temperature, T0 is the lattice temperature at room temperature, and T Lm For a carrier concentration of N C The melting point of the semiconductor substrate, E g L is the bandgap width of the semiconductor substrate. m The latent heat of fusion of the semiconductor substrate.

[0022] In some embodiments, the laser parameters of the femtosecond laser beam are set based on the relationship between the desired thickness of the oxide layer formed by the second portion of the semiconductor substrate and a first reference thickness and a second reference thickness. The first reference thickness is the thickness of the oxide layer formed by the second portion of the semiconductor substrate when the femtosecond laser beam is irradiated with a first laser parameter threshold, and the second reference thickness is the thickness of the oxide layer formed by the second portion of the semiconductor substrate when the femtosecond laser beam is irradiated with a second laser parameter threshold.

[0023] In some embodiments, the laser parameters of the femtosecond laser beam include intensity, wavelength, or a combination thereof.

[0024] In some embodiments, irradiating a second portion of a semiconductor substrate with a femtosecond laser beam includes irradiating the second portion of the semiconductor substrate with the femtosecond laser beam in a pulsed manner. In such embodiments, the femtosecond laser beam may be referred to as a pulsed femtosecond laser beam. In some examples, the laser parameters of the pulsed femtosecond laser beam include pulse width, energy density, wavelength, or combinations thereof. The pulse width and energy density of the pulsed femtosecond laser beam together determine the intensity of the pulsed femtosecond laser beam.

[0025] In some embodiments, the pulse width of the femtosecond laser beam is set between 50 femtoseconds (fs) and 150 fs.

[0026] In some embodiments, the pulse frequency of the femtosecond laser beam is configured such that the non-thermal melting of the second portion of the semiconductor substrate occurs continuously.

[0027] In some embodiments, the pulse frequency of the femtosecond laser beam is set to be greater than 1 megahertz (MHz).

[0028] In some embodiments, the femtosecond laser beam is configured to be irradiated in a direction parallel to a depth direction of the trench, and the irradiation region of the femtosecond laser beam is configured to cover the trench in a width direction of the trench.

[0029] In some embodiments, irradiating the second portion of the semiconductor substrate with the femtosecond laser beam includes causing a single femtosecond laser beam or multiple femtosecond laser beams to scan the second portion of the semiconductor substrate in a scanning direction parallel to a length direction of the trench.

[0030] In some embodiments, when the single femtosecond laser beam scans the second portion of the semiconductor substrate in the scanning direction, a previous irradiation region and a next irradiation region of the single femtosecond laser beam partially overlap with each other in the scanning direction; or when the multiple femtosecond laser beams scan the second portion of the semiconductor substrate in the scanning direction, the irradiation regions of each adjacent two of the multiple femtosecond laser beams partially overlap with each other in the scanning direction.

[0031] In some embodiments, the method further includes forming a gate electrode over the oxide layer.

[0032] In some embodiments, the method further includes forming one of the source region and the drain region in a fifth portion of the semiconductor substrate at one side of the top of the trench, and forming the other of the source region and the drain region in a sixth portion of the semiconductor substrate at the other side of the top of the trench; or forming one of the source region and the drain region in one or both of the fifth portion and the sixth portion of the semiconductor substrate, and forming the other of the source region and the drain region in a seventh portion of the semiconductor substrate below the trench.

[0033] In some embodiments, providing the semiconductor substrate in which the trench is formed includes forming a hard mask layer on the semiconductor substrate; forming a photoresist pattern on the hard mask layer to etch the hard mask layer and the semiconductor substrate to form the trench in the semiconductor substrate.

[0034] In some embodiments, the method further includes, after completing the irradiation of the femtosecond laser beam and before performing the thermal oxidation process on the semiconductor substrate, removing the hard mask layer.

[0035] In some embodiments, the femtosecond laser beam is a first femtosecond laser beam, and the method further comprises: performing a pullback treatment on the hard mask layer to expose one or both of a fifth portion and a sixth portion of the semiconductor substrate located at two sides of the top of the trench before the thermal oxidation treatment is performed on the semiconductor substrate; irradiating one or both of the fifth portion and the sixth portion of the semiconductor substrate with a third femtosecond laser beam such that non-thermal melting occurs in one or both of the fifth portion and the sixth portion of the semiconductor substrate; and after the irradiation of the first femtosecond laser beam and the third femtosecond laser beam is completed, performing the thermal oxidation treatment on the semiconductor substrate such that the second portion of the semiconductor substrate and the one or both of the fifth portion and the sixth portion form the oxide layer.

[0036] In some embodiments, the third femtosecond laser beam is the same as the first femtosecond laser beam.

[0037] In some embodiments, the irradiation of the first femtosecond laser beam and the irradiation of the third femtosecond laser beam are configured such that a depth of a region in which non-thermal melting occurs in the second portion of the semiconductor substrate is equal to a depth of a region in which non-thermal melting occurs in the one or both of the fifth portion and the sixth portion of the semiconductor substrate.

[0038] In some embodiments, the method further comprises forming a gate electrode over the oxide layer, and wherein the method further comprises: forming one of a source region and a drain region in an eighth portion of the semiconductor substrate located at a side of the fifth portion away from the trench and forming the other of the source region and the drain region in a ninth portion of the semiconductor substrate located at a side of the sixth portion away from the trench; or forming one of the source region and the drain region in one or both of the eighth portion and the ninth portion of the semiconductor substrate and forming the other of the source region and the drain region in a seventh portion of the semiconductor substrate located under the trench.

[0039] According to a second aspect of the present disclosure, there is provided a semiconductor device manufactured by the method according to the first aspect of the present disclosure.

[0040] In some embodiments, the semiconductor device comprises a MOSFET, wherein the oxide layer is configured to provide a gate oxide layer of the MOSFET. BRIEF DESCRIPTION OF DRAWINGS

[0041] The foregoing and other features and advantages of the present disclosure will become apparent to those skilled in the art from the following description of embodiments of the present disclosure, taken in conjunction with the accompanying drawings. The drawings constitute a part of this specification and are included to explain the principles of the present disclosure and to enable a person skilled in the art to make and use the present disclosure. In the drawings:

[0042] FIG. 1 shows a schematic cross-section of a conventional trench-type SiC MOSFET;

[0043] Figure 2 shows a flowchart of a method for manufacturing a semiconductor device according to some embodiments of the present disclosure;

[0044] Figures 3A to 3J show schematic cross-sectional views of semiconductor devices corresponding to the respective steps of a non-limiting example process for implementing the method shown in Figure 2;

[0045] Figure 4A shows a schematic top view of a semiconductor device scanning a semiconductor substrate with a single femtosecond laser beam according to some embodiments of the present disclosure;

[0046] Figure 4B shows a schematic top view of a semiconductor device scanning a semiconductor substrate with a multi-femtosecond laser beam according to some embodiments of the present disclosure;

[0047] Figure 5 shows a schematic cross-sectional view of a semiconductor device corresponding to corresponding steps of a non-limiting example process for implementing a method for manufacturing a semiconductor device according to some embodiments of the present disclosure;

[0048] Figure 6 shows a schematic cross-sectional view of a semiconductor device corresponding to a corresponding step of another non-limiting example process for implementing a method for manufacturing a semiconductor device according to some embodiments of the present disclosure.

[0049] Note that in the embodiments described below, the same reference numerals are sometimes used across different figures to denote the same parts or parts with the same function, and repeated descriptions are omitted. In some cases, similar reference numerals and letters are used to denote similar items, so once an item is defined in one figure, it does not need to be discussed further in subsequent figures.

[0050] For ease of understanding, the positions, dimensions, and extents of the structures shown in the accompanying drawings and other materials may not represent actual positions, dimensions, and extents. Therefore, this disclosure is not limited to the positions, dimensions, and extents disclosed in the accompanying drawings and other materials. Detailed Implementation

[0051] Various exemplary embodiments of the present disclosure will now be described in detail with reference to the accompanying drawings. It should be noted that, unless otherwise specifically stated, the relative arrangement, numerical expressions, and values ​​of the components and steps set forth in these embodiments do not limit the scope of the present disclosure.

[0052] The following description of at least one exemplary embodiment is merely illustrative and is in no way intended to limit the scope of this disclosure or its application or use. That is, the structures and methods herein are shown in an exemplary manner to illustrate different embodiments of the structures and methods in this disclosure. However, those skilled in the art will understand that they merely illustrate exemplary ways that can be used to implement this disclosure, and not exhaustive ways. Furthermore, the drawings are not necessarily drawn to scale, and some features may be enlarged to show details of specific components.

[0053] In addition, techniques, methods and equipment known to those skilled in the art may not be discussed in detail, but where appropriate, such techniques, methods and equipment should be considered part of the specification.

[0054] In all examples shown and discussed herein, any specific values ​​should be interpreted as merely exemplary and not as limitations. Therefore, other examples of exemplary embodiments may have different values.

[0055] In this document, the same or similar characters may be used to represent the same or similar variables. Therefore, once a variable is defined in one embodiment, it does not need to be described again in subsequent embodiments.

[0056] Because the electric field strength of the gate oxide layer in a SiC MOSFET is higher than that of the SiC material, the gate oxide layer may break down before the SiC material does, leading to premature failure of the semiconductor device. Therefore, to fabricate high-quality SiC MOSFETs, the reliability of the gate oxide layer must be considered.

[0057] The gate oxide layer of SiC MOSFETs is typically prepared by thermally oxidizing SiC to generate silicon dioxide (SiO2). This thermal oxidation process is anisotropic, with significant differences in oxidation rates at different crystal planes of SiC, which can adversely affect the performance of the semiconductor device. Specifically, in a hexagonal SiC structure, on the (0001) crystal plane, one chemical bond of the tetrahedral Si atoms is along the C-axis (…). <0001> This crystal plane is called the "Si crystal plane". And... On a crystal plane, one chemical bond of a tetrahedral C atom is along the C-axis. This crystal plane is called the "C plane". Besides the Si and C planes, there are other... The crystal plane is called the "A-plane". The crystal plane is called the "M plane". Surface energy, chemical activation, and electronic properties are significantly related to the crystal plane.

[0058] The thermal oxidation of SiC can be represented by the following equation:

[0059] It can be seen that the oxidation rate of SiC strongly depends on the crystal orientation of SiC. The fundamental reason is that when Si atoms on the surface of SiC substrate are oxidized, there is one Si-C bond to be broken on the C plane, two Si-C bonds to be broken on the A plane, and three Si-C bonds to be broken on the Si plane. Because the ratio of activation energy is the same as the difference in the number of broken Si-C bonds between the crystal orientation, the oxidation activation energy in the rate-limiting interface reaction should be related to the bond energy of the broken Si-C bonds on the crystal plane. Therefore, the oxidation rate is the fastest on the C plane , the oxidation rate is the slowest on the Si plane (0001), and the oxidation rate on the A plane and the M plane is between the oxidation rate on the Si plane (0001) and the C plane .

[0060] When a trench is prepared in a SiC substrate, the bottom of the trench is usually oriented to the Si plane (0001), and the sidewall of the trench is usually oriented to the A plane or the M plane . That is, under the condition of ensuring uniform heating of each crystal plane during thermal oxidation, the thickness of the oxide layer formed at the bottom of the trench in the SiC substrate will be less than the thickness of the oxide layer formed on the sidewall of the trench. For example, FIG. 1 shows a schematic cross-section of a trench-type SiC MOSFET 10 after a conventional thermal oxidation process (not all parts are shown in FIG. 1 to avoid obscuring the points, and parts not discussed are not shown in FIG. 1). As shown in FIG. 1, the thickness of the gate oxide layer 13 located at the bottom of the trench 11 is about one-third of the thickness of the gate oxide layer 12 located on the sidewall of the trench 11. However, in a trench-type SiC MOSFET, the electric field is concentrated at the corner of the trench, the oxide layer is easily broken down, and thus the blocking voltage of the semiconductor device is limited.

[0061] Although the above is described taking SiC as an example, it should be understood that if other substrate materials also have different oxidation rates on different crystal planes, resulting in anisotropy in the thermal oxidation process, there will also be similar reliability problems of the gate oxide layer.

[0062] Therefore, a new semiconductor device manufacturing method is desired to optimize the formation of the oxide layer of the semiconductor device to improve the performance of the semiconductor device.

[0063] To this end, the present disclosure provides a method for manufacturing a semiconductor device, which irradiates a portion of a semiconductor substrate that is adjacent to a specific portion of a trench with a femtosecond laser beam, so that the portion of the semiconductor substrate undergoes non-thermal melting, thereby enabling the thickness of an oxide layer formed by the portion of the semiconductor substrate to meet a demand, increasing the reliability of the oxide layer, improving the blocking voltage and the reliability of the semiconductor device. Furthermore, the thickness distribution of the oxide layer formed can be further adjusted to meet various demands in actual semiconductor manufacturing by changing the laser parameters and the irradiation parameters of the femtosecond laser beam.

[0064] The type of melting includes both thermal melting and non-thermal melting. Note that, in this context, "undergoes non-thermal melting" means that, in the melting, the non-thermal melting process is complete or the non-thermal melting process is dominant with some thermal melting process, but excludes the case where the thermal melting process is complete or the thermal melting process is dominant with some non-thermal melting process. That is, the form of melting depends on the contribution of the non-thermal melting process and the thermal melting process to the energy required for melting, and if the non-thermal melting process is dominant, it is referred to as "non-thermal melting".

[0065] A method for manufacturing a semiconductor device according to some embodiments of the present disclosure and a corresponding semiconductor device will be described in detail below with reference to the accompanying drawings. It will be understood that the actual method can have other steps and the actual semiconductor device can have other components, but in order to avoid obscuring the gist of the present disclosure, other steps / other components are not shown in the accompanying drawings and are not discussed herein.

[0066] FIG. 2 shows a flowchart of a method 100 for manufacturing a semiconductor device 200 according to some embodiments of the present disclosure. FIGS. 3A to 3J respectively show schematic cross-sectional views of a semiconductor device corresponding to respective steps of a non-limiting example process of implementing the method shown in FIG. 2.

[0067] For convenience of explanation, in the present disclosure, the direction parallel to the thickness direction of the transistor is indicated by z, the direction perpendicular to the thickness direction of the transistor is indicated by x, and the direction perpendicular to x and z is indicated by y. In addition, in this context, for convenience of explanation, "high", "low", "upper", "lower", "deep", "shallow", and the like can be used to describe the relative relationship of the transistor in z, "left", "right", and the like can be used to describe the relative relationship of the transistor in x, and "front", "back", and the like can be used to describe the relative relationship of the transistor in y.

[0068] As shown in FIG. 2, the method 100 includes, at step S102, providing a semiconductor substrate in which a trench is formed.

[0069] For example, the semiconductor substrate can include a semiconductor material having different oxidation rates on different crystal planes. In some embodiments, the semiconductor substrate includes silicon carbide. For illustrative purposes, in the following description, a semiconductor substrate whose semiconductor material includes silicon carbide (SiC) is taken as a non-limiting example.

[0070] In some embodiments, in the intact crystal structure of the semiconductor substrate (i.e., the crystal structure is not changed), the oxidation rate of the crystal plane where the first portion of the trench is located is lower than the oxidation rate of the crystal plane where the third portion of the trench, which is different from the first portion, is located. For example, in the intact crystal structure of the semiconductor substrate, the number of bonds that need to be broken when the crystal plane where the first portion of the trench is located is oxidized can be greater than the number of bonds that need to be broken when the crystal plane where the third portion of the trench is located is oxidized. In some examples, the first portion of the trench is the bottom surface of the trench, and the third portion of the trench is the side surface of the trench. For example, in a SiC semiconductor substrate, the bottom surface of the trench is usually a Si crystal plane (0001), and the side surface of the trench is usually an A crystal plane or an M crystal plane The oxidation rate of the Si crystal plane (0001) is lower than the oxidation rate of the A crystal plane and the M crystal plane .

[0071] A semiconductor substrate in which a trench is pre-formed can be provided, or a semiconductor substrate that is not processed can be provided and then a trench is formed therein. In some embodiments, providing a semiconductor substrate in which a trench is formed can include: forming a hard mask layer on the semiconductor substrate; forming a photoresist pattern on the hard mask layer to etch the hard mask layer and the semiconductor substrate to form a trench in the semiconductor substrate. For example, referring to FIGS. 3A-3D.

[0072] As shown in FIG. 3A, a semiconductor substrate 201 is provided.

[0073] As shown in FIG. 3B, a hard mask layer 202 is formed (e.g., can be formed by deposition (such as but not limited to chemical vapor deposition, etc.) or thermal oxidation growth process, etc.) on the semiconductor substrate 201.

[0074] The hard mask layer 202 may, for example, include but is not limited to an oxide or nitride of a semiconductor material or a combination thereof, such as silicon dioxide and / or silicon nitride, etc. In some embodiments, the hard mask layer 202 can be a single layer or a multi-layer structure, for example, can include a stack of a silicon dioxide layer and a silicon nitride layer. The hard mask layer 202 can have any suitable thickness, for example, the thickness thereof can be between 1 nanometer (nm) and 2 micrometers (pm), or can be between 50 nm and 1 pm, or can be between 100 nm and 500 nm. The hard mask layer 202 can help to ensure that, in a subsequent laser processing process, while a thin layer of the semiconductor substrate 201 near the trench surface (which is not covered by the hard mask layer 202) is melted by the femtosecond laser beam irradiation, the portion of the hard mask layer 202 and the thin layer of the semiconductor substrate 201 under the hard mask layer 201 near the substrate upper surface, which are also irradiated by the femtosecond laser beam, do not melt. Since the unetched portion of the upper surface of the semiconductor substrate 201 still maintains a good native interface, the hard mask layer 202 can protect the good native interface thereof.

[0075] As shown in FIG. 3C, a photoresist pattern 203 is formed on the hard mask layer 202. For example, photoresist can be first coated on the hard mask layer 202, and then the photoresist pattern 203 is formed by exposure and development. The photoresist pattern 203 can define the position, shape and size of the trench to be manufactured in the semiconductor substrate 201. Any suitable means such as spin-on coating, spray coating, dip coating, brush coating or evaporation, etc. can be used to form the photoresist pattern 203 on the hard mask layer 202.

[0076] As shown in FIG. 3D, the hard mask layer 202 and the semiconductor substrate 201 are etched to form a trench 204 in the semiconductor substrate 201. For example, the hard mask layer 202 can be first etched using the photoresist pattern 203, and then the semiconductor substrate 201 is etched to form the trench 204 using the etched hard mask layer 202 after the photoresist pattern 203 is removed (which can be removed in any suitable manner such as dry and / or wet method, etc. without particular limitation here). As shown in FIG. 3D, the trench 204 includes a bottom surface 2041 (first portion) and a side surface 2042 (third portion).

[0077] Referring back to FIG. 2, the method 100 further includes, at step S104, irradiating a second portion of the semiconductor substrate that is contiguous to the first portion of the trench with the femtosecond laser beam such that the second portion of the semiconductor substrate undergoes non-thermal melting.

[0078] For example, as shown in FIG. 3E, a second portion 2011 of the semiconductor substrate 201 abutting the bottom surface 2041 of the trench 204 is irradiated with the femtosecond laser beam 205 so that the non-thermal melting of the second portion 2011 of the semiconductor substrate 201 occurs. Meanwhile, a fourth portion 2012 of the semiconductor substrate 201 abutting the side surface 2042 of the trench 204 is not irradiated with the femtosecond laser beam 205.

[0079] The physical processes caused by the laser irradiation of the semiconductor substrate can be described as follows.

[0080] (1) Carrier excitation. The semiconductor substrate absorbs laser energy to cause carrier excitation therein. When the photon energy of the laser is greater than or equal to the band gap width of the semiconductor substrate, single-photon absorption can occur; when the photon energy of the laser is less than the band gap width of the semiconductor substrate, multi-photon absorption can occur. Free carrier absorption increases the energy of the carriers, but does not change the number density of the carriers. In addition, when the energy of one electron in a high-energy state exceeds the band gap energy of the minimum conduction band, it can ionize another electron in the valence band, thereby generating a collision ionization process of two excited electrons at the minimum of the conduction band. These electrons can be heated again by the laser electromagnetic field through free carrier absorption, and once they have enough energy, they will collide with more valence band electrons. As long as there is a strong enough laser electromagnetic field, this process will repeat, resulting in a so-called electron avalanche.

[0081] (2) Carrier lattice thermalization. After carrier excitation, electrons and holes are redistributed in the conduction band and the valence band through carrier-carrier and carrier-phonon scattering. This takes about a few hundred femtoseconds. Carrier-carrier scattering does not change the total energy of the excited carrier system or the number of carriers. In carrier-phonon scattering, free carriers lose or gain energy by emitting or absorbing phonons. Although carrier-phonon scattering does not change the number of carriers, the total energy of the carrier system is reduced due to the spontaneous emission of phonons, which transfers energy to the lattice. In semiconductors, carrier-carrier scattering and carrier-phonon scattering occur simultaneously in the first few hundred femtoseconds after excitation. Because the energy carried by the phonons emitted in the carrier-phonon scattering process is small, the carrier system and the lattice system are initially in a non-thermal equilibrium state, and many scattering processes are needed to reach a thermal equilibrium state, which takes several picoseconds to tens of picoseconds.

[0082] (3) Carrier removal. Once the carriers and the lattice reach equilibrium, the material is at a well-defined temperature. Although the carriers have the same temperature as the lattice, there is an excess of free carriers compared to thermal equilibrium. The excess carriers are removed by recombination of electrons and holes or by diffusion out of the excited region. The recombination processes include radiative and non-radiative processes. In the radiative process, which is the inverse of the photoexcitation process, the excess carrier energy is released as a photon. The non-radiative processes include Auger recombination, defect recombination, and surface recombination. For silicon, germanium, and other indirect bandgap semiconductors, Auger recombination dominates the recombination process. In the Auger process, one electron and one hole recombine, and the excess energy excites a higher electron in the conduction band. Like the other recombination mechanisms, Auger recombination reduces the carrier density. However, it keeps the total energy of the free carrier system constant, while the average energy of the remaining carriers increases. Carrier diffusion simply removes the carriers from the region of the sample where they were initially excited and does not reduce the total number of free carriers in the material.

[0083] (4) Thermal effects and changes in lattice structure. When the free carriers and the lattice reach the equilibrium temperature and the excess free carriers are removed, the material is essentially the same as a material that has been heated by conventional means. The material can reach the equilibrium temperature within a few picoseconds after laser irradiation, but it takes a longer time to remove the excess carriers. If the lattice temperature exceeds the melting or boiling point, melting or vaporization can occur, but not on the picosecond time scale. If no phase change occurs, the temperature returns to ambient values on the microsecond time scale. If melting or vaporization occurs, resolidification or liquefaction occurs when the temperature is below the melting or boiling point, respectively, but the material does not necessarily return to its original structure or phase.

[0084] Thus, to achieve non-thermal melting, it is desirable that the carriers and the lattice have not reached thermal equilibrium. Since the scattering processes required to reach thermal equilibrium typically take from a few picoseconds to tens of picoseconds, it can be advantageous to control the laser duration to be within a picosecond (ps), and more advantageously to control the laser duration to be on the order of femtoseconds (less than a picosecond, e.g., from a few femtoseconds to a few hundred femtoseconds). Such a laser beam having a duration on the order of femtoseconds is referred to herein as a femtosecond laser beam.

[0085] In some embodiments, the femtosecond laser beam is provided by a femtosecond laser. The femtosecond laser can be configured to generate very short pulses of femtosecond order (pulse width in femtosecond order, i.e. less than one picosecond, typically between a few femtoseconds to a few hundred femtoseconds), for example. In some embodiments, the second portion of the semiconductor substrate can be irradiated with the femtosecond laser beam in a pulsed form. Illustratively, the pulse width of the femtosecond laser beam can be set to be between 50 fs and 150 fs, for example about 100 fs. In some embodiments, the pulse frequency of the femtosecond laser beam can be configured such that the non-thermal melting of the second portion of the semiconductor substrate occurs continuously. That is, before the non-thermal melting process caused by the previous pulse ends, the next pulse has already irradiated onto the second portion of the semiconductor, thereby ensuring a good non-thermal melting effect. Specifically, the pulse frequency of the femtosecond laser beam can be set to be greater than 1 MHz, for example.

[0086] With the SiC semiconductor substrate as an example, when the femtosecond laser beam irradiates onto the SiC surface, the high-density plasma excited by the intense light can weaken the crystal lattice, increase the mobility of atoms, and will not significantly increase their thermal energy. When about ten percent of the valence electrons are excited to the conduction band, under the action of the plasma, the bond energy between the crystal lattices is weakened, the kinetic energy of the ions increases, and the ions will drift greatly from the initial position, thereby causing permanent structural changes. According to observations, SiC shows a molten state within a few hundred femtoseconds after laser irradiation. This non-thermal melting is accompanied by partial carbon-silicon bond breaking in the laser irradiation region, thereby reducing the number of carbon-silicon bonds that need to be broken in the subsequent oxidation process and thus having an improved oxidation rate. In contrast, if a pulsed laser beam with a pulse width above the picosecond order (e.g. a picosecond laser beam) is selected, according to observations, the irradiation region of SiC during the irradiation process undergoes a thermal melting process, and the carbon-silicon bond does not break but the bond length of the carbon-silicon bond is elongated by about fifteen percent. In such a laser irradiation process with a large pulse width, the thermal influence region in the SiC along the laser irradiation direction is large and the irradiation region modification process is violent, which is not conducive to the growth of the subsequent oxide layer.

[0087] In addition, the wavelength of the femtosecond laser beam can be determined based on the band gap width of the semiconductor substrate. In some embodiments, the wavelength of the femtosecond laser beam can be selected such that the semiconductor substrate preferentially undergoes single-photon absorption. For example, for a SiC semiconductor substrate, the wavelength of the femtosecond laser beam can be selected to be 248 nm. Of course, laser wavelengths that cause multi-photon absorption of the semiconductor substrate are also possible, but can require an increased laser intensity.

[0088] In some embodiments, step S104 can be performed under an atmosphere of an inert gas such as but not limited to nitrogen, helium, etc., or can be performed in a vacuum environment. This is to avoid water and oxygen and to maintain cleanliness, preventing the molten portion of the semiconductor substrate from being doped with impurity particles during the laser processing process.

[0089] Still referring to FIG. 3E, in some embodiments, the femtosecond laser beam 205 is configured to be irradiated along a direction parallel to the depth direction (z direction) of the trench 204. In other embodiments, the femtosecond laser beam 205 can also be configured to be irradiated at an angle with respect to the z direction. In some examples, such an angle is no more than 15 degrees, or no more than 10 degrees, or no more than 5 degrees.

[0090] In some embodiments, the irradiation region of the femtosecond laser beam 205 is configured to cover the trench 204 in the width direction (x direction) of the trench 204. As mentioned before, the hard mask layer 202 can protect the thin layer of the semiconductor substrate 201 near the upper surface underneath from melting even if it is under the irradiation region of the femtosecond laser beam 205, which can make the requirement for the spot size of the femtosecond laser beam 205 less stringent as long as the femtosecond laser beam 205 is configured to cover the trench 204 in the width direction (x direction) of the trench 204, which can also eliminate the need for scanning the femtosecond laser beam in the x direction or increasing the number of femtosecond laser beams.

[0091] If the irradiation region of the femtosecond laser beam 205 (which can be the connection of irradiation regions of multiple femtosecond laser beams) is large enough to cover the entire second portion 2011 of the semiconductor substrate 201, the second portion 2011 of the semiconductor substrate 201 can be processed at the same time. However, such an approach is subject to many limitations, such as the second portion 2011 of the semiconductor substrate 201 that can be applied cannot be too wide and / or too long, the number of laser combinations that are needed is too large, etc. Therefore, scanning the femtosecond laser beam can be used. In some embodiments, irradiating the second portion 2011 of the semiconductor substrate 201 with the femtosecond laser beam 205 can include scanning the second portion 2011 of the semiconductor substrate 201 with a single femtosecond laser beam or multiple femtosecond laser beams along a scanning direction parallel to the length direction (y direction) of the trench 204. A preset dwell time can be set for each scanning position to ensure that sufficient non-thermal melting occurs at each position. In some embodiments, the preset dwell time can be in the order of milliseconds, such as between a few milliseconds and a few hundred milliseconds. By scanning the femtosecond laser beam, a wider and / or larger second portion of the semiconductor substrate can be effectively applied, multiple second portions of the same semiconductor substrate that need non-thermal melting processing (e.g., multiple trenches 204) can be applied, and the number of lasers used can be reduced.

[0092] In some embodiments, when a single femtosecond laser beam scans the second portion 2011 of the semiconductor substrate 201 along the scanning direction, the previous irradiation area and the next irradiation area of ​​the single femtosecond laser beam partially overlap each other in the scanning direction. For example, as shown in FIG4A, the femtosecond laser beam 205 is a single femtosecond laser beam, and its previous irradiation area 250 and the next irradiation area 250' have an overlapping area 2500 in the scanning direction. By setting the overlapping area, the time for each location to undergo laser processing can be equivalently extended.

[0093] In some embodiments, when a plurality of femtosecond laser beams scan the second portion 2011 of the semiconductor substrate 201 along a scanning direction, the irradiation areas of each pair of adjacent femtosecond laser beams partially overlap each other in the scanning direction. For example, as shown in FIG4B, the femtosecond laser beam 205 includes femtosecond laser beam 251 and femtosecond laser beam 252, and when scanning the second portion 2011 of the semiconductor substrate 201, the irradiation areas of adjacent femtosecond laser beams 251 and 252 overlap in the scanning direction with an overlapping region 2500'. By setting the overlapping region, the intensity of laser processing at each location can be equivalently enhanced.

[0094] Furthermore, to promote non-thermal melting of the second part of the semiconductor substrate, it can be required that the ratio of the energy contribution of the non-thermal melting process to the energy contribution of the thermal melting process of the second part of the semiconductor substrate exceeds a preset ratio during irradiation by the femtosecond laser beam. In some examples, this preset ratio can be determined based on the value at the maximum slope of the trend of the ratio of the energy contribution of the non-thermal melting process to the energy contribution of the thermal melting process with the lasing parameters of the femtosecond laser beam. For example, with a fixed wavelength of the femtosecond laser beam, the trend of the ratio of the energy contribution of the non-thermal melting process to the energy contribution of the thermal melting process with the intensity of the femtosecond laser beam can be determined, and the preset ratio can be determined based on the ratio value at the maximum slope of this trend. If the femtosecond laser beam is a pulsed femtosecond laser beam, with a fixed wavelength and pulse width of the pulsed femtosecond laser beam, the trend of the ratio of the energy contribution of the non-thermal melting process to the energy contribution of the thermal melting process with the energy density of the pulsed femtosecond laser beam can be determined, and the preset ratio can be determined based on the ratio value at the maximum slope of this trend. Of course, the preset ratio can be the ratio corresponding to the maximum slope, or any ratio within the expected range determined based on the maximum slope.

[0095] The energy contribution of the non-thermal melting process can be determined based on the carrier concentration in the semiconductor substrate and the bandgap width of the semiconductor substrate under femtosecond laser beam irradiation. Specifically, for example, the energy contribution of the non-thermal melting process can be expressed as N. C E g , where N C E represents the carrier concentration.g This represents the bandgap width of the semiconductor substrate. The bandgap width typically varies with carrier concentration and lattice temperature. For example, the carrier concentration in 4H-SiC is 1 × 10⁻⁶. 12 / cm 3 In the case of bandgap width E g It can be represented as Among them, T L is the lattice temperature.

[0096] The energy contribution of the thermal melting process can be determined based on the density of the semiconductor substrate, the lattice heat capacity of the semiconductor substrate, and the melting point of the semiconductor substrate associated with the carrier concentration in the semiconductor substrate under femtosecond laser beam irradiation. Specifically, for example, the energy contribution of the thermal melting process can be expressed as ρC L (T Lm -T0), where ρ is the density of the semiconductor substrate, C L T is the lattice heat capacity of the semiconductor substrate. Lm For a carrier concentration of N C T0 is the melting point of the semiconductor substrate (or the lattice temperature at this point), and T0 is the lattice temperature at room temperature (usually 300K).

[0097] By controlling the laser parameters of a femtosecond laser beam, the ratio of energy contribution from the non-thermal melting process to that from the thermal melting process can be controlled, thereby controlling the degree of non-thermal melting of the semiconductor substrate. In some embodiments, the laser parameters may include intensity, wavelength, or a combination thereof. When the femtosecond laser beam is a pulsed femtosecond laser beam, the intensity of the femtosecond laser beam can be determined by the pulse width and energy density.

[0098] Specifically, the attenuation of the femtosecond laser beam inside the material along the propagation direction z can be expressed as:

[0099] Therefore, the intensity I of the femtosecond laser beam can be expressed as:

[0100] Where α1 is the single-photon absorption coefficient, β is the two-photon absorption coefficient, and α FCA Let be the free carrier absorption coefficient, z be the spatial coordinate, and I0 be the surface (z=0) laser intensity. If the pulsed femtosecond laser beam is simulated as a Gaussian beam, then the temporal and spatial evolution of I0 can be expressed as follows:

[0101] Where r is the off-axis radial distance (the distance between a point in the femtosecond laser beam and the central axis), t is time, R is reflectivity, J is energy density, and τ is... p Given the pulse width, t0 = 3τ p .

[0102] For example, for an indirect bandgap semiconductor (e.g., silicon carbide), the photon absorption process can only occur with the help of phonons, and thus, the absorption coefficients a1, β, and a FCA depend on the lattice temperature. In addition, a FCA also depends on the carrier concentration, the greater the concentration, the greater the absorption coefficient. a FCA can be expressed as where N C is the carrier concentration, e is the electronic charge, c0is the speed of light, λ is the wavelength, m eff is the effective mass of the electron, ε0is the vacuum permittivity, n is the refractive index, and μ(T) is the temperature-dependent electron mobility.

[0103] It should be noted that during laser irradiation, the change in free carrier concentration will not only affect a FCA , but also cause a significant change in reflectivity R. It is usually assumed that the reflectivity depends only on the lattice temperature when simulating irradiation, although this simplifies the calculation process, it can affect the accuracy of the simulation results. For this purpose, the Drude model can be used to consider the effect of instantaneous carrier concentration on reflectivity, and the reflectivity expression under this model framework is

[0104] where k is the extinction coefficient, ε is the dielectric constant of the semiconductor substrate, and Re(ε) is the real part of ε. The carrier concentration N C will affect the dielectric constant ε, and in turn affect the extinction coefficient k and the refractive index n, and ultimately affect the reflectivity R.

[0105] In some embodiments, the laser parameters of the femtosecond laser beam 205 are configured to be no less than a first laser parameter threshold at which the second portion 2011 of the semiconductor substrate 201 starts to melt. That is, during irradiation of the femtosecond laser beam 205 at the first laser parameter threshold, the sum of the non-thermal melting process energy contribution and the thermal melting process energy contribution just provides the heat required to be absorbed by the semiconductor substrate 201 from room temperature to the melting point. Additionally, in some embodiments, the laser parameters of the femtosecond laser beam 205 are also configured to be no greater than a second laser parameter threshold at which the second portion 2011 of the semiconductor substrate 201 completely melts. That is, during irradiation of the femtosecond laser beam 205 at the second laser parameter threshold, the sum of the non-thermal melting process energy contribution and the thermal melting process energy contribution just provides the heat required to be absorbed by the semiconductor substrate 201 from room temperature to the melting point as well as the latent heat of melting of the semiconductor substrate 201. It can be appreciated that the laser parameter configuration of the femtosecond laser beam 205 is equally applicable to the other femtosecond laser beams to be described hereinafter. Further, in order to enable the semiconductor substrate to undergo as much non-thermal melting as possible to improve the thickness of the oxide layer formed in the thermal oxidation process subsequently, the laser parameters of the femtosecond laser beam are also configured to make the ratio of the non-thermal melting process energy contribution to the thermal melting process energy contribution as large as possible.

[0106] In some embodiments, the first laser parameter threshold and the second laser parameter threshold are determined based on the carrier number density balance of the semiconductor substrate, the carrier system energy conservation and the lattice system energy balance of the semiconductor substrate. Specifically, for example, the carrier number density balance of the semiconductor substrate requires

[0107] The carrier system energy conservation of the semiconductor substrate requires

[0108] The lattice system energy balance of the semiconductor substrate requires

[0109] The second portion of the semiconductor substrate starts to melt requires L (T m -T0) = pC L (T Lm -T0) + N C E g (4)

[0110] The second portion of the semiconductor substrate completely melts requires L (T m -T0) + L m = pC L (T Lm -T0) + N C E g(5)

[0111] where N is the carrier concentration, t is time, a1 is the single-photon absorption coefficient, I is the intensity of the femtosecond laser beam, hv is the photon energy corresponding to the wavelength of the femtosecond laser beam, β is the two-photon absorption coefficient, δ is the impact ionization coefficient, γ is the Auger recombination coefficient, U is the total carrier system energy, a is the free carrier absorption coefficient, k is the Boltzmann constant, τ is the carrier-lattice relaxation time, T is the carrier temperature, T is the lattice temperature, U is the total lattice system energy, z is the spatial coordinate, κ is the lattice thermal conductivity, ρ is the density of the semiconductor substrate, C is the lattice heat capacity, T is the melting point of the semiconductor substrate at room temperature, T0 is the lattice temperature at room temperature, T is the melting point of the semiconductor substrate when the carrier concentration is N, E is the band gap width of the semiconductor substrate, and L is the latent heat of fusion of the semiconductor substrate. C C FCA B C C L L L L m Lm C g m

[0112] The laser-semiconductor interaction results in the generation of non-equilibrium carriers and increases the carrier temperature and the lattice temperature. In equation (1), the first two terms on the right side describe the single-photon absorption process and the two-photon absorption process, and the third and fourth terms describe the impact ionization process and the Auger recombination process. It can be understood that more photon absorption processes are similarly considered.

[0113] The total carrier system energy is regulated by the laser absorption process and the transport process. In equation (2), the first term on the right side describes the energy source of the carrier system through the single-photon absorption process and the free carrier absorption process, the second term is the energy source obtained by the two-photon absorption, and the third term is the energy transfer between the carrier system and the lattice system.

[0114] The laser pulse energy cannot be directly transferred to the lattice system, and the lattice system energy is obtained from the carrier system through the carrier-lattice relaxation process. In equation (3), the first term on the right side is the energy transport term of the lattice system, and the second term is the energy exchange between the lattice system and the carrier system.

[0115] If it is assumed that the optical phonon and the acoustic phonon are in a state of thermodynamic equilibrium, the lattice system can be regarded as a single thermodynamic system. Under the above assumption, the internal energy of the carrier system and the lattice system can be described as U​​​​​​​​​​​​​​​C = N C E g + C C T C and U L = C L T L , where C C is the carrier thermal capacity.

[0116] In equations (4), (5), the first term on the right side of the equal sign is the energy contribution of the thermal melting process, and the second term on the right side of the equal sign is the energy contribution of the non-thermal melting process.

[0117] For example, in the case where the wavelength (corresponding to v) of the femtosecond laser beam is fixed, by simultaneously solving the above equations (1)-(5), the intensity of the femtosecond laser beam at which equation (4) is established is solved as the first laser intensity threshold, and the intensity of the femtosecond laser beam at which equation (5) is established is solved as the second laser intensity threshold, and then the intensity of the femtosecond laser beam can be controlled to be between the first laser intensity threshold and the second laser intensity threshold, for example, the intensity value in this range that maximizes the ratio of the energy contribution of the non-thermal melting process to the energy contribution of the thermal melting process can be selected as the intensity of the femtosecond laser beam to be applied.

[0118] For example, in the case where the wavelength (corresponding to v) of the femtosecond laser beam and the pulse width (τ p ) are fixed, by simultaneously solving the above equations (1)-(5), the energy density (corresponding to J) of the femtosecond laser beam at which equation (4) is established is solved as the first laser energy density threshold, and the energy density of the femtosecond laser beam at which equation (5) is established is solved as the second laser intensity energy density threshold, and then the energy density of the pulsed femtosecond laser beam can be controlled to be between the first laser energy density threshold and the second laser intensity energy density, for example, the energy density value in this range that maximizes the ratio of the energy contribution of the non-thermal melting process to the energy contribution of the thermal melting process can be selected as the energy density of the pulsed femtosecond laser beam to be applied.

[0119] Referring back to FIG. 2, the method 100 further includes, at step S106, after the irradiation of the femtosecond laser beam is completed, performing a thermal oxidation process on the semiconductor substrate, so that the second portion of the semiconductor substrate forms an oxide layer.

[0120] For example, referring to FIG. 3F, the hard mask layer 202 can be removed after the irradiation of the femtosecond laser beam 205 is completed and before the thermal oxidation process is performed on the semiconductor substrate 201.

[0121] As shown in FIG. 3G, after the thermal oxidation process is performed on the semiconductor substrate 201, an oxide layer 206 is formed on the surface of the semiconductor substrate 201, including the oxide layer formed by the second portion 2011 and the fourth portion 2012 of the semiconductor substrate 201. As shown in FIG. 3G, it can be seen that even in the perfect crystal structure of the semiconductor substrate 201, the oxidation rate of the crystal plane where the bottom surface of the trench 204 is located is lower than the oxidation rate of the crystal plane where the side surface of the trench 204 is located, but since the second portion 2011 of the semiconductor substrate 201 is subjected to the non-thermal melting process, the thickness dl of the oxide layer formed thereby can be close to or even greater than the thickness d2 of the oxide layer formed by other portions (e.g., the fourth portion 2012) that are not subjected to the non-thermal melting process.

[0122] In addition, by controlling the degree of non-thermal melting of the semiconductor substrate, the thickness of the oxide layer formed by the semiconductor substrate can be controlled. For example, the laser parameters (such as intensity (or pulse width, energy density, etc. in the case of a pulsed femtosecond laser beam), wavelength, etc.) of the femtosecond laser beam and the irradiation parameters (such as irradiation duration, pulse frequency in the case of a pulsed femtosecond laser beam, preset dwell time of scanning, spot overlapping area, etc. in the case of a scanning femtosecond laser beam) of the femtosecond laser beam can be used to control the degree of non-thermal melting of the semiconductor substrate.

[0123] In some embodiments, the laser parameters of the femtosecond laser beam can be set based on a relationship of a desired thickness of the oxide layer to be formed by the second portion of the semiconductor substrate relative to a first reference thickness and a second reference thickness, where the first reference thickness is a thickness of the oxide layer to be formed by the second portion of the semiconductor substrate in a case where the femtosecond laser beam is irradiated with a first laser parameter threshold, and the second reference thickness is a thickness of the oxide layer to be formed by the second portion of the semiconductor substrate in a case where the femtosecond laser beam is irradiated with a second laser parameter threshold, so as to achieve flexible setting of the thickness of the oxide layer of the semiconductor substrate to meet different needs of actual semiconductor manufacturing processes.

[0124] Additionally, in some embodiments, the method 100 can further include forming a gate electrode over the oxide layer. For example, as shown in FIG. 3H, a layer of conductive material can be deposited as a gate electrode 207 over the oxide layer 206 within the trench 204. Excess conductive material and oxide layer can be removed by means such as, but not limited to, chemical mechanical polishing, etc. As a non-limiting example, the conductive material of the gate electrode 207 can include one or more of the following: polysilicon, doped polysilicon (such as polysilicon doped with phosphorus ions, polysilicon doped with arsenic ions, polysilicon doped with antimony ions), metal (e.g., copper), etc. Here, the oxide layer 206 provides a gate oxide layer for the gate electrode 207.

[0125] In some embodiments, the method 100 can further include forming one of the source region and the drain region in a fifth portion of the semiconductor substrate at one side of the top of the trench, and forming the other of the source region and the drain region in a sixth portion of the semiconductor substrate at the other side of the top of the trench. For example, as shown in FIGS. 3H and 31, the source region 208 is formed in the fifth portion 2013 of the semiconductor substrate 201 at one side of the top of the trench 204, and the drain region 209 is formed in the sixth portion 2014 of the semiconductor substrate 201 at the other side of the top of the trench 204, by means such as an ion implantation process. Of course, in other embodiments, the drain region 209 can also be formed in the fifth portion 2013 of the semiconductor substrate 201, and the source region 208 can be formed in the sixth portion 2014 of the semiconductor substrate 201. In the transistor structure as shown in FIG. 31 (herein referred to as a first type of transistor structure), the channel region is located in the active region of the semiconductor substrate 201 between the source region 208 and the drain region 209 and is at least partially defined by the trench 204. When the transistor is turned on, an electrically conductive channel will be formed in the channel region that extends at least partially along the oxide layer 206 to connect the source region 208 and the drain region 209. Due to the presence of the trench 204, the length of the electrically conductive channel is increased compared to the lateral (x-direction) distance between the source region 208 and the drain region 209, thereby facilitating the avoidance or amelioration of short channel effects when the transistor is miniaturized (i.e., the lateral distance between the source region 208 and the drain region 209 is shortened).

[0126] Alternatively, in some embodiments, the method 100 can further include forming one of the source region and the drain region in one or both of the fifth portion and the sixth portion of the semiconductor substrate, and forming the other of the source region and the drain region in a seventh portion of the semiconductor substrate below the trench. For example, as shown in FIGS. 3H and 3J, the source region 208 is formed in the fifth portion 2013 and the sixth portion 2014 of the semiconductor substrate 201, and the drain region 209 is formed in the seventh portion 2015 of the semiconductor substrate 201 below the trench 204, by means such as an ion implantation process. Of course, in other embodiments, the drain region 209 can also be formed in the fifth portion 2013 and the sixth portion 2014 of the semiconductor substrate 201, and the source region 208 can be formed in the seventh portion 2015 of the semiconductor substrate 201. In the transistor structure as shown in FIG. 3J (herein referred to as a second type of transistor structure), the channel region is located in the active region of the semiconductor substrate 201 between the source region 208 and the drain region 209 and is at least partially defined by the trench 204. When the transistor is turned on, an electrically conductive channel will be formed in the channel region that extends at least partially along the oxide layer 206 to connect the source region 208 and the drain region 209.

[0127] In addition, respective portions of the semiconductor substrate adjacent to different portions of the trench can be irradiated by respective femtosecond laser beams according to the thickness requirement of the oxide layer in different regions, and the thickness of the oxide layer formed by the respective portions can be controlled by controlling the degree of non-thermal melting of the respective portions.

[0128] Assuming that the femtosecond laser beam used to irradiate the second portion of the semiconductor substrate in step S104 is a first femtosecond laser beam, in some embodiments, the method 100 can further include: before the semiconductor substrate is subjected to the thermal oxidation process, irradiating a fourth portion of the semiconductor substrate adjacent to a third portion (e.g., a side surface) of the trench with a second femtosecond laser beam, so that the fourth portion of the semiconductor substrate undergoes non-thermal melting; after the irradiation of the first femtosecond laser beam and the second femtosecond laser beam is completed, subjecting the semiconductor substrate to the thermal oxidation process, so that the second portion and the fourth portion of the semiconductor substrate form an oxide layer.

[0129] For example, in the case where the oxidation rate of the crystal plane where the first portion of the trench is located is lower than the oxidation rate of the crystal plane where the third portion of the trench is located, the irradiation of the first femtosecond laser beam and the irradiation of the second femtosecond laser beam can be configured so that the depth of the region in the second portion of the semiconductor substrate where non-thermal melting occurs is greater than the depth of the region in the fourth portion of the semiconductor substrate where non-thermal melting occurs. In this way, the thickness of the oxide layer subsequently formed by the second portion of the semiconductor substrate can be close to or even greater than the thickness of the oxide layer formed by the fourth portion of the semiconductor substrate. Specifically, any thickness of the oxide layer formed by the second portion and the fourth portion of the semiconductor substrate, respectively, can be achieved by controlling the laser parameters and the irradiation parameters of the first femtosecond laser beam and the second femtosecond laser beam, respectively, to adjust the degree of non-thermal melting of the second portion and the fourth portion of the semiconductor substrate.

[0130] Referring to FIG. 5, FIG. 5 shows schematic cross-sectional views of a semiconductor device corresponding to respective steps of a non-limiting example process for fabricating the semiconductor device. Although FIG. 5 is described with the aforementioned second type of transistor structure as an example, the teachings can be similarly applied to various transistor structures such as the aforementioned first type of transistor structure or other semiconductor device structures. As shown in (a)-(d) of FIG. 5, a trench is formed in a semiconductor substrate by a method as previously mentioned. As shown in (e) of FIG. 5, a second portion of the semiconductor substrate that is contiguous to a bottom surface of the trench is irradiated with a first femtosecond laser beam 2051 to cause non-thermal melting thereof. As shown in (f) of FIG. 5, a fourth portion of the semiconductor substrate that is contiguous to a side surface of the trench is irradiated with a second femtosecond laser beam 2052 to cause non-thermal melting thereof. It can be appreciated that although the irradiation of the first femtosecond laser beam 2051 and the second femtosecond laser beam 2052 are respectively described in (f) and (g) of FIG. 5, the irradiation of the second femtosecond laser beam 2051 can be at least partially parallel or serial with the irradiation of the first femtosecond laser beam 2051. Specifically, the irradiation of the first femtosecond laser beam 2051 and the irradiation of the second femtosecond laser beam 2052 are configured such that a depth of a region in the second portion of the semiconductor substrate where non-thermal melting occurs is greater than a depth of a region in the fourth portion of the semiconductor substrate where non-thermal melting occurs. For example, the configuration of the first femtosecond laser beam 2051 and the second femtosecond laser beam 2052 can satisfy one or more of the following: a duration of the irradiation of the first femtosecond laser beam 2051 is greater than a duration of the irradiation of the second femtosecond laser beam 2052; an intensity of the first femtosecond laser beam 2051 is greater than an intensity of the second femtosecond laser beam 2052 (e.g., in a case where the first femtosecond laser beam 2051 and the second femtosecond laser beam 2052 are both pulsed laser beams and have a same pulse width, an energy density of the first femtosecond laser beam 2051 is greater than an energy density of the second femtosecond laser beam 2052); the first femtosecond laser beam 2051 and the second femtosecond laser beam 2052 are pulsed, and a pulse frequency of the first femtosecond laser beam 2051 is greater than a pulse frequency of the second femtosecond laser beam 2052; and / or the like. As shown in (g) of FIG. 5, after the irradiation of the first femtosecond laser beam 2051 and the second femtosecond laser beam 2052 is completed, the hard mask layer can be removed. Then, as shown in (h) of FIG. 5, a thermal oxidation process is performed on the semiconductor substrate such that an oxide layer formed from the second portion of the semiconductor substrate has a thickness dl that is greater than an oxide layer formed from the fourth portion of the semiconductor substrate has a thickness d3. Additionally, it can be appreciated that since the fourth portion of the semiconductor substrate is irradiated by the second femtosecond laser beam 2052 in FIG. 5, the oxide layer formed from the fourth portion of the semiconductor substrate at this time has a thickness d3 that is greater than the oxide layer formed from the fourth portion of the semiconductor substrate that is not irradiated by the femtosecond laser beam shown in FIG. 3G has a thickness d2. With continued reference to FIG. 5, as shown in (h) of FIG. 5, a gate, a source region, and a drain region can also be further prepared to form the second type of transistor structure.

[0131] In some embodiments, the method 100 further comprises: performing a pull-back process on the hard mask layer before the thermal oxidation process on the semiconductor substrate, to expose one or both of the fifth portion and the sixth portion of the semiconductor substrate respectively located at two sides of the top of the trench; irradiating the one or both of the fifth portion and the sixth portion of the semiconductor substrate with a third femtosecond laser beam, such that non-thermal melting occurs in the one or both of the fifth portion and the sixth portion of the semiconductor substrate; and after the irradiation of the first femtosecond laser beam and the third femtosecond laser beam is completed, performing the thermal oxidation process on the semiconductor substrate, such that the second portion of the semiconductor substrate and the one or both of the fifth portion and the sixth portion form an oxide layer. Additionally, in some embodiments, the third femtosecond laser beam is the same as the first femtosecond laser beam. The irradiation of the third femtosecond laser beam can be at least partially in parallel or in series with the irradiation of the first femtosecond laser beam (and the irradiation of the second femtosecond laser beam, if any). Illustratively, the irradiation of the first femtosecond laser beam and the irradiation of the third femtosecond laser beam are configured such that the depth of the region in which non-thermal melting occurs in the second portion of the semiconductor substrate is equal to the depth of the region in which non-thermal melting occurs in the one or both of the fifth portion and the sixth portion of the semiconductor substrate. Of course, any thickness of the oxide layer to be formed by the second portion of the semiconductor substrate and the one or both of the fifth portion and the sixth portion of the semiconductor substrate, respectively, can be achieved by controlling the laser parameters and the irradiation parameters of the first femtosecond laser beam and the third femtosecond laser beam, respectively, to adjust the degree of non-thermal melting of the second portion of the semiconductor substrate and the one or both of the fifth portion and the sixth portion of the semiconductor substrate.

[0132] Referring to FIG. 6, FIG. 6 shows schematic cross-sectional views of a semiconductor device corresponding to respective steps of a non-limiting example process for fabricating the semiconductor device. Although FIG. 6 is described by way of example with the first-type transistor structure and the second-type transistor structure described above, the teachings thereof can be similarly applied to various other transistor structures or other semiconductor device structures. As shown in (a) to (d) of FIG. 6, the trench 204 is formed in the semiconductor substrate by the method as mentioned above, and the second portion of the semiconductor substrate adjacent to the bottom surface of the trench is irradiated with the first femtosecond laser beam 2051. As shown in (e) of FIG. 6, a pullback process is performed on the hard mask layer to expose the fifth portion and the sixth portion of the semiconductor substrate respectively located on both sides of the top of the trench. As shown in (f) of FIG. 6, the fifth portion and the sixth portion of the semiconductor substrate are irradiated with the third femtosecond laser beam 2053 which is the same as the first femtosecond laser beam 2051 to cause non-thermal melting thereof. It can be appreciated that although the irradiation processes of the first femtosecond laser beam 2051 and the third femtosecond laser beam 2053 are respectively described in (d) and (f) of FIG. 6, the irradiation of the third femtosecond laser beam 2053 can be at least partially parallel or serial to the irradiation of the first femtosecond laser beam 2051. As shown in (g) of FIG. 6, after the irradiation of the first femtosecond laser beam 2051 and the third femtosecond laser beam 2053 is completed, the hard mask layer is removed. Then, as shown in (h) of FIG. 6, a thermal oxidation process is performed on the semiconductor substrate such that the thickness d4 of the oxide layer formed on the fifth portion and the sixth portion of the semiconductor substrate is substantially equal to the thickness d1 of the oxide layer formed on the second portion 2011 of the semiconductor substrate 201, and is greater than the thickness d5 of the oxide layer formed on the horizontal surface of the semiconductor substrate which is not irradiated by the first femtosecond laser beam 2051 and the third femtosecond laser beam 2053 under the hard mask layer before, and is also greater than the thickness d3 of the oxide layer formed on the vertical surface of the semiconductor substrate which is not subjected to the femtosecond laser process. By providing thick oxide layers at both the corners of the top of the trench and the bottom of the trench, the blocking voltage of the semiconductor device can be further improved, and the electrical performance can be improved.

[0133] Further, the oxide layer formed in (h) of FIG. 6 can be utilized as a gate oxide layer to form transistor structures such as the first type transistor structure and the second type transistor structure as previously described. For example, as shown in (il) of FIG. 6, a gate is formed over the oxide layer in the trench of the semiconductor substrate, one of a source region and a drain region is formed in the eighth portion of the semiconductor substrate at a side of the fifth portion distal to the trench and in the ninth portion of the semiconductor substrate at a side of the sixth portion distal to the trench, and the other of the source region and the drain region is formed in the seventh portion of the semiconductor substrate below the trench. Alternatively, as shown in (i2) of FIG. 6, a gate is formed over the oxide layer in the trench of the semiconductor substrate, one of a source region and a drain region is formed in the eighth portion of the semiconductor substrate, and the other of the source region and the drain region is formed in the ninth portion of the semiconductor substrate. The transistor structures as shown in (il), (i2) of FIG. 6 can achieve further extended conductive channel length compared to the transistor structures as shown in FIG. 3J, FIG. 31, respectively.

[0134] The present disclosure also provides, in another aspect, a semiconductor device manufactured according to the method of any of the embodiments of the present disclosure. In some embodiments, the semiconductor device comprises a MOSFET, wherein the oxide layer is configured to provide a gate oxide layer of the MOSFET. The semiconductor device manufactured according to the teachings of the present disclosure has an oxide layer with high reliability, and thus improved electrical performance.

[0135] The words "left," "right," "front," "back," "top," "bottom," "over," "under," "upper," "lower," and the like in the description and the claims, if any, are used for descriptive purposes and not necessarily for describing permanent relative positions. It is to be understood that the use of such terms can be interchanged in the context of the disclosure, such that an embodiment described herein, for example, can operate in other orientations than described or otherwise depicted in the figures. For example, if the device is inverted, a feature that was originally described as above other features can now be described as below other features. The device can also be oriented in other ways (rotated 90 degrees or in other orientations), and the relative spatial relationships will be interpreted accordingly.

[0136] In the description and claims, the terms "on", "attached to", "connected to", "coupled to", or "in contact with" one element to another element, among others, can mean the element is either directly on, directly attached to, directly connected to, directly coupled to, or directly in contact with the other element or one or more intervening elements can also be present. In contrast, the terms "directly on", "directly attached to", "directly connected to", "directly coupled to", or "directly in contact with" one element to another element mean that there are no intervening elements present. In the description and claims, one feature being arranged "adjacent" to another feature can mean that the feature has a portion that overlaps with the adjacent feature or a portion that is above or below the adjacent feature.

[0137] As used herein, the word "exemplary" means "serving as an example, instance, or illustration," and not "preferred" or "advantageous over other implementations." In addition, the disclosure is not limited to the

[0138] As used herein, the word "substantially" means including any minor variations as a result of design, manufacturing, tolerances, environmental impacts, and / or other factors. The word "substantially" also allows for differences between a perfect or ideal situation and a real-world situation.

[0139] In addition, the terms "first", "second", and similar terms can also be used herein, merely for purposes of reference and thus do not necessarily have to comply with the chronological or chronological order of the objects or elements they refer to, unless explicitly stated otherwise.

[0140] It will also be understood that, although the terms "first", "second", etc. can be used herein to describe various elements, these elements should not be limited by these terms since such terms are also used to describe one element from another. For example, unless otherwise specified, a first element can be termed a second element, and, similarly, a second element can also be termed a first element without departing from the teachings of the present disclosure.

[0141] In the present disclosure, the term "providing" is used in a broad sense to cover all ways of obtaining an object, and thus "providing an object" includes, but is not limited to, "buying", "preparing / manufacturing", "arranging / setting", "installing / fitting", and / or "ordering" the object, etc.

[0142] As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.

[0143] Those skilled in the art will realize that the boundaries between the above described operations merely illustrative. The multiple operations can be combined into a single operation, a single operation can be distributed in additional operations and operations can be executed at least partially overlapping in time. Moreover, alternative embodiments can include a number of instances of a particular operation, and the order of the operations can be altered in other various embodiments. However, other modifications, variations, and alternatives are also possible. The aspects and elements of all such embodiments can be combined in any manner and / or combination with one another and with other aspects or elements of other embodiments, to provide additional embodiments within the scope of the present disclosure. Thus, the present specification and figures are to be regarded as illustrative in nature and not as restrictive.

[0144] While certain embodiments of the disclosure have been described herein, other embodiments will be apparent to those skilled in the art from consideration of the specification and practice of the disclosure. Therefore, the disclosure is not limited to the specific disclosed embodiments, but encompasses all such embodiments consistent with the following claims. Various modifications and changes can be made thereto by those skilled in the art which further fall within the scope and spirit of the disclosure, without departing from the latter. The disclosure is not to be limited, in terms of either scope or application, by the embodiments described, which are intended for the purposes of exemplification thereof only. The embodiments are to cover all modifications and alternatives within the scope and spirit of the disclosure. The scope of the disclosure is to be indicated by the appended claims, rather than the foregoing description, and all changes that come within the meaning and range of equivalents are intended to be embraced therein.

Claims

1. A method for manufacturing a semiconductor device, the method comprising: providing a semiconductor substrate having a trench formed therein; irradiating a second portion of the semiconductor substrate that is contiguous with a first portion of the trench with a femtosecond laser beam such that the second portion of the semiconductor substrate undergoes non-thermal melting; and after completion of the irradiation of the femtosecond laser beam, subjecting the semiconductor substrate to a thermal oxidation process such that the second portion of the semiconductor substrate forms an oxide layer.

2. The method of claim 1, wherein, An oxidation rate of a crystal plane in which the first portion of the trench is located is lower than an oxidation rate of a crystal plane in which a third portion of the trench that is different from the first portion is located in an intact crystal structure of the semiconductor substrate.

3. The method of claim 2, wherein, The femtosecond laser beam is a first femtosecond laser beam, and the method further comprises: before subjecting the semiconductor substrate to the thermal oxidation process, irradiating a fourth portion of the semiconductor substrate that is contiguous with the third portion of the trench with a second femtosecond laser beam such that the fourth portion of the semiconductor substrate undergoes non-thermal melting; after completion of the irradiation of the first femtosecond laser beam and the second femtosecond laser beam, subjecting the semiconductor substrate to the thermal oxidation process such that the second portion and the fourth portion of the semiconductor substrate form an oxide layer, wherein the irradiation of the first femtosecond laser beam and the irradiation of the second femtosecond laser beam are configured such that a depth of a region in which non-thermal melting occurs in the second portion of the semiconductor substrate is greater than a depth of a region in which non-thermal melting occurs in the fourth portion of the semiconductor substrate.

4. The method of claim 3, wherein, At least one of the following is satisfied: an irradiation duration of the first femtosecond laser beam is greater than an irradiation duration of the second femtosecond laser beam; or an intensity of the first femtosecond laser beam is greater than an intensity of the second femtosecond laser beam; or the first femtosecond laser beam and the second femtosecond laser beam are irradiated in a pulsed form, and a pulse frequency of the first femtosecond laser beam is greater than a pulse frequency of the second femtosecond laser beam.

5. The method of claim 2, wherein, The first portion of the trench is a bottom surface of the trench, and the third portion of the trench is a side surface of the trench.

6. The method of claim 1, wherein, The semiconductor substrate comprises silicon carbide.

7. The method of claim 1, wherein, A ratio of a non-thermal melting process energy contribution of the second portion of the semiconductor substrate to a thermal melting process energy contribution of the second portion of the semiconductor substrate exceeds a preset ratio during the irradiation of the femtosecond laser beam.

8. The method of claim 7, wherein, The preset ratio is determined based on a value of the ratio of the non-thermal melting process energy contribution to the thermal melting process energy contribution at a maximum slope of a trend of the ratio with respect to a change in a laser parameter of the femtosecond laser beam.

9. The method of claim 1, wherein, The laser parameter of the femtosecond laser beam is configured to be not less than a first laser parameter threshold at which the second portion of the semiconductor substrate starts to melt.

10. The method of claim 9, wherein, The laser parameter of the femtosecond laser beam is configured to be not greater than a second laser parameter threshold at which the second portion of the semiconductor substrate is completely melted.

11. The method of claim 10, wherein, The laser parameters of the femtosecond laser beam are set based on a relationship of a desired thickness of an oxide layer to be formed from the second portion of the semiconductor substrate relative to a first reference thickness and a second reference thickness, the first reference thickness being a thickness of an oxide layer to be formed from the second portion of the semiconductor substrate if the femtosecond laser beam is irradiated with the first laser parameter threshold, the second reference thickness being a thickness of an oxide layer to be formed from the second portion of the semiconductor substrate if the femtosecond laser beam is irradiated with the second laser parameter threshold.

12. The method of any one of claims 8-11, wherein, The laser parameters of the femtosecond laser beam include intensity, wavelength, or a combination thereof.

13. The method of claim 1, wherein, Irradiating the second portion of the semiconductor substrate with the femtosecond laser beam includes irradiating the second portion of the semiconductor substrate with the femtosecond laser beam in a pulsed form.

14. The method of claim 13, wherein, A pulse width of the femtosecond laser beam is set to be between 50 fs and 150 fs.

15. The method of claim 13, wherein, A pulse frequency of the femtosecond laser beam is configured such that non-thermal melting of the second portion of the semiconductor substrate occurs continuously.

16. The method of claim 13, wherein, The pulse frequency of the femtosecond laser beam is set to be greater than 1 MHz.

17. The method of claim 1, wherein, The femtosecond laser beam is configured to be irradiated in a direction parallel to a depth direction of the trench, and an irradiation area of the femtosecond laser beam is configured to cover the trench in a width direction of the trench.

18. The method of claim 1, wherein, Irradiating the second portion of the semiconductor substrate with the femtosecond laser beam includes causing a single femtosecond laser beam or a plurality of femtosecond laser beams to scan the second portion of the semiconductor substrate in a scanning direction parallel to a length direction of the trench.

19. The method of claim 18, wherein, when causing a single femtosecond laser beam to scan the second portion of the semiconductor substrate in the scanning direction, a previous irradiation area and a next irradiation area of the single femtosecond laser beam partially overlap with each other in the scanning direction; or when causing a plurality of femtosecond laser beams to scan the second portion of the semiconductor substrate in the scanning direction, irradiation areas of each adjacent two of the plurality of femtosecond laser beams partially overlap with each other in the scanning direction.

20. The method of claim 1, further comprising forming a gate electrode over the oxide layer.

21. The method of claim 20, further comprising: forming one of a source region and a drain region in a fifth portion of the semiconductor substrate at one side of a top of the trench, and forming the other of the source region and the drain region in a sixth portion of the semiconductor substrate at the other side of the top of the trench; or forming one of a source region and a drain region in one or both of the fifth portion and the sixth portion of the semiconductor substrate, and forming the other of the source region and the drain region in a seventh portion of the semiconductor substrate below the trench.

22. The method of claim 1, wherein, Providing a semiconductor substrate having a trench formed therein includes: forming a hard mask layer on a semiconductor substrate; forming a photoresist pattern on the hard mask layer to etch the hard mask layer and the semiconductor substrate to form a trench in the semiconductor substrate, wherein the femtosecond laser beam is a first femtosecond laser beam, the method further comprising: performing a pullback process on the hard mask layer to expose one or both of a fifth portion and a sixth portion of the semiconductor substrate located on either side of a top portion of the trench prior to performing a thermal oxidation process on the semiconductor substrate; irradiating the one or both of the fifth portion and the sixth portion of the semiconductor substrate with a third femtosecond laser beam such that non-thermal melting occurs in the one or both of the fifth portion and the sixth portion of the semiconductor substrate; and performing a thermal oxidation process on the semiconductor substrate after the irradiation of the first femtosecond laser beam and the third femtosecond laser beam are completed such that the second portion of the semiconductor substrate and the one or both of the fifth portion and the sixth portion form an oxide layer.

23. The method of claim 22, wherein, the irradiation of the first femtosecond laser beam and the irradiation of the third femtosecond laser beam are configured such that a depth of a region in which non-thermal melting occurs in the second portion of the semiconductor substrate is equal to a depth of a region in which non-thermal melting occurs in the one or both of the fifth portion and the sixth portion of the semiconductor substrate.

24. The method of claim 22, wherein, the method further comprising forming a gate electrode over the oxide layer, and wherein the method further comprises: forming one of a source region and a drain region in an eighth portion of the semiconductor substrate located at a side of the fifth portion distal to the trench and forming the other of the source region and the drain region in a ninth portion of the semiconductor substrate located at a side of the sixth portion distal to the trench; or forming one of a source region and a drain region in one or both of the eighth portion and the ninth portion of the semiconductor substrate and forming the other of the source region and the drain region in a seventh portion of the semiconductor substrate located below the trench.

25. A semiconductor device manufactured by the method of any one of claims 1 to 24. ​

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