Timing controller, display device and adjustment method and apparatus therefor, and storage medium

Abstract

The present application belongs to the technical field of displays. Disclosed are a timing controller, a display device and an adjustment method and apparatus therefor, and a storage medium. The timing controller comprises: a built-in image generation module and a data selection module, wherein the data selection module is used for stopping, when the level of a first frame synchronization signal jumps from a first level to a second level, sending a first video signal to a display panel, and sending a second video signal to the display panel when the level of a second frame synchronization signal jumps from a third level to a fourth level, such that the display panel performs power-off compensation on the basis of the second video signal. In this way, the timing controller can start signal switching at an end moment of a video signal frame of a first video signal output by a main board, and complete the signal switching at a start moment of a video signal frame of a second video signal generated by the timing controller.

Description

Timing controller, display device and adjustment method and device thereof and storage medium

[0001] The present application claims priority to the Chinese patent application No. 202410544225.7, filed on April 29, 2024, and entitled "Timing controller, display device and adjustment method and device thereof and storage medium", the entire content of which is incorporated herein by reference. TECHNICAL FIELD

[0002] The present application relates to the technical field of display, in particular to a timing controller, a display device and an adjustment method and device thereof and a storage medium. BACKGROUND

[0003] An organic light emitting diode (OLED) display panel has good color saturation, contrast and response speed.

[0004] A timing controller is used for a display device, the display device comprising a display panel, a timing controller and a mainboard, the timing controller being configured to receive a first video signal sent by the mainboard, decode the first video signal and send the decoded first video signal to the display panel, so that the display panel displays a picture, or perform shutdown compensation based on the first video signal, the shutdown compensation being a compensation on a threshold voltage of a driving transistor on the display panel.

[0005] However, the stability of the first video signal is low, resulting in poor compensation effect of the display panel. SUMMARY

[0006] Embodiments of the present application provide a timing controller, a display device and an adjustment method and device thereof and a storage medium. The technical solution is as follows:

[0007] According to an aspect of the present application, a timing controller is provided for a display device, the display device comprising a display panel and a mainboard, the timing controller being electrically connected to the display panel and the mainboard respectively, the timing controller comprising a built-in image generation module and a data selection module, the mainboard being configured to send a first video signal to the data selection module and send a shutdown compensation signal to the built-in image generation module and the data selection module;

[0008] The built-in image generation module is electrically connected to the data selection module, and the built-in image generation module is configured to generate a second video signal after receiving the shutdown compensation signal and send the second video signal to the data selection module, the second video signal comprising a second frame synchronization signal;

[0009] The data selection module is electrically connected with the display panel, and is configured to, after receiving the shutdown compensation signal, send the first video signal to the display panel, the first video signal comprising a first frame synchronization signal, so that the display panel displays a picture based on the first video signal.

[0010] The data selection module is further configured to, when a level of the first frame synchronization signal jumps from a first level to a second level, stop sending the first video signal to the display panel, and when a level of the second frame synchronization signal jumps from a third level to a fourth level, send the second video signal to the display panel, so that the display panel performs shutdown compensation based on the second video signal.

[0011] Optionally, the first video signal further comprises a first data enable signal, the first data enable signal comprising a blanking area and an active area arranged alternately, and the display panel comprises a driving transistor.

[0012] The timing controller further comprises a compensation conversion module electrically connected with the data selection module, the compensation conversion module having a real-time detection mode, and the compensation conversion module is configured to, in the real-time detection mode, send a real-time detection signal to the display panel, the real-time detection signal being used to instruct the display panel to detect a mobility of the driving transistor.

[0013] The data selection module is further configured to, when sending the first video signal, detect whether a first data enable signal in the first video signal is in the active area, and send a data valid signal to the compensation conversion module when the first data enable signal is in the active area.

[0014] The compensation conversion module is configured to, based on the data valid signal, close the real-time detection mode to stop sending the real-time detection signal to the display panel.

[0015] Optionally, the built-in image generation module is configured to, when receiving the shutdown compensation signal, immediately generate the second video signal.

[0016] The first frame synchronization signal jumps from the first level to the second level at a first time, and the second frame synchronization signal jumps from the third level to the fourth level at a second time, and the first time and the second time have a first time length.

[0017] Optionally, the data selection module is further configured to, when the level of the first frame synchronization signal jumps from the first level to the second level, send an opening signal to the built-in image generation module.

[0018] The built-in image generation module is configured to generate the second video signal immediately upon receiving the start signal.

[0019] The level of the first frame synchronization signal jumps from the first level to the second level at the same time as the level of the second frame synchronization signal jumps from the third level to the fourth level.

[0020] Optionally, the data selection module comprises a comparison module and a gating module, and the comparison module is electrically connected to the mainboard and the gating module, respectively.

[0021] The comparison module is configured to generate a first indication signal and output the first indication signal to the gating module when the level of the first frame synchronization signal of the first video signal output by the mainboard reaches the second level.

[0022] The gating module is configured to stop sending the first video signal to the display panel based on the first indication signal.

[0023] Optionally, the data selection module comprises a comparison module and a gating module, and the comparison module is electrically connected to the built-in image generation module and the gating module, respectively.

[0024] The comparison module is configured to generate a second indication signal and output the second indication signal to the gating module when the level of the second frame synchronization signal of the second video signal output by the built-in image generation module reaches the fourth level.

[0025] The gating module is configured to send the second video signal to the display panel based on the second indication signal.

[0026] Optionally, the display device further comprises a memory electrically connected to the timing controller, and the memory is configured to output a compensation completion signal, wherein the compensation completion signal is a signal generated by the memory upon receiving a first detection value sent by the display panel, and the first detection value is a first detection value obtained by the display panel during the power-off compensation.

[0027] The data selection module is further configured to send the second video signal to the display panel after receiving the compensation completion signal.

[0028] The data selection module is further configured to stop sending the second video signal to the display panel when the level of the second frame synchronization signal jumps from the third level to the fourth level, and send the first video signal to the display panel when the level of the first frame synchronization signal jumps from the first level to the second level.

[0029] Optionally, the first video signal further comprises a first data enable signal, the first data enable signal comprises blanking areas and active areas arranged alternately, and the display panel comprises a driving transistor;

[0030] The timing controller further comprises a compensation conversion module, which is electrically connected with the data selection module, and has a real-time detection mode, and is configured to send a real-time detection signal to the display panel in the real-time detection mode, so as to instruct the display panel to detect the mobility of the driving transistor.

[0031] The data selection module is further configured to detect whether the first data enable signal in the first video signal is in the active area when the first video signal is being sent, and send a data valid signal to the compensation conversion module when the first data enable signal is in the active area.

[0032] The compensation conversion module is configured to start the real-time detection mode based on the data valid signal, so as to be able to send the real-time detection signal to the display panel.

[0033] Optionally, the second video signal comprises a first black screen signal and a third video signal.

[0034] The data selection module is further configured to send the first black screen signal to the display panel when the level of the second frame synchronization signal jumps from the third level to the fourth level, the first black screen signal having a second time length, so that the display panel displays a black screen for the second time length.

[0035] The data selection module is further configured to send the third video signal to the display panel after sending the first black screen signal to the display panel, so that the display panel performs shutdown compensation based on the third video signal.

[0036] Optionally, the second video signal further comprises a second black screen signal.

[0037] The data selection module is further configured to send the second black screen signal to the display panel when the compensation completion signal is received, the second black screen signal having a second time length, so that the display panel displays a black screen for the second time length.

[0038] Optionally, the first video signal further comprises a third black screen signal.

[0039] The data selection module is further configured to send the third black screen signal to the display panel when the shutdown compensation signal is received, the third black screen signal having a second time length, so that the display panel displays a black screen for the second time length.

[0040] Optionally, the second time length is N frame display time lengths, and N is an integer greater than or equal to 1.

[0041] According to another aspect of the present application, there is provided a display device adjustment method applied to the timing controller described above, the method comprising:

[0042] receiving the first video signal and the shutdown compensation signal sent by the mainboard, the first video signal comprising a first frame synchronization signal;

[0043] based on the shutdown compensation signal, sending the first video signal to the display panel, so that the display panel displays a picture based on the first video signal, and generating a second video signal, the second video signal comprising a second frame synchronization signal;

[0044] stopping sending the first video signal to the display panel when the level of the first frame synchronization signal jumps from a first level to a second level;

[0045] based on the shutdown compensation signal, sending the first video signal to the display panel, so that the display panel displays a picture based on the first video signal, and generating a second video signal, the second video signal comprising a second frame synchronization signal;

[0046] Optionally, the first video signal further comprises a first data enable signal, the first data enable signal comprising alternatingly arranged blanking areas and active areas, the display panel comprising a driving transistor, and the compensation conversion module having a real-time detection mode.

[0047] Before stopping sending the first video signal to the display panel, the method further comprises:

[0048] sending a real-time detection signal to the display panel, the real-time detection signal being used to instruct the display panel to detect the mobility of the driving transistor;

[0049] detecting whether the first data enable signal in the first video signal is in an active area;

[0050] in response to the first data enable signal being in the active area, closing the real-time detection mode to stop sending the real-time detection signal to the display panel.

[0051] Optionally, based on the shutdown compensation signal, generating a second video signal comprises:

[0052] generating the second video signal immediately after receiving the shutdown compensation signal;

[0053] wherein a time length between a time when the level of the first frame synchronization signal jumps from the first level to the second level and a time when the level of the second frame synchronization signal jumps from the third level to the fourth level is the first time length.

[0054] Optionally, generating the second video signal based on the shutdown compensation signal comprises:

[0055] generating the second video signal immediately after the level of the first frame synchronization signal jumps from the first level to the second level;

[0056] wherein the time when the level of the first frame synchronization signal jumps from the first level to the second level coincides with the time when the level of the second frame synchronization signal jumps from the third level to the fourth level.

[0057] According to another aspect of the present application, a display device is provided, comprising a main board, a display panel and a timing controller, the timing controller being electrically connected to the display panel and the main board respectively, and the timing controller being the timing controller as described above.

[0058] According to another aspect of the present application, an adjusting apparatus of a display device is provided, the adjusting apparatus of the display device comprising a processor and a memory, the memory storing at least one instruction, at least one program, a code set or an instruction set, the at least one instruction, the at least one program, the code set or the instruction set being loaded and executed by the processor to implement the adjusting method of the display device as described above.

[0059] According to another aspect of the present application, a computer storage medium is provided, the computer storage medium storing at least one instruction, at least one program, a code set or an instruction set, the at least one instruction, the at least one program, the code set or the instruction set being loaded and executed by a processor to implement the adjusting method of the display device as described above.

[0060] According to another aspect of the present application, a computer program product or a computer program is provided, the computer program product or the computer program comprising computer instructions stored in a computer readable storage medium. A processor of a computer device reads the computer instructions from the computer readable storage medium, and the processor executes the computer instructions to cause the computer device to perform the adjusting method of the display device as described above.

[0061] The technical solutions provided by the embodiments of the present application have at least the following beneficial effects:

[0062] A timing controller including a built-in image generation module and a data selection module is provided. The data selection module is configured to stop sending a first video signal to a display panel when a level of a first frame synchronization signal jumps from a first level to a second level, and start sending a second video signal to the display panel when a level of a second frame synchronization signal jumps from a third level to a fourth level, so that the display panel performs shutdown compensation based on the second video signal. In this way, the timing controller can start signal switching at an end time of a frame of the first video signal output by a mainboard, and complete signal switching at a start time of a frame of the second video signal generated by the timing controller. During signal switching, the timing controller sends a complete frame of video signal to the display panel, so that the display panel does not work abnormally due to incomplete frame of video signal input to the display panel caused by signal switching. Moreover, the video source of the display panel is switched to the second video signal generated by the built-in image generation module, so that shutdown compensation can be performed normally. The compensation effect of the display panel can be improved, and the compensation effect of the display panel can be improved. BRIEF DESCRIPTION OF DRAWINGS

[0063] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed in the embodiment description will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative labor.

[0064] FIG. 1 is a structural schematic diagram of a display device according to an embodiment of the present application;

[0065] FIG. 2 is a signal switching timing diagram of a timing controller according to an embodiment of the present application;

[0066] FIG. 3 is a structural schematic diagram of another display device according to an embodiment of the present application;

[0067] FIG. 4 is a structural schematic diagram of a pixel circuit according to an embodiment of the present application;

[0068] FIG. 5 is a threshold voltage detection schematic diagram according to an embodiment of the present application;

[0069] FIG. 6 is a signal switching flowchart;

[0070] FIG. 7 is a signal switching timing diagram;

[0071] FIG. 8 is another signal switching timing diagram;

[0072] FIG. 9 is a signal switching timing diagram of another timing controller according to an embodiment of the present application;

[0073] FIG. 10 is a signal switching timing diagram of another timing controller according to an embodiment of the present application;

[0074] FIG. 11 is a structural diagram of a detection compensation circuit according to an embodiment of the present application;

[0075] FIG. 12 is a signal switching flow chart according to an embodiment of the present application;

[0076] FIG. 13 is another signal switching flow chart according to an embodiment of the present application;

[0077] FIG. 14 is another signal switching flow chart according to an embodiment of the present application;

[0078] FIG. 15 is a flow chart of an adjusting method of a display device according to an embodiment of the present application;

[0079] FIG. 16 is a flow chart of another adjusting method of a display device according to an embodiment of the present application.

[0080] The above-mentioned figures have shown the explicit embodiments of the present application, which will be described in more details hereinafter. These figures and the written description are not intended to limit the scope of the present application in any way, but to illustrate the concept of the present application to those skilled in the art by referring to specific embodiments. DETAILED DESCRIPTION

[0081] In order to make the purpose, technical solutions and advantages of the present application more clear, the embodiments of the present application will be described in more details hereinafter by referring to the figures.

[0082] Please refer to FIG. 1, a display device can include a display panel 11, a main board 12 and a timing controller 13 (English: Timing Controller; abbreviation: TCON), wherein the timing controller 13 is electrically connected with the display panel 11 and the main board 12 respectively, the timing controller 13 can include a built-in image generation module 131 and a data selection module 132, the main board 12 can be used to send a first video signal to the data selection module 132, and send a shutdown compensation signal to the built-in image generation module 131 and the data selection module 132.

[0083] The built-in image generation module 131 can be electrically connected with the data selection module 132, and the built-in image generation module 131 is configured to generate a second video signal after receiving the shutdown compensation signal, and send the second video signal to the data selection module 132, the second video signal comprising a second frame synchronization signal (English: Vertical Sync 2; abbreviation: VS2). The stability of the second video signal is stronger than that of the first video signal, that is, the second video signal is more stable than the first video signal, which can make the shutdown compensation effect of the display panel 11 better.

[0084] The data selection module 132 can be electrically connected with the display panel 11, and the data selection module 132 can receive the first video signal and the shutdown compensation signal output by the mainboard 12. The data selection module 132 is configured to send the first video signal to the display panel 11 after receiving the shutdown compensation signal, and the first video signal comprises a first frame synchronization signal (English: Vertical Sync 1; abbreviation: VS1), so that the display panel 11 displays a picture based on the first video signal.

[0085] Please refer to FIG. 2, the data selection module 132 is further configured to stop sending the first video signal to the display panel 11 when the level of the first frame synchronization signal VS1 jumps from the first level to the second level (t2), and send the second video signal to the display panel 11 when the level of the second frame synchronization signal VS2 jumps from the third level to the fourth level (t3), so that the display panel 11 performs shutdown compensation based on the second video signal. The actual VS signal in FIG. 2 represents the frame synchronization signal in the video signal actually sent by the timing controller 13 to the display panel 11.

[0086] The first video signal comprises a plurality of video signals, and when the level of the first frame synchronization signal VS1 jumps from the first level to the second level, it can represent that one frame of video signal in the first video signal ends, or it can represent that another frame of video signal in the first video signal starts, that is, the jump of the level can be regarded as a division point of two frames of video signals in the first video signal. Similarly, the second video signal comprises a plurality of video signals, and when the level of the second frame synchronization signal VS2 jumps from the third level to the fourth level, it can represent that one frame of video signal in the second video signal ends, or it can represent that another frame of video signal in the second video signal starts, that is, the jump of the level can be regarded as a division point of two frames of video signals in the second video signal.

[0087] If the timing controller 13 directly switches the signal being transmitted in the process of switching the first video signal to the second video signal, a frame of the first video signal can not be completely transmitted at the moment of signal switching, that is, only part of the frame of the first video signal is transmitted to the display panel 11, and a frame of the second video signal is transmitted from the middle, that is, only part of the frame of the second video signal is transmitted to the display panel 11. The two parts of the signal will be combined into a frame of video signal, so that the amount of data of a frame of video signal received by the display panel 11 at the moment of signal switching is more or less than that of a frame of video signal of the second video signal, which will cause the display panel 11 to receive abnormal video signal, so that the display panel 11 works disorderly and affects the compensation effect of the display panel 11 in the power-off compensation.

[0088] Therefore, in the embodiment of the present application, the timing controller 13 can start signal switching at the end of a frame of the first video signal output by the mainboard 12 and complete signal switching at the beginning of a frame of the second video signal generated by the timing controller 13 after receiving the power-off compensation instruction. In the process of signal switching, the timing controller 13 transmits a complete frame of video signal to the display panel 11, which can avoid the problem of abnormal working of the display panel 11 caused by the incomplete frame of video signal input into the display panel 11 due to signal switching. Moreover, switching the video source of the display panel 11 to the second video signal with strong stability generated by the built-in image generation module 131 can ensure that the power-off compensation can be normally performed.

[0089] In summary, the embodiment of the present application provides a timing controller including a built-in image generation module and a data selection module. The data selection module is configured to stop sending a first video signal to a display panel when a level of a first frame synchronization signal jumps from a first level to a second level, and start sending a second video signal to the display panel when a level of a second frame synchronization signal jumps from a third level to a fourth level, so that the display panel performs shutdown compensation based on the second video signal. In this way, the timing controller can start signal switching at an end time of a frame of video signal of the first video signal output by the mainboard, and complete signal switching at a start time of a frame of video signal of the second video signal generated by the timing controller. During signal switching, the timing controller sends a complete frame of video signal to the display panel, which can avoid the problem of abnormal operation of the display panel caused by incomplete frame of video signal input into the display panel due to signal switching. Moreover, the video source of the display panel can be switched to the second video signal generated by the built-in image generation module, which has strong stability, so that the shutdown compensation can be performed normally. The problem of poor compensation effect of the display panel in the related art can be solved, and the compensation effect of the display panel can be improved.

[0090] It should be noted that the first level and the second level in the embodiment of the present application can be two levels with different amplitudes, and the third level and the fourth level can be two levels with different amplitudes, and the embodiment of the present application does not limit the specific amplitudes of the first level, the second level, the third level and the fourth level.

[0091] It can be understood that before receiving the shutdown compensation signal, the data selection module 132 can receive the first video signal output by the mainboard 12, and send the first video signal to the display panel 11, so that the display panel 11 displays a picture based on the first video signal. After the data selection module 132 receives the shutdown compensation signal, the data selection module 132 will not immediately perform signal switching, and will still receive the first video signal output by the mainboard 12, and send the received first video signal to the display panel 11, until the level of the first frame synchronization signal VS1 in the first video signal jumps from the first level to the second level, and then stop sending the first video signal to the display panel 11.

[0092] The display panel 11 can include a driving transistor, and the shutdown compensation in the embodiment of the present application is to detect a threshold voltage of the driving transistor of the display panel 11 to obtain a first detection value, and the timing controller 13 can compensate the driving transistor according to the first detection value, and the first detection value can be a voltage value.

[0093] It should be noted that the embodiments of the present application do not limit the compensation mode of the display panel 11 based on the second video signal for shutdown compensation, and different pixel circuits and detection compensation circuit structures can be set, and corresponding shutdown compensation timing can be designed according to the designed pixel driving circuit and detection compensation circuit structure, and the timing controller 13 drives the pixel circuit and the detection compensation circuit to work according to the shutdown compensation timing, to obtain a corresponding first detection value, and then calculates the compensation gain value of the to-be-driven transistor according to the obtained first detection value.

[0094] In an exemplary embodiment, as shown in FIG. 2, the first video signal can include a first synchronization signal and a first data signal DATA1 (DA1), and the first synchronization signal can include a first frame synchronization signal VS1, a first line synchronization signal (English: Horizon Sync; abbreviation: HS1) and a first data enable signal (English: Data Enable; abbreviation: DE1). DA in the drawings of the embodiments of the present application represents the DATA signal.

[0095] The second video signal can include a second synchronization signal and a second data signal DATA2 (DA2), and the second synchronization signal can include a second frame synchronization signal VS2, a second line synchronization signal HS2 and a second data enable signal DE2. Since the built-in image generation module 131 uses the crystal oscillator on the timing controller 13 as the clock to generate the second video signal, the second video signal is very stable, and the width of the signal, the front shoulder value and the rear shoulder value of the signal can be set according to the actual needs of the shutdown compensation.

[0096] The actual HS signal in FIG. 2 represents the line synchronization signal in the video signal actually sent by the timing controller 13 to the display panel 11, and the actual DE signal represents the data enable signal in the video signal actually sent by the timing controller 13 to the display panel 11.

[0097] Referring to FIG. 3, the display panel 11 can include a data signal driver 111, a scan signal driver 112, a plurality of data signal lines, a plurality of scan signal lines, a plurality of detection signal lines, and a pixel array (not shown in the figure), the timing controller 13 can be electrically connected to the data signal driver 111 and the scan signal driver 112 respectively, the data signal driver 111 can be electrically connected to the plurality of data signal lines respectively and electrically connected to the plurality of detection signal lines respectively, and the scan signal driver 112 can be electrically connected to the plurality of scan signal lines respectively. The pixel array can include a plurality of sub-pixels, at least one sub-pixel can include a pixel circuit and a light emitting device electrically connected to the pixel circuit, and the pixel circuit can include at least one scan signal line, at least one data signal line, at least one detection signal line, and the light emitting device. In an exemplary embodiment, the timing controller 13 can provide a gray value and a control signal suitable for the specification of the data signal driver 111 to the data signal driver 111, and can provide a clock signal, a scan start signal, etc. suitable for the specification of the scan signal driver 112 to the scan signal driver 112.

[0098] The data signal driver 111 can generate a data voltage based on the received gray value and control signal, and send the data voltage to the data signal line. For example, the data signal driver 111 can sample the gray value using the clock signal, and apply the data voltage corresponding to the gray value to the data signal line in units of pixels.

[0099] The scan signal driver 112 can generate a scan signal based on the received clock signal, scan start signal, etc., and send the scan signal to the scan signal line. For example, the scan signal driver 112 can sequentially provide the scan signal to the scan signal line. For example, the scan signal driver 112 can be configured in the form of a shift register, and can generate the scan signal in a manner that sequentially transmits the scan start signal to the next stage circuit under the control of the clock signal.

[0100] The pixel circuit is configured to receive the data voltage transmitted by the data signal line under the control of the scan signal line, and output a corresponding current to the light emitting device. The light emitting device in each sub-pixel is connected to the pixel circuit of the sub-pixel where the light emitting device is located, and the light emitting device is configured to emit light of a corresponding brightness in response to the current output by the pixel circuit of the sub-pixel where the light emitting device is located.

[0101] In an exemplary embodiment, the pixel circuit can be a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C, 7T1C or 8T1C structure. Referring to FIG. 4, the pixel circuit is a 3T1C structure, which can include 3 transistors (a first transistor T1, a second transistor T2 and a third transistor T3), 1 storage capacitor C and 6 signal lines (a data signal line D, a first scan signal line G1, a second scan signal line G2, a detection signal line S, a first power supply line VDD and a second power supply line VSS).

[0102] In an exemplary embodiment, the first transistor T1 is a switch transistor, the second transistor T2 is a drive transistor, and the third transistor T3 is a compensation transistor. The first pole of the storage capacitor C is electrically connected to the control pole of the second transistor T2, and the second pole of the storage capacitor C is electrically connected to the second pole of the second transistor T2, and the storage capacitor C is used to store the potential of the control pole of the second transistor T2. The control pole of the first transistor T1 is electrically connected to the first scan signal line G1, the first pole of the first transistor T1 is electrically connected to the data signal line D, and the second pole of the first transistor T1 is electrically connected to the control pole of the second transistor T2. The first transistor T1 is used to receive the data signal transmitted by the data signal line D under the control of the first scan signal line G1, so that the control pole of the second transistor T2 receives the data signal. The control pole of the second transistor T2 is electrically connected to the second pole of the first transistor T1, the first pole of the second transistor T2 is electrically connected to the first power supply line VDD, and the second pole of the second transistor T2 is electrically connected to the first pole (anode) of the light emitting device. The second transistor T2 is used to generate a corresponding current at the second pole under the control of the data signal received by the control pole. The control pole of the third transistor T3 is electrically connected to the second scan signal line G2, the first pole of the third transistor T3 is electrically connected to the detection signal line S, and the second pole of the third transistor T3 is electrically connected to the second pole of the second transistor T2. The third transistor T3 is used to extract the threshold voltage Vth and the mobility K of the second transistor T2 in response to the compensation timing, so as to compensate the threshold voltage Vth. The second pole (cathode) of the light emitting device is connected to the second power supply line VSS.

[0103] In an exemplary embodiment, the light emitting device can be an OLED, which includes a first pole (anode), an organic light emitting layer and a second pole (cathode) stacked together. The first pole of the OLED is electrically connected to the second pole of the second transistor T2, and the second pole of the OLED is electrically connected to the second power supply line VSS. The OLED is used to emit light with a corresponding brightness in response to the current of the second pole of the second transistor T2.

[0104] In an exemplary embodiment, the signal of the first power line VDD is a high level signal continuously provided, and the signal of the second power line VSS is a low level signal. The first transistor T1 to the third transistor T3 can be P-type transistors, or can be N-type transistors. Using the same type of transistors in the pixel driving circuit can simplify the process flow, reduce the process difficulty of the display panel 11, and improve the yield of the product.

[0105] In the use of the OLED display panel 11, the driving transistor will have characteristic drift due to the influence of current stress, temperature, light, etc. This change will be reflected on the display panel 11, and will form a display afterimage. Therefore, a transistor compensation technology is needed to eliminate these afterimages. The characteristic parameters of the driving transistor that need to be compensated include two: threshold voltage Vth and mobility K (English: Mobility), wherein the detection of mobility K requires a relatively short time, about a few hundred microseconds, so the detection of mobility K can be performed in the off state or in the blank time of real-time display. The time of each frame (English: Frame) of the display device is divided into active display time (English: Active time) and blank time (English: Blank time). In the active display time, the display device uses the pixel circuit to perform normal data output display, and in the blank time, the display panel 11 is detected and compensated in real time (English: Real Time Sense).

[0106] The detection of threshold voltage Vth requires a relatively long charging time, so the detection of threshold voltage Vth is usually performed in the off state of the black picture. For example, refer to FIG. 4 and FIG. 5, the abscissa of FIG. 5 is time (t / ms), and the ordinate is voltage (V). The detection method of threshold voltage Vth can be: using a fixed data (English: Data) voltage to charge the detection (English: sense) signal line until the driving transistor T2 is cut off, at this time, the difference between the data voltage (Vdata; abbreviated as Vda) and the detection voltage (Vsense; abbreviated as Vse) on the detection signal line is the Vth value of the driving transistor T2. The duration of this process can be about 30 ms, so it cannot be performed when the display panel 11 is normally displayed, and is usually detected when the display device is off, i.e., the display device is not in a state of displaying a normal picture, but in a state of displaying a black picture. It can be understood that the off state in the embodiment of the present application can include a state in which the display panel 11 does not display a normal picture, and displays a black picture, that is, in the off state, the display device can not be completely turned off, but only not normally displayed.

[0107] When the display device performs the power-off compensation, the frame synchronization signal (VS), the line synchronization signal (HS) and the data enable signal (DE) of the video signal are used to detect the charging line by line. When the power-off detection is performed, if the video signal sent from the mainboard 12 (SOC board) is unstable, the corresponding flag signal will also fluctuate, lose the signal and change the period, etc. These unstable phenomena will cause the source control signal and the gate control signal to be wrong during the power-off compensation, and further cause the power-off compensation function to be abnormal. For example, abnormal display appears, or the wrong compensation data is calculated based on the wrong voltage value detected, and the wrong compensation data not only cannot achieve the compensation effect, but even makes the display effect worse.

[0108] Please refer to FIG. 6, a timing controller in the related art has a display mode (SOC mode) and a built-in image mode, the timing controller outputs a first video signal in the SOC mode and outputs a second video signal in the built-in image mode. A signal switching method is to switch the first video signal output by the mainboard directly to the second video signal generated by the local timing controller 13 before the power-off compensation is performed, so that the display panel can perform the power-off compensation based on the second video signal.

[0109] However, in the above signal switching method, when the signal switching is performed, there is a great possibility that the frequency, period and length of the video flag signal (especially the DE signal) will change. Please refer to FIG. 7, during the signal switching, the following two cases can occur, as shown in the first case of FIG. 7, the switching signal causes the DE signal and the VS signal to be shortened, as shown in the second case of FIG. 7, the switching signal causes the DE signal and the VS signal to be lengthened. In other words, the data signal driver can include a plurality of source chips (English: Source IC), when the DE and the VS are shortened, the scanning time of a row of pixels is also shortened, and the amount of data of the signal transmitted by the timing controller to at least one Source IC will be less, and since the Source IC must receive a specific amount of data each time to output normally, the Source IC will work abnormally. Similarly, when the DE and the HS are lengthened, the scanning time of a row of pixels is also lengthened, and the amount of data of the signal transmitted by the timing controller to at least one Source IC will be more, and the Source IC will also work abnormally.

[0110] Therefore, in the embodiment of the present application, the first video signal is stopped from being sent to the display panel 11 when the level of the first frame synchronization signal VS1 jumps from the first level to the second level (t2), and the second video signal is sent to the display panel 11 when the level of the second frame synchronization signal VS2 jumps from the third level to the fourth level (t3), so that the display panel 11 performs the shutdown compensation based on the second video signal. That is, after receiving the shutdown compensation instruction, the timing controller 13 can start the signal switching at the end of a frame of the first video signal output by the main board 12, and complete the signal switching at the start of a frame of the second video signal generated by the timing controller 13. During the signal switching, the timing controller 13 sends a complete frame of video signal to the display panel 11, which can avoid the problem of abnormal operation of the display panel 11 caused by the incomplete frame of video signal input into the display panel 11 due to the signal switching.

[0111] Please refer to FIG. 8, which shows the case that the signal switching in the related art interrupts the process of detecting the mobility of the driving transistor in real time. That is, if the display panel is performing the action of detecting the mobility in real time when the signal switching is performed, the detection action will be interrupted abnormally. The display panel can further include an analog-to-digital converter (ADC) electrically connected to the detection signal line (S), which can convert the voltage on the detection transistor obtained by the detection signal line (S) into digital data (the digital data is the detection value), and send the detection value to the timing controller. The analog-to-digital converter can be integrated in the Source IC. In FIG. 8, the Sample (Sa) signal is a sampling signal sent by the timing controller to the analog-to-digital converter (ADC), which is used to instruct the analog-to-digital converter (ADC) to start the digital-to-analog conversion, and the ADC-TX signal is a transmission signal output by the timing controller to the analog-to-digital converter (ADC), which is used to instruct the analog-to-digital converter (ADC) to send the detection value to the memory after the conversion is completed. Due to the signal switching, the timing controller only sends the Sample signal to the analog-to-digital converter (ADC), and does not send the ADC-TX signal to the analog-to-digital converter (ADC), which causes the digital data generated by the analog-to-digital converter (ADC) in the Source IC after the voltage conversion to be unable to be sent to the memory, resulting in the disorder of the Source IC. At the same time, it can also affect the real-time detection result, and further affect the real-time detection compensation effect of the display panel.

[0112] Please refer to FIG. 2, in an alternative embodiment, the first video signal can further include a first data enable signal DE1, the first data enable signal DE1 includes blanking areas and active areas arranged alternately, and the display panel 11 includes a driving transistor. The blanking areas of the first data enable signal DE1 correspond to the blank time of the first video signal, and the active areas of the first data enable signal DE1 correspond to the active display time of the first video signal.

[0113] The timing controller 13 further includes a compensation conversion module 133, the compensation conversion module 133 is electrically connected with the data selection module 132, the compensation conversion module 133 has a real-time detection mode, and the compensation conversion module 133 is configured to send a real-time detection signal to the display panel 11 in the real-time detection mode, the real-time detection signal is used to instruct the display panel 11 to detect the mobility of the driving transistor. The data selection module 132 is further configured to detect whether the first data enable signal DE1 in the first video signal is in the active area when the first video signal is sent (t1), and send a data valid signal to the compensation conversion module 133 when the first data enable signal DE1 is in the active area (t1). The compensation conversion module 133 is configured to close the real-time detection mode based on the data valid signal, so as to stop sending the real-time detection signal to the display panel 11.

[0114] Since the detection action of the real-time detection compensation of the display panel 11 is performed in the blank time in a frame, in the embodiment of the application, the first video signal being sent can be detected before the data selection circuit stops sending the first video signal to the display panel 11, and the compensation conversion module 133 is instructed to close the real-time detection mode when the first data enable signal DE1 is in the active area (t1), so that the compensation conversion module 133 can stop sending the real-time detection signal to the display panel 11 when the first data enable signal DE1 is in the blanking area, that is, the display panel 11 stops the detection action of the real-time detection compensation. In other words, since the first video signal is in the active display time, the compensation conversion module 133 does not send the real-time detection signal to the display panel 11, and the display panel 11 does not perform the detection action of the real-time detection compensation, the compensation conversion module 133 is instructed to close the real-time detection mode at t1, so that the display panel 11 can stop the detection action of the real-time detection compensation in advance, and the phenomenon of interruption of the detection action of the real-time detection compensation of the display panel 11 can be avoided, so that the phenomenon of Source IC disorder can be avoided.

[0115] In an alternative embodiment, referring to FIG. 2, the built-in image generation module 131 can be configured to generate the second video signal immediately upon receiving the shutdown compensation signal. In this case, the rising edge of the second video signal is not synchronized with the rising edge of the first video signal, and the data selection module 132 continues to output the first video signal instead of the second video signal for a period of time after the built-in image generation module 131 generates the second video signal immediately.

[0116] In this case, the time t2 at which the level of the first frame synchronization signal VS1 jumps from the first level to the second level coincides with the time t3 at which the level of the second frame synchronization signal VS2 jumps from the third level to the fourth level.

[0117] For example, in stage 1 between t1 and t2 in FIG. 2, the timing controller 13 sends the first video signal to the display panel 11, and no real-time detection is performed in this stage; in stage 2 between t2 and t3, the timing controller 13 does not send any video signal to the display panel 11; and in stage 3 after t3, the timing controller 13 sends the second video signal to the display panel 11, and shutdown compensation is performed in this stage.

[0118] In an alternative embodiment, referring to FIG. 9, the row synchronization signal is not shown in FIG. 9 to simplify the switching timing diagram. The data selection module 132 can also be configured to send an enable signal to the built-in image generation module 131 when the level of the first frame synchronization signal VS1 jumps from the first level to the second level. The built-in image generation module 131 is configured to generate the second video signal immediately upon receiving the enable signal.

[0119] In this case, the first rising edge of the second video signal can be synchronized with the rising edge of the first video signal. In other words, the built-in image generation module 131 does not generate the second video signal immediately upon receiving the shutdown compensation signal, but only starts to generate the second video signal after receiving the enable signal sent by the data selection module 132. At the time when the built-in image generation module 131 generates the second video signal immediately, the data selection circuit also stops outputting the first video signal at the same time and outputs the second video signal immediately.

[0120] In this case, the time t2 at which the level of the first frame synchronization signal VS1 jumps from the first level to the second level coincides with the time t3 at which the level of the second frame synchronization signal VS2 jumps from the third level to the fourth level.

[0121] Please refer to FIG. 3, in an alternative embodiment, the data selection module 132 can include a comparison module 1321 and a gating module 1322, the comparison module 1321 is electrically connected with the mainboard 12 and the gating module 1322 respectively. The comparison module 1321 is configured to generate a first indication signal and output the first indication signal to the gating module 1322 when the level of the first frame synchronization signal VS1 of the first video signal output by the mainboard 12 is detected to reach a second level. The gating module 1322 is configured to stop sending the first video signal to the display panel 11 based on the first indication signal. The second level can be a level indicating that the first video signal is at a frame completion, for example, when the second level reaches 3V, the comparison circuit can send the first indication signal to the gating module 1322, so that the gating module 1322 can respond to the change of the first video signal output by the mainboard 12 in time.

[0122] Please refer to FIG. 3, in an alternative embodiment, the data selection module 132 can include a comparison module 1321 and a gating module 1322, the comparison module 1321 is electrically connected with the mainboard 12 and the gating module 1322 respectively. The comparison module 1321 is configured to generate a first indication signal and output the first indication signal to the gating module 1322 when the level of the first frame synchronization signal VS1 of the first video signal output by the mainboard 12 is detected to reach a second level. The gating module 1322 is configured to stop sending the first video signal to the display panel 11 based on the first indication signal. The second level can be a level indicating that the first video signal is at a frame completion, for example, when the second level reaches 3V, the comparison circuit can send the first indication signal to the gating module 1322, so that the gating module 1322 can respond to the change of the first video signal output by the mainboard 12 in time.

[0123] Please refer to FIG. 3 and FIG. 10, in an alternative embodiment, the display device can further include a memory 14, the memory 14 is electrically connected with the timing controller 13, and the memory is configured to output a compensation completion signal, the compensation completion signal is a signal generated by the memory 14 when the memory 14 receives a first detection value sent by the display panel 11, and the first detection value is a first detection value obtained by the display panel 11 in the process of shutdown compensation.

[0124] The data selection module 132 is further configured to send the second video signal to the display panel 11 after receiving the compensation completion signal, and stop sending the second video signal to the display panel 11 when the level of the second frame synchronization signal VS2 jumps from a third level to a fourth level (t4), and send the first video signal to the display panel 11 when the level of the first frame synchronization signal VS1 jumps from a first level to a second level (t5).

[0125] The display panel 11 comprises a detection compensation circuit 113, the memory 14 can be configured to store a detection result of the detection compensation circuit 113, and the memory 14 can further comprise a look-up table for storing a corresponding relationship between the detection result and a compensation gain value. After the shutdown compensation is completed, normal display can be continued, i.e., the display device can be switched back to the display mode of the mainboard 12 (SOC) to display normal video images. The switching process of the second video signal to the first video signal can be similar to the switching process of the first video signal to the second video signal. After receiving the compensation completion signal, the timing controller 13 can start the signal switching at the end of a frame of the second video signal generated by the timing controller 13, and complete the signal switching at the beginning of a frame of the first video signal output by the mainboard 12.

[0126] In the signal switching process, the timing controller 13 sends a complete frame of video signal to the display panel 11, so that the problem of abnormal operation of the display panel 11 caused by incomplete frame of video signal input to the display panel 11 due to signal switching can be avoided.

[0127] For example, in stage 4 between t4 and t5 in FIG. 10, the timing controller 13 does not send a video signal to the display panel 11; after t5, the timing controller 13 sends the first video signal to the display panel 11, and does not perform real-time detection on the display panel in stage 5 between t5 and t6, and performs real-time detection on the display panel after t6.

[0128] In some example embodiments, as shown in FIG. 3 and FIG. 11, the detection compensation circuit 113 can be integrated in the Source IC, and the detection compensation circuit 113 is connected with the detection signal line S, for obtaining the amount of charge flowing through the to-be-driven element within a preset detection time, so that the memory 14 calculates the compensation gain value of the to-be-driven transistor according to the obtained amount of charge.

[0129] In some example embodiments, as shown in FIG. 11, the detection compensation circuit 113 comprises a current integrator, a sampling switch and an analog-to-digital converter connected in sequence, wherein one end of the current integrator is connected with the detection signal line S, and the other end of the current integrator is connected with a first passage end of the sampling switch; a second passage end of the sampling switch is connected with a first end of the analog-to-digital converter, and a control end of the sampling switch receives a sampling signal; a second end of the analog-to-digital converter is electrically connected with the timing controller 13 and the memory 14.

[0130] In an alternative embodiment, the first video signal further comprises a first data enable signal DE1 (DE1), the first data enable signal DE1 comprises a blanking area and an active area arranged alternately, and the display panel 11 comprises a driving transistor.

[0131] The timing controller 13 further includes a compensation conversion module 133, which is electrically connected with the data selection module 132. The compensation conversion module 133 has a real-time detection mode. In the real-time detection mode, the compensation conversion module 133 is configured to send a real-time detection signal to the display panel 11. The real-time detection signal is used to instruct the display panel 11 to detect the mobility of the driving transistor. The data selection module 132 is further configured to, when the first video signal is being sent, detect whether the first data enable signal DE1 in the first video signal is in the active region, and send a data valid signal to the compensation conversion module 133 when the first data enable signal DE1 is in the active region (t6). The compensation conversion module 133 is configured to, based on the data valid signal, start the real-time detection mode, so as to be able to send the real-time detection signal to the display panel 11.

[0132] Since the detection action of the real-time detection compensation of the display panel 11 is performed in the blank time in a frame, in the embodiment of the present application, the first video signal being sent can be detected after the data selection circuit sends the first video signal to the display panel 11 again. When the first data enable signal DE1 is in the active region (t6), the compensation conversion module 133 is instructed to start the real-time detection mode, so as to be able to send the real-time detection signal to the display panel 11 when the first data enable signal DE1 is in the blank region, so that the display panel 11 starts the detection action of the real-time detection compensation. That is, since the first video signal is in the active display time, the compensation conversion module 133 does not send the real-time detection signal to the display panel 11, and the display panel 11 does not perform the detection action of the real-time detection compensation. Therefore, the compensation conversion module 133 is instructed to start the real-time detection mode at t6, which can avoid the interruption of the detection action of the real-time detection compensation of the display panel 11, so as to avoid the phenomenon of Source IC disorder.

[0133] In an alternative embodiment, the second video signal includes a first black screen signal and a third video signal. The data selection module 132 is further configured to, when the level of the second frame synchronization signal VS2 jumps from the third level to the fourth level, send the first black screen signal to the display panel 11. The first black screen signal has a second time length, so that the display panel 11 displays a black screen for the second time length. The data selection module 132 is further configured to, after sending the first black screen signal to the display panel 11, send the third video signal to the display panel 11, so that the display panel 11 performs the shutdown compensation based on the third video signal.

[0134] In some example embodiments, the second time length can be two frame display times or one frame display time. For example, the second time length can be 35 ms. During the process of displaying the black picture for the second time length, the data voltage in the display panel 11 can be 0.

[0135] The timing controller 13 can further include a processing output module 135, which can include an image processing and compensation module 1351, a source driving control module (also referred to as a Source IC control module) 1352, and a gate driving control module (also referred to as a Gate IC / GOA control module) 1353. The display panel 11 includes a data signal driver 111 and a scanning signal driver 112. The image processing and compensation module 1351 can be configured to perform image processing and uniformity compensation on the first video signal or the second video signal, and output the first video signal or the second video signal after image processing and uniformity compensation to the source driving control module 1352 and the gate driving control module 1353.

[0136] The source driving control module 1352 can be configured to generate source control signals and data signals according to the first video signal or the second video signal, and output the source control signals and the data signals to the data signal driver 111. The gate driving control module 1353 can be configured to generate gate control signals according to the first video signal or the second video signal, and output the gate control signals to the scanning signal driver 112.

[0137] In this way, the data selection module 132 can first send the first black picture signal to the processing output module 135, and the processing output module 135 can send the processed first black picture signal to the display panel 11. In this process, the processing output module 135 can be configured to capture signal parameters of the second video signal, which can include the width of the VS signal, the width of the DE signal, the front shoulder of the frame, the rear shoulder of the frame, the frame pulse width, and the line pulse width, etc. This can avoid the problem of occasional detection abnormalities due to the fact that the data signal driver 111 does not receive normal driving signals.

[0138] In an alternative, the second video signal further includes a second black picture signal. The data selection module 132 is further configured to send the second black picture signal to the compensation conversion module 133 when the compensation completion signal is received. The second black picture signal has a time length of the second time length, so that the display panel 11 displays a black picture for the second time length. In this way, residual charges on the display panel 11 can be eliminated, and the problem of display residual image after switching signals on the display panel 11 can be avoided.

[0139] Optionally, the first video signal further comprises a third black screen signal; and the data selection module 132 is further configured to, when the shutdown compensation signal is received, send the third black screen signal to the display panel 11, the third black screen signal having a second time length, so that the display panel 11 displays a black screen for the second time length. In this way, residual charges on the display panel 11 can be eliminated, and the problem of display panel 11 displaying residual images after switching signals can be avoided.

[0140] Referring to FIG. 3, in some example embodiments, the mainboard 12 can include a television mainboard or a video signal generator. The timing controller 13 can further include a data decoding module 134 configured to receive the first video signal output by the mainboard 12 and decode the first video signal. For example, the first video signal output by the mainboard 12 is a VBO (English: V-by-One) signal, which is a digital interface standard developed for image transmission. The first video signal after decoding by the data decoding module 134 includes a first synchronization signal and a first data signal DATA1, and the first synchronization signal includes a first frame synchronization signal VS1, a first line synchronization signal HS1 and a first data enable signal DE1.

[0141] The third black screen signal can be generated by the data decoding module 134 or the mainboard 12. For example, the mainboard 12 is further configured to send a shutdown compensation signal to the data decoding module 134, and the data decoding module 134 is configured to output the third black screen signal after receiving the shutdown compensation signal.

[0142] Optionally, the second time length is N frame display time length, and N is an integer greater than or equal to 1.

[0143] In an optional embodiment, the compensation conversion module 133 is electrically connected to a source drive control module 1352 and a gate drive control module 1353 respectively, the display panel 11 includes a data signal driver 111 and a scanning signal driver 112, the source drive control module 1352 is electrically connected to the data signal driver 111, and the gate drive control module 1353 is electrically connected to the scanning signal driver 112. The compensation conversion module 133 is configured to receive the data valid signal output by the data selection module 132, generate a first shutdown signal based on the data valid signal, and send the first shutdown signal to the source drive control module 1352 and the gate drive control module 1353; the source drive control module 1352 is configured to stop sending real-time sensing signals to the data signal driver 111 according to the first shutdown signal; and the gate drive control module 1353 is configured to stop sending real-time sensing signals to the scanning signal driver 112 according to the first shutdown signal.

[0144] In an alternative embodiment, the compensation conversion module 133 has a power-off detection mode, and is configured to send a power-off detection signal to the display panel 11 in the power-off detection mode, where the power-off detection signal is used to instruct the display panel 11 to detect the threshold voltage of the driving transistor. The data selection module 132 is further configured to send a parameter acquisition completion signal to the compensation conversion module 133 after sending the first black frame signal.

[0145] The compensation conversion module 133 is configured to start the power-off detection mode based on the parameter acquisition completion signal, and send the power-off detection signal to the display panel 11.

[0146] In an alternative embodiment, during the power-off operation stage of the display device, the main board 12 can determine whether the characteristic parameters in the display panel 11 need to be detected in the power-off mode. When the characteristic parameters in the display panel 11 need to be detected in the power-off mode, the timing controller 13 is instructed to perform the following power-off operation: detecting the characteristic parameters in the display panel 11 in the power-off mode, obtaining the detection values, and storing the detection values in the storage 14.

[0147] During the operation of the display device or the power-on operation stage, the main board 12 can also instruct the timing controller 13 to detect the characteristic parameters in the display panel 11 according to the detection time specified by the user.

[0148] In an exemplary embodiment, please refer to FIG. 2 and FIG. 12. During the normal display process, the timing controller detects whether the power-off compensation instruction is received, and the timing controller works in the normal display mode. When the power-off compensation instruction is received, the black frame is displayed for 35 ms (greater than two frame times) in the normal display mode to eliminate the residual charge on the display panel. Then at t1, the switching signal instruction is sent to close the real-time detection of the display panel, the main board signal is closed (i.e. the first video signal is stopped to be sent) at t2, the TCON signal is opened (i.e. the second video signal is started to be sent) at t3, and the black frame is maintained for 35 ms. After that, the display panel is compensated in the power-off mode, and after the compensation is completed, the power-off operation is performed.

[0149] In an exemplary embodiment, referring to FIG. 9 and FIG. 13, in the normal display process, the timing controller detects whether the shutdown compensation instruction is received, at which time the timing controller works in the normal display mode. When the shutdown compensation instruction is received, a black picture is displayed for 35 ms (greater than two frame times) in the normal display mode to eliminate the residual charge on the display panel. Then at time t1, a switching signal instruction is sent to turn off the real-time detection of the display panel, the mainboard signal is turned off at time t2 (i.e., the first video signal is stopped from being sent), and the video signal, which is the second video signal, is generated and the TCON signal is turned on at time t2 (i.e., the second video signal is started to be sent), and the black picture is maintained for 35 ms, after which the display panel is compensated for shutdown, and after the compensation is completed, the shutdown operation is performed.

[0150] In an exemplary embodiment, referring to FIG. 10 and FIG. 14, after the shutdown compensation, the display device can be shut down or continue to display. If the display device is set to be directly shut down, after the compensation is completed, the shutdown operation is performed. If the display continues, after the shutdown compensation is completed, a black picture is displayed for 35 ms, then at time t4, the TCON signal is turned off (i.e., the second video signal is stopped from being sent), and at time t5, the mainboard signal is turned on (i.e., the first video signal is started to be sent), and at time t6, the display effective area (i.e., the effective display time) of the first video signal is entered, the real-time detection is turned on to start the real-time detection of the display panel, and the normal display state is entered to display the normal video image. The process of the signal switching has no visible characteristics to the naked eye and cannot be perceived by the user.

[0151] In summary, the embodiment of the present application provides a timing controller including a built-in image generation module and a data selection module. The data selection module is configured to stop sending the first video signal to the display panel when the level of the first frame synchronization signal jumps from the first level to the second level, and start sending the second video signal to the display panel when the level of the second frame synchronization signal jumps from the third level to the fourth level, so that the display panel performs shutdown compensation based on the second video signal. In this way, the timing controller can start signal switching at the end of a frame of the first video signal output by the mainboard, and complete signal switching at the start of a frame of the second video signal generated by the timing controller. During signal switching, the timing controller sends a complete frame of video signal to the display panel, which can avoid the problem of abnormal operation of the display panel caused by incomplete frame of video signal input into the display panel due to signal switching. Moreover, the video source of the display panel can be switched to the second video signal generated by the built-in image generation module, which has strong stability, so that shutdown compensation can be performed normally. The compensation effect of the display panel can be improved, and the problem of poor compensation effect of the display panel in the related art can be solved.

[0152] Please refer to FIG. 15, which is a flowchart of a display device adjustment method provided by an embodiment of the present application. The display device adjustment method can be applied to the timing controller in any of the above embodiments. The method includes the following steps:

[0153] Step 201: receiving a first video signal and a shutdown compensation signal sent by a mainboard. The first video signal includes a first frame synchronization signal.

[0154] Step 202: based on the shutdown compensation signal, sending the first video signal to a display panel, so that the display panel displays a picture based on the first video signal, and generating a second video signal. The second video signal includes a second frame synchronization signal.

[0155] Step 203: stopping sending the first video signal to the display panel when the level of the first frame synchronization signal jumps from the first level to the second level.

[0156] Step 204: sending the second video signal to the display panel when the level of the second frame synchronization signal jumps from the third level to the fourth level, so that the display panel performs shutdown compensation based on the second video signal.

[0157] Please refer to FIG. 16, which is a flowchart of another display device adjustment method provided by an embodiment of the present application. The display device adjustment method can be applied to the timing controller in any of the above embodiments. The method includes the following steps:

[0158] In step 301, a first video signal and a shutdown compensation signal sent by the mainboard are received, and the first video signal comprises a first frame synchronization signal.

[0159] The timing controller can send the received first video signal to the display panel to make the display panel display a picture.

[0160] In step 302, based on the shutdown compensation signal, the first video signal is sent to the display panel to make the display panel display a picture based on the first video signal, and a second video signal is generated, and the second video signal comprises a second frame synchronization signal.

[0161] After receiving the shutdown compensation signal, the timing controller continues to send the first video signal to the display panel to make the display panel continue to display a picture. The stability of the second video signal is better than that of the first video signal.

[0162] In step 303, a real-time detection signal is sent to the display panel.

[0163] The real-time detection signal is used to instruct the display panel to detect the mobility of the driving transistor.

[0164] In step 304, whether a first data enable signal in the first video signal is in an effective area is detected.

[0165] The first data enable signal comprises a blanking area and an effective area arranged alternately.

[0166] In step 305, in response to the first data enable signal being in the effective area, the real-time detection mode is closed to stop sending the real-time detection signal to the display panel.

[0167] Since the detection action of the real-time detection compensation of the display panel is performed in the blank time in a frame, in the embodiment of the application, the first video signal being sent can be detected before the data selection circuit stops sending the first video signal to the display panel, and when the first data enable signal is in the effective area (t1), the compensation conversion module is instructed to close the real-time detection mode, so that the compensation conversion module can stop sending the real-time detection signal to the display panel when the first data enable signal is in the blanking area, that is, the display panel stops the detection action of the real-time detection compensation. In other words, since the compensation conversion module does not send the real-time detection signal to the display panel when the first video signal is in the effective display time, and the display panel does not perform the detection action of the real-time detection compensation, the compensation conversion module is instructed to close the real-time detection mode at t1, so that the display panel can stop the detection action of the real-time detection compensation in advance, and the phenomenon of interruption of the detection action of the real-time detection compensation of the display panel can be avoided, so that the phenomenon of Source IC disorder can be avoided.

[0168] In step 306, when the level of the first frame synchronization signal jumps from the first level to the second level, the sending of the first video signal to the display panel is stopped.

[0169] The first video signal includes multiple frames of video signals. When the level of the first frame synchronization signal jumps from the first level to the second level, it can represent that one frame of video signals in the first video signal ends, or it can represent that another frame of video signals in the first video signal starts. That is, the jump of the level can be regarded as a dividing point of two frames of video signals in the first video signal.

[0170] In step 307, when the level of the second frame synchronization signal jumps from the third level to the fourth level, the second video signal is sent to the display panel, so that the display panel performs shutdown compensation based on the second video signal.

[0171] The second video signal includes multiple frames of video signals. When the level of the second frame synchronization signal jumps from the third level to the fourth level, it can represent that one frame of video signals in the second video signal ends, or it can represent that another frame of video signals in the second video signal starts. That is, the jump of the level can be regarded as a dividing point of two frames of video signals in the second video signal.

[0172] Because the timing controller directly switches the signal being transmitted in the process of switching the first video signal to the second video signal, when the signal is switched, one frame of video signals in the first video signal can not be completely transmitted, that is, only part of the signal in the frame of video signals is transmitted to the display panel, and one frame of video signals in the second video signal is transmitted from the middle, that is, only part of the signal in the frame of video signals is transmitted to the display panel. The above two parts of the signal will be combined into one frame of video signals, so that the amount of data of one frame of video signals received by the display panel at the time of signal switching is more or less than the amount of data of one frame of video signals in the second video signal, which will cause the display panel to receive abnormal video signals, so that the display panel works disorderly and affects the compensation effect of the display panel during shutdown compensation.

[0173] Therefore, in the embodiment of the application, after receiving the shutdown compensation instruction, the timing controller starts signal switching at the end of one frame of video signals of the first video signal output by the mainboard, and completes signal switching at the start of one frame of video signals of the second video signal generated by the timing controller. During signal switching, the timing controller sends any frame of video signals to the display panel, which is a complete frame of video signals, so that the problem of abnormal working of the display panel caused by incomplete frame of video signals input into the display panel due to signal switching can be avoided. Moreover, the video source of the display panel is switched to the second video signal generated by the built-in image generation module, which has strong stability, so that the shutdown compensation can be performed normally.

[0174] Optionally, in step 302, generating the second video signal based on the shutdown compensation signal can include the following two ways:

[0175] In the first way, the second video signal is generated immediately when the shutdown compensation signal is received.

[0176] The first time length is between the time when the level of the first frame synchronization signal jumps from the first level to the second level and the time when the level of the second frame synchronization signal jumps from the third level to the fourth level.

[0177] In the second way, the second video signal is generated immediately when the level of the first frame synchronization signal jumps from the first level to the second level.

[0178] The first time length is between the time when the level of the first frame synchronization signal jumps from the first level to the second level and the time when the level of the second frame synchronization signal jumps from the third level to the fourth level.

[0179] In summary, the adjustment method of the display device can be applied to the timing controller, which includes a built-in image generation module and a data selection module. The data selection module is used to stop sending the first video signal to the display panel when the level of the first frame synchronization signal jumps from the first level to the second level, and to send the second video signal to the display panel when the level of the second frame synchronization signal jumps from the third level to the fourth level, so that the display panel performs shutdown compensation based on the second video signal. In this way, the timing controller can start signal switching at the end of a frame of the first video signal output by the mainboard, and complete signal switching at the beginning of a frame of the second video signal generated by the timing controller. During signal switching, the timing controller sends a complete frame of video signal to the display panel, which can avoid the problem of abnormal operation of the display panel caused by incomplete frame of video signal input to the display panel due to signal switching. Moreover, the video source of the display panel can be switched to the second video signal generated by the built-in image generation module, which has strong stability, so that the shutdown compensation can be performed normally. The compensation effect of the display panel can be improved, and the compensation effect of the display panel can be improved.

[0180] According to another aspect of the present application, a display device is provided, which includes a mainboard, a display panel, and a timing controller. The timing controller is electrically connected to the display panel and the mainboard, respectively, and is the timing controller in any of the above embodiments. Optionally, the display device can be any product or component with display function, such as AMOLED display device, mobile phone, tablet computer, television, and display.

[0181] According to another aspect of the present application, there is provided an adjusting apparatus of a display device, the adjusting apparatus of the display device comprising a processor and a memory, the memory storing at least one instruction, at least one program, a code set or an instruction set, the at least one instruction, the at least one program, the code set or the instruction set being loaded and executed by the processor to implement the adjusting method of the display device in any of the embodiments.

[0182] According to another aspect of the present application, there is provided a computer storage medium, the computer storage medium storing at least one instruction, at least one program, a code set or an instruction set, the at least one instruction, the at least one program, the code set or the instruction set being loaded and executed by a processor to implement the adjusting method of the display device in any of the embodiments.

[0183] According to another aspect of the present application, there is provided a computer program product or a computer program, the computer program product or the computer program comprising computer instructions stored in a computer readable storage medium. A processor of a computer device reads the computer instructions from the computer readable storage medium, and the processor executes the computer instructions to cause the computer device to perform the adjusting method of the display device.

[0184] In the present application, the terms "first", "second", "third", and "fourth" are only for descriptive purpose, and cannot be understood as indicating or implying relative importance. The term "multiple" refers to two or more, unless otherwise explicitly limited.

[0185] In several embodiments provided in the present application, it should be understood that the disclosed apparatus and method can be implemented in other ways. For example, the apparatus embodiments described above are only illustrative, for example, the division of the units is only a logical function division, and actual implementation can have another division manner, for example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. In addition, the coupling or direct coupling or communication connection between the units or components shown or discussed can be indirect coupling or communication connection through some interfaces, apparatuses or units, and can be electrical, mechanical or other forms.

[0186] The units described as separate components can or can not be physically separated, and the components shown as units can or can not be physical units, i.e. can be located in one place, or can be distributed on multiple network units. Part or all of the units can be selected according to actual needs to achieve the purpose of the embodiment scheme.

[0187] Those skilled in the art can understand that all or part of the steps of the above-mentioned embodiments can be completed by hardware, or can be instructed to relevant hardware by program. The program can be stored in a computer readable storage medium, and the storage medium mentioned above can be a read-only memory, a magnetic disk or an optical disk, etc.

[0188] The above only describes optional embodiments of the present application and is not used to limit the present application. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A timing controller, characterized by, The application discloses a display device, a timing controller, an in-built image generation module and a data selection module. The in-built image generation module is electrically connected with the data selection module, and the in-built image generation module is used to generate a second video signal after receiving the shutdown compensation signal and send the second video signal to the data selection module, wherein the second video signal comprises a second frame synchronization signal. The data selection module is electrically connected with the display panel, and the data selection module is used to send the first video signal to the display panel after receiving the shutdown compensation signal, wherein the first video signal comprises a first frame synchronization signal, so that the display panel displays a picture based on the first video signal. The data selection module is also used to stop sending the first video signal to the display panel when the level of the first frame synchronization signal jumps from a first level to a second level, and send the second video signal to the display panel when the level of the second frame synchronization signal jumps from a third level to a fourth level, so that the display panel performs shutdown compensation based on the second video signal.

2. The timing controller of claim 1, wherein, The first video signal also comprises a first data enable signal, the first data enable signal comprises a blanking area and an effective area arranged alternately, and the display panel comprises a driving transistor. The timing controller also comprises a compensation conversion module, the compensation conversion module is electrically connected with the data selection module, and the compensation conversion module has a real-time detection mode. The data selection module is also used to detect whether the first data enable signal in the first video signal is in the effective area when the first video signal is sent, and send a data valid signal to the compensation conversion module when the first data enable signal is in the effective area. The compensation conversion module is used to close the real-time detection mode based on the data valid signal, so as to stop sending the real-time detection signal to the display panel.

3. The timing controller of claim 1, wherein, The in-built image generation module is used to generate the second video signal immediately when the shutdown compensation signal is received. The first frame synchronization signal jumps from the first level to the second level at a first time, and the second frame synchronization signal jumps from the third level to the fourth level at a second time.

4. The timing controller of claim 1, wherein, The data selection module is also used to send an opening signal to the in-built image generation module when the level of the first frame synchronization signal jumps from the first level to the second level. The in-built image generation module is used to generate the second video signal immediately when the opening signal is received. The time point when the level of the first frame synchronization signal jumps from the first level to the second level coincides with the time point when the level of the second frame synchronization signal jumps from the third level to the fourth level.

5. The timing controller of claim 1, wherein, The data selection module comprises a comparison module and a gating module, and the comparison module is electrically connected with the mainboard and the gating module respectively. The comparison module is configured to generate a first indication signal when the level of the first frame synchronization signal of the first video signal output by the mainboard reaches the second level, and output the first indication signal to the gating module. The gating module is configured to stop sending the first video signal to the display panel based on the first indication signal.

6. The timing controller of claim 1, wherein, The data selection module comprises a comparison module and a gating module, and the comparison module is electrically connected with the built-in image generation module and the gating module respectively. The comparison module is configured to generate a second indication signal when the level of the second frame synchronization signal of the second video signal output by the built-in image generation module reaches the fourth level, and output the second indication signal to the gating module. The gating module is configured to send the second video signal to the display panel based on the second indication signal.

7. The timing controller of claim 1, wherein, The display device further comprises a memory electrically connected with the timing controller, and the memory is configured to output a compensation completion signal, which is a signal generated by the memory when the first detection value sent by the display panel is received, and the first detection value is a first detection value acquired by the display panel in the process of the power-off compensation. The data selection module is further configured to send the second video signal to the display panel after the compensation completion signal is received. The data selection module is further configured to stop sending the second video signal to the display panel when the level of the second frame synchronization signal jumps from the third level to the fourth level, and send the first video signal to the display panel when the level of the first frame synchronization signal jumps from the first level to the second level.

8. The timing controller of claim 7, wherein, The first video signal further comprises a first data enable signal, the first data enable signal comprises a blanking area and an active area arranged alternately, and the display panel comprises a driving transistor. The timing controller further comprises a compensation conversion module electrically connected with the data selection module, and the compensation conversion module has a real-time detection mode. The data selection module is further configured to detect whether the first data enable signal in the first video signal is in the active area when the first video signal is sent, and send a data valid signal to the compensation conversion module when the first data enable signal is in the active area. The compensation conversion module is configured to start the real-time detection mode based on the data valid signal, so as to enable the display panel to receive the real-time detection signal.

9. The timing controller of claim 1, wherein, The second video signal comprises a first black picture signal and a third video signal. The data selection module is further configured to send the first black picture signal to the display panel when the level of the second frame synchronization signal jumps from the third level to the fourth level, and the first black picture signal has a second time length, so that the display panel displays a black picture for the second time length. The data selection module is further configured to send the third video signal to the display panel after sending the first black picture signal to the display panel, so that the display panel performs shutdown compensation based on the third video signal.

10. The timing controller of claim 7, wherein, The second video signal further comprises a second black picture signal. The data selection module is further configured to send the second black picture signal to the display panel when the compensation completion signal is received, and the second black picture signal has a second time length, so that the display panel displays a black picture for the second time length.

11. The timing controller of claim 1, wherein, The first video signal further comprises a third black picture signal. The data selection module is further configured to send the third black picture signal to the display panel when the shutdown compensation signal is received, and the third black picture signal has a second time length, so that the display panel displays a black picture for the second time length.

12. A timing controller as claimed in any one of claims 9 to 11, wherein, The second time length is N frame display time length, and N is an integer greater than or equal to 1.

13. A method of adjusting a display device, characterized by, The method is applied to the timing controller of any one of claims 1 to 12, and the method comprises: receiving the first video signal and the shutdown compensation signal sent by the mainboard, wherein the first video signal comprises a first frame synchronization signal; based on the shutdown compensation signal, sending the first video signal to the display panel, so that the display panel displays a picture based on the first video signal, and generates a second video signal, wherein the second video signal comprises a second frame synchronization signal; when the level of the first frame synchronization signal jumps from a first level to a second level, stopping sending the first video signal to the display panel; when the level of the second frame synchronization signal jumps from a third level to a fourth level, sending the second video signal to the display panel, so that the display panel performs shutdown compensation based on the second video signal.

14. The method of claim 13, wherein, The first video signal further comprises a first data enable signal, the first data enable signal comprises alternating blanking areas and active areas, the display panel comprises a driving transistor, and the compensation conversion module has a real-time detection mode. Before the method stops sending the first video signal to the display panel, the method further comprises: sending a real-time detection signal to the display panel, wherein the real-time detection signal is used to instruct the display panel to detect the mobility of the driving transistor; detecting whether the first data enable signal in the first video signal is in the active area; in response to the first data enable signal being in the active area, closing the real-time detection mode to stop sending the real-time detection signal to the display panel.

15. The method of claim 13, wherein, Generating a second video signal based on the shutdown compensation signal, comprising: Generating the second video signal immediately upon receiving the shutdown compensation signal; Wherein the time when the level of the first frame synchronization signal jumps from the first level to the second level coincides with the time when the level of the second frame synchronization signal jumps from the third level to the fourth level.

16. The method of claim 13, wherein, Generating a second video signal based on the shutdown compensation signal, comprising: Generating the second video signal immediately upon the level of the first frame synchronization signal jumps from the first level to the second level; Wherein the time when the level of the first frame synchronization signal jumps from the first level to the second level coincides with the time when the level of the second frame synchronization signal jumps from the third level to the fourth level.

17. A display device, characterized by The display panel further comprises a main board, a display panel and a timing controller, the timing controller is electrically connected with the display panel and the main board respectively, and the timing controller is any one of the timing controllers in claims 1-12.

18. An adjusting apparatus of a display device, characterized by comprising: The adjusting device of the display panel comprises a processor and a memory, the memory stores at least one instruction, at least one program, a code set or an instruction set, and the at least one instruction, the at least one program, the code set or the instruction set is loaded and executed by the processor to realize the adjusting method of the display device in any one of claims 13-16.

19. A computer storage medium, comprising, The computer storage medium stores at least one instruction, at least one program, a code set or an instruction set, and the at least one instruction, the at least one program, the code set or the instruction set is loaded and executed by the processor to realize the adjusting method of the display device in any one of claims 13-16.

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