Driver circuit and display device

Abstract

The present application discloses a driver circuit and a display device. The driver circuit comprises a control module, switching modules, a light-emitting module and a driver module that are connected to each other. Each switching module comprises a plurality of switching circuits, and the switching circuits are used for outputting switching signals; the light-emitting module comprises a plurality of light-emitting elements for receiving the switching signals; the plurality of switching circuits at least include a first switching circuit; and in a same signal frame, the starting times of the switching signals output by at least two first switching circuits are different.

Description

Drive circuit and display device Technical Field

[0001] This application relates to the field of display technology, and in particular to a driving circuit and display device. Background Technology

[0002] Mini LED display panels have significant advantages such as higher brightness, better luminous efficiency, and lower power consumption. Furthermore, the backlight of these Mini LED display panels supports multi-zone dynamic dimming, enabling a contrast ratio of millions, making them a key research focus in the display panel industry.

[0003] To achieve independent dimming of the backlight in multiple zones, each zone's LEDs need to be controlled independently. When the number of zones exceeds the maximum number of channels in the driver chip, multiple driver chips are required to drive the backlight. When multiple driver chips are driving the LEDs to light up, and a certain number of LEDs are simultaneously turned on or off, multiple drive signals of the same frequency are superimposed, resulting in strong harmonics at the harmonics level. This generates significant electromagnetic interference, causing serious damage to the display panel. Summary of the Invention

[0004] This application provides a driving circuit and a display device to alleviate the technical problem of electromagnetic interference in existing driving circuits.

[0005] To address the above issues, the technical solution provided in this application is as follows:

[0006] This application provides a driving circuit, which includes

[0007] Control module;

[0008] Multiple switch modules are connected to the control module, and each switch module includes multiple switch circuits, which are used to output switch signals.

[0009] Multiple light-emitting modules are used to receive the switching signal, one of the light-emitting modules is connected to one of the switching modules, and the light-emitting module includes multiple light-emitting elements;

[0010] Multiple driving modules, one of which is connected to one of the light-emitting modules and the control module;

[0011] Among them, the plurality of switching circuits include at least a first switching circuit, and in the same signal frame, the start times of the switching signals output by at least two of the first switching circuits are different.

[0012] This application also proposes a display device including the above-described driving circuit, the driving circuit comprising:

[0013] Control module;

[0014] Multiple switch modules are connected to the control module, and each switch module includes multiple switch circuits, which are used to output switch signals.

[0015] Multiple light-emitting modules are used to receive the switching signal. Each light-emitting module is connected to a corresponding switching module. Each light-emitting module includes multiple light-emitting elements.

[0016] Multiple driving modules are provided, each driving module corresponds to a switch module, each driving module is connected to a light-emitting module, and the control module is connected to the multiple driving modules.

[0017] Among them, the plurality of switching circuits include at least a first switching circuit, and in the same signal frame, the start times of the switching signals output by the first switching circuits of at least two of the switching modules are different. Attached Figure Description

[0018] Figure 1 is a timing diagram of the driving circuit under PWM dimming in the prior art;

[0019] Figure 2 is a timing diagram of the driving circuit under DC dimming in the prior art;

[0020] Figure 3 is a timing diagram of the driving circuit under time-division row scanning in the prior art;

[0021] Figure 4 is a structural diagram of the driving circuit of this application;

[0022] Figure 5 is a structural diagram of the switching circuit in the driving circuit of this application;

[0023] Figure 6 is a timing diagram of each node in Figure 5;

[0024] Figure 7 shows the potential distribution of internal nodes in delay cells with different resistances and capacitances over time.

[0025] Figure 8 shows the timing diagram of the switching signals output by different switching circuits in the existing drive circuit;

[0026] Figure 9 is a timing diagram of the switching signals output by different switching circuits in the driving circuit of this application;

[0027] Figure 10 is a simplified timing diagram of the drive circuit in Figure 4;

[0028] Figure 11 is a flowchart of the time-division frequency misalignment process of the driving circuit of this application. Embodiments of the present invention

[0029] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application. Furthermore, it should be understood that the specific embodiments described herein are only for illustration and explanation of this application and are not intended to limit this application. In this application, unless otherwise stated, directional terms such as "upper" and "lower" generally refer to the upper and lower positions of the device in its actual use or working state, specifically the drawing directions in the accompanying drawings; while "inner" and "outer" refer to the outline of the device.

[0030] In current technology, to achieve independent dimming of multiple backlight zones, the LEDs in each zone need to be controlled independently. When the number of zones exceeds the maximum number of channels in the driver chip, multiple driver chips are required to drive the backlight. The dimming methods of the driver chips for the LEDs are usually PWM (Pulse Width Modulation) dimming by adjusting the duty cycle of the switch and DC (Direct Current) dimming by adjusting the direct current, as shown in Figures 1 and 2.

[0031] For PWM dimming, when multiple driver chips are driving LED beads to light up, and when a certain number of LED beads are simultaneously turned on or off, multiple drive signals of the same frequency are superimposed, resulting in strong harmonics at the doubling frequency, generating severe electromagnetic interference and causing serious interference to the display panel. Furthermore, as shown in Figure 3, when using line scanning, the switching on and off of the line scanning devices also generates switching electromagnetic interference noise. Therefore, this application proposes a driving circuit to address the above-mentioned technical problems.

[0032] Please refer to Figure 4. This application provides a driving circuit 10, which may include a control module 100, multiple switch modules 200, multiple light-emitting modules 300, and multiple driving modules 400. The multiple switch modules 200 are all connected to the control module 100, one light-emitting module 300 is connected to one switch module 200, and one driving module 400 is connected to one light-emitting module 300. That is, the driving module 400 and the switch module 200 correspond one-to-one, and the multiple driving modules 400 are simultaneously connected to the control module 100.

[0033] In this embodiment, each switch module 200 includes multiple switch circuits 210, which are used to output switch signals. The light-emitting module 300 includes multiple light-emitting elements D, which are used to receive the switch signals output by the switch circuits 210.

[0034] In this embodiment, the plurality of switching circuits 210 include at least a first switching circuit 210a. In the same signal frame, the start times of the switching signals output by at least two first switching circuits 210a are different.

[0035] It should be noted that the start time of the switch signal in this application refers to the moment when the switch signal reaches a high level, or the cutoff moment of the rising edge of the switch signal waveform.

[0036] This application avoids the problem of multiple light-emitting elements D lighting up simultaneously when the driver chip drives the light-emitting element D to light up by making the switching signals received by the light-emitting elements D connected to the same switching circuit 210 have a phase difference, thereby eliminating the technical problem of multiple driving signals of the same frequency superimposed and improving the phenomenon of electromagnetic interference in the driving circuit 10.

[0037] It should be noted that the number of switch modules 200, the number of light-emitting modules 300, and the number of drive modules 400 are all equal. For example, the drive circuit 10 in Figure 4 is illustrated using two switch modules 200, two light-emitting modules 300, and two drive modules 400. Meanwhile, the number of switch circuits 210 in each light-emitting module 300 can be the same or different. Each light-emitting module 300 in this application can be provided with three switch circuits 210, and the output terminal of the switch circuit 210 is connected to the anode of the corresponding light-emitting element D.

[0038] It should be noted that the light-emitting element D in this application can be at least one of LED, Mini LED or Micro LED.

[0039] It should be noted that the driving module 400 is provided with multiple driving output terminals 410. One driving output terminal 410 can be connected to a column of light-emitting elements D in a light-emitting module 300, and one switching circuit 210 can be connected to a row of light-emitting elements D in a light-emitting module 300. For example, in this application, a driving module 400 can be provided with two driving output terminals 410, and a light-emitting module 300 is provided with six light-emitting elements D in a 3*2 distribution, namely D1 to D6. Each switching circuit 210 is simultaneously connected to the anode of two light-emitting elements D located in the same row, and each signal output terminal is electrically connected to the cathode of three light-emitting elements D located in the same column.

[0040] It should be noted that the driving module 400 can be a driving chip, and one driving module 400 is used to drive one light-emitting module 300; the control module 100 can be an FPGA (Field Programmable Gate Array), and the control module 100 is used to output control signals to the switching circuit 210 in the switching module 200. The switching circuit 210 receives the control signals and transmits the anode voltage to the anode of the light-emitting element D, and the driving module 400 transmits the cathode voltage to the light-emitting element D.

[0041] In the driving circuit 10 of this application, the structure of the switching circuit 210 can be the same or different. The following description takes the example of each switching circuit 210 having the same structure.

[0042] Please refer to Figure 5. The switching circuit 210 may include a first delay unit 211, a second delay unit 212, a third delay unit 213, a first transistor T1, a second transistor T2, a third transistor T3, and a voltage divider resistor R0.

[0043] In this embodiment, the first delay unit 211 has a first internal node P1, a first end of the first delay unit 211 is connected to the first control node Q1, and a second end of the first delay unit 211 is connected to the first potential line Vgl; the gate of the first transistor T1 is connected to the first internal node P1, the first electrode of the first transistor T1 is connected to the second control node Q2, and the second electrode of the first transistor T1 is connected to the first potential line Vgl; the gate of the second transistor T2 is connected to the second control node Q2, and the first electrode of the second transistor T2 is connected to the first control node Q1; the second delay unit 212 has a second internal node P2, and the second electrode of the second transistor T2... The first and second ends of the second delay unit 212 are both connected to the first potential line Vgl, which is connected to the second internal node P2. The gate of the third transistor T3 is connected to the second internal node P2, and the first electrode of the third transistor T3 is connected to the second potential line Vgh. The third delay unit 213 has a third internal node P3, the first end of the third delay unit 213 is connected to the second electrode of the third transistor T3, the second end of the third delay unit 213 is connected to the first potential line Vgl, and the third internal node P3 is connected to the anode of the light-emitting element D. The first end of the voltage divider resistor R0 is connected to the first control node Q1, and the second end of the voltage divider resistor R0 is connected to the second control node Q2.

[0044] In this embodiment, the first delay unit 211 includes a first resistor R1 and a first capacitor C1 connected to the first internal node P1. The end of the first resistor R1 away from the first capacitor C1 is connected to the first control node Q1, and the end of the first capacitor C1 away from the first resistor R1 is connected to the first potential line Vgl. The second delay unit 212 includes a second resistor R2 and a second capacitor C2. One end of the second resistor R2 and the second capacitor C2 is connected to the second internal node P2, and the other end of the second resistor R2 and the second capacitor C2 is connected to the first potential line Vgl. The third delay unit 213 includes a third resistor R3 and a third capacitor C3 connected to the third internal node P3. The end of the third resistor R3 away from the third capacitor C3 is connected to the second electrode of the third transistor T3, and the end of the third capacitor C3 away from the third resistor R3 is connected to the first potential line Vgl.

[0045] In the driving circuit 10 of this application, the first transistor T1 can be either an N-type transistor or a P-type transistor, and the second transistor T2 and the third transistor T3 can be either an N-type transistor or a P-type transistor. The following description will be based on the example of the first transistor T1 being an N-type transistor and the second transistor T2 and the third transistor T3 being P-type transistors.

[0046] In this embodiment, the first potential line Vgl can be a constant voltage low-level line, such as a ground line; the second potential line Vgh can be a constant voltage high-level line.

[0047] In this embodiment, the resistance value of the voltage divider resistor R0 can be 10. 5 Ohms to 10 6 ohm.

[0048] In this embodiment, the output of the control module 100 is connected to the first control node Q1.

[0049] The operation of the switching circuit 210 in Figure 5 is described below based on the timing diagram in Figure 6.

[0050] In the first stage, when the control signal output by the control module 100 is high, that is, the potential of the first control node Q1 is high, the first internal node P1 is connected in series with the first control node Q1, so the first internal node P1 is high; since the first transistor T1 is an N-type transistor, that is, the first transistor T1 is turned on by the high level of the first internal node P1, the second control node Q2 will be connected to the first potential line Vgl, and since the voltage divider resistor R0 is a resistor with a large resistance value, the voltage of the first control node Q1 is divided by the voltage divider resistor R0, so the second control node Q2 is low; since the second transistor T2 is a P-type transistor, the second transistor T2 is turned on by the low level of the second control node Q2, the second internal node P2 will be connected to the first control node Q1, and the potential of the second internal node P2 is high; while since the third transistor T3 is a P-type transistor, the third transistor T3 is cut off, the third internal node P3 outputs a low level to the corresponding light-emitting element D, and the light-emitting element D does not emit light.

[0051] In the second stage, when the control signal output by the control module 100 is high, that is, the potential of the first control node Q1 is low, the first internal node P1 and the first control node Q1 are connected in series, and due to the presence of the first capacitor C1, the discharge of the first capacitor C1 maintains the first internal node P1 at the high level for a period of time. Afterwards, the potential of the first internal node P1 gradually decreases, and when the voltage difference between the potential of the first internal node P1 and the first potential line Vgl is less than the threshold voltage of the first transistor T1, the first transistor T1 is turned off, and the potential of the first internal node P1 gradually decreases; at the same time, when the second control node Q2 is low, the potential of the second internal node P2 is pulled down by the low potential of the first control node Q1, and due to the second capacitor C2... Discharge occurs when the second internal node P2 remains at a high level for a period of time after the first control node Q1 goes low. The potential of the second internal node P2 continues to decrease. When the potential of the second internal node P2 drops to the threshold voltage of the third transistor T3, the third transistor T3 turns on, and the third internal node P3 connects to the second potential line Vgh. Due to the presence of the third capacitor C3, the pull-up of the potential of the third internal node P3 is delayed until the second internal node P2 is at a low level. As the third capacitor C3 charges, the potential of the third internal node P3 gradually increases until the potential of the third internal node P3 is equal to the voltage of the second potential line Vgh. The third internal node P3 then outputs a high level to the corresponding light-emitting element D, and the light-emitting element D emits light.

[0052] In the third stage, when the control signal output by the control module 100 is high, that is, the potential of the first control node Q1 is high, the first internal node P1 is connected in series with the first control node Q1, and due to the presence of the first capacitor C1, the charging of the first capacitor C1 causes the potential of the first internal node P1 to gradually increase; when the first transistor T1 is off, since the resistance of the first transistor T1 is greater than the resistance of the voltage divider resistor R0, the potential of the second control node Q2 is the same as that of the first control node Q1, and the potential of the second control node Q2 is high, that is, the second transistor T2 is off. At this time, the second internal node P2 is connected to the first potential line Vgl through the second resistor R2, and the second internal node P2 is continuously at a low level. The third transistor T3 is turned on, and the potential of the third internal node P3 is the same as the voltage of the second potential line Vgh. The third internal node P3 outputs a high level to the corresponding light-emitting element D, and the light-emitting element D emits light; as the potential of the first internal node P1 increases... When the voltage reaches a high level, the first transistor T1 is turned on by the high level of the first internal node P1. The second control node Q2 is connected to the first potential line Vgl. Since the voltage divider resistor R0 is a resistor with a large resistance, the voltage of the first control node Q1 is divided by the voltage divider resistor R0. Therefore, the second control node Q2 is at a low level. Thus, the second transistor T2 is turned on by the low level of the second control node Q2. The second internal node P2 is connected to the first control node Q1. Due to the presence of the second capacitor C2, the potential of the second internal node P2 gradually increases to a high level. When the potential of the second internal node P2 is greater than the threshold voltage of the third transistor T3, the third transistor T3 is turned off. The third internal node P3 and the second potential line Vgh are disconnected. The third capacitor C3 discharges to maintain the high potential of the third internal node P3 for a period of time. After that, the potential of the third internal node P3 gradually decreases to a low level. The third internal node P3 outputs a low level to the corresponding light-emitting element D, and the light-emitting element D does not emit light.

[0053] In the structures of Figures 5 and 6, the combination of the first resistor R1 and the first capacitor C1, the combination of the second resistor R2 and the second capacitor C2, and the combination of the third resistor R3 and the third capacitor C3 each constitute a resistor-capacitor delay circuit. In Figure 6, the absolute value of the slope of the rising or falling edge of the first internal node P1, the second internal node P2, and the third internal node P3 is negatively correlated with the product of the corresponding resistor and capacitor.

[0054] For example, the product of the resistance of the first resistor R1 and the capacitance of the first capacitor C1 is the first product; the product of the resistance of the second resistor R2 and the capacitance of the second capacitor C2 is the second product; and the product of the resistance of the third resistor R3 and the capacitance of the third capacitor C3 is the third product. When the first product, the second product, and the third product are all equal, the absolute values ​​of the slopes of the rising or falling edges of the first internal node P1, the second internal node P2, and the third internal node P3 are all equal. When the first product is the smallest and the third product is the largest, the absolute value of the slope of the rising or falling edge of the first internal node P1 is the largest, and the absolute value of the slope of the rising or falling edge of the third internal node P3 is the smallest.

[0055] Similarly, please refer to Figure 7. Figure 7 is a graph showing the potential distribution of internal nodes in delay units with different resistors and capacitors over time. The horizontal axis represents time, and the vertical axis represents voltage. There are a total of 9 curves in Figure 7. In the direction from curve A to curve B, the product of resistance and capacitance in the delay unit gradually increases, and the absolute value of the slope of the rising or falling edge of the waveform gradually decreases, that is, the rising or falling edge of the same curve gradually becomes gentler.

[0056] In this embodiment, the product of the resistance of the first resistor R1 and the capacitance of the first capacitor C1 can be less than the product of the resistance of the third resistor R3 and the capacitance of the third capacitor C3, and the product of the resistance of the second resistor R2 and the capacitance of the second capacitor C2 can be less than the product of the resistance of the third resistor R3 and the capacitance of the third capacitor C3. That is, the absolute value of the slope of the waveform of the third internal node P3 in this application is the smallest, and the rising or falling edge is the gentlest, so as to reduce the radiation energy of the light-emitting element D due to instantaneous switching.

[0057] In this embodiment, the plurality of switch modules 200 include a first switch module 200a and a second switch module 200b, and both the first switch module 200a and the second switch module 200b include at least a first switch circuit 210a.

[0058] In this embodiment, the control module 100 may include multiple switch output terminals, and each switch output terminal is connected to a switch circuit 210 in each switch module 200. For example, the control module 100 includes at least a first switch output terminal 101, and the first switch output terminals 101 are all connected to the first control node Q1 of the first switch circuit 210a in the first switch module 200a and the second switch module 200b. In the same signal frame, the rising edge of the waveform of the switch signal output by the first switch circuit 210a in the first switch module 200a has a first slope, and the rising edge of the waveform of the switch signal output by the first switch circuit 210a in the second switch module 200b has a second slope. The first slope and the second slope are different.

[0059] For example, in the structure shown in Figure 4, both the first switch module 200a and the second switch module 200b may include a first switch circuit 210a, a second switch circuit 210b, and a third switch circuit 210c. The multiple light-emitting modules 300 may include a first light-emitting module 300a and a second light-emitting module 300b. The control module 100 may be provided with a first switch output terminal 101, a second switch output terminal 102, and a third switch output terminal 103. That is, the first switch output terminal 101 is connected to the first control node Q1 of the first switch circuit 210a in the first switch module 200a and the second switch module 200b, the second switch output terminal 102 is connected to the first control node Q1 of the second switch circuit 210b in the first switch module 200a and the second switch module 200b, and the third switch output terminal 103 is connected to the first control node Q1 of the third switch circuit 210c in the first switch module 200a and the second switch module 200b. The following description only uses the first switch output terminal 101 and the first switch circuit 210a as examples.

[0060] In the prior art, referring to Figure 8, when the control module receives the start signal Vs, it transmits control signals to the first switch circuit 210a in the first switch module 200a and the second switch module 200b simultaneously through the first switch output terminal 101. The switch signal SW1 transmitted by the first switch circuit 210a to the light-emitting element D is at a high level. That is, the high level simultaneously reaches the light-emitting element D connected to the first switch circuit 210a in each switch module 200, and the light-emitting element D will be turned on at the same time, resulting in relatively large noise.

[0061] In this embodiment, referring to Figure 9, in the first switch module 200a, the rising edge of the waveform of the switch signal output by the first switch circuit 210a has a first slope, and in the second switch module 200b, the rising edge of the waveform of the switch signal output by the first switch circuit 210a has a second slope. Since the first slope and the second slope are different, the time when the third internal node P3 in the first switch circuit 210a in the first switch module 200a reaches a high level is different from the time when the third internal node P3 in the first switch circuit 210a in the second switch module 200b reaches a high level. The two are staggered, which avoids the simultaneous activation of the light-emitting element D, eliminates the technical problem of multiple driving signals of the same frequency superimposed, and improves the phenomenon of electromagnetic interference in the driving circuit 10.

[0062] It should be noted that, for ease of description, Figure 9 does not include the difference in the slope of the rising edge of the third internal node P3 in different switch modules 200. Only the starting time of the third internal node P3 reaching the high level is included. In reality, the starting time of the rising edge of the third internal node P3 in different switch modules 200 is the same, but the cutoff time of reaching the high level is different.

[0063] It should be noted that the SWn signal in Figures 8 and 9 is the switching signal transmitted by the nth switching circuit 210 in the switching module 200.

[0064] In this embodiment, the third capacitor C3 of the first switching circuit 210a in the first switching module 200a can be the same as the third capacitor C3 of the first switching circuit 210a in the second switching module 200b. Simultaneously, the resistance value of the third resistor R3 of the first switching circuit 210a in the first switching module 200a is less than the resistance value of the third resistor R3 of the first switching circuit 210a in the second switching module 200b; or, the third resistor R3 of the first switching circuit 210a in the first switching module 200a can be the same as the third capacitor C3 of the first switching circuit 210a in the second switching module 200b. The third resistor R3 in the switching circuit 210a is the same, and the capacitance of the third capacitor C3 in the first switching module 200a is less than the capacitance of the third capacitor C3 in the first switching circuit 210a in the second switching module 200b; or, the product of the resistance value of the third resistor R3 and the capacitance value of the third capacitor C3 in the first switching circuit 210a in the first switching module 200a is less than the product of the resistance value of the third resistor R3 and the capacitance value of the third capacitor C3 in the first switching circuit 210a in the second switching module 200b.

[0065] In this embodiment, in addition to adjusting the third resistor R3 and the third capacitor C3, this application can also make the product of the resistance value of the first resistor R1 and the capacitance value of the first capacitor C1 in the first switch circuit 210a of the first switch module 200a less than the product of the resistance value of the first resistor R1 and the capacitance value of the first capacitor C1 in the first switch circuit 210a of the second switch module 200b; or / and the product of the resistance value of the second resistor R2 and the capacitance value of the second capacitor C2 in the first switch circuit 210a of the first switch module 200a less than the product of the resistance value of the second resistor R2 and the capacitance value of the second capacitor C2 in the first switch circuit 210a of the second switch module 200b.

[0066] Therefore, the adjustment of the third resistor R3 and the third capacitor C3 is to adjust the cutoff time when the rising edge of the third internal node P3 reaches the high level, while the adjustment of the first resistor R1 and the first capacitor C1, that is, the adjustment of the second resistor R2 and the second capacitor C2, is to adjust the difference in the start time of the rising edge of the third internal node P3. That is, this application can make the slope of the rising edge of the third internal node P3 in different switching modules 200 the same, but the start time of the rising edge is designed differently to avoid the light-emitting element D from being turned on at the same time, thus eliminating the technical problem of multiple driving signals of the same frequency superimposed.

[0067] Please refer to Figure 4. The multiple light-emitting elements D include at least a first light-emitting element and a second light-emitting element. The anodes of the first light-emitting element and the second light-emitting element are both connected to the third internal node P3 of the same first switching circuit 210a. The driving module 400 includes at least a first driving output terminal 410a and a second driving output terminal 410b. The cathode of the first light-emitting element is connected to the first driving output terminal 410a, and the cathode of the second light-emitting element is connected to the second driving output terminal 410b. In a signal frame, the driving signal output by the first driving output terminal 410a and the driving signal output by the second driving output terminal 410b are different.

[0068] In this embodiment, for example, the first light-emitting element can be light-emitting element D1 in the light-emitting module 300, the second light-emitting element can be light-emitting element D2 in the light-emitting module 300, and the driving module 400 can include n driving output terminals 410. This application only uses two driving output terminals 410 as an example for description. The first driving output terminal 410a is connected to the first column of light-emitting elements D1 to D3, and the second driving output terminal 410b is connected to the second column of light-emitting elements D4 to D6.

[0069] In this embodiment, the control module 100 further includes a brightness output terminal 120a and a synchronization output terminal 120b. Each driving module 400 includes a brightness receiving terminal 420a and a synchronization receiving terminal 420b. The brightness output terminal 120a is connected to the brightness receiving terminal 420a in each driving module 400, and the synchronization output terminal 120b is connected to the synchronization receiving terminal 420b in each driving module 400.

[0070] Referring specifically to the timing diagram shown in Figure 10, before each signal frame is activated, the brightness output terminal 120a outputs a brightness signal to the brightness receiving terminal 420a. Based on this brightness signal, the driving module 400 outputs the same or different cathode voltages to the light-emitting elements D in different columns through each driving output terminal 410. At the same time, the synchronization output terminal 120b outputs a synchronization signal to the synchronization receiving terminal 420b. For example, if the control module 100 has four or more built-in scanning frequencies, the control module 100 can select a suitable scanning frequency according to the display state of the display device. The scanning frequency in this application is mainly adjusted by the frequency of the control signal output by the switch output terminal in the control module 100. Taking PWM dimming and a scanning frequency of 480Hz as an example, within 1 / 480s, the light-emitting elements D1 to D3 need to be lit once each, and at the same time, the driving output terminal 410 needs to synchronously transmit the cathode signal to the corresponding light-emitting element D.

[0071] Please refer to Figure 11 for the specific working process. Before each signal frame is activated, the control module 100 first selects an appropriate scanning frequency according to the display state of the display device to configure the frequency. Secondly, the control module 100 configures the drive current to transmit the same or different cathode voltages to the drive module 400. Thirdly, the synchronization output terminal 120b of the control module 100 outputs a synchronization signal to the synchronization receiving terminal 420b of the drive module 400. Finally, the control module 100 outputs a control signal to the first control node of the switch module 200.

[0072] It should be noted that during the next scan frame, the control module of this application can be configured with different scan frequencies. For example, when the control module 100 has four built-in scan frequencies, four different scan frequencies can be configured in four scan stages to achieve time-division frequency-shifting scanning, avoid the concentration of scan energy frequency points, and further reduce the technical problem of electromagnetic interference.

[0073] For example, referring to Figure 4, the first switch output terminal simultaneously outputs the same first control signal S1 to the first switch circuit 210a of the first switch module 200a and the second switch module 200b. The first switch circuit 210a of the first switch module 200a and the second switch module 200b outputs a first switch signal K1 to the light-emitting elements D1 and D4 in the light-emitting module 300 according to the first control signal S1. The second switch output terminal simultaneously outputs the same second control signal S2 to the second switch circuit 210b of the first switch module 200a and the second switch module 200b. The second switching circuit 210b of module 200a and the second switching module 200b outputs a second switching signal K2 to the light-emitting elements D2 and D5 in the light-emitting module 300 according to the second control signal S2; the third switch output terminal simultaneously outputs the same third control signal S3 to the third switching circuit 210c of the first switching module 200a and the second switching module 200b, and the third switching circuit 210c of the first switching module 200a and the second switching module 200b outputs a third switching signal K3 to the light-emitting elements D3 and D6 in the light-emitting module 300 according to the third control signal S3.

[0074] In this embodiment, in each switching module 200, the switching signals output by multiple switching circuits 210 in the same scan frame have the same frequency, and the switching signals output by multiple switching circuits 210 in two adjacent scan frames have different frequencies.

[0075] For example, in the first scan frame, the control module 100 outputs a first control signal S1, a second control signal S2, and a third control signal S3 with a first frequency to the corresponding switch circuit 210 through the switch output terminal. The switch circuit 210 outputs a first switch signal K1, a second switch signal K2, and a third switch signal K3 according to the corresponding first control signal S1, second control signal S2, and third control signal S3, respectively. Since the first control signal S1, second control signal S2, and third control signal S3 have the same frequency, the frequencies of the first switch signal K1, second switch signal K2, and third switch signal K3 are also the same. The frequencies can be the same; similarly, in the second scan frame, the control module 100 outputs a first control signal S1, a second control signal S2, and a third control signal S3 with a second frequency to the corresponding switch circuit 210 through the switch output terminal. The frequencies of the first switch signal K1, the second switch signal K2, and the third switch signal K3 can be the same, while the first frequency and the second frequency of this application can be different, so as to realize that the switch signals output by the switch circuit 210 have different frequencies in different scan frames, so as to realize the time-division frequency-shifting scan of the drive circuit, avoid the frequency point concentration of the scan energy, and reduce the technical problem of electromagnetic interference.

[0076] Similarly, when the control module 100 has four built-in scanning frequencies and has four or more switch modules 200, different scanning frequencies can be configured in four consecutive scanning stages using these four scanning frequencies. For example, in the first scanning frame, the control module 100 can configure a first control signal S1 with a first frequency to all switch circuits 210; in the second scanning frame, the control module 100 can configure a second control signal S2 with a second frequency to all switch circuits 210; in the third scanning frame, the control module 100 can configure a third control signal S3 with a third frequency to all switch circuits 210; in the fourth scanning frame, the control module 100 can configure a fourth control signal (not shown) with a fourth frequency to all switch circuits 210; and in the fifth scanning frame, the control module 100 can configure a first control signal S1 with a first frequency to all switch circuits 210. Subsequent scanning frames can configure the scanning frequency according to the above scanning method.

[0077] It should be noted that, in one scan frame of this application, the time required for all light-emitting elements to complete one scan in the driving circuit is represented.

[0078] In this embodiment, in each switching module 200, the switching signals output by two adjacent switching circuits 210 have different frequencies. For example, referring to FIG4, in each scanning stage, the control module 100 outputs a first control signal S1 with a first frequency to the first switching circuit 210a through the first switch output terminal 101, and the first switching circuit 210a outputs a first switching signal K1 according to the first control signal S1; the control module 100 outputs a second control signal S2 with a second frequency to the second switching circuit 210b through the second switch output terminal 102, and the second switching circuit 210b outputs a second switching signal K2 according to the second control signal S2; the control module 100 outputs a second control signal S2 with a second frequency to the third switching circuit through the third switch output terminal 103. The third control signal S3 with a third frequency is output by the third switch circuit 210c. The third switch circuit 210c outputs a third switch signal K3 according to the third control signal S3. Since the frequencies of the first control signal S1, the second control signal S2 and the third control signal S3 are all different, the frequencies of the first switch signal K1, the second switch signal K2 and the third switch signal K3 are also different. This is to achieve that the switch signals output by two adjacent switch circuits 210 in the same scanning frame have different frequencies, so as to realize the time-division frequency-shifting scanning of the drive circuit 10, avoid the frequency point concentration of scanning energy and reduce the technical problem of electromagnetic interference.

[0079] Similarly, when the control module 100 has four built-in scanning frequencies and the switch module 200 has four or more switch circuits 210, the four scanning frequencies are used to configure different scanning frequencies in four consecutive switch circuits 210. For example, in the first signal frame, the control module 100 can configure a first control signal S1 with a first frequency to all first switch circuits 210a; in the second signal frame, the control module 100 can configure a second control signal S2 with a second frequency to all second switch circuits 210b; in the third signal frame, the control module 100 can configure a third control signal S3 with a third frequency to all third switch circuits 210c; in the fourth signal frame, the control module 100 can configure a fourth control signal (not shown) with a fourth frequency to all fourth switch circuits (not shown); in the fifth signal frame, the control module 100 can configure a first control signal S1 with a first frequency to all fifth switch circuits (not shown); and subsequent signal frames can configure the scanning frequency according to the above scanning method.

[0080] It should be noted that, in a signal frame of this application, the time required for all light-emitting elements connected to the same switch output terminal to complete one scan is represented by the signal frame driving circuit.

[0081] This application also proposes a display device including the aforementioned driving circuit. The display device can be a liquid crystal display panel or a direct-view display panel. The display device can include electronic devices such as mobile phones, televisions, and laptops.

[0082] In the above embodiments, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.

[0083] The technical solutions provided in the embodiments of this application have been described in detail above. Specific examples have been used to illustrate the principles and implementation methods of this application. The descriptions of the embodiments above are only for the purpose of helping to understand the technical solutions and core ideas of this application. Those skilled in the art should understand that they can still modify the technical solutions described in the foregoing embodiments or make equivalent substitutions for some of the technical features. These modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions in the embodiments of this application.

Claims

1. A driving circuit, comprising: Control module; Multiple switch modules are connected to the control module, and each switch module includes multiple switch circuits, which are used to output switch signals. Multiple light-emitting modules are used to receive the switching signal. Each light-emitting module is connected to a corresponding switching module. Each light-emitting module includes multiple light-emitting elements. Multiple driving modules are provided, each driving module corresponds to a switch module, each driving module is connected to a light-emitting module, and the control module is connected to the multiple driving modules. Among them, the plurality of switching circuits include at least a first switching circuit, and in the same signal frame, the start times of the switching signals output by the first switching circuits of at least two of the switching modules are different.

2. The driving circuit according to claim 1, wherein, The switching circuit includes: A first delay unit has a first internal node, a first end of the first delay unit is connected to a first control node, and a second end of the first delay unit is connected to a first potential line; A first transistor, wherein the gate of the first transistor is connected to the first internal node, the first electrode of the first transistor is connected to the second control node, and the second electrode of the first transistor is connected to the first potential line; The second transistor has its gate connected to the second control node and its first electrode connected to the first control node; The second delay unit has a second internal node, the second electrode of the second transistor is connected to the second internal node, and the first end and the second end of the second delay unit are both connected to the first potential line; The third transistor has its gate connected to the second internal node and its first electrode connected to the second potential line; A third delay unit, having a third internal node, wherein a first end of the third delay unit is connected to the second electrode of the third transistor, a second end of the third delay unit is connected to the first potential line, and the third internal node is connected to the anode of the light-emitting element; and A voltage divider resistor, wherein the first end of the voltage divider resistor is connected to the first control node, and the second end of the voltage divider resistor is connected to the second control node.

3. The driving circuit according to claim 2, wherein, The first delay unit includes a first resistor and a first capacitor connected to the first internal node. The end of the first resistor away from the first capacitor is connected to the first control node, and the end of the first capacitor away from the first resistor is connected to the first potential line. The second delay unit includes a second resistor and a second capacitor. One end of the second resistor and the second capacitor is connected to the second internal node, and the other end of the second resistor and the second capacitor is connected to the first potential line. The third delay unit includes a third resistor and a third capacitor connected to the third internal node. The end of the third resistor away from the third capacitor is connected to the second electrode of the third transistor, and the end of the third capacitor away from the third resistor is connected to the first potential line.

4. The driving circuit according to claim 3, wherein, The first potential line is a constant voltage low-level line, and the second potential line is a constant voltage high-level line.

5. The driving circuit according to claim 3, wherein, The resistance of the voltage divider resistor is 10. 5 Ohms to 10 6 ohm.

6. The driving circuit according to claim 3, wherein, The product of the resistance of the first resistor and the capacitance of the first capacitor is less than the product of the resistance of the third resistor and the capacitance of the third capacitor, and the product of the resistance of the second resistor and the capacitance of the second capacitor is less than the product of the resistance of the third resistor and the capacitance of the third capacitor.

7. The driving circuit according to claim 3, wherein, The plurality of switch modules include a first switch module and a second switch module, wherein both the first switch module and the second switch module include at least the first switch circuit; The control module includes at least a first switch output terminal, which is connected to the first control node of the first switch circuit in the first switch module and the second switch module. The product of the resistance value of the first resistor and the capacitance value of the first capacitor in the first switching circuit of the first switching module is less than the product of the resistance value of the first resistor and the capacitance value of the first capacitor in the first switching circuit of the second switching module; or / and The product of the resistance value of the second resistor and the capacitance value of the second capacitor in the first switching circuit of the first switching module is less than the product of the resistance value of the second resistor and the capacitance value of the second capacitor in the first switching circuit of the second switching module; or / and In the first switch module, the product of the resistance value of the third resistor and the capacitance value of the third capacitor in the first switch circuit is less than the product of the resistance value of the third resistor and the capacitance value of the third capacitor in the second switch module.

8. The driving circuit according to claim 7, wherein, In the same signal frame, the rising edge of the waveform of the switch signal output by the first switch circuit in the first switch module has a first slope, and the rising edge of the waveform of the switch signal output by the first switch circuit in the second switch module has a second slope, wherein the first slope and the second slope are different.

9. The driving circuit according to claim 7, wherein, The resistance value of the third resistor in the first switch circuit of the first switch module is less than the resistance value of the third resistor in the first switch circuit of the second switch module.

10. The driving circuit according to claim 7, wherein, The capacitance of the third capacitor in the first switching circuit of the first switching module is less than the capacitance of the third capacitor in the first switching circuit of the second switching module.

11. The driving circuit according to claim 2, wherein, The plurality of light-emitting elements include at least a first light-emitting element and a second light-emitting element, wherein the anode of the first light-emitting element and the anode of the second light-emitting element are both connected to the third internal node of the same first switching circuit.

12. The driving circuit according to claim 11, wherein, The driving module includes at least a first driving output terminal and a second driving output terminal. The cathode of the first light-emitting element is connected to the first driving output terminal, and the cathode of the second light-emitting element is connected to the second driving output terminal. In a signal frame, the driving signal output by the first driving output terminal and the driving signal output by the second driving output terminal are different.

13. The driving circuit according to claim 2, wherein, The first transistor is either an N-type transistor or a P-type transistor, and the second transistor and the third transistor are either N-type transistors or P-type transistors.

14. The driving circuit according to claim 1, wherein, The control module includes multiple switch output terminals, and one of the switch output terminals is connected to a switch circuit in each of the switch modules. Among the multiple switch modules, the frequency of the switch signal output by the switch circuit connected to the same switch output terminal is the same.

15. The driving circuit according to claim 14, wherein, In each of the aforementioned switching modules, the switching signals output by the multiple switching circuits in the same scan frame have the same frequency, and the switching signals output by the multiple switching circuits in two adjacent scan frames have different frequencies.

16. The driving circuit according to claim 14, wherein, In each of the aforementioned switching modules, the frequencies of the switching signals output by two adjacent switching circuits are different.

17. The driving circuit according to claim 1, wherein, The control module further includes a brightness output terminal and a synchronization output terminal. Each driving module includes a brightness receiving terminal and a synchronization receiving terminal. The brightness output terminal is connected to the brightness receiving terminal in each driving module, and the synchronization output terminal is connected to the synchronization receiving terminal in each driving module.

18. The driving circuit according to claim 1, wherein, The light-emitting element is at least one of LED, Mini LED, or Micro LED.

19. A display device comprising a driving circuit; wherein, The driving circuit includes: Control module; Multiple switch modules are connected to the control module, and each switch module includes multiple switch circuits, which are used to output switch signals. Multiple light-emitting modules are used to receive the switching signal. Each light-emitting module is connected to a corresponding switching module. Each light-emitting module includes multiple light-emitting elements. Multiple driving modules are provided, each driving module corresponds to a switch module, each driving module is connected to a light-emitting module, and the control module is connected to the multiple driving modules. Among them, the plurality of switching circuits include at least a first switching circuit, and in the same signal frame, the start times of the switching signals output by the first switching circuits of at least two of the switching modules are different.

20. The display device according to claim 19, wherein, The control module includes multiple switch output terminals, one of which is connected to a switch circuit in each of the switch modules. In the multiple switch modules, the frequency of the switch signal output by the switch circuit connected to the same switch output terminal is the same. In each of the switching modules, the switching signals output by the multiple switching circuits in the same scan frame have the same frequency, and the switching signals output by the multiple switching circuits in two adjacent scan frames have different frequencies; or, in each of the switching modules, the switching signals output by two adjacent switching circuits have different frequencies.

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