Semiconductor device and display device

Abstract

The purpose of the present invention is to provide a semiconductor device that minimizes any deviation in the output voltage. This semiconductor device has first to fourth amplifiers, first to sixth resistance elements, and a selector circuit. The selector circuit has first and second input terminals. An input terminal of the first amplifier is connected to an input terminal of the second amplifier via the first resistance element, the input terminal of the second amplifier is connected to an input terminal of the third amplifier via the second resistance element, and the input terminal of the third amplifier is connected to an input terminal of the fourth amplifier via the third resistance element. An output terminal of the first amplifier is connected to an output terminal of the second amplifier via the fourth resistance element, the output terminal of the second amplifier is connected to an output terminal of the third amplifier via the fifth resistance element, and the output terminal of the third amplifier is connected to an output terminal of the fourth amplifier via the sixth resistance element. The output terminal of the second amplifier is connected to the first input terminal, and the output terminal of the third amplifier is connected to the second input terminal.

Description

Semiconductor device and display device

[0001] One embodiment of the present invention relates to a semiconductor device and a display device.

[0002] Note that one embodiment of the present invention is not limited to the above technical field. The technical field of the invention disclosed in this specification and the like relates to an object, an operating method, or a manufacturing method. Alternatively, one embodiment of the present invention relates to a process, a machine, manufacture, or a composition of matter. Therefore, specific examples of the technical field of one embodiment of the present invention disclosed in this specification include semiconductor devices, display devices (including liquid crystal display devices), light-emitting devices, power storage devices, imaging devices, memory devices, processing devices, signal processing devices, sensors, arithmetic devices (including processors), electronic devices, systems, driving methods thereof, manufacturing methods thereof, and inspection methods thereof.

[0003] In recent years, improvements have been made in various aspects to display devices included in wearable devices, monitors, mobile phones (e.g., smartphones), wristwatch-type information terminals, tablet-type information terminals, notebook PCs (personal computers), etc. for XR (Extended Reality or Cross Reality) such as VR (Virtual Reality) and AR (Augmented Reality). For example, display devices are being developed to improve screen resolution, color reproducibility (NTSC ratio), size of driving circuits, and power consumption.

[0004] For example, wearable devices for XR are preferably equipped with high-definition (high pixel density) display devices to enhance the sense of immersion and realism for users. High-definition display devices can make pixels less visible to users and reduce the graininess of images displayed on the display device. In display devices with many fine pixel circuits, the number of pixel circuits connected to a single data line (sometimes referred to herein as a source line, image signal line, etc.) increases, making attenuation of image signals transmitted to the data line more likely. Patent Document 1 discloses an invention in which a display device includes a data driver circuit (sometimes referred to herein as a source driver circuit, etc.) and a load circuit in each of multiple display units, and the display units, data driver circuit, and load circuit are overlapped to reduce the number of columns per display unit and suppress attenuation of image signals transmitted to the data line. Patent Document 1 also discloses a configuration in which a buffer amplifier (sometimes referred to herein as an amplifier or amplifier) ​​for amplifying image signals is not connected to the data line, which can suppress attenuation of image signals.

[0005] International Publication No. 2021 / 191721

[0006] Takashi Koida, "High Mobility Transparent Conductive Films," National Institute of Advanced Industrial Science and Technology, AIST Photovoltaic Power Generation Research Results Report 2019, Internet <URL: https: / / unit.aist.go.jp / rpd-envene / PV / ja / results / 2019 / oral / T13.pdf> Y. Park et al., ISSCC, pp. 432-433, 2024. J. Ahn et al., ISSCC, pp. 434-435, 2024. G.-W. Lim et al., ISSCC, pp. 110-111, 2022.

[0007] In display devices provided in wearable devices for XR, increasing the gradation level allows for smoother color shading, thereby providing images that are closer to reality. Increasing the gradation level can be achieved by, for example, increasing the resolution of a digital-to-analog conversion circuit provided in the source driver circuit of the display device.

[0008] There are various types of digital-to-analog conversion circuits, one example of which is a resistive voltage divider method using a resistor string in which resistor elements are connected in series, or a two-stage resistive voltage divider method in which two resistor strings and multiple amplifiers are prepared, and input terminals of the amplifiers are connected to each of the junctions between the resistor elements of one resistor string, and output terminals of the amplifiers are connected to each of the junctions between the resistor elements of the other resistor string.

[0009] In this two-stage resistive voltage divider digital-analog conversion circuit, the multiple amplifiers shorten the time required for charging and discharging the data lines. Therefore, the digital-analog conversion circuit can handle, for example, large changes in luminance based on the image signal transmitted to the data lines, in other words, large changes in the potential corresponding to the image signal. Therefore, the digital-analog conversion circuit can rewrite images with large changes in luminance within a specified frame.

[0010] Note that each of the multiple amplifiers described above generates a significant transient current at each connection point between the resistor elements of the other resistor string, which is affected by the parasitic resistance between the output terminal of the amplifier and the connection point. This causes a voltage drop at the connection point, which can cause the potential at the connection point to fluctuate from the potential that should be output. In particular, among the transient currents flowing from the multiple amplifiers, the transient current flowing from the top amplifier, which outputs a potential corresponding to the MSB (Most Significant Bit), and the transient current flowing from the bottom amplifier, which outputs a potential corresponding to the LSB (Least Significant Bit), are dominantly large. This can cause the potential corresponding to the MSB to be lower than the potential that should be output, and the potential corresponding to the LSB to be higher than the potential that should be output. The potentials output by the digital-to-analog conversion circuit, particularly the potential corresponding to the MSB or the LSB, deviate from the target potential, resulting in a deviation in the brightness of the image displayed on the display device. This can degrade the display quality of the image displayed by the display device.

[0011] An object of one embodiment of the present invention is to provide a semiconductor device in which a deviation in output potential is suppressed.An object of one embodiment of the present invention is to provide a semiconductor device with a reduced circuit area.An object of one embodiment of the present invention is to provide a display device including the semiconductor device.An object of one embodiment of the present invention is to provide a display device with high display quality.An object of one embodiment of the present invention is to provide a display device with a high driving frequency.An object of one embodiment of the present invention is to provide a novel semiconductor device or a novel display device.

[0012] Note that the problem of one embodiment of the present invention is not limited to the above problem. The above problem does not preclude the existence of other problems. Note that the other problems are problems not mentioned in this section, which will be described below. Problems not mentioned in this section can be derived by a person skilled in the art from the description in the specification or drawings, and can be appropriately extracted from these descriptions. Note that one embodiment of the present invention solves at least one of the above problem and other problems, and does not necessarily solve all of the above problem and other problems.

[0013] In a two-stage resistive voltage divider digital-to-analog conversion circuit, as described above, the transient currents flowing from the top amplifier corresponding to the MSB and the bottom amplifier corresponding to the LSB are large, while the transient currents flowing from the amplifiers connected near the center of the two resistor strings are small.

[0014] Therefore, in order to suppress the deviation of the potentials corresponding to the MSB and LSB, we propose a configuration in which multiple new resistor elements and multiple amplifiers are added to the conventional structure of two resistor strings and multiple existing amplifiers. The existing multiple amplifiers are designated as the second amplifier and the third amplifier, and one of the two resistor strings includes the second resistor element, while the other includes the fifth resistor element. The newly added multiple resistor elements are designated as the first resistor element, the third resistor element, the fourth resistor element, and the sixth resistor element, and the newly added multiple amplifiers are designated as the first amplifier and the fourth amplifier.

[0015] The second amplifier corresponds to the input and output of the MSB potential, and the first terminal of the first resistor element and the first terminal of the fourth resistor element are connected to the input and output terminals of the second amplifier, respectively. The second terminal of the first resistor element is connected to the input terminal of the first amplifier, and the second terminal of the fourth resistor element is connected to the output terminal of the first amplifier. The third amplifier corresponds to the input and output of the LSB potential, and the first terminal of the third resistor element and the first terminal of the sixth resistor element are connected to the input and output terminals of the third amplifier, respectively. The second terminal of the third resistor element is connected to the input terminal of the fourth amplifier, and the second terminal of the sixth resistor element is connected to the output terminal of the fourth amplifier.

[0016] A typical example of a configuration according to one embodiment of the present invention will be described below.

[0017] (1) One aspect of the present invention is a semiconductor device including a first amplifier, a second amplifier, a third amplifier, a fourth amplifier, a first resistor element, a second resistor element, a third resistor element, a fourth resistor element, a fifth resistor element, a sixth resistor element, and a selector circuit, wherein the selector circuit has a first input terminal and a second input terminal.

[0018] The input terminal of the first amplifier is electrically connected to the input terminal of the second amplifier via a first resistive element, the input terminal of the second amplifier is electrically connected to the input terminal of the third amplifier via a second resistive element, and the input terminal of the third amplifier is electrically connected to the input terminal of the fourth amplifier via a third resistive element. The output terminal of the first amplifier is electrically connected to the output terminal of the second amplifier via a fourth resistive element, the output terminal of the second amplifier is electrically connected to the output terminal of the third amplifier via a fifth resistive element, and the output terminal of the third amplifier is electrically connected to the output terminal of the fourth amplifier via a sixth resistive element. The output terminal of the second amplifier is electrically connected to the first input terminal, and the output terminal of the third amplifier is electrically connected to the second input terminal.

[0019] (2) Alternatively, according to one aspect of the present invention, in the above-described (1), each of the first amplifier, the second amplifier, the third amplifier, and the fourth amplifier may include a differential amplifier circuit.

[0020] The input terminal of the first amplifier is the non-inverting input terminal of the differential amplifier circuit included in the first amplifier, and the output terminal of the first amplifier is the output terminal of the differential amplifier circuit included in the first amplifier. The input terminal of the second amplifier is the non-inverting input terminal of the differential amplifier circuit included in the second amplifier, and the output terminal of the second amplifier is the output terminal of the differential amplifier circuit included in the second amplifier. The input terminal of the third amplifier is the non-inverting input terminal of the differential amplifier circuit included in the third amplifier, and the output terminal of the third amplifier is the output terminal of the differential amplifier circuit included in the third amplifier. The input terminal of the fourth amplifier is the non-inverting input terminal of the differential amplifier circuit included in the fourth amplifier, and the output terminal of the fourth amplifier is the output terminal of the differential amplifier circuit included in the fourth amplifier. Preferably, the inverting input terminal and the output terminal of the differential amplifier circuit in each of the first, second, third, and fourth amplifiers are electrically connected to each other.

[0021] (3) Alternatively, according to one aspect of the present invention, in the above (2), the differential amplifier circuit may include a first transistor, a second transistor, a third transistor, and a fourth transistor.

[0022] In particular, it is preferable that one of the source or drain of the first transistor and one of the source or drain of the second transistor are electrically connected to the first wiring. It is also preferable that the other of the source or drain of the first transistor is electrically connected to one of the source or drain of the third transistor and an output terminal of the differential amplifier circuit. It is also preferable that the other of the source or drain of the second transistor is electrically connected to the gate of the first transistor, the gate of the second transistor, and one of the source or drain of the fourth transistor. It is also preferable that the gate of the third transistor is electrically connected to the non-inverting input terminal of the differential amplifier circuit. It is also preferable that the gate of the fourth transistor is electrically connected to the inverting input terminal of the differential amplifier circuit. It is also preferable that the other of the source or drain of the third transistor and the other of the source or drain of the fourth transistor are electrically connected to the second wiring.

[0023] (4) Alternatively, in one embodiment of the present invention, in the above (3), the first transistor and the second transistor may each be a p-channel transistor, and the third transistor and the fourth transistor may each be an n-channel transistor. In particular, it is preferable that the channel formation region of the first transistor and the channel formation region of the second transistor each contain silicon, and that the channel formation region of the third transistor and the channel formation region of the fourth transistor each contain indium oxide.

[0024] Preferably, a third transistor and a fourth transistor are located above the first transistor and the second transistor with an insulating layer interposed therebetween.

[0025] (5) Alternatively, according to one aspect of the present invention, in the above (1), the input terminal of the first amplifier may be electrically connected to the third wiring, and the input terminal of the fourth amplifier may be electrically connected to the fourth wiring.

[0026] In particular, the third wiring preferably functions as a wiring that applies a first potential as a power supply potential, and the fourth wiring preferably functions as a wiring that applies a second potential that is lower than the first potential as a power supply potential.

[0027] (6) Alternatively, in one aspect of the present invention, in the above (5), the selector circuit may have a tree-structured analog multiplexer using pass transistor logic.

[0028] In particular, the analog multiplexer preferably includes a fifth transistor, a sixth transistor, and an inverter. The fifth transistor is preferably a p-channel transistor, and the sixth transistor is preferably an n-channel transistor. A channel formation region of the fifth transistor preferably contains silicon, and a channel formation region of the sixth transistor preferably contains indium oxide. Preferably, one of the source or drain of the fifth transistor is electrically connected to the first input terminal, one of the source or drain of the sixth transistor is electrically connected to the second input terminal, and an output terminal of the inverter is electrically connected to the gate of the fifth transistor and the gate of the sixth transistor.

[0029] (7) Another embodiment of the present invention is a display device including a driver circuit and a pixel circuit located above the driver circuit. The driver circuit includes any one of the semiconductor devices described above in (1) to (6), a fifth amplifier, and a switch. The pixel circuit includes a seventh transistor, an eighth transistor, and a light-emitting device. The selector circuit includes an output terminal.

[0030] The output terminal of the selector circuit is electrically connected to the input terminal of the fifth amplifier. The output terminal of the fifth amplifier is electrically connected to a first terminal of a switch, and a second terminal of the switch is electrically connected to one of the source or drain of a seventh transistor. The other of the source or drain of the seventh transistor is electrically connected to the gate of an eighth transistor, and the one of the source or drain of the eighth transistor is electrically connected to the anode of the light-emitting device.

[0031] (8) In another embodiment of the present invention, in the above-described (7), the seventh transistor and the eighth transistor may each be an n-channel transistor. In particular, it is preferable that the channel formation region of the seventh transistor and the channel formation region of the eighth transistor each contain indium oxide.

[0032] With the above configuration, the transient currents flowing from the output terminals of the newly provided first and fourth amplifiers are increased, and the transient currents flowing from the output terminals of the second amplifier corresponding to the MSB potential and the third amplifier corresponding to the LSB potential are reduced. This makes it possible to suppress fluctuations in the MSB potential and the LSB potential due to parasitic resistance. Furthermore, by suppressing fluctuations in the MSB potential and the LSB potential, it is possible to input potentials corresponding to image signals to the data lines almost accurately, thereby improving the display quality of images displayed on the display device.

[0033] According to one embodiment of the present invention, a semiconductor device in which deviation in output potential is suppressed can be provided. According to another embodiment of the present invention, a semiconductor device with a reduced circuit area can be provided. According to another embodiment of the present invention, a display device including the semiconductor device can be provided. According to another embodiment of the present invention, a display device with high display quality can be provided. According to another embodiment of the present invention, a display device with a high driving frequency can be provided. According to another embodiment of the present invention, a novel semiconductor device or a novel display device can be provided.

[0034] Note that the effects of one embodiment of the present invention are not limited to the above-described effects. The above-described effects do not preclude the existence of other effects. Furthermore, the other effects are effects not mentioned in this section, which will be described below. Effects not mentioned in this section can be derived by a person skilled in the art from the description in the specification or drawings, and can be extracted as appropriate from these descriptions. Note that one embodiment of the present invention has at least one of the above-described effects and other effects. Furthermore, one embodiment of the present invention may not have the above-described effects in some cases.

[0035] FIG. 1 is a circuit diagram showing an example of a circuit included in a drive circuit. FIG. 2 is a circuit diagram showing an example of a drive circuit. FIG. 3 is a circuit diagram showing an example of a circuit included in a drive circuit. FIG. 4 is a circuit diagram showing an example of a circuit included in a drive circuit. FIG. 5 is a circuit diagram showing an example of a circuit included in a drive circuit. FIG. 6 is a circuit diagram showing an example of a circuit included in a drive circuit. FIG. 7A is a diagram showing a circuit symbol of an amplifier, and FIGS. 7B and 7C are circuit diagrams showing examples of the circuit configuration of an amplifier. FIG. 7D is a timing chart showing an example of the operation of an amplifier. FIG. 8 is a plan view schematic diagram showing an example of a circuit included in a drive circuit. FIG. 9 is a plan view schematic diagram showing an example of a circuit included in a drive circuit. FIG. 10 is a timing chart showing an example of the operation of a drive circuit. FIG. 11 is a circuit diagram showing an example of a drive circuit. FIG. 12 is a block diagram showing an example of the configuration of a display device. FIG. 13 is a perspective view schematic diagram showing an example of the configuration of a display device. FIG. 14 is a perspective view schematic diagram showing an example of the configuration of a display device. FIG. 15 is a perspective view schematic diagram showing an example of the configuration of a display device. 16A and 16B are diagrams illustrating the carrier concentration dependence of Hall mobility. FIG. 16C is a cross-sectional view illustrating an indium oxide film. FIGS. 17A to 17D are circuit diagrams illustrating an example of a pixel circuit. FIGS. 18A and 18B are circuit diagrams illustrating an example of a pixel circuit. FIGS. 19A and 19B are circuit diagrams illustrating an example of a pixel circuit. FIG. 20 is a circuit diagram illustrating an example of a pixel circuit. FIGS. 21A to 21C are schematic perspective views illustrating an example of a display device. FIG. 22 is a block diagram illustrating an example of a display device. FIG. 23 is a schematic cross-sectional view illustrating an example of a display device. FIG. 24A is a schematic plan view illustrating an example of a transistor, and FIGS. 24B and 24C are schematic cross-sectional views illustrating an example of a transistor. FIG. 25A is a schematic plan view illustrating an example of a transistor, and FIGS. 25B and 25C are schematic cross-sectional views illustrating an example of a transistor. FIGS. 26A to 26C are schematic cross-sectional views illustrating an example of a portion of a display device. Fig. 27 is a cross-sectional view showing a configuration example of a display device, Fig. 28 is a cross-sectional view showing a configuration example of a display device, and Fig. 29 is a cross-sectional view showing a configuration example of a transistor.FIG. 30 is a cross-sectional view showing an example of the configuration of a display device. FIG. 31 is a cross-sectional view showing an example of the configuration of a display device. FIG. 32A is a plan view showing an example of the configuration of a transistor, and FIGS. 32B to 32D are cross-sectional views showing an example of the configuration of a transistor. FIGS. 33A to 33C are cross-sectional views showing an example of the configuration of a transistor. FIG. 34A is a plan view showing an example of the configuration of a transistor, and FIGS. 34B to 34D are cross-sectional views showing an example of the configuration of a transistor. FIGS. 35A and 35B are diagrams showing an example of the configuration of a display module. FIGS. 36A to 36I are perspective views showing an example of an electronic device. FIGS. 37A and 37B are photographs of a display device according to an example. FIGS. 38A to 38C are block diagrams showing the configuration of a circuit included in a display device according to an example. FIG. 39 is a circuit diagram showing the configuration of a circuit included in a display device according to an example. FIG. 40 is a graph showing a comparison of power consumption in two operation methods in a display device according to an example. Fig. 41 is a graph showing the luminance of each point in an image displayed by a display device according to an example. Fig. 42A1 to Fig. 42A7 and Fig. 42B1 to Fig. 42B6 are circuit diagrams for explaining electrical connections.

[0036] (Additional Notes Related to the Present Specification) In the present specification, a semiconductor device is a device that utilizes semiconductor characteristics, and refers to a circuit including a semiconductor element (for example, a transistor, a diode, and a photodiode), or a device having such a circuit. A semiconductor device also refers to any device that can function by utilizing semiconductor characteristics. An example of a semiconductor device is an integrated circuit. Another example of a semiconductor device is a chip equipped with an integrated circuit. Another example of a semiconductor device is an electronic component that houses a chip in a package. For example, a memory device, a display device, a light-emitting device, a lighting device, and an electronic device may themselves be a semiconductor device, or may include a semiconductor device.

[0037] In this specification, "connection" includes, for example, "electrical connection."

[0038] In addition, when the term "electrical connection" is used to define the connection relationship between circuit elements as an object, "electrical connection" includes, for example, "direct connection" and "indirect connection." "A and B are directly connected" refers to a case where A and B are connected without a circuit element (e.g., a transistor or a switch; wiring is not a circuit element). On the other hand, "A and B are indirectly connected" refers to a case where A and B are connected via one or more circuit elements. A, B, and C, which will be described later, represent objects such as elements, circuits, wiring, electrodes, terminals, semiconductor layers, and conductive layers.

[0039] Here, when "A and B are indirectly connected," it refers to the following connection relationship, for example. That is, assuming that a circuit is operating, if there is a time during the operation of the circuit when electrical signal transmission or potential interaction occurs between A and B, such a circuit can be defined as an entity, and "A and B are indirectly connected." Note that even if there is a time when electrical signal transmission or potential interaction does not occur between A and B, if there is a time during the operation of the circuit when electrical signal transmission or potential interaction occurs between A and B, it can be defined as "A and B are indirectly connected." Note that "A and B are indirectly connected" is a definition of the connection relationship between circuit elements as an entity. Therefore, for example, even when a power supply voltage is not supplied to a circuit and the circuit is not operating, the circuit can be defined as an entity, and "A and B are indirectly connected" (however, for example, this is limited to the case where electrical signal transmission or potential interaction occurs between A and B during the operation of the circuit when a power supply voltage is supplied to the circuit and the circuit is operating).

[0040] Specific examples of "indirect connection" are shown below. First, an example of "A and B are indirectly connected" is when A and B are connected via the source and drain of one or more transistors, as shown in FIGS. 42A1 and 42A2. Another example of "A and B are indirectly connected" is when A and B are connected via one or more switches. When "A and B are indirectly connected," it is assumed that, assuming the circuit is operating, there is at least one time when a transistor between A and B is in an on state, a conductive state, or a state in which a current can flow. Note that "A and B are indirectly connected" also includes cases in which a transistor between A and B is in an off state or a non-conductive state. When "A and B are indirectly connected," if multiple transistors are connected between A and B, it is assumed that, assuming the circuit is operating, each of the multiple transistors between A and B is in an on state, a conductive state, or a state in which a current can flow at least one time. In other words, when "A and B are indirectly connected," it is not necessary for all of the multiple transistors to be in an on state, a conductive state, or a state in which current can flow simultaneously. Therefore, when "A and B are indirectly connected," it also includes cases in which the multiple transistors between A and B are in an off state or a non-conductive state at the same time or at different times. As another example, as shown in FIG. 42A3, when A and C are connected via the source and drain of transistor TrP and B and C are connected via the source and drain of transistor TrQ, it can be defined as "A and C are indirectly connected," "B and C are indirectly connected," or "A and B are indirectly connected." However, as will be described later, when a constant potential V is supplied to C from a power supply, GND, or the like, it can be said that "A and C are indirectly connected" or "B and C are indirectly connected," but it cannot be said that "A and B are indirectly connected."

[0041] While we have provided examples of cases where an "indirect connection" can and cannot be established, we will now present another example of a case where an "indirect connection" cannot be established. Even if an electrical signal exchange or potential interaction occurs between A and B during the operation of the circuit, there are exceptional cases where it cannot be said that "A and B are indirectly connected." An example of such an exceptional case is when A and B are connected via an insulator. In other words, when A and B are connected via an insulator, it cannot be said that "A and B are indirectly connected." A specific example of a case where A and B are connected via an insulator is when a capacitive element is connected between A and B, as shown in FIG. 42A4. Another example of a case where A and B are connected via an insulator is when a gate insulating film of a transistor is interposed between A and B, as shown in FIG. 42A5. In this case, it cannot be said that "A (the gate of the transistor) and B (the source or drain of the transistor) are indirectly connected."

[0042] Another example of a case where it cannot be said that "A and B are indirectly connected" is a case where there is no timing when an electrical signal is exchanged or when potential interaction occurs between A and B. An example of this is when, as shown in Figures 42A6 and 42A7, multiple transistors are connected via their sources and drains to the path from A to B, and a constant potential V is supplied to a node between the transistors from a power supply, GND, or the like. In this case, it cannot be said that "A and B are indirectly connected," but it is possible to say that "A and V are indirectly connected" or "B and V are indirectly connected." In addition, in Figure 42A3, if A and C are connected via the source and drain of transistor TrP, and B and C are connected via the source and drain of transistor TrQ, and a constant potential V is supplied to C from a power supply or GND, etc., the relationship will be the same as in Figures 42A6 and 42A7, so it cannot be said that "A and B are indirectly connected," but it can be said that "A and C are indirectly connected," or "B and C are indirectly connected."

[0043] Although an example of "indirect connection" has been given above, as an example, the provision of "indirect connection" is included in the provision of "electrical connection," so when "A and B are indirectly connected," it can also be said that "A and B are electrically connected."

[0044] Next, specific examples of "direct connection" are shown. Examples of "A and B are directly connected" include cases where A and B are connected without any circuit elements between them, as shown in FIGS. 42B1, 42B2, and 42B3. When A and B are connected to a power supply that supplies a constant potential V or to GND without any circuit elements between them, as shown in FIGS. 42B4 and 42B5, it can be said that "A and B are directly connected," "A and V are directly connected," or "B and V are directly connected." It can also be said that "A and B are directly connected," when A (or B) is connected to a constant potential V via the source and drain of a transistor, as shown in FIG. 42B6. Because A and V or B and V are connected via the source and drain of a transistor, they cannot be said to be directly connected, but rather that "A and V are indirectly connected" or "B and V are indirectly connected."

[0045] Although an example of "direct connection" has been given above, as an example, the definition of "direct connection" is included in the definition of "electrical connection," so when "A and B are directly connected," it can also be said that "A and B are electrically connected."

[0046] Note that even when independent components are shown as being connected to each other in a circuit diagram, one component may have the functions of multiple components. For example, if part of a wiring also functions as an electrode, one conductive film has the functions of both a wiring and an electrode. Therefore, in this specification, the term "connection" also includes such cases where one conductive film has the functions of multiple components.

[0047] Generally, examples of a "resistance element" include a circuit element having a resistance value higher than 0Ω, wiring having a resistance value higher than 0Ω, etc. Therefore, the "resistance element" described in this specification includes wiring, diodes, or coils having a resistance value. Therefore, the term "resistance element" can sometimes be replaced with the terms "resistance," "load," or "region having a resistance value." Conversely, the terms "resistance," "load," or "region having a resistance value" can sometimes be replaced with the term "resistance element." The resistance value can be, for example, preferably 1 mΩ or more and 10 Ω or less, more preferably 5 mΩ or more and 5 Ω or less, and even more preferably 10 mΩ or more and 1 Ω or less. In addition, for example, 1 Ω or more and 1×10 ９ It can be made smaller than Ω.

[0048] Generally, examples of "capacitance" include a circuit element having a capacitance value higher than 0 F, a region of wiring having a capacitance value higher than 0 F, and a region between a gate or back gate and a source or drain in a transistor having a capacitance value higher than 0 F. Furthermore, the terms "capacitance element," "parasitic capacitance," or "gate capacitance" may sometimes be replaced with the term "capacitance." Conversely, the term "capacitance" may sometimes be replaced with the terms "capacitance element," "parasitic capacitance," or "gate capacitance."

[0049] Furthermore, a "capacitor" (including a "capacitor" with three or more terminals) includes an insulator and a pair of conductors sandwiching the insulator. Therefore, the term "pair of conductors" in a "capacitor" can be rephrased as "pair of electrodes," "pair of conductive regions," "pair of regions," or "pair of terminals." Furthermore, the terms "one of the pair of terminals" and "the other of the pair of terminals" may be referred to as a first terminal and a second terminal, respectively. The value of the electrostatic capacitance of a capacitor can be, for example, 0.05 fF or more and 10 pF or less. Furthermore, it can be, for example, 1 pF or more and 10 μF or less.

[0050] The switches described in this specification are described as having the function of being turned on or off and controlling whether or not a current flows, or as having the function of selecting and switching the path through which a current flows.

[0051] In this specification, a "conductive state" refers to a state in which a current can flow between two input / output terminals, and a "non-conductive state" refers to a state in which the two input / output terminals are considered to be electrically disconnected. In this specification, the on state of a switch falls under the category of a "conductive state," and the off state of a switch falls under the category of a "non-conductive state." Therefore, in this specification, the "conductive state" and the "on state" of a switch are interchangeable, and the "non-conductive state" and the "off state" are interchangeable.

[0052] Furthermore, the switch may have two or more terminals for passing current in addition to the control terminal. For example, an electrical switch, a mechanical switch, or the like may be used. In other words, the switch is not limited to a specific type as long as it has the function of controlling current.

[0053] Examples of electrical switches include transistors (e.g., bipolar transistors, MOS transistors, etc.), diodes (e.g., PN diodes, PIN diodes, Schottky diodes, MIM (Metal Insulator Metal) diodes, MIS (Metal Insulator Semiconductor) diodes, and diode-connected transistors), or logic circuits combining these. When a transistor is used as a switch, the "conductive state" or "on state" of the transistor refers to a state in which a current can flow between the source electrode and the drain electrode of the transistor. The "non-conductive state" or "off state" of the transistor refers to a state in which the source electrode and the drain electrode of the transistor can be considered to be electrically disconnected. When a transistor is operated simply as a switch, the polarity (conductivity type) of the transistor is not particularly limited.

[0054] An example of a mechanical switch is a switch that uses MEMS (microelectromechanical systems) technology. A mechanical switch has an electrode that can be mechanically moved, and the mechanical switch operates by controlling the conductive state and non-conductive state by the movement of the electrode.

[0055] In this specification, a transistor has three terminals called a gate, a source, and a drain. The gate is a control terminal that controls switching between a conductive state and a non-conductive state of the transistor. The two terminals that function as a source or a drain are input / output terminals of the transistor. One of the two input / output terminals serves as a source and the other as a drain depending on the conductivity type (n-channel or p-channel) of the transistor and the level of potential applied to the three terminals of the transistor. Therefore, in this specification, the terms "source" and "drain" are sometimes interchangeable. In addition, in this specification, when describing the connection relationship of a transistor, the terms "one of the source and the drain" and "the other of the source and the drain" are used. In this specification, one of the source and the drain is sometimes referred to as a "first electrode of the transistor" or a "first terminal of the transistor," and the other of the source and the drain is sometimes referred to as a "second electrode of the transistor" or a "second terminal of the transistor." Note that, depending on the structure of a transistor, a backgate may be provided in addition to the three terminals described above. In this case, in this specification, one of the gate or back gate of the transistor may be referred to as a first gate, and the other of the gate or back gate of the transistor may be referred to as a second gate. Furthermore, for the same transistor, the terms "gate" and "back gate" may be interchangeable. Furthermore, in this specification, when a transistor has three or more gates, the respective gates may be referred to as a first gate, a second gate, a third gate, etc.

[0056] For example, an example of a transistor described herein may include a transistor with a multi-gate structure having two or more gate electrodes. The multi-gate structure allows the channel formation regions to be connected in series, resulting in a structure in which multiple transistors are connected in series. Therefore, the multi-gate structure can reduce the off-state current and improve the transistor's breakdown voltage (reliability). Alternatively, the multi-gate structure allows for a voltage-current characteristic with a flat slope to be obtained when operating in the saturation region, since the current between the drain and source does not change significantly even when the voltage between the drain and source changes. By utilizing the voltage-current characteristic with a flat slope, an ideal current source circuit or an active load with a very high resistance value can be realized. As a result, a differential circuit or a current mirror circuit with excellent characteristics can be realized.

[0057] Generally, the threshold voltage of a transistor is a voltage between the subthreshold region (weak inversion region) and the strong inversion region, and can be said to be the voltage at which switching between the subthreshold region and the strong inversion region occurs. In addition, as an example of a method for measuring the threshold voltage, Id is calculated based on the Id (source-drain current) - Vgs (gate-source voltage) characteristics. １／２ -Vgs characteristics are plotted, and Id １／２ Id on the tangent line where the slope of the -Vgs characteristic is maximum １／２ As another example, in the Id-Vgs characteristic where the drain potential is 1.2 V, Id=1.0×10 −１２ A is set as the threshold voltage.

[0058] Furthermore, even when a single circuit element is shown on a circuit diagram, the circuit element may actually include multiple circuit elements. For example, when a circuit diagram shows one resistor element, this includes two or more resistor elements connected in series or parallel. For example, when a circuit diagram shows one capacitor element, this includes two or more capacitor elements connected in parallel. For example, when a circuit diagram shows one transistor, this includes two or more transistors connected in series with their sources and drains directly connected and their gates directly connected. Furthermore, a configuration in which two or more transistors are connected in series with their sources and drains directly connected and their gates directly connected can sometimes be represented as a single transistor. For example, when a circuit diagram shows one transistor, this includes two or more transistors with their first terminals directly connected to each other, their second terminals directly connected to each other, and their gates directly connected to each other. In addition, a configuration in which the first terminals of two or more transistors are directly connected to each other, the second terminals of each transistor are directly connected to each other, and the gates of each transistor are directly connected to each other can sometimes be represented as a single transistor.

[0059] In this specification, a node can be referred to as a terminal, a wiring, an electrode, a conductive layer, a conductor, an impurity region, etc. depending on the circuit configuration and device structure. A terminal, a wiring, etc. can also be referred to as a node.

[0060] Furthermore, the selector circuit described herein may be, for example, a circuit having multiple input terminals and one output terminal, selecting one of the multiple input terminals, and establishing a conductive state between the selected input terminal and the one output terminal. In other words, the selector circuit described herein may be a circuit that selects one of the input signals input to each of the multiple input terminals and outputs the selected input signal to the output terminal. Alternatively, the selector circuit described herein may be, for example, a circuit having multiple output terminals and one input terminal, selecting one of the multiple output terminals, and establishing a conductive state between the selected output terminal and the one input terminal. In other words, the selector circuit may be a circuit that selects one of the multiple output terminals and outputs the input signal input to the input terminal to the selected output terminal. In other words, the selector circuit may refer to a multiplexer or a demultiplexer. In particular, when an analog potential or an analog current is input or output, the selector circuit may refer to an analog multiplexer or an analog demultiplexer.

[0061] Furthermore, in this specification, the terms "voltage" and "potential" can be interchanged as appropriate. "Voltage" refers to the potential difference from a reference potential. For example, if the reference potential is the ground potential (earth potential), then "voltage" can be interchanged with "potential." Note that ground potential does not necessarily mean 0 V. Furthermore, potential is relative, and as the reference potential changes, the potential applied to wiring, the potential applied to a circuit, etc., the potential output from a circuit, etc. also changes.

[0062] Furthermore, in this specification, the terms "high-level potential" and "low-level potential" do not mean specific potentials. For example, when two wirings are both described as "functioning as wirings that supply a high-level potential," the high-level potentials applied to the two wirings may be different from each other. Similarly, when two wirings are both described as "functioning as wirings that supply a low-level potential," the low-level potentials applied to the two wirings may be different from each other.

[0063] Furthermore, "current" refers to the phenomenon of charge transfer (electrical conduction). For example, the statement "electrical conduction of a positively charged body is occurring" can be rephrased as "electrical conduction of a negatively charged body is occurring in the opposite direction." Therefore, in this specification, unless otherwise specified, "current" refers to the phenomenon of charge transfer (electrical conduction) associated with the movement of carriers. Examples of carriers here include electrons, holes, anions, cations, and complex ions, and the carriers differ depending on the system through which the current flows (e.g., semiconductor, metal, electrolyte, and vacuum). Furthermore, the "direction of current" in wiring, etc., refers to the direction in which positively charged carriers move and is expressed as a positive current amount. In other words, the direction in which negatively charged carriers move is opposite to the direction of current and is expressed as a negative current amount. Therefore, in this specification, unless otherwise specified regarding the positive / negative sign of the current (or the direction of current), the statement "current flows from element A to element B" can be rephrased as "current flows from element B to element A." Furthermore, the statement "current is input to element A" can be rephrased as "current is output from element A."

[0064] Furthermore, in this specification, ordinal numbers such as "first," "second," and "third" are used to avoid confusion between components. Therefore, they do not limit the number of components. Furthermore, they do not limit the order of components, such as the order of processes or stacking. Furthermore, even if a term does not have an ordinal number in this specification, an ordinal number may be added in the claims to avoid confusion between components. Furthermore, even if a term has an ordinal number in this specification, a different ordinal number may be added in the claims. Furthermore, even if a term has an ordinal number in this specification, the counter may be omitted in the claims. For example, a component referred to with the ordinal number "first" in one embodiment of this specification may be referred to with a different ordinal number, such as "second" or "third," in other embodiments or claims. Furthermore, for example, a component referred to with the ordinal number "first" in one embodiment of this specification may be omitted in other embodiments or claims.

[0065] Furthermore, in this specification, terms indicating position, such as "above" and "below," may be used for convenience in describing the positional relationship between components with reference to the drawings. Furthermore, the positional relationship between components changes as appropriate depending on the direction in which each configuration is depicted. Therefore, the terms are not limited to those described in the specification, etc., and can be rephrased appropriately depending on the situation. For example, the expression "insulator located on the upper surface of a conductor" can be rephrased as "insulator located on the lower surface of a conductor" by rotating the orientation of the drawing 180 degrees.

[0066] Furthermore, the terms "above" and "below" do not limit the positional relationship of components to being directly above or below and in direct contact with each other. For example, the expression "electrode B on insulating layer A" does not require that electrode B be formed in direct contact with insulating layer A, and does not exclude the inclusion of other components between insulating layer A and electrode B. Similarly, the expression "electrode B above insulating layer A" does not require that electrode B be formed in direct contact with insulating layer A, and does not exclude the inclusion of other components between insulating layer A and electrode B. Similarly, the expression "electrode B below insulating layer A" does not require that electrode B be formed in direct contact below insulating layer A, and does not exclude the inclusion of other components between insulating layer A and electrode B.

[0067] Furthermore, in this specification, terms such as "row" and "column" may be used to describe components arranged in a matrix and their positional relationships. Furthermore, the positional relationships between components change as appropriate depending on the direction in which each component is depicted. Therefore, the terms are not limited to those used in the specification, and may be rephrased appropriately depending on the situation. For example, the expression "row direction" may be rephrased as "column direction" by rotating the orientation of the drawing by 90 degrees.

[0068] Furthermore, in this specification, the terms "film" and "layer" can be interchanged depending on the situation. For example, the term "conductive layer" can be changed to the term "conductive film". Or, for example, the term "insulating film" can be changed to the term "insulating layer". Or, in some cases or depending on the situation, the terms "film" and "layer" can be replaced with other terms without being used. For example, the term "conductive layer" or "conductive film" can be changed to the term "conductor". Or, for example, the term "insulating layer" or "insulating film" can be changed to the term "insulator".

[0069] Furthermore, in this specification, terms such as "electrode," "wiring," and "terminal" do not limit the functionality of these components. For example, an "electrode" may be used as part of a "wiring," and vice versa. Furthermore, terms such as "electrode" or "wiring" include cases where multiple "electrodes" or "wirings" are integrally formed. Furthermore, for example, a "terminal" may be used as part of a "wiring" or "electrode," and vice versa. Furthermore, the term "terminal" includes cases where one or more selected from "electrode," "wiring," and "terminal" are integrally formed. Therefore, for example, an "electrode" can be part of a "wiring" or "terminal," and a "terminal" can be part of a "wiring" or "electrode." Furthermore, the terms "electrode," "wiring," and "terminal" may be replaced with the term "region" in some cases.

[0070] Furthermore, in this specification, terms such as "wiring," "signal line," and "power line" may be interchangeable depending on the circumstances. For example, the term "wiring" may be changed to the term "signal line." For example, the term "wiring" may be changed to the term "power line." Vice versa, terms such as "signal line" or "power line" may be changed to the term "wiring." A term such as "power line" may be changed to the term "signal line." Vice versa, a term such as "signal line" may be changed to the term "power line." Furthermore, a term "potential" applied to a wiring may be changed to the term "signal" depending on the circumstances. Vice versa, a term such as "signal" may be changed to the term "potential."

[0071] In addition, timing charts may be used in this specification to explain an operation method of a semiconductor device. The timing charts used in this specification illustrate ideal operation examples, and the periods, magnitudes, and timings of signals (e.g., potentials or currents) described in the timing charts are not limited unless otherwise specified. The magnitudes and timings of signals (e.g., potentials or currents) input to each wiring (including a node) in the timing charts described in this specification may be changed depending on the situation. For example, even if two periods are shown at equal intervals in a timing chart, the lengths of the two periods may be different. For example, even if one period is shown as long and the other as short, the lengths of the two periods may be equal, or one period may be short and the other period may be long. For example, to clearly illustrate the timing charts, two or more overlapping signals may be intentionally shifted.

[0072] In this specification, a metal oxide refers to an oxide of a metal in a broad sense. Metal oxides are classified into oxide insulators, oxide conductors (including transparent oxide conductors), oxide semiconductors (also referred to as oxide semiconductors or simply as OSs), and the like. For example, when a metal oxide is contained in a channel formation region of a transistor, the metal oxide may be referred to as an oxide semiconductor. In other words, when a metal oxide can form a channel formation region of a transistor having at least one of an amplifying function, a rectifying function, and a switching function, the metal oxide can be referred to as a metal oxide semiconductor. Furthermore, an OS transistor can be referred to as a transistor including a metal oxide or an oxide semiconductor.

[0073] In this specification, nitrogen-containing metal oxides may also be collectively referred to as metal oxides, and nitrogen-containing metal oxides may also be referred to as metal oxynitrides.

[0074] In this specification, the term "impurities" in a semiconductor refers to, for example, elements other than the main component constituting the semiconductor layer. For example, an element having a concentration of less than 0.1 atomic % is an impurity. The presence of impurities may cause one or more of the following: an increase in the defect level density of the semiconductor, a decrease in carrier mobility, and a decrease in crystallinity. When the semiconductor is an oxide semiconductor, impurities that change the characteristics of the semiconductor include, for example, Group 1 elements, Group 2 elements, Group 13 elements, Group 14 elements, Group 15 elements, and transition metals other than the main component, particularly, for example, hydrogen (also contained in water), lithium, sodium, silicon, boron, phosphorus, carbon, and nitrogen.

[0075] In this specification, "parallel" refers to a state in which two straight lines are arranged at an angle of -10 degrees or more and 10 degrees or less. Therefore, it also includes cases in which the angle is -5 degrees or more and 5 degrees or less. Furthermore, "substantially parallel" or "roughly parallel" refers to a state in which two straight lines are arranged at an angle of -30 degrees or more and 30 degrees or less. Furthermore, "perpendicular" refers to a state in which two straight lines are arranged at an angle of 80 degrees or more and 100 degrees or less. Therefore, it also includes cases in which the angle is 85 degrees or more and 95 degrees or less. Furthermore, "substantially perpendicular" or "approximately perpendicular" refers to a state in which two straight lines are arranged at an angle of 60 degrees or more and 120 degrees or less.

[0076] In this specification, unless otherwise specified, the expression "A and B are equal" means that the ratio of one of A and B to the other is 0.9 or more and 1.1 or less. For example, the case where the ratio of B to A is 0.9 or more and 1.1 or less and the ratio of A to B is not 0.9 or more and 1.1 or less is also considered to be "A and B are equal." Furthermore, unless otherwise specified, the expression "A and B are approximately equal" means that the ratio of one of A and B to the other is 0.8 or more and 1.2 or less, is also considered to be "A and B are approximately equal." For example, the case where the ratio of B to A is 0.8 or more and 1.2 or less and the ratio of A to B is not 0.8 or more and 1.2 or less is also considered to be "A and B are approximately equal."

[0077] In this specification, the configurations shown in each embodiment can be combined with the configurations shown in other embodiments as appropriate to form one aspect of the present invention. When multiple configuration examples are shown in one embodiment, the configuration examples can be combined with each other as appropriate.

[0078] In addition, the content described in one embodiment can be applied, combined, or replaced with another content described in that embodiment and at least one of the content described in another embodiment.

[0079] The contents described in the embodiments refer to the contents described in each embodiment using various figures or the contents described using text in the specification.

[0080] Furthermore, a figure described in one embodiment can be combined with another portion of that figure and at least one figure described in one or more other embodiments to form even more figures.

[0081] The embodiments described in this specification are described with reference to the drawings. However, it will be readily understood by those skilled in the art that the embodiments can be implemented in many different ways, and that various changes in form and details can be made without departing from the spirit and scope of the invention. Therefore, the present invention should not be interpreted as being limited to the description of the embodiments. Note that in the configuration of the invention of the embodiments, the same reference numerals are used in different drawings for the same parts or parts having similar functions, and repeated description thereof may be omitted. Also, in perspective views and the like, the description of some components may be omitted to ensure clarity of the drawings.

[0082] In this specification, when the same reference numeral is used for multiple elements, and particularly when it is necessary to distinguish between them, an identification symbol such as "_1", "[n]", "[m, n]" may be added to the reference numeral. Furthermore, when an identification symbol such as "_1", "[n]", "[m, n]" is added to the reference numeral in the drawings or the like, the identification symbol may not be added if it is not necessary to distinguish between them in this specification.

[0083] In addition, in the drawings of this specification, the size, layer thickness, or region may be exaggerated for clarity. Therefore, the drawings are not necessarily limited to the scale. Note that the drawings are schematic illustrations of ideal examples, and are not limited to the shapes or values ​​shown in the drawings. For example, variations in signals, voltages, or currents due to noise, or variations in signals, voltages, or currents due to timing differences may be included.

[0084] Embodiment 1 In this embodiment, a driver circuit which is a semiconductor device of one embodiment of the present invention and a display device including the driver circuit will be described.

[0085] <Driver Circuit Configuration Example 1> First, a configuration example of the driver circuit will be described. Fig. 2 is a block diagram showing a configuration example of the driver circuit. The driver circuit SD shown in Fig. 2 functions as a source driver circuit of a display device, as an example. The driver circuit SD is configured when pixel circuits provided in a pixel array of the display device are arranged in N columns (N is an integer equal to or greater than 1).

[0086] In FIG. 2, the driver circuit SD includes, as an example, a shift register SR, logic circuits LMP[1] to LMP[N], flip-flop circuits FFA[1] to FFA[N], latch circuits LTA[1] to LTA[N], level shifter circuits LS[1] to LS[N], a digital-to-analog conversion circuit DAC, amplifiers AP[1] to AP[N], and switches SWA[1] to SWA[N].

[0087] The shift register SR has, for example, a plurality of output terminals. Each of the logic circuits LMP[1] to LMP[N] has, for example, a first input terminal, a second input terminal, and an output terminal.

[0088] Furthermore, each of the flip-flop circuits FFA[1] to FFA[N] has, as an example, an input terminal DA, an output terminal QA, and a clock input terminal CK (sometimes called an input terminal, a strobe input terminal, etc.).

[0089] Furthermore, each of the latch circuits LTA[1] to LTA[N] has, for example, an input terminal, an output terminal, and an enable input terminal (which may also be referred to as an input terminal, a clock input terminal, etc.). In this specification, to distinguish between the input terminal and the enable input terminal, the input terminal may be referred to as a first input terminal, and the enable input terminal may be referred to as a second input terminal.

[0090] The digital-analog conversion circuit DAC has, for example, an input terminal and an output terminal corresponding to each column. Here, it can also be said that the digital-analog conversion circuit DAC has N input terminals and N output terminals. The digital-analog conversion circuit DAC also has, for example, a voltage generation circuit RSTR and selector circuits PTL[1] to PTL[N]. Each of the selector circuits PTL[1] to PTL[N] also has, for example, an input terminal, an output terminal, and a terminal VIT that is a power supply terminal.

[0091] Each of the level shifter circuits LS[1] to LS[N] has, for example, an input terminal and an output terminal, and each of the amplifiers AP[1] to AP[N] has, for example, an input terminal and an output terminal.

[0092] 2 (where j is an integer between 1 and N), a first input terminal of a logic circuit LMP[j] is connected to the jth output terminal of the shift register SR, a second input terminal of the logic circuit LMP[j] is connected to a wiring CKL1, and an output terminal of the logic circuit LMP[j] is connected to a wiring CKL2[j]. In addition, the wiring CKL2[j] is connected to the clock input terminal of a flip-flop circuit FFA[j].

[0093] The input terminal DA of the flip-flop circuit FFA[j] is connected to the wiring DL, the output terminal QA of the flip-flop circuit FFA[j] is connected to the first input terminal of the latch circuit LTA[j], the output terminal of the latch circuit LTA[j] is connected to the input terminal of the level shifter circuit LS[j], and the second input terminal of the latch circuit LTA[j] is connected to the wiring LL.

[0094] The output terminal of the level shifter circuit LS[j] is connected to the j-th input terminal of the digital-analog conversion circuit DAC, and the j-th output terminal of the digital-analog conversion circuit DAC is connected to the input terminal of the amplifier AP[j].

[0095] Specifically, the output terminal of the level shifter circuit LS[j] is connected to the input terminal of the selector circuit PTL[j] via the wiring SEL[j], and the output terminal of the selector circuit PTL[j] is connected to the input terminal of the amplifier AP[j]. That is, the jth input terminal of the digital-analog conversion circuit DAC corresponds to the input terminal of the selector circuit PTL[j], and the jth output terminal of the digital-analog conversion circuit DAC corresponds to the output terminal of the selector circuit PTL[j]. Therefore, the jth input terminal of the digital-analog conversion circuit DAC can be rephrased as the input terminal of the selector circuit PTL[j], and the jth output terminal of the digital-analog conversion circuit DAC can be rephrased as the output terminal of the selector circuit PTL[j].

[0096] Furthermore, the terminal VIT, which is the power supply terminal of the selector circuit PTL[j], is connected to the terminal VOT, which is the output terminal of the voltage generating circuit RSTR.

[0097] The jth output terminal of the digital-to-analog conversion circuit DAC is connected to the input terminal of the amplifier AP[j]. The output terminal of the amplifier AP[j] is connected to the first terminal of the switch SWA[j]. The second terminal of the switch SWA[j] is connected to the line SL[j], and the control terminal of the switch SWA[j] is connected to the line SWL.

[0098] For example, the wiring CKL1 functions as a wiring that applies a variable potential. The variable potential can be a clock potential (sometimes referred to as a clock signal) that transitions from a low-level potential to a high-level potential and from a high-level potential to a low-level potential. Note that, as shown in the above connection configuration, the variable potential is transmitted to the second input terminals of the logic circuits LMP[1] to LMP[N].

[0099] For example, the wiring DL functions as a wiring for transmitting an image signal. Note that, as shown in the above connection configuration, the image signal is transmitted to each of the input terminals DA of the flip-flop circuits FFA[1] to FFA[N]. Note that the image signal here is a digital signal.

[0100] For example, the wiring LL functions as a wiring for transmitting an enable signal or a disable signal to each of the latch circuits LTA[1] to LTA[N]. Note that, as in the above connection configuration, the enable signal or the disable signal is transmitted to the second input terminal of each of the latch circuits LTA[1] to LTA[N].

[0101] The wirings SEL[1] to SEL[N] function as wirings for transmitting image signals from the level shifter circuit LS to the digital-to-analog conversion circuit DAC. The image signals here are also digital signals.

[0102] For example, the wiring SWL functions as a wiring for transmitting a signal for controlling switching between the on state and the off state of each of the switches SWA[1] to SWA[N].

[0103] For example, the wirings SL[1] to SL[N] function as wirings for transmitting image signals from the driver circuit SD to pixel circuits included in the pixel array. Therefore, the pixel circuits included in the pixel array of the display device are connected to the ends of the wirings SL[j] to which the image signals are transmitted. The wirings SL[1] to SL[N] may also be referred to as source lines or data lines in the pixel circuits.

[0104] Next, each circuit shown in FIG. 2 will be described.

[0105] For example, the shift register SR has a function of selecting one of a plurality of output terminals and outputting a high-level potential from the selected output terminal each time a rising or falling edge of a clock signal is input. For example, if the shift register SR has first to Nth output terminals, when the first rising or falling edge of the clock signal is input to the shift register SR, the shift register SR outputs a high-level potential from the first output terminal and a low-level potential from the second to Nth output terminals. When the second rising or falling edge of the clock signal is input to the shift register SR, the shift register SR outputs a high-level potential from the second output terminal and a low-level potential from the first and third to Nth output terminals. When the jth rising or falling edge of the clock signal is input to the shift register SR, the shift register SR outputs a high-level potential from the jth output terminal and a low-level potential from the first to Nth output terminals excluding the jth output terminal.

[0106] The above operation of the shift register SR is an example, and depending on the circuit configuration of the drive circuit SD, the high level potential and the low level potential of the shift register SR may be interchanged in the above operation.

[0107] 2, for example, each of the logic circuits LMP[1] to LMP[N] is an AND circuit. For example, the logic circuit LMP[j] has a function of performing a logical AND operation on a logic corresponding to a potential transmitted from the wiring CKL1 and a logic of a signal transmitted from the j-th output terminal of the shift register SR, and outputting the operation result to the wiring CKL2[j].

[0108] As an example of the operation of the logic circuit LMP[j], when a high-level potential is output from the j-th output terminal of the shift register SR and input to the first input terminal of the logic circuit LMP[j], and a high-level potential is input from the wiring CKL1 to the second input terminal of the logic circuit LMP[j], the logic circuit LMP[j] outputs a high-level potential from its output terminal to the wiring CKL2[j]. Note that when a low-level potential is input to one or both of the first and second input terminals of the logic circuit LMP[j], the logic circuit LMP[j] outputs a low-level potential from its output terminal to the wiring CKL2[j].

[0109] The high-level potential or low-level potential output from the output terminal of the logic circuit LMP[j] to the wiring CKL2[j] functions as an enable signal or a disable signal input to the clock input terminal CK of the flip-flop circuit FFA[j] described later.

[0110] As an example, the flip-flop circuit FFA[j] has the function of holding a potential corresponding to a signal input to the input terminal DA, and the function of transmitting the held potential as a signal from the output terminal QA to the input terminal of the latch circuit LTA[j] when the potential input to the clock input terminal CK rises or falls.

[0111] As an example, the flip-flop circuit FFA[j] has a function of holding image data corresponding to the image signal by inputting a rising or falling edge of a clock signal to the clock input terminal CK while the image signal is being input to the input terminal DA. Furthermore, once the flip-flop circuit FFA[j] has held the image data, it always outputs the image signal to the output terminal QA until a rising or falling edge of the clock signal is again input to the clock input terminal CK. Note that the image signal output from the output terminal QA of the flip-flop circuit FFA[j] here is a digital signal.

[0112] For example, the latch circuit LTA[j] has a function of holding image data corresponding to an image signal by inputting an enable signal to the second input terminal while the image signal is input to the first input terminal. Furthermore, once the latch circuit LTA[j] has held the image data, it continues to output the image signal to the output terminal until the enable signal changes to a disable signal. Note that the image signal output from the output terminal of the latch circuit LTA[j] is a digital signal.

[0113] For example, the level shifter circuit LS[j] has a function of shifting a potential corresponding to an image signal input to an input terminal to a potential at a level that can be handled by at least a digital-analog conversion circuit DAC described later. Note that if the potential corresponding to the image signal output from the output terminal of the latch circuit LTA[j] is a potential at a level that can be handled by the digital-analog conversion circuit DAC, the driver circuit SD does not need to be provided with the level shifter circuit LS[j]. In other words, in this case, the output terminal of the latch circuit LTA[j] may be electrically connected directly to the wiring SEL[j].

[0114] For example, the digital-analog conversion circuit DAC has a function of acquiring a digital image signal from the wiring SEL[j], converting the image signal into an analog potential, and transmitting the analog potential to the amplifier AP[j]. Note that the detailed circuit configuration of the digital-analog conversion circuit DAC will be described later.

[0115] Also, as an example, the digital-analog conversion circuit DAC can be said to have first to Nth input terminals and first to Nth output terminals. As described above, the input terminal of the selector circuit PTL[1] corresponds to the first input terminal of the digital-analog conversion circuit DAC, and the output terminal of the selector circuit PTL[1] corresponds to the first output terminal of the digital-analog conversion circuit DAC. Similarly, the input terminal of the selector circuit PTL[N] corresponds to the Nth input terminal of the digital-analog conversion circuit DAC, and the output terminal of the selector circuit PTL[N] corresponds to the Nth output terminal of the digital-analog conversion circuit DAC.

[0116] Each of the amplifiers AP[1] to AP[N] functions as an analog buffer that amplifies an image signal, which is an analog potential, for example. Note that in FIG. 2 , each of the amplifiers AP[1] to AP[N] includes a differential amplifier circuit, for example, and can be configured as a voltage follower in which the output terminal and inverting input terminal of the differential amplifier circuit are directly connected. Therefore, each of the amplifiers AP[1] to AP[N] can output an image signal input to its input terminal with an amplification factor (sometimes referred to as an amplification rate) of 1 to its output terminal. Specifically, the voltage follower included in each of the amplifiers AP[1] to AP[N] can amplify an image signal input to the non-inverting input terminal of the differential amplifier circuit with an amplification factor of 1 and output the amplified signal to the output terminal of the differential amplifier circuit. Therefore, the input terminal of the amplifier AP can be regarded as the non-inverting input terminal of the differential amplifier circuit, and the output terminal of the amplifier AP can be regarded as the inverting input terminal or output terminal of the differential amplifier circuit.

[0117] The drive of the amplifier AP[j] can be controlled by switching the switch SWA[j] between an on state and an off state. For example, when transmitting image data to the wiring SL[j], the switch SWA[j] is turned on to establish electrical continuity between the output terminal of the amplifier AP[j] and the wiring SL[j], thereby transmitting an image signal from the amplifier AP[j] to the wiring SL[j], and thereby transmitting the image signal to the pixel circuit connected to the wiring SL[j].

[0118] Furthermore, for example, when image data is not transmitted to the wiring SL[j], the output of the amplifier AP[j] can be set to high impedance by turning off the switch SWA[j], and a non-conductive state is established between the output terminal of the amplifier AP[j] and the wiring SL[j]. When the image displayed on the pixel circuit arranged in the jth column of the pixel array does not change, the amplifier AP[j] can be stopped by setting the output of the amplifier AP[j] to high impedance, as described above. This reduces the power consumption of the amplifier AP[j].

[0119] Furthermore, each of the switches SWA[1] to SWA[N] can be, for example, an electrical switch such as an analog switch or a transistor. In particular, it is more preferable to use an OS transistor as the electrical switch for each of the switches SWA[1] to SWA[N]. Note that when an electrical switch is used for each of the switches SWA[1] to SWA[N], the electrical switch can be, for example, a Si transistor other than an OS transistor. Furthermore, each of the switches SWA[1] to SWA[N] can be, for example, a mechanical switch.

[0120] In addition, in this specification, each of switches SWA[1] to SWA[N] is assumed to be in an on state when a high-level potential is applied to the control terminal, and to be in an off state when a low-level potential is applied to the control terminal.

[0121] Note that, for example, a transistor containing indium oxide in a channel formation region is preferably used as the OS transistor, which can improve on-state characteristics and reduce off-state current.

[0122] <<Configuration Example of Digital-Analog Conversion Circuit>> Figure 1 shows an example of the circuit configuration of a digital-analog conversion circuit DAC. Note that the digital-analog conversion circuit DAC shown in Figure 1 is configured to convert a 9-bit digital signal (image signal) into an analog potential. Specifically, as an example, Figure 1 shows a voltage generation circuit RSTR that generates an analog potential with a 9-bit resolution (a potential corresponding to a value from "0" to "511") and a selector circuit PTL[j] that selects and outputs one of the 9-bit analog potentials. Figure 1 also shows an amplifier AP[j] and wiring SEL[j] to clarify the connection between the digital-analog conversion circuit DAC and its peripheral circuits.

[0123] The selector circuit PTL[j] is a circuit corresponding to the j-th one of the selector circuits PTL[1] to PTL[N] shown in Figure 2. The amplifier AP[j] is a circuit corresponding to the j-th one of the amplifiers AP[1] to AP[N] shown in Figure 2. The wiring SEL[j] is a wiring corresponding to the j-th one of the wirings SEL[1] to SEL[N] shown in Figure 2.

[0124] 1 has a resolution of 9 bits, the wiring SEL is treated as a wiring group having wirings for 9 bits. In FIG. 1, the wiring SEL is treated as a wiring group having wirings SELa_0 to SELa_8.

[0125] The wiring SELa_0 functions as a wiring that transmits the value of the 0th bit as a signal, and the wiring SELa_8 functions as a wiring that transmits the value of the 8th bit as a signal.

[0126] As an example, the voltage generating circuit RSTR has two terminals for outputting the 9-bit analog potentials generated by the circuit itself. ９ 1, the output terminals are shown as terminals VOT_0 to VOT_511.

[0127] The selector circuit PTL[j] has two terminals for acquiring the 9-bit analog potential generated by the voltage generation circuit RSTR. ９ 1, the input terminals are shown as terminals VIT_0 to VIT_511.

[0128] As an example, the voltage generation circuit RSTR includes amplifiers GA_0 to GA_511, an amplifier DHA, an amplifier DLA, resistors Ra_1 to Ra_511, resistors Rb_1 to Rb_511, resistors DHRaS, resistors DHRbS, resistors DLRaS, and resistors DLRbS.

[0129] In addition, in FIG. 1, in the voltage generating circuit RSTR, a circuit including the amplifiers GA_0 to GA_511, the resistors Ra_1 to Ra_511, and the resistors Rb_1 to Rb_511 is shown as a circuit RSTRA.

[0130] Each of the amplifiers GA_0 to GA_511, the amplifier DHA, and the amplifier DLA functions as a gamma amplifier. Note that in Fig. 1, the gamma amplifier is shown as a voltage follower using a differential amplifier circuit. That is, each of the amplifiers GA_0 to GA_511, the amplifier DHA, and the amplifier DLA has an amplification factor of 1, so the potential of the input terminal and the potential of the output terminal are equal.

[0131] In the voltage generation circuit RSTR, the resistors Ra_1 to Ra_511 are connected in series, and therefore in this specification, the resistors Ra_1 to Ra_511 may be collectively referred to as a resistor string. In addition, the resistors Ra_1 to Ra_511 are connected in series with the resistors DHRaS and DLRaS, and therefore the resistors Ra_1 to Ra_511 may be collectively referred to as a resistor string.

[0132] Similarly, in the voltage generation circuit RSTR, the resistors Rb_1 to Rb_511 are connected in series, and therefore in this specification, the resistors Rb_1 to Rb_511 are collectively referred to as a resistor string. Furthermore, the resistors Rb_1 to Rb_511 are connected in series with the resistors DHRbS and DLRbS, and therefore the resistors Rb_1 to Rb_511 and either or both of the resistors DHRbS and DLRbS are collectively treated as a single resistor string.

[0133] 1, as an example, each of the resistive elements DHRaS, DLRaS, DHRbS, and DLRbS is shown to include a plurality of resistive elements. One aspect of the present invention is not limited to this, and for example, each of the resistive elements DHRaS, DLRaS, DHRbS, and DLRbS may include a single resistive element instead of a plurality of resistive elements.

[0134] 1, as an example, each of the resistors Ra_1 to Ra_511 and the resistors Rb_1 to Rb_511 is illustrated as a single resistor. One embodiment of the present invention is not limited thereto, and for example, each of the resistors Ra_1 to Ra_511 and the resistors Rb_1 to Rb_511 may include a plurality of resistors, such as the resistors DHRaS, DLRaS, DHRbS, and DLRbS, instead of a single resistor.

[0135] In this specification, the resistor DHRaS, the resistors Ra_1 to Ra_511, the resistor DLRaS, the resistor DHRbS, the resistors Rb_1 to Rb_511, and the resistor DLRbS may be referred to as wirings having resistance values.

[0136] In the resistor string of the resistor element DLRaS, the resistor elements Ra_1 to Ra_511, and the resistor element DHRaS, one end of the resistor element Ra_1 is connected to one end of the resistor element DLRaS and the input terminal of the amplifier GA_0, and one end of the resistor element Ra_511 is connected to one end of the resistor element DHRaS and the input terminal of the amplifier GA_511. Also, the input terminal of the amplifier GA_p-1 is connected to a region where the resistor element Ra_p-1 (p is an integer between 2 and 511) and the resistor element Ra_p are connected to each other.

[0137] The other end of the resistor element DLRaS is connected to the wiring VSE and the input terminal of the amplifier DLA. The other end of the resistor element DHRaS is connected to the wiring VDE and the input terminal of the amplifier DHA.

[0138] In the resistor string of the resistor element DLRbS, resistor elements Rb_1 to Rb_511, and resistor element DHRbS, one end of the resistor element Rb_1 is connected to one end of the resistor element DLRbS and the output terminal of the amplifier GA_0, and one end of the resistor element Rb_511 is connected to one end of the resistor element DHRbS and the output terminal of the amplifier GA_511. In addition, the output terminal of the amplifier GA_p-1 is connected to the region where the resistor elements Rb_p-1 and Rb_p are connected to each other.

[0139] The other end of the resistor element DLRbS is connected to the output terminal of the amplifier DLA, and the other end of the resistor element DHRbS is connected to the output terminal of the amplifier DHA.

[0140] The output terminal of the amplifier GA_0 is connected to the terminal VOT_0, and the output terminal of the amplifier GA_511 is connected to the terminal VOT_511. The output terminal of the amplifier GA_p-1 is connected to the terminal VOT_p-1.

[0141] For example, the wiring VDE functions as a wiring that supplies a high power supply potential to generate an analog potential corresponding to the resolution in the voltage generation circuit RSTR, and the wiring VSE functions as a wiring that supplies a low power supply potential to generate an analog potential corresponding to the resolution in the voltage generation circuit RSTR.

[0142] Here, consider a case where the amplifier DLA, the amplifier DHA, the resistor element DLRaS, the resistor element DHRaS, the resistor element DLRbS, and the resistor element DHRbS are not provided in the voltage generating circuit RSTR of Fig. 1, and the wiring VSE is connected to the input terminal of the amplifier GA_0, and further the wiring VDE is connected to the input terminal of the amplifier GA_511 (see Fig. 3). In other words, consider a case where a 9-bit analog potential is generated using only the circuit RSTRA shown in Fig. 1.

[0143] 3, the potential output from the output terminal of the amplifier GA_0 is preferably equal to the low power supply potential provided by the wiring VSE. However, in reality, since a wiring resistance (sometimes called a parasitic resistance) exists between the output terminal of the amplifier GA_0 and one end of the resistor Rb_1, the potential of the connection region between the output terminal of the amplifier GA_0 and one end of the resistor Rb_1 may become higher than the low power supply potential.

[0144] Similarly, the potential output from the output terminal of the amplifier GA_511 is preferably equal to the high power supply potential provided by the wiring VDE. However, in reality, since wiring resistance (parasitic resistance) exists between the output terminal of the amplifier GA_511 and one end of the resistor Rb_511, the potential of the connection region between the output terminal of the amplifier GA_511 and one end of the resistor Rb_511 may be lower than the high power supply potential.

[0145] Similarly to the above, the potential at the connection region between the resistor element Rb_p-1 and the resistor element Rb_p may also deviate from the expected value due to the wiring resistance (parasitic resistance) between the output terminal of the amplifier GA_p and the connection region.

[0146] In other words, to summarize the above, the wiring resistance (parasitic resistance) between the output terminal of any one of amplifiers GA_0 to GA_511 and the resistor string including resistor elements Rb_1 to Rb_511 may cause the voltage output from terminals VOT_0 to VOT_511 of the voltage generation circuit RSTR to deviate from the desired gradation voltage.

[0147] 3 , the amount of current flowing from the amplifiers GA_0 to GA_511 to the resistor string including the resistor elements Rb_1 to Rb_511 is dominated by the current flowing from the bottom amplifier GA_0 and the top amplifier GA_511. Conversely, the amount of current flowing from the amplifiers GA near the center, for example, the amplifiers GA_200 to GA_300, to the resistor string is smaller than that from the bottom amplifier GA_0 and the top amplifier GA_511. For this reason, the deviation from the desired grayscale voltage at each of the above-mentioned terminals VOT_0 to VOT_511 is greatest at terminals VOT_0 and VOT_511, and smallest at terminals VOT_255, VOT_256, or terminals nearby.

[0148] 1 has a configuration that solves the above-mentioned problem, and by providing an amplifier DLA, an amplifier DHA, and resistor elements DLRaS, DHRaS, DLRbS, and DHRbS to the configuration of Fig. 3, the amount of current flowing through the resistor string of resistor elements Rb_1 to Rb_511 is largely dominated by the amount of current flowing from the amplifier DLA and the amplifier DHA, and it is possible to reduce the amount of current flowing from the amplifier GA_0 and the amplifier GA_511. This makes it possible to reduce deviations from the desired grayscale voltages at the terminals VOT_0 to VOT_511.

[0149] Furthermore, in the voltage generation circuit RSTR of the digital-to-analog conversion circuit DAC shown in FIG. 1, if deviations from the desired gradation voltages at each of the terminals VOT_0 to VOT_511 are not acceptable, it may be possible to further reduce the deviations from the desired gradation voltages at each of the terminals VOT_0 to VOT_511 by further increasing the number of amplifiers DHA or amplifiers DLA outside the circuit RSTRa.

[0150] The voltage generation circuit RSTR shown in Fig. 4 has a configuration in which the amplifier DHA in the voltage generation circuit RSTR in Fig. 1 is replaced with amplifiers DHA_1 to DHA_Q (where Q is an integer of 2 or more), and the amplifier DLA is replaced with amplifiers DLA_1 to DLA_R (where R is an integer of 2 or more). Also, in the voltage generation circuit RSTR shown in Fig. 4, the resistor DHRaS has resistors DHRa_1 to DHRa_Q, and the resistor DLRaS has resistors DLRa_1 to DLRa_R.

[0151] One end of the resistor element DHRa_1 is connected to the input terminal of the amplifier DHA_1 and one end of the resistor element DHRa_2 (not shown), and the other end of the resistor element DHRa_1 is connected to the input terminal of the amplifier GA_511 and one end of the resistor element Ra_511. One end of the resistor element DHRa_Q is connected to the input terminal of the amplifier DHA_Q and the wiring VDE. The input terminal of the amplifier DHA_q-1 is connected to a region where the resistor elements DHRa_q-1 (where q is an integer between 2 and Q) and DHRa_q are connected to each other.

[0152] One end of resistor DHRb_1 is connected to the output terminal of amplifier DHA_1 and one end of resistor DHRb_2 (not shown), and the other end of resistor DHRb_1 is connected to the output terminal of amplifier GA_511 and one end of resistor Rb_511. One end of resistor DHRb_Q is connected to the output terminal of amplifier DHA_Q. The output terminal of amplifier DHA_q-1 is connected to the region where resistor DHRb_q-1 and resistor DHRb_q are connected to each other.

[0153] One end of the resistor element DLRa_1 is connected to the input terminal of the amplifier DLA_1 and one end of the resistor element DLRa_2 (not shown), and the other end of the resistor element DLRa_1 is connected to the input terminal of the amplifier GA_0 and one end of the resistor element Ra_1. One end of the resistor element DLRa_R is connected to the input terminal of the amplifier DLA_R and the wiring VSE. The input terminal of the amplifier DLRa_r-1 is connected to a region where the resistor element DLRa_r-1 (here, r is an integer between 2 and R) and the resistor element DLRa_r are connected to each other.

[0154] One end of the resistor element DLRb_1 is connected to the output terminal of the amplifier DLA_1 and one end of the resistor element DLRb_2 (not shown), and the other end of the resistor element DLRb_1 is connected to the output terminal of the amplifier GA_0 and one end of the resistor element Rb_1. One end of the resistor element DLRb_R is connected to the output terminal of the amplifier DLA_R. The output terminal of the amplifier DLA_r-1 is connected to the region where the resistor elements DLRb_r-1 and DLRb_r are connected to each other.

[0155] As described above, in the voltage generation circuit RSTR of the digital-to-analog conversion circuit DAC shown in FIG. 1, if deviations from the desired gradation voltages at each of the terminals VOT_0 to VOT_511 are not acceptable, the deviations from the desired gradation voltages at each of the terminals VOT_0 to VOT_511 can be further reduced by further increasing the number of amplifiers DHA or amplifiers DLA outside the circuit RSTRa, as in the voltage generation circuit RSTR shown in FIG. 4.

[0156] 1, the voltage generation circuit RSTR is provided with 512 amplifiers GA, but the number of amplifiers GA may be reduced if the purpose is to stabilize the voltages of the resistor strings of the resistor elements Ra_1 to Ra_511 and the resistor strings of the resistor elements Rb_1 to Rb_511. For example, as shown in FIG. 5, the voltage generation circuit RSTR may include 33 amplifiers GA, namely, amplifiers GAD_1 to GAD_33. 5, amplifier GAD_1 corresponds to amplifier GA_0 in the voltage generation circuit RSTR of FIG. 1, amplifier GAD_2 corresponds to amplifier GA_16 (not shown in FIG. 1) in the voltage generation circuit RSTR of FIG. 1, amplifier GAD_32 corresponds to amplifier GAD_497 (not shown in FIG. 1) in the voltage generation circuit RSTR of FIG. 1, and amplifier GAD_33 corresponds to amplifier GA_511 in the voltage generation circuit RSTR of FIG. 1. As shown in FIG. 5, by reducing the amplifier GA in the voltage generation circuit RSTR of FIG. 1, the power consumption in the voltage generation circuit RSTR can be reduced. Furthermore, the circuit area of ​​the voltage generation circuit RSTR can be reduced.

[0157] Next, a configuration example of the selector circuit PTL[j] shown in FIG. 1 and FIG. 3 to FIG. 5 will be described.

[0158] 6 is a circuit diagram of the digital-analog conversion circuit DAC, mainly showing an example of the configuration of the selector circuit PTL[j]. In addition, in order to clarify the connection between the digital-analog conversion circuit DAC and its peripheral circuits, the amplifier AP and the wirings SELa_0 to SELa_8 are also shown in FIG.

[0159] The selector circuit PTL[j] shown in Figure 6 is an analog multiplexer with a tree structure of pass transistor logic. Also, as shown in Figure 6, the selector circuit PTL[j] has one or more p-channel transistors and n-channel transistors. For example, when the analog multiplexer selects and outputs one of analog potentials with a resolution of H bits (H is an integer of 1 or more), the number of p-channel transistors and n-channel transistors included in the analog multiplexer is Σ2（ｈ−１） In addition, Σ2 （ｈ−１） is the number of times when the integer h is from 1 to H. （ｈ−１） Therefore, the total number of p-channel transistors and n-channel transistors is Σ2 ｈ In this specification, an analog multiplexer that selects and outputs one of analog potentials with a resolution of H bits is called an H-bit analog multiplexer.

[0160] One or more p-channel transistors and one or more n-channel transistors included in the selector circuit PTL[j] can be Si transistors. Alternatively, one or more n-channel transistors included in the selector circuit PTL[j] can be OS transistors. In particular, by using an OS transistor containing indium oxide in a channel formation region, which will be described in detail in Embodiment 2, the on-state characteristics of the transistor can be improved and the off-state current can be reduced.

[0161] Specifically, in the case of a 1-bit analog multiplexer, one p-channel transistor and one n-channel transistor are required to select and output one analog potential with 1-bit resolution. In the case of a 3-bit analog multiplexer, 1 + 2 + 4 = 7 p-channel transistors and 1 + 2 + 4 = 7 n-channel transistors are required to select and output one analog potential with 3-bit resolution. The selector circuit PTL[j] shown in Figure 6 is an analog multiplexer with 9-bit resolution and is configured to select and output one analog potential of 9 bits. Therefore, the number of p-channel transistors and the number of n-channel transistors are 1 + 2 + 4 + 8 + 16 + 32 + 64 + 128 + 256 = 511. Note that the selector circuit PTL[j] in Figure 6 shows only some, but not all, of the transistors.

[0162] The selector circuit PTL[j] in FIG. 6 also includes inverters INV_0 to INV_8 for controlling the on and off states of the transistors.

[0163] In addition, in an H-bit analog multiplexer, the number of transistors arranged in the H-h-th bit stage of the H bits is 2 ｈ For example, as shown in FIG. 6, in the case of an analog multiplexer with H=9 bits, there are two transistors arranged at the 9-1=8th bit (when h=1). One of the two transistors is a p-channel transistor, and the other is an n-channel transistor. The gates of the p-channel transistor and the n-channel transistor are connected to a wiring SELa_8 via an inverter INV_8, which transmits the value of the H-h=9-1=8th bit as a signal.

[0164] For example, in the case of an analog multiplexer with H=9 bits, there are 512 transistors arranged at the 0th bit (when h=9) (H-h=9-9). Of these 512 transistors, 256 are p-channel transistors, and the remaining 256 are n-channel transistors. The gates of 128 of the 256 p-channel transistors and 128 of the 256 n-channel transistors are connected to wiring SELa_0, which transmits the value of the 0th bit as a signal. The gates of the remaining 128 of the 256 p-channel transistors and 128 of the 256 n-channel transistors are connected to wiring SELa_0 via inverter INV_0.

[0165] 6 generates 9-bit analog potentials and outputs the respective potentials to terminals VOT_0 to VOT_511, similar to the voltage generation circuit RSTR in FIG. 1. Each of the terminals VOT_u (u is an integer between 0 and 511) is connected to the terminal VIT_u of the selector circuit PTL[j]. In other words, each of the terminals VOT_0 to VOT_511 of the voltage generation circuit RSTR is connected in a one-to-one relationship to one of the sources or drains of the 512 transistors arranged at the 0th bit in the selector circuit PTL[j].

[0166] 6, the on / off state of each of the 511 p-channel transistors and the 511 n-channel transistors included in the selector circuit PTL[j] is determined by the potentials of the 9-bit image signal transmitted to the wirings SELa_0 to SELa_8. This uniquely determines an electrical path between any one of the terminals VIT_0 to VIT_511 and the input terminal of the amplifier AP[j]. That is, one of the 9-bit analog potentials generated by the voltage generation circuit RSTR is selected in accordance with the potentials of the 9-bit image signal and input to the input terminal of the amplifier AP[j]. This converts the 9-bit image signal flowing through the wiring SEL[j] into an analog potential.

[0167] The p-channel transistor and the n-channel transistor described above can be Si transistors. The n-channel transistor can be an OS transistor. In particular, by using an OS transistor containing indium oxide in a channel formation region, which will be described in detail in Embodiment 2, the on-state characteristics of the transistor can be improved and the off-state current can be reduced.

[0168] <<Configuration Example of Voltage Generator>> Here, the circuit configuration of the amplifier GA, the amplifier DLA, or the amplifier DHA will be described. After describing the circuit configuration of the amplifier GA, an example of the layout of the voltage generator circuit RSTR will be described.

[0169] 7A is a circuit diagram of the amplifier GA, the amplifier DLA, or the amplifier DHA shown in FIGS. 1 and 3 to 5 . The circuit diagram of FIG. 7A also shows a terminal IT as an input terminal of the amplifier GA, the amplifier DLA, or the amplifier DHA, and a terminal OT as an output terminal. That is, the input terminals of the amplifiers GA, DLA, and DHA described above correspond to the terminal IT, and in this specification, the input terminals can be referred to as the terminal IT. The output terminals of the amplifiers GA, DLA, and DHA correspond to the terminal OT, and in this specification, the output terminals can be referred to as the terminal OT. As shown in FIG. 7A , the terminal IT can be regarded as the non-inverting input terminal of the differential amplifier circuit, and the terminal OT can be regarded as the output terminal and the inverting input terminal of the differential amplifier circuit.

[0170] Fig. 7B is a circuit diagram showing an example of the amplifier GA, the amplifier DLA, or the amplifier DHA shown in Fig. 1 and Fig. 3 to Fig. 5. Note that the circuit configurations of the amplifier GA, the amplifier DLA, and the amplifier DHA shown in Fig. 7B are examples of differential amplifier circuits.

[0171] 7B includes, for example, a transistor Mp1, a transistor Mp2, a transistor Mn1, and a transistor Mn2. Note that here, the transistors Mp1 and Mp2 are both p-channel transistors, and the transistors Mn1 and Mn2 are both n-channel transistors.

[0172] Note that the transistors Mp1, Mp2, Mn1, and Mn2 can be Si transistors. The transistors Mn1 and Mn2 can be OS transistors. In particular, by using the OS transistors containing indium oxide in their channel formation regions, which will be described in detail in Embodiment 2, the on-state characteristics of the transistors can be improved and the off-state current can be reduced.

[0173] The first terminal of transistor Mp1 and the first terminal of transistor Mp2 are each connected to wiring VHE. The second terminal of transistor Mp1 is connected to terminal OT, the first terminal of transistor Mn1, and the gate of transistor Mn2. The second terminal of transistor Mp2 is connected to the gate of transistor Mp1, the gate of transistor Mp2, and the first terminal of transistor Mn2. The second terminal of transistor Mn1 and the second terminal of transistor Mn2 are each connected to wiring VLE.

[0174] For example, the wiring VHE functions as a wiring that applies a high power supply potential for driving the amplifier GA, the amplifier DLA, or the amplifier DHA. Note that the high power supply potential can be equal to or higher than the high power supply potential applied by the wiring VDE.

[0175] For example, the wiring VLE functions as a wiring that applies a low power supply potential to drive the amplifier GA, the amplifier DLA, or the amplifier DHA. Note that the low power supply potential can be equal to or lower than the high power supply potential applied by the wiring VSE.

[0176] By configuring each of the amplifier GA, the amplifier DLA, and the amplifier DHA as shown in FIG. 7B, each of the amplifier GA, the amplifier DLA, and the amplifier DHA can be treated as a voltage follower.

[0177] Fig. 7C shows an example of the circuit configuration of an amplifier that can replace the amplifier GA, amplifier DLA, and amplifier DHA shown in Fig. 7A. In other words, the amplifier GA, amplifier DLA, and amplifier DHA shown in Fig. 7C can be an example of the amplifier GA, amplifier DLA, or amplifier DHA shown in Fig. 1, 3 to 5.

[0178] The amplifiers GA, DLA, and DHA shown in Figure 7C function as voltage followers, similar to the amplifiers GA, DLA, and DHA shown in Figures 7A and 7B. In addition to the above, the amplifiers GA, DLA, and DHA shown in Figure 7C also have the function of canceling the offset of the output voltage caused by the differential amplifier circuit. By canceling the offset of the output voltage caused by the differential amplifier circuit, the amplification factor of the amplifiers GA, DLA, and DHA shown in Figure 7C can be made closer to 1x.

[0179] As an example, the amplifier GA, amplifier DLA, and amplifier DHA in FIG. 7C each include a capacitance element CD, switches SW1 to SW4, and a differential amplifier circuit AM.

[0180] For example, the switches SW1 to SW4 can be configured using the same switches as the switches SWA[1] to SWA[N]. For example, the switches SW1 to SW4 can be configured using OS transistors as electrical switches.

[0181] Furthermore, like switches SWA[1] to SWA[N], each of switches SW1 to SW4 is turned on when a high-level potential is applied to its control terminal, and is turned off when a low-level potential is applied to its control terminal.

[0182] A first terminal of the switch SW2 is connected to the terminal IT and the non-inverting input terminal of the differential amplifier circuit AM, and a second terminal of the switch SW2 is connected to the first terminal of the capacitance element CD and the first terminal of the switch SW3. A second terminal of the capacitance element CD is connected to the inverting input terminal of the differential amplifier circuit AM and the first terminal of the switch SW1. A second terminal of the switch SW1 is connected to the second terminal of the switch SW3, the first terminal of the switch SW4, and the output terminal of the differential amplifier circuit AM. A second terminal of the switch SW4 is connected to the terminal OT.

[0183] The control terminal of switch SW1 is connected to wiring SWL1, the control terminal of switch SW2 is connected to wiring SWL2, the control terminal of switch SW3 is connected to wiring SWL3, and the control terminal of switch SW4 is connected to wiring SWL4.

[0184] Next, an example of a method for driving the amplifier GA, the amplifier DLA, and the amplifier DHA shown in Fig. 7C will be described. Fig. 7D is a timing chart showing a method for driving the amplifier GA, the amplifier DLA, and the amplifier DHA shown in Fig. 7C. Note that the timing chart shows changes in the potentials of the wirings SWL1 to SWL4 from time U1 to time U2 and around the same time.

[0185] In Fig. 7D, between time U1 and time U2, a preliminary operation for canceling the offset of the output voltage is performed in the amplifiers GA, DLA, and DHA shown in Fig. 7C. At this time, the data input to the terminal IT is blank.

[0186] Between time U1 and time U2, a high-level potential is applied to each of the wirings SWL1 and SWL2, and a low-level potential is applied to each of the wirings SWL3 and SWL4, so that the switches SW1 and SW2 are turned on and the switches SW3 and SW4 are turned off.

[0187] At this time, a state of conduction is established between the non-inverting input terminal and the output terminal of the differential amplifier circuit AM, and negative feedback is applied to the differential amplifier circuit AM. In other words, the differential amplifier circuit AM has a voltage follower configuration, and ideally, the potential of the non-inverting input terminal and the potential of the output terminal of the differential amplifier circuit AM are equal. However, in an actual circuit, a difference (offset) may occur between the potential of the non-inverting input terminal and the potential of the output terminal.

[0188] Here, the potential of the non-inverting input terminal of the differential amplifier circuit AM is V ｉｎ The potentials of the inverting input terminal and the output terminal of the differential amplifier circuit AM are V ｏｕｔ At this time, the offset with respect to the output voltage in the differential amplifier circuit AM is |V ｉｎ -V ｏｕｔIn addition, the pair of electrodes of the capacitance element CD are connected to each other by |V ｉｎ -V ｏｕｔ The voltage of | is written.

[0189] Between time U1 and time U2, the pair of electrodes of the capacitance element CD are connected to V ｉｎ -V ｏｕｔ After the voltage V is written, the high-level potential applied to the wiring SWL1 is changed to a low-level potential. This turns off the switch SW1, and the pair of electrodes of the capacitor CD are applied with V ｉｎ -V ｏｕｔ Next, the high-level potential applied to the wiring SWL2 is changed to a low-level potential, and the low-level potentials applied to the wirings SWL3 and SWL4 are changed to a high-level potential, thereby turning off the switch SW2 and turning on the switches SW3 and SW4.

[0190] At this time, the potential of the first terminal of the capacitance element CD is V ｉｎ The potential V output from the output terminal of the differential amplifier circuit AM ｏｕｔ This change causes the potential of the inverting input terminal of the differential amplifier circuit AM to change due to the capacitive coupling of the capacitance element CD. Specifically, the amount of change in the potential at the first terminal of the capacitance element CD is V ｏｕｔ -V ｉｎ When the capacitive coupling coefficient of the capacitance element CD is set to 1, the amount of change in the potential at the second terminal of the capacitance element CD is also V ｏｕｔ -V ｉｎ In other words, the potential of the inverting input terminal of the differential amplifier circuit AM is V ｏｕｔ ni|V ｉｎ -V ｏｕｔ This allows the offset of the output voltage of the differential amplifier circuit AM to be cancelled.

[0191] By performing a preliminary operation to cancel the offset of the output voltage of the differential amplifier circuit AM between time U1 and time U2, from time U2 onwards, the potential corresponding to the image data D[1], D[2], etc. that are sequentially transmitted to terminal IT can be amplified while reducing the influence of the offset.

[0192] <<Layout of Voltage Generator Circuit RSTR>> Next, an example of the layout of the voltage generator circuit RSTR will be described. Fig. 8 and Fig. 9 show a part of a schematic plan view of the voltage generator circuit RSTR. Fig. 8 shows amplifiers DLA, GA_0, and GA_1, as well as their peripheral circuit elements and wiring, and Fig. 9 shows amplifiers DHA, GA_510, and GA_511, as well as their peripheral circuit elements and wiring.

[0193] 8 and 9, the voltage generation circuit RSTR includes, as an example, a conductive layer 31, a conductive layer 32, a conductive layer 35, a semiconductor region 71, a low resistance region 72, a semiconductor region 73, a low resistance region 74, and a high resistance region 75. In order to clearly show the layout, the planar schematic views of FIGS. 8 and 9 do not show insulating layers included in the voltage generation circuit RSTR.

[0194] Consider a case where the channel formation regions of transistors Mp1, Mp2, Mn1, and Mn2 are included in a single-crystal substrate made of silicon. That is, consider a case where transistors Mp1, Mp2, Mn1, and Mn2 are each Si transistors. In this case, a circuit pattern including semiconductor region 71, low-resistance region 72, semiconductor region 73, low-resistance region 74, and high-resistance region 75 can be formed on the single-crystal substrate by performing exposure and development processes, etching processes, resist stripping and cleaning processes, etc. Furthermore, semiconductor region 71, low-resistance region 72, semiconductor region 73, low-resistance region 74, and high-resistance region 75 can be separately formed by adjusting the amount of carriers injected.

[0195] 8 and 9, the transistors Mp1, Mp2, Mn1, and Mn2 each have a Fin-type transistor structure. A Fin-type transistor structure is one in which, in a plan view, the width d1 of the semiconductor region 73 is shorter than the width d2 of the low-resistance region 74. A Fin-type transistor structure is one in which, in a cross-sectional view in the channel width direction (the direction along the width d1), the semiconductor region 73 has a convex shape, and the conductive layer 31 is formed so as to cover the convex shape of the semiconductor region 73. As described above, by forming the semiconductor region 73 to have a convex shape and the conductive layer 31 so as to cover the convex shape, the effective channel width of the semiconductor region 73 can be increased, thereby improving the on-state characteristics. Furthermore, the contribution of the electric field from the conductive layer 31 to the inside of the semiconductor region 73 is increased, thereby reducing the off-state current. For this reason, by applying Fin-type transistors to the transistors Mp1, Mp2, Mn1, and Mn2, the on-state characteristics of these transistors can be improved and the off-state current can be reduced. Note that Fin-type transistors will be described in detail in Embodiment 4.

[0196] 8 and 9 may be OS transistors instead of Si transistors, and one or more selected from the transistors Mp1, Mp2, Mn1, and Mn2 may include a conductive layer in a low-resistance region included in the OS transistor.

[0197] Furthermore, each of the resistor elements DRaL, Ra_1, Ra_2, Ra_511, DRaH, DRbL, Rb_1, Rb_2, Rb_510, Rb_511 and DRbH shown in Figures 1, 4 and 5 can be the high resistance region 75 shown in Figures 8 and 9.

[0198] When the high-resistance region 75 is formed on a single-crystal substrate made of silicon, the high-resistance region 75 may be referred to as a diffusion layer. In this case, the above-described resistive element may also be referred to as a diffused resistive element. The high-resistance region 75 may be formed on the single-crystal substrate using silicide, polysilicon, a conductive layer with low conductivity, or the like. If the high-resistance region 75 does not include a diffusion layer, a substrate other than a single-crystal substrate may be used to fabricate the voltage generating circuit RSTR. Specifically, for example, a substrate applicable to the substrate BS described in embodiment 4 may be used as the other substrate.

[0199] The resistivity of the high resistance region 75 is 1.0×10 −８ Ω・m or more 1.0×10 −７ It is preferable that the resistance is Ω·m or less, and 1.0×10 −７ Ω・m or more 1.0×10 −６ It is more preferable that the resistance is Ω·m or less, and 1.0×10 −６ Ω・m or more 1.0×10 −５ It is more preferable that the resistance is Ω·m or less.

[0200] As an example, the conductive layer 31 is provided above the semiconductor region 71, the low resistance region 72, the semiconductor region 73, the low resistance region 74, or the high resistance region 75. The conductive layer 31 also functions as a wiring and as the gates of the transistors Mp1, Mp2, Mn1, and Mn2.

[0201] For example, the conductive layer 32 is provided above the semiconductor region 71, the low-resistance region 72, the semiconductor region 73, the low-resistance region 74, the high-resistance region 75, or the conductive layer 31. The conductive layer 32 also functions as a wiring, and in particular, a part of the conductive layer 32 extends as a wiring VDE, a wiring VSE, a wiring VHE, or a wiring VLE. As shown in FIGS. 8 and 9 , the conductive layer 32 may also function as each of the terminals VOT_0 to VOT_511.

[0202] An insulating layer (not shown) functioning as an interlayer film is provided between the semiconductor region 71, the low-resistance region 72, the semiconductor region 73, the low-resistance region 74, the high-resistance region 75, or the conductive layer 31 and the conductive layer 32. Openings are provided in each of the following regions of the insulating layer: a partial region where the high-resistance region 75 and the conductive layer 32 overlap each other; a partial region where the low-resistance region 72 and the conductive layer 32 overlap each other; a partial region where the low-resistance region 74 and the conductive layer 32 overlap each other; and a partial region where the conductive layer 31 and the conductive layer 32 overlap each other. A conductive layer 35 is embedded in these openings.

[0203] By embedding the conductive layer 35 in the opening of the insulating layer, for example, charge can be transferred between the high-resistance region 75 and the conductive layer 32 via the conductive layer 35. Similarly, charge can be transferred between the low-resistance region 72 and the conductive layer 32 via the conductive layer 35, and charge can be transferred between the low-resistance region 74 and the conductive layer 32 via the conductive layer 35. Furthermore, charge can be transferred between the conductive layer 31 and the conductive layer 32 via the conductive layer 35. That is, in FIGS. 8 and 9 , the conductive layer 35 functions as a contact plug.

[0204] Each of the conductive layers 31, 32, and 35 preferably includes a material having high conductivity because a part of each of the conductive layers 31, 32, and 35 functions as a wiring. Specifically, for example, a material that can be used for the conductive layer 131, the conductive layer 132, the conductive layer 134, and the like described in Embodiment 4 can be used.

[0205] As described above, the high-resistance region 75 is preferably made of a conductive material with high resistivity, while the conductive layers 31 and 32 are preferably made of conductive materials with low resistivity. From this perspective, the wiring width d3 of the high-resistance region 75 is preferably shorter than the wiring widths d41 and d42 of the conductive layer 32. The wiring width d3 of the high-resistance region 75 is preferably shorter than the wiring width d5 ​​of the conductive layer 31.

[0206] <<Example of Operation of Drive Circuit>> Next, an example of operation of the drive circuit SD will be described.

[0207] Fig. 10 is a timing chart illustrating an example of the operation of the driver circuit SD in Fig. 2. The timing chart illustrated in Fig. 10 illustrates changes in potentials of the wirings CKL1, CKL2[1], CKL2[2], CKL2[N], LL1, and SWL before time T01, from time T01 to time T08, and after time T08.

[0208] 10 also shows image data transmitted to the wiring DL and the wirings SL[1] to SL[N] at times T01 to T08. In FIG. 10, as an example, image data D[i,1] to D[i,N] to be written to the i-th row of the pixel array PXA are sequentially transmitted to the wiring DL.

[0209] [Between Time T01 and Time T07] Between Time T01 and Time T07, a high-level potential (denoted as "High" in FIG. 10) is input to the wiring CKL1, so that the high-level potential from the wiring CKL1 is input to the second terminals of the logic circuits LMP[1] to LMP[N].

[0210] Furthermore, between time T01 and time T07, a low-level potential (denoted as "Low" in FIG. 10) is input to the wiring LL1. As a result, a low-level potential is input to the second input terminals of the latch circuits LTA[1] to LTA[N]. At this time, the latch circuits LTA[1] to LTA[N] do not hold the data input to their first input terminals.

[0211] [Between Time T01 and Time T08] Between Time T01 and Time T08, a low-level potential is input to the wiring SWL. As a result, a low-level potential is applied to each of the control terminals of the switches SWA[1] to SWA[N], and the switches SWA[1] to SWA[N] are turned off. Therefore, between Time T01 and Time T08, the outputs of the amplifiers AP[1] to AP[N] become high impedance, and the operation of the amplifiers AP[1] to AP[N] stops. This reduces the power consumption of the driver circuit SD.

[0212] [Between Time T02 and Time T03] From Time T02 to Time T03, image data D[i,1] is transmitted to the wiring DL. Also, from Time T02 to Time T03, a high-level potential is output from the first output terminal of the shift register SR. As a result, a high-level potential is input to the first input terminal of the logic circuit LMP[1]. Also, a low-level potential is input to each of the second input terminals of the logic circuits LMP[2] to LMP[N]. As a result, the logic circuit LMP[1] outputs a high-level potential from its output terminal, and each of the logic circuits LMP[2] to LMP[N] outputs a low-level potential from its output terminal. As a result, the potential of the wiring CKL2[1] becomes a high-level potential, and the potentials of the wirings CKL2[2] to CKL2[N] become a low-level potential.

[0213] Therefore, a high-level potential is input from the line CKL2[1] to the clock input terminal of the flip-flop circuit FFA[1]. As a result, the flip-flop circuit FFA[1] holds the image data D[i,1] input to the input terminal DA and outputs the image data D[i,1] to the output terminal QA. In addition, the image data D[i,1] is input to the input terminal of the latch circuit LTA[1].

[0214] On the other hand, since the potentials of the wirings CKL2[2] to CKL2[N] are low, a low potential is input to the clock input terminals of the flip-flop circuits FFA[2] to FFA[N], and therefore the flip-flop circuits FFA[2] to FFA[N] do not hold the image data D[i,1] transmitted to the wiring DL.

[0215] [Between Time T03 and Time T04] From Time T03 to Time T04, image data D[i,2] is transmitted to the wiring DL. Also, from Time T03 to Time T04, a high-level potential is output from the second output terminal of the shift register SR. As a result, a high-level potential is input to the first input terminal of the logic circuit LMP[2]. Also, a low-level potential is input to the second input terminals of the logic circuit LMP[1] and the logic circuits LMP[3] to LMP[N]. As a result, the logic circuit LMP[2] outputs a high-level potential from its output terminal, and the logic circuit LMP[1] and the logic circuits LMP[3] to LMP[N] output a low-level potential from their output terminals. As a result, the potential of the wiring CKL2[2] becomes a high-level potential, and the potentials of the wiring CKL2[1] and the wirings CKL2[3] to CKL2[N] become low-level potentials.

[0216] Therefore, a high-level potential is input from the line CKL2[2] to the clock input terminal of the flip-flop circuit FFA[2]. As a result, the flip-flop circuit FFA[2] holds the image data D[i,2] input to the input terminal DA and outputs the image data D[i,2] to the output terminal QA. In addition, the image data D[i,2] is input to the input terminal of the latch circuit LTA[2].

[0217] On the other hand, since the potentials of the wirings CKL2[1] and CKL2[3] to CKL2[N] are low, a low potential is input to the clock input terminals of the flip-flop circuits FFA[1] and FFA[3] to FFA[N]. Therefore, the flip-flop circuits FFA[1] and FFA[3] to FFA[N] do not hold the image data D[i,2] transmitted to the wiring DL.

[0218] [Between Time T04 and Time T05] Between Time T04 and Time T05, image data D[i,3] to D[i,N-1] are sequentially transmitted to the wiring DL. Also, between Time T04 and Time T05, high-level potentials are sequentially output from the third to (N-1)th output terminals of the shift register SR. Note that low-level potentials are output to output terminals that do not output high-level potentials. As a result, high-level potentials are sequentially input to the first input terminals of the logic circuits LMP[3] to LMP[N-1]. Therefore, the potentials of the wirings CKL2[3] to CKL2[N-1] sequentially become high-level potentials.

[0219] As described above, similar to the flip-flop circuit FFA[1] from time T02 to time T03, or the flip-flop circuit FFA[2] from time T03 to time T04, the image data D[i,3] to D[i,N-1] are held in the flip-flop circuits FFA[3] to FFA[N-1], respectively, in the third to (N-1)th columns of the drive circuit SD from time T04 to time T05. Furthermore, the image data D[i,3] to D[i,N-1] are transmitted from the output terminals QA of the flip-flop circuits FFA[3] to FFA[N-1] to the latch circuits LTA[3] to LTA[N-1], respectively.

[0220] [Between Time T05 and Time T06] From Time T05 to Time T06, image data D[i,N] is transmitted to the wiring DL. Also, from Time T05 to Time T06, a high-level potential is output from the Nth output terminal of the shift register SR. As a result, a high-level potential is input to the first input terminal of the logic circuit LMP[N]. Also, a low-level potential is input to each second input terminal of the logic circuits LMP[1] to LMP[N-1]. As a result, the logic circuit LMP[N] outputs a high-level potential from its output terminal, and each of the logic circuits LMP[1] to LMP[N-1] outputs a low-level potential from its output terminal. As a result, the potential of the wiring CKL2[N] becomes a high-level potential, and the potentials of the wirings CKL2[1] to CKL2[N-1] become a low-level potential.

[0221] Therefore, a high-level potential is input from the line CKL2[N] to the clock input terminal of the flip-flop circuit FFA[N]. As a result, the flip-flop circuit FFA[N] holds the image data D[i,N] input to the input terminal DA and outputs the image data D[i,N] to the output terminal QA. In addition, the image data D[i,N] is input to the first input terminal of the latch circuit LTA[N].

[0222] On the other hand, since the potentials of the wirings CKL2[1] to CKL2[N-1] are low, a low potential is input to the clock input terminals of the flip-flop circuits FFA[1] to FFA[N-1], and therefore the flip-flop circuits FFA[1] to FFA[N-1] do not hold the image data D[i,N] transmitted to the wiring DL.

[0223] [Between Time T06 and Time T07] Between Time T06 and Time T07, the potential of the wiring CKL1 transitions from a high-level potential to a low-level potential. As a result, a low-level potential from the wiring CKL1 is input to the second input terminals of each of the logic circuits LMP[1] to LMP[N]. Therefore, regardless of the potential (e.g., high-level potential or low-level potential) input from the output terminal of the shift register SR to the first input terminals of each of the logic circuits LMP[1] to LMP[N], the output terminals of each of the logic circuits LMP[1] to LMP[N] output a low-level potential.

[0224] That is, the potentials of the wirings CKL2[1] to CKL2[N] become low-level potentials, and low-level potentials are input to the clock input terminals of the flip-flop circuits FFA[1] to FFA[N], respectively. As a result, the image data held in the flip-flop circuits FFA[1] to FFA[N] is not updated.

[0225]

[0074] Between time T07 and time T08, a high-level potential is applied to the wiring LL1, thereby applying a high-level potential to the second input terminals of the latch circuits LTA[1] to LTA[N].

[0226] When a high-level potential is applied to the second input terminal of each of the latch circuits LTA[1] to LTA[N], the latch circuits LTA[1] to LTA[N] each hold the image data applied to their first input terminal and output the image data to their output terminal. Specifically, the latch circuit LTA[1] holds the image data D[i,1] and outputs the image data D[i,1] from its output terminal. Similarly, the latch circuit LTA[2] holds the image data D[i,2] and outputs the image data D[i,2] from its output terminal, and the latch circuit LTA[N] holds the image data D[i,N] and outputs the image data D[i,N] from its output terminal.

[0227] The image data D[i,1] to D[i,N] output from the output terminals of the latch circuits LTA[1] to LTA[N] are input to the level shifter circuits LS[1] to LS[N], and the digital potentials corresponding to the image data D[i,1] to D[i,N] are shifted to a level that can be handled by the digital-to-analog conversion circuit DAC.

[0228] Furthermore, the level-shifted image data D[i,1] to D[i,N] are converted from digital potential to analog potential by a digital-analog conversion circuit DAC. For the digital-analog conversion circuit DAC, the description of the digital-analog conversion circuit DAC in Figures 1 to 6 can be referred to. Each of the image data D[i,1] to D[i,N] converted into analog potential is sent to the input terminal of the amplifier AP of each column.

[0229] Each of the amplifiers AP[1] to AP[N] functions as an analog buffer, and outputs to the output terminal a potential that is approximately equal to the analog potential corresponding to the image data D[i,1] to D[i,N] input to the input terminal.

[0230] Note that between time T07 and time T08, the wiring SWL continues to be supplied with a low-level potential from before time T07. Therefore, each of the switches SWA[1] to SWA[N] is in an off state. Therefore, the outputs of the amplifiers AP[1] to AP[N] have high impedance, and analog potentials corresponding to the image data D[i,1] to D[i,N] are not output to the wirings SL[1] to SL[N].

[0231] [Between Time T08 and Time T09] A high-level potential is applied to the wiring SWL between Time T08 and Time T09. As a result, a high-level potential is applied to each of the control terminals of the switches SWA[1] to SWA[N], turning on each of the switches SWA[1] to SWA[N].

[0232] As a result, conduction is established between the amplifier AP[j] and the wiring SL[j], and an analog potential corresponding to the image data D[i, j] is output from the output terminal of the amplifier AP[j] to the wiring SL[j]. Specifically, an analog potential corresponding to the image data D[i, 1] is output from the output terminal of the amplifier AP[1] to the wiring SL[1], an analog potential corresponding to the image data D[i, 2] is output from the output terminal of the amplifier AP[2] to the wiring SL[2], and an analog potential corresponding to the image data D[i, N] is output from the output terminal of the amplifier AP[N] to the wiring SL[N].

[0233] As described above, image data D[i,1] to D[i,N] can be written to pixel circuits PX[i,1] to PX[i,N] located in the i-th row of the pixel array PXA, respectively. Also, an image corresponding to the image data D[i,1] to D[i,N] can be displayed on the pixel array PXA.

[0234] <Structure Example 2 of Driver Circuit> Next, a structure of a driver circuit in a semiconductor device of one embodiment of the present invention, which is different from the driver circuit SD in FIG. 2, will be described.

[0235] The drive circuit SDA shown in Fig. 11 is a modified example of the drive circuit SD in Fig. 2, and differs from the drive circuit SD in that it includes switches SWB[1] to SWB[N]. Therefore, for the components of the drive circuit SDA shown in Fig. 11 that are common to the drive circuit SD, the description of the drive circuit SD in Fig. 2 can be referred to.

[0236] 11 has a circuit configuration that can transmit each image signal to the wiring SL[1] to the wiring SL[N] without using the amplifiers AP[1] to AP[N]. Specifically, when the image signal can be amplified by the amplifiers provided in the digital-analog conversion circuit DAC, each of the switches SWA[1] to SWA[N] is turned off and each of the switches SWB[1] to SWB[N] is turned on to transmit each image signal output from the digital-analog conversion circuit DAC to the wiring SL[1] to the wiring SL[N]. This deactivates each of the amplifiers AP[1] to AP[N], thereby reducing the power consumption of each of the amplifiers AP[1] to AP[N].

[0237] 11, the first and Nth rows of the N rows are selectively shown, as in Fig. 2. Therefore, Fig. 11 selectively shows the switches SWB[1] and SWB[N] from the switches SWB[1] to SWB[N].

[0238] For example, the switches SWB[1] to SWB[N] can be configured using the same switches as the switches SWA[1] to SWA[N]. For example, the switches SWB[1] to SWB[N] can be configured using OS transistors as electrical switches.

[0239] Furthermore, like switches SWA[1] to SWA[N], each of switches SWB[1] to SWB[N] is turned on when a high-level potential is applied to its control terminal, and is turned off when a low-level potential is applied to its control terminal.

[0240] 11 (where j is an integer between 1 and N), the first terminal of the switch SWB[j] is connected to the jth output terminal of the digital-to-analog converter circuit DAC and the input terminal of the amplifier AP[j]. The second terminal of the switch SWB[j] is connected to the second terminal of the switch SWA[j] and the wiring SL[j]. The control terminal of the switch SWB[j] is connected to the wiring SWLB.

[0241] For example, the wiring SWLB functions as a wiring for transmitting a signal for controlling the switching between the on state and the off state of each of the switches SWB[1] to SWB[N].

[0242] If the amplifier provided in the digital-to-analog conversion circuit DAC is not sufficient to amplify the image signal, the switch SWB[j] can be turned off and the switch SWA[j] can be turned on, and the image signal output from the jth output terminal of the digital-to-analog conversion circuit DAC can be amplified by the amplifier AP[j], and the image signal can be transmitted to the wiring SL[j].

[0243] At this time, a high-level potential is preferably applied to the wiring SWL to turn on the switch SWA[j], and a low-level potential is preferably applied to the wiring SWLB to turn off the switch SWB[j]. In this specification, the operation mode in which the amplifier AP[j] is used to amplify the image signal transmitted to the wiring SL[j] is referred to as a first mode (also referred to as a normal mode).

[0244] As described above, the driver circuit SDA in FIG. 11 can stop the amplifier AP[j] by turning off the switch SWA[j], and can transmit the image signal output from the jth output terminal of the digital-analog conversion circuit DAC to the wiring SL[j] via the switch SWB[j] by turning on the switch SWB[j]. This operation is suitable for the case where the image signal transmitted to the wiring SL[j] can be amplified using an amplifier included in the digital-analog conversion circuit DAC, specifically, the amplifiers GA_0 to GA_511, the amplifier DHA, the amplifier DLA, etc., shown in FIGS. 1, 3 to 5, etc., instead of the amplifier AP[j]. Furthermore, this operation stops the amplifier AP[j], thereby reducing the power consumption of the driver circuit SDA.

[0245] At this time, a low-level potential is preferably applied to the wiring SWL to turn off the switch SWA[j], and a high-level potential is preferably applied to the wiring SWLB to turn on the switch SWB[j]. In this specification, the operation mode in which the amplifier AP[j] is stopped and the image signal transmitted to the wiring SL[j] is amplified by the amplifier included in the digital-to-analog conversion circuit DAC is referred to as a second mode (also referred to as an amplifier mode).

[0246] As described above, by using the driver circuit SDA, it is possible to select whether to use the amplifier AP[j] when transmitting an image signal from the driver circuit SDA to the wiring SL[j].

[0247] 12 is a block diagram showing an example of the configuration of a display device having the drive circuit described above. As an example, the display device DSP is configured to include a pixel array PXA, a drive circuit GD, and a drive circuit SD.

[0248] The pixel array PXA, the drive circuit GD, and the drive circuit SD may be provided on the same support. Some or all of the circuits listed above may be formed directly on the support, or may be mounted on the support using a COG (chip on glass) method or the like. Some or all of the circuits listed above may be mounted on a flexible printed circuit (FPC) electrically connected to the support using a COF (chip on film) method or the like.

[0249] As an example, the pixel array PXA includes a plurality of pixel circuits PX. The plurality of pixel circuits PX are arranged in an array in the pixel array PXA. For example, the pixel array PXA includes a plurality of pixel circuits PX arranged in any one of a matrix array, a stripe array, an S-stripe array, a delta array, a Bayer array, a Pentile array, and the like. In FIG. 12 , the pixel circuit PX located in the i-th row and j-th column (i is an integer equal to or greater than 1, and j is an integer equal to or greater than 1) among the plurality of pixel circuits PX is represented as pixel circuit PX[i, j]. The pixel array PXA may include only one pixel circuit PX instead of a plurality of pixel circuits PX.

[0250] The multiple pixel circuits PX have the function of, for example, acquiring an image signal transmitted from a drive circuit SD (described later) and emitting light of an intensity corresponding to the image signal. Note that one pixel circuit PX may include two or more sub-pixel circuits. For example, the number of sub-pixel circuits included in one pixel circuit PX and the colors of their emitted light may be determined so that the light emitted by the multiple sub-pixel circuits is combined to produce white light. For example, by setting the emission colors of the multiple sub-pixel circuits included in the pixel circuit PX to red (R), green (G), and blue (B), the pixel circuit PX as a whole can be configured as a circuit capable of emitting white light.

[0251] The screen resolution of the display device DSP is determined according to the number of pixel circuits PX included in the pixel array PXA. For example, if the screen resolution of the display device DSP is 8K4K, the number of pixel circuits PX included in the pixel array PXA is 7680 x 4320. Furthermore, if the pixel circuit PX includes, for example, three sub-pixel circuits of red (R), green (G), and blue (B), the total number of such sub-pixel circuits included in the pixel array PXA is 7680 x 4320 x 3. The screen resolution of the display device DSP may be SD (720 x 480 pixel circuits PX), HD (1280 x 720 pixel circuits PX), FHD (1920 x 1080 pixel circuits PX), or 4K2K (3840 x 2160 pixel circuits PX). Furthermore, the screen resolution of the display device DSP is not limited to the above, and may be determined arbitrarily at the design stage of the display device DSP.

[0252] The diagonal size of the display area (for example, the pixel array PXA) of the display device DSP can be determined by the electronic device equipped with the display device DSP. For example, in applications involving large displays such as television devices, the diagonal size of the display area may be 20 inches or more, 30 inches or more, 60 inches or more, or 100 inches or more. In applications involving small to medium-sized displays such as tablet information terminals or mobile information terminals, the diagonal size of the display area may be 3 inches or more and 13 inches or less. In applications involving small displays such as XR devices and wearable information terminals, the diagonal size may be 3 inches or less, 1.5 inches or less, or 1 inch or less, for example.

[0253] The resolution of the display area of ​​the display device DSP (sometimes referred to as pixel density) is determined by the screen resolution and diagonal size described above. For example, when the display device DSP is used in a large display, the resolution of the display area of ​​the display device DSP is preferably, for example, 50 ppi or more, more preferably 100 ppi or more, and even more preferably 150 ppi or more. When the display device DSP is used in a small or medium-sized display, the resolution of the display area of ​​the display device DSP is preferably, for example, 200 ppi or more, more preferably 400 ppi or more, and even more preferably 800 ppi or more. When the display device DSP is used in a small display, the resolution of the display area of ​​the display device DSP is preferably, for example, 1000 ppi or more, more preferably 2000 ppi or more, and even more preferably 4000 ppi or more.

[0254] Furthermore, there is no particular limitation on the screen ratio (aspect ratio) of the display area (for example, the pixel array PXA) of the display device DSP, and the display area can accommodate various screen ratios such as 1:1 (square), 4:3, 16:9, 16:10, 21:9, or 32:9.

[0255] The drive circuit GD functions as, for example, a gate driver circuit for selecting a pixel circuit PX included in the pixel array PXA to which an image signal is to be written.

[0256] The drive circuit SD functions as, for example, a source driver circuit for transmitting image signals to the pixel circuits PX included in the pixel array PXA.

[0257] The pixel circuit PX[i,j] is electrically connected to the drive circuit GD via a wiring GLS[i], for example. The pixel circuit PX[i,j] is also electrically connected to the drive circuit SD via a wiring SLS[j], for example.

[0258] As an example, the wiring GLS[i] functions as a wiring (sometimes referred to as a gate line in this specification) for transmitting a selection signal from the driving circuit GD to the pixel circuit PX[i,j] to drive the pixel circuit PX[i,j].

[0259] As an example, the wiring SLS[j] functions as a wiring (sometimes referred to as a source line, data line, etc. in this specification) for transmitting an image signal from the driving circuit SD to the pixel circuit PX[i,j] to display an image on the pixel circuit PX[i,j].

[0260] Note that the wiring GLS[i] may be a single wiring or a wiring group including multiple wirings. Similarly, the wiring SLS[j] may be a single wiring or a wiring group including multiple wirings.

[0261] The display device DSP of Fig. 12 may have the configuration of a display device DSPA shown in Fig. 13. The display device DSPA of Fig. 13 has a configuration in which a pixel array PXA is divided into a plurality of display areas PXDM, and drive circuits GD and drive circuits SD are provided in the same number as the number of display areas PXDM. In particular, in Fig. 13, a circuit area CIA is provided as an area having a plurality of drive circuits GD and a plurality of drive circuits SD, and the pixel array PXA is provided so as to overlap with the circuit area CIA.

[0262] Furthermore, the circuit area CIA has the same number of drive circuit areas DRDM as the number of display areas PXDM, and each drive circuit area DRDM includes one drive circuit GD and one drive circuit SD.

[0263] Furthermore, one display region PXDM corresponds to one drive circuit region DRDM, and the pixel circuits PX included in that display region PXDM are connected to the drive circuit GD included in that drive circuit region DRDM via wiring GLS, and are also connected to the drive circuit SD via wiring SLS. Furthermore, since the display region PXDM is located above the drive circuit region DRDM, it can be said that each of the wiring SLS and the wiring GLS has a region extending in the height direction, such as a plug.

[0264] 13 is configured such that the driver circuits GD and SD are connected to each of the display regions PXDM obtained by dividing the pixel array PXA into a plurality of regions, thereby reducing the number of pixel circuits PX handled by each of the driver circuits GD and SD. Furthermore, because the driver circuits GD and SD are disposed below the pixel array PXA, the lengths of the wiring SLS and wiring GLS can be shortened. This reduces the attenuation or delay of signals transmitted from the driver circuits GD or SD to the pixel circuits PX.

[0265] 13, the driver circuit GD and the driver circuit SD are arranged below the pixel array PXA, which allows the frame area of ​​the display device DSPA to be reduced. As a result, when the display device DSPA is applied to an electronic device, the housing of the electronic device can be made smaller, thereby enabling the electronic device to be made more compact.

[0266] The display device DSP in Fig. 12 may have the configuration of a display device DSPB shown in Fig. 14. The display device DSPB in Fig. 14 has a circuit area CIA and a pixel array PXA overlapping the circuit area CIA, similar to the display device DSPA in Fig. 13.

[0267] The pixel array PXA of the display device DSPB is divided into a plurality of display regions PXDM. Specifically, the pixel array PXA is divided into a certain number of rows as shown in FIG.

[0268] The circuit area CIA is provided with as many drive circuits SD as the divided display areas PXDM, and one drive circuit GD is provided in the circuit area CIA so as to be connected to the pixel circuits PX included in all the display areas PXDM.

[0269] As shown in the display device DSPB in Figure 14, by providing a drive circuit SD in each of the display areas PXDM divided into a certain number of rows, the number of drive circuits SD can be reduced compared to the number provided in the circuit area CIA in Figure 13. By reducing the number of drive circuits SD, the number of wirings that provide power supply potential, etc. can be reduced, thereby reducing the parasitic capacitance of the wiring and thereby increasing the drive speed of the display device DSPB. Furthermore, by reducing the number of drive circuits SD, the number of digital-analog conversion circuits, etc. provided in the circuit area CIA can be reduced, thereby reducing the power consumption of the digital-analog conversion circuits.

[0270] Note that the display device of one embodiment of the present invention is not limited to the display device DSPB in Fig. 14. The display device of one embodiment of the present invention may have a configuration in which two driver circuits GD are provided on both sides of the circuit region CIA, instead of the configuration in which one driver circuit GD is provided in the circuit region CIA in the display device DSPB in Fig. 14 (see Fig. 15).

[0271] Note that this embodiment mode can be appropriately combined with the same or other embodiment modes described in this specification. For example, the configurations, structures, methods, and the like described in this embodiment mode can be appropriately combined and used with the configurations, structures, methods, and the like described in the other embodiment modes. For example, the configurations, structures, methods, and the like described in this embodiment mode can be appropriately combined and used with the configurations, structures, methods, and the like described in the other embodiment modes.

[0272] Embodiment 2 In this embodiment, a metal oxide that functions as an oxide semiconductor will be described.

[0273] <Metal Oxide (Oxide Semiconductor)> The OS transistor described in the above embodiment preferably includes a metal oxide that functions as an oxide semiconductor and that includes a channel formation region. For example, the metal oxide that includes the channel formation region preferably has a band gap of 2 eV or more, preferably 2.5 eV or more, and more preferably 3.0 eV or more. Specifically, for example, a metal oxide that functions as an oxide semiconductor is preferably used for active layers of the n-channel transistor shown in FIG. 6 and the transistors Mn1 and Mn2 shown in FIG. 7B.

[0274] Note that metal oxide structures are divided into single-crystal structures and other structures (non-single-crystal structures). Examples of non-single-crystal structures include a c-axis aligned crystalline (CAAC) structure, a polycrystalline (polycrystalline) structure, a nanocrystalline (nc) structure, a pseudo-amorphous (a-like) structure, and an amorphous structure. The structure of the metal oxide of one embodiment of the present invention is not particularly limited, and any of the above structures can be used. However, use of a crystalline metal oxide, such as a CAAC structure or an nc structure, is preferable because a highly reliable semiconductor device can be obtained.

[0275] The metal oxide can be an oxide semiconductor having an axial growth CAAC (AG CAAC) structure. The AG CAAC refers to an oxide semiconductor having a CAAC structure, which is produced by solid-phase growth of a metal oxide contained in an oxide semiconductor layer including a first layer and a second layer having higher crystallinity than the first layer, using the second layer as a nucleus or seed.

[0276] For example, the first layer is preferably formed by atomic layer deposition (ALD) or chemical vapor deposition (CVD). Examples of CVD include plasma enhanced CVD (PECVD), thermal CVD, photo-assisted CVD, and metal organic CVD (MOCVD). The first layer may also be formed by a wet process. Furthermore, molecular beam epitaxy (MBE), which is a film formation method for growing a thin film having a crystalline structure that reflects the crystalline system of the substrate, may also be used. These film formation methods can reduce damage to the surface to be formed compared to sputtering.

[0277] Next, the second layer is preferably formed by sputtering or pulsed laser deposition (PLD). By forming the second layer after the first layer, in particular, it is possible to prevent a mixed layer from being formed at the interface between the first and second layers. Furthermore, it is possible to prevent impurities contained in the surface on which the second layer is formed from being mixed into the second layer. These factors further enhance the crystallinity of the second layer.

[0278] Examples of methods for solid-phase growth of the metal oxide contained in the first layer using the second layer as a nucleus or seed include heat treatment, plasma treatment, microwave (typically 2.45 GHz) treatment, microwave plasma treatment, and light (e.g., ultraviolet light) irradiation treatment. Note that a plurality of these treatments may be performed simultaneously or sequentially. For example, heat treatment and microwave plasma treatment may be performed simultaneously. Alternatively, microwave plasma treatment may be performed after heat treatment.

[0279] In this specification, microwaves refer to electromagnetic waves having a frequency of 300 MHz to 300 GHz. Microwave plasma treatment refers to treatment using a device with a power source that generates high-density plasma using microwaves. Microwave plasma treatment can also be called microwave-excited high-density plasma treatment.

[0280] Furthermore, it is more preferable to perform the treatment for increasing the crystallinity of the oxide semiconductor layer multiple times during the formation of the oxide semiconductor layer. For example, when the oxide semiconductor layer is formed by an ALD method, it is preferable to perform a microwave plasma treatment every time an atomic layer is formed. Alternatively, it is preferable to perform a treatment for increasing the crystallinity every time an oxide semiconductor layer having a thickness within a predetermined range is formed, in order to increase productivity. Specifically, it is preferable to form a first oxide semiconductor layer having a thickness of 1 nm to 10 nm, perform the first microwave plasma treatment, and then form a second oxide semiconductor layer having a thickness of 1 nm to 10 nm, and perform the second microwave plasma treatment. Note that the method for forming the first oxide semiconductor layer and the second oxide semiconductor layer is not particularly limited, and ALD or sputtering can be used, respectively. In particular, forming the first oxide semiconductor layer by an ALD method is preferable because it can prevent elements of the layers constituting the formation surface from being mixed (also referred to as mixing) into the first oxide semiconductor layer and the second oxide semiconductor layer. This is particularly suitable when the element contained in the layer constituting the formation surface inhibits crystallization of the oxide semiconductor (for example, when silicon, carbon, or the like is contained). The first oxide semiconductor layer and the second oxide semiconductor layer may have different compositions. Although a stacked structure of the first oxide semiconductor layer and the second oxide semiconductor layer is illustrated here, the present invention is not limited to this. The same treatment can be applied to a single oxide semiconductor layer or a stacked structure of three or more oxide semiconductor layers.

[0281] Treatment for increasing the crystallinity of the oxide semiconductor layer may be performed after the oxide semiconductor layer is formed. Specifically, the treatment may be performed directly on the formed oxide semiconductor layer, or may be performed through another film such as an insulating film formed on the oxide semiconductor layer. For example, microwave plasma treatment may be performed after the oxide semiconductor layer is formed, or an insulating film (e.g., a silicon nitride film, a silicon oxide film, or an aluminum oxide film) may be formed after the oxide semiconductor layer is formed, and then heat treatment or microwave plasma treatment may be performed on the oxide semiconductor layer through the insulating film.

[0282] Note that the treatment for increasing the crystallinity of the oxide semiconductor layer can also serve as treatment for removing impurities contained in the oxide semiconductor layer. For example, carbon, hydrogen, nitrogen, and the like contained in the oxide semiconductor layer can be preferably removed. Alternatively, by performing the treatment for increasing the crystallinity of the oxide semiconductor layer in an oxygen gas atmosphere, oxygen vacancies in the oxide semiconductor layer can be reduced.

[0283] When the treatment for increasing the crystallinity of the oxide semiconductor layer is performed, the temperature of the substrate is preferably set to room temperature (for example, 25° C.) or higher, 100° C. or higher and 600° C. or lower, or 300° C. or higher and 450° C. The temperature of the heat treatment is preferably set to 100° C. or higher and 700° C. or lower, or 300° C. or higher and 450° C.

[0284] By performing treatment to increase the crystallinity of the oxide semiconductor layer in addition to the above-described method for forming the oxide semiconductor layer, a highly reliable transistor can be provided.

[0285] As described in the above embodiment, the metal oxide preferably contains at least indium. In particular, it is preferable that it contains indium and zinc. In addition to these, it is preferable that the element M is contained. The element M can be one or more selected from aluminum, gallium, silicon, yttrium, tin, copper, vanadium, chromium, manganese, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, calcium, strontium, barium, cobalt, and antimony. In particular, it is preferable that the element M is one or more of aluminum, gallium, yttrium, and tin. It is even more preferable that the element M contains one or both of gallium and tin.

[0286] Specifically, for example, it is preferable to use indium oxide as the metal oxide. In particular, it is preferable to use crystalline indium oxide. Details of crystalline indium oxide will be described later. Furthermore, the metal oxide may be In—Ga—Zn oxide (indium-gallium-zinc oxide), Ga—Zn oxide, or gallium oxide.

[0287] The metal oxide may have an atomic ratio of In:Ga:Zn=1:3:4, 1:3:2, 1:1:0.5, 1:1:1, 4:2:3, or 3:1:2. The metal oxide may have an atomic ratio of In:Zn=4:1.

[0288] The metal oxide can be preferably formed by sputtering or ALD. When the metal oxide is formed by sputtering, a film with high crystallinity or high film density can be formed. Furthermore, when the metal oxide is formed by ALD, atoms can be deposited layer by layer, which has the advantages of enabling film formation with fewer defects such as pinholes, film formation with excellent coverage, and film formation at low temperatures. After the metal oxide is formed, it is preferable to perform an impurity removal treatment to remove impurities (typically, impurities such as water, hydrogen, carbon, and nitrogen) from the metal oxide film. Examples of impurity removal treatments include plasma treatment, microwave treatment, and heat treatment.

[0289] <Indium Oxide> Here, indium oxide that can be used as a metal oxide for a channel formation region of the OS transistor according to one embodiment of the present invention described in the above embodiment will be described.

[0290] In this specification and the like, indium oxide having at least a crystalline portion or a crystalline region in a film is referred to as crystalline indium oxide (crystal IO) or crystalline indium oxide (crystalline IO). Examples of crystalline IO or crystalline IO include single-crystalline indium oxide, polycrystalline indium oxide, and microcrystalline indium oxide.

[0291] Indium oxide is a semiconductor material having physical properties that are completely different from those of the oxide semiconductors such as IGZO and zinc oxide described above.

[0292] The carrier concentration dependence of the Hall mobility of indium oxide, silicon, and IGZO will be explained. FIG. 16A shows the carrier concentration dependence of the Hall mobility of silicon (Si) and indium oxide (InO Ｘ ) and FIG. 16B is a schematic diagram showing the carrier concentration dependence of the hole mobility for IGZO.

[0293] First, IGZO tends to exhibit higher hole mobility as the carrier concentration increases, as shown by the arrows in Figure 16B. On the other hand, indium oxide tends to exhibit higher hole mobility as the carrier concentration decreases, as shown by the arrows in Figure 16A (see Non-Patent Document 1). This trend is similar to that of silicon; the lower the dopant (impurity) concentration in the material, the less impurity scattering there is and the higher the hole mobility. In other words, the higher the purity and intrinsic indium oxide, the higher the hole mobility. From these results, it can be said that indium oxide, unlike IGZO, is a material with physical properties similar to those of silicon. Note that the characteristics of indium oxide shown in Figure 16A are assumed to be single crystal. Therefore, when indium oxide is non-single crystal (e.g., polycrystalline), the characteristics may differ from those shown in Figure 16A.

[0294] 16A, the range R1 of low carrier concentration has extremely high hole mobility, and therefore can be said to be a range of carrier concentration suitable for the channel formation region of a transistor. For example, in the case of indium oxide, the range R1 is a range where the carrier concentration is 1×10 １５ cm −３ The range includes, for example, 1×10 １４ cm −３ That's it, 1 x 10 １８ cm −３ By sufficiently reducing the carrier concentration, the Hall mobility value can be increased to 270 cm ２ It is expected that the resistance can be increased to about / (V·s).

[0295] In addition, in indium oxide, the region where the carrier concentration is in the range R1 may contain an element that lowers the carrier concentration. Examples of elements that lower the carrier concentration include magnesium, calcium, zinc, cadmium, and copper. By substituting these elements for indium, the carrier concentration can be lowered. Examples of elements that lower the carrier concentration include nitrogen, phosphorus, arsenic, and antimony. For example, by substituting nitrogen, phosphorus, arsenic, or antimony for oxygen, the carrier concentration can be lowered.

[0296] On the other hand, the range R2 with a high carrier concentration has a low electrical resistance, and can be said to be a range of carrier concentrations suitable for, for example, the source and drain regions of a transistor, or a resistor or transparent conductive film. ２０ cm −３ The range includes, for example, 1×10 １９ cm −３ That's it, 1 x 10 ２２ cm −３ By increasing the carrier concentration sufficiently, the resistivity can be reduced to 1×10 −４ It is expected that the resistivity can be reduced to Ω·cm or less.

[0297] In the indium oxide, the region having a carrier concentration in the range R2 may contain an element that increases the carrier concentration. For example, it is preferable that the indium oxide contains an element that is common to the source electrode and the drain electrode of the transistor. Examples of elements that increase the carrier concentration include titanium, zirconium, hafnium, tantalum, tungsten, tin, silicon, and boron. In particular, it is more preferable to use an element whose oxide has conductive or semiconductive properties. In addition to the above elements, examples of the element include elements contained in a conductive layer that can be used for a source electrode or a drain electrode, which will be described later in Embodiment 4.

[0298] In this way, indium oxide uses a region with a low carrier concentration as the channel formation region of a transistor, and a region with a high carrier concentration as the source and drain regions of the transistor. In other words, indium oxide can be said to be an oxide capable of valence electron control. Note that IGZO may experience strain in the source and drain regions due to stress from electrodes in contact with the IGZO, resulting in the formation of n-type regions. On the other hand, unlike IGZO, indium oxide is capable of valence electron control, and therefore does not require strain to be formed in the film as with IGZO. Less strain in the film is expected to improve reliability. For example, by separately creating a region with a carrier concentration in the range R1 shown in FIG. 16A and a region with a carrier concentration in the range R2 in the indium oxide film, a so-called n-i-n junction (a junction between an n-type region, an i-type region, and an n-type region) can be created. Note that valence electron control in transistors using silicon is generally known. On the other hand, valence electron control in transistors using indium oxide is a novel technical concept that would not normally be conceived.

[0299] By using the above technical concept, the transistor having indium oxide in this specification and the like has two or more, preferably three or more, more preferably four or more, and most preferably five of the following characteristics (1) to (5): (1) high on-current (in other words, high mobility); (2) low off-current; (3) normally-off operation; (4) high reliability; and (5) high cutoff frequency (fT). For example, the transistor having indium oxide in this specification and the like has high mobility, low off-current, and is normally-off operation. The transistor has high mobility and is different from a normally-on transistor.

[0300] Next, an indium oxide film applied to a transistor will be described. The indium oxide film preferably has crystallinity (i.e., has crystal grains). Examples of films having crystal grains include single-crystal films, polycrystalline films, and amorphous films containing crystal grains (also called microcrystalline films). In particular, the indium oxide film is preferably a polycrystalline film, and more preferably a single-crystal film. A single-crystal film does not have grain boundaries. Impurities (typically, insulating impurities, insulating oxides, etc.) that hinder carrier flow tend to segregate at grain boundaries. The use of a single-crystal film can suppress carrier scattering at grain boundaries, thereby realizing a transistor exhibiting high field-effect mobility. Furthermore, the use of a single-crystal film has the excellent effect of suppressing variations in transistor characteristics due to the grain boundaries.

[0301] Furthermore, polycrystalline films are preferable because they can reduce carrier scattering and exhibit high field-effect mobility compared to microcrystalline or amorphous films. When using a polycrystalline film, it is preferable to use a film with as large a crystal grain size as possible and with few crystal grain boundaries. Note that in a transistor using an indium oxide polycrystalline film, if there is no crystal grain boundary in the channel formation region or no crystal grain boundary is observed, the channel formation region is located within a single crystal region included in the polycrystalline film, and therefore the transistor can be considered to be using single-crystal indium oxide.

[0302] The crystallinity of indium oxide can be analyzed by, for example, X-ray diffraction (XRD), transmission electron microscopy (TEM), or electron diffraction (ED). Alternatively, the analysis may be performed by combining a plurality of these techniques.

[0303] In this specification and the like, a semiconductor layer in which no crystal grain boundary is observed in the channel formation region, a semiconductor layer in which the channel formation region is included in one crystal grain, or a semiconductor layer in which the crystal axis direction is the same in at least two regions in the channel formation region can be called a single crystal film. Also, a semiconductor layer in which, in the channel formation region, within one crystal grain, the direction of another crystal axis continuously changes around a certain crystal axis or a certain crystal orientation as the axis of rotation can be called a single crystal film.

[0304] The channel formation region refers to a region of the semiconductor layer that overlaps (or faces) the gate electrode via the gate insulating layer, and is located between the region in contact with the source electrode and the region in contact with the drain electrode. The current path in the channel formation region is the shortest distance between the source electrode and the drain electrode. Therefore, the crystal grains, crystal grain boundaries, crystal axes, crystal orientation, etc. in the channel formation region can be confirmed by observing a cross section including the semiconductor layer, the source electrode, and the drain electrode.

[0305] The indium oxide film in the channel formation region preferably has a lower impurity concentration. Impurities in the indium oxide film in the channel formation region can be a scattering source of carriers, which can lead to a decrease in field-effect mobility. These impurities can also hinder the crystal growth of the indium oxide film. Examples of impurities in the indium oxide film include boron and silicon. The indium oxide film preferably contains these impurities at concentrations of 0.1% or less, and more preferably 0.01% (100 ppm) or less. Carbon, hydrogen, and other elements may be contained in the film-forming gas or precursor during film formation, and may remain in the indium oxide film in greater amounts than the above-mentioned impurities.

[0306] The indium oxide film in the channel formation region may contain an element that can become the same trivalent cation as indium, as long as the crystal maintains a cubic crystal structure (bixbyite type). Examples of such an element include Group 13 elements of the periodic table, such as gallium and aluminum, and Group 3 elements of the periodic table. These elements exist mainly as trivalent cations in oxides, and therefore the carrier concentration of indium oxide can be maintained low.

[0307] By using such an indium oxide film in a transistor, the field effect mobility of the transistor can be increased to 50 cm ２ / (V·s) or more, preferably 100 cm ２ / (V·s) or more, more preferably 150 cm ２ / (V·s) or more, more preferably 200 cm ２ / (V·s) or more, more preferably 250 cm ２ / (V·s) or more.

[0308] One of the features of an indium oxide film is that it has higher oxygen permeability (diffusibility) than an IGZO film. As shown in FIG. 16C, an indium oxide film (InO Ｘ Oxygen (O) diffusing into the indium oxide film passes through the indium oxide film and becomes oxygen molecules (O ２ ) and is released as water molecules (H ２ O) may be released in the film. Ｏ In the case where an indium oxide film is present, oxygen atoms diffuse to compensate for the oxygen vacancies. Since oxygen diffuses easily in the indium oxide film, it can be said that oxygen vacancies are more easily compensated for in the indium oxide film than in the IGZO film.

[0309] As described above, an indium oxide film can more easily reduce oxygen vacancies in the film than an IGZO film. Therefore, by using such an indium oxide film in a transistor, a transistor exhibiting extremely high reliability can be realized.

[0310] 16C, the indium oxide film diffuses hydrogen. Hydrogen that diffuses into the indium oxide film from the outside passes through the indium oxide film and becomes hydrogen molecules (H ２ ) or reacts with the oxygen contained in the film and is released as water molecules.

[0311] A transistor using an indium oxide film is an accumulation-type transistor that uses electrons as majority carriers. Assuming that the carrier relaxation time is constant, the smaller the effective mass of the electrons (carriers), the higher the electron mobility. In other words, by using indium oxide, which has a small effective mass of electrons, for a transistor, the on-state current or field-effect mobility of the transistor can be increased.

[0312] The table below shows the properties of single crystal indium oxide (here, In ２ O ３ ) and single-crystal silicon (Si). As shown in the table below, indium oxide is characterized by a small effective mass of electrons and a large effective mass of holes. Indium oxide also has the characteristic that the effective mass of electrons is almost independent of the crystal orientation. Therefore, by using crystalline indium oxide in a transistor, a transistor with high field-effect mobility and high frequency characteristics (also called f characteristics) can be realized. Furthermore, because the effective mass of holes is large, a transistor with extremely small off-current can be realized. For example, by applying an indium oxide film to a vertical transistor, the off-current per 1 μm of channel width can be reduced to 1 fA (1×10) in an environment of 125° C. −１５ A) or less, or 1aA (1 x 10 −１８ A) or less, and under room temperature (25°C) conditions, −１８ A) or less, or 1zA (1 x 10 −２１ Furthermore, as shown in the table below, indium oxide has a smaller effective mass of electrons and a larger effective mass of holes than silicon, and therefore may be able to realize a transistor with higher field-effect mobility and lower off-state current than a Si transistor.

[0313]

[0314] It is preferable to provide a seed layer so as to be in contact with at least a portion of the crystalline indium oxide film. The seed layer is preferably made of a material containing crystals with a small difference in lattice constant (also called lattice mismatch) with indium oxide. This can improve the crystallinity of the indium oxide film. Note that a substrate (e.g., a single-crystal substrate) may be used as one of the layers in contact with at least a portion of the crystalline indium oxide film.

[0315] One method for evaluating the degree of lattice mismatch is to use the value of the lattice mismatch shown below. The lattice mismatch Δa [%] of the crystals of the formed film (here, the indium oxide film) with respect to the crystals of the seed layer is expressed as Δa = ((L １ -L ２ ) / L ２ ) × 100, where L １ is the length or lattice constant of the unit lattice vector of the crystal of the formed film, and L ２ is the length of the unit lattice vector or the lattice constant of the crystal of the seed layer.

[0316] The smaller the absolute value of the lattice mismatch Δa between the seed layer and the indium oxide film, the more preferable, and it is most preferably 0. For example, Δa can be set to −5% or more and 5% or less, preferably −4% or more and 4% or less, more preferably −3% or more and 3% or less, and even more preferably −2% or more and 2% or less.

[0317] Here, the indium oxide crystal has a cubic crystal structure (bixbyite type). For example, the crystal of yttria-stabilized zirconia (YSZ) can have a cubic crystal structure (fluorite type). The lattice mismatch of the indium oxide crystal with the cubic YSZ crystal is in the range of −2% to 2%, and a single crystal film of indium oxide can be epitaxially grown on the YSZ substrate.

[0318] It should be noted that the crystal structure of the seed layer and the crystal structure of the indium oxide film may not necessarily have the same crystal system or crystal orientation. For example, a film having crystals of a hexagonal or trigonal structure may be used under an indium oxide film having crystals of a cubic structure. For example, by setting the crystal orientation of the surface of the seed layer to

[001] and the crystal orientation of the underside of the indium oxide film to

[111] , the requirements related to the crystal orientation necessary for epitaxial growth can be satisfied. Examples of hexagonal or trigonal crystals include wurtzite structure, YbFe ２ O ４ Type structure, Yb ２ Fe ３ O ７ YbFeFe alloys have the following structures: ２ O ４ Type structure or Yb ２ Fe ３ O ７ An example of a crystal having a ZnO-type structure is IGZO.

[0319] Note that this embodiment mode can be appropriately combined with the same or other embodiment modes described in this specification. For example, the configurations, structures, methods, and the like described in this embodiment mode can be appropriately combined and used with the configurations, structures, methods, and the like described in the other embodiment modes. For example, the configurations, structures, methods, and the like described in this embodiment mode can be appropriately combined and used with the configurations, structures, methods, and the like described in the other embodiment modes.

[0320] Embodiment Mode 3 In this embodiment mode, a configuration example that can be applied to the pixel circuit PX included in the display device described in Embodiment Mode 1 will be described.

[0321] <Configuration Example 1 of Pixel Circuit> FIG. 17A is a circuit diagram showing a configuration example of a circuit that can be applied to the pixel circuit PX of the display device DSP described in the first embodiment.

[0322] The pixel circuit PX1 shown in FIG. 17A includes, for example, a transistor Tr1, a transistor Tr2, a capacitance element Cs1, a capacitance element Cs2, and a light-emitting device ED.

[0323] Examples of the light-emitting device ED include a light-emitting device containing an organic EL material, a light-emitting device containing an inorganic EL material, and a light-emitting diode (e.g., a micro LED). The pixel circuit PX1 can be a pixel circuit to which one or more of the above-mentioned light-emitting devices ED are applied. In this embodiment, the pixel circuit PX of the pixel array PXA is described as being applied with a light-emitting device containing an organic EL material. The brightness of light emitted from a light-emitting device capable of emitting particularly high brightness light is, for example, 500 cd / m ２ More than 1000 cd / m is preferable. ２ More than 10000cd / m ２ More preferably, 2000 cd / m or less ２ More than 5000cd / m ２ The following is even more preferred:

[0324] The first terminal of transistor Tr1 is connected to wiring SL, the second terminal of transistor Tr1 is connected to the gate of transistor Tr2 and the first terminal of capacitor Cs1, and the gate of transistor Tr1 is connected to wiring GL. The first terminal of transistor Tr2 is connected to wiring IL, and the second terminal of transistor Tr2 is connected to the second terminal of capacitor Cs1, the first terminal of capacitor Cs2, and the anode of light-emitting device ED. The second terminal of capacitor Cs2 is connected to wiring VCOM. The cathode of light-emitting device ED is connected to wiring VCAT.

[0325] As an example, the wiring SL shown in Figure 17A is a wiring corresponding to any one of the wirings SL[1] to SL[N] shown in Figure 2 or the wiring SLS[j] shown in Figure 12, and functions as a wiring for transmitting an image signal from the driver circuit SD shown in Figure 12 to the pixel circuit PX[i, j].

[0326] Furthermore, the wiring GL shown in Figure 17A is, as an example, a wiring corresponding to the wiring GLS[i] shown in Figure 12, and functions as a wiring for transmitting a selection signal or a non-selection signal from the driver circuit GD shown in Figure 12 to the pixel circuit PX[i, j].

[0327] The wiring IL functions as a wiring for supplying a current to the anode of the light emitting device ED, and is therefore sometimes called a current supply line.

[0328] The wiring VCOM functions as a wiring that applies a fixed potential to the second terminal of the capacitance element Cs2. In particular, this fixed potential may be called a common potential. As an example, the common potential may be a low-level potential, a ground potential, or a negative potential. The wiring VCOM may also be a wiring that applies a common potential to the second terminal of the capacitance element Cs2 provided in another pixel circuit PX1 within the same pixel array PXA.

[0329] The wiring VCAT functions as a wiring that applies a fixed potential to the cathode of the light-emitting device ED. In particular, this fixed potential may be called a cathode potential. The cathode potential may be, for example, a low-level potential, a ground potential, or a negative potential. The wiring VCAT may also be a wiring that applies a cathode potential to the cathode of a light-emitting device ED provided in another pixel circuit PX1 within the same pixel array PXA.

[0330] The common potential provided by the wiring VCOM and the cathode potential provided by the wiring VCAT may be equal to each other. In this case, the wiring VCOM and the wiring VCAT may be the same wiring (not shown).

[0331] The transistor Tr1 functions as a writing transistor for an image signal in the pixel circuit PX. Therefore, when the frame frequency of the display device DSP is to be increased, a transistor with a high driving frequency is preferably used as the transistor Tr1. Furthermore, since the transistor Tr1 is a writing transistor that holds an image signal as a potential, a transistor with a low off-state current is preferably used as the transistor Tr1. Specifically, for example, the transistor Tr1 is preferably an OS transistor. In particular, the transistor Tr1 preferably contains indium oxide, which is the oxide semiconductor described in Embodiment 2, in a channel formation region.

[0332] The transistor Tr2 also functions as a drive transistor for controlling the amount of current flowing between the anode and cathode of the light-emitting device ED in the pixel circuit PX. Therefore, when the potential corresponding to the image signal is high, it is preferable to use a transistor with high voltage resistance for the transistor Tr2. Furthermore, when the light-emitting device ED is a light-emitting device containing an organic EL material, the luminance of the light-emitting device ED is proportional to the current flowing between the anode and cathode of the light-emitting device. Therefore, to increase the luminance of the light-emitting device ED, it is preferable to use a transistor with high on-state characteristics for the transistor Tr2. For example, the transistor Tr2 is preferably an OS transistor. In particular, it is preferable that the transistor Tr2 contains indium oxide, which is the oxide semiconductor described in Embodiment 2, in its channel formation region.

[0333] <Pixel Circuit Configuration Example 2> FIG. 17B is a circuit diagram showing a circuit configuration example that can be applied to the pixel circuit PX[i, j] of the display device DSP described in the first embodiment and that is different from the pixel circuit of FIG. 17A.

[0334] The pixel circuit PX2 shown in FIG. 17B includes, for example, a transistor Tr1, a transistor Tr2, a transistor Tr3, a transistor Tr4, a capacitance element Cs1, a capacitance element Cs3, and a light-emitting device ED.

[0335] For the transistor Tr1, the transistor Tr2, the capacitance element Cs1, and the light-emitting device ED, the description of the transistor Tr1, the transistor Tr2, the capacitance element Cs1, and the light-emitting device ED included in the pixel circuit PX1 can be referred to.

[0336] The pixel circuit PX2 not only emits light with an intensity corresponding to an input image signal, but also has the function of correcting the threshold voltage of the transistor Tr2, which is a drive transistor.

[0337] The first terminal of transistor Tr1 is connected to wiring SL, the second terminal of transistor Tr1 is connected to the gate of transistor Tr2 and the first terminal of capacitor Cs1, and the gate of transistor Tr1 is connected to wiring GL1. The first terminal of transistor Tr2 is connected to the first terminal of transistor Tr3, and the second terminal of transistor Tr2 is connected to the second terminal of capacitor Cs1, the first terminal of capacitor Cs3, the first terminal of transistor Tr4, and the anode of light-emitting device ED. The second terminal of transistor Tr3 is connected to wiring VEL, and the gate of transistor Tr3 is connected to wiring GL2. The second terminal of capacitor Cs3 is connected to wiring VEL. The second terminal of transistor Tr4 is connected to wiring INIL, and the gate of transistor Tr4 is connected to wiring GL3. The cathode of light-emitting device ED is connected to wiring VCAT.

[0338] For the wiring SL and the wiring VCAT, the description of the wiring SL and the wiring VCAT connected to the pixel circuit PX1 in FIG. 17A can be referred to.

[0339] For the wiring GL1, the description of the wiring GL connected to the pixel circuit PX1 in FIG. 17A can be referred to.

[0340] For example, the wiring GL2 functions as a wiring for transmitting a selection signal for turning on the transistor Tr3 or a non-selection signal for turning off the transistor Tr3.

[0341] For example, the wiring GL3 functions as a wiring for transmitting a selection signal for turning on the transistor Tr4 or a non-selection signal for turning off the transistor Tr4.

[0342] 17B correspond to the wiring GLS[i] shown in Fig. 12. In this case, the wiring GLS[i] in Fig. 12 is a wiring group.

[0343] For example, the wiring VEL functions as a wiring for applying a potential to the anode of the light-emitting device ED. The potential can be the anode potential of the light-emitting device ED.

[0344] The wiring INIL functions as a wiring for applying a potential to the anode of the light-emitting device ED. In particular, the potential can be, for example, an initialization potential for resetting the anode potential of the light-emitting device ED.

[0345] The transistors Tr3 and Tr4 preferably have high voltage tolerance. Furthermore, the transistors Tr3 and Tr4 preferably have high on-state characteristics. For example, the transistors Tr3 and Tr4 are preferably OS transistors. In particular, the transistors Tr3 and Tr4 preferably contain indium oxide, which is the oxide semiconductor described in Embodiment 2, in their channel formation regions.

[0346] 18A , the pixel circuit PX2 may have a configuration in which the back gate of the transistor Tr1 is connected to the gate of the transistor Tr1 and the back gate of the transistor Tr2 is connected to the second terminal of the transistor Tr2.

[0347] <Pixel circuit configuration example 3> Figure 17C is a circuit diagram showing an example of a circuit configuration that can be applied to the pixel circuit PX[i, j] of the display device DSP of Figure 12 described in embodiment 1, and is different from the pixel circuits of Figures 17A and 17B.

[0348] The pixel circuit PX3 shown in FIG. 17C includes, as an example, a transistor Tr1, a transistor Tr2, a transistor Tr4, a transistor Tr5, a capacitance element Cs1, and a light-emitting device ED.

[0349] For the transistors Tr1, Tr2, Tr4, the capacitance element Cs1, and the light-emitting device ED, the description of the transistors Tr1, Tr2, Tr4, the capacitance element Cs1, and the light-emitting device ED included in the pixel circuit PX2 above can be referred to.

[0350] Like the pixel circuit PX2, the pixel circuit PX3 not only emits light with an intensity corresponding to an input image signal, but also has the function of correcting the threshold voltage of the transistor Tr2, which is a drive transistor.

[0351] The first terminal of transistor Tr1 is connected to wiring SL, the second terminal of transistor Tr1 is connected to the gate of transistor Tr2, the first terminal of transistor Tr5, and the first terminal of capacitor Cs1, and the gate of transistor Tr1 is connected to wiring GL1. The first terminal of transistor Tr2 is connected to wiring VEL, and the second terminal of transistor Tr2 is connected to the second terminal of capacitor Cs1, the first terminal of transistor Tr4, and the anode of light-emitting device ED. The second terminal of transistor Tr5 is connected to wiring VBL, and the gate of transistor Tr5 is connected to wiring GL4. The second terminal of transistor Tr4 is connected to wiring INIL, and the gate of transistor Tr4 is connected to wiring GL3. The cathode of light-emitting device ED is connected to wiring VCAT.

[0352] For the wiring SL, the wiring VCAT, the wiring VEL, and the wiring INIL, the description of the wiring SL, the wiring VCAT, the wiring VEL, and the wiring INIL connected to the pixel circuit PX2 in Fig. 17B can be referred to. For the wiring GL1, the description of the wiring GL1 connected to the pixel circuit PX1 in Fig. 17A can be referred to. For the wiring GL3, the description of the wiring GL3 connected to the pixel circuit PX2 in Fig. 17B can be referred to.

[0353] For example, the wiring GL4 functions as a wiring for transmitting a selection signal for turning on the transistor Tr5 or a non-selection signal for turning off the transistor Tr5.

[0354] The wiring VBL functions as a wiring for applying a fixed potential to the first terminal of the capacitor Cs1. The fixed potential is, for example, a potential input to the gate of the transistor Tr2 when correcting the threshold voltage of the transistor Tr2, and is preferably equal to the potential applied by the wiring VEL.

[0355] The transistor Tr5 preferably has high voltage tolerance. Furthermore, the transistor Tr5 preferably has excellent on-state characteristics. For example, the transistor Tr5 is preferably an OS transistor. In particular, the transistor Tr5 preferably contains indium oxide, which is the oxide semiconductor described in Embodiment 2, in a channel formation region.

[0356] <Pixel Circuit Configuration Example 4> Figure 17D is a circuit diagram showing a circuit configuration example that can be applied to the pixel circuit PX[i, j] of the display device DSP of Figure 12 described in embodiment 1 and is different from the pixel circuits of Figures 17A to 17C.

[0357] The pixel circuit PX4 shown in FIG. 17D includes, as an example, a transistor Tr1, a transistor Tr2, a transistor Tr4, a capacitive element Cs1, and a light-emitting device ED.

[0358] For the transistors Tr1, Tr2, Tr4, the capacitance element Cs1, and the light-emitting device ED, the description of the transistors Tr1, Tr2, Tr4, the capacitance element Cs1, and the light-emitting device ED included in the pixel circuit PX3 above can be referred to.

[0359] Like the pixel circuit PX1, the pixel circuit PX4 also has the function of emitting light with a luminous intensity according to an input image signal.

[0360] The first terminal of transistor Tr1 is connected to wiring SL, the second terminal of transistor Tr1 is connected to the gate of transistor Tr2 and the first terminal of capacitor Cs1, and the gate of transistor Tr1 is connected to wiring GL1. The first terminal of transistor Tr2 is connected to wiring VEL, and the second terminal of transistor Tr2 is connected to the second terminal of capacitor Cs1, the first terminal of transistor Tr4, and the anode of light-emitting device ED. The second terminal of transistor Tr4 is connected to wiring INIL, and the gate of transistor Tr4 is connected to wiring GL3. The cathode of light-emitting device ED is connected to wiring VCAT.

[0361] For the wiring SL, the description of the wiring SL connected to the pixel circuit PX3 in FIG. 17C can be referred to. For the wiring VCAT, the description of the wiring VCAT connected to the pixel circuit PX3 in FIG. 17C can be referred to. For the wiring INIL, the description of the wiring INIL connected to the pixel circuit PX3 in FIG. 17C can be referred to. For the wiring GL1 and the wiring GL3, the description of the wiring GL1 and the wiring GL3 connected to the pixel circuit PX3 in FIG. 17C can be referred to.

[0362] In the pixel circuit PX4, the transistor Tr2 may be a transistor having a back gate. Specifically, as shown in FIG. 18B , the pixel circuit PX4 may be configured such that the back gate of the transistor Tr2 is connected to the second terminal of the transistor Tr2.

[0363] <Pixel Circuit Configuration Example 5> Figure 19A is a circuit diagram showing a circuit configuration example that can be applied to the pixel circuit PX[i, j] of the display device DSP of Figure 12 described in embodiment 1 and is different from the pixel circuits of Figures 17A to 17D.

[0364] The pixel circuit PX5 shown in FIG. 19A includes, for example, transistors Tr1 to Tr4, a transistor Tr6, a transistor Tr7, a capacitor Cs1, and a light-emitting device ED.

[0365] Note that for the transistors Tr1 to Tr4, the capacitor Cs1, and the light-emitting device ED, the descriptions of the transistors Tr1 to Tr4, the capacitor Cs1, and the light-emitting device ED included in the pixel circuit PX2 can be referred to.

[0366] Like the pixel circuits PX2 and PX3, the pixel circuit PX5 not only emits light with an intensity corresponding to the input image signal, but also has the function of correcting the threshold voltage of the transistor Tr2, which is a drive transistor.

[0367] The first terminal of transistor Tr1 is connected to wiring SL, the second terminal of transistor Tr1 is connected to the first terminal of transistor Tr2 and the first terminal of transistor Tr7, and the gate of transistor Tr1 is connected to wiring GL1. The second terminal of transistor Tr2 is connected to the first terminal of transistor Tr3 and the first terminal of transistor Tr6, and the gate of transistor Tr2 is connected to the second terminal of transistor Tr6 and the first terminal of capacitor Cs1. The second terminal of transistor Tr3 is connected to wiring VEL, and the gate of transistor Tr3 is connected to wiring GL2. The gate of transistor Tr6 is connected to the gate of transistor Tr4 and wiring GL3. The second terminal of transistor Tr7 is connected to the first terminal of transistor Tr4, the second terminal of capacitor Cs1, and the anode of light-emitting device ED. The second terminal of transistor Tr4 is connected to wiring INIL. The cathode of the light emitting device ED is connected to the wiring VCAT.

[0368] For the wiring SL, the description of the wiring SL connected to the pixel circuit PX2 in FIG. 17B can be referred to. For the wiring VCAT, the description of the wiring VCAT connected to the pixel circuit PX2 in FIG. 17B can be referred to. For the wiring INIL, the description of the wiring INIL connected to the pixel circuit PX2 in FIG. 17B can be referred to. For the wiring VEL, the description of the wiring VEL connected to the pixel circuit PX2 in FIG. 17B can be referred to. For the wirings GL1 to GL3, the description of the wirings GL1 to GL3 connected to the pixel circuit PX2 in FIG. 17B can be referred to.

[0369] For example, the wiring GL5 functions as a wiring for transmitting a selection signal for turning on the transistor Tr7 or a non-selection signal for turning off the transistor Tr7.

[0370] The transistors Tr6 and Tr7 preferably have high voltage tolerance. Furthermore, the transistors Tr6 and Tr7 preferably have high on-state characteristics. For example, the transistors Tr6 and Tr7 are preferably OS transistors. In particular, the transistors Tr6 and Tr7 preferably contain indium oxide, which is the oxide semiconductor described in Embodiment 2, in their channel formation regions.

[0371] Note that the pixel circuit of the semiconductor device of one embodiment of the present invention is not limited to the configuration of the pixel circuit PX5 illustrated in FIG. 19A, and the circuit configuration of the pixel circuit PX5 may be changed as appropriate.

[0372] For example, as shown in a pixel circuit PX5A in Fig. 19B, a capacitance element Cs4 may be provided in the pixel circuit PX5 in Fig. 19A. A first terminal of the capacitance element Cs4 is connected to the gate of the transistor Tr1 and the wiring GL1, and a second terminal of the capacitance element Cs4 is connected to the first terminal of the transistor Tr4, the second terminal of the transistor Tr7, the second terminal of the capacitance element Cs1, and the anode of the light-emitting device ED.

[0373] 20 , the pixel circuit PX5A may have a configuration in which the back gate of the transistor Tr1 is connected to the gate of the transistor Tr1, the back gate of the transistor Tr2 is connected to the second terminal of the transistor Tr2, and the back gate of the transistor Tr6 is connected to the gate of the transistor Tr6.

[0374] Note that this embodiment mode can be appropriately combined with the same or other embodiment modes described in this specification. For example, the configurations, structures, methods, and the like described in this embodiment mode can be appropriately combined and used with the configurations, structures, methods, and the like described in the other embodiment modes. For example, the configurations, structures, methods, and the like described in this embodiment mode can be appropriately combined and used with the configurations, structures, methods, and the like described in the other embodiment modes.

[0375] Embodiment Mode 4 In this embodiment mode, an example of a cross-sectional structure of the display device described in the above embodiment mode will be described.

[0376] FIG. 21A is a schematic perspective view illustrating a display device according to one embodiment of the present invention. For example, the display device DSP1 includes a display region DIS, a driver circuit region DRV, and a terminal region TMR. The display device DSP1 also includes a substrate BS, and the display region DIS, the driver circuit region DRV, and the terminal region TMR are located on the substrate BS. The display region DIS may include, for example, the pixel array PXA shown in FIG. 12 and described in Embodiment 1. The driver circuit SD described in Embodiment 1 may be provided outside the display device DSP1 shown in FIG. 21A.

[0377] The drive circuit region DRV includes, for example, a drive circuit GD1, a drive circuit GD2, and a drive circuit SD. The drive circuits GD1 and GD2 correspond to the drive circuit GD of the display device DSP in FIG. 12 described in the first embodiment, and the drive circuit SD corresponds to the drive circuit SD of the display device DSP in FIG. 12 described in the first embodiment.

[0378] The substrate BS can be, for example, a semiconductor substrate (e.g., a single-crystal substrate made of silicon or germanium). In addition to semiconductor substrates, other materials that can be used for the substrate BS include, for example, an SOI (Silicon-On-Insulator) substrate, a glass substrate, a quartz substrate, a plastic substrate, a sapphire glass substrate, a metal substrate, a stainless steel substrate, a substrate having stainless steel foil, a tungsten substrate, a substrate having tungsten foil, a flexible substrate, a laminated film, and a paper or base film containing a fibrous material. Examples of glass substrates include barium borosilicate glass, aluminoborosilicate glass, and soda-lime glass. Examples of flexible substrates, laminated films, and base films include plastics such as polyethylene terephthalate (PET), polyethylene naphthalate (PEN), polyethersulfone (PES), and polytetrafluoroethylene (PTFE). Another example is a synthetic resin such as an acrylic resin. Other examples include polypropylene, polyester, polyvinyl fluoride, and polyvinyl chloride. Other examples include polyamide, polyimide, aramid, epoxy resin, inorganic vapor deposition film, and paper. If the manufacturing process of the display device DSP1 includes a heat treatment, it is preferable to use a material with high heat resistance for the substrate BS.

[0379] For example, when the substrate BS is a semiconductor substrate made of silicon, the transistors included in the display region DIS and the drive circuit region DRV can be formed as Si transistors on the substrate BS.

[0380] Further, for example, when the substrate BS is a glass substrate, the transistors included in the display region DIS and the driver circuit region DRV can be formed as OS transistors over the substrate BS.

[0381] One or more of the drive circuits GD1, GD2, and SD included in the drive circuit region DRV may be mounted on the substrate BS as an IC (Integrated Circuit) chip using COG (Chip On Glass) technology.

[0382] The drive circuits GD1 and GD2 each function as a drive circuit for displaying an image in the display area DIS. Specifically, the drive circuits GD1 and GD2 each function as a gate driver circuit for the display area DIS. The drive circuit SD also functions as a source driver circuit for the display area DIS.

[0383] The terminal region TMR includes terminals for supplying image signals and power supply potentials from the outside of the display device DSP1 to the inside of the display device DSP1. A flexible printed circuit (FPC) may be connected to the terminal region TMR. An IC chip may be mounted on the FPC using chip-on-film (COF) technology. The IC chip may include, for example, a drive circuit for displaying an image in the display region DIS.

[0384] The display area DIS has, for example, a plurality of pixels, which may be arranged in a matrix in the display area DIS.

[0385] Furthermore, the multiple pixels may be pixel circuits that use one or more of a liquid crystal display device, a light-emitting device including an organic EL material, a light-emitting device including an inorganic EL material, and a light-emitting device including a light-emitting diode such as a micro LED.

[0386] Furthermore, each of the multiple pixels can express one or multiple colors. In particular, the multiple colors can be, for example, three colors: red, green, and blue. Alternatively, the multiple colors can be, for example, red, green, and blue, plus two or more colors selected from cyan, magenta, yellow, and white. Note that each pixel expressing a different color is referred to as a sub-pixel, and when white is expressed by multiple sub-pixels of different colors, the multiple sub-pixels are sometimes collectively referred to as a pixel. For convenience, in this specification, sub-pixels will be referred to as pixels.

[0387] Note that the display device of one embodiment of the present invention is not limited to the configuration of the display device DSP1 illustrated in Fig. 21A. For example, the display device of one embodiment of the present invention may have the configuration of the display device DSP2 illustrated in Fig. 21B.

[0388] 21B shows an example of a display device DSP2 that includes a display area DIS, a circuit area SIC, and a terminal area TMR. The display device DSP2 also includes a substrate BS, similar to the display device DSP1. The display device DSP2 differs from the display area DSP1 in that the circuit area SIC and the terminal area TMR are provided on the substrate BS, and the display area DIS is provided on the circuit area SIC.

[0389] The circuit region SIC includes, as an example, the drive circuit region DRV described above. The circuit region SIC may also include various functional circuits other than the drive circuit region DRV. In this embodiment, the functional circuits are included in the functional circuit region MFNC. For example, the drive circuit SD described in the first embodiment can be included in the functional circuit region MFNC.

[0390] Furthermore, for example, the functional circuit area MFNC may include a GPU (Graphics Processing Unit). Furthermore, if the display device DSP2 includes a touch panel, the functional circuit area MFNC may include a sensor controller that controls a touch sensor included in the touch panel.

[0391] Furthermore, when a light-emitting device using an organic EL material is used as a display element of the display device DSP2, the functional circuit region MFNC may include a correction circuit. The correction circuit, for example, has the function of appropriately adjusting the amount of current input to the light-emitting device containing the organic EL material. Because the brightness of a light-emitting device containing an organic EL material when emitting light is proportional to the current, poor characteristics of the drive transistor connected to the light-emitting device may result in the brightness of the light emitted by the light-emitting device being lower than desired. The correction circuit, for example, monitors the amount of current flowing through the light-emitting device, and when the amount of current is smaller than desired, increases the amount of current flowing through the light-emitting device to increase the brightness of the light emitted by the light-emitting device. Conversely, when the amount of current is larger than desired, the correction circuit may decrease the amount of current flowing through the light-emitting device.

[0392] Furthermore, when a liquid crystal element is used as the display element of the display device DSP2, the functional circuit area MFNC may include a gamma correction circuit.

[0393] Fig. 22 is a block diagram showing an example of the configuration of the display device DSP2 shown in Fig. 21B. The display device DSP2 shown in Fig. 22 has, as an example, a display area DIS and a circuit area SIC. Although Fig. 22 shows a sensor PDA, the sensor PDA may be arranged inside or outside the display device DSP2.

[0394] 21A may be connected to a functional circuit region MFNC located outside the display device DSP1 via a terminal region TMR. In this case, the configuration of the display device DSP1 can be considered to be the same as the configuration of the display device DSP2 shown in FIG.

[0395] In FIG. 22, thick solid lines indicate multiple wires or bus wires.

[0396] 22, as an example, a plurality of pixel circuits PX are arranged in a matrix in the display region DIS. The pixel circuits PX arranged in a matrix can be considered to be included in the pixel array PXA of FIG. 12 described in the first embodiment.

[0397] In addition, in FIG. 22, the circuit region SIC has a drive circuit region DRV and a functional circuit region MFNC, as described above.

[0398] The drive circuit region DRV functions as a peripheral circuit for driving the display region DIS, for example. Specifically, the drive circuit region DRV includes, for example, a drive circuit SD and a drive circuit GD. The drive circuit SD corresponds to, for example, the drive circuit SD shown in FIG. 2 or 12 described in the first embodiment, and the drive circuit GD corresponds to, for example, the drive circuit GD shown in FIG. 12 described in the first embodiment.

[0399] The functional circuit area MFNC may be provided with circuits such as a memory device that stores image data to be displayed in the display area DIS, a decoder that restores encoded image data, a GPU that processes image data, a power supply circuit, a correction circuit, or a CPU. In Fig. 22, the functional circuit area MFNC includes, as an example, a memory device MEM, a GPU 22, a correction circuit ECR, a timing controller TMC, a CPU 21, a sensor controller SCC, and a power supply circuit EPS.

[0400] Furthermore, the display device DSP2 in FIG. 22 is configured such that, as an example, bus lines BSL are connected to the circuits included in the drive circuit region DRV and the circuits included in the functional circuit region MFNC.

[0401] The drive circuit SD has a function of transmitting image data to the pixel circuits PX included in the display area DIS, for example, and is therefore connected to the pixel circuits PX via wirings SL.

[0402] The drive circuit SD may include a digital-to-analog conversion circuit. The digital-to-analog conversion circuit has a function of converting image data digitally processed by a GPU or a correction circuit (described later) into analog data. The image data converted into analog data is transmitted to the display area DIS via the drive circuit SD. The digital-to-analog conversion circuit may be disposed outside the drive circuit SD.

[0403] For example, the driving circuit GD has a function of selecting a pixel circuit PX in the display area DIS to which image data is to be sent, and is therefore connected to the pixel circuit PX via a wiring GL.

[0404] The drive circuit SD may include a level shifter. For example, the level shifter has a function of converting a selection signal to a pixel circuit in the display area DIS to an appropriate level. The level shifter may also have a function of converting signals input to the drive circuit SD, digital-to-analog conversion circuit, drive circuit GD, etc. to an appropriate level.

[0405] The memory device MEM has a function of storing image data to be displayed in the display area DIS, for example. The memory device MEM can be configured to store image data as digital data or analog data.

[0406] Furthermore, when image data is stored in the memory device MEM, it is preferable that the memory device MEM is a nonvolatile memory. In this case, for example, a NAND type memory or the like can be used as the memory device MEM.

[0407] Furthermore, when temporary data generated by the GPU 22, the correction circuit ECR, the CPU 21, etc. is stored in the memory device MEM, it is preferable to use a volatile memory as the memory device MEM. In this case, for example, an SRAM (Static Random Access Memory), a DRAM (Dynamic Random Access Memory), etc. can be used as the memory device MEM.

[0408] The GPU 22 has a function of, for example, performing processing to render image data read from the memory device MEM in the display area DIS. In particular, the GPU 22 is configured to perform parallel pipeline processing, so that the image data to be displayed in the display area DIS can be processed at high speed. The GPU 22 can also function as a decoder to restore encoded images.

[0409] The functional circuit region MFNC may also include multiple circuits capable of improving the display quality of the display region DIS. For example, such circuits may include a correction circuit (a circuit for correcting color or dimming) that detects color unevenness in an image displayed in the display region DIS and corrects the color unevenness to produce an optimal image. Furthermore, if a light-emitting device using an organic EL material is applied to the pixels of the display region DIS, the functional circuit region MFNC may also include an EL correction circuit. In this embodiment, the pixel circuits PX of the display region DIS are described as being applied with light-emitting devices containing an organic EL material, and therefore, the functional circuit region MFNC includes, as an example, a correction circuit ECR as an EL correction circuit.

[0410] Furthermore, artificial intelligence may be used for the image correction described above. For example, the current flowing through a display device (or the voltage applied to the display device) provided in the pixel may be monitored and acquired, the image displayed in the display area DIS may be acquired by an image sensor or the like, the current (or voltage) and the image may be treated as input data for an artificial intelligence calculation (for example, an artificial neural network), and the output result may be used to determine whether or not to correct the image.

[0411] Furthermore, the calculations of the artificial intelligence can be applied not only to image correction but also to up-conversion processing of image data. As a result, by up-converting image data with a low screen resolution to match the screen resolution of the display area DIS, it is possible to display an image with high display quality in the display area DIS. Furthermore, the calculations of the artificial intelligence can also be applied to down-conversion processing of image data.

[0412] The above-mentioned artificial intelligence calculations can be performed using the GPU 22 included in the functional circuit area MFNC. That is, various correction calculations (correction of color unevenness, up-conversion processing, etc.) can be performed using the GPU 22. The GPU 22 may also include a circuit 22a that corrects color unevenness and a circuit 22b that performs up-conversion processing.

[0413] In this specification, a GPU that performs calculations for artificial intelligence is referred to as an AI accelerator. That is, in this specification, a GPU provided in the functional circuit area MFNC may be described as an AI accelerator.

[0414] As an example, the timing controller TMC has a function of varying the frame rate at which images are displayed in the display area DIS. For example, when a still image is displayed in the display area DIS, the display device DSP2 can be driven by the timing controller TMC at a lower frame rate. Also, when a moving image is displayed in the display area DIS, the display device DSP2 can be driven by the timing controller TMC at an increased frame rate. In other words, by providing the timing controller TMC in the display device DSP2, the frame rate can be changed depending on whether a still image or a moving image is displayed. In particular, when a still image is displayed in the display area DIS, the display device DSP2 can be operated at a lower frame rate, thereby reducing the power consumption of the display device DSP2.

[0415] The CPU 21 has a function of performing general-purpose processing, such as executing an operating system, controlling data, and executing various calculations and programs. In the display device DSP2, the CPU 21 has a role of issuing commands such as writing or reading image data to or from the memory device MEM, correcting image data, or operating a sensor (described later). The CPU 21 may also have a function of transmitting control signals to one or more circuits selected from the circuits included in the functional circuit area MFNC, such as the memory device, GPU, correction circuit, timing controller, and high-frequency circuit.

[0416] The CPU 21 may also include a circuit (hereinafter referred to as a backup circuit) that temporarily backs up data. It is preferable that the backup circuit be able to retain the data even if the supply of power supply potential is stopped. For example, when a still image is displayed in the display area DIS, the CPU 21 can suspend its function until an image different from the current still image is displayed. Therefore, by temporarily saving data being processed by the CPU 21 to the backup circuit and then stopping the supply of power supply potential to the CPU 21, the dynamic power consumption of the CPU 21 can be reduced. In this specification, a CPU having a backup circuit is referred to as a NoffCPU (registered trademark).

[0417] The sensor controller SCC has a function of controlling the sensor PDA, for example. Also, in Fig. 22, a line SNCL is shown as a line for connecting the sensor PDA and the sensor controller SCC.

[0418] Furthermore, the sensor PDA can be, for example, an illuminance sensor. In particular, by acquiring the intensity of external light illuminating the display area DIS using the illuminance sensor, the brightness (luminance) of the image displayed in the display area DIS can be changed according to the external light. For example, when the external light is bright, the luminance of the image displayed in the display area DIS can be increased to improve the visibility of the image. Conversely, when the external light is dark, the luminance of the image displayed in the display area DIS can be decreased to reduce power consumption.

[0419] Alternatively, the sensor PDA may be, for example, an image sensor. For example, by acquiring an image or the like using the image sensor, the image can be displayed in the display area DIS.

[0420] For example, the power supply circuit EPS has a function of generating voltages to be supplied to circuits included in the drive circuit region DRV, circuits included in the functional circuit region MFNC, pixels included in the display region DIS, etc. The power supply circuit EPS may also have a function of selecting the circuit to which to supply voltage. For example, during a period in which a still image is displayed in the display region DIS, the power supply circuit EPS can reduce the power consumption of the entire display device DSP by stopping the supply of voltage to each circuit included in the drive circuit region DRV (e.g., the drive circuit SD, the digital-to-analog conversion circuit, etc.) and each circuit included in the functional circuit region MFNC (e.g., the CPU 21, the GPU 22, etc.).

[0421] Furthermore, the display device of one embodiment of the present invention may be a display device DSP3 illustrated in FIG. 21C, which is obtained by changing the configuration of the display device DSP1 in FIG. 21A.

[0422] The display device DSP3 is a modified example of the display device DSP1, and is configured such that a sensor area TP is provided in an area overlapping the display area DIS.

[0423] The display device DSP3 also includes a drive circuit TDE and a drive circuit TDR, each of which is provided on a substrate BS. As shown in FIG. 21C , each of the drive circuits TDE and TDR is included in a drive circuit region DRV.

[0424] The driving circuit TDR has a function of sequentially transmitting pulse signals to the multiple sensors included in the sensor region TP, and the driving circuit TDE has a function of detecting changes in the amount of current flowing from the multiple sensors included in the sensor region TP.

[0425] As described above, the display device DSP3 is configured to have a touch panel as a user interface.

[0426] Although not shown, a sensor region TP may also be provided above the display region DIS of the display device DSP2. In this case, it is preferable that the drive circuits TDR and TDE are provided in the circuit region SIC.

[0427] <Cross-Sectional Configuration Example 1 of Display Device> Next, a configuration example in a cross-section of the display device DSP1 shown in FIG. 21A will be described.

[0428] The display device DSP1A shown in Fig. 23 is a cross-sectional configuration example of the display device DSP1 shown in Fig. 21A. The display device DSP1A has a configuration in which pixel circuits, drive circuits, etc. are provided on a substrate 101. The display device DSP1A in Fig. 23 also shows the drive circuit region DRV and display region DIS shown in Fig. 21A. In addition, in order to seal the pixel circuits, drive circuits, etc., the display unit DSP1A has a substrate 201 provided on the substrate 101 with the pixel circuits, drive circuits, etc. interposed therebetween.

[0429] The substrate 101 in FIG. 23 corresponds to the substrate BS shown in FIG. 21A . The diagonal size of the display device DSP1A can be determined, for example, by the type and size of the substrate 101. For example, when manufacturing a display device with a diagonal size of 30 inches or more, 50 inches or more, 70 inches or more, or 100 inches or more for a television device or an electronic device for digital signage, a glass substrate may be used as the substrate 101. For example, when manufacturing a display device with a diagonal size of 1.5 inches or less, 1 inch or less, or 0.5 inches or less for an XR device or a wearable information terminal, a semiconductor substrate may be used as the substrate 101.

[0430] The type and size of the substrate 201 are also determined depending on the type and size of the substrate 101. The material used for the substrate 201 can be selected from materials that can be used for the substrate BS depending on the direction of light emitted from the display device DSP1A. For example, if the display device DSP1A is a top-emission type, it is preferable that the substrate 201 be made of a material that is highly translucent.

[0431] In the description of the display device DSP1A in FIG. 23, it is assumed that the substrate 101 and the substrate 201 are glass substrates.

[0432] Furthermore, there are no particular limitations on the screen ratio (aspect ratio) of the display device DSP1A. For example, the display device DSP1A can support various screen ratios such as 1:1 (square), 4:3, 16:9, 16:10, 21:9, or 32:9.

[0433] In the display device DSP1 of Fig. 23, a transistor 100y and a transistor 100x are formed on a substrate. In this specification and the like, the transistors 100y and 100x are collectively referred to as transistors 100. Furthermore, light-emitting devices 200 (light-emitting devices 200R, 200G, and 200B in Fig. 23) are provided above the transistors 100y and 100x.

[0434] The transistor 100x is included in the display region DIS and functions as, for example, a transistor included in the pixel circuit PX. The transistor 100y functions as a transistor included in the drive circuit region DRV. Therefore, the transistor 100y can be, for example, a transistor included in the drive circuit SD or the drive circuit GD described in embodiment 1. The light-emitting device 200 can be a light-emitting device included in the pixel circuit PX.

[0435] Next, specific configurations of the transistor 100y and the transistor 100x will be described. Fig. 24A shows a schematic plan view of the transistor 100. Fig. 24B is a schematic cross-sectional view corresponding to the portion taken along dashed line A1-A2 in Fig. 24A and is also a schematic cross-sectional view of the transistor 100. Fig. 24C is a schematic cross-sectional view corresponding to the portion taken along dashed line A3-A4 in Fig. 24A and is also a schematic cross-sectional view of the transistor 100.

[0436] In Figures 24A to 24C, the direction of the dashed dotted line A1-A2 is the X direction, and the direction of the dashed dotted line A3-A4 is the Y direction. The direction perpendicular to the X and Y directions is the Z direction. The X and Y directions can be perpendicular to each other. The definitions of the X, Y, and Z directions may be the same or different in subsequent drawings. In describing schematic plan views such as Figure 24A, the right side may be referred to as the +X direction, the left side as the -X direction, the upper side as the +Y direction, and the lower side as the -Y direction. In describing schematic cross-sectional views such as Figure 24B, the right side may be referred to as the +X direction, the left side as the -X direction, the upper side as the +Z direction, and the lower side as the -Z direction. In describing schematic cross-sectional views such as Figure 24C, the right side may be referred to as the +Y direction, the left side as the -Y direction, the upper side as the +Z direction, and the lower side as the -Z direction.

[0437] The transistor 100 in FIGS. 24A to 24C includes insulating layers 111 to 113, an insulating layer 161, conductive layers 131 to 133, and a semiconductor layer 151.

[0438] For example, the insulating layer 111 functions as a base film or an interlayer film for providing regions functioning as sources, drains, channel formation regions, and the like of the transistor 100 thereover.

[0439] The insulating layer 111 can be made of, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, or silicon nitride. Alternatively, the insulating layer 111 can be made of, for example, silicon oxide doped with fluorine, silicon oxide doped with carbon, silicon oxide doped with carbon and nitrogen, or silicon oxide having vacancies. Silicon oxide and silicon oxynitride are particularly preferred because they are thermally stable. Materials such as silicon oxide, silicon oxynitride, or silicon oxide having vacancies are particularly preferred because they can easily form regions containing oxygen that is released by heating. Alternatively, the insulating layer 111 can be made of, for example, a resin. The material used for the insulating layer 111 may be an appropriate combination of the above-mentioned insulating materials.

[0440] In this specification and elsewhere, an oxynitride refers to a material whose composition contains more oxygen than nitrogen, and a nitride oxide refers to a material whose composition contains more nitrogen than oxygen. For example, silicon oxynitride refers to a material whose composition contains more oxygen than nitrogen, and silicon nitride oxide refers to a material whose composition contains more nitrogen than oxygen.

[0441] Furthermore, it is preferable to use an insulating material with a low relative dielectric constant for the insulating layer 111. By using an insulating material with a low relative dielectric constant as an interlayer film, it is possible to reduce the parasitic capacitance that occurs between wirings. Specifically, for example, the relative dielectric constant of the insulating layer 111 is preferably less than 4, and more preferably less than 3. Examples of insulating materials with a low relative dielectric constant include silicon oxide, silicon oxynitride, and silicon nitride oxide.

[0442] The conductive layer 131 is a conductor (which may be referred to as a terminal, a wiring, or the like) that functions as one of the source and the drain in the transistor 100. The conductive layer 132 is a conductor (which may be referred to as a terminal, a wiring, or the like) that functions as the other of the source and the drain in the transistor 100.

[0443] 24A to 24C , the conductive layer 131 is provided as a wiring extending in the −Y direction and the +Y direction, for example, and the conductive layer 132 is provided as a wiring extending in the −X direction and the X direction, for example.

[0444] For each of the conductive layers 131 and 132, it is preferable to use, for example, a metal element selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, cobalt, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, palladium, iridium, strontium, and lanthanum, an alloy containing two or more of the above-mentioned metal elements, or an alloy combining two or more of the above-mentioned metal elements. Furthermore, it is preferable to use, for example, tantalum nitride, titanium nitride, tungsten, a nitride containing titanium and aluminum, a nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, or an oxide containing lanthanum and nickel for the conductive layer 131. Tantalum nitride, titanium nitride, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, and oxides containing lanthanum and nickel are preferred because they are conductive materials that are resistant to oxidation or materials that maintain conductivity even when absorbing oxygen. Furthermore, the conductor may be a semiconductor with high electrical conductivity, typified by polycrystalline silicon containing an impurity element (e.g., phosphorus or arsenic), or a silicide (e.g., nickel silicide).

[0445] For example, the insulating layer 112 functions as an interlayer film that separates the source and drain of the transistor 100 .

[0446] For the insulating layer 112, for example, a material that can be used for the insulating layer 111 can be used.

[0447] Furthermore, an opening 102 having a side surface that is approximately perpendicular to the X-Y plane (a taper angle of 70 degrees or more and 110 degrees or less) is formed in a region of the insulating layer 112 where the transistor 100 is provided. In particular, the area of ​​the opening 102 can be reduced as the taper angle approaches 90 degrees, thereby reducing the area for forming the transistor 100. Furthermore, the semiconductor layer 151 including the channel formation region of the transistor 100 is provided so as to be in contact with the conductive layer 131 and the conductive layer 132 through the opening 102.

[0448] 24A , the shape of the opening 102 is a perfect circle, for example. However, one embodiment of the present invention is not limited to this. The shape of the opening 102 may be, for example, a figure (including an ellipse) whose edge is a single closed curve, or a polygon with rounded corners. Specifically, the shape of the opening 102 may be an ellipse, a shape including a curve (for example, an ellipse, a cloud shape, a triangle with rounded corners, a polygon such as a square or a pentagon), or a shape with corners (for example, a polygon such as a triangle, a square or a pentagon). Alternatively, the shape may be a combination of these shapes.

[0449] The semiconductor layer 151 can be, for example, a metal oxide that functions as an oxide semiconductor. In this case, the transistor 100 becomes an OS transistor. For example, the metal oxide preferably contains at least indium. Alternatively, it preferably contains indium and zinc. Furthermore, it is preferable that the element M is also contained. As the element M, one or more selected from aluminum, gallium, silicon, yttrium, tin, copper, vanadium, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, cobalt, and antimony can be used. In particular, the element M is preferably one or more of aluminum, gallium, yttrium, and tin. Furthermore, it is more preferable that the element M contains one or both of gallium and tin.

[0450] In particular, crystalline indium oxide is preferably used, for example, for the semiconductor layer 151. That is, by using the transistor 100 as an OS transistor including crystalline indium oxide in a channel formation region, as described in detail in Embodiment 2, the on-state characteristics of the transistor 100 can be improved and the off-state current can be reduced.

[0451] For the semiconductor layer 151, other than crystalline indium oxide, In-Ga-Zn oxide (indium-gallium-zinc oxide), Ga-Zn oxide, or gallium oxide can be used.

[0452] In particular, it is more preferable that the In—Ga—Zn oxide used for the semiconductor layer 151 be a metal oxide having a composition of In:Ga:Zn=1:1:1 (atomic ratio) or a composition thereabout, a composition of 4:2:3 (atomic ratio) or a composition thereabout, or a composition of 3:1:2 (atomic ratio) or a composition thereabout. As another example, it is also preferable to use In—Zn oxide for the semiconductor layer 151. In particular, it is more preferable that the In—Zn oxide be a metal oxide having a composition of In:Zn=4:1 (atomic ratio) or a composition thereabout.

[0453] The metal oxide functioning as an oxide semiconductor is described in detail in Embodiment 2.

[0454] In the transistor 100, an insulating layer 161 is provided over the semiconductor layer 151. Specifically, in a plan view, the insulating layer 161 is positioned so as to overlap a channel formation region included in the semiconductor layer 151. Therefore, the insulating layer 161 functions as a gate insulating film of the transistor 100.

[0455] The insulating layer 161 may be made of, for example, aluminum oxide, hafnium oxide, tantalum oxide, zirconium oxide, lead zirconate titanate (PZT), strontium titanate (SrTiO ３ ), or (Ba,Sr)TiO ３It is preferable to use a single layer or a stack of insulators containing a so-called high-k material such as BST (Bistable Silicon Trioxide). Alternatively, the insulating layer 161 may be made of an insulator having a high dielectric constant, such as an oxide containing aluminum and hafnium, an oxynitride containing aluminum and hafnium, an oxide containing silicon and hafnium, an oxynitride containing silicon and hafnium, or a nitride containing silicon and hafnium.

[0456] In the transistor 100, the conductive layer 133 is provided over the insulating layer 161 so as to fill the opening 102. The conductive layer 133 is a conductor (which may also be referred to as a terminal, a wiring, or the like) that functions as a gate in each of the transistors 100.

[0457] For the conductive layer 133, for example, a material that can be used for the conductive layer 131 or the conductive layer 132 can be used.

[0458] 24A to 24C, the conductive layer 133 is provided as a wiring extending in the Y direction, for example.

[0459] 24A to 24C , the conductive layer 131 functioning as one of the source and the drain is located below the insulating layer 112 that serves as an interlayer film, and the conductive layer 132 functioning as the other of the source and the drain is located above the insulating layer 112. Therefore, the transistor 100 has a structure in which a channel formation region is provided along the opening 102.

[0460] In this way, the transistor 100 has a structure in which the source electrode and the drain electrode are located at different heights, and the current flowing through the semiconductor layer flows in the height direction. In other words, it can be said that the channel length direction has a component in the height direction (vertical direction), and therefore the transistor 100 can also be called a VFET (Vertical Field Effect Transistor), a vertical transistor, a vertical channel transistor, a vertical channel type transistor, or the like.

[0461] 24A to 24C , by providing the channel formation region of the transistor along the side surface of the opening in the insulator that functions as an interlayer film, the formation area of ​​the transistor can be made smaller than when the channel formation region of the transistor is provided along the X-Y plane. Furthermore, since the source electrode, semiconductor layer, and drain electrode of the transistor 100 can be provided in an overlapping manner, the occupied area can be significantly reduced compared to a so-called planar transistor in which the semiconductor is arranged in a planar shape. Therefore, by forming a circuit using one or both of the transistors 100, the area of ​​the circuit can be reduced. Furthermore, as a result, the area of ​​a semiconductor device or display device including the circuit can be reduced.

[0462] Note that a p-channel transistor or an n-channel transistor can be used as the transistor 100. Alternatively, a plurality of transistors 100 may be provided and both p-channel transistors and n-channel transistors may be used.

[0463] The transistor 100 may be a transistor having a VLFET (Vertical Lateral Field Effect Transistor) structure, instead of the vertical channel transistor shown in FIGS. 24A to 24C.

[0464] The transistor 100 shown in Figures 25A to 25C is a VLFET transistor with a structure in which current flows both vertically and horizontally. Specifically, a semiconductor layer is positioned so as to contact the side surface of an opening provided in a first insulating layer and the upper surface of a second insulating layer that corresponds to the bottom of the opening, and the semiconductor layer includes a channel formation region of the transistor 100. In other words, the channel length of the transistor 100 has a component along the side surface of the opening and a component along the bottom of the opening, making it easier to make it longer than the channel length of a conventional transistor structure. Note that the channel length here can be the length between the source and drain of the channel formation region.

[0465] Note that the transistor 100 in FIG. 25B shows a channel length 171 of a channel formation region included in the semiconductor layer 151.

[0466] Increasing the channel length can reduce the off-state current (leakage current) of the transistor. Therefore, for example, by applying the transistor 100 shown in FIGS. 25A to 25C to the transistor Tr1 in each of the pixel circuits PX shown in FIGS. 17A to 20, the potential at the first terminal of the capacitance element Cs1 can be maintained for a long period of time. In other words, it is possible to prevent unintended fluctuations in the potential at the first terminal of the capacitance element Cs1 due to leakage current or the like.

[0467] Fig. 25A shows a schematic plan view of the transistor 100. Fig. 25B is a schematic cross-sectional view corresponding to the portion of the dashed-dotted line A1-A2 shown in Fig. 25A and is also a schematic cross-sectional view of the transistor 100. Fig. 25C is a schematic cross-sectional view corresponding to the portion of the dashed-dotted line A3-A4 shown in Fig. 25A and is also a schematic cross-sectional view of the transistor 100.

[0468] 25A to 25C includes, for example, insulating layers 111 to 113, an insulating layer 161, conductive layers 132a, 132b, and 133, and a semiconductor layer 151.

[0469] 25A to 25C, the descriptions of the insulating layers 111 to 113, the insulating layer 161, the conductive layer 133, and the semiconductor layer 151 shown in Figures 24A to 24C can be referred to. Also, the description of the conductive layer 132 shown in Figures 24A to 24C can be referred to for the conductive layer 132a and the conductive layer 132b shown in Figures 25A to 25C.

[0470] 25A to 25C , the insulating layer 112 has a function as an insulating layer for forming the semiconductor layer 151. As shown in FIG. 25A to FIG. 25C , the insulating layer 112 has an opening 103, and the transistor 100 has a structure in which a part of the semiconductor layer 151 is included in the opening 103. Specifically, the opening 103 is provided in the insulating layer 112 so that the semiconductor layer 151 has a region in contact with a sidewall of the insulating layer 112 corresponding to the side surface of the opening 103 and an upper surface of the insulating layer 111 corresponding to the bottom of the opening 103. Note that the transistor 100 has a structure in which a channel formation region of the transistor 100 is included in the semiconductor layer 151 provided inside the opening 103.

[0471] 25A , the shape of the opening 103 is a perfect circle, but this is not a limitation of one embodiment of the present invention. The shape of the opening 103 may be, for example, a figure (including an ellipse) whose edge is a single closed curve, or a polygon with rounded corners.

[0472] For example, the conductive layer 132a functions as one of the source and the drain in the transistor 100. For example, the conductive layer 132b functions as the other of the source and the drain in the transistor 100. Note that all or part of the conductive layer 132a and the conductive layer 132b may be referred to as, for example, an electrode, a terminal, a wiring, or the like.

[0473] The conductive layers 132a and 132b are each located above the insulating layer 112. In particular, the conductive layers 132a and 132b are separated by the opening 103 to form a pair of conductive layers in the schematic top view of FIG. 25A and the schematic cross-sectional view of FIG. 25B. Therefore, in the transistor 100 in FIGS. 25A to 25C, the widths of the conductive layers 132a and 132b in the Y direction are preferably smaller than the width of the opening 103 in the Y direction in the schematic top view of FIG. 25A. Note that in the schematic top view of FIG. 25A, for example, the opening 103 is a perfect circle, and the width of the opening 103 in the Y direction is the diameter of the perfect circle.

[0474] 25A to 25C, the conductive layer 132a is provided as a wiring extending in the −X direction, for example, and the conductive layer 132b is provided as a wiring extending in the +X direction, for example.

[0475] As described above, the semiconductor layer 151 has a region in contact with the sidewall of the insulating layer 112 corresponding to the side surface of the opening 103 and the top surface of the insulating layer 111 corresponding to the bottom of the opening 103. Furthermore, the semiconductor layer 151 has a region in contact with the top surface of the conductive layer 132a and the top surface of the conductive layer 132b. As described above, the semiconductor layer 151 includes a channel formation region of the transistor 100. Note that the channel length 171 of the channel formation region of the transistor 100 is determined by the area of ​​the bottom of the opening 103 and the depth of the opening 103 (the length of the side surface of the opening 103 or the film thickness of the insulating layer 112).

[0476] For example, the insulating layer 161 functions as a gate insulating layer (sometimes referred to as a gate insulating film) of the transistor 100. The insulating layer 161 has regions in contact with the top surface of the semiconductor layer 151, the top surface of the conductive layer 132a, and the top surface of the conductive layer 132b.

[0477] In particular, the thickness of the insulating layer 161 significantly contributes to the electrical characteristics of the transistor 100. For example, when the thickness of the insulating layer 161 is increased (when the gate insulating layer of the transistor 100 is increased), the voltage gradient between the gate (conductive layer 133) of the transistor 100 and the channel formation region of the semiconductor layer 151 can be made gentler, thereby increasing the tolerance to the gate potential (also referred to as gate-source voltage or gate-drain voltage). On the other hand, when the gate insulating film of the transistor is thinned, the change in the electric field applied from the gate to the channel formation region of the semiconductor when the gate potential is changed becomes faster, thereby increasing the driving frequency of the transistor.

[0478] Therefore, for example, by determining the film thickness of the insulating layer 161, which is the gate insulating layer of each of the multiple transistors 100, it is possible to easily create transistors with high resistance to gate potential and transistors with high driving frequencies.

[0479] 23, an insulating layer 181 is formed above the transistor 100y and the transistor 100x, and an insulating layer 114 is formed on the insulating layer 181. Openings are provided in the insulating layer 113, the insulating layer 181, and the insulating layer 114, and a conductive layer 134 is embedded in the openings. Therefore, the conductive layer 132 has a region in contact with the conductive layer 134.

[0480] The insulating layer 181 preferably has a function of suppressing diffusion of impurities such as water and hydrogen (e.g., hydrogen atoms and / or hydrogen molecules). That is, the insulating layer 181 preferably functions as a barrier insulating film that suppresses the impurities from entering the transistor 100. The insulating layer 181 also preferably has a function of suppressing diffusion of oxygen (e.g., oxygen atoms and / or oxygen molecules). For example, the insulating layer 181 preferably has lower oxygen permeability than the insulating layer 113 and the insulating layer 114. That is, the insulating layer 181 preferably has a function of suppressing oxygen from being released from the semiconductor layer 151 and diffusing above the insulating layer 113.

[0481] As an example of a film having a barrier property against hydrogen, silicon nitride formed by a CVD method can be used.

[0482] The amount of desorption of hydrogen can be analyzed by, for example, thermal desorption spectrometry (TDS). For example, the amount of desorption of hydrogen from the insulating layer 481 is calculated by TDS as follows: when the surface temperature of the film is 50° C. or higher and 500° C. or lower, the amount of desorption converted into hydrogen atoms is 10×10 per area of ​​the insulating layer 481. １５ atoms / cm ２ It is preferable that the density is 5×10 or less. １５ atoms / cm２ It is more preferable to set the following:

[0483] Therefore, the insulating layer 181 may be formed of an insulator having a function of suppressing the permeation of impurities such as water and hydrogen and oxygen, such as a single layer or a stack of insulators containing one or more elements selected from boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, and tantalum. Specifically, examples of insulators having a function of suppressing the permeation of impurities such as water and hydrogen and oxygen include metal oxides such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide. Furthermore, examples of insulators having a function of suppressing the permeation of impurities such as water and hydrogen and oxygen include oxides containing aluminum and hafnium (hafnium aluminate). Furthermore, examples of insulators that have the function of suppressing the permeation of impurities such as water and hydrogen, and oxygen include nitrides such as aluminum nitride, silicon nitride oxide, and silicon nitride.

[0484] In particular, it is preferable to use aluminum oxide or silicon nitride for the insulating layer 181. This can prevent impurities such as water and hydrogen from diffusing from above the insulating layer 181 to the transistor 100. Furthermore, it can prevent oxygen from diffusing from above the insulating layer 181 to the transistor 100.

[0485] For example, the insulating layer 114 preferably has a lower dielectric constant than the insulating layer 181. By using a material with a low dielectric constant as an interlayer film, parasitic capacitance generated between wirings can be reduced. In addition, the insulating layer 114 preferably has a reduced concentration of impurities such as water and hydrogen.

[0486] Therefore, for the insulating layer 114, for example, a material that can be used for any one of the insulating layers 111 to 113 can be used.

[0487] As the material for each plug and wiring (e.g., the conductive layer 134), one or more conductive materials selected from metal materials, alloy materials, metal nitride materials, and metal oxide materials can be used in a single layer or a stacked layer. It is preferable to use a high-melting-point material such as tungsten or molybdenum that has both heat resistance and conductivity, and tungsten is preferred. Furthermore, it is preferable to use a low-resistance conductive material such as aluminum or copper as the material. The use of a low-resistance conductive material can reduce the wiring resistance.

[0488] An insulating layer 182 and an insulating layer 115 are stacked in this order over the insulating layer 114 and the conductive layer 134 .

[0489] Furthermore, it is preferable to use an insulating film (referred to as a barrier insulating film or barrier insulating layer) for the insulating layer 182 that has barrier properties to prevent impurities such as water and hydrogen from diffusing from the substrate 101 or the transistor 100 to the region above the insulating layer 182 (for example, the region where the light-emitting device 200R, the light-emitting device 200G, and the light-emitting device 200B are provided).

[0490] Note that the insulating layer 115 preferably has a lower dielectric constant than the insulating layer 182. The insulating layer 115 preferably has a reduced concentration of impurities such as water and hydrogen. For this reason, the insulating layer 115 can be formed using, for example, a material that can be used for any one of the insulating layers 112 to 114.

[0491] Furthermore, a conductive layer 135 that connects to a light-emitting device or the like that is provided above the insulating layer 115 is embedded in the insulating layer 182 and the insulating layer 115. The conductive layer 135 functions as a plug or wiring. Furthermore, for conductors that function as plugs or wiring, the same reference numeral may be used to denote multiple structures. Furthermore, in this specification and the like, the wiring and the plug that connects to the wiring may be integrated. That is, there are cases where a part of the conductor functions as the wiring, and cases where a part of the conductor functions as the plug.

[0492] For the conductive layer 135, for example, a material that can be used for the conductive layer 134 can be used.

[0493] An insulating layer 281 and an insulating layer 211 are formed in this order over the insulating layer 115 and the conductive layer 135 .

[0494] For example, the insulating layer 281 is preferably an insulating layer having barrier properties against one or more selected from hydrogen, oxygen, and water, similar to the insulating layers 181 and 182. Furthermore, the insulating layer 211 is preferably an insulator with a relatively low relative dielectric constant, similar to the insulating layer 115, in order to reduce parasitic capacitance generated between wirings. For this reason, the insulating layer 281 can be made of a material that can be used for the insulating layer 181 or the insulating layer 182.

[0495] The insulating layer 211 functions as an interlayer insulating film and a planarizing film.

[0496] For example, the insulating layer 211 preferably has a lower dielectric constant than the insulating layer 281. The insulating layer 211 preferably has a reduced concentration of impurities such as water and hydrogen. For this reason, the insulating layer 211 can be formed using, for example, a material that can be used for any one of the insulating layers 111 to 113.

[0497] The light emitting device 200 and the connection portion 271 are formed on the insulating layer 211 .

[0498] The connection portion 271 may be referred to as a cathode contact portion, and is connected to the cathode electrodes of the light-emitting devices 200R, 200G, and 200B. In Fig. 23, the connection portion 271 has one or more conductive layers selected from conductive layers 231a to 231c described later, at least one conductive layer from conductive layers 232a to 232c described later, one or more conductive layers selected from conductive layers 233a to 233c described later, a common layer 292 described later, and a conductive layer 234 functioning as a common electrode described later.

[0499] The connection portion 271 may be provided so as to surround the four sides of the display portion in a plan view, or may be provided inside the display portion (for example, between adjacent light-emitting devices 200).

[0500] The light-emitting device 200R includes a conductive layer 231a, a conductive layer 232a on the conductive layer 231a, and a conductive layer 233a on the conductive layer 232a. The conductive layers 231a, 232a, and 233a may all be referred to as pixel electrodes, or some of them may be referred to as pixel electrodes. The light-emitting device 200G includes a conductive layer 231b, a conductive layer 232b on the conductive layer 231b, and a conductive layer 233b on the conductive layer 232b. Similar to the light-emitting device 200R, the conductive layers 231b, 232b, and 233b may all be referred to as pixel electrodes, or some of them may be referred to as pixel electrodes. The light-emitting device 200B includes a conductive layer 231c, a conductive layer 232c on the conductive layer 231c, and a conductive layer 233c on the conductive layer 232c. As in the light-emitting devices 200R and 200G, the conductive layers 231c, 232c, and 233c may all be called pixel electrodes, or some of them may be called pixel electrodes.

[0501] The conductive layers 231a to 231c and the conductive layers 232a to 232c can be, for example, conductive layers functioning as reflective electrodes. For the conductive layers functioning as reflective electrodes, a conductor with high reflectivity to visible light, such as silver, aluminum, or an alloy film of silver (Ag), palladium (Pd), and copper (Cu) (Ag-Pd-Cu (APC) film), can be used. Furthermore, the conductive layers 231a to 231c and the conductive layers 232a to 232c can be a stacked film of aluminum sandwiched between a pair of titanium films (a stacked film of Ti, Al, and Ti in this order) or a stacked film of silver sandwiched between a pair of indium tin oxide films (a stacked film of ITO, Ag, and ITO in this order).

[0502] Alternatively, for example, a conductive layer functioning as a reflective electrode may be used as the conductive layers 231a to 231c, and a highly light-transmitting conductor may be used as the conductive layers 232a to 232c. An example of a highly light-transmitting conductor is indium tin oxide (sometimes referred to as ITO). An alloy of silver and magnesium may be used for the conductive layers 232a to 232c as long as it is a thin film that transmits light.

[0503] The conductive layers 233a to 233c can be, for example, a conductive layer functioning as a transparent electrode. The conductive layer functioning as a transparent electrode can be, for example, the above-described conductor having high light-transmitting properties.

[0504] The conductive layer 231a is connected to the conductive layer 135 embedded in the insulating layer 115 through an opening provided in the insulating layer 211. The end of the conductive layer 232a is located outside the end of the conductive layer 231a. The end of the conductive layer 232a and the end of the conductive layer 233a are aligned or approximately aligned.

[0505] Conductive layer 231b, conductive layer 232b, and conductive layer 233b in light-emitting device 200G, and conductive layer 231c, conductive layer 232c, and conductive layer 233c in light-emitting device 200B are similar to conductive layer 231a, conductive layer 232a, and conductive layer 233a in light-emitting device 200R, and therefore detailed description thereof will be omitted.

[0506] The conductive layers 231a, 231b, and 231c have recesses formed therein so as to cover the openings formed in the insulating layer 211. The layer 202 is buried in the recesses.

[0507] The layer 202 has a function of planarizing the recessed portions of the conductive layers 231a to 231c. Conductive layers 232a to 232c in contact with the conductive layers 231a to 231c, respectively, are provided over the conductive layers 231a to 231c and over the layer 202. Therefore, regions overlapping with the recessed portions of the conductive layers 231a to 231c can also be used as light-emitting regions, and the aperture ratio of the pixel can be increased.

[0508] The layer 202 may be an insulating layer or a conductive layer. Various inorganic insulating materials, organic insulating materials, and conductive materials can be used as appropriate for the layer 202. In particular, the layer 202 is preferably formed using an insulating material.

[0509] An insulating layer containing an organic material can be suitably used for the layer 202. For example, acrylic resin, polyimide resin, epoxy resin, polyamide resin, polyimideamide resin, siloxane resin, benzocyclobutene resin, phenolic resin, or precursors of these resins can be used for the layer 202. Alternatively, a photosensitive resin can be used for the layer 202. Examples of photosensitive resins include positive-type materials and negative-type materials.

[0510] By using a photosensitive resin, the layer 202 can be manufactured only through exposure and development steps, and the influence of dry etching or wet etching on the surfaces of the conductive layers 231 a, 231 b, and 231 c can be reduced. Furthermore, by forming the layer 202 using a negative photosensitive resin, the layer 202 can be formed using the same photomask (exposure mask) as that used to form the openings in the insulating layer 211 in some cases.

[0511] Although Fig. 23 shows an example in which the top surface of layer 202 has a flat portion, the shape of layer 202 is not particularly limited. As shown in Fig. 26A, the top surface of layer 202 may have a shape that has a concave curved surface at the center and its vicinity in a cross-sectional view. Alternatively, as shown in Fig. 26B, layer 202 may have a shape that has a convex curved surface at the center and its vicinity in a cross-sectional view. Furthermore, as shown in Fig. 26C, layer 202 may have a shape that has a concave curved surface and a convex curved surface at the center and its vicinity.

[0512] Light-emitting device 200R has a first layer 291a, a common layer 292 on the first layer 291a, and a conductive layer 234 on the common layer 292. Light-emitting device 200G has a second layer 291b, a common layer 292 on the second layer 291b, and a conductive layer 234 on the common layer 292. Light-emitting device 200B has a third layer 291c, a common layer 292 on the third layer 291c, and a conductive layer 234 on the common layer 292.

[0513] The first layer 291a is formed so as to cover the upper and side surfaces of the conductive layer 232a and the conductive layer 233a. Similarly, the second layer 291b is formed so as to cover the upper and side surfaces of the conductive layer 232b and the conductive layer 233b. Similarly, the third layer 291c is formed so as to cover the upper and side surfaces of the conductive layer 232c and the conductive layer 233c. Therefore, the entire regions where the conductive layers 232a, 232b, and 232c are provided can be used as light-emitting regions of the light-emitting devices 200R, 200G, and 200B, thereby increasing the aperture ratio of the pixels.

[0514] In light-emitting device 200R, first layer 291a and common layer 292 can be collectively referred to as an EL layer. Similarly, in light-emitting device 200G, second layer 291b and common layer 292 can be collectively referred to as an EL layer. Similarly, in light-emitting device 200B, third layer 291c and common layer 292 can be collectively referred to as an EL layer.

[0515] The structure of the light emitting device of this embodiment is not particularly limited, and may be a single structure or a tandem structure.

[0516] The first layer 291a, the second layer 291b, and the third layer 291c are processed into island shapes by lithography. Therefore, the angle between the top surface and the side surface of each of the first layer 291a, the second layer 291b, and the third layer 291c is close to 90 degrees at the end. On the other hand, for example, an organic film formed using FMM (Fine Metal Mask) tends to gradually become thinner closer to the end, and the top surface is formed in a sloped shape over a range of, for example, 1 μm to 10 μm, making it difficult to distinguish between the top surface and the side surface.

[0517] The top surface and side surface of each of the first layer 291a, the second layer 291b, and the third layer 291c are clearly distinguishable. As a result, in adjacent first and second layers 291a and 291b, one side surface of the first layer 291a and one side surface of the second layer 291b are arranged opposite each other. This is true for any combination of the first layer 291a, the second layer 291b, and the third layer 291c.

[0518] The first layer 291 a, the second layer 291 b, and the third layer 291 c each have at least a light-emitting layer. For example, it is preferable that the first layer 291 a has a light-emitting layer that emits red light, the second layer 291 b has a light-emitting layer that emits green light, and the third layer 291 c has a light-emitting layer that emits blue light. Furthermore, each light-emitting layer may be of a color other than the above, such as cyan, magenta, yellow, or white.

[0519] Each of the first layer 291a, the second layer 291b, and the third layer 291c preferably includes a light-emitting layer and a carrier transport layer (electron transport layer or hole transport layer) on the light-emitting layer. The surfaces of the first layer 291a, the second layer 291b, and the third layer 291c may be exposed during the manufacturing process of the display device. Therefore, by providing the carrier transport layer on the light-emitting layer, the light-emitting layer can be prevented from being exposed to the outermost surface, and damage to the light-emitting layer can be reduced. This can improve the reliability of the light-emitting device.

[0520] The common layer 292 includes, for example, an electron injection layer or a hole injection layer. Alternatively, the common layer 292 may include a stack of an electron transport layer and an electron injection layer, or a stack of a hole transport layer and a hole injection layer. The common layer 292 is shared by the light-emitting devices 200R, 200G, and 200B.

[0521] 23 , the conductive layer 234 is a common electrode shared by the light-emitting devices 200R, 200G, and 200B. The conductive layer 234, which is a common electrode shared by the plurality of light-emitting devices, is in contact with a conductor included in the connection portion 271.

[0522] The insulating layer 212 preferably functions as a barrier insulating layer against water and / or oxygen. The insulating layer 212 preferably has a function of suppressing diffusion of water and / or oxygen. The insulating layer 212 preferably has a function of capturing or fixing (also referred to as gettering) water and / or oxygen. The insulating layer 212 has a function as a barrier insulating layer or a gettering function, which can suppress the entry of impurities (typically, water and / or oxygen) that can diffuse from the outside into each light-emitting device. This structure makes it possible to provide a highly reliable light-emitting device and a highly reliable display panel.

[0523] The insulating layer 212 preferably has a low impurity concentration. This can prevent impurities from entering the EL layer from the insulating layer 212 and causing deterioration of the EL layer. Furthermore, a low impurity concentration in the insulating layer 212 can improve barrier properties against water and / or oxygen. For example, it is desirable that the insulating layer 212 has a sufficiently low hydrogen concentration and / or carbon concentration.

[0524] An insulating layer containing an organic material can be suitably used as the insulating layer 213. A photosensitive organic resin is preferably used as the organic material, such as a photosensitive resin composition containing an acrylic resin. The viscosity of the material for the insulating layer 213 is preferably 1 cP or more and 1500 cP or less, and more preferably 1 cP or more and 12 cP or less. By setting the viscosity of the material for the insulating layer 213 within the above range, the insulating layer 213 having a tapered shape, as described below, can be formed relatively easily. Note that in this specification and elsewhere, the term "acrylic resin" does not refer only to polymethacrylic acid ester or methacrylic resin, but may refer to all acrylic polymers in a broad sense.

[0525] In this specification and the like, the term "tapered shape" refers to a shape in which at least a part of a side surface of a structure is inclined with respect to the substrate surface. For example, it is preferable that the structure has a region in which the angle (also referred to as the taper angle) between the inclined side surface and the substrate surface is less than 90 degrees.

[0526] As described below, the insulating layer 213 may have a tapered side surface, and the organic material that can be used for the insulating layer 213 is not limited to the above. For example, the insulating layer 213 may be made of acrylic resin, polyimide resin, epoxy resin, imide resin, polyamide resin, polyimideamide resin, silicone resin, siloxane resin, benzocyclobutene resin, phenolic resin, or precursors of these resins. The insulating layer 213 may also be made of organic materials such as polyvinyl alcohol (PVA), polyvinyl butyral (PVB), polyvinylpyrrolidone, polyethylene glycol, polyglycerin, pullulan, water-soluble cellulose, or alcohol-soluble polyamide resin. The insulating layer 213 may also be made of a photosensitive resin, such as a photoresist. Examples of photosensitive resins include positive-type materials and negative-type materials.

[0527] The insulating layer 213 may be made of a material that absorbs visible light. By absorbing light emitted from the light-emitting device, the insulating layer 213 can suppress leakage of light (stray light) from the light-emitting device to another adjacent light-emitting device through the insulating layer 213. This can improve the display quality of the display panel. Furthermore, since the display quality can be improved without using a polarizing plate in the display panel, the display panel can be made lighter and thinner.

[0528] Examples of materials that absorb visible light include materials containing pigments such as black, materials containing dyes, light-absorbing resin materials (e.g., polyimide), and resin materials that can be used for color filters (color filter materials). In particular, using a resin material in which two or more color filter materials are laminated or mixed is preferable because it can enhance the visible light blocking effect. In particular, mixing three or more color filter materials makes it possible to form a black or nearly black resin layer.

[0529] The insulating layer 213 can be formed by a wet film formation method such as spin coating, dipping, spray coating, inkjet printing, dispensing, screen printing, offset printing, doctor knife method, slit coating, roll coating, curtain coating, or knife coating. In particular, it is preferable to form the organic insulating film that becomes the insulating layer 213 by spin coating.

[0530] The insulating layer 213 is formed at a temperature lower than the heat resistance temperature of the EL layer. The substrate temperature when the insulating layer 213 is formed is typically 200° C. or lower, preferably 180° C. or lower, more preferably 160° C. or lower, more preferably 150° C. or lower, and more preferably 140° C. or lower.

[0531] Below, the structure of the insulating layer 213 and the like will be described using the structure of the insulating layer 213 between the light-emitting device 200R and the light-emitting device 200G as an example. The same can be said for the insulating layer 213 between the light-emitting device 200G and the light-emitting device 200B and the insulating layer 213 between the light-emitting device 200B and the light-emitting device 200R. Furthermore, below, the end of the insulating layer 213 on the second layer 291b will be described as an example in some cases, but the same can be said for the end of the insulating layer 213 on the first layer 291a and the end of the insulating layer 213 on the third layer 291c.

[0532] The insulating layer 213 preferably has a tapered shape on its side surface with a taper angle θ1 in a cross-sectional view of the display device. The taper angle θ1 is the angle between the side surface of the insulating layer 213 and the substrate surface. However, it is not limited to the substrate surface, and may be the angle between the top surface of the flat portion of the insulating layer 212 or the top surface of the flat portion of the second layer 291b and the side surface of the insulating layer 213. Furthermore, by tapering the side surface of the insulating layer 213, the side surface of the insulating layer 212 and the side surface of the mask layer 203a may also be tapered.

[0533] The taper angle θ1 of the insulating layer 213 is less than 90 degrees, preferably 60 degrees or less, and more preferably 45 degrees or less. By forming the side end of the insulating layer 213 in such a forward tapered shape, the common layer 292 and the conductive layer 234 provided on the side end of the insulating layer 213 can be formed with good coverage without causing discontinuities or local thinning of the film. This can improve the in-plane uniformity of the common layer 292 and the conductive layer 234, thereby improving the display quality of the display device.

[0534] In addition, in a cross-sectional view of the display device, the upper surface of the insulating layer 213 preferably has a convex curved shape. The convex curved shape of the upper surface of the insulating layer 213 preferably has a shape that bulges gently toward the center. In addition, it is preferable that the convex curved portion at the center of the upper surface of the insulating layer 213 smoothly connects to the tapered portion at the side edge. By forming the insulating layer 213 in such a shape, the common layer 292 and the conductive layer 234 can be formed with good coverage over the entire insulating layer 213.

[0535] The insulating layer 213 is formed in a region between two EL layers (for example, a region between the first layer 291a and the second layer 291b), with a portion of the insulating layer 213 being disposed between a side edge of one EL layer (for example, the first layer 291a) and a side edge of the other EL layer (for example, the second layer 291b).

[0536] It is also preferable that one end of the insulating layer 213 overlaps with the conductive layer 232a functioning as a pixel electrode, and the other end of the insulating layer 213 overlaps with the conductive layer 232b functioning as a pixel electrode. This structure allows the end of the insulating layer 213 to be formed on a substantially flat region of the first layer 291a (second layer 291b). Therefore, it is relatively easy to process the insulating layer 213 into a tapered shape as described above.

[0537] As described above, by providing the insulating layer 213 or the like, it is possible to prevent discontinuities and locally thin portions from being formed in the common layer 292 and the conductive layer 234 from the substantially flat region of the first layer 291 a to the substantially flat region of the second layer 291 b. Therefore, it is possible to prevent connection defects caused by discontinuities and increases in electrical resistance caused by locally thin portions in the common layer 292 and the conductive layer 234 between the light-emitting devices.

[0538] The display device of this embodiment can reduce the distance between light-emitting devices. Specifically, the distance between light-emitting devices, the distance between EL layers, or the distance between pixel electrodes can be less than 10 μm, 8 μm or less, 5 μm or less, 3 μm or less, 2 μm or less, 1 μm or less, 500 nm or less, 200 nm or less, 100 nm or less, 90 nm or less, 70 nm or less, 50 nm or less, 30 nm or less, 20 nm or less, 15 nm or less, or 10 nm or less. In other words, the display device of this embodiment has a region where the distance between two adjacent island-shaped EL layers is 1 μm or less, preferably a region where the distance is 0.5 μm (500 nm) or less, and more preferably a region where the distance is 100 nm or less. In this way, by reducing the distance between light-emitting devices, a display device with high definition and a large aperture ratio can be provided.

[0539] A protective layer 204 is provided on the light-emitting device 200. The protective layer 204 is a film that functions as a passivation film that protects the light-emitting device 200. By providing the protective layer 204 that covers the light-emitting device, it is possible to prevent impurities such as water and oxygen from entering the light-emitting device, thereby improving the reliability of the light-emitting device 200. The protective layer 204 can be made of, for example, aluminum oxide, silicon nitride, or silicon nitride oxide.

[0540] The protective layer 204 and the substrate 201 are bonded via an adhesive layer 205. A solid sealing structure, a hollow sealing structure, or the like can be applied to seal the light-emitting device. In FIG. 23 , the space between the substrates 101 and 201 is filled with the adhesive layer 205, and a solid sealing structure is applied. Alternatively, the space may be filled with an inert gas (such as nitrogen or argon), and a hollow sealing structure may be applied. In this case, the adhesive layer 205 may be provided so as not to overlap with the light-emitting device. Furthermore, the space may be filled with a resin different from the frame-shaped adhesive layer 205.

[0541] The adhesive layer 205 can be made of various curable adhesives, such as ultraviolet-curable photocurable adhesives, reactive curable adhesives, thermosetting adhesives, and anaerobic adhesives. Examples of such adhesives include epoxy resin, acrylic resin, silicone resin, phenolic resin, polyimide resin, imide resin, PVC (polyvinyl chloride) resin, PVB (polyvinyl butyral) resin, and EVA (ethylene vinyl acetate) resin. Materials with low moisture permeability, such as epoxy resin, are particularly preferred. Two-component resins may also be used. An adhesive sheet may also be used.

[0542] The display device DSP1A is a top-emission type. Light emitted by the light-emitting device is emitted toward the substrate 201. For this reason, it is preferable to use a material that is highly transparent to visible light for the substrate 201. For example, it is preferable to select a substrate that is highly transparent to visible light for the substrate 201 from among substrates that can be used for the substrate 101 and the substrate BS. The pixel electrode contains a material that reflects visible light, and the counter electrode (conductive layer 234) contains a material that transmits visible light.

[0543] Note that the display device of one embodiment of the present invention may be a bottom-emission type instead of a top-emission type in which light emitted from a light-emitting device is emitted toward the substrate 101. In this case, it is preferable to select a substrate that has high transmittance to visible light as the substrate 101.

[0544] Next, a configuration example in a cross-sectional view of the display device DSP1 shown in FIG. 21A, which is different from the display device DSP1A of FIG. 23, will be described.

[0545] The display device DSP1B shown in FIG. 27 is a cross-sectional configuration example of the display device DSP1 shown in FIG. 21A, and is a display device including a transmissive liquid crystal element (sometimes called a liquid crystal display device).

[0546] The display device DSP1B has a substrate 101 and a substrate 301, and a pixel circuit including a liquid crystal element and a driver circuit are sandwiched between the substrate 101 and the substrate 301. Note that for each component included in the display device DSP1B in Fig. 27 from the substrate 101 to the insulating layer 115 and the conductive layer 135, the description of the display device DSP1A in Fig. 23 can be referred to unless otherwise specified.

[0547] For example, the display device DSP1B can display an image by transmitting light from a backlight (not shown) serving as a light source through liquid crystal elements 300a to 300c (described later). For this reason, it is preferable to use, for the substrate 101 and the substrate 301, a substrate having high transparency to visible light among substrates applicable to the substrate 101 of the display device DSP1A described in FIG.

[0548] An insulating layer 381 and an insulating layer 311 are formed in this order over the insulating layer 115 and the conductive layer 135. Note that the description of the insulating layer 281 can be referred to for the insulating layer 381, and the description of the insulating layer 211 can be referred to for the insulating layer 311.

[0549] Liquid crystal elements 300 a to 300 c are provided over the insulating layer 311 .

[0550] 27, a liquid crystal element 300a serving as a display element includes a conductive layer 331a functioning as a first electrode, a conductive layer 332 functioning as a second electrode, and a liquid crystal layer 302. Similarly, a liquid crystal element 300b includes a conductive layer 331b functioning as a first electrode, a conductive layer 332 functioning as a second electrode, and a liquid crystal layer 302, and also includes a conductive layer 331c functioning as a first electrode, the conductive layer 332 functioning as a second electrode, and the liquid crystal layer 302.

[0551] Hereinafter, the liquid crystal elements 300a to 300c will be collectively referred to as the liquid crystal element 300.

[0552] The conductive layer 331 a is connected to the conductive layer 135 embedded in the insulating layer 115 through an opening provided in the insulating layer 311 .

[0553] The display device DSP1B also includes insulating layers 307 and 308, which function as alignment films, to sandwich the liquid crystal layer 302. The conductive layer 332 is provided on the substrate 301 side, and the conductive layers 331a to 331c and the conductive layer 332 overlap with each other with the liquid crystal layer 302 interposed therebetween. The liquid crystal layer 302 is sealed with a sealant 304, which functions to bond the substrate 101 side and the substrate 301 side. The transistor 100x provided in the display region DIS is connected to the liquid crystal element 300.

[0554] The conductive layers 331a to 331c and the conductive layer 332 are preferably formed using a conductive material that transmits visible light. Examples of the conductive material include a material containing one or more selected from indium (In), zinc (Zn), and tin (Sn). Specific examples include indium oxide, indium tin oxide (ITO), indium zinc oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium tin oxide containing silicon oxide (ITSO), zinc oxide, and zinc oxide containing gallium. Note that the conductive layers 331a to 331c and the conductive layer 332 can be formed using a film containing graphene. The film containing graphene can be formed by reducing a film containing graphene oxide formed over a film of an insulator, a conductor, or the like.

[0555] Further, for each of the insulating layers 111 to 113, the insulating layer 161, the conductive layers 131 to 133, the semiconductor layer 151, the insulating layer 181, the insulating layer 114, the insulating layer 182, the insulating layer 115, the insulating layer 281, the insulating layer 211, the conductive layer 135, and the conductive layer 134 described in the display device DSP1A in FIG. 23 and the transistor 100 in FIG. 24, a highly light-transmitting material is preferably used so that light from a backlight (not shown) serving as a light source can pass through.

[0556] The liquid crystal element 300 may be, for example, a liquid crystal element to which an FFS (Fringe Field Switching) mode is applied. Generally, liquid crystal materials are classified into positive-type liquid crystal materials in which the anisotropy (Δε) of the dielectric constant is positive, and negative-type liquid crystal materials in which the anisotropy (Δε) of the dielectric constant is negative. Both types of materials can be applied to the liquid crystal element 300 shown in this embodiment, and an optimal liquid crystal material can be used depending on the applied mode and design.

[0557] In the display device described in this embodiment, it is preferable to use a negative liquid crystal material. Negative liquid crystals can suppress the influence of the flexoelectric effect caused by the polarization of liquid crystal molecules, and there is almost no difference in transmittance due to polarity. Therefore, it is possible to suppress flicker from being visible to users of the display device. The flexoelectric effect is a phenomenon that is mainly caused by molecular shape and causes polarization due to orientation distortion. Negative liquid crystal materials are less likely to cause orientation distortion due to spreading deformation and bending deformation.

[0558] Although an element to which the FFS mode is applied is used as the liquid crystal element 300 here, the present invention is not limited to this, and liquid crystal elements to which various modes are applied can be used. For example, a liquid crystal element to which a VA (Vertical Alignment) mode, a TN (Twisted Nematic) mode, an IPS (In-Plane-Switching) mode, an ASM (Axially Symmetric Aligned Micro-cell) mode, an OCB (Opticaly Compensated Birefringence) mode, an FLC (Ferroelectric Liquid Crystal) mode, an AFLC (AntiFerroelectric Liquid Crystal) mode, an ECB (Electrically Controlled Birefringence) mode, a VA-IPS mode, a guest-host mode, or the like is applied can be used.

[0559] The display device described in this embodiment may be a normally black liquid crystal display device, for example, a transmissive liquid crystal display device employing a vertical alignment (VA) mode. As the vertical alignment mode, a multi-domain vertical alignment (MVA) mode, a patterned vertical alignment (PVA) mode, an advanced super view (ASV) mode, or the like may be used.

[0560] A liquid crystal element is an element that controls the transmission or non-transmission of light by the optical modulation action of the liquid crystal. The optical modulation action of the liquid crystal is controlled by an electric field (including a horizontal electric field, a vertical electric field, or an oblique electric field) applied to the liquid crystal. Liquid crystals that can be used in liquid crystal elements include thermotropic liquid crystals, low-molecular-weight liquid crystals, polymer liquid crystals, polymer-dispersed liquid crystals (PDLC: Polymer Dispersed Liquid Crystal), ferroelectric liquid crystals, and antiferroelectric liquid crystals. These liquid crystal materials exhibit cholesteric phases, smectic phases, cubic phases, chiral nematic phases, isotropic phases, and the like, depending on the conditions.

[0561] Although FIG. 27 illustrates an example of a display device having a vertical-field liquid crystal element, a display device having a horizontal-field liquid crystal element can also be used in one embodiment of the present invention. When the horizontal-field mode is employed, a liquid crystal exhibiting a blue phase without an alignment film may be used. The blue phase is a liquid crystal phase that appears immediately before a cholesteric liquid crystal transitions from a cholesteric phase to an isotropic phase as the temperature of the liquid crystal increases. Because the blue phase appears only within a narrow temperature range, a liquid crystal composition containing 5 wt % or more of a chiral dopant is used for the liquid crystal layer 302 to improve the temperature range. A liquid crystal composition containing a liquid crystal exhibiting a blue phase and a chiral dopant has a short response time and optical isotropy. Furthermore, a liquid crystal composition containing a liquid crystal exhibiting a blue phase and a chiral dopant does not require an alignment treatment and has low viewing angle dependence. Furthermore, since an alignment film is not required, a rubbing treatment is also unnecessary. This can prevent electrostatic breakdown caused by the rubbing treatment and reduce defects or damage to the liquid crystal display device during the manufacturing process.

[0562] The spacers 303 are columnar spacers obtained by selectively etching an insulating layer, and are provided to control the distance (cell gap) between the conductive layers 331a to 331c and the conductive layer 332. Note that spherical spacers may also be used.

[0563] Furthermore, optical components (optical substrates) such as a black matrix (light-shielding layer), a colored layer (color filter), a polarizing component, a retardation component, and an anti-reflection component may be appropriately provided as needed. For example, circularly polarized light produced by a polarizing substrate and a retardation substrate may be used. A backlight unit, a sidelight unit, or the like may be used as the light source (not shown). Micro LEDs or the like may be used as the backlight unit and the sidelight unit. In the case of the display device DSP1B of FIG. 27 , for example, a polarizing substrate is preferably provided on the front side of the substrate 301 (the side opposite to the side on which the colored layer 306R, the colored layer 306G, the colored layer 306B, and the light-shielding layer 305 are provided) and on the back side of the substrate 101 (the side opposite to the side on which the transistors 100x and 100y are provided), and a backlight unit is preferably provided on the back side of the substrate 101 via the polarizing substrate (not shown).

[0564] In the display device shown in FIG. 27, a light-shielding layer 305 , colored layers 306 R, 306 G, and 306 B, and an insulating layer 312 are provided between a substrate 301 and a conductive layer 332 .

[0565] Materials that can be used for the light-shielding layer 305 include carbon black, titanium black, metals, metal oxides, and composite oxides including solid solutions of multiple metal oxides. The light-shielding layer may be a film containing a resin material or a thin film of an inorganic material such as a metal. The light-shielding layer 305 may also be a laminated film of films containing one of the materials of the colored layers 306R to 306B. For example, a laminated structure may be used in which a film containing the material used for the colored layer 306R that transmits light of one color and a film containing the material used for the colored layer 306G that transmits light of another color. Using a common material for the colored layers 306R to 306B and the light-shielding layer 305 allows for the use of common equipment and simplifies the process, which is preferable.

[0566] Materials that can be used for the colored layers 306R to 306B include metal materials, resin materials, and resin materials containing pigments or dyes. The light-shielding layer and the colored layers may be formed in the same manner as the above-described methods for forming each layer. For example, they may be formed by an inkjet method or the like.

[0567] The insulating layer 312 is preferably an overcoat having a planarizing function. The planarizing function of the insulating layer 312 allows a flat insulating film to be formed on the surface on which the colored layers 306R to 306B and the light-shielding layer 305, each having a different thickness, are formed. The planarization of the insulating layer 312 allows the conductive layer 332 to be formed flat, thereby reducing variations in the thickness of the liquid crystal layer 302. Examples of such an insulating layer 312 include an acrylic resin.

[0568] <Second Cross-Sectional Configuration Example of Display Device> Next, a configuration example in a cross-section of the display device DSP2 shown in FIG. 21B will be described.

[0569] The display device DSP2A shown in Fig. 28 is a cross-sectional configuration example of the display device DSP2 shown in Fig. 21B. The display device DSP2A has a configuration in which pixel circuits, drive circuits, etc. are provided on a substrate 401. Note that the display device DSP2A in Fig. 28 also shows a wiring area LIN in addition to the circuit area SIC and display area DIS shown in Fig. 21B.

[0570] The circuit region SIC includes, for example, a substrate 401 on which a transistor 400d is formed. A wiring region LIN is provided above the transistor 400d, and wiring is provided in the wiring region LIN to connect the transistor 400d, a transistor 500x (described later), the light-emitting device 200R, the light-emitting device 200G, or the light-emitting device 200B. A display region DIS is provided above the wiring region LIN, and the display region DIS includes, for example, the transistor 500x and the light-emitting device 200 (in FIG. 28 , the light-emitting device 200R, the light-emitting device 200G, and the light-emitting device 200B).

[0571] That is, the transistor 400d can be a transistor included in the circuit region SIC. The transistor 500x can be a transistor included in the pixel circuit PX shown in each of Figures 17A to 20. For example, the transistor 500x can be the transistor Tr2 included in the pixel circuit PX. The light-emitting device 200 can be a light-emitting device included in the pixel circuit PX.

[0572] Furthermore, for the light-emitting devices 200 (light-emitting devices 200R, 200G, and 200B in FIG. 28) located above the transistor 500x, the description of the light-emitting device 200 in FIG. 23 can be referred to.

[0573] The substrate 401 can be, for example, a substrate that can be used for the substrate BS. In this embodiment, the substrate 401 will be described as a semiconductor substrate made of silicon. Therefore, the transistors included in the circuit region SIC can be Si transistors. For example, Si transistors include transistors whose channel formation region includes single crystal silicon or transistors whose channel formation region includes low-temperature polysilicon (LTPS).

[0574] Therefore, the transistor 400d formed on the substrate 401 has a structure different from that of the transistor 100x and the transistor 100y shown in Fig. 23. Note that in the display device DSP2A of Fig. 28, the transistors included in the circuit region SIC may be the transistor 100x and the transistor 100y shown in Fig. 23.

[0575] For the screen ratio (aspect ratio) of the display device DSP2A, the description of the screen ratio of the display device DSP1A can be referred to. Also, for the diagonal size of the display device DSP2A, the description of the diagonal size of the display device DSP1A can be referred to.

[0576] The transistor 400d includes an element isolation layer 402, a conductive layer 431, an insulating layer 461, an insulating layer 411, a semiconductor region 471 formed of part of the substrate 401, and low-resistance regions 472a and 472b that function as source and drain regions. Therefore, the transistor 400d is a Si transistor. Note that although FIG. 28 illustrates a structure in which one of the source and drain of the transistor 400d is connected to a conductive layer 433 and a conductive layer 434, which will be described later, via a conductive layer 432, which will be described later, the electrical connection structure of the display device of one embodiment of the present invention is not limited thereto. In the display device of one embodiment of the present invention, for example, the gate of the transistor 400d may be connected to the conductive layer 432.

[0577] The transistor 400d can be a Fin-type transistor by, for example, configuring the upper surface and side surfaces in the channel width direction of the semiconductor region 471 to be covered with the conductive layer 431 via the insulating layer 461 that functions as a gate insulating film. FIG. 29 is a cross-sectional view of the Fin-type transistor 400 in the channel width direction. As shown in FIG. 29, the upper surface and side surfaces in the channel width direction of the semiconductor region 471 are covered with the conductive layer 431 via the insulating layer 461. By configuring the transistor 400d as a Fin-type transistor, the effective channel width can be increased, thereby improving the on-state characteristics of the transistor 400d. Furthermore, the contribution of the electric field of the gate electrode can be increased, thereby improving the off-state characteristics of the transistor 400d. The transistor 400d may be a planar type transistor instead of a Fin-type transistor.

[0578] Note that the transistor 400d can be a p-channel transistor or an n-channel transistor. Alternatively, a plurality of transistors 400d may be provided and both p-channel transistors and n-channel transistors may be used.

[0579] The region where the channel of the semiconductor region 471 is formed, the region nearby, and the low-resistance region 472a and the low-resistance region 472b that become the source region or drain region preferably contain a silicon-based semiconductor, specifically, single-crystal silicon. Alternatively, each of the above-mentioned regions may be formed using, for example, germanium, silicon germanium, gallium arsenide, aluminum gallium arsenide, or gallium nitride. Alternatively, a configuration using silicon in which the effective mass is controlled by applying stress to the crystal lattice and changing the lattice spacing may be used. Alternatively, the transistor 400d may be, for example, a high electron mobility transistor (HEMT) using gallium arsenide and aluminum gallium arsenide.

[0580] The conductive layer 431 functioning as a gate electrode can be made of a semiconductor material such as silicon containing an element that imparts n-type conductivity, such as arsenic or phosphorus, or an element that imparts p-type conductivity, such as boron or aluminum. Alternatively, the conductive layer 431 can be made of a conductive material such as a metal material, an alloy material, or a metal oxide material.

[0581] Since the work function is determined by the material of the conductor, the threshold voltage of the transistor can be adjusted by selecting the material of the conductor. Specifically, it is preferable to use one or both of titanium nitride and tantalum nitride as the conductor. Furthermore, in order to achieve both conductivity and embeddability, it is preferable to use one or both of tungsten and aluminum as the conductor in a stacked structure, and tungsten is particularly preferable in terms of heat resistance.

[0582] The element isolation layer 402 is provided to isolate a plurality of transistors formed on the substrate 401. The element isolation layer can be formed by, for example, a local oxidation of silicon (LOCOS) method, a shallow trench isolation (STI) method, or a mesa isolation method.

[0583] Over a transistor 400d shown in FIG. 28, an insulating layer 412 and an insulating layer 413 are stacked in this order from the substrate 401 side.

[0584] The insulating layers 412 and 413 can be formed using, for example, one or more selected from silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, aluminum oxynitride, aluminum nitride oxide, and aluminum nitride.

[0585] The insulating layer 413 may function as a planarizing film that planarizes steps caused by the insulating layer 412 and the transistor 400d covered with the insulating layer 413. For example, the top surface of the insulating layer 413 may be planarized by planarization treatment using a chemical mechanical polishing (CMP) method to improve the planarity.

[0586] A conductive layer 432 connected to the transistor 500x and the like provided above the insulating layer 413 is buried in the insulating layer 412 and the insulating layer 413. Note that the conductive layer 432 functions as a plug or a wiring. For this reason, the conductive layer 432 can be formed using a material that can be used for the conductive layer 134.

[0587] In the display device DSP2A, a wiring region LIN is provided over the transistor 400d. The wiring region LIN includes, for example, an insulating layer 481, an insulating layer 414, a conductive layer 433, an insulating layer 482, an insulating layer 415, an insulating layer 416, and a conductive layer 434.

[0588] An insulating layer 481 and an insulating layer 414 are stacked in this order over the insulating layer 413 and the conductive layer 432. An opening is formed in the insulating layer 481 and the insulating layer 414 in a region overlapping with the conductive layer 432. A conductive layer 433 is embedded in the opening.

[0589] An insulating layer 482, an insulating layer 415, and an insulating layer 416 are stacked in this order over the insulating layer 414 and the conductive layer 433. An opening is formed in the insulating layer 482, the insulating layer 415, and the insulating layer 416 in a region overlapping with the conductive layer 433. The conductive layer 434 is filled in the opening.

[0590] The conductive layer 433 and the conductive layer 434 function as a plug or a wiring connected to the transistor 400d. Note that the conductive layer 433 and the conductive layer 434 can be formed using a material similar to that of the conductive layer 432 or the conductive layer 135 described above.

[0591] Note that, for example, the insulating layers 481 and 482 are preferably made of an insulator having a barrier property against one or more selected from hydrogen, oxygen, and water, similar to the insulating layers 181 and 182. Similarly to the insulating layers 114 and 115, the insulating layers 414, 415, and 416 are preferably made of an insulator having a relatively low dielectric constant in order to reduce parasitic capacitance between wirings. The insulating layers 414, 415, and 416 function as an interlayer insulating film and a planarizing film. The insulating layers 414, 415, and 416 preferably include an insulating layer having a barrier property against one or more selected from hydrogen, oxygen, and water.

[0592] An insulating layer 511 and an insulating layer 581 are stacked in this order over the insulating layer 416 and the conductive layer 434. A transistor 500x is provided over the insulating layer 581.

[0593] The insulating layer 511 functions as a planarizing film that flattens steps caused by the transistor 400d, a plug, and the like, similarly to the insulating layers 412 and 413. For this reason, the insulating layer 511 can be formed using a material that functions as a planarizing film, similarly to the insulating layers 412 and 413.

[0594] An insulator with a relatively low dielectric constant is preferably used for the insulating layer 511. For this reason, an insulator with a relatively low dielectric constant can be used for the insulating layer 511, similar to the insulating layers 111 to 115.

[0595] The insulating layer 581 is preferably formed using an insulator having a barrier property against one or more selected from hydrogen, oxygen, and water, similar to the insulating layers 181, 182, 481, and 482. Therefore, the insulating layer 581 can be formed using an insulator having a barrier property against one or more selected from hydrogen, oxygen, and water, similar to the insulating layers 181, 182, 481, and 482.

[0596] The transistor 500x is a transistor in which an island-shaped semiconductor layer formed on an insulating layer 511 and an insulating layer 581 are used as base films, and an active layer is an island-shaped semiconductor layer formed on the base films. The gate of the transistor 500x is provided so as to surround the top surface and side surfaces of a portion of the island-shaped semiconductor layer. In FIG. 28 , a conductive layer functioning as the gate is provided on the top surface of a portion of the island-shaped semiconductor layer. A conductive layer functioning as one of the source and drain and a conductive layer functioning as the other of the source and drain are provided on another top surface of the island-shaped semiconductor layer. The conductive layer functioning as one of the source and drain and the conductive layer functioning as the other of the source and drain are provided so as to sandwich the gate.

[0597] 28 includes an island-shaped semiconductor layer and an interlayer film covering the semiconductor layer, and has an opening in the interlayer film for embedding a conductive layer having a gate function. After the opening is formed, the conductive layer is formed, so that the conductive layer is formed in a self-aligned manner within the opening. In this specification and elsewhere, the transistor 500x having a gate formed in a self-aligned manner within the opening may be referred to as a transistor with a top gate self-aligned (TGSA) structure.

[0598] In particular, in a transistor with a TGSA structure, an insulating layer functioning as a gate insulating film is formed in the opening, and then a conductive layer functioning as a gate is formed. That is, the insulating layer is located between the semiconductor layer and the conductive layer. The insulating layer functioning as a gate insulating film significantly contributes to the electrical characteristics of the transistor 500x. For example, if the insulating layer is made thicker (if the gate insulating film of the transistor 100 is made thicker), the voltage gradient between the gate of the transistor 500x and the channel formation region of the semiconductor layer can be made gentler, thereby improving the tolerance to the gate potential (sometimes referred to as the gate-source voltage or gate-drain voltage). On the other hand, if the gate insulating film of the transistor is made thinner, the change in the electric field applied from the gate to the channel formation region of the semiconductor when the gate potential is changed becomes faster, thereby increasing the driving frequency of the transistor.

[0599] 28, the transistor 500x included in the display region DIS may be the transistor 100x and the transistor 100y shown in FIG. 23. In particular, since the channel lengths of the transistors 100x and 100y are shorter than the channel length of the transistor 500x, the area of ​​the pixel circuit included in the display region DIS can be reduced. Furthermore, in the display device DSP2A of FIG. 28, if it is desired to increase the on-state current of the transistor 500x included in the display region DIS, it is preferable to change the transistor 500x to the transistor 100.

[0600] An insulating layer 583, an insulating layer 514, an insulating layer 584, an insulating layer 515, an insulating layer 281, and an insulating layer 211 are formed in this order above the transistor 500x. A conductive layer 533 is embedded in the insulating layer 583 and the insulating layer 514, and a conductive layer 534 is embedded in the insulating layer 584 and the insulating layer 515.

[0601] 23 can be referred to for the insulating layer 583 in FIG. 28 . The description of the insulating layer 181 in FIG. 23 can be referred to for the insulating layer 514 in FIG. 28 . The description of the insulating layer 114 in FIG. 23 can be referred to for the insulating layer 584 in FIG. 28 . The description of the insulating layer 182 in FIG. 23 can be referred to for the insulating layer 515 in FIG. 28 . The description of the insulating layer 115 in FIG. 23 can be referred to for the insulating layer 515 in FIG. 28 . The description of the conductive layer 134 in FIG. 23 or the conductive layer 533 in FIG. 31 (to be described later) can be referred to for the conductive layer 534 in FIG. 28 . The description of the conductive layer 135 in FIG. 23 can be referred to for the conductive layer 534 in FIG. 28 .

[0602] The transistor 500x preferably includes a metal oxide functioning as an oxide semiconductor in a channel formation region. In particular, the metal oxide is preferably indium oxide described in Embodiment 2.

[0603] 28, the circuit area SIC may include...

Claims

a first amplifier, a second amplifier, a third amplifier, a fourth amplifier, a first resistor element, a second resistor element, a third resistor element, a fourth resistor element, a fifth resistor element, a sixth resistor element, and a selector circuit; the selector circuit has a first input terminal and a second input terminal; an input terminal of the first amplifier is electrically connected to an input terminal of the second amplifier via the first resistive element; an input terminal of the second amplifier is electrically connected to an input terminal of the third amplifier via the second resistive element; an input terminal of the third amplifier is electrically connected to an input terminal of the fourth amplifier via the third resistive element; an output terminal of the first amplifier is electrically connected to an output terminal of the second amplifier via the fourth resistive element; an output terminal of the second amplifier is electrically connected to an output terminal of the third amplifier via the fifth resistive element; an output terminal of the third amplifier is electrically connected to an output terminal of the fourth amplifier via the sixth resistive element; an output terminal of the second amplifier electrically connected to the first input terminal; the output terminal of the third amplifier is electrically connected to the second input terminal; Semiconductor device. 　 In claim 1, each of the first amplifier, the second amplifier, the third amplifier, and the fourth amplifier includes a differential amplifier circuit; an input terminal of the first amplifier is a non-inverting input terminal of the differential amplifier circuit included in the first amplifier; the output terminal of the first amplifier is the output terminal of the differential amplifier circuit included in the first amplifier, an input terminal of the second amplifier is a non-inverting input terminal of the differential amplifier circuit included in the second amplifier; the output terminal of the second amplifier is the output terminal of the differential amplifier circuit included in the second amplifier, an input terminal of the third amplifier is a non-inverting input terminal of the differential amplifier circuit included in the third amplifier; the output terminal of the third amplifier is the output terminal of the differential amplifier circuit included in the third amplifier, an input terminal of the fourth amplifier is a non-inverting input terminal of the differential amplifier circuit included in the fourth amplifier; the output terminal of the fourth amplifier is the output terminal of the differential amplifier circuit included in the fourth amplifier, In each of the first amplifier, the second amplifier, the third amplifier, and the fourth amplifier, an inverting input terminal and an output terminal of the differential amplifier circuit are electrically connected to each other. Semiconductor device. 　 In claim 2, the differential amplifier circuit includes a first transistor, a second transistor, a third transistor, and a fourth transistor; one of the source and the drain of the first transistor and one of the source and the drain of the second transistor are electrically connected to a first wiring; the other of the source and the drain of the first transistor is electrically connected to one of the source and the drain of the third transistor and to an output terminal of the differential amplifier circuit; the other of the source and the drain of the second transistor is electrically connected to the gate of the first transistor, the gate of the second transistor, and one of the source and the drain of the fourth transistor; a gate of the third transistor electrically connected to a non-inverting input terminal of the differential amplifier circuit; a gate of the fourth transistor electrically connected to an inverting input terminal of the differential amplifier circuit; the other of the source or the drain of the third transistor and the other of the source or the drain of the fourth transistor are each electrically connected to a second wiring; Semiconductor device. 　 In claim 3, each of the first transistor and the second transistor is a p-channel transistor; each of the third transistor and the fourth transistor is an n-channel transistor; a channel formation region of the first transistor and a channel formation region of the second transistor each contain silicon; a channel formation region of the third transistor and a channel formation region of the fourth transistor each contain indium oxide; the third transistor and the fourth transistor are located above the first transistor and the second transistor with an insulating layer interposed therebetween; Semiconductor device. 　 In claim 1, an input terminal of the first amplifier is electrically connected to a third wiring; an input terminal of the fourth amplifier is electrically connected to a fourth wiring; the third wiring has a function as a wiring that applies a first potential as a power supply potential, the fourth wiring has a function as a wiring that applies a second potential lower than the first potential as a power supply potential; Semiconductor device. 　 In claim 5, The selector circuit has a tree-structured analog multiplexer using pass transistor logic, the analog multiplexer includes a fifth transistor, a sixth transistor, and an inverter; the fifth transistor is a p-channel transistor, the sixth transistor is an n-channel transistor, a channel formation region of the fifth transistor includes silicon; a channel formation region of the sixth transistor includes indium oxide; one of the source and the drain of the fifth transistor is electrically connected to the first input terminal; One of the source and the drain of the sixth transistor is electrically connected to the second input terminal. an output terminal of the inverter is electrically connected to a gate of the fifth transistor and a gate of the sixth transistor; Semiconductor device. 　 a driving circuit and a pixel circuit located above the driving circuit; the drive circuit includes the semiconductor device according to any one of claims 1 to 6, a fifth amplifier, and a switch; the pixel circuit includes a seventh transistor, an eighth transistor, and a light-emitting device; the selector circuit has an output terminal; an output terminal of the selector circuit electrically connected to an input terminal of the fifth amplifier; an output terminal of the fifth amplifier electrically connected to a first terminal of the switch; a second terminal of the switch electrically connected to one of the source and the drain of the seventh transistor; the other of the source and the drain of the seventh transistor is electrically connected to the gate of the eighth transistor; one of the source and the drain of the eighth transistor is electrically connected to the anode of the light emitting device; Display device. 　 In claim 7, each of the seventh transistor and the eighth transistor is an n-channel transistor; a channel formation region of the seventh transistor and a channel formation region of the eighth transistor each contain indium oxide; Display device.

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