Signal demodulator

Abstract

This signal demodulator comprises: a semiconductor layer (200) that is cylindrical and that extends in a first direction; a gate (201) that is disposed away from the semiconductor layer (200) at a location partway between one end (200a) and the other end (200b) of the semiconductor layer (200); and a semiconductor layer (202) that is cylindrical, that extends in a second direction intersecting the first direction, and that is disposed away from the other end (200b) of the semiconductor layer (200) in the first direction. A modulation signal is input into the one end (200a) of the semiconductor layer (200), and a signal obtained by demodulating the modulation signal is output from the semiconductor layer (202).

Description

signal demodulator

[0001] The present invention relates to a signal demodulator for demodulating amplitude modulated signals, amplitude shift keyed signals, frequency shift keyed signals, and the like.

[0002] In wireless communication, a signal to be transmitted is transmitted on a carrier wave. Analog modulation methods for transmitting signals include amplitude modulation (AM) and frequency modulation (FM), while digital modulation methods include amplitude shift keying (ASK) and frequency shift keying (FSK). The transmitted signal is restored to its original state by a demodulation circuit that combines discrete devices such as diodes and capacitors, and a phase-locked loop (PLL) (Non-Patent Documents 1 and 2).

[0003] In the future, as high frequencies such as the terahertz (THz) band are used as carrier waves for the purpose of transmitting large amounts of information, the difficulty of circuit design will increase. For example, when using a diode to demodulate a THz band signal, the diode's rectification characteristics cannot be maintained due to the characteristic that impedance drops in the high frequency band due to the capacitance component formed by the pn junction, and the recovery characteristics when switching from forward bias to reverse bias, limiting the usable frequency band. Furthermore, since AC signals must be transmitted, the usable frequency band is also limited by the parasitic components of the diode and the RC time constant due to wiring, etc. Furthermore, when the input signal is small, on the order of a few tens of millivolts, the rectification characteristics of the diode may not be fully utilized.

[0004] This problem may be solved by using devices made of low-dimensional materials such as carbon nanotubes and semiconductor quantum dots. However, these devices are difficult to operate at room temperature in principle, and the selection of materials depending on the signal is limited, and the device fabrication is not easy (Non-Patent Document 3).

[0005] As described above, it has been difficult for conventional signal demodulators to demodulate high frequency signals in the range of 100 GHz to THz at room temperature due to the operating principle of the device, the RC time constant, and other reasons.

[0006] Atsushi Hirohata, "Analog Design with High Frequency Sensing, Vol. 9," Transistor Technology, CQ Publishing Co., Ltd., November 2002. Shingo Katsumoto, "Electronic Circuit Theory, Vol. 12," Faculty of Science, Graduate School of Science, The University of Tokyo (Institute for Solid State Physics), 2014, <https: / / kats.issp.u-tokyo.ac.jp / kats / electroniccircuit / note12.pdf> Y. Kawano, "Terahertz Response of Carbon Nanotubes and Graphene," Journal of the Physical Society of Japan, vol. 84, 121010, 2015.

[0007] The present invention has been made to solve the above-mentioned problems, and aims to provide a signal demodulator that can demodulate a high-frequency modulated signal and can demodulate even if the intensity of the modulated signal is low.

[0008] The signal demodulator of the present invention comprises a columnar first semiconductor layer extending in a first direction, a first gate arranged at a position midway from one end of the first semiconductor layer to the other end and spaced apart from the first semiconductor layer, and a columnar second semiconductor layer extending in a second direction intersecting the first direction and spaced apart from the other end of the first semiconductor layer in the first direction, wherein a modulated signal is input to one end of the first semiconductor layer and a signal demodulated from the modulated signal is output from the second semiconductor layer.

[0009] The present invention is characterized by utilizing a steady-state process that occurs by inducing a non-equilibrium state using a leakage current-free FET configured by providing a first gate in a first semiconductor layer. The present invention is also characterized by storing a low-intensity AC signal in a capacitor between the first semiconductor layer and the second semiconductor layer, and reading out the current using another FET configured between the other end of the first semiconductor layer and the second semiconductor layer. Due to these features, the present invention is capable of demodulating modulated signals in the range of 100 GHz to 1 THz at room temperature without the frequency being limited by the RC time constant of the circuit. The present invention also enables demodulation even when the modulated signal has a low intensity.

[0010] FIG. 1A is a plan view showing the basic configuration of a signal demodulator according to the present invention. FIG. 1B is a cross-sectional view showing the basic configuration of a signal demodulator according to the present invention. FIG. 1C is an equivalent circuit diagram of a signal demodulator according to the present invention. FIGS. 2A and 2C are diagrams showing the energy band structures of semiconductor layers according to the present invention. FIG. 3 is a diagram showing the results of a simulation of the potential increase in a charge accumulation region when the frequency of an AC signal applied to an input terminal is changed. FIG. 4 is a diagram showing the results of a simulation of the change in the number of electrons in a charge accumulation region depending on the presence or absence of an AC signal. FIG. 5 is a diagram showing the results of a simulation of the change in the number of electrons in a charge accumulation region depending on the amplitude of an AC signal. FIG. 6A is a plan view showing the configuration of a signal demodulator according to a first embodiment of the present invention. FIG. 6B is a cross-sectional view showing the configuration of a signal demodulator according to the first embodiment of the present invention. FIG. 7A is a plan view showing the configuration of a signal demodulator according to a second embodiment of the present invention. FIG. 7B is a cross-sectional view showing the configuration of a signal demodulator according to the second embodiment of the present invention. FIGS. 8A and 8B are diagrams showing the electrical connections of signal demodulators according to the first and second embodiments of the present invention. FIG. 9A is a diagram showing the original binary signal of an FSK signal. 9B is a diagram showing an FSK signal, and a diagram showing the setting of an FSK frequency for demodulating an FSK signal by the signal demodulator according to the first and second embodiments of the present invention.

[0011] [Principle of the Invention] In the following explanation, electrons are assumed to be current carriers, but holes can also be used as carriers by reversing the polarity of the driving voltage. First, essential parts will be explained to explain the basic principle of the signal demodulator of the present invention. FIG. 1A is a plan view showing the basic configuration of the signal demodulator, FIG. 1B is a cross-sectional view taken along line A-A' in FIG. 1A, and FIG. 1C is an equivalent circuit diagram of FIGS. 1A and 1B. Note that FIG. 1A illustrates the semiconductor layer with a perspective view of the inside of the insulating layer, which will be described later.

[0012] The signal demodulator of the present invention is basically configured with a field effect transistor (FET) Q1 consisting of a semiconductor layer 100 and a gate 101. The semiconductor layer 100 is columnar and extends in a first direction (left-right direction in FIGS. 1A and 1B ), and a channel through which carriers flow is formed. The gate 101 is disposed at a position midway from one end 100a to the other end 100b of the semiconductor layer 100, spaced apart from the semiconductor layer 100, and applies a gate voltage to the semiconductor layer 100. The gate 101 is formed on an insulating layer 102 formed on the semiconductor layer 100.

[0013] One end 100a of the semiconductor layer 100 (the drain of the FET Q1) is connected to the input terminal of a signal demodulator, and an AC signal is input thereto. The other end 100b of the semiconductor layer 100 (the source of the FET Q1) is not connected to anything, but has a capacitance component, so it can be considered as an equivalent circuit in which a capacitor C1 is connected, as shown in Figure 1C.

[0014] 2A, 2B, and 2C show the energy band structure of the semiconductor layer 100. Here, we consider a case where an energy barrier is formed by the gate 101, and the charge accumulation region 100c of the semiconductor layer 100, which is connected to the capacitor C1, is electrically disconnected from the input terminal 100a. Electrons in the input terminal 100a and the charge accumulation region 100c have energy (thermal energy) caused by heat and move randomly. Therefore, the energy possessed by each electron varies with respect to each Fermi level, and the probability of having that energy follows a Boltzmann distribution based on the Fermi level.

[0015] Since the Boltzmann distribution is uniquely determined by thermal energy, i.e., temperature, when no AC signal is input to the input terminal 100a, the electron energy distribution Ea in the region 100d of the semiconductor layer 100 on the input terminal 100a side and the electron energy distribution Eb in the charge accumulation region 100c have the same shape (FIG. 2A). Therefore, an equilibrium state is maintained in which the flow of electrons entering the charge accumulation region 100c from the input terminal 100a is equal to the flow of electrons entering the input terminal 100a side from the charge accumulation region 100c.

[0016] When an AC signal is applied to the input terminal 100a, the electron energy changes by the amount of the AC signal. As a result, the electron energy distribution Ea in the semiconductor layer 100 on the input terminal 100a side expands, resulting in a wider range of energy that the electrons can have. As a result, a difference in electron energy distribution occurs between the charge accumulation region 100c, which is not affected by the AC signal, and the semiconductor layer 100 on the input terminal 100a side to which the AC signal is applied, resulting in an energy non-equilibrium state. Therefore, high-energy electrons flow from the input terminal 100a side into the charge accumulation region 100c, overcoming the energy barrier created by the voltage of the gate 101. As a result, the potential of the charge accumulation region 100c increases, as shown in FIG. 2C.

[0017] When the flow of electrons from the input terminal 100a into the charge storage region 100c and the flow of electrons from the charge storage region 100c into the input terminal 100a become equal, the potential of the charge storage region 100c stops rising and a steady state is reached. In this way, by applying an AC signal to the input terminal 100a, the potential of the charge storage region 100c rises and energy is stored.

[0018] To achieve such energy storage, the time T ｅｌｅｃｔｒｏｎ (corresponding to the time constant of the current path formed by FET Q1 and capacitor C1) is the period T ａｃ The reason is that T ａｃ T ｅｌｅｃｔｒｏｎIf the distance is longer than 100 m, electrons will enter and exit the charge accumulation region 100 c in response to changes in the AC signal, and the electron energy distribution on the input terminal 100 a side will be aligned with the electron energy distribution in the charge accumulation region 100 c, preventing an unbalanced state.

[0019] Therefore, the frequency f of the AC signal required to store energy in the charge storage region 100c is ａｃ is 10 / T ｅｌｅｃｔｒｏｎ That is all. In other words, the time constant T ｅｌｅｃｔｒｏｎ The AC signal must be faster than the frequency f ａｃ If the time constant is low, the potential of the charge storage region 100c does not increase. In the conventional concept, the input signal must be slower than the time constant for a circuit or device to operate. Therefore, the AC signal conditions in this embodiment are the opposite of the conventional concept.

[0020] The frequency f of the AC signal applied to the input terminal 100a ａｃ 3 shows the simulation results of the potential rise in the charge accumulation region 100c when the frequency f of the AC signal is changed. ａｃ As the frequency f ａｃ 10 / T ｅｌｅｃｔｒｏｎ It can be seen that above this point, the potential rise saturates.

[0021] FIG. ｅｌｅｃｔｒｏｎ 4 shows the current monitoring the change in the number of electrons in the charge accumulation region 100c depending on whether or not an AC signal is applied at time = 3 seconds. In FIG. 4, 400 shows the electron count current when no AC signal is applied, and 401 shows the electron count current when an AC signal is applied. By applying an AC signal to the input terminal 100a, the electron count current is reduced overall compared to when no AC signal is applied. This reduction in current indicates an increase in the potential of the charge accumulation region 100c.

[0022] FIG. 5 shows the frequency of 10 / T ｅｌｅｃｔｒｏｎ The graph shows the change in the number of electrons in the charge accumulation region 100c when the amplitude of the AC signal is changed. Since the number of electrons increases monotonically with the amplitude of the AC signal, it can be seen that the signal amplitude is reflected in the number of electrons. In other words, when the transmission signal frequency of the AM signal is 10 / T,ｅｌｅｃｔｒｏｎ When this signal is applied to the input terminal 100a, electrons corresponding in number to the signal amplitude are accumulated in the charge accumulation region 100c, and the potential of the charge accumulation region 100c rises.

[0023] When the signal amplitude is several tens of mV, the number of electrons in the charge storage region 100c approaches zero, but this small number of electrons is due to the extremely small size of the charge storage region 100c. Therefore, by enlarging the charge storage region 100c as necessary, electrons can be stored in the charge storage region 100c even with a signal amplitude of several tens of mV.

[0024] The above description describes electrons moving in and out between the input terminal 100a and the charge storage region 100c. During this movement, the electrons must overcome an energy barrier created by the voltage of the gate 101. In other words, the operating principle of the present invention cannot be satisfied by a leakage current from the FET Q1. Furthermore, when electrons move in and out between the input terminal 100a and the charge storage region 100c, the electrons must not lose their energy due to scattering or the like.

[0025] [First embodiment] Based on the above principles, a first embodiment of the present invention will be described. Figure 6A is a plan view of the signal demodulator of this embodiment, and Figure 6B is a cross-sectional view taken along line BB' in Figure 6A. Figure 6A shows the semiconductor layer seen through the inside of the insulating layer.

[0026] The signal demodulator of this embodiment includes a columnar semiconductor layer 200 extending in a first direction (horizontal direction in FIGS. 6A and 6B ), a gate 201 disposed midway from one end of the semiconductor layer 200 to the other end and spaced apart from the semiconductor layer 200, and a columnar semiconductor layer 202 extending in a second direction (vertical direction in FIG. 6A ) intersecting the first direction and spaced apart from the other end of the semiconductor layer 200 in the first direction. The semiconductor layers 200 and 202 are embedded in an insulating layer 203. A back gate 204 is formed on the surface of the insulating layer 203 opposite the gate 201 (the lower surface in FIG. 6B ). The semiconductor layers 200 and 202 are formed of, for example, silicon, the gate 201 and back gate 204 are formed of, for example, polysilicon, and the insulating layer 203 is formed of, for example, silicon oxide.

[0027] In this embodiment, a semiconductor layer 202 is added to the basic structure of the first embodiment. The other end 200b of the semiconductor layer 200 opposite to the input terminal 200a is capacitively coupled to the semiconductor layer 202, so that the charge accumulation region 200c formed on the other end 200b side of the semiconductor layer 200 functions as a gate for the semiconductor layer 202. The semiconductor layer 202 and the other end 200b of the semiconductor layer 200 constitute a FET.

[0028] When a modulation signal such as an AM signal or an ASK signal is applied to the input terminal 200a, the potential (number of electrons) of the charge accumulation region 200c changes, and this change is applied as a gate voltage to the semiconductor layer 202, causing a change in the DC current I flowing through the semiconductor layer 202. In other words, the modulation signal is converted into a DC current in the semiconductor layer 202, and a demodulated signal can be obtained by reading out this DC current. According to this embodiment, demodulation is possible even if the intensity of the modulation signal is low.

[0029] Next, the structure required for this embodiment will be described. The shorter the distance between the charge accumulation region 200c and the semiconductor layer 202, the more accurately the demodulated signal can be read out. It is also desirable that the width (vertical direction in FIG. 6A ) and thickness (vertical direction in FIG. 6B ) of the semiconductor layer 200 be small. Similarly, it is also desirable that the width (horizontal direction in FIG. 6A ) and thickness (vertical direction in FIG. 6B ) of the semiconductor layer 202 be small.

[0030] For example, the distance between the charge accumulation region 200c and the semiconductor layer 202 is set to 50 nm or less, the width and thickness of the semiconductor layers 200 and 202 are set to 10 nm or less, and the length of the charge accumulation region 200c (left and right directions in FIGS. 6A and 6B) is set to 100 nm or less. With this configuration, even a change of just one electron in the number of electrons in the charge accumulation region 200c can be detected as a change in current in the semiconductor layer 202 (see K. Nishiguchi et al., "Single-Electron-Resolution Electrometer Based on Field-Effect Transistor," Japanese Journal of Applied Physics, vol. 47, no. 11, pp. 8305-8310, 2008).

[0031] As a result, electrons entering and leaving the charge accumulation region 200c can be monitored with high sensitivity at the single-electron level, as shown in Fig. 4. Note that although the current changes stepwise in Fig. 4, the amount of potential change in the charge accumulation region 200c can be obtained by taking the time average.

[0032] Furthermore, in this embodiment, by providing a back gate 204, the potential of the charge accumulation region 200c can be precisely controlled by the gate 201 and the back gate 204. Furthermore, by using the back gate 204 to induce carriers in the semiconductor layer 200, carrier conduction can be achieved without introducing impurities into the semiconductor layer 200. For example, applying a positive voltage to the semiconductor layer 200 using the back gate 204 induces electrons in the semiconductor layer 200. Generally, in a FET, impurities are introduced into the source and drain to conduct carriers between them. However, during the process of introducing these impurities, crystalline defects occur in the semiconductor layer (channel), causing leakage current such as GIDL (Gate Induced Drain Leakage). Using the back gate 204 also makes it possible to suppress leakage current. However, the back gate 204 is not an essential component of the present invention, and the back gate 204 may not be provided.

[0033] Second Embodiment Next, a second embodiment of the present invention will be described. Fig. 7A is a plan view of the signal demodulator of this embodiment, and Fig. 7B is a cross-sectional view taken along line BB' in Fig. 7A. Fig. 7A shows the semiconductor layer seen through the inside of the insulating layer.

[0034] In this embodiment, a gate 205 is newly formed on the surface of the insulating layer 203 above the charge accumulation region 200c, in contrast to the signal demodulator of the first embodiment. According to this embodiment, the potential of the charge accumulation region 200c of the semiconductor layer 200 can be precisely controlled by the gate 205 and the back gate 204. Furthermore, when a modulated signal input to the input terminal 200a propagates through space, the gate 205 can function as a shield against this propagated signal. This makes it possible to prevent the propagated signal from affecting the charge accumulation region 200c.

[0035] [Third embodiment] Next, as a third embodiment of the present invention, a method for demodulating an FSK signal in the structure shown in the first and second embodiments will be described. The electrical connections of the signal demodulator of this embodiment are shown in Figures 8A and 8B. In Figures 8A and 8B, 300 indicates a gate voltage V Ｇ１ 301 is a DC variable power supply that supplies a gate voltage V Ｇ２ 302 supplies a gate voltage V ＢＧ A DC variable power supply 303 supplies a voltage V Ｄ It is a variable DC power supply that supplies

[0036] For example, the gate voltage V supplied to the gate 201 Ｇ１ An energy barrier is formed by the gate voltage V supplied to the gate 205. Ｇ２ and the gate voltage V supplied to the back gate 204 ＢＧ The potential of the charge accumulation region 200c is controlled by the back gate 204 and the DC variable power supply 302. As described in the first embodiment, the back gate 204 and the DC variable power supply 302 may be omitted. 8A and 8B show the electrical connections in the second embodiment, but it goes without saying that the first embodiment does not require the gate 205 and the DC variable power supply 301.

[0037] The FSK signal is obtained by modulating the frequency as shown in Fig. 9B in accordance with the binary signal shown in Fig. 9A. For example, when the original binary signal is "0", the frequency of the FSK signal is f0, and when the binary signal is "1", the frequency of the FSK signal is f1. The FSK signal V with these frequencies f0 and f1 set as shown in Fig. 10 is ＩＮ is applied to the input terminal 200a, the FSK signal V ＩＮ When the frequency of the FSK signal V is f0 (the binary signal is "0"), the potential of the charge storage region 200c becomes almost zero. ＩＮ When the frequency of the charge accumulation region 200c is f1 (the binary signal is "1"), the potential of the charge accumulation region 200c rises. Therefore, by reading out the current I from the other end 200b of the semiconductor layer 202, the original binary signal can be obtained.

[0038] Some or all of the above embodiments can be described as, but are not limited to, the following supplementary notes.

[0039] (Supplementary Note 1) A signal demodulator of the present invention comprises a columnar first semiconductor layer extending in a first direction, a first gate arranged at a position midway from one end of the first semiconductor layer to the other end and spaced apart from the first semiconductor layer, and a columnar second semiconductor layer extending in a second direction intersecting the first direction and spaced apart from the other end of the first semiconductor layer in the first direction, wherein a modulated signal is input to one end of the first semiconductor layer and a signal demodulated from the modulated signal is output from the second semiconductor layer.

[0040] (Supplementary Note 2) The signal demodulator according to Supplementary Note 1 further includes a back gate arranged on the opposite side of the first gate with the first semiconductor layer therebetween, spaced apart from the first and second semiconductor layers.

[0041] (Supplementary Note 3) The signal demodulator according to Supplementary Note 1 further comprises a second gate arranged above a charge accumulation region formed on the other end side of the first semiconductor layer and spaced apart from the first semiconductor layer.

[0042] (Supplementary Note 4) The signal demodulator according to Supplementary Note 3 further includes a back gate arranged on the opposite side of the first and second gates, with the first semiconductor layer sandwiched therebetween, and spaced apart from the first and second semiconductor layers.

[0043] (Supplementary Note 5) The signal demodulator described in Supplementary Note 1 further includes a first DC power supply configured to supply a voltage to the first gate and a second DC power supply configured to supply a voltage to one end of the second semiconductor layer, and a signal demodulated from the modulated signal is output from the other end of the second semiconductor layer.

[0044] (Supplementary Note 6) The signal demodulator described in Supplementary Note 5 further includes a back gate arranged on the opposite side of the first gate with the first semiconductor layer therebetween and spaced apart from the first and second semiconductor layers, and a third DC power supply configured to supply a voltage to the back gate.

[0045] (Supplementary Note 7) The signal demodulator described in Supplementary Note 3 further includes a first DC power supply configured to supply a voltage to the first gate, a second DC power supply configured to supply a voltage to the second gate, and a third DC power supply configured to supply a voltage to one end of the second semiconductor layer, and a signal demodulated from the modulated signal is output from the other end of the second semiconductor layer.

[0046] (Supplementary Note 8) The signal demodulator described in Supplementary Note 7 further includes a back gate arranged on the opposite side of the first and second gates with the first semiconductor layer therebetween and spaced apart from the first and second semiconductor layers, and a fourth DC power supply configured to supply a voltage to the back gate.

[0047] The present invention can be applied to a technique for demodulating a modulated signal.

[0048] 100, 200, 202...semiconductor layers, 101, 201, 205...gates, 102, 203...insulating layers, 204...back gates, 100c, 200c...charge storage regions, 300 to 303...DC variable power supplies.

Claims

1. A signal demodulator comprising: a columnar first semiconductor layer extending in a first direction; a first gate disposed midway from one end of the first semiconductor layer to the other end and spaced apart from the first semiconductor layer; and a columnar second semiconductor layer extending in a second direction intersecting the first direction and spaced apart from the other end of the first semiconductor layer in the first direction; wherein a modulated signal is input to one end of the first semiconductor layer; and a signal demodulated from the modulated signal is output from the second semiconductor layer.

2. A signal demodulator according to claim 1, further comprising a back gate arranged at a distance from the first and second semiconductor layers on the opposite side of the first gate with the first semiconductor layer sandwiched therebetween.

3. A signal demodulator according to claim 1, further comprising a second gate arranged above a charge accumulation region formed on the other end side of said first semiconductor layer and spaced apart from said first semiconductor layer.

4. A signal demodulator according to claim 3, further comprising a back gate arranged at a distance from said first and second semiconductor layers on the opposite side of said first and second gates with said first semiconductor layer sandwiched therebetween.

5. A signal demodulator according to claim 1, further comprising a first DC power supply configured to supply a voltage to the first gate, and a second DC power supply configured to supply a voltage to one end of the second semiconductor layer, wherein a signal obtained by demodulating the modulated signal is output from the other end of the second semiconductor layer.

6. A signal demodulator according to claim 5, further comprising: a back gate disposed on the opposite side of the first gate with the first semiconductor layer interposed therebetween and spaced apart from the first and second semiconductor layers; and a third DC power supply configured to supply a voltage to the back gate.

7. A signal demodulator according to claim 3, further comprising a first DC power supply configured to supply a voltage to the first gate, a second DC power supply configured to supply a voltage to the second gate, and a third DC power supply configured to supply a voltage to one end of the second semiconductor layer, wherein a signal demodulated from the modulated signal is output from the other end of the second semiconductor layer.

8. A signal demodulator according to claim 7, further comprising: a back gate arranged on the opposite side of the first and second gates with the first semiconductor layer interposed therebetween and spaced apart from the first and second semiconductor layers; and a fourth DC power supply configured to supply a voltage to the back gate.

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