Semiconductor memory device

Abstract

Active regions (P1-P4) having configured therein drive transistors (PU1, PU2) and access transistors (PG1-PG4), which are P-type transistors, are formed in a lower part of a cell. Active regions (P1-P4) having configured therein load transistors (PD1, PD2), which are N-type transistors, are formed in an upper part of the cell. Power supply wiring (11) for supplying a first power supply voltage is formed in a back wiring layer.

Description

semiconductor memory device

[0001] The present disclosure relates to a layout structure of a static random access memory (SRAM) cell (hereinafter, also simply referred to as a cell, as appropriate) using a complementary field effect transistor (CFET).

[0002] SRAMs are widely used in semiconductor integrated circuits, and include dual-port SRAMs that have two ports for reading and writing data.

[0003] Furthermore, transistors, which are fundamental components of LSIs, have achieved improved integration density, reduced operating voltages, and improved operating speeds through the reduction of gate length (scaling). However, in recent years, excessive scaling has led to problems with off-state current and the resulting significant increase in power consumption. To solve this problem, three-dimensional transistors, which change the transistor structure from the conventional planar type to a three-dimensional type, have been actively researched. Nanosheet FETs are one type of three-dimensional transistor that has attracted attention.

[0004] Patent Document 1 discloses a layout of a two-port SRAM cell using a CFET in which a P-type nanosheet transistor and an N-type nanosheet transistor are stacked on a substrate.

[0005] International Publication No. 2020 / 246344

[0006] In the technology of Patent Document 1, the bit lines and power supply lines are provided separately in the buried wiring layer and the upper wiring layer, thereby increasing the wiring width of the wiring provided in the upper wiring layer, but the wiring in the buried wiring layer cannot be provided overlapping with the transistor (nanosheet). Therefore, the wiring width of the wiring formed in the buried wiring layer cannot be increased, so the wiring resistance of the wiring increases and the operating speed of the semiconductor memory device decreases.

[0007] In addition, P-type nanosheet transistors and N-type nanosheet transistors are mixed in at least one of the layers in the lower and upper parts of the cell. This complicates the manufacturing process of the semiconductor memory device, increasing manufacturing costs. Furthermore, since the P-type nanosheet transistors and the N-type nanosheet transistors must be spaced apart, the area of ​​the semiconductor memory device increases.

[0008] The present disclosure aims to improve the operating speed of a semiconductor memory device, reduce manufacturing costs, and reduce the area of ​​the semiconductor memory device in a layout structure of an SRAM cell using a CFET.

[0009] In a first aspect of the present disclosure, there is provided a semiconductor memory device including an SRAM cell, the SRAM cell comprising: a first transistor having a source connected to a first power supply that supplies a first power supply voltage, a drain connected to a first node, and a gate connected to a second node; a second transistor having a source connected to the first power supply, a drain connected to the second node, and a gate connected to the first node; a third transistor having a source connected to a first bit line, a drain connected to the first node, and a gate connected to a first word line; and a second bipolar transistor having a source connected to the first bit line and forming a first complementary bit line pair with the first bit line. a fourth transistor having a source connected to a third bit line, a drain connected to the first node, and a gate connected to the first word line; a fifth transistor having a source connected to a third bit line, a drain connected to the first node, and a gate connected to the second word line; a sixth transistor having a source connected to a fourth bit line forming a second complementary bit line pair with the third bit line, a drain connected to the second node, and a gate connected to the second word line; a sixth transistor having a source connected to a second power supply that supplies a second power supply voltage different from the first power supply voltage, a drain connected to the first node, and a gate connected to the second node; and an eighth transistor having a source connected to the second power supply, a drain connected to the second node, and a gate connected to the first node, wherein the first to sixth transistors are transistors of a first conductivity type, and the seventh and eighth transistors are transistors of a second conductivity type different from the first conductivity type; the SRAM cell comprises a channel, a source, and a drain of the third transistor, the channel of which comprises a third nanosheet extending in a first direction, and a channel, a source, and a drain of the fifth transistor, the channel of which comprises a first active region including the fifth nanosheet extending in the first direction, the channel of which comprises the channel, the source, and drain of the first transistor, a second active region including the first nanosheet extending in the first direction, the channel of which comprises the channel, the source, and drain of the second transistor, and a third active region including the second nanosheet extending in the first direction, the channel of which comprises the channel, the source, and drain of the fourth transistor;a fourth active region including a fourth nanosheet extending in the first direction as the channel and constituting the channel, source, and drain of the sixth transistor and including the sixth nanosheet extending in the first direction as the channel; a fifth active region formed higher than the first to fourth active regions in the depth direction and constituting the channel, source, and drain of the seventh transistor and including the seventh nanosheet extending in the first direction as the channel; a sixth active region formed higher than the first to fourth active regions in the depth direction and constituting the channel, source, and drain of the eighth transistor and including the eighth nanosheet extending in the first direction as the channel; the first and seventh nanosheets are formed in a backside wiring layer, which is a wiring layer of the first active region, extending in the first direction and overlapping with the second and third active regions in a planar view, and including a first power supply wiring connected to the first power supply, a first via formed in a region where a region in the second active region that becomes the source of the first transistor and the first power supply wiring overlap, and connecting the source of the first transistor in the second active region and the first power supply wiring, and a second via formed in a region where a region in the third active region that becomes the source of the second transistor and the first power supply wiring overlap, and connecting the source of the second transistor in the third active region and the first power supply wiring, wherein the first and seventh nanosheets overlap in a planar view, and the second and eighth nanosheets overlap in a planar view.

[0010] According to the present disclosure, a first power supply wiring for supplying a first power supply voltage is formed in a back wiring layer, which is a wiring layer on the back side of the first to eighth transistors. The power supply wiring overlaps the second and third active regions in a planar view and is connected to each other through vias provided in the overlapping regions. Therefore, the active regions (transistors) and the power supply wiring can be arranged overlapping each other, thereby increasing the wiring width of the first power supply wiring for supplying the first power supply voltage and reducing the wiring resistance of the power supply wiring. This improves the operating speed and stability of the semiconductor memory device. Furthermore, the fifth and sixth active regions are formed higher in the depth direction than the first to fourth active regions. This allows a first conductivity type transistor to be formed in the lower part of the cell and a second conductivity type transistor to be formed in the upper part of the cell, thereby reducing the complexity of the manufacturing process of the semiconductor memory device and reducing manufacturing costs. Furthermore, since it is not necessary to space the first conductivity type transistor and the second conductivity type transistor apart, the area of ​​the semiconductor memory device can be reduced.

[0011] A second aspect of the present disclosure is a semiconductor memory device including an SRAM cell, the SRAM cell comprising a first transistor having a source connected to a first power supply that supplies a first power supply voltage, a drain connected to a first node, and a gate connected to a second node; a second transistor having a source connected to the first power supply, a drain connected to the second node, and a gate connected to the first node; a third transistor having a source connected to a first bit line, a drain connected to the first node, and a gate connected to a first word line; and a second bit line having a source connected to a second word line that forms a first complementary bit line pair with the first bit line. a fourth transistor having a source connected to a third bit line, a drain connected to the first node, and a gate connected to the first word line; a fifth transistor having a source connected to a third bit line, a drain connected to the first node, and a gate connected to the second word line; a sixth transistor having a source connected to a fourth bit line forming a second complementary bit line pair with the third bit line, a drain connected to the second node, and a gate connected to the second word line; a sixth transistor having a source connected to a second power supply that supplies a second power supply voltage different from the first power supply voltage, a drain connected to the first node, and a gate connected to the second node; a seventh transistor connected to the first power supply, a drain connected to the second node, and a gate connected to the first node, wherein the first and second transistors are transistors of a first conductivity type, and the fifth to eighth transistors are transistors of a second conductivity type different from the first conductivity type; the SRAM cell comprises: a first active region constituting the channel, source, and drain of the first transistor and including a first nanosheet extending in a first direction as the channel; a second active region constituting the channel, source, and drain of the second transistor and including a second nanosheet extending in the first direction as the channel; a third active region formed above the first and second active regions in the depth direction and constituting the channel, source, and drain of the third transistor and including a third nanosheet extending in the first direction as the channel; and a third active region constituting the channel, source, and drain of the fifth transistor and including a fifth nanosheet extending in the first direction as the channel;a fourth active region formed above the first and second active regions in the depth direction, constituting the channel, source, and drain of the seventh transistor, the channel including a seventh nanosheet extending in the first direction; a fifth active region formed above the first and second active regions in the depth direction, constituting the channel, source, and drain of the eighth transistor, the channel including an eighth nanosheet extending in the first direction; and a fifth active region formed above the first and second active regions in the depth direction, constituting the channel, source, and drain of the fourth transistor, the channel including a fourth nanosheet extending in the first direction, and the channel including a fourth nanosheet extending in the first direction. the sixth active region including a sixth nanosheet extending in the first direction; a first power supply wiring formed in a back wiring layer that is a wiring layer on the back side of the first to eighth transistors, extending in the first direction and overlapping with the first and second active regions in a plan view, and connected to the first power supply; a first via formed in a region where a region in the first active region that becomes the source of the first transistor and the first power supply wiring overlap, connecting the source of the first transistor in the first active region and the first power supply wiring; and a second via formed in a region in the second active region where a region in the second active region that becomes the source of the second transistor and the first power supply wiring overlap, connecting the source of the second transistor in the second active region and the first power supply wiring, wherein the first and seventh nanosheets overlap in a plan view.

[0012] According to the present disclosure, a first power supply wiring for supplying a first power supply voltage is formed in a back wiring layer, which is a wiring layer on the back side of the first to eighth transistors. The power supply wiring overlaps the second and third active regions in a planar view and is connected to each other through vias provided in the overlapping regions. Therefore, since the active regions (transistors) and the power supply wiring can be arranged overlapping each other, the wiring width of the first power supply wiring for supplying the first power supply voltage can be increased, thereby reducing the wiring resistance of the power supply wiring. This improves the operating speed and operational stability of the semiconductor memory device. Furthermore, the third to sixth active regions are formed higher in the depth direction than the first and second active regions. This allows a first conductivity type transistor to be formed in the lower part of the cell and a second conductivity type transistor to be formed in the upper part of the cell, thereby reducing the complexity of the manufacturing process of the semiconductor memory device and reducing manufacturing costs. Furthermore, since it is not necessary to space the first conductivity type transistor and the second conductivity type transistor apart, the area of ​​the semiconductor memory device can be reduced.

[0013] A third aspect of the present disclosure is a semiconductor memory device including an SRAM cell, the SRAM cell comprising: a first transistor having a source connected to a first power supply that supplies a first power supply voltage, a drain connected to a first node, and a gate connected to a second node; a second transistor having a source connected to the first power supply, a drain connected to the second node, and a gate connected to the first node; a third transistor having a source connected to a first bit line, a drain connected to the first node, and a gate connected to a first word line; and a second transistor having a source connected to the first bit line and a second word line that forms a first complementary bit line pair with the first bit line. a fourth transistor having a source connected to a bit line, a drain connected to the second node, and a gate connected to the first word line; a fifth transistor having a source connected to a third bit line, a drain connected to the first node, and a gate connected to the second word line; a sixth transistor having a source connected to a fourth bit line forming a second complementary bit line pair with the third bit line, a drain connected to the second node, and a gate connected to the second word line; and a sixth transistor having a source connected to a second power supply that supplies a second power supply voltage different from the first power supply voltage, a drain connected to the first node, and a gate connected to the second node. and an eighth transistor having a source connected to the second power supply, a drain connected to the second node, and a gate connected to the first node, wherein the first transistor includes a ninth and tenth transistor, the second transistor includes an eleventh and twelfth transistor, the third to sixth and ninth to twelfth transistors are transistors of a first conductivity type, and the seventh and eighth transistors are transistors of a second conductivity type different from the first conductivity type, and the SRAM cell includes a first active region including a third nanosheet extending in a first direction as the channel, and a ninth nanosheet extending in the first direction as the channel, and a fifth active region including a fifth nanosheet extending in the first direction as the channel, and a tenth active region including a fifth nanosheet extending in the first direction as the channel, and a tenth active region including a fifth nanosheet extending in the first direction as the channel, and a tenth active region including a fifth active regiona second active region including a tenth nanosheet extending in the first direction; a third active region forming the channel, source, and drain of the fourth transistor, the channel including the fourth nanosheet extending in the first direction as the channel, and the channel, source, and drain of the eleventh transistor, the channel including the eleventh nanosheet extending in the first direction as the channel; a fourth active region forming the channel, source, and drain of the sixth transistor, the channel including the sixth nanosheet extending in the first direction as the channel, and the channel, source, and drain of the twelfth transistor, the channel including the twelfth nanosheet extending in the first direction as the channel; and a fourth active region formed higher than the first to fourth active regions in the depth direction, the channel of the seventh transistor. a fifth active region forming a channel, a source, and a drain of the eighth transistor, the channel including a seventh nanosheet extending in the first direction; and a sixth active region formed higher than the first to fourth active regions in the depth direction, forming a channel, a source, and a drain of the eighth transistor, the channel including an eighth nanosheet extending in the first direction, wherein the third and ninth nanosheets are arranged side by side in the first direction, the fifth and tenth nanosheets are arranged side by side in the first direction, the fourth and eleventh nanosheets are arranged side by side in the first direction, the sixth and twelfth nanosheets are arranged side by side in the first direction, the seventh and tenth nanosheets overlap in a planar view, and the sixth and eleventh nanosheets overlap in a planar view.

[0014] According to the present disclosure, the fifth and sixth active regions are formed higher in the depth direction than the first to fourth active regions. This allows a first conductivity type transistor to be formed in the lower part of the cell and a second conductivity type transistor to be formed in the upper part of the cell, thereby reducing the complexity of the manufacturing process of the semiconductor memory device and reducing manufacturing costs. Furthermore, since it is not necessary to space the first conductivity type transistor and the second conductivity type transistor apart, the area of ​​the semiconductor memory device can be reduced.

[0015] According to the present disclosure, in a layout structure of an SRAM cell using a CFET, it is possible to improve the operating speed of a semiconductor memory device, reduce manufacturing costs, and reduce the area of ​​the semiconductor memory device.

[0016] 1 is a plan view showing an example of a layout structure of an SRAM cell according to the first embodiment; 2 is a cross-sectional view showing an example of a layout structure of an SRAM cell according to the first embodiment; 3 is a cross-sectional view showing an example of a layout structure of an SRAM cell according to the first embodiment; 4 is a circuit diagram showing a configuration of an SRAM cell according to the first embodiment; 5 is another configuration example of a semiconductor integrated circuit device according to the first embodiment; 6 is a plan view showing another example of a layout structure of an SRAM cell according to the first embodiment; 7 is a plan view showing another example of a layout structure of an SRAM cell according to the first embodiment; 8 is a diagram for explaining a manufacturing method of a semiconductor memory device according to the first embodiment; 9 is a plan view showing another example of a layout structure of an SRAM cell according to the first embodiment; 10 is a plan view showing another example of a layout structure of an SRAM cell according to the first embodiment; 11 is a circuit diagram showing another configuration of an SRAM cell according to the first embodiment; 12 is a plan view showing another example of a layout structure of an SRAM cell according to the first embodiment;

[0017] Hereinafter, embodiments will be described with reference to the drawings. In the following embodiments, a semiconductor memory device includes a plurality of SRAM cells. At least some of the plurality of SRAM cells include nanosheet FETs, and further include a CFET structure in which transistors of different conductivity types (in the embodiment, the lower part of the cell is P conductivity type and the upper part of the cell is N conductivity type) are stacked.

[0018] In this specification, "VDD" and "VSS" refer to the power supply voltage or the power supply itself. In this specification, expressions such as "same wiring width" that mean the same width, etc., are considered to include the range of manufacturing variations.

[0019] (First Embodiment) (Configuration of SRAM Cell) Figures 1 to 3 show an example of the layout structure of an SRAM cell according to the first embodiment, with Figures 1(a) and 1(b) being plan views, and Figures 2(a) to 2(c) and 3(a) and 3(b) being cross-sectional views in the horizontal direction in a plan view. Specifically, Figure 1(a) shows the upper part of the cell, i.e., the part including the nanosheet transistor formed on the side farther from the substrate, and Figure 1(b) shows the lower part of the cell, i.e., the part including the nanosheet transistor formed on the side closer to the substrate. Figure 2(a) is a cross-section along line X1-X1', Figure 2(b) is a cross-section along line X2-X2', Figure 2(c) is a cross-section along line X3-X3', Figure 3(a) is a cross-section along line X4-X4', and Figure 3(b) is a cross-section along line X5-X5'.

[0020] In the following description, in plan views such as Figure 1, the vertical direction of the drawing is the Y direction (first direction), the horizontal direction of the drawing is the X direction (second direction), and the direction perpendicular to the substrate surface is the Z direction (depth direction).

[0021] 4 is a circuit diagram showing the configuration of an SRAM cell according to the first embodiment. As shown in FIG. 4, the SRAM cell according to this embodiment has a two-port SRAM cell circuit made up of drive transistors PU1 and PU2, load transistors PD1 and PD2, and access transistors PG1 to PG4. The drive transistors PU1 and PU2 and the access transistors PG1 to PG4 are P-type FETs, and the load transistors PD1 and PD2 are N-type FETs.

[0022] The drive transistor PU1 is provided between the power supply VDD and a first node NA, and the load transistor PD1 is provided between the first node NA and a power supply VSS. The gates of the drive transistor PU1 and the load transistor PD1 are connected to a second node NB, and they form an inverter INV1. The drive transistor PU2 is provided between the power supply VDD and the second node NB, and the load transistor PD2 is provided between the second node NB and the power supply VSS. The gates of the drive transistor PU2 and the load transistor PD2 are connected to the first node NA, and they form an inverter INV2. In other words, the output of one inverter is connected to the input of the other inverter, thereby forming a latch.

[0023] The access transistor PG1 is provided between the first bit line BLA and the first node NA, and its gate is connected to the first word line WLA. The access transistor PG2 is provided between the second bit line BLAX and the second node NB, and its gate is connected to the first word line WLA. The access transistor PG3 is provided between the third bit line BLB and the first node NA, and its gate is connected to the second word line WLB. The access transistor PG4 is provided between the fourth bit line BLBX and the second node NB, and its gate is connected to the second word line WLB. The first and second bit lines BLA and BLAX form a first complementary bit line pair, and the third and fourth bit lines BLB and BLBX form a second complementary bit line pair.

[0024] In a two-port SRAM cell circuit, when the first and second bit lines BLA, BLAX constituting a first complementary bit line pair are driven to a high level and a low level, respectively, and the first word line WLA is driven to a low level, a high level is written to the first node NA and a low level is written to the second node NB. On the other hand, when the first and second bit lines BLA, BLAX are driven to a low level and a high level, respectively, and the first word line WLA is driven to a low level, a low level is written to the first node NA and a high level is written to the second node NB. Then, when the first word line WLA is driven to a high level while data is written to the first and second nodes NA, NB, the latch state is established and the data written to the first and second nodes NA, NB is held.

[0025] Furthermore, when the first and second bit lines BLA, BLAX are discharged to a low level in advance and the first word line WLA is driven to a low level, the states of the first and second bit lines BLA, BLAX are determined according to the data written to the first and second nodes NA, NB, and data can be read from the SRAM cell. Specifically, when the first node NA is at a high level and the second node NB is at a low level, the first bit line BLA is charged to a high level and the second bit line BLAX is held at a low level. On the other hand, when the first node NA is at a low level and the second node NB is at a high level, the first bit line BLA is held at a low level and the second bit line BLAX is charged to a high level.

[0026] Furthermore, when the third and fourth bit lines BLB, BLBX constituting the second complementary bit line pair are driven to a high level and a low level, respectively, and the second word line WLB is driven to a low level, a high level is written to the first node NA and a low level is written to the second node NB. On the other hand, when the third and fourth bit lines BLB, BLBX are driven to a low level and a high level, respectively, and the second word line WLB is driven to a low level, a low level is written to the first node NA and a high level is written to the second node NB. Then, when the second word line WLB is driven to a high level while data is written to the first and second nodes NA, NB, the latch state is established and the data written to the first and second nodes NA, NB is held.

[0027] Furthermore, when the third and fourth bit lines BLB, BLBX are discharged to a low level in advance and the second word line WLB is driven to a low level, the states of the third and fourth bit lines BLB, BLBX are determined according to the data written to the first and second nodes NA, NB, and data can be read from the SRAM cell. Specifically, when the first node NA is at a high level and the second node NB is at a low level, the third bit line BLB is charged to a high level and the fourth bit line BLBX is held at a low level. On the other hand, when the first node NA is at a low level and the second node NB is at a high level, the third bit line BLB is held at a low level and the fourth bit line BLBX is charged to a high level.

[0028] As described above, the two-port SRAM cell has the functions of writing data to, retaining data, and reading data from the SRAM cell by controlling the first and second bit lines BLA, BLAX and the first word line WLA. Also, the two-port SRAM cell has the functions of writing data to, retaining data, and reading data from the SRAM cell by controlling the third and fourth bit lines BLB, BLBX and the second word line WLB.

[0029] In the following description, the dashed lines running vertically and horizontally in plan views such as FIG. 1 and the dashed lines running vertically in cross-sectional views such as FIG. 2 indicate grids used for component placement during design. The grids are arranged at equal intervals in the X direction and at equal intervals in the Y direction. The grid spacing may be the same or different in the X and Y directions. The grid spacing may also be different for each layer. Furthermore, each component does not necessarily have to be arranged on a grid.

[0030] 1 and other plan views, the dotted lines surrounding the cells indicate the cell frame (outer edge of the SRAM cell) of the SRAM cell. The SRAM cell is arranged so that the cell frame is in contact with the cell frame of an adjacent cell in the X or Y direction.

[0031] 1 and the like, an SRAM cell is arranged on each side of the SRAM cell in the X direction, with the SRAM cell inverted in the X direction, and an SRAM cell is arranged on each side of the SRAM cell in the Y direction, with the SRAM cell inverted in the Y direction.

[0032] 1B, a BM0 (Backside Metal 0) wiring layer is formed on the back surface of the semiconductor chip on which the transistors are formed. The BM0 wiring layer corresponds to the back surface wiring layer.

[0033] The BM0 wiring layer is formed with a power supply wiring 11 extending in the Y direction from the top to the bottom of the cell in the drawing. The power supply wiring 11 supplies a power supply voltage VDD.

[0034] A plurality of active regions that form the channel, source, and drain of the P-type transistor are formed in a P-type transistor region on an N-type well (NWell) (not shown). Specifically, active regions P1 to P4 are formed in the P-type transistor region. Active regions P2 and P3 overlap with power supply wiring 11 in plan view.

[0035] In the P-type transistor region, access transistors PG1 to PG4 and drive transistors PU1 and PU2 are formed. The access transistors PG1 and PG3, the drive transistors PU1 and PU2, and the access transistors PG2 and PG4 each have a channel made of two overlapping sheet structures in a plan view, and each have nanosheets 21 to 26 extending in the Y direction.

[0036] In the active region P2, the portion that becomes the source of the drive transistor PU1 is connected to the power supply wiring 11 through a via 91 that is provided at a position that overlaps the power supply wiring 11 in a plan view. In the active region P3, the portion that becomes the source of the load transistor PU2 is connected to the power supply wiring 11 through a via 92 that is provided at a position that overlaps the power supply wiring 11 in a plan view.

[0037] As shown in Figure 1(a), a plurality of active regions that form the channel, source, and drain of the N-type transistor are formed in the N-type transistor region. Specifically, active regions N1 to N4 are formed in the N-type transistor region. The active regions N1 to N4 are respectively arranged above the active regions P1 to P4 in the Z direction. The active regions N1 to N4 overlap with the active regions P1 to P4, respectively, in a plan view.

[0038] In the N-type transistor region, load transistors PD1 and PD2 and dummy transistors DN1 to DN4 are formed. The load transistors PD1 and PD2 and the dummy transistors DN1 to DN4 each have a channel made of two overlapping sheet structures in a plan view, and each have nanosheets 27, 28, and 30a to 30d extending in the Y direction. Note that the dummy transistors DN1 to DN4 are transistors that do not have a logic function.

[0039] The width of the nanosheets 23, 24, 27, and 28 in the X direction is twice the width of the nanosheets 21, 22, 25, 26, and 30a to 30d in the X direction.

[0040] In the active region, the portions that become the source and drain on both sides of the nanosheet are formed, for example, by epitaxial growth from the nanosheet.

[0041] Gate wirings (Gate) 31 to 36 are formed extending in the X direction. The gate wiring 31 surrounds the outer peripheries of the nanosheets 21 and 30a in the X and Z directions. The gate wiring 32 surrounds the outer peripheries of the nanosheets 24 and 28 in the X and Z directions. The gate wiring 33 surrounds the outer peripheries of the nanosheets 25 and 30b in the X and Z directions. The gate wiring 34 surrounds the outer peripheries of the nanosheets 22 and 30c in the X and Z directions. The gate wiring 35 surrounds the outer peripheries of the nanosheets 23 and 27 in the X and Z directions. The gate wiring 36 surrounds the outer peripheries of the nanosheets 26 and 30d in the X and Z directions. The gate wiring 31 corresponds to the gates of the access transistor PG1 and the dummy transistor DN1. The gate wiring 32 corresponds to the gates of the drive transistor PU2 and the load transistor PD2. The gate wiring 33 corresponds to the gates of the access transistor PG2 and the dummy transistor DN2. The gate wiring 34 corresponds to the gates of the access transistor PG3 and the dummy transistor DN3. The gate wiring 35 corresponds to the gates of the drive transistor PU1 and the load transistor PD1. The gate wiring 36 corresponds to the gates of the access transistor PG4 and the dummy transistor DN4.

[0042] As shown in FIG. 1B, local interconnects (LI) 41-46 extending in the X direction are formed below the cell. Local interconnect 41 is connected to the source of access transistor PG1 in active region P1. Local interconnect 42 is connected to the source of access transistor PG2 in active region P4. Local interconnect 43 is connected to the drain of access transistor PG1 in active region P1, the drain of access transistor PG3 in active region P1, and the drain of drive transistor PU1 in active region P2. Local interconnect 44 is connected to the drain of drive transistor PU2 in active region P3, the drain of access transistor PG2 in active region P4, and the drain of access transistor PG4 in active region P4. Local interconnect 45 is connected to the source of access transistor PG3 in active region P1. Local interconnect 46 is connected to the source of access transistor PG4 in active region P4.

[0043] As shown in FIG. 1A, local interconnections 47 to 50 extending in the X direction are formed above the cell. Local interconnection 47 is connected to a portion in active region N3 that will become the source of load transistor PD2. Local interconnection 48 is connected to a portion in active region N2 that will become the drain of load transistor PD1. Local interconnection 49 is connected to a portion in active region N3 that will become the drain of load transistor PD2. Local interconnection 50 is connected to a portion in active region N2 that will become the source of load transistor PD1.

[0044] The local wiring 48 is connected to the gate wiring 32 via a shared contact 51. The local wiring 48 is connected to the local wiring 43 via a via 52. The local wiring 49 is connected to the gate wiring 35 via a shared contact 53. The local wiring 49 is connected to the local wiring 44 via a via 54. The gate wiring 32, the local wirings 43 and 48, the shared contact 51, and the via 52 correspond to a first node NA. The gate wiring 35, the local wirings 44 and 49, the shared contact 53, and the via 54 correspond to a second node NB.

[0045] A power supply line 61 and lines 62 to 65 extending in the Y direction from the top to the bottom of the cell in the drawing are formed in the M1 wiring layer, which is a metal wiring layer above the active regions N1 to N4. Lines 66 to 69 are also formed. The power supply line 61 supplies a power supply voltage VSS. The lines 62 to 65 correspond to the first bit line BLA, the third bit line BLB, the second bit line BLAX, and the fourth bit line BLBX, respectively.

[0046] The power supply wiring 61 overlaps with the active regions P2, P3, N2, and N3 and the power supply wiring 11 in a planar view. The power supply wiring 61 is connected to the local wiring 47 through a via 55 and to the local wiring 50 through a via 56. The via 55 is formed in a region where the power supply wiring 61 and the active region N3 overlap in a planar view. The via 56 is formed in a region where the power supply wiring 61 and the active region N2 overlap in a planar view.

[0047] The wiring 62 is connected to the local wiring 41 through a via 57. The wiring 63 is connected to the local wiring 45 through a via 58. The wiring 64 is connected to the local wiring 42 through a via 59. The wiring 65 is connected to the local wiring 46 through a via 60.

[0048] Wirings 71 and 72 extending in the X direction from the left to the right of the cell in the drawing are formed in the M2 wiring layer, which is an upper layer of the M1 wiring layer. Wirings 71 and 72 correspond to the first word line WLA and the second word line WLB, respectively. Wiring 71 is connected to gate wiring 31 via via 81, wiring 66, and via 60a. Wiring 71 is connected to gate wiring 33 via via 82, wiring 67, and via 60b. Wiring 72 is connected to gate wiring 34 via via 83, wiring 68, and via 60c. Wiring 72 is connected to gate wiring 36 via via 84, wiring 69, and via 60d.

[0049] With the above configuration, power supply wiring 11 that supplies power supply voltage VDD is formed in the BM0 wiring layer, which is the wiring layer on the back side of the transistors. Power supply wiring 11 overlaps active regions P2 and P3 in a planar view, and is connected to each other by vias 91 and 92 provided in the overlapping region. Therefore, since the active region (transistor) and the power supply wiring can be arranged to overlap, the wiring width of power supply wiring 11 that supplies power supply voltage VDD can be increased, and the wiring resistance of the power supply wiring can be reduced. This can improve the operating speed and operational stability of the semiconductor memory device.

[0050] In addition, P-type active regions P1 to P4 are formed in the lower part of the cell. N-type active regions N1 to N4 are formed in the upper part of the cell. As a result, only P-type nanosheet transistors are formed in the lower part of the cell and only N-type nanosheet transistors are formed in the upper part of the cell, which makes it possible to reduce the complexity of the manufacturing process of the semiconductor memory device and to reduce manufacturing costs. Furthermore, since it is not necessary to arrange the P-type nanosheet transistor and the N-type nanosheet transistor at a distance, it is possible to reduce the area of ​​the semiconductor memory device.

[0051] Furthermore, the X-direction width of nanosheets 23, 24, 27, and 28 is twice the X-direction width of nanosheets 21, 22, 25, and 26. That is, the ratio of the width of the nanosheets in load transistors PD1 and PD2 to the width of the nanosheets in drive transistors PU1 and PU2 to the width of the nanosheets in access transistors PG1 to PG4 is 4:4:2. Here, the drive capability of load transistors PD1 and PD2 is suppressed lower than that of drive transistors PU1 and PU2 by adjusting the concentration of N-type impurities contained in active regions N2 and N3. For example, the concentration of N-type impurities contained in active regions N2 and N3 is adjusted so that the drive capability of load transistors PD1 and PD2 is 1 / 4 of that of drive transistors PU1 and PU2. Therefore, the ratio of the drive capability of load transistors PD1 and PD2 to the drive capability of drive transistors PU1 and PU2 to the drive capability of access transistors PG1 to PG4 is 1:4:2. This ensures stability of the operation of the SRAM cell (static noise margin) when the word line is driven.

[0052] (Another Configuration Example) Fig. 5(a) shows another configuration example of the semiconductor integrated circuit device according to the first embodiment. The semiconductor integrated circuit device 100 shown in Fig. 5(a) is configured by stacking a first semiconductor chip 101 (chip A) and a second semiconductor chip 102 (chip B). Chip A has the above-mentioned SRAM cells and the like arranged therein. Chip B has power supply wiring formed in a wiring layer provided on its surface. Chip B is attached to the back side of chip A using bumps and the like.

[0053] 5B shows a cross section of the SRAM cell of FIG. 1 taken along line X1-X1' in this configuration example. As shown in FIG. 5B, a power supply wiring 11 that supplies VDD is formed in a wiring layer provided on the surface of chip B. The power supply wiring 11 is connected to active region P3 of chip A via via 92. Although not shown in the figure, the power supply wiring 11 is also connected to active region P2 of chip A via via 91.

[0054] 6A and 6B are plan views showing another example of the layout structure of the SRAM cell according to the first embodiment. Specifically, Fig. 6A shows the upper part of the cell, and Fig. 6B shows the lower part of the cell.

[0055] 6, compared to FIG. 1, the wires 63 and 65 in the M1 wiring layer are omitted, and wires 12 and 13 extending in the Y direction across the upper and lower ends of the cell in the drawing are formed in the BM0 wiring layer.

[0056] The wirings 12 and 13 correspond to the third bit line BLB and the fourth bit line BLBX, respectively. The wiring 12 overlaps with the active regions N1 and P1 and the wiring 62 in a planar view. The wiring 13 overlaps with the active regions N4 and P4 and the wiring 64 in a planar view. The wiring 12 is connected to a portion of the active region P1 that will become the source of the access transistor PG3 through a via 93 provided at a position where the wiring 12 and the wiring 13 overlap in a planar view. The wiring 13 is connected to a portion of the active region P4 that will become the source of the access transistor PG4 through a via 94 provided at a position where the wiring 12 and the wiring 13 overlap in a planar view.

[0057] 6 , wirings 12 and 13 corresponding to the third bit line BLB and the fourth bit line BLBX, respectively, are formed in the BM0 wiring layer. Wirings 62 and 64 corresponding to the first bit line BLA and the second bit line BLAX, respectively, are formed in the M1 wiring layer. This allows the wirings corresponding to the third bit line BLB and the fourth bit line BLBX and the wirings corresponding to the first bit line BLA and the second bit line BLAX to be formed in different wiring layers, thereby suppressing crosstalk noise between the third bit line BLB and the fourth bit line BLBX and the first bit line BLA and the second bit line BLAX. This improves the operational stability of the semiconductor memory device.

[0058] Furthermore, since the wiring corresponding to the third bit line BLB and the fourth bit line BLBX and the wiring corresponding to the first bit line BLA and the second bit line BLAX are formed in different wiring layers, the wiring width of the wirings 12, 13, 62, and 64 can be increased, thereby improving the operating speed of the semiconductor memory device.

[0059] In addition, the same effects as those in FIG. 1 can be obtained.

[0060] 7A and 7B are plan views showing another example of the layout structure of the SRAM cell according to the first embodiment. Specifically, Fig. 7A shows the upper part of the cell, and Fig. 7B shows the lower part of the cell.

[0061] 7, compared to FIG. 1, nanosheets 27a and 28a are arranged instead of the nanosheets 27 and 28.

[0062] Nanosheets 27a and 28a correspond to the channels of load transistors PD1 and PD2, respectively. The X-direction width of nanosheets 27a and 28a is half the X-direction width of nanosheets 23 and 24 (27 and 28). That is, the drive capabilities of load transistors PD1 and PD2 in FIG. 7 are lower than the drive capabilities of load transistors PD1 and PD2 in FIG. 1. This allows the drive capabilities of load transistors PD1 and PD2 to be suppressed. The X-direction width of nanosheets 27a and 28a may be determined depending on the drive capabilities of load transistors PD1 and PD2, and may be larger or smaller than the X-direction width of nanosheets 21, 22, 25, and 26, for example.

[0063] 8A to 8C are diagrams for explaining the method for manufacturing the semiconductor memory device according to the first embodiment. Specifically, FIGS. 8A to 8C are cross-sectional views taken along line X6-X6′ in FIG.

[0064] In Figure 7, the nanosheet 23 (24) of the drive transistor PU1 (PU2) and the nanosheet 27a (28a) of the load transistor PD1 (PD2) are arranged overlapping in the Z direction. As described above, the width of the nanosheet 27a (28a) in the X direction is half the width of the nanosheet 23 (24) in the X direction. That is, in Figure 7, nanosheets with different widths in the X direction are stacked in the Z direction. In the following explanation, a method for manufacturing a semiconductor memory device in which nanosheets with different widths in the X direction are stacked in the Z direction will be described using Figures 8(a) to 8(c).

[0065] 8A, a laminated semiconductor 210 is formed on a semiconductor substrate 200. The laminated semiconductor 210 is formed by alternately laminating semiconductor layers 220 and 230. Here, silicon (Si) is used as the material for the semiconductor layer 220, and a silicon germanium alloy (SiGe) is used as the material for the semiconductor layer 230.

[0066] 8, the laminated semiconductor 210 includes four semiconductor layers 220. Of the four semiconductor layers 220, the two semiconductor layers 220 (220a) at the top of the drawing correspond to the nanosheet 27a at the top of the cell, and the two semiconductor layers 220 (220b) at the bottom of the drawing correspond to the nanosheet 23 at the bottom of the cell.

[0067] After forming the laminated semiconductor 210 on the semiconductor substrate 200, a mask 241 is formed above the laminated semiconductor 210 in the figure. The width and position of the mask 241 in the X and Y directions are formed to match the width and position of the nanosheet 23 in the X and Y directions. Then, the laminated semiconductor 210 on both the left and right sides of the mask 241 in the X direction in the figure is removed by anisotropic etching. Thereafter, the mask 241 is removed.

[0068] Next, as shown in FIG. 8B , a mask 242 is formed on the upper right portion of the laminated semiconductor 210 in the drawing. The width and position of the mask 242 in the X and Y directions are formed to match the width and position of the nanosheet 27a in the X and Y directions. Then, the laminated semiconductor 210 on the left side of the mask 242 in the drawing is removed by anisotropic etching. Specifically, the upper portion of the laminated semiconductor 210 arranged on the left side of the mask 242 in the drawing, i.e., the semiconductor layer 220a and the semiconductor layer 230, are removed. Then, after the mask 242 is removed, the load transistor PD1 and the drive transistor PU1 are formed.

[0069] By the manufacturing method described above, it is possible to manufacture a semiconductor memory device in which nanosheets with different widths in the X direction are stacked in the Z direction, as shown in FIG. 8(c).

[0070] 8B, if the mask 242 is not formed on the upper part of the laminated semiconductor 210, the upper part of the laminated semiconductor 210, i.e., the semiconductor layer 220a and the semiconductor layer 230, are all removed. This allows the nanosheet (transistor) to be formed only on the lower part of the cell, without forming the nanosheet (transistor) on the upper part of the cell.

[0071] 9A and 9B are plan views showing another example of the layout structure of the SRAM cell according to the first embodiment. Specifically, Fig. 9A shows the upper part of the cell, and Fig. 9B shows the lower part of the cell.

[0072] 9, compared to FIG. 1, the drive transistors PU1 and PU2 are each composed of two nanosheet FETs. Specifically, the drive transistor PU1 is composed of transistors PU11 and PU12. The drive transistor PU2 is composed of transistors PU21 and PU22. Furthermore, nanosheets 27b and 28b are arranged in place of the nanosheets 27 and 28.

[0073] 9B, active regions P5 to P8 are formed in the P-type transistor region. The active regions P5 to P8 overlap with the power supply wiring 11 in plan view.

[0074] In the P-type transistor region, transistors PU11, PU12, PU21, and PU22 are formed. The transistors PU11, PU12, PU21, and PU22 have nanosheets 23a, 23b, 24a, and 24b extending in the Y direction, respectively.

[0075] In active region P5, the portion that will become the source of transistor PU11 is connected to power supply wiring 11 via a via 95 that is provided at a position that overlaps with power supply wiring 11 in a planar view. In active region P6, the portion that will become the source of transistor PU12 is connected to power supply wiring 11 via a via 96 that is provided at a position that overlaps with power supply wiring 11 in a planar view. In active region P7, the portion that will become the source of transistor PU21 is connected to power supply wiring 11 via a via 97 that is provided at a position that overlaps with power supply wiring 11 in a planar view. In active region P8, the portion that will become the source of transistor PU22 is connected to power supply wiring 11 via a via 98 that is provided at a position that overlaps with power supply wiring 11 in a planar view.

[0076] 9A, active regions N5 to N8 are formed in the N-type transistor region. The active regions N5 to N8 are respectively arranged above the active regions P5 to P8 in the Z direction. The active regions N5 to N8 overlap with the active regions P5 to P8, respectively, in a plan view.

[0077] In the N-type transistor region, load transistors PD1 and PD2 and dummy transistors DN5 and DN6 are formed. The load transistors PD1 and PD2 and the dummy transistors DN5 and DN6 have nanosheets 27b, 28b, 30e, and 30f, respectively, extending in the Y direction. Note that the dummy transistors DN5 and DN6 are transistors that do not have a logic function.

[0078] The nanosheets 21, 22, 23a, 23b, 24a, 24b, 25, 26, 27b, 28b, and 30a to 30f have the same width in the X direction.

[0079] Gate wiring 32 surrounds the outer peripheries of nanosheets 24a, 24b, 28b, and 30f in the X and Z directions. Gate wiring 35 surrounds the outer peripheries of nanosheets 23a, 23b, 27b, and 30e in the X and Z directions. Gate wiring 32 corresponds to the gates of transistors PU21 and PU22, load transistor PD2, and dummy transistor DN6. Gate wiring 35 corresponds to the gates of transistors PU11 and PU12, load transistor PD1, and dummy transistor DN5.

[0080] The portion that becomes the drain of transistor PU11 in active region P5 and the portion that becomes the drain of transistor PU12 in active region P6 are connected to the portions that become the drains of access transistors PG1 and PG3 in active region P1, the portion that becomes the drain of load transistor PD1 in active region N5, and gate wiring 32 via local wiring 43, via 52, local wiring 48, and shared contact 51. The portion that becomes the drain of transistor PU21 in active region P7 and the portion that becomes the drain of transistor PU22 in active region P8 are connected to the portions that become the drains of access transistors PG2 and PG4 in active region P4, the portion that becomes the drain of load transistor PD2 in active region N8, and gate wiring 35 via local wiring 44, via 54, local wiring 49, and shared contact 53.

[0081] The portion that becomes the source of the load transistor PD1 in the active region N5 is connected to the power supply wiring 61 via the local wiring 50 and the via 56. The portion that becomes the source of the load transistor PD2 in the active region N8 is connected to the power supply wiring 61 via the local wiring 47 and the via 55.

[0082] 9, transistors PU11 and PU12 constituting drive transistor PU1 have nanosheets 23a and 23b, respectively. Transistors PU21 and PU22 constituting drive transistor PU2 have nanosheets 24a and 24b, respectively. Load transistors PD1 and PD2 have nanosheets 27b and 28b, respectively. The widths in the X direction of nanosheets 23a, 23b, 24a, 24b, 27b, 30e, 30f, and 28b are the same. This allows the drive capabilities of drive transistors PU1 and PU2 to be greater than the drive capabilities of load transistors PD1 and PD2.

[0083] Furthermore, nanosheets 23a, 23b, 24a, and 24b overlap nanosheets 27b, 30e, 30f, and 28b in plan view, respectively, so that the widths in the X direction of the nanosheets stacked in the Z direction are the same in the upper and lower cell sections, which makes it possible to prevent the manufacturing process from becoming complicated and the manufacturing costs from increasing.

[0084] Although the nanosheets 23a, 23b, 24a, and 24b have the same width in the X direction, they do not have to be the same.

[0085] 7, the wirings 63 and 65 in the M1 wiring layer may be omitted, and the wirings 12 and 13 corresponding to the third bit line BLB and the fourth bit line BLBX, respectively, may be formed in the BM0 wiring layer.

[0086] 10A and 10B are plan views showing another example of the layout structure of the SRAM cell according to the first embodiment. Specifically, Fig. 10A shows the upper part of the cell, and Fig. 10B shows the lower part of the cell.

[0087] In FIG. 10, the circuit configured in the SRAM cell is different from that in FIG.

[0088] 11 is a circuit diagram showing another configuration of the SRAM cell according to the first embodiment. As shown in FIG. 11, the SRAM cell according to this modification has a two-port SRAM cell circuit made up of load transistors PU1 and PU2, drive transistors PD1 and PD2, and access transistors PG1 to PG4. The load transistors PU1 and PU2 are P-type FETs, and the drive transistors PD1 and PD2 and the access transistors PG1 to PG4 are N-type FETs.

[0089] The load transistor PU1 is provided between the power supply VDD and a first node NA, and the drive transistor PD1 is provided between the first node NA and a power supply VSS. The gates of the load transistor PU1 and the drive transistor PD1 are connected to a second node NB, and they form an inverter INV1. The load transistor PU2 is provided between the power supply VDD and the second node NB, and the drive transistor PD2 is provided between the second node NB and the power supply VSS. The gates of the load transistor PU2 and the drive transistor PD2 are connected to the first node NA, and they form an inverter INV2. In other words, the output of one inverter is connected to the input of the other inverter, thereby forming a latch.

[0090] The access transistor PG1 is provided between the first bit line BLA and the first node NA, and its gate is connected to the first word line WLA. The access transistor PG2 is provided between the second bit line BLAX and the second node NB, and its gate is connected to the first word line WLA. The access transistor PG3 is provided between the third bit line BLB and the first node NA, and its gate is connected to the second word line WLB. The access transistor PG4 is provided between the fourth bit line BLBX and the second node NB, and its gate is connected to the second word line WLB. The first and second bit lines BLA and BLAX form a first complementary bit line pair, and the third and fourth bit lines BLB and BLBX form a second complementary bit line pair.

[0091] In a two-port SRAM cell circuit, when the first and second bit lines BLA, BLAX constituting a first complementary bit line pair are driven to a high level and a low level, respectively, and the first word line WLA is driven to a high level, a high level is written to the first node NA and a low level is written to the second node NB. On the other hand, when the first and second bit lines BLA, BLAX are driven to a low level and a high level, respectively, and the first word line WLA is driven to a high level, a low level is written to the first node NA and a high level is written to the second node NB. Then, when the first word line WLA is driven to a low level while data is written to the first and second nodes NA, NB, the latch state is established and the data written to the first and second nodes NA, NB is held.

[0092] Furthermore, when the first and second bit lines BLA, BLAX are precharged to a high level and the first word line WLA is driven to a high level, the states of the first and second bit lines BLA, BLAX are determined according to the data written to the first and second nodes NA, NB, making it possible to read data from the SRAM cell. Specifically, when the first node NA is at a high level and the second node NB is at a low level, the first bit line BLA is held at a high level and the second bit line BLAX is discharged to a low level. On the other hand, when the first node NA is at a low level and the second node NB is at a high level, the first bit line BLA is discharged to a low level and the second bit line BLAX is held at a high level.

[0093] Furthermore, when the third and fourth bit lines BLB, BLBX constituting the second complementary bit line pair are driven to a high level and a low level, respectively, and the second word line WLB is driven to a high level, a high level is written to the first node NA and a low level is written to the second node NB. On the other hand, when the third and fourth bit lines BLB, BLBX are driven to a low level and a high level, respectively, and the second word line WLB is driven to a high level, a low level is written to the first node NA and a high level is written to the second node NB. Then, when the second word line WLB is driven to a low level while data is written to the first and second nodes NA, NB, the latch state is established and the data written to the first and second nodes NA, NB is held.

[0094] Furthermore, when the third and fourth bit lines BLB, BLBX are precharged to a high level in advance and the second word line WLB is driven to a high level, the states of the third and fourth bit lines BLB, BLBX are determined according to the data written to the first and second nodes NA, NB, making it possible to read data from the SRAM cell. Specifically, when the first node NA is at a high level and the second node NB is at a low level, the third bit line BLB is held at a high level and the fourth bit line BLBX is discharged to a low level. On the other hand, when the first node NA is at a low level and the second node NB is at a high level, the third bit line BLB is discharged to a low level and the fourth bit line BLBX is held at a high level.

[0095] As described above, the two-port SRAM cell has the functions of writing data to, retaining data, and reading data from the SRAM cell by controlling the first and second bit lines BLA, BLAX and the first word line WLA. Also, the two-port SRAM cell has the functions of writing data to, retaining data, and reading data from the SRAM cell by controlling the third and fourth bit lines BLB, BLBX and the second word line WLB.

[0096] 10B, the BM0 wiring layer is formed with a power supply wiring 11 extending in the Y direction from the top to the bottom of the cell in the drawing. The power supply wiring 11 supplies a power supply voltage VDD.

[0097] Active regions P1 to P4 are formed in the P-type transistor region. The active regions P2 and P3 overlap with the power supply wiring 11 in plan view.

[0098] In the P-type transistor region, load transistors PU1 and PU2 and dummy transistors DP1 to DP4 are formed. The dummy transistors DP1 and DP3, the load transistors PU1 and PU2, and the dummy transistors DP2 and DP4 each have nanosheets 21 to 26 extending in the Y direction as their channels. Note that the dummy transistors DP1 to DP4 are transistors that do not have a logic function.

[0099] 10A, active regions N1 to N4 are formed in the N-type transistor region. The active regions N1 to N4 are respectively arranged above the active regions P1 to P4 in the Z direction. The active regions N1 to N4 overlap with the active regions P1 to P4, respectively, in a plan view.

[0100] In the N-type transistor region, drive transistors PD1 and PD2 and access transistors PG1 to PG4 are formed. The drive transistors PD1 and PD2 and the access transistors PG1 to PG4 have nanosheets 27, 28, and 30a to 30d extending in the Y direction as channels, respectively.

[0101] The width of the nanosheets 23, 24, 27, and 28 in the X direction is twice the width of the nanosheets 21, 22, 25, 26, and 30a to 30d in the X direction.

[0102] Gate wiring 31 to 36 are formed extending in the X direction. Gate wiring 31 surrounds the outer peripheries of nanosheets 21 and 30a in the X and Z directions. Gate wiring 32 surrounds the outer peripheries of nanosheets 24 and 28 in the X and Z directions. Gate wiring 33 surrounds the outer peripheries of nanosheets 25 and 30b in the X and Z directions. Gate wiring 34 surrounds the outer peripheries of nanosheets 22 and 30c in the X and Z directions. Gate wiring 35 surrounds the outer peripheries of nanosheets 23 and 27 in the X and Z directions. Gate wiring 36 surrounds the outer peripheries of nanosheets 26 and 30d in the X and Z directions. Gate wiring 31 corresponds to the gates of access transistor PG1 and dummy transistor DP1. Gate wiring 32 corresponds to the gates of load transistor PU2 and drive transistor PD2. Gate wiring 33 corresponds to the gates of access transistor PG2 and dummy transistor DP2. The gate wiring 34 corresponds to the gates of the access transistor PG3 and the dummy transistor DP3, the gate wiring 35 corresponds to the gates of the load transistor PU1 and the drive transistor PD1, and the gate wiring 36 corresponds to the gates of the access transistor PG4 and the dummy transistor DP4.

[0103] 10B, local wirings 43 and 44 extending in the X direction are formed below the cell. The local wiring 43 is connected to a portion of the active region P2 that will become the drain of the load transistor PU1. The local wiring 44 is connected to a portion of the active region P3 that will become the drain of the load transistor PU2.

[0104] As shown in FIG. 10A, local interconnections 47-50 and 50a-50d extending in the X direction are formed above the cell. Local interconnection 47 is connected to the portion that will become the source of drive transistor PD2 in active region N3. Local interconnection 48 is connected to the portion that will become the drain of access transistor PG1 in active region N1, the portion that will become the drain of access transistor PG3 in active region N1, and the portion that will become the drain of drive transistor PD1 in active region N2. Local interconnection 49 is connected to the portion that will become the drain of drive transistor PD2 in active region N3, the portion that will become the drain of access transistor PG2 in active region N4, and the portion that will become the drain of access transistor PG4 in active region N4. Local interconnection 50 is connected to the portion that will become the source of drive transistor PD1 in active region N2. Local interconnection 50a is connected to the portion that will become the source of access transistor PG1 in active region N1. Local interconnection 50b is connected to the portion that will become the source of access transistor PG2 in active region N4. The local interconnection 50c is connected to a portion of the active region N1 that will become the source of the access transistor PG3, and the local interconnection 50d is connected to a portion of the active region N4 that will become the source of the access transistor PG4.

[0105] The local wiring 48 is connected to the gate wiring 32 via a shared contact 51. The local wiring 48 is connected to the local wiring 43 via a via 52. The local wiring 49 is connected to the gate wiring 35 via a shared contact 53. The local wiring 49 is connected to the local wiring 44 via a via 54. The gate wiring 32, the local wirings 43 and 48, the shared contact 51, and the via 52 correspond to a first node NA. The gate wiring 35, the local wirings 44 and 49, the shared contact 53, and the via 54 correspond to a second node NB.

[0106] The M1 wiring layer is formed with a power supply wiring 61 and wirings 62 to 65 extending in the Y direction from the top to the bottom of the cell in the drawing. Wirings 66 to 69 are also formed. The power supply wiring 61 supplies a power supply voltage VSS. The wirings 62 to 65 correspond to the first bit line BLA, the third bit line BLB, the second bit line BLAX, and the fourth bit line BLBX, respectively.

[0107] The power supply wiring 61 overlaps with the active regions N2, N3, P2, and P3 and the power supply wiring 11 in a planar view. The power supply wiring 61 is connected to the local wiring 47 through a via 55 and to the local wiring 50 through a via 56. The via 55 is formed in a region where the power supply wiring 61 and the active region N3 overlap in a planar view. The via 56 is formed in a region where the power supply wiring 61 and the active region N2 overlap in a planar view.

[0108] Wire 62 is connected to local wire 50a through via 60e. Wire 63 is connected to local wire 50c through via 60f. Wire 64 is connected to local wire 50b through via 60g. Wire 65 is connected to local wire 50d through via 60h.

[0109] The M2 wiring layer is formed with wirings 71 and 72 extending in the X direction from the left to the right ends of the cell in the drawing. The wirings 71 and 72 correspond to the first word line WLA and the second word line WLB, respectively. The wiring 71 is connected to the gate wiring 31 via a via 81, a wiring 66, and a via 60a. The wiring 71 is connected to the gate wiring 33 via a via 82, a wiring 67, and a via 60b. The wiring 72 is connected to the gate wiring 34 via a via 83, a wiring 68, and a via 60c. The wiring 72 is connected to the gate wiring 36 via a via 84, a wiring 69, and a via 60d.

[0110] In the configuration of Figure 10, power supply wiring 11 that supplies power supply voltage VDD is formed in the BM0 wiring layer, which is the wiring layer on the back side of the transistors. Power supply wiring 11 overlaps active regions P2 and P3 in a planar view and is connected to each other by vias 91 and 92 provided in the overlapping region. Therefore, since the active regions (transistors) and the power supply wiring can be arranged to overlap, the wiring width of power supply wiring 11 that supplies power supply voltage VDD can be increased and the wiring resistance of the power supply wiring can be reduced. This can improve the operating speed and operational stability of the semiconductor memory device.

[0111] In addition, P-type active regions P1 to P4 are formed in the lower part of the cell. N-type active regions N1 to N4 are formed in the upper part of the cell. As a result, only P-type nanosheet transistors are formed in the lower part of the cell and only N-type nanosheet transistors are formed in the upper part of the cell, which makes it possible to reduce the complexity of the manufacturing process of the semiconductor memory device and to reduce manufacturing costs. Furthermore, since it is not necessary to arrange the P-type nanosheet transistor and the N-type nanosheet transistor at a distance, it is possible to reduce the area of ​​the semiconductor memory device.

[0112] Furthermore, the X-direction width of nanosheets 23, 24, 27, and 28 is twice the X-direction width of nanosheets 21, 22, 25, and 26. That is, the ratio of the width of the nanosheets in load transistors PU1 and PU2 to the width of the nanosheets in drive transistors PD1 and PD2 to the width of the nanosheets in access transistors PG1 to PG4 is 4:4:2. Here, the drive capability of load transistors PU1 and PU2 is suppressed lower than that of drive transistors PD1 and PD2 by adjusting the concentration of P-type impurities contained in active regions P2 and P3. For example, the concentration of P-type impurities contained in active regions P2 and P3 is adjusted so that the drive capability of load transistors PU1 and PU2 is 1 / 4 of that of drive transistors PD1 and PD2. Therefore, the ratio of the drive capability of load transistors PU1 and PU2 to the drive capability of drive transistors PD1 and PD2 to the drive capability of access transistors PG1 to PG4 is 1:4:2. This ensures stability of the operation of the SRAM cell (static noise margin) when the word line is driven.

[0113] 12A and 12B are plan views showing another example of the layout structure of the SRAM cell according to the first embodiment. Specifically, Fig. 12A shows the upper part of the cell, and Fig. 12B shows the lower part of the cell.

[0114] 12, compared to FIG. 10, the drive transistors PD1 and PD2 are each composed of two nanosheet FETs. Specifically, the drive transistor PD1 is composed of transistors PD11 and PD12. The drive transistor PD2 is composed of transistors PD21 and PD22. Furthermore, nanosheets 23c and 24c are arranged in place of the nanosheets 23 and 24.

[0115] 12B, active regions P5 to P8 are formed in the P-type transistor region, and the active regions P5 to P8 overlap with the power supply wiring 11 in plan view.

[0116] In the P-type transistor region, load transistors PU1 and PU2 and dummy transistors DP5 and DP6 are formed. The load transistors PU1 and PU2 and the dummy transistors DP5 and DP6 have nanosheets 23c, 24c, 30g, and 30h extending in the Y direction, respectively. Note that the dummy transistors DP5 and DP6 are transistors that do not have a logic function.

[0117] In the active region P5, the portion that becomes the source of the load transistor PU1 is connected to the power supply wiring 11 through a via 91 that is provided at a position that overlaps the power supply wiring 11 in a planar view. In the active region P8, the portion that becomes the source of the load transistor PU2 is connected to the power supply wiring 11 through a via 92 that is provided at a position that overlaps the power supply wiring 11 in a planar view.

[0118] 12A, active regions N5 to N8 are formed in the N-type transistor region. The active regions N5 to N8 are respectively arranged above the active regions P5 to P8 in the Z direction. The active regions N5 to N8 overlap with the active regions P5 to P8, respectively, in a plan view.

[0119] In the N-type transistor region, transistors PD11, PD12, PD21, and PD22 are formed. The transistors PD11, PD12, PD21, and PD22 have nanosheets 27c, 27d, 28c, and 28d extending in the Y direction, respectively.

[0120] The nanosheets 21, 22, 23c, 24c, 25, 26, 27c, 27d, 28c, 28d, 30a to 30d, 30g, and 30h have the same width in the X direction.

[0121] Gate wiring 32 surrounds the outer peripheries of nanosheets 24c, 28c, 28d, and 30h in the X and Z directions. Gate wiring 35 surrounds the outer peripheries of nanosheets 23c, 27c, 27d, and 30g in the X and Z directions. Gate wiring 32 corresponds to the gates of transistors PD21 and PD22, load transistor PU2, and dummy transistor DP6. Gate wiring 35 corresponds to the gates of transistors PD11 and PD12, load transistor PU1, and dummy transistor DP5.

[0122] The portion that becomes the drain of load transistor PU1 in active region P5 is connected, via local wiring 43, via 52, local wiring 48, and shared contact 51, to the portion that becomes the drain of access transistors PG1 and PG3 in active region N1, the portion that becomes the drain of transistor PD11 in active region N5, the portion that becomes the drain of transistor PD12 in active region N6, and gate wiring 32. The portion that becomes the drain of load transistor PU2 in active region P8 is connected, via local wiring 44, via 54, local wiring 49, and shared contact 53, to the portion that becomes the drain of access transistors PG2 and PG4 in active region N4, the portion that becomes the drain of transistor PD21 in active region N7, the portion that becomes the drain of transistor PD22 in active region N8, and gate wiring 35.

[0123] 12, transistors PD11 and PD12 constituting drive transistor PD1 have nanosheets 27c and 27d, respectively. Transistors PD21 and PD22 constituting drive transistor PD2 have nanosheets 28c and 28d, respectively. Load transistors PU1 and PU2 have nanosheets 23c and 24c, respectively. Nanosheets 23c, 24c, 27c, 27d, 28c, 28d, 30g, and 30h have the same width in the X direction. This allows the drive capabilities of drive transistors PD1 and PD2 to be greater than the drive capabilities of load transistors PU1 and PU2.

[0124] Furthermore, nanosheets 23c, 30g, 30h, and 24c overlap nanosheets 27c, 27d, 28c, and 28d in plan view, which makes the widths of the stacked nanosheets in the X direction the same in the upper and lower parts of the cell, thereby preventing the manufacturing process from becoming complicated and the manufacturing costs from increasing.

[0125] Although the nanosheets 27c, 27d, 28c, and 28d have the same width in the X direction, they do not have to be the same.

[0126] 7, the wirings 63 and 65 in the M1 wiring layer may be omitted, and the wirings 12 and 13 corresponding to the third bit line BLB and the fourth bit line BLBX, respectively, may be formed in the BM0 wiring layer.

[0127] Second Embodiment Fig. 13 is a plan view showing an example of a layout structure of an SRAM cell according to a second embodiment. Specifically, Fig. 13(a) shows the upper part of the cell, and Fig. 13(b) shows the lower part of the cell. In Fig. 13, the circuit of Fig. 4 is configured in the SRAM cell.

[0128] 1, in FIG. 13, the drive transistors PU1 and PU2 are each composed of two nanosheet FETs. Specifically, the drive transistor PU1 is composed of transistors PU11 and PU12. The drive transistor PU2 is composed of transistors PU21 and PU22. Also, the arrangement of the access transistors PG1 to PG4 is different.

[0129] 13B, the BM0 wiring layer is formed with a power supply wiring 111 and wirings 112 to 115 that extend in the Y direction from the top to the bottom of the cell. The power supply wiring 111 supplies a power supply voltage VDD. The wirings 112 to 115 correspond to the first bit line BLA, the third bit line BLB, the second bit line BLAX, and the fourth bit line BLBX, respectively.

[0130] Active regions P11 to P14 are formed in the P-type transistor region. The active regions P11 to P14 overlap with the wirings 112 to 115, respectively, in a plan view.

[0131] In the P-type transistor region, access transistors PG1 to PG4 and transistors PU11, PU12, PU21, and PU22 are formed. Access transistor PG1, transistor PU11, access transistor PG3, transistors PU12 and PU21, access transistor PG2, transistor PU22, and access transistor PG4 each have nanosheets 121 to 128 extending in the Y direction as a channel.

[0132] In the active region P11, the portion that will become the source of the access transistor PG1 is connected to the wiring 112 via a via 191 that is provided at a position that overlaps the wiring 112 in a planar view. In the active region P12, the portion that will become the source of the access transistor PG3 is connected to the wiring 113 via a via 192 that is provided at a position that overlaps the wiring 113 in a planar view. In the active region P13, the portion that will become the source of the access transistor PG2 is connected to the wiring 114 via a via 193 that is provided at a position that overlaps the wiring 114 in a planar view. In the active region P14, the portion that will become the source of the access transistor PG4 is connected to the wiring 115 via a via 194 that is provided at a position that overlaps the wiring 115 in a planar view.

[0133] 13A, active regions N11 to N14 are formed in the N-type transistor region. The active regions N11 to N14 are respectively arranged above the active regions P11 to P14 in the Z direction. The active regions N11 to N14 overlap with the active regions P11 to P14, respectively, in a plan view.

[0134] In the N-type transistor region, load transistors PD1 and PD2 and dummy transistors DN11 to DN14 are formed. The load transistors PD1 and PD2 and the dummy transistors DN11 to DN14 have nanosheets 129, 130, and 130a to 130d extending in the Y direction, respectively. Note that the dummy transistors DN11 to DN14 are transistors that do not have a logic function.

[0135] The widths in the X direction of the nanosheets 129 and 130 are smaller than the widths in the X direction of the nanosheets 121 to 128 and 130a to 130d. Note that the widths in the X direction of the nanosheets 129 and 130 may be the same as the widths in the X direction of the nanosheets 121 to 128 and 130a to 130d.

[0136] Gate wiring 131 to 136 are formed extending in the X direction. Gate wiring 131 surrounds the outer peripheries of nanosheets 121 and 130a in the X and Z directions. Gate wiring 132 surrounds the outer peripheries of nanosheet 123 in the X and Z directions. Gate wiring 133 surrounds the outer peripheries of nanosheets 125, 127, 130, and 130b in the X and Z directions. Gate wiring 134 surrounds the outer peripheries of nanosheets 122, 124, 129, and 130c in the X and Z directions. Gate wiring 135 surrounds the outer peripheries of nanosheet 126 in the X and Z directions. Gate wiring 136 surrounds the outer peripheries of nanosheets 128 and 130d in the X and Z directions. Gate wiring 131 corresponds to the gates of access transistor PG1 and dummy transistor DN11. Gate wiring 132 corresponds to the gate of access transistor PG3. Gate wiring 133 corresponds to the gates of load transistor PD2, transistors PU21 and PU22, and dummy transistor DN12. Gate wiring 134 corresponds to the gates of load transistor PD1, transistors PU11 and PU12, and dummy transistor DN13. Gate wiring 135 corresponds to the gate of access transistor PG2. Gate wiring 136 corresponds to the gates of access transistor PG4 and dummy transistor DN14.

[0137] 13B, local interconnections 141 to 144 extending in the X direction are formed below the cell. Local interconnection 141 is connected to power supply interconnection 111 via via 195. Local interconnection 141 is connected to the portion that will become the source of transistor PU21 in active region P13 and the portion that will become the source of transistor PU22 in active region P14. Local interconnection 142 is connected to the portion that will become the drain of access transistor PG1 in active region P11, the portion that will become the drain of transistor PU11 in active region P11, the portion that will become the drain of access transistor PG3 in active region P12, and the portion that will become the drain of transistor PU12 in active region P12. Local interconnection 143 is connected to the portion that will become the drain of transistor PU21 in active region P13, the portion that will become the drain of access transistor PG2 in active region P13, the portion that will become the drain of transistor PU22 in active region P14, and the portion that will become the drain of access transistor PG4 in active region P14. Local interconnection 144 is connected to power supply interconnection 111 through via 196. Local interconnection 144 is connected to the portion that will become the source of transistor PU11 in active region P11 and the portion that will become the source of transistor PU12 in active region P12.

[0138] 13A, local interconnections 145 to 148 extending in the X direction are formed above the cell. Local interconnection 145 is connected to a portion in active region N13 that will become the source of load transistor PD2. Local interconnection 146 is connected to a portion in active region N12 that will become the drain of load transistor PD1. Local interconnection 147 is connected to a portion in active region N13 that will become the drain of load transistor PD2. Local interconnection 148 is connected to a portion in active region N12 that will become the source of load transistor PD1.

[0139] Local wiring 146 is connected to gate wiring 133 via shared contact 151. Local wiring 146 is connected to local wiring 142 via via 152. Local wiring 147 is connected to gate wiring 134 via shared contact 153. Local wiring 147 is connected to local wiring 143 via via 154. Gate wiring 133, local wirings 142 and 146, shared contact 151, and via 152 correspond to a first node NA. Gate wiring 134, local wirings 143 and 147, shared contact 153, and via 154 correspond to a second node NB.

[0140] A power supply wiring 161 extending in the Y direction from the top to the bottom of the cell in the drawing is formed in the M1 wiring layer. Wirings 162 to 165 are also formed. The power supply wiring 161 supplies a power supply voltage VSS. The power supply wiring 161 is connected to the local wiring 145 through a via 155 and to the local wiring 148 through a via 156.

[0141] The M2 wiring layer is formed with wirings 171 and 172 extending in the X direction from the left to the right ends of the cell in the drawing. The wirings 171 and 172 correspond to the first word line WLA and the second word line WLB, respectively. The wiring 171 is connected to the gate wiring 131 via vias 181, 162, and 157. The wiring 171 is connected to the gate wiring 135 via vias 182, 163, and 158. The wiring 172 is connected to the gate wiring 132 via vias 183, 164, and 159. The wiring 172 is connected to the gate wiring 136 via vias 184, 165, and 160.

[0142] With the above configuration, wirings 112 to 115 corresponding to the first bit line BLA, the third bit line BLB, the second bit line BLAX, and the fourth bit line BLBX are formed in the BM0 wiring layer, which is the wiring layer on the back side of the transistors. Wiring 112 overlaps with active region P11 in a planar view and is connected to each other through via 191 provided in the overlapping region. Wiring 113 overlaps with active region P12 in a planar view and is connected to each other through via 192 provided in the overlapping region. Wiring 114 overlaps with active region P13 in a planar view and is connected to each other through via 193 provided in the overlapping region. Wiring 115 overlaps with active region P14 in a planar view and is connected to each other through via 194 provided in the overlapping region. Therefore, since the active regions (transistors) and the bit lines can be arranged to overlap, the wiring width of the bit lines can be increased and the wiring resistance of the bit lines can be reduced. This can improve the operating speed of the semiconductor memory device.

[0143] In addition, P-type active regions P11 to P14 are formed in the lower part of the cell. N-type active regions N11 to N14 are formed in the upper part of the cell. As a result, only P-type nanosheet transistors are formed in the lower part of the cell, and only N-type nanosheet transistors are formed in the upper part of the cell, which makes it possible to suppress the complexity of the manufacturing process of the semiconductor memory device and reduce manufacturing costs. Furthermore, since it is not necessary to arrange the P-type nanosheet transistor and the N-type nanosheet transistor at a distance, the area of ​​the semiconductor memory device can be reduced.

[0144] In this embodiment, the widths of the nanosheets 129 and 130 in the X direction are smaller than the widths of the nanosheets 121 to 128 and 130a to 130d in the X direction. The nanosheets 129 and 130 are arranged overlapping the nanosheets 124 and 125 in the Z direction. That is, in this embodiment, nanosheets with different widths in the X direction are stacked in the Z direction. The method for manufacturing a semiconductor memory device in FIG. 8 allows nanosheets with different widths in the X direction to be stacked in the Z direction.

[0145] Furthermore, no nanosheets are formed above the nanosheets 123 and 126 in the Z direction. That is, in this embodiment, no nanosheets are formed above the cells, and nanosheets are formed only below the cells. In this case, in the method for manufacturing the semiconductor memory device of FIG. 8, by not forming the mask 242 above the stacked semiconductor 210 in FIG. 8(b), nanosheets can be formed only below the cells.

[0146] In the above-described embodiments and modifications, each transistor is provided with two nanosheets, but some or all of the transistors may be provided with one nanosheet or three or more nanosheets.

[0147] In addition, in the above-described embodiments and modifications, the cross-sectional shape of the nanosheet is rectangular, but this is not limited to this and may be, for example, square, circular, elliptical, or the like.

[0148] In addition, in each of the above-described embodiments and modifications, the shared contacts 51, 53, 151, 153 may be manufactured in the same process as the contacts (gate-contacts) and local wiring, or may be manufactured in a separate process.

[0149] Furthermore, in each of the above-described embodiments and variations, the power supply that supplies the power supply voltage VDD to the sources of the drive transistors PU1 and PU2 is not limited to a power supply supplied from outside the semiconductor integrated circuit, but may be a power supply generated inside the semiconductor integrated circuit or a power supply generated inside the semiconductor memory device.

[0150] According to the present disclosure, in a layout structure of an SRAM cell using a CFET, it is possible to improve the operating speed of a semiconductor memory device, reduce manufacturing costs, and reduce the area of ​​the semiconductor memory device.

[0151] 11, 61, 111, 161 Power supply wiring 91 to 98, 191 to 194 Vias 21 to 28, 23a to 23c, 24a to 24c, 27a to 27d, 28a to 28d, 30a to 30h, 121 to 130, 130a to 130d Nanosheets 31 to 36, 131 to 136 Gate wiring 12, 13, 62 to 65 Wiring PU1, PU2 Drive transistor (load transistor) PD1, PD2 Load transistor (drive transistor) PU11, PU12, PU21, PU22, PD11, PD12, PD21, PD22 Transistors PG1 to PG4 Access transistors DP1 to DP6, DN1 to DN6, DN11 to DN14 Dummy transistors BLA First bit line BLAX Second bit line BLB Third bit line BLBX Fourth bit line WLA First word line WLB Second word line

Claims

1. A semiconductor memory device including an SRAM cell, wherein the SRAM cell comprises: a first transistor having a source connected to a first power supply that supplies a first power supply voltage, a drain connected to a first node, and a gate connected to a second node; a second transistor having a source connected to the first power supply, a drain connected to the second node, and a gate connected to the first node; a third transistor having a source connected to a first bit line, a drain connected to the first node, and a gate connected to a first word line; a fourth transistor having a source connected to a second bit line that forms a first complementary bit line pair with the first bit line, a drain connected to the second node, and a gate connected to the first word line; a fifth transistor having a source connected to the third bit line, a drain connected to the first node, and a gate connected to the second word line; and a sixth transistor having a source connected to a fourth bit line that forms a second complementary bit line pair with the third bit line, a drain connected to the second node, and a gate connected to the second word line. the SRAM cell comprises: a seventh transistor having a source connected to a second power supply that supplies a second power supply voltage different from the first power supply voltage, a drain connected to the first node, and a gate connected to the second node; and an eighth transistor having a source connected to the second power supply, a drain connected to the second node, and a gate connected to the first node, wherein the first to sixth transistors are transistors of a first conductivity type, and the seventh and eighth transistors are transistors of a second conductivity type different from the first conductivity type; the SRAM cell comprises: a first active region constituting the channel, source, and drain of the third transistor, the channel including a third nanosheet extending in a first direction, and constituting the channel, source, and drain of the fifth transistor, the channel including a fifth nanosheet extending in the first direction; a second active region constituting the channel, source, and drain of the first transistor, the channel including the first nanosheet extending in the first direction; and a third active region constituting the channel, source, and drain of the second transistor, the channel including the second nanosheet extending in the first direction.a fourth active region constituting the channel, source, and drain of the fourth transistor, the channel being a fourth nanosheet extending in the first direction, and constituting the channel, source, and drain of the sixth transistor, the channel being a sixth nanosheet extending in the first direction; a fifth active region formed higher than the first to fourth active regions in the depth direction, constituting the channel, source, and drain of the seventh transistor, the channel being a seventh nanosheet extending in the first direction; a sixth active region formed higher than the first to fourth active regions in the depth direction, constituting the channel, source, and drain of the eighth transistor, the channel being an eighth nanosheet extending in the first direction; a first power supply wiring formed in a back wiring layer that is a wiring layer on the back side of the first to eighth transistors, extending in the first direction, overlapping with the second and third active regions in a plan view, and connected to the first power supply; a first via formed in a region where a region that becomes the source of the first transistor in the second active region overlaps with the first power supply wiring, connecting the source of the first transistor in the second active region with the first power supply wiring; and a second via formed in a region where a region that becomes the source of the second transistor in the third active region overlaps with the first power supply wiring, connecting the source of the second transistor in the third active region with the first power supply wiring, wherein the first and seventh nanosheets overlap in a planar view, and the second and eighth nanosheets overlap in a planar view.

2. A semiconductor memory device according to claim 1, wherein the first and seventh nanosheets have the same width in a second direction perpendicular to the first direction and the depth direction, and the second and eighth nanosheets have the same width in the second direction.

3. A semiconductor memory device according to claim 1, wherein the seventh nanosheet has a smaller width in a second direction perpendicular to the first direction and the depth direction than the first nanosheet, and the eighth nanosheet has a smaller width in the second direction than the second nanosheet.

4. A semiconductor memory device according to claim 1, wherein the first bit line is formed in a metal wiring layer above the first to eighth transistors and includes a first wiring extending in the first direction; the second bit line is formed in the metal wiring layer and includes a second wiring extending in the first direction; the third bit line is formed in the metal wiring layer and includes a third wiring extending in the first direction; and the fourth bit line is formed in the metal wiring layer and includes a fourth wiring extending in the first direction.

5. A semiconductor memory device according to claim 1, wherein the first bit line is formed in a metal wiring layer above the first to eighth transistors and includes a first wiring extending in the first direction; the second bit line is formed in the metal wiring layer and includes a second wiring extending in the first direction; the third bit line is formed in the backside wiring layer and includes a third wiring extending in the first direction; the fourth bit line is formed in the backside wiring layer and includes a fourth wiring extending in the first direction; and the SRAM cell comprises: a third via formed in a region in the first active region where a region serving as the source of the fifth transistor overlaps with the third wiring, connecting the source of the fifth transistor in the first active region with the third wiring; and a fourth via formed in a region in the fourth active region where a region serving as the source of the sixth transistor overlaps with the fourth wiring, connecting the source of the sixth transistor in the fourth active region with the fourth wiring.

6. A semiconductor memory device according to claim 1, wherein the first transistor further includes a ninth transistor of the first conductivity type, and the second transistor further includes a tenth transistor of the first conductivity type, and the SRAM cell comprises: a seventh active region formed in the same layer as the first to fourth active regions, constituting the channel, source, and drain of the ninth transistor, the channel including a ninth nanosheet extending in the first direction; an eighth active region formed in the same layer as the first to fourth active regions, constituting the channel, source, and drain of the tenth transistor, the channel including a tenth nanosheet extending in the first direction; and a ninth active region formed in the same layer as the fifth and sixth active regions, constituting the channel, source, and drain of a first dummy transistor of the second conductivity type, the channel including an eleventh nanosheet extending in the first direction. a tenth active region formed in the same layer as the fifth and sixth active regions, constituting the channel, source, and drain of the second conductivity type second dummy transistor, the channel including a twelfth nanosheet extending in the first direction; a fifth via formed in a region in the seventh active region where a region serving as the source of the ninth transistor overlaps with the first power supply wiring, connecting the source of the ninth transistor in the seventh active region with the first power supply wiring; and a sixth via formed in a region in the eighth active region where a region serving as the source of the tenth transistor overlaps with the first power supply wiring, connecting the source of the tenth transistor in the eighth active region with the first power supply wiring, wherein the first and seventh nanosheets have the same width in a second direction perpendicular to the first direction and the depth direction, the second and eighth nanosheets have the same width in the second direction, and the ninth and eleventh nanosheets overlap in a plan view and have the same width in the second direction. The tenth and twelfth nanosheets overlap in a planar view and have the same width in the second direction.

7. In the semiconductor memory device according to claim 1, the SRAM cell comprises: an eleventh active region formed in the same layer as the fifth and sixth active regions, constituting the channel, source, and drain of the third dummy transistor of the second conductivity type, the channel being a thirteenth nanosheet extending in the first direction, and constituting the channel, source, and drain of the fourth dummy transistor of the second conductivity type, the channel including a fourteenth nanosheet extending in the first direction; and a twelfth active region formed in the same layer as the fifth and sixth active regions, constituting the channel, source, and drain of the fifth dummy transistor of the second conductivity type, the channel being a fifteenth nanosheet extending in the first direction, and constituting the channel, source, and drain of the sixth dummy transistor of the second conductivity type, the channel including a sixteenth nanosheet extending in the first direction, wherein the third and thirteenth nanosheets overlap in a plan view and have the same width in a second direction perpendicular to the first direction and the depth direction. The fifth and fourteenth nanosheets overlap in a planar view and have the same width in the second direction; the fourth and fifteenth nanosheets overlap in a planar view and have the same width in the second direction; and the sixth and sixteenth nanosheets overlap in a planar view and have the same width in the second direction.

8. A semiconductor memory device including an SRAM cell, wherein the SRAM cell comprises: a first transistor having a source connected to a first power supply that supplies a first power supply voltage, a drain connected to a first node, and a gate connected to a second node; a second transistor having a source connected to the first power supply, a drain connected to the second node, and a gate connected to the first node; a third transistor having a source connected to a first bit line, a drain connected to the first node, and a gate connected to a first word line; a fourth transistor having a source connected to a second bit line that forms a first complementary bit line pair with the first bit line, a drain connected to the second node, and a gate connected to the first word line; a fifth transistor having a source connected to the third bit line, a drain connected to the first node, and a gate connected to the second word line; and a sixth transistor having a source connected to a fourth bit line that forms a second complementary bit line pair with the third bit line, a drain connected to the second node, and a gate connected to the second word line. the SRAM cell comprises: a seventh transistor having a source connected to a second power supply that supplies a second power supply voltage different from the first power supply voltage, a drain connected to the first node, and a gate connected to the second node; and an eighth transistor having a source connected to the second power supply, a drain connected to the second node, and a gate connected to the first node, wherein the first and second transistors are transistors of a first conductivity type, and the third to eighth transistors are transistors of a second conductivity type different from the first conductivity type, and the SRAM cell comprises: a first active region constituting the channel, source, and drain of the first transistor, the channel including a first nanosheet extending in a first direction; and a second active region constituting the channel, source, and drain of the second transistor, the channel including a second nanosheet extending in the first direction.a third active region formed higher in the depth direction than the first and second active regions, constituting the channel, source, and drain of the third transistor, the channel including a third nanosheet extending in the first direction, and constituting the channel, source, and drain of the fifth transistor, the channel including a fifth nanosheet extending in the first direction; a fourth active region formed higher in the depth direction than the first and second active regions, constituting the channel, source, and drain of the seventh transistor, the channel including a seventh nanosheet extending in the first direction; a fifth active region formed higher in the depth direction than the first and second active regions, constituting the channel, source, and drain of the eighth transistor, the channel including an eighth nanosheet extending in the first direction; a sixth active region formed higher than the first and second active regions in the depth direction, and constituting the channel, source, and drain of the fourth transistor, the channel including a fourth nanosheet extending in the first direction as the channel, and a sixth nanosheet forming the channel, source, and drain of the sixth transistor, the channel including a sixth nanosheet extending in the first direction as the channel; a first power supply wiring formed in a back wiring layer that is a wiring layer on the back side of the first to eighth transistors, extending in the first direction, overlapping with the first and second active regions in a plan view, and connected to the first power supply; a first via formed in a region in the first active region where a region that becomes the source of the first transistor overlaps with the first power supply wiring, and connecting the source of the first transistor in the first active region with the first power supply wiring; and a second via formed in a region in the second active region where a region that becomes the source of the second transistor overlaps with the first power supply wiring, and connecting the source of the second transistor in the second active region with the first power supply wiring, the first and seventh nanosheets overlap in plan view,A semiconductor memory device, wherein the second and eighth nanosheets overlap in a planar view.

9. A semiconductor memory device according to claim 8, wherein the first and seventh nanosheets have the same width in a second direction perpendicular to the first direction and the depth direction, and the second and eighth nanosheets have the same width in the second direction.

10. A semiconductor memory device according to claim 8, wherein the first bit line is formed in a metal wiring layer above the first to eighth transistors and includes a first wiring extending in the first direction; the second bit line is formed in the metal wiring layer and includes a second wiring extending in the first direction; the third bit line is formed in the metal wiring layer and includes a third wiring extending in the first direction; and the fourth bit line is formed in the metal wiring layer and includes a fourth wiring extending in the first direction.

11. A semiconductor memory device according to claim 8, wherein the first bit line is formed in a metal wiring layer above the first to eighth transistors and includes a first wiring extending in the first direction; the second bit line is formed in the metal wiring layer and includes a second wiring extending in the first direction; the third bit line is formed in the back wiring layer and includes a third wiring extending in the first direction; and the fourth bit line is formed in the back wiring layer and includes a fourth wiring extending in the first direction.

12. A semiconductor memory device according to claim 8, wherein the seventh transistor further includes a ninth transistor of the second conductivity type, and the eighth transistor further includes a tenth transistor of the second conductivity type, and the SRAM cell comprises: a seventh active region formed in the same layer as the third to sixth active regions, constituting the channel, source, and drain of the ninth transistor, the channel including a ninth nanosheet extending in the first direction; an eighth active region formed in the same layer as the third to sixth active regions, constituting the channel, source, and drain of the tenth transistor, the channel including a tenth nanosheet extending in the first direction; and a ninth active region formed in the same layer as the first and second active regions, constituting the channel, source, and drain of a first dummy transistor of the first conductivity type, the channel including an eleventh nanosheet extending in the first direction. a tenth active region formed in the same layer as the first and second active regions, constituting the channel, source, and drain of the second dummy transistor of the first conductivity type, and including a twelfth nanosheet extending in the first direction as the channel; wherein the first and seventh nanosheets have the same width in a second direction perpendicular to the first direction and the depth direction; the second and eighth nanosheets have the same width in the second direction; the ninth and eleventh nanosheets overlap in a planar view and have the same width in the second direction; and the tenth and twelfth nanosheets overlap in a planar view and have the same width in the second direction.

13. In the semiconductor memory device according to claim 8, the SRAM cell comprises: an eleventh active region formed in the same layer as the first and second active regions, constituting the channel, source, and drain of the third dummy transistor of the first conductivity type, the channel being a thirteenth nanosheet extending in the first direction, and constituting the channel, source, and drain of the fourth dummy transistor of the first conductivity type, the channel being a fourteenth nanosheet extending in the first direction; and a twelfth active region formed in the same layer as the first and second active regions, constituting the channel, source, and drain of the fifth dummy transistor of the first conductivity type, the channel being a fifteenth nanosheet extending in the first direction, and constituting the channel, source, and drain of the sixth dummy transistor of the first conductivity type, the channel being a sixteenth nanosheet extending in the first direction, wherein the third and thirteenth nanosheets overlap in a plan view and have the same width in a second direction perpendicular to the first direction and the depth direction. The fifth and fourteenth nanosheets overlap in a planar view and have the same width in the second direction; the fourth and fifteenth nanosheets overlap in a planar view and have the same width in the second direction; and the sixth and sixteenth nanosheets overlap in a planar view and have the same width in the second direction.

14. A semiconductor memory device including an SRAM cell, wherein the SRAM cell comprises: a first transistor having a source connected to a first power supply that supplies a first power supply voltage, a drain connected to a first node, and a gate connected to a second node; a second transistor having a source connected to the first power supply, a drain connected to the second node, and a gate connected to the first node; a third transistor having a source connected to a first bit line, a drain connected to the first node, and a gate connected to a first word line; a fourth transistor having a source connected to a second bit line that forms a first complementary bit line pair with the first bit line, a drain connected to the second node, and a gate connected to the first word line; a fifth transistor having a source connected to the third bit line, a drain connected to the first node, and a gate connected to the second word line; and a sixth transistor having a source connected to a fourth bit line that forms a second complementary bit line pair with the third bit line, a drain connected to the second node, and a gate connected to the second word line. the SRAM cell comprises: a seventh transistor having a source connected to a second power supply that supplies a second power supply voltage different from the first power supply voltage, a drain connected to the first node, and a gate connected to the second node; and an eighth transistor having a source connected to the second power supply, a drain connected to the second node, and a gate connected to the first node; the first transistor includes a ninth and tenth transistor; the second transistor includes an eleventh and twelfth transistor; the third to sixth and ninth to twelfth transistors are transistors of a first conductivity type; and the seventh and eighth transistors are transistors of a second conductivity type different from the first conductivity type; and the SRAM cell comprises: a first active region including a third nanosheet that forms a channel, a source, and a drain of the third transistor and extends in a first direction as the channel, and a ninth nanosheet that forms a channel, a source, and a drain of the ninth transistor and extends in the first direction as the channel;a second active region constituting the channel, source, and drain of the fifth transistor, the channel being a fifth nanosheet extending in the first direction, and constituting the channel, source, and drain of the tenth transistor, the channel being a tenth nanosheet extending in the first direction; a third active region constituting the channel, source, and drain of the fourth transistor, the channel being a fourth nanosheet extending in the first direction, and constituting the channel, source, and drain of the eleventh transistor, the channel being an eleventh nanosheet extending in the first direction; a fourth active region constituting the channel, source, and drain of the sixth transistor, the channel being a sixth nanosheet extending in the first direction, and constituting the channel, source, and drain of the twelfth transistor, the channel being a twelfth nanosheet extending in the first direction; a fifth active region formed higher in the depth direction than the first to fourth active regions, and constituting the channel, source, and drain of the seventh transistor, the channel being a seventh nanosheet extending in the first direction; a sixth active region formed higher than the first to fourth active regions in the depth direction, constituting the channel, source, and drain of the eighth transistor, the sixth active region including an eighth nanosheet extending in the first direction as the channel; the third and ninth nanosheets being arranged side by side in the first direction; the fifth and tenth nanosheets being arranged side by side in the first direction; the fourth and eleventh nanosheets being arranged side by side in the first direction; the sixth and twelfth nanosheets being arranged side by side in the first direction; and the seventh and tenth nanosheets overlapping in a planar view.

15. A semiconductor memory device according to claim 14, wherein the SRAM cell comprises a first power supply wiring formed in a back wiring layer which is a wiring layer on the back side of the third to sixth and ninth to twelfth transistors.

16. A semiconductor memory device according to claim 14, wherein the first bit line is formed in a back wiring layer that is a wiring layer on the back side of the third to sixth and ninth to twelfth transistors, and includes a first wiring extending in the first direction; the second bit line is formed in the back wiring layer and includes a second wiring extending in the first direction; the third bit line is formed in the back wiring layer and includes a third wiring extending in the first direction; the fourth bit line is formed in the back wiring layer and includes a fourth wiring extending in the first direction; and the SRAM cell comprises: a first via formed in a region in the first active region where a region that will become the source of the third transistor overlaps with the first wiring, and connecting the source of the third transistor in the first active region with the first wiring; and a second via formed in a region in the second active region where a region that will become the source of the fifth transistor overlaps with the third wiring, and connecting the source of the fifth transistor in the second active region with the third wiring. a third via formed in a region in the third active region where a region that will become a source of the fourth transistor overlaps with the second wiring, connecting the source of the fourth transistor in the third active region to the second wiring; and a fourth via formed in a region in the fourth active region where a region that will become a source of the sixth transistor overlaps with the fourth wiring, connecting the source of the sixth transistor in the fourth active region to the fourth wiring.

17. A semiconductor memory device according to claim 14, wherein the tenth nanosheet has a width in a second direction perpendicular to the first direction and the depth direction that is greater than that of the seventh nanosheet, and the eleventh nanosheet has a width in the second direction that is greater than that of the eighth nanosheet.

18. In the semiconductor memory device according to claim 14, the SRAM cell comprises: a seventh active region formed in the same layer as the fifth and sixth active regions, constituting the channel, source, and drain of the first dummy transistor of the second conductivity type, the channel being a thirteenth nanosheet extending in the first direction, and constituting the channel, source, and drain of the second dummy transistor of the second conductivity type, the channel being a fourteenth nanosheet extending in the first direction; and an eighth active region formed in the same layer as the fifth and sixth active regions, constituting the channel, source, and drain of the third dummy transistor of the second conductivity type, the channel being a fifteenth nanosheet extending in the first direction, and constituting the channel, source, and drain of the fourth dummy transistor of the second conductivity type, the channel being a sixteenth nanosheet extending in the first direction, wherein the third and thirteenth nanosheets overlap in a plan view and have the same width in a second direction perpendicular to the first direction and the depth direction. A semiconductor memory device, wherein the ninth and fourteenth nanosheets overlap in a planar view and have the same width in the second direction.

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