Memory device

Abstract

The present disclosure relates to the technical field of semiconductor chips, and provides a memory device, aiming to improve the storage density of the memory device. The memory device comprises a first stacked structure, a second stacked structure, first connection structures, and bit lines. The first stacked structure comprises a plurality of first gate layers and a plurality of first dielectric layers alternately stacked in a first direction. The second stacked structure comprises a plurality of second gate layers and a plurality of second dielectric layers alternately stacked in the first direction. The first connection structures are located on one side of each of the first stacked structure and the second stacked structure in a second direction, the first connection structures are connected to at least one first gate layer, and the first connection structures are connected to at least one second gate layer. The bit lines are located between the first stacked structure and the second stacked structure, and the extension direction of the bit lines intersects the first direction. By means of the arrangement, one first gate layer and one second gate layer share one first connection structure, which is conducive to improving the storage density of the memory device.

Description

Memory device TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of semiconductor chip, and in particular, to a memory device. BACKGROUND

[0002] As the feature size of the memory cell approaches the lower limit of the process, the planar process and manufacturing technology become challenging and costly, which causes the storage density of 2D or planar NAND flash memory to approach the upper limit.

[0003] To overcome the limitations of 2D or planar NAND flash memory, the industry has developed a memory with a three-dimensional structure (3D NAND) to improve the storage density by arranging the memory cells three-dimensionally above the substrate.

[0004] SUMMARY

[0005] In one aspect, some embodiments of the present disclosure provide a memory device, comprising: a first stack structure, a second stack structure, a first connection structure, and a bit line. The first stack structure comprises a plurality of first gate layers and a plurality of first dielectric layers alternately stacked along a first direction; the second stack structure comprises a plurality of second gate layers and a plurality of second dielectric layers alternately stacked along the first direction, and the second stack structure is stacked along the first direction with the first stack structure; the first connection structure is located on one side of the first stack structure and the second stack structure along a second direction, the first connection structure is connected with at least one of the first gate layers, and the first connection structure is connected with at least one of the second gate layers, and the second direction intersects the first direction; the bit line is located between the first stack structure and the second stack structure, and the extension direction of the bit line intersects the first direction.

[0006] In some embodiments, the first connection structure comprises a first connection sub-portion and a second connection sub-portion stacked along the first direction; the first connection sub-portion comprises a first connection column and at least one first connection layer; the first connection column extends along the first direction, and the first connection layer is parallel to the second direction, and one first connection layer connects the first connection column and one first gate layer; the second connection sub-portion comprises a second connection column and at least one second connection layer; the second connection column extends along the first direction and is connected with the first connection column; the second connection layer is parallel to the second direction, and one second connection layer connects the second connection column and one second gate layer.

[0007] In some embodiments, the first connection sub-portion and the second connection sub-portion are an integral structure.

[0008] In some embodiments, in the second direction, a dimension of the first connecting post near an end of the second connecting post is greater than a dimension of the second connecting post near an end of the first connecting post.

[0009] In some embodiments, in the second direction, a dimension of the first connecting post near an end of the second connecting post is greater than a dimension of the first connecting post away from an end of the second connecting post; and / or, in the second direction, a dimension of the second connecting post away from an end of the first connecting post is greater than a dimension of the second connecting post near an end of the first connecting post.

[0010] In some embodiments, the first connecting structure further comprises a first isolation layer and a second isolation layer; the first isolation layer is located on a side of the first connecting layer near the second connecting layer, and the first isolation layer is arranged around the first connecting post; the second isolation layer is located on a side of the second connecting layer away from the first connecting layer, and the second isolation layer is arranged around the second connecting post.

[0011] In some embodiments, a dimension of the first isolation layer away from an end of the first connecting layer in the second direction is greater than a dimension of the first isolation layer near an end of the first connecting layer in the second direction.

[0012] In some embodiments, the first connecting structure further comprises a third isolation layer and a fourth isolation layer; the third isolation layer is located on a side of the first connecting layer away from the first isolation layer; the third isolation layer is in contact with the first connecting post and the third isolation layer is arranged around the first connecting post; the fourth isolation layer is located on a side of the second connecting layer away from the second isolation layer; the fourth isolation layer is in contact with the second connecting post and the fourth isolation layer is arranged around the second connecting post.

[0013] In some embodiments, the first connecting layer comprises a first sub-layer and a second sub-layer arranged in a stack along the first direction, the first sub-layer is located between the first isolation layer and the second sub-layer, and the first isolation layer is arranged around the first sub-layer.

[0014] In some embodiments, further comprising: a third connecting layer arranged around the connecting post and connected with the first connecting post, in the first direction, an edge of a side of the third connecting layer away from the first isolation layer is connected with the first connecting layer; the first connecting layer is arranged around the third connecting layer, and the first connecting layer is connected with the first gate layer.

[0015] In some embodiments, the first isolation layer includes a first sub-isolation layer, a second sub-isolation layer, and a third sub-isolation layer; the first sub-isolation layer is disposed around the connecting column; the second sub-isolation layer is between the first sub-isolation layer and the connecting column, and the second sub-isolation layer is disposed around the connecting column; the third sub-isolation layer is between the second sub-isolation layer and the connecting column, and the third sub-isolation layer is disposed around the connecting column.

[0016] In some embodiments, the third connecting layer extends towards the second sub-isolation layer near the edge of one side of the second sub-isolation layer.

[0017] In some embodiments, further comprising a first select gate, a second select gate, a third select gate, and a fourth select gate; the first select gate is on one side of the first stack structure away from the second stack structure; the second select gate is on one side of the first stack structure near the second stack structure; the third select gate is on one side of the second stack structure near the first stack structure; the bit line connects the second select gate and the third select gate; and the fourth select gate is on one side of the second stack structure away from the first stack structure.

[0018] In some embodiments, the first stack structure includes a first sub-stack structure and a second sub-stack structure stacked along the first direction; a first channel structure penetrating the first sub-stack structure; and a second channel structure penetrating the second sub-stack structure; the first channel structure is between the first select gate and the second select gate.

[0019] In some embodiments, the memory device includes a first region and a second region, the first region is adjacent to the second region, the first stack structure and the second stack structure are both in the first region, and the first connecting structure is in the second region; the second region is on one side of the first region; or, the first region includes a first sub-region and a second sub-region, and the second region is between the first sub-region and the second sub-region.

[0020] In some embodiments, further comprising a third stack structure and a fourth stack structure stacked along the first direction, the third stack structure and the fourth stack structure are both located in the second region; the first connecting column penetrates the third stack structure, the third stack structure comprises a plurality of third dielectric layers and a plurality of fourth dielectric layers alternately stacked along the first direction, at least one of the third dielectric layers is connected with at least one of the first connecting layers; the second connecting column penetrates the fourth stack structure, the fourth stack structure comprises a plurality of fifth dielectric layers and a plurality of sixth dielectric layers alternately stacked along the first direction, at least one of the fifth dielectric layers is connected with at least one of the second connecting layers.

[0021] In some embodiments, further comprising a second connecting structure; the second connecting structure is located at one side of the first stack structure and the second stack structure along the second direction; one of the first selection gate and the second selection gate is connected with the second connecting structure.

[0022] In some embodiments, further comprising a second connecting structure; the second connecting structure is located at one side of the first stack structure and the second stack structure along the second direction; one of the first selection gate and the second selection gate is connected with the second connecting structure.

[0023] In some embodiments, further comprising a first selection gate, a second selection gate, a third selection gate, a fourth selection gate and a second connecting structure; the first selection gate is located at one side of the first stack structure away from the second stack structure; the second selection gate is located at one side of the first stack structure close to the second stack structure; the third selection gate is located at one side of the second stack structure close to the first stack structure; the fourth selection gate is located at one side of the second stack structure away from the first stack structure; the second connecting structure is located at one side of the first stack structure and the second stack structure along the second direction; one of the first selection gate, the second selection gate, the third selection gate and the fourth selection gate is connected with the second connecting structure.

[0024] In some embodiments, further comprising: a first bit line and a second bit line, the first bit line is located at a side of the first select gate away from the first stack structure, and the second bit line is located at a side of the fourth select gate away from the first stack structure; the extension direction of the first bit line and the second bit line intersects with the first direction.

[0025] In some embodiments, the memory device comprises a first region and a second region, the first region and the second region are adjacent in the second direction, the first stack structure and the second stack structure are both located in the first region, and the first connection structure is located in the second region; the second region is located at a side of the first region; or, the first region comprises a first sub-region and a second sub-region, and the second region is located between the first sub-region and the second sub-region.

[0026] In another aspect, some embodiments of the present disclosure further provide a memory device, comprising: a first stack structure and a second stack structure, a first select gate and a second select gate, and a bit line, which are stacked along a first direction. The first stack structure comprises a plurality of first gate layers and a plurality of first dielectric layers which are alternately stacked along the first direction, and the second stack structure comprises a plurality of second gate layers and a plurality of second dielectric layers which are alternately stacked along the first direction; the first select gate is located at a side of the first stack structure close to the second stack structure, and the second select gate is located at a side of the second stack structure close to the first stack structure; the bit line is located between the first select gate and the second select gate, and the extension direction of the bit line intersects with the first direction.

[0027] In some embodiments, further comprising: a first connection structure; the first connection structure is located at a side of the first stack structure and the second stack structure along a second direction, the first connection structure is connected with at least one of the first gate layers, and the first connection structure is connected with at least one of the second gate layers, and the second direction intersects with the first direction.

[0028] In some embodiments, further comprising: a third select gate, a fourth select gate, and a second connection structure, the third select gate is located at a side of the first stack structure away from the second stack structure, and the fourth select gate is located at a side of the second stack structure away from the first stack structure; the second connection structure is located at a side of the first stack structure and the second stack structure along the second direction; one of the first select gate, the second select gate, the third select gate, and the fourth select gate is connected with the second connection structure. BRIEF DESCRIPTION OF DRAWINGS

[0029] In order to more clearly illustrate the technical solutions in the present disclosure, the following will briefly introduce the drawings needed to be used in some embodiments of the present disclosure. Obviously, the drawings in the following description only represent some embodiments of the present disclosure, and other drawings can also be obtained by those skilled in the art according to these drawings. In addition, the drawings in the following description can be regarded as schematic diagrams, and are not limited to the actual size, actual process, actual time sequence, etc. of the product, method, signal, etc. involved in the embodiments of the present disclosure.

[0030] FIG. 1 is a block diagram of an electronic device according to some embodiments;

[0031] FIG. 2 is a block diagram of a storage system according to some embodiments;

[0032] FIG. 3 is a block diagram of a storage system according to some other embodiments;

[0033] FIG. 4 is a perspective structural schematic diagram of a storage device according to some embodiments;

[0034] FIG. 5 is a sectional view of a storage device according to some embodiments;

[0035] FIG. 6 is a sectional view of a storage unit string along the section line AA' in the storage device shown in FIG. 4;

[0036] FIG. 7 is an equivalent circuit diagram of the storage unit string in FIG. 6;

[0037] FIG. 8 is a circuit schematic diagram of a storage device according to some embodiments;

[0038] FIG. 9 is a structural schematic diagram of a storage device according to some embodiments;

[0039] FIG. 10 is a structural schematic diagram of a storage device according to some other embodiments;

[0040] FIG. 11 is a structural schematic diagram of a storage device in a Y-Z section according to some embodiments;

[0041] FIG. 12 is a structural schematic diagram of a storage device in a Y-Z section according to some other embodiments;

[0042] FIGS. 13-15 are structural schematic diagrams of storage devices according to different embodiments;

[0043] FIG. 16 is a circuit schematic diagram of a storage device according to some other embodiments;

[0044] FIG. 17 is a structural schematic diagram of a storage device according to some other embodiments;

[0045] FIG. 18 is a flow chart of a preparation method of a storage device according to some embodiments;

[0046] FIGS. 19-43 are schematic diagrams of structures of a memory device during fabrication according to some embodiments;

[0047] FIG. 44 is a flow chart of a method of fabricating a memory device according to some other embodiments;

[0048] FIG. 45 is a flow chart of a method of fabricating a memory device according to some other embodiments;

[0049] FIG. 46 is a schematic diagram of structures of a memory device during fabrication according to some other embodiments. DETAILED DESCRIPTION

[0050] The technical solutions in the embodiments of the present disclosure will be clearly and completely described below with reference to the drawings. It should be apparent that the described embodiments are only a part of the embodiments of the present disclosure, and not all the embodiments. Based on the embodiments provided by the present disclosure, all other embodiments obtained by a person of ordinary skill in the art belong to the scope of protection of the present disclosure.

[0051] In the description of the present disclosure, it should be understood that the terms "center", "upper", "lower", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", and the like indicate the orientation or positional relationship shown in the drawings, and are only intended to facilitate the description of the present disclosure and simplify the description, and therefore cannot be understood as indicating or implying that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as a limitation on the present disclosure.

[0052] Unless otherwise required by context, the term "comprises" in the specification and claims is to be construed as an open, inclusive meaning, i.e., "including, but not limited to". In the description of the specification, the terms "one embodiment", "some embodiments", "exemplary embodiment", "exemplary", or "some examples" are intended to mean that a particular feature, structure, material, or characteristic included in at least one embodiment or example of the present disclosure. The illustrative representation of the above terms does not necessarily refer to the same embodiment or example. In addition, the specific features, structures, materials, or characteristics described can be included in any one or more embodiments or examples in any appropriate manner.

[0053] Hereinafter, the terms "first", "second" are used only for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Therefore, the features defined with "first", "second" can explicitly or implicitly include one or more features. In the description of the embodiments of the present disclosure, unless otherwise stated, the meaning of "a plurality of" is two or more.

[0054] In describing some embodiments, it will be understood that the terms "coupled" and "connected," along with derivatives thereof, can be used to describe either an electrical or a physical connection. In some embodiments, "connected" can be used to indicate that two or more elements are in direct physical or electrical contact. In some embodiments, "coupled" can be used to indicate that two or more elements are in either physical or electrical contact, whether or not directly. The embodiments disclosed herein are not necessarily limited in terms of the particular nature of the connection between the elements.

[0055] "at least one of A, B, and C" has the same meaning as "at least one of A, B, or C" and includes the following combinations: only A, only B, only C, a combination of A and B, a combination of A and C, a combination of B and C, and a combination of A, B, and C.

[0056] "A and / or B" includes the following combinations: A alone, B alone, and a combination of A and B.

[0057] The use of "adapted to" or "configured to" herein means open and inclusive language that does not exclude additional devices or steps not specifically recited.

[0058] Additionally, the use of "based on" means open and inclusive language that does not exclude additional conditions or values not specifically recited.

[0059] As used herein, "about," "approximately," or "around" includes the recited value and the average value within an acceptable range of deviation from the particular value, as determined by one of ordinary skill in the art considering the measurement being discussed and the error in measurement associated with the particular quantity being measured (i.e., the limitations of the measurement system).

[0060] In the present disclosure, the meaning of "on," "over," and "above" should be interpreted in the broadest reasonable manner, such that "on" means not only "directly on" but also includes the meaning of "on" with intervening features or layers therebetween, and "over" or "above" means not only "over" or "above" but also includes the meaning of "over" or "above" without intervening features or layers therebetween (i.e., directly on).

[0061] Exemplary embodiments are described herein with reference to cross-sectional and / or plan view illustrations that are schematic illustrations of idealized embodiments. Variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and / or tolerances, are to be expected. Thus, embodiments should not be construed as limited to the particular shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, an etched region illustrated as a rectangle will, typically, have jagged edges. Thus, the regions illustrated in the figures are schematic and their shapes are not intended to illustrate the precise shape of a region of a device and are not intended to limit the scope of an embodiment.

[0062] As used herein, the term "substrate" refers to a material on which a subsequent layer of material can be added. The substrate itself can be patterned. The material added on the substrate can be patterned or can remain unpatterned. Further, the substrate can include a variety of semiconductor materials such as silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate can be made of a non-conductive material such as glass, plastic, or sapphire wafer.

[0063] Some embodiments of the present disclosure provide an electronic device. FIG. 1 is a block diagram of an electronic device according to some embodiments. As shown in FIG. 1, the electronic device 3000 includes a mainboard 2000 and a storage system 1000, where the mainboard 2000 is electrically connected with the storage system 1000. In addition to this, the electronic device 3000 can further include at least one of a central processing unit (CPU) and a cache, etc.

[0064] Exemplarily, the electronic device 3000 can be any one of a mobile phone, a desktop computer, a tablet computer, a notebook computer, a server, a vehicle-mounted device, a wearable device (such as a smart watch, a smart bracelet, smart glasses, etc.), a mobile power supply, a game console, a digital multimedia player, etc.

[0065] FIG. 2 is a block diagram of a storage system according to some embodiments. FIG. 3 is a block diagram of a storage system according to other embodiments.

[0066] Referring to FIGS. 2 and 3, some embodiments of the present disclosure further provide a storage system 1000. The storage system 1000 includes a controller 20 and a storage device 10. Wherein the controller 20 is coupled with the storage device 10 to control the storage device 10 to store data.

[0067] The storage system 1000 can be integrated into various types of storage devices, for example, included in the same package (e.g., a Universal Flash Storage (UFS) package or an Embedded Multi Media Card (eMMC) package). That is, the storage system 1000 can be applied to and packaged into different types of electronic products, for example, a mobile phone (e.g., a cell phone), a desktop computer, a tablet computer, a notebook computer, a server, a vehicle-mounted device, a game console, a printer, a positioning device, a wearable device, a smart sensor, a mobile power supply, a Virtual Reality (VR) device, an Augmented Reality (AR) device, or any other suitable electronic device having a storage.

[0068] In some embodiments, referring to FIG. 2, the storage system 1000 includes a controller 20 and one memory device 10, and the storage system 1000 can be integrated into a memory card. Exemplarily, the memory device 10 can be a memory with a three-dimensional structure (3D NAND).

[0069] The memory card includes any one of a PC card (PCMCIA, Personal Computer Memory Card International Association), a Compact Flash (CF) card, a Smart Media (SM) card, a memory stick, a Multimedia Card (MMC), a Secure Digital Memory Card (SD card), or a UFS.

[0070] In other embodiments, referring to FIG. 3, the storage system 1000 includes a controller 20 and a plurality of memory devices 10, and the storage system 1000 is integrated into a Solid State Drives (SSD) device.

[0071] In the storage system 1000, in some embodiments, the controller 20 is configured to operate in a low duty cycle environment, for example, an SD card, a CF card, a Universal Serial Bus (USB) flash drive, or other media used in electronic devices such as personal computers, digital cameras, mobile phones, etc.

[0072] In other embodiments, the controller 20 is configured for operating in a high duty cycle environment SSD device or eMMC for data storage of mobile devices such as smart phones, tablets, laptops, etc. and enterprise storage arrays.

[0073] In some embodiments, the controller 20 can be configured to manage data stored in the memory device 10 and communicate with an external device (e.g., a host). In some embodiments, the controller 20 can also be configured to control operations of the memory device 10, such as read, erase, and program operations. In some embodiments, the controller 20 can also be configured to manage various functions related to data stored or to be stored in the memory device 10, including at least one of bad block management, garbage collection, logical to physical address translation, wear leveling. In some embodiments, the controller 20 is also configured to process error correction codes related to data read from or written to the memory device 10.

[0074] Of course, the controller 20 can also perform any other suitable functions, such as formatting the memory device 10; for example, the controller 20 can communicate with an external device (e.g., a host) through at least one of various interface protocols.

[0075] It is noted that the interface protocols include at least one of a USB protocol, an MMC protocol, a Peripheral Component Interconnect (PCI) protocol, a PCI Express (PCI-E) protocol, an Advanced Technology Attachment (ATA) protocol, a Serial ATA protocol, a Parallel ATA protocol, a Small Computer Small Interface (SCSI) protocol, an Enhanced Small Disk Interface (ESDI) protocol, an Integrated Drive Electronics (IDE) protocol, a Firewire protocol.

[0076] The controller 20 in the above embodiments can be, for example, a Central Processing Unit (CPU), a general-purpose processor, a Digital Signal Processor (DSP), an Application-Specific Integrated Circuit (ASIC), a Field Programmable Gate Array (FPGA) or other programmable logic device, a transistor logic device, a hardware component, or any combination thereof.

[0077] Some embodiments of the present disclosure provide a memory device 10. The memory device 10 can be applied in the above-mentioned storage system 1000, of course, the memory device 10 can also be applied in other storage systems, the present disclosure does not limit this.

[0078] FIG. 4 is a perspective structural schematic view of a memory device according to some embodiments, FIG. 5 is a cross-sectional view of the memory device according to some embodiments, FIG. 6 is a cross-sectional view of one memory cell string of the memory device in FIG. 4 along the cross-sectional line AA’, and FIG. 7 is an equivalent circuit diagram of the memory cell string in FIG. 6.

[0079] It is noted that in FIG. 4 and FIG. 5, the first direction X and the second direction Y can be two intersecting directions, and the third direction Z can be perpendicular to the X-Y plane. The disclosure is explained with the second direction Y and the third direction Z being two orthogonal directions in the plane where the semiconductor structure 200 is located (e.g., the plane where the semiconductor layer is located): the second direction Y is, for example, the extension direction of the word line WL, and the third direction Z is, for example, the extension direction of the bit line BL. The first direction X is perpendicular to the two orthogonal directions in the plane where the semiconductor structure 200 is located, i.e., perpendicular to the X-Y plane. The memory device 10 extends in the Y-Z plane.

[0080] As used in the disclosure, whether a component (e.g., a layer, structure, or device) is “on”, “above”, or “below” another component (e.g., a layer, structure, or device) of a semiconductor device (e.g., a memory device) is determined with respect to the semiconductor layer of the semiconductor device in the first direction X when the semiconductor layer is located in the lowest plane of the semiconductor device in the first direction X. Throughout the disclosure, the same concept is applied to describe the spatial relationship.

[0081] Referring to FIG. 4 and FIG. 5, some embodiments of the disclosure provide a memory device 10. The memory device 10 can include a semiconductor structure 200, and a peripheral device 100 coupled with the semiconductor structure 200. The peripheral device 100 can be disposed at one side of the semiconductor structure 200.

[0082] The semiconductor structure 200 can include a semiconductor layer. The constituent material of the semiconductor layer can include, for example, monocrystalline silicon, monocrystalline germanium, III-V compound semiconductor material, II-VI compound semiconductor material, and other semiconductor materials.

[0083] The semiconductor structure 200 can further include an array of memory cell transistor strings (referred to herein as “memory cell strings”, e.g., NAND memory cell strings) 400. The semiconductor layer can include a source layer SL, which can be coupled with the source ends of the plurality of memory cell strings 400. Exemplarily, the source layer SL can be partially or entirely doped. For example, the source layer SL can include a doped region, which is doped by a p-type dopant. The source layer can also include an undoped region.

[0084] Specifically, referring to FIG. 6 and FIG. 7, the memory cell string 400 can include a plurality of transistors T, one transistor T (e.g., T1-T6 in FIG. 7) can be configured as one memory cell, and the transistors T are connected together to form the memory cell string. One transistor T (e.g., each transistor T) can be formed by a channel structure 240 and a gate line G surrounding the channel structure 240. The gate line G is configured to control the conduction state of the transistor.

[0085] It should be noted that the number of transistors in FIG. 4-FIG. 7 is only illustrative, and the memory device provided by the embodiments of the present disclosure can also include other numbers of transistors, such as 4, 16, 32, 64.

[0086] Further, along the third direction Z, the lowermost gate line (e.g., the gate line closest to the source layer SL among the plurality of gate lines G) is configured as a source side select gate SGS, which is configured to control the conduction state of the transistor T6, and further control the conduction state of the source side channel in the memory cell string 400. The uppermost gate line (e.g., the gate line farthest from the source layer SL among the plurality of gate lines G) is configured as a drain side select gate SGD, which is configured to control the conduction state of the transistor T1, and further control the conduction state of the drain side channel in the memory cell string 400. The gate lines in the middle among the plurality of gate lines G can be configured as a plurality of word lines WL, such as word line WLO, word line WL1, word line WL2, and word line WL3. By writing different voltages on the word lines WL, data writing, reading, and erasing of each memory cell (e.g., transistor T) in the memory cell string 400 can be completed.

[0087] Continuing to refer to FIG. 4 and FIG. 5, in some embodiments, the semiconductor structure 200 can further include an array interconnection layer 300. The array interconnection layer 300 can be coupled with the memory cell string 400. The array interconnection layer 300 can include the drain end (i.e., the bit line BL) of the memory cell string 400, which can be coupled with the semiconductor channel of each transistor T in at least one memory cell string 400.

[0088] The array interconnect layer 300 can include one or more first interlayer insulating layers 292, and can further include a plurality of contacts insulated from each other by the first interlayer insulating layers 292, including, for example, bit line contacts BL-CNT coupled to bit lines BL, drain select gate contacts SGD-CNT coupled to drain select gates SGD, and gate line contacts G-CNT coupled to gate lines G. The array interconnect layer 300 can further include one or more first interconnect conductor layers 291. The first interconnect conductor layers 291 can include a plurality of connection lines, such as bit lines BL, and word line connection lines WL-CL coupled to word lines WL. The materials of the first interconnect conductor layers 291 and the contacts can be conductive materials, such as one or more of tungsten, cobalt, copper, aluminum, and metal silicides, and can be other conductive materials. The materials of the first interlayer insulating layers 292 can be insulating materials, such as one or more of silicon oxide, silicon nitride, and high-k insulating materials, and can be other insulating materials.

[0089] The peripheral device 100 can include a peripheral circuit. The peripheral circuit is configured to control and sense the array device. The peripheral circuit can be any suitable digital, analog, or mixed-signal control and sensing circuitry to support operation of the array device, including but not limited to page buffers, decoders (e.g., row and column decoders), sense amplifiers, drivers (e.g., word line drivers), charge pumps, current or voltage references, or any active or passive components (e.g., transistors, diodes, resistors, or capacitors) of the circuitry. The peripheral circuit can further include any other circuitry compatible with advanced logic processes, including logic circuitry (e.g., processors and programmable logic devices (PLDs)) or memory circuitry (e.g., static random-access memory (SRAM)).

[0090] In particular, in some embodiments, the peripheral device 100 can include a substrate 110, transistors 120 disposed on the substrate 110, and a peripheral interconnect layer 130 disposed on the substrate 110. The peripheral circuit can include the transistors 120.

[0091] The substrate 110 can be monocrystalline silicon, or can be other suitable materials, such as silicon germanium, germanium, or silicon-on-insulator thin film.

[0092] The peripheral interconnection layer 130 is coupled with the transistor 120 to enable transmission of electrical signals between the transistor 120 and the peripheral interconnection layer 130. The peripheral interconnection layer 130 can include one or more second interlayer insulating layers 131 and one or more second interconnection conductor layers 132. The different second interconnection conductor layers 132 can be coupled through contacts. The materials of the second interconnection conductor layers 132 and the contacts can be conductive materials, such as one or more of tungsten, cobalt, copper, aluminum, and metal silicides, or other suitable materials. The materials of the second interlayer insulating layers 131 can be insulating materials, such as one or more of silicon oxide, silicon nitride, and high-k insulating materials, or other suitable materials.

[0093] The peripheral interconnection layer 130 can be coupled with the array interconnection layer 300 so that the semiconductor structure 200 and the peripheral device 100 can be coupled. Specifically, because the peripheral interconnection layer 130 is coupled with the array interconnection layer 300, the peripheral circuit in the peripheral device 100 can be coupled with the memory cell string in the semiconductor structure 200 to enable transmission of electrical signals between the peripheral circuit and the memory cell string. In some possible implementations, a bonding interface 500 can be provided between the peripheral interconnection layer 130 and the array interconnection layer 300, through which the peripheral interconnection layer 130 and the array interconnection layer 300 can be bonded and coupled with each other.

[0094] At present, users pursue storage devices with large capacity and small size. Continuing to refer to FIG. 4, to improve the capacity of the storage device, the number of stacked layers of the gate line G is increasing. However, one gate line G is connected with one gate line contact G-CNT. As the number of layers of the gate line G increases, the number of gate line contacts G-CNT coupled with the gate line G also increases, and thus the area occupied by the gate line contact G-CNT increases, which leads to an increase in the size of the storage device in the second direction, and is not conducive to improving the storage density of the storage device and developing the storage device to a smaller size.

[0095] In addition, the gate line G is coupled with an SD device (String Driver) through the gate line contact G-CNT. However, one gate line contact G-CNT is connected with one SD device, and as the number of gate line contacts G-CNT increases, the number of SD devices also increases, and thus the area occupied by the SD device also increases, which is not conducive to developing the storage device to a smaller size.

[0096] In addition, as the number of stacked layers of the gate line G increases, the number of SD devices also increases, and to control the size of the storage device, how to reduce the size of the SD device is one of the problems to be solved in the field.

[0097] FIG. 8 is a circuit schematic diagram of a memory device according to some embodiments. FIG. 9 is a structural schematic diagram of a memory device according to some embodiments. As shown in FIGS. 8 and 9, a memory device 10 provided by some embodiments of the present disclosure includes a first stack structure 210, a second stack structure 220, a first connection structure 230, and a bit line BL.

[0098] The first stack structure 210 can be disposed on a semiconductor layer 600. Exemplarily, the first stack structure 210 can be in direct contact with the semiconductor layer 600. Exemplarily, the semiconductor layer 600 can include, for example, monocrystalline silicon, monocrystalline germanium, III-V compound semiconductor material, II-VI compound, and other suitable semiconductor materials.

[0099] The first stack structure 210 includes a plurality of first gate layers 211 and a plurality of first dielectric layers 212 alternately stacked along a first direction X. For example, the first gate layers 211 and the first dielectric layers 212 are alternately arranged along the first direction X, and are stacked to form a plurality of first gate layers 211 and a plurality of first dielectric layers 212 spaced from each other. It can also be understood that one first gate layer 211 and one first dielectric layer 212 together constitute a first gate structure pair, and the first stack structure 210 includes a plurality of first gate structure pairs stacked along the first direction X.

[0100] Exemplarily, the number of layers of the first gate layers 211 and the first dielectric layers 212 can be 4, 16, 32, 64, 128, 256, etc. The thickness (i.e., the size along the first direction X) of the first gate layers 211 can be substantially equal to the thickness of the first dielectric layers 212, or can be different. For example, the thickness of the first dielectric layers 212 can be greater than the thickness of the first gate layers 211.

[0101] Exemplarily, the first gate layers 211 can include a conductive material, which includes but is not limited to one or more of a combination of tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, silicide, or other suitable conductive materials. In some examples, the first gate layers 211 include a metal layer, such as a tungsten layer. In some examples, the first gate layers 211 include a doped polysilicon layer. The polysilicon can be doped to a desired doping concentration using a suitable dopant, so that the polysilicon can become a conductive material used as the first gate layers 211.

[0102] Exemplarily, the first dielectric layer 212 can include an insulating material, which can include one or more of a combination of silicon oxide, silicon nitride, silicon oxynitride, and high dielectric constant insulating material, or can also be other suitable insulating materials. Among them, the dielectric constant of silicon oxynitride is higher than that of silicon oxide, for example: the dielectric constant of silicon oxynitride is about 4-7, for example: 3.8, 4, 4.8, 5.3, 5.9, 6, 6.36, 6.88, 7, 7.2, etc. In some examples, the first dielectric layer 212 includes a silicon oxide layer. In some examples, the first dielectric layer 212 includes a silicon oxynitride layer.

[0103] Exemplarily, the thickness (i.e. the size along the first direction X) of the first gate layer 211 can be between 10 nm-50 nm, for example: 10 nm, 15 nm, 18.3 nm, 20 nm, 25 nm, 27.7 nm, 30 nm, 35 nm, 40 nm, 45 nm, 50 nm, etc. Similarly, the thickness (i.e. the size along the third direction Z) of the first dielectric layer 212 can be between 10 nm-50 nm, for example: 10 nm, 15 nm, 18.3 nm, 20 nm, 25 nm, 27.7 nm, 30 nm, 35 nm, 40 nm, 45 nm, 50 nm, etc. Among them, the first gate layer 211 can be a gate line G (see FIG. 6) around the memory cell string, and can extend laterally (i.e. along the second direction Y) as a word line WL (see FIG. 4).

[0104] The second stack structure 220 includes a plurality of second gate layers 221 and a plurality of second dielectric layers 222 alternately stacked along the first direction X, for example, the second gate layer 221 and the second dielectric layer 222 are alternately arranged along the first direction X, and the second gate layer 221 and the second dielectric layer 222 are alternately stacked.

[0105] It can be understood that the composition material, thickness and number of the second gate layer 221 and the second dielectric layer 222 can refer to the examples of the composition material, thickness and number of the first gate layer 211 and the first dielectric layer 212. The composition material, thickness and number of the second gate layer 221 and the first gate layer 211 can be the same or different, and the composition material, thickness and number of the second dielectric layer 222 and the first dielectric layer 212 can be the same or different.

[0106] And, as shown in FIG. 9, the second stack structure 220 is stacked with the first stack structure 210 along the first direction X. An isolation medium layer 770 is arranged between the first stack structure 210 and the second stack structure 220, and the thickness of the isolation medium layer 770 is much greater than the thickness of the first medium layer 212 (or the second medium layer 222) along the first direction X. For example, the thickness of the isolation medium layer 770 can be 2-10 times the thickness of the first medium layer 212 along the first direction X. For example, the thickness of the isolation medium layer 770 can be 2 times, 6 times, or 10 times the thickness of the first medium layer 212 along the first direction X. When the thickness of the isolation medium layer 770 approaches 2 times the thickness of the first medium layer 212, the spacing between the first stack structure 210 and the second stack structure 220 is small, which is conducive to improving the storage density of the memory device 10. When the thickness of the isolation medium layer 770 approaches 10 times the thickness of the first medium layer 212, it is conducive to improving the isolation effect between the first stack structure 210 and the second stack structure 220.

[0107] The composition of the isolation medium layer 770 can be the same as that of the first medium layer 212 (or the second medium layer 222). For example, the top layer of the first stack structure 210 (the layer closest to the second stack structure 220 in the first stack structure 210) can be the first medium layer 212. When forming the first medium layer 212 at the top of the first stack structure 210, the thickness of the first medium layer 212 at the top can be increased to serve as an isolation medium layer 770 between the first stack structure 210 and the second stack structure 220. Here, the thickened first medium layer 212 at the top can serve as the isolation medium layer 770 between the first stack structure 210 and the second stack structure 220. For example, the bottom layer of the second stack structure 220 (the layer closest to the first stack structure 210 in the second stack structure 220) can be the second medium layer 222. When forming the second medium layer 222 at the bottom of the second stack structure 220, the thickness of the second medium layer 222 at the bottom can be increased to serve as an isolation medium layer 770 between the first stack structure 210 and the second stack structure 220. Here, the thickened second medium layer 222 at the bottom can serve as the isolation medium layer 770 between the first stack structure 210 and the second stack structure 220.

[0108] In this embodiment, as shown in FIGS. 8 and 9, the first connection structure 230 is located on one side of the first stack structure 210 and the second stack structure 220 along the second direction Y. For example, the memory device 10 can include a first region 101 and a second region 102, and the first region 101 and the second region 102 are adjacent along the second direction Y. The first stack structure 210 and the second stack structure 220 can both be located in the first region 101, and the first connection structure 230 can be located in the second region 102.

[0109] The first connection structure 230 is used to connect the first gate layer 211 and the SD device, and is used to connect the second gate layer 221 and the SD device. Exemplarily, the constituent material of the first connection structure 230 can include a conductive material, which includes but is not limited to one or more of a combination of tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, silicide, or can also be other suitable conductive materials.

[0110] As shown in FIGS. 8 and 9, the first connection structure 230 is connected with at least one first gate layer 211, and the first connection structure 230 is connected with at least one second gate layer 221. For example, in FIG. 9, the first connection structure 230 is connected with one first gate layer 211 in the first stack structure 210, and the first connection structure 230 is connected with one second gate layer 221 in the second stack structure 220. One end of the first connection structure 230 away from the semiconductor layer 600 can be connected with an SD device, and the SD device can be electrically connected with at least one first gate layer 211 and at least one second gate layer 221 through the first connection structure 230.

[0111] It should be noted that the first connection structure 230 being connected with at least one first gate layer 211 can be understood as that the first connection structure 230 can be connected with one first gate layer 211, or the first connection structure 230 can be connected with a plurality of first gate layers 211. And the first connection structure 230 being connected with at least one second gate layer 221 can be understood as that the first connection structure 230 can be connected with one second gate layer 221, or the first connection structure 230 can be connected with a plurality of second gate layers 221. In the embodiment, the first connection structure 230 is connected with one first gate layer 211, and the first connection structure 230 is connected with one second gate layer 221, which are taken as examples for explanation.

[0112] In other embodiments, referring to FIGS. 4, 8 and 9, one first gate layer 211 is connected with one SD device through one gate line contact G-CNT, and one second gate layer 221 is connected with one SD device through one gate line contact G-CNT. There are a large number of gate line contacts G-CNT and SD devices, and the plurality of gate line contacts G-CNT are arranged in a stepped manner, which results in a large area occupied by the gate line contacts G-CNT and the SD devices, and is not conducive to improving the storage density of the memory device 10.

[0113] In the embodiment, referring to FIG. 8 and FIG. 9, one first gate layer 211 and one second gate layer 221 can share one first connection structure 230 and share one SD device. Then, when the memory device 10 has two stack structures (i.e. the first stack structure 210 and the second stack structure 220), compared to that one first gate layer 211 is connected with one SD device through one gate line contact G-CNT and one second gate layer 221 is connected with one SD device through one gate line contact G-CNT, the number of the first connection structure 230 in the embodiment is less than the number of the gate line contact G-CNT, the number of the SD device in the embodiment is also less, then the area occupied by the first connection structure 230 is less than the area occupied by the gate line contact G-CNT, at the same time, the area occupied by the SD device is also reduced, which is beneficial to improve the storage density of the memory device 10.

[0114] When the memory device 10 includes more stack structures, for example, the memory device 10 can include 4 stack structures, 6 stack structures or 8 stack structures or a plurality of stack structures, at this time, the first connection structure 230 can be connected with one gate layer in each of the plurality of stack structures. Through the above setting, even if more stack structures are increased, the number of the first connection structure 230 will not be increased, that is, the occupied area of the first connection structure 230 will not be increased, which is beneficial to improve the storage density of the memory device 10 and is beneficial to the development of the memory device 10 in the direction of large capacity and small size.

[0115] In addition, it is mentioned above that in order to improve the capacity of the memory device 10, the number of stack structures is increased, and the number of SD devices is also increased, in order to control the size of the memory device 10, the problem of reducing the size of the SD device is faced. However, by using the first connection structure 230 in the embodiment to connect one gate layer in each of the plurality of stack structures, the number of SD devices will not be increased, therefore, the demand for reducing the size of the SD device can be reduced.

[0116] In the embodiment, as shown in FIG. 9 and FIG. 10, the bit line BL is located between the first stack structure 210 and the second stack structure 220, and the extension direction of the bit line BL intersects the first direction X. Understandably, the bit line BL can extend in the Y-Z plane, for example, the extension direction of the bit line BL can be parallel to the third direction Z. The number of bit lines BL is multiple, and the multiple bit lines BL are arranged at intervals along the second direction Y. As shown in FIG. 10, the bit line BL is connected with the channel structure in the first stack structure 210, and the bit line BL is also connected with the channel structure in the second stack structure 220. Through the above arrangement, the bit line BL is located between the first stack structure 210 and the second stack structure 220, and the bit line BL can drive the channel structure in the first stack structure 210 upward, and at the same time, drive the channel structure in the second stack structure 220 downward. In other embodiments, when the bit line BL is located at the top end of the multiple stack structures (in the embodiment, that is, the end of the second stack structure 220 away from the first stack structure 210), due to the resistance in the channel structure, the current intensity in the channel structure away from the bit line BL is weak. Compared with the scheme that the bit line BL is located at the top end of the multiple stack structures, in the embodiment, the bit line BL is located between the first stack structure 210 and the second stack structure 220, which is beneficial to improve the current intensity in the channel structure and improve the problem that the current intensity in the channel structure away from the bit line BL is weak.

[0117] In some embodiments, as shown in FIG. 9, the first connection structure 230 includes a first connection sub-portion 231 and a second connection sub-portion 232 stacked along the first direction X. The first connection sub-portion 231 includes a first connection column 2311 and at least one first connection layer 2312. The first connection column 2311 extends along the first direction X, and the first connection layer 2312 is parallel to the second direction Y. One first connection layer 2312 connects the first connection column 2311 and one first gate layer 211.

[0118] Exemplarily, in the Y-Z plane, the first connection layer 2312 can surround the first connection column 2311 and be connected with the first connection column 2311. In addition, the first connection column 2311 and the first connection layer 2312 can be integrally arranged. The first connection layer 2312 can be located in the same horizontal plane (Y-Z plane) as one first gate layer 211, so as to connect the first connection layer 2312 with one first gate layer 211.

[0119] It should be noted that the first connecting sub-portion 231 includes at least one first connecting layer 2312. It can be understood that the first connecting sub-portion 231 can include one first connecting layer 2312, or the first connecting sub-portion 231 can include multiple first connecting layers 2312. When the first connecting sub-portion 231 includes multiple first connecting layers 2312, the multiple first connecting layers 2312 can be arranged at intervals along the first direction X. In the embodiment, the first connecting sub-portion 231 includes one first connecting layer 2312.

[0120] Referring to FIG. 11, in the Y-Z plane, the cross section of the first connecting column 2311 can be circular, for example, and the cross section of the first connecting layer 2312 can be circular ring, for example. The first connecting layer 2312 can be arranged around the first connecting column 2311, and the first connecting layer 2312 is connected with the first connecting column 2311.

[0121] The second connecting sub-portion 232 includes a second connecting column 2321 and at least one second connecting layer 2322. The second connecting column 2321 extends along the first direction X and is connected with the first connecting column 2311. The second connecting layer 2322 is parallel to the second direction Y, and one second connecting layer 2322 connects the second connecting column 2321 and one second gate layer 221.

[0122] Exemplarily, referring to FIG. 9 and FIG. 12, in the Y-Z plane, the second connecting layer 2322 can surround the second connecting column 2321 and be connected with the second connecting column 2321. Since the second connecting column 2321 is connected with the first connecting column 2311, the first connecting column 2311, the first connecting layer 2312, the second connecting column 2321, and the second connecting layer 2322 can be integrally arranged. The second connecting layer 2322 can be located in the same horizontal plane (Y-Z plane) as one second gate layer 221, so as to connect the second connecting layer 2322 with one second gate layer 221.

[0123] It should be noted that the second connecting sub-portion 232 includes at least one second connecting layer 2322. It can be understood that the second connecting sub-portion 232 can include one second connecting layer 2322, or the second connecting sub-portion 232 can include multiple second connecting layers 2322. When the second connecting sub-portion 232 includes multiple second connecting layers 2322, the multiple second connecting layers 2322 can be arranged at intervals along the first direction X. In the embodiment, the first connecting sub-portion 231 includes one first connecting layer 2312.

[0124] Referring to FIG. 12, in the Y-Z plane, the cross section of the second connecting column 2321 can be circular, for example, and the cross section of the second connecting layer 2322 can be annular, for example. The second connecting layer 2322 can be disposed around the second connecting column 2321, and the second connecting layer 2322 is connected to the second connecting column 2321.

[0125] Through the above arrangement, the end of the second connecting column 2321 away from the first connecting column 2311 can be connected to an SD device. One SD device can be connected to at least one second gate layer 221 through the second connecting column 2321 and the second connecting layer 2322, and the SD device can be connected to at least one first gate layer 211 through the first connecting column 2311 and the first connecting layer 2312. It can be understood that the gate layers in different stack structures can share one first connecting structure 230 and one SD device, which is conducive to improving the storage density of the memory device 10.

[0126] In some embodiments, as shown in FIG. 9, the first connecting sub-portion 231 and the second connecting sub-portion 232 are an integral structure. The constituent materials of the first connecting sub-portion 231 and the second connecting sub-portion 232 can be the same. It can be understood that the first connecting sub-portion 231 and the second connecting sub-portion 232 can be made in one process step. Through the above arrangement, the first connecting sub-portion 231 and the second connecting sub-portion 232 are an integral structure, which is conducive to the electrical connection between the first connecting sub-portion 231 and the second connecting sub-portion 232 and improves the stability of the memory device 10.

[0127] In some embodiments, as shown in FIG. 9, in the second direction Y, the size of the end of the first connecting column 2311 close to the second connecting column 2321 is greater than the size of the end of the second connecting column 2321 close to the first connecting column 2311. For example, in the X-Y plane, the cross section of the first connecting column 2311 can be rectangular, and the cross section of the second connecting column 2321 can also be rectangular. In the second direction Y, the width of the first connecting column 2311 is greater than the width of the second connecting column 2321. Alternatively, in the X-Y plane, the cross section of the first connecting column 2311 can be an inverted trapezoid with the upper part wider than the lower part, and the cross section of the second connecting column 2321 can also be an inverted trapezoid with the upper part wider than the lower part. In the X-Y plane, the size of the upper base of the first connecting column 2311 is greater than the size of the lower base of the second connecting column 2321.

[0128] In the embodiment, on the plane where the first connecting pillar 2311 contacts the second connecting pillar 2321, in the second direction Y, the width of the first connecting pillar 2311 is greater than the width of the second connecting pillar 2321. In addition, on the plane where the first connecting pillar 2311 contacts the second connecting pillar 2321, in the second direction Y, the first connecting pillar 2311 and the second connecting pillar 2321 can be fully overlapped, that is, the edges on both sides of the second connecting pillar 2321 can be located within the edges on both sides of the first connecting pillar 2311; or, the first connecting pillar 2311 and the second connecting pillar 2321 can be partially overlapped, that is, the edge on one side of the second connecting pillar 2321 can be located outside the edge on one side of the first connecting pillar 2311.

[0129] Through the above arrangement, it is beneficial to improve the process window for realizing contact connection between the second connecting pillar 2321 and the first connecting pillar 2311, so as to facilitate the connection of the second connecting pillar 2321 and the first connecting pillar 2311, improve the stability of the connection of the first connecting pillar 2311 and the second connecting pillar 2321, and further improve the storage stability of the memory device 10.

[0130] In some embodiments, as shown in FIG. 9, in the second direction Y, the size of the end of the first connecting pillar 2311 close to the second connecting pillar 2321 is greater than the size of the end of the first connecting pillar 2311 away from the second connecting pillar 2321. For example, as shown in FIG. 9, in the Y-Z plane, the cross-sectional shape of the first connecting pillar 2311 can be an inverted trapezoid with the upper part wider than the lower part, and in the second direction Y, the width of the upper base of the cross section of the first connecting pillar 2311 is greater than the width of the lower base of the cross section of the first connecting pillar 2311.

[0131] In addition, in the second direction Y, the size of the end of the second connecting pillar 2321 away from the first connecting pillar 2311 is greater than the size of the end of the second connecting pillar 2321 close to the first connecting pillar 2311. For example, as shown in FIG. 9, in the Y-Z plane, the cross-sectional shape of the second connecting pillar 2321 can be an inverted trapezoid with the upper part wider than the lower part, and in the second direction Y, the width of the upper base of the cross section of the second connecting pillar 2321 is greater than the width of the lower base of the cross section of the second connecting pillar 2321. In the Y-Z plane, the lower base of the cross section of the second connecting pillar 2321 contacts the upper base of the cross section of the first connecting pillar 2311, thereby realizing the electrical connection of the first connecting pillar 2311 and the second connecting pillar 2321.

[0132] Through the above arrangement, it is beneficial to improve the process window for realizing contact connection between the second connecting pillar 2321 and the first connecting pillar 2311, so as to facilitate the connection of the second connecting pillar 2321 and the first connecting pillar 2311, improve the stability of the connection of the first connecting pillar 2311 and the second connecting pillar 2321, and further improve the storage stability of the memory device 10.

[0133] In some embodiments, as shown in FIG. 9, the first connection structure 230 further includes a first isolation layer 233 and a second isolation layer 234. The first isolation layer 233 is located on the side of the first connection layer 2312 close to the second connection layer 2322, and the first isolation layer 233 is arranged around the first connection column 2311, for example, the first isolation layer 233 can cover the peripheral surface of the first connection column 2311, so as to isolate the first connection column 2311 and prevent the first connection column 2311 from generating a leakage current with other conductive structures, which is conducive to improving the storage stability of the memory device 10.

[0134] In addition, the second isolation layer 234 is located on the side of the second connection layer 2322 away from the first connection layer 2312, and the second isolation layer 234 is arranged around the second connection column 2321, for example, the second isolation layer 234 can cover the peripheral surface of the second connection column 2321, so as to isolate the second connection column 2321 and prevent the second connection column 2321 from generating a leakage current with other conductive structures, which is conducive to improving the storage stability of the memory device 10.

[0135] In some embodiments, as shown in FIG. 9, the size of the first isolation layer 233 away from the end of the first connection layer 2312 in the second direction is greater than the size of the first isolation layer 233 close to the end of the first connection layer 2312 in the second direction. In the second direction Y, the first isolation layer 233 has a certain thickness, and the thickness of the end of the first isolation layer 233 close to the second connection column 2321 can be greater than the thickness of the end of the first isolation layer 233 close to the first connection layer 2312. In this way, it is conducive to further improving the isolation effect of the first connection column 2311 close to the end of the second connection column 2321.

[0136] Continuing to refer to FIG. 9, in the second direction Y, the second isolation layer 234 has a certain thickness, and the thickness of the end of the second isolation layer 234 away from the first connection column 2311 can be greater than the thickness of the end of the second isolation layer 234 close to the first connection column 2311. In this way, it is conducive to further improving the isolation effect of the second isolation layer 234 on the end of the second connection column 2321 away from the first connection column 2311.

[0137] In some embodiments, as shown in FIG. 9, the first connection structure 230 further includes a third isolation layer 235 and a fourth isolation layer 236.

[0138] The third isolation layer 235 is located on the side of the first connection layer 2312 away from the first isolation layer 233, the third isolation layer 235 is in contact with the first connection column 2311 and the third isolation layer 235 is arranged around the first connection column 2311. It can be understood that the first isolation layer 233 is located above the first connection layer 2312, and the first isolation layer 233 is arranged around the first connection column 2311 to isolate the first connection column 2311 above the first connection layer 2312; the third isolation layer 235 is located below the first connection layer 2312, and the third isolation layer 235 is arranged around the first connection column 2311 to isolate the first connection column 2311 below the first connection layer 2312. The first isolation layer 233 and the third isolation layer 235 are both in contact with the first connection column 2311.

[0139] The fourth isolation layer 236 is located on the side of the second connection layer 2322 away from the second isolation layer 234, the fourth isolation layer 236 is in contact with the second connection column 2321 and the fourth isolation layer 236 is arranged around the second connection column 2321. It can be understood that the second isolation layer 234 is located above the second connection layer 2322, and the second isolation layer 234 is arranged around the second connection column 2321 to isolate the second connection column 2321 above the second connection layer 2322; the fourth isolation layer 236 is located below the second connection layer 2322, and the fourth isolation layer 236 is arranged around the second connection column 2321 to isolate the second connection column 2321 below the second connection layer 2322. The second isolation layer 234 and the fourth isolation layer 236 are both in contact with the second connection column 2321.

[0140] By arranging the third isolation layer 235, the first connection column 2311 is isolated, preventing leakage current between the first connection column 2311 and other conductive structures, and improving the storage stability of the storage device 10. By arranging the fourth isolation layer 236, the second connection column 2321 is isolated, preventing leakage current between the second connection column 2321 and other conductive structures, and improving the storage stability of the storage device 10.

[0141] In some embodiments, as shown in FIG. 9, the first connection layer 2312 includes a first sub-layer 3121 and a second sub-layer 3122 stacked along the first direction X, the first sub-layer 3121 is located between the first isolation layer 233 and the second sub-layer 3122, and the first isolation layer 233 is arranged around the first sub-layer 3121. The first sub-layer 3121 and the second sub-layer 3122 are both arranged around the first connection column 2311, and the first sub-layer 3121 and the second sub-layer 3122 are both in contact with the first connection column 2311. The first sub-layer 3121 and the second sub-layer 3122 are stacked along the first direction X and are in contact, so that the first sub-layer 3121 is electrically connected to the first connection column 2311, the second sub-layer 3122 is electrically connected to the first connection column 2311, and the first sub-layer 3121 is electrically connected to the second sub-layer 3122. The first connection layer 2312 is connected to the first connection column 2311 through the first sub-layer 3121 and the second sub-layer 3122, which is conducive to improving the stability of the electrical connection between the first connection layer 2312 and the first connection column 2311.

[0142] For example, in the first direction X, the size of the first sub-layer 3121 can be greater than the size of the second sub-layer 3122, which can increase the contact area between the first sub-layer 3121 and the first connection column 2311, and is conducive to further improving the stability of the electrical connection between the first connection layer 2312 and the first connection column 2311.

[0143] In addition, the first isolation layer 233 can be arranged around the first sub-layer 3121, thereby preventing leakage current between the first sub-layer 3121 and other conductive structures, and is conducive to improving the storage stability of the memory device 10.

[0144] In some embodiments, as shown in FIG. 13, the memory device 10 further includes a third connection layer 250. The third connection layer 250 is arranged around the connection column, and the third connection layer 250 is connected to the first connection column 2311. In the first direction X, the edge of the side of the third connection layer 250 away from the first isolation layer 233 is connected to the first connection layer 2312. The first connection layer 2312 is arranged around the third connection layer 250, and the first connection layer 2312 is connected to the first gate layer 211.

[0145] Referring to FIG. 13, the first connection layer 2312 can be, for example, a ring structure. A part of the outer edge of the first connection layer 2312 can be connected to the first gate layer 211, and the inner edge of the first connection layer 2312 can be connected to the third connection layer 250. The third connection layer 250 can be arranged around the first connection column 2311, and the third connection layer 250 can be in contact with the first connection column 2311 to achieve electrical connection. Through the above arrangement, the first connection layer 2312 can be electrically connected to the first connection column 2311 through the third connection layer 250, thereby achieving signal transmission.

[0146] In some embodiments, as shown in FIG. 13, the first isolation layer 233 includes a first sub-isolation layer 2331, a second sub-isolation layer 2332, and a third sub-isolation layer 2333. The first sub-isolation layer 2331 is arranged around the connecting column. The second sub-isolation layer 2332 is between the first sub-isolation layer 2331 and the connecting column, and the second sub-isolation layer 2332 is arranged around the connecting column. The third sub-isolation layer 2333 is between the second sub-isolation layer 2332 and the connecting column, and the third sub-isolation layer 2333 is arranged around the connecting column.

[0147] For example, the first sub-isolation layer 2331, the second sub-isolation layer 2332, and the third sub-isolation layer 2333 can be composed of an insulating material. The insulating material can be, for example, a combination of one or more of silicon oxide, silicon nitride, and high dielectric constant insulating material, or other insulating materials. The first sub-isolation layer 2331, the second sub-isolation layer 2332, and the third sub-isolation layer 2333 can be composed of the same material or different materials, which is not limited in the present disclosure.

[0148] Through the above arrangement, the first sub-isolation layer 2331, the second sub-isolation layer 2332, and the third sub-isolation layer 2333 collectively isolate the first connecting column 2311 on the side of the first connecting layer 2312 close to the second connecting layer 2322, which is conducive to enhancing the isolation effect of the first isolation layer 233 on the first connecting column 2311, thereby preventing leakage current between the first sub-layer 3121 and other conductive structures, and improving the storage stability of the memory device 10.

[0149] In some embodiments, as shown in FIG. 13, the edge of the third connecting layer 250 on the side close to the second sub-isolation layer 2332 extends in the direction close to the second sub-isolation layer 2332. That is, the edge of the third connecting layer 250 on the side close to the second sub-isolation layer 2332 can extend upward between the first sub-isolation layer 2331 and the third sub-isolation layer 2333, thereby increasing the connection force between the third connecting layer 250 and the first isolation layer 233, and improving the structural stability of the memory device 10.

[0150] In the present embodiment, the first sub-isolation layer 2331 can be arranged around the third connecting layer 250 to prevent leakage current between the third connecting layer 250 and other conductive structures, thereby improving the storage stability of the memory device 10.

[0151] In some embodiments, as shown in FIG. 10, the memory device 10 further comprises a first selection gate 261, a second selection gate 262, a third selection gate 263, and a fourth selection gate 264. The first selection gate 261 is located on a side of the first stack structure 210 away from the second stack structure 220. The second selection gate 262 is located on a side of the first stack structure 210 close to the second stack structure 220. The third selection gate 263 is located on a side of the second stack structure 220 close to the first stack structure 210. The bit line BL is connected to the second selection gate 262 and the third selection gate 263. The fourth selection gate 264 is located on a side of the second stack structure 220 away from the first stack structure 210.

[0152] Referring to FIG. 10, the bit line BL is located between the second selection gate 262 and the third selection gate 263, and the bit line BL is connected to the second selection gate 262 and the third selection gate 263. Through the above arrangement, when the bit line BL is turned on, the first selection gate 261 and the second selection gate 262 can be turned on, and further, the bit line BL can drive the channel structure in the first stack structure 210 upward, and at the same time, drive the channel structure in the second stack structure 220 downward. Through the above arrangement, it is beneficial to improve the current intensity in the channel structure, and improve the problem that the current intensity in the channel structure away from the bit line BL is weak.

[0153] In some embodiments, as shown in FIG. 14 and FIG. 15, the first stack structure 210 comprises a first sub-stack structure 2101 and a second sub-stack structure 2102 stacked along the first direction X, a first channel structure 2103, and a second channel structure 2104. The first channel structure 2103 penetrates the first sub-stack structure 2101, and the second channel structure 2104 penetrates the second sub-stack structure 2102. The first channel structure 2103 is located between the first selection gate 261 and the second selection gate 262.

[0154] In this embodiment, as shown in FIG. 14 and FIG. 15, the first stack structure 210 can comprise a first sub-stack structure 2101 and a second sub-stack structure 2102 stacked along the first direction X. It can be understood that the first stack structure 210 can comprise a plurality of sub-stack structures, for example, the first stack structure 210 can comprise but is not limited to 2 sub-stack structures, 4 sub-stack structures, or 8 sub-stack structures, and the like, thereby improving the storage capacity of the memory device 10. In addition, the first sub-stack structure 2101 and the second sub-stack structure 2102 are stacked along the first direction X, which is beneficial to improve the storage density of the memory device 10. This embodiment takes the first stack structure 210 comprising 2 sub-stack structures as an example for explanation and description.

[0155] Continuing to refer to FIGS. 14 and 15, the first channel structure 2103 penetrates the first sub-stack structure 2101, and the second channel structure 2104 penetrates the second sub-stack structure 2102. Exemplarily, the first channel structure 2103 and the second channel structure 2104 can be in communication, so as to improve the storage capacity of the memory device 10. Among the plurality of first gate layers 211 surrounding the first channel structure 2103, the first gate layer 211 farthest from the second channel structure 2104 can be arranged as the first selection gate 261. Among the plurality of first gate layers 211 surrounding the second channel structure 2104, the first gate layer 211 farthest from the first channel structure 2103 can be arranged as the second selection gate 262. Then, the first channel structure 2103 and the second channel structure 2104 are located between the first selection gate 261 and the second selection gate 262, which facilitates the reading and writing operations of the memory device 10 on the first channel structure 2103 and the second channel structure 2104.

[0156] In some embodiments, as shown in FIGS. 11 and 12, the memory device 10 includes a first region 101 and a second region 102, the first region 101 is adjacent to the second region 102, the first stack structure 210 and the second stack structure 220 are both located in the first region 101, and the first connection structure 230 is located in the second region 102. The second region 102 is located on one side of the first region 101. For example, in FIG. 11, in the second direction Y, the second region 102 is located on one side of the first region 101, and the first region 101 and the second region 102 are adjacent only on one side.

[0157] Alternatively, in other embodiments, as shown in FIG. 12, the first region 101 includes a first sub-region 1011 and a second sub-region 1012, and the second region 102 is located between the first sub-region 1011 and the second sub-region 1012.

[0158] Through the above arrangement, the first connection structure 230 located in the second region 102 can be connected with one first gate layer 211, and the first connection structure 230 is connected with one second gate layer 221. Compared with the way that the gate line contacts G-CNT in the stepped arrangement in FIG. 4 lead out the first gate layer 211 and the second gate layer 221 one by one, one first gate layer 211 and the first second gate layer 221 in the present embodiment share one first connection structure 230, which is conducive to controlling the area of the second region 102, and further improves the storage density of the memory device 10.

[0159] In some embodiments, as shown in FIG. 13, the memory device 10 further includes a third stack structure 270 and a fourth stack structure 280 which are arranged in a stack along the first direction X, and the third stack structure 270 and the fourth stack structure 280 are both located in the second region 102. A relatively thick dielectric layer can be arranged between the third stack structure 270 and the fourth stack structure 280.

[0160] The first connecting column 2311 penetrates through the third stack structure 270, which comprises a plurality of third dielectric layers 271 and a plurality of fourth dielectric layers 272 arranged alternately along the first direction X, and at least one third dielectric layer 271 is connected with at least one first connecting layer 2312. Here, the first connecting layer 2312 connected with the third dielectric layer 271 can be connected with one first gate layer 211.

[0161] The second connecting column 2321 penetrates through the fourth stack structure 280, which comprises a plurality of fifth dielectric layers 281 and a plurality of sixth dielectric layers 282 arranged alternately along the first direction X, and at least one fifth dielectric layer 281 is connected with at least one second connecting layer 2322. Here, the second connecting layer 2322 connected with the fifth dielectric layer 281 can be connected with one second gate layer 221.

[0162] Exemplarily, the third dielectric layer 271 can be connected with the first gate layer 211, and the fourth dielectric layer 272 can be connected with the first dielectric layer 212. In addition, the fourth dielectric layer 272 can be made of the same material as the first dielectric layer 212, and further, the fourth dielectric layer 272 can be arranged in the same layer as the first dielectric layer 212. The arrangement in the same layer refers to the positional relationship of a plurality of patterns in the same pattern layer. The pattern layer refers to a film layer formed by one patterning process. The patterning process refers to a process capable of forming at least one pattern with a certain shape. For example, a thin film is formed on a substrate by any one of a plurality of film forming processes such as deposition, coating, sputtering, etc., and then the thin film is patterned to form a film layer containing at least one pattern. The steps of patterning include coating photoresist, exposure, development, etching, and stripping photoresist, etc. In the present embodiment, the positional relationship of a plurality of patterns belonging to the same pattern layer is referred to as arrangement in the same layer.

[0163] Exemplarily, the fifth dielectric layer 281 can be connected with the second gate layer 221, and the sixth dielectric layer 282 can be connected with the second dielectric layer 222. In addition, the sixth dielectric layer 282 can be made of the same material as the second dielectric layer 222, and further, the sixth dielectric layer 282 can be arranged in the same layer as the second dielectric layer 222.

[0164] In the present embodiment, the first dielectric layer 212, the second dielectric layer 222, the fourth dielectric layer 272, and the sixth dielectric layer 282 are all made of oxide, and the third dielectric layer 271 and the fifth dielectric layer 281 are both made of nitride.

[0165] In some embodiments, referring to FIGS. 8, 10 and 11, the memory device 10 further comprises a second connection structure 240. The second connection structure 240 is located at one side of the first stack structure 210 and the second stack structure 220 along the second direction, for example, in FIG. 11, the first stack structure 210 and the second stack structure 220 can be located in the second region 102, and the second connection structure 240 can be located in the first region 101. One of the first selection gate 261 and the second selection gate 262 is connected with the second connection structure 240. That is, the second connection structure 240 is connected with the first selection gate 261, or the second connection structure 240 is connected with the second selection gate 262.

[0166] In other examples, referring to FIGS. 8 and 10, one of the third selection gate 263 and the fourth selection gate 264 is connected with the second connection structure 240. That is, the second connection structure 240 is connected with the third selection gate 263, or the second connection structure 240 is connected with the fourth selection gate 264.

[0167] Through the above arrangement, the memory device 10 can select to turn on the channel structure in the first stack structure 210 or the channel structure in the second stack structure 220 through the second connection structure 240, and then further select to read or write the storage node in the first stack structure 210 or the second stack structure 220 through the first connection structure 230 and the bit line BL.

[0168] Exemplarily, the number of the second connection structure 240 can be multiple, for example, one second connection structure 240 connected with the first selection gate 261, one second connection structure 240 connected with the second selection gate 262, one second connection structure 240 connected with the third selection gate 263, and one second connection structure 240 connected with the fourth selection gate 264. In this way, multiple second connection structures 240 are arranged, and when one of the second connection structures 240 is connected poorly, the first stack structure 210 and the second stack structure 220 can be selected through other second connection structures 240, which is beneficial to improve the storage stability of the memory device 10.

[0169] Some embodiments of the present disclosure further provide a memory device 10, referring to FIGS. 13 and 16, the memory device 10 comprises: a first stack structure 210, a second stack structure 220 and a first connection structure 230. Wherein, the first stack structure 210 comprises a plurality of first gate layers 211 and a plurality of first dielectric layers 212 which are alternately arranged in a first direction X. The second stack structure 220 comprises a plurality of second gate layers 221 and a plurality of second dielectric layers 222 which are alternately arranged in the first direction X. The second stack structure 220 and the first stack structure 210 are arranged in the first direction X.

[0170] The first stack structure 210 can be disposed on the semiconductor layer 600. For example, the first stack structure 210 can be in direct contact with the semiconductor layer 600. For example, the semiconductor layer 600 can include, for example, monocrystalline silicon, monocrystalline germanium, a group III-V compound semiconductor material, a group II-VI compound, and other suitable semiconductor materials.

[0171] It should be noted that the first stack structure 210 and the second stack structure 220 in this embodiment can refer to the explanation of the first stack structure 210 and the second stack structure 220 in some previous embodiments, which will not be repeated here.

[0172] As shown in FIG. 13, the first connection structure 230 includes a connection column 237, at least one first connection layer 2312, and at least one second connection layer 2322. The connection column 237 is located on one side of the first stack structure 210 and the second stack structure 220 along the second direction Y. The first connection layer 2312 is parallel to the second direction Y, and one first connection layer 2312 connects one first gate layer 211 and the connection column 237. The second connection layer 2322 is parallel to the second direction Y, and one second connection layer 2322 connects one second gate layer 221 and the connection column 237.

[0173] It should be noted that the first connection structure 230 can refer to the explanation of the first connection structure 230 in some previous embodiments.

[0174] In this embodiment, the first connection structure 230 can include one first connection layer 2312 or a plurality of first connection layers 2312, and the first connection structure 230 can include one second connection layer 2322 or a plurality of second connection layers 2322. Hereinafter, the first connection structure 230 includes one first connection layer 2312 and one second connection layer 2322 as an example for explanation.

[0175] By the above arrangement, the first connection layer 2312 in the first connection structure 230 is connected with the first gate layer 211 in the first stack structure 210, the second connection layer 2322 in the first connection structure 230 is connected with the second gate layer 221 in the second stack structure 220, and the connection column is connected with the SD device. Compared with FIG. 4, one first gate layer 211 is connected with the SD device through one gate line contact G-CNT, one second gate layer 221 is connected with the SD device through one gate line contact G-CNT, and the plurality of gate line contacts G-CNT are arranged in a stepped manner, resulting in that the plurality of gate line contacts G-CNT occupy a large area. The number of the first connection structure 230 in the embodiment is less than the number of the gate line contact G-CNT, and the number of the SD device in the embodiment is also less, so the area occupied by the first connection structure 230 is less than the area occupied by the gate line contact G-CNT, and at the same time, the area occupied by the SD device is also reduced, which is beneficial to improve the storage density of the memory device 10.

[0176] When more stack structures are included in the memory device 10, for example, the memory device 10 can include 4 stack structures, 6 stack structures, or 8 stack structures, and the like, at this time, the first connection structure 230 can be connected with one gate layer in each of the plurality of stack structures. By the above arrangement, even if more stack structures are increased, the number of the first connection structure 230 will not be increased, that is, the area occupied by the first connection structure 230 will not be increased, which is beneficial to improve the storage density of the memory device 10 and is beneficial to the development of the memory device 10 in the direction of large capacity and small size.

[0177] In addition, it is mentioned in the foregoing that in order to improve the capacity of the memory device 10, the number of stack structures is increasing, and the number of SD devices is also increasing, in order to control the size of the memory device 10, the problem of reducing the size of the SD device is faced. However, by using the first connection structure 230 in the embodiment to connect one gate layer in each of the plurality of stack structures, the number of SD devices will not be increased, so the demand for reducing the size of the SD device can be reduced.

[0178] In some embodiments, as shown in FIGS. 10 and 16, the memory device 10 further includes a first selection gate 261, a second selection gate 262, a third selection gate 263, a fourth selection gate 264, and a second connection structure 240. Among them, the first selection gate 261 is located on the side of the first stack structure 210 away from the second stack structure 220, the second selection gate 262 is located on the side of the first stack structure 210 close to the second stack structure 220, the third selection gate 263 is located on the side of the second stack structure 220 close to the first stack structure 210, and the fourth selection gate 264 is located on the side of the second stack structure 220 away from the first stack structure 210.

[0179] The second connection structure 240 is located at one side of the first stack structure 210 and the second stack structure 220 along the second direction Y, and the second connection structure 240 and the first connection structure 230 can be located at the same side of the first stack structure 210 and the second stack structure 220. One of the first select gate 261, the second select gate 262, the third select gate 263, and the fourth select gate 264 is connected with the second connection structure 240.

[0180] Through the above arrangement, the memory device 10 can select to turn on the channel structure in the first stack structure 210 or the channel structure in the second stack structure 220 through the second connection structure 240, and then further select to read or write the storage node in the first stack structure 210 or the second stack structure 220 through the first connection structure 230 and the bit line BL.

[0181] In some embodiments, as shown in FIG. 16, the memory device 10 further includes a first bit line BL-1 and a second bit line BL-2. The first bit line BL-1 is located at the side of the first select gate 261 away from the first stack structure 210, and the second bit line BL-2 is located at the side of the fourth select gate 264 away from the first stack structure 210. The extension direction of the first bit line BL-1 and the second bit line BL-2 intersects the first direction X. The extension direction of the first bit line BL-1 and the second bit line BL-2 can be parallel.

[0182] It should be noted that when the memory device 10 continues to stack multiple stack structures, the first bit line BL-1 and the second bit line BL-2 are respectively located at both sides of all stack structures along the first direction X, and a source layer is arranged between adjacent stack structures.

[0183] In this embodiment, a source layer (for example, a silicon material is deposited) can be formed between the first stack structure 210 and the second stack structure 220, the first dielectric layer 212 in the first stack structure 210 contacts one side of the source layer, and the second dielectric layer 222 in the second stack structure 220 contacts the other side of the source layer. The channel structure in the first stack structure 210 can penetrate through the first stack structure 210 and part of the source layer, and the channel structure in the second stack structure 220 can penetrate through the second stack structure 220 and part of the source layer, and the channel structure in the first stack structure 210 and the channel structure in the second stack structure 220 are in communication.

[0184] Through the above arrangement, the first bit line BL-1, the channel structure in the first stack structure 210, the channel structure in the second stack structure 220, and the second bit line BL-2 are all in communication, so that the channel structures in the first stack structure 210 and the second stack structure 220 can be driven through the first bit line BL-1 and the second bit line BL-2. Compared with the scheme in which the bit line BL is located at the topmost end of the plurality of stack structures, in the embodiment, the bit line BL is located between the first stack structure 210 and the second stack structure 220, which is conducive to improving the current intensity in the channel structure and solving the problem that the current intensity in the channel structure far from the bit line BL is weak.

[0185] In some embodiments, as shown in FIG. 11, the memory device 10 includes a first region 101 and a second region 102, the first region 101 and the second region 102 are adjacent in the second direction Y, the first stack structure 210 and the second stack structure 220 are both located in the first region 101, and the first connection structure 230 is located in the second region 102. For example, in the second direction Y, the second region 102 is located on one side of the first region 101, and the first region 101 and the second region 102 only have one side adjacent to each other. In some embodiments, the second connection structure 240 is also located in the second region 102.

[0186] Alternatively, in other embodiments, the first region 101 includes a first sub-region 1011 and a second sub-region 1012, and the second region 102 is located between the first sub-region 1011 and the second sub-region 1012.

[0187] Through the above arrangement, the first connection structure 230 located in the second region 102 can be connected with one first gate layer 211, and the first connection structure 230 is connected with one second gate layer 221. Compared with the way of leading out the first gate layer 211 and the second gate layer 221 one by one through the gate line contact G-CNT arranged in a stepped manner in FIG. 4, in the embodiment, one first gate layer 211 and the first second gate layer 221 share one first connection structure 230, which is conducive to controlling the area of the second region 102, and further improving the storage density of the memory device 10.

[0188] In the embodiment, the memory device 10 can further include a third stack structure 270 and a fourth stack structure 280 stacked along the first direction X, and the third stack structure 270 and the fourth stack structure 280 are both located in the second region 102. The connection column can penetrate through the third stack structure 270 and the fourth stack structure 280. The specific structure of the third stack structure 270 and the fourth stack structure 280 can refer to the explanation of the third stack structure 270 and the fourth stack structure 280 in some embodiments described above.

[0189] Some embodiments of the present disclosure also provide a memory device 10, as shown in FIG. 8, FIG. 9 and FIG. 17, the memory device 10 comprises: a first stack structure 210 and a second stack structure 220 arranged in a first direction, a first selection gate 261, a second selection gate 262 and a bit line BL. Wherein, the first stack structure 210 comprises a plurality of first gate layers 211 and a plurality of first dielectric layers 212 arranged alternately in the first direction X, and the second stack structure 220 comprises a plurality of second gate layers 221 and a plurality of second dielectric layers 222 arranged alternately in the first direction X.

[0190] The first selection gate 261 is located on the side of the first stack structure 210 close to the second stack structure 220, and the second selection gate 262 is located on the side of the second stack structure 220 close to the first stack structure 210. For example, the first gate layer 211 closest to the second stack structure 220 in the plurality of first gate layers 211 can be set as the first selection gate 261, and the second gate layer 221 closest to the first stack structure 210 in the plurality of second gate layers 221 can be set as the second selection gate 262.

[0191] The bit line BL can be located between the first selection gate 261 and the second selection gate 262, and the bit line BL can be connected with the first selection gate 261, and the bit line BL can be connected with the second selection gate 262. The extension direction of the bit line BL intersects with the first direction X, for example, the bit line BL can extend in the Y-Z plane, for example, the extension direction of the bit line BL can be parallel to the third direction Z. The number of bit lines BL is a plurality, and the plurality of bit lines BL are arranged at intervals along the second direction Y.

[0192] As shown in FIG. 17, the bit line BL is connected with the channel structure in the first stack structure 210, and the bit line BL is also connected with the channel structure in the second stack structure 220. Through the above arrangement, the bit line BL is located between the first stack structure 210 and the second stack structure 220, the bit line BL can drive the channel structure in the first stack structure 210 upwards, at the same time, drive the channel structure in the second stack structure 220 downwards. In other embodiments, when the bit line BL is located at the top end of the plurality of stack structures (in this embodiment, it is the end of the second stack structure 220 away from the first stack structure 210), because there is resistance in the channel structure, the current intensity in the channel structure away from the bit line BL is weak. Compared with the scheme that the bit line BL is located at the top end of the plurality of stack structures, in this embodiment, the bit line BL is located between the first stack structure 210 and the second stack structure 220, which is beneficial to improve the current intensity in the channel structure and improve the problem that the current intensity in the channel structure away from the bit line BL is weak.

[0193] In some embodiments, as shown in FIG. 9, the memory device 10 includes a first connection structure 230. The first connection structure 230 is located at one side of the first stack structure 210 and the second stack structure 220 along the second direction Y, the first connection structure 230 is connected with at least one first gate layer 211, and the first connection structure 230 is connected with at least one second gate layer 221.

[0194] In this embodiment, the first connection structure 230 can refer to the introduction of the first connection structure 230 in some embodiments described above, which will not be repeated here.

[0195] Through the above setting, one first gate layer 211 and one second gate layer 221 can share one first connection structure 230 and one SD device. Then, when the memory device 10 has two stack structures (i.e., the first stack structure 210 and the second stack structure 220), compared with one first gate layer 211 connected with one SD device through one gate line contact G-CNT (refer to FIG. 4 and FIG. 8), one second gate layer 221 connected with one SD device through one gate line contact G-CNT, the number of the first connection structure 230 in this embodiment is less than the number of the gate line contact G-CNT, and the number of the SD device in this embodiment is also less, so the area occupied by the first connection structure 230 is less than the area occupied by the gate line contact G-CNT, at the same time, the area occupied by the SD device is also reduced, which is beneficial to improve the storage density of the memory device 10.

[0196] When the memory device 10 includes more stack structures, for example, the memory device 10 can include 4 stack structures, 6 stack structures or 8 stack structures, etc. At this time, the first connection structure 230 can be connected with one gate layer in each of the plurality of stack structures. Through the above setting, even if more stack structures are increased, the number of the first connection structure 230 will not be increased, that is, the occupied area of the first connection structure 230 will not be increased, which is beneficial to improve the storage density of the memory device 10 and is beneficial to the development of the memory device 10 in the direction of large capacity and small size.

[0197] In addition, as mentioned above, in order to improve the capacity of the memory device 10, the number of stack structures is increasing, and the number of SD devices is also increasing. In order to control the size of the memory device 10, the size of the SD device needs to be reduced. However, by using the first connection structure 230 in this embodiment to connect one gate layer in each of the plurality of stack structures, the number of SD devices will not be increased, so the demand for reducing the size of the SD device can be reduced.

[0198] In some embodiments, as shown in FIG. 16 and FIG. 17, the memory device 10 further comprises a third selection gate 263, a fourth selection gate 264 and a second connection structure 240. The third selection gate 263 is located at a side of the first stack structure 210 away from the second stack structure 220, and the fourth selection gate 264 is located at a side of the second stack structure 220 away from the first stack structure 210. Exemplarily, among the plurality of first gate layers 211, the first gate layer 211 farthest away from the second stack structure 220 can be set as the third selection gate 263. Among the plurality of second gate layers 221, the second gate layer 221 farthest away from the first stack structure 210 can be set as the fourth selection gate 264.

[0199] The second connection structure 240 is located at a side of the first stack structure 210 and the second stack structure 220 along the second direction Y. The second connection structure 240 and the first connection structure 230 can be located at the same side of the first stack structure 210 and the second stack structure 220. One of the first selection gate 261, the second selection gate 262, the third selection gate 263 and the fourth selection gate 264 is connected with the second connection structure 240.

[0200] Through the above arrangement, the memory device 10 can select to turn on the channel structure in the first stack structure 210 or the channel structure in the second stack structure 220 through the second connection structure 240, and further select to read or write the storage node in the first stack structure 210 or the second stack structure 220 through the first connection structure 230 and the bit line BL.

[0201] Exemplarily, the number of the second connection structure 240 can be multiple, for example, one second connection structure 240 connected with the first selection gate 261, one second connection structure 240 connected with the second selection gate 262, one second connection structure 240 connected with the third selection gate 263 and one second connection structure 240 connected with the fourth selection gate 264. In this way, multiple second connection structures 240 are arranged, and when one of the second connection structures 240 is connected poorly, the first stack structure 210 and the second stack structure 220 can be selected through other second connection structures 240, which is conducive to improving the storage stability of the memory device 10.

[0202] Some embodiments of the present disclosure provide a preparation method of a memory device, which is explained and described below in combination with FIG. 18-FIG. 43.

[0203] FIG. 18 is a flow chart of a preparation method of a memory device according to some embodiments. As shown in FIG. 18, the preparation method of the memory device provided by some embodiments of the present disclosure comprises S1-S4.

[0204] S1, forming a first stack structure, the first stack structure comprising a plurality of first gate layers and a plurality of first dielectric layers alternately stacked along a first direction.

[0205] In this step, referring to FIGS. 19 and 20, a semiconductor layer 600 is provided, and a first stack structure 210 is formed on the semiconductor layer 600. For example, the first dielectric layers 212 and the first gate layers 211 can be alternately formed on the semiconductor layer 600 by a deposition process. The deposition process includes, but is not limited to, one or more thin film deposition processes in physical vapor deposition (PVD), chemical vapor deposition (CVD), and atomic layer deposition (ALD).

[0206] The semiconductor layer 600 can include silicon (e.g., monocrystalline silicon), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon on insulator (SOI), and / or any other suitable semiconductor material. In some examples, the semiconductor layer 600 includes silicon, such as monocrystalline silicon or polycrystalline silicon.

[0207] The first stack structure 210 includes a plurality of first gate layers 211 and a plurality of first dielectric layers 212 alternately stacked along a first direction X. For example, the first gate layers 211 and the first dielectric layers 212 alternately arranged along the first direction X are stacked to form a plurality of first gate layers 211 and a plurality of first dielectric layers 212 spaced apart from each other. It can also be understood that one first gate layer 211 and one first dielectric layer 212 together constitute a first gate structure pair, and the first stack structure 210 includes a plurality of first gate structure pairs stacked along the first direction X.

[0208] Exemplarily, the number of layers of the first gate layers 211 and the first dielectric layers 212 can be 4, 16, 32, 64, 128, 256, etc. The thickness (i.e., the size along the first direction X) of the first gate layers 211 and the thickness of the first dielectric layers 212 can be substantially equal, or can be different. For example, the thickness of the first dielectric layers 212 is greater than the thickness of the first gate layers 211.

[0209] Exemplarily, the first gate layer 211 can include a conductive material, which can include but is not limited to one or more of tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, silicide, or a combination thereof, or can also be other suitable conductive material. In some examples, the first gate layer 211 includes a metal layer, such as a tungsten layer. In some examples, the first gate layer 211 includes a doped polysilicon layer. The polysilicon can be doped to a desired doping concentration with a suitable dopant, so that the polysilicon can become a conductive material used as the first gate layer 211.

[0210] Exemplarily, the first dielectric layer 212 can include an insulating material, which can include one or more of silicon oxide, silicon nitride, silicon oxynitride, and high dielectric constant insulating material, or can also be other suitable insulating material. Among them, the dielectric constant of silicon oxynitride is higher than that of silicon oxide, for example: the dielectric constant of silicon oxynitride is about 4-7, such as 3.8, 4, 4.8, 5.3, 5.9, 6, 6.36, 6.88, 7, 7.2, etc. In some examples, the first dielectric layer 212 includes a silicon oxide layer. In some examples, the first dielectric layer 212 includes a silicon oxynitride layer.

[0211] Exemplarily, the thickness (i.e., the size along the first direction X) of the first gate layer 211 can be between 10 nm and 50 nm, such as 10 nm, 15 nm, 18.3 nm, 20 nm, 25 nm, 27.7 nm, 30 nm, 35 nm, 40 nm, 45 nm, 50 nm, etc. Similarly, the thickness (i.e., the size along the third direction Z) of the first dielectric layer 212 can be between 10 nm and 50 nm, such as 10 nm, 15 nm, 18.3 nm, 20 nm, 25 nm, 27.7 nm, 30 nm, 35 nm, 40 nm, 45 nm, 50 nm, etc. Among them, the first gate layer 211 can be a gate line G (see FIG. 6) around the memory cell string, and can extend laterally (i.e., along the second direction Y) as a word line WL (see FIG. 4).

[0212] S2, a second stack structure is formed, the second stack structure includes a plurality of second gate layers and a plurality of second dielectric layers alternately stacked along the first direction, and the second stack structure is stacked with the first stack structure along the first direction.

[0213] In this step, please refer to FIG. 19, FIG. 20 and FIG. 21, before forming the second stack structure 220, a deposition process can be used to form an isolation medium layer 770 on the first stack structure 210. Exemplarily, the material of the isolation medium layer 770 can be the same as the first medium layer 212. Forming the first medium layer 212 on the top of the first stack structure 210, and forming the isolation medium layer 770 can be formed in the same process step.

[0214] After forming the isolation medium layer 770, the deposition process can be continued to alternately form the second medium layer 222 and the second gate layer 221 on the isolation medium layer 770. The composition material, thickness and number of the second gate layer 221 and the second medium layer 222 can refer to the examples of the composition material, thickness and number of the first gate layer 211 and the first medium layer 212. The composition material, thickness and number of the second gate layer 221 can be the same as or different from the first gate layer 211, and the composition material, thickness and number of the second medium layer 222 can be the same as or different from the first medium layer 212.

[0215] S3, form a first connection structure, the first connection structure is located on one side of the first stack structure and the second stack structure along a second direction, the first connection structure is connected with at least one first gate layer, and the first connection structure is connected with at least one second gate layer, the second direction intersects the first direction.

[0216] In this step, please refer to FIG. 21, before forming the first connection structure 230, the third stack structure 270 and the fourth stack structure 280 can be formed on one side of the first stack structure 210 and the second stack structure 220 along the second direction Y. By using etching process, deposition process, etc., the first connection structure 230 is formed. And the first connection structure 230 is connected with at least one first gate layer 211, and the first connection structure 230 is connected with at least one second gate layer 221.

[0217] Exemplarily, the composition material of the first connection structure 230 can include conductive material, which includes but is not limited to one or more combinations of tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, silicide, or other suitable conductive materials.

[0218] After forming the first connection structure 230, an SD device can also be formed, which is electrically connected with the first connection structure 230.

[0219] The memory device 10 prepared by the above steps, one SD device can be electrically connected with at least one first gate layer 211 and at least one second gate layer 221 through the first connection structure 230. One first gate layer 211 and one second gate layer 221 can share one first connection structure 230, and share one SD device. Then, when the memory device 10 has two stack structures (i.e. the first stack structure 210 and the second stack structure 220), compared with one first gate layer 211 connected with one SD device through one gate line contact G-CNT, and one second gate layer 221 connected with one SD device through one gate line contact G-CNT, the number of the first connection structure 230 in the embodiment is less than the number of the gate line contact G-CNT, and the number of the SD device in the embodiment is also less, then the area occupied by the first connection structure 230 is less than the area occupied by the gate line contact G-CNT, at the same time, the area occupied by the SD device is also reduced, which is beneficial to improve the storage density of the memory device 10.

[0220] After the second stack structure 220 is formed, and before the first connection structure 230 is formed, a plurality of stack structures can also be formed along the first direction X, for example, 2 stack structures, 4 stack structures or 6 stack structures can be formed. After the plurality of stack structures are formed, when the first connection structure 230 is formed, the first connection structure 230 can be connected with a gate layer in each of the plurality of stack structures.

[0221] The memory device 10 formed by the above preparation method, even if more stack structures are formed, the number of the first connection structure 230 will not increase. Therefore, the memory device 10 obtained by the above preparation method, the occupied area of the first connection structure 230 will not increase with the increase of the stack structure, which is beneficial to improve the storage density of the memory device 10, and is beneficial to the development of the memory device 10 in the direction of large capacity and small size.

[0222] In addition, in order to improve the capacity of the memory device 10, the number of stack structures is increasing, and the number of SD devices is also increasing. In order to control the size of the memory device 10, the size of the SD device needs to be reduced. However, the first connection structure 230 of the embodiment connects a gate layer in each of the plurality of stack structures, so the number of SD devices will not increase, and therefore the demand for reducing the size of the SD device can be reduced.

[0223] S4, forming a bit line, the bit line is located between the first stack structure and the second stack structure, and the extension direction of the bit line intersects the first direction.

[0224] In this step, as shown in FIG. 19, the extension direction of the bit line BL intersects the first direction X, for example, the bit line BL can extend along the third direction Z.

[0225] The memory device 10 prepared in this step has the bit line BL located between the first stack structure 210 and the second stack structure 220, and the bit line BL is connected with the channel structure in the first stack structure 210, and the bit line BL is also connected with the channel structure in the second stack structure 220. Therefore, the bit line BL can drive the channel structure in the first stack structure 210 upward, while driving the channel structure in the second stack structure 220 downward. Compared with forming the bit line BL on the second stack structure 220, in this embodiment, the bit line BL is formed between the first stack structure 210 and the second stack structure 220, which is beneficial to improve the current intensity of the channel structure in the first stack structure 210, and the current intensity of the channel structure in the second stack structure 220, and improve the problem that the current intensity of the channel structure far away from the bit line BL is weak.

[0226] In some embodiments, as shown in FIG. 23, the first stack structure 210 is formed by: forming a first layer structure 710, the first region 101 of the first layer structure 710 includes a plurality of first sacrificial layers 711 and a plurality of first dielectric layers 212 which are alternately stacked along the first direction, the first region 101 of the first layer structure 710 is adjacent to the second region 102 of the first layer structure 710, and the second region 102 of the first layer structure 710 is located on one side of the first region 101 of the first layer structure 710 along the second direction Y.

[0227] In this step, as shown in FIG. 23, for example, a deposition process can be used to alternately form the first dielectric layer 212 and the first sacrificial layer 711. For example, the material of the first dielectric layer 212 can be silicon oxide, and the material of the first sacrificial layer 711 can be silicon nitride.

[0228] The second stack structure 220 is formed as shown in FIG. 21, including: forming a second layer structure 720, the second layer structure 720 is located on the side of the bit line BL away from the first layer structure 710, the first region 101 of the second layer structure 720 includes a plurality of second sacrificial layers 721 and a plurality of second dielectric layers 222 which are alternately stacked along the first direction, the first region 101 of the second layer structure 720 is adjacent to the second region 102 of the second layer structure 720, and the second region 102 of the second layer structure 720 is located on one side of the first region 101 of the second layer structure 720 along the second direction Y.

[0229] In this step, as shown in FIG. 21, a deposition process can be used to form the second dielectric layer 222 and the second sacrificial layer 721 alternately on the first stack structure 710. Exemplarily, the material of the second dielectric layer 222 can be silicon oxide, and the material of the second sacrificial layer 721 can be silicon nitride.

[0230] As shown in FIG. 21, after forming the first stack structure 710 and before forming the second stack structure 720, a portion of the first stack structure 710 is removed to form a first connection hole 712, and the first connection hole 712 is located in the second region 102 of the first stack structure 710.

[0231] In this step, the first connection hole 712 can pass through the first stack structure 710 to the semiconductor layer 600. The first connection hole 712 can be formed by any suitable process. For example, a patterned photoresist layer can be formed on the first stack structure 710. The patterned photoresist layer can expose a portion of the first stack structure 710 for forming the first connection hole 712. A suitable etching process can be performed to remove the portion of the first stack structure 710 for forming the first connection hole 712. For example, the etching process can include a dry etching process.

[0232] After forming the first connection hole 712, the patterned photoresist layer on the first stack structure 710 can be removed, and the surface of the first stack structure 710 can be planarized, for example, by chemical mechanical polishing (CMP) to remove the patterned photoresist layer on the first stack structure 710.

[0233] In some embodiments, in the step of removing a portion of the first stack structure 710 to form the first connection hole 712, a first gate slit 743 is also formed, and the first gate slit 743 is located in the first region 101 of the first stack structure 710.

[0234] In this step, continuing to refer to FIG. 21, a first channel hole 751 can also be formed, and the first gate slit is located between the first channel hole 751 and the first connection hole 712, and the first channel hole 751 and the first gate slit are both located in the first region 101 of the first stack structure 710. The first connection hole 712, the first gate slit, and the first channel hole 751 can be formed by one process step, for example, by a dry etching process. Forming the first connection hole 712, the first gate slit, and the first channel hole 751 by one process step is advantageous to simplify the process steps and thus save the manufacturing cost of the memory device 10.

[0235] With continued reference to FIG. 21, after the second stack structure 720 is formed, and before the first connection structure 230 is formed, there is further included: removing a portion of the second stack structure 720 to form a second connection hole 722, the second connection hole 722 is located in the second region 102 of the second stack structure 720, and the second connection hole 722 and the first connection hole 712 together form a connection hole 730.

[0236] In this step, the second connection hole 722 can be formed through the second stack structure 720 to the first connection hole 712. The second connection hole 722 can be formed by any suitable process. For example, a patterned photoresist layer can be formed on the second stack structure 720. The patterned photoresist layer can expose a portion of the second stack structure 720 for forming the second connection hole 722. A suitable etching process can be performed to remove the portion of the second stack structure 720 for forming the second connection hole 722. For example, the etching process can include a dry etching process.

[0237] After the second connection hole 722 is formed, the patterned photoresist layer on the second stack structure 720 can be removed, and the surface of the second stack structure 720 can be planarized, for example, by chemical mechanical polishing (CMP), to remove the patterned photoresist layer on the second stack structure 720.

[0238] In some embodiments, in the step of removing a portion of the second stack structure 720 to form the second connection hole 722, there is further included: forming a second gate slit 744, the second gate slit 744 is located in the first region 101 of the second stack structure 720, and the second gate slit 744 and the first gate slit 743 together form a gate slit 760.

[0239] In this step, with continued reference to FIG. 21, there is further included forming a second channel hole 752, the second gate slit is located between the second channel hole 752 and the second connection hole 722, and the second channel hole 752 and the second gate slit are both located in the first region 101 of the second stack structure 720. The second connection hole 722, the second gate slit, and the second channel hole 752 can be formed by one process step. For example, by a dry etching process. Forming the second connection hole 722, the second gate slit, and the second channel hole 752 by one process step is advantageous to simplify the process steps, thereby saving the manufacturing cost of the memory device 10.

[0240] After the second stack structure 720 is formed, and before the first connection structure 230 is formed, as shown in FIG. 21 and FIG. 22, there is further included: replacing the first sacrificial layer 711 with a first gate layer 211, and replacing the second sacrificial layer 721 with a second gate layer 221.

[0241] The first connection structure 230 is formed by depositing a conductive material in the connection hole 730 to form the first connection structure 230, as shown in FIGS. 21 and 22. Exemplarily, the conductive material includes, but is not limited to, one or more of a combination of tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, silicide, or other suitable conductive materials.

[0242] The deposition process includes, but is not limited to, one or more thin film deposition processes such as physical vapor deposition (PVD), chemical vapor deposition (CVD), and atomic layer deposition (ALD).

[0243] The preparation method in this embodiment can form the first connection hole 712, the first gate slit, and the first channel hole 751 through one process step, and form the second connection hole 722, the second gate slit, and the second channel hole 752 through one process step, which is advantageous to simplify the preparation process steps and save the preparation cost of the memory device 10.

[0244] In some embodiments, referring to FIGS. 22 and 23, after the first stack structure 710 is formed and before the part of the first stack structure 710 is removed, as shown in FIG. 23, the method further includes: forming a first recess 713, the first recess 713 is located in the second region 102 of the first stack structure 710, and the first recess 713 penetrates through part of the first stack structure 710 along the first direction X, wherein the second region 102 of the first stack structure 710 includes a plurality of third dielectric layers 271 and a plurality of fourth dielectric layers 272 alternately stacked along the first direction X, and at least one third dielectric layer 271 is connected with the first sacrificial layer 711.

[0245] In this step, continuing to refer to FIG. 23, the third dielectric layer 271 and the first sacrificial layer 711 can be film layers formed by a one-time patterning process. The fourth dielectric layer 272 and the first dielectric layer 212 can be film layers formed by a one-time patterning process. The patterning process refers to a process capable of forming at least one pattern having a certain shape. For example, a thin film is formed on a substrate by any one of various film formation processes such as deposition, coating, sputtering, etc., and then the thin film is patterned to form a film layer containing at least one pattern, which is called a pattern layer. The patterning step includes coating photoresist, exposure, development, etching, and stripping photoresist, etc.

[0246] Referring to FIGS. 23, 24, 25, and 26, after the first recess 713 is formed, the method further includes: forming a first connection sacrificial layer 714.

[0247] In this step, referring to FIG. 24 and FIG. 25, forming the first connection sacrificial layer 714 includes forming a first sub-insulation layer 2331 covering the sidewall of the first recess 713. For example, an insulation material, such as one or more of silicon oxide, silicon nitride, and high dielectric constant insulation material, or other insulation material, can be deposited in the first recess 713. After the insulation material is deposited in the first recess 713, the insulation material on the bottom of the first recess 713 and the fourth dielectric layer 272 on the bottom of the first recess 713 can be removed to form the first sub-insulation layer 2331 covering the sidewall of the first recess 713 and exposing the third dielectric layer 271.

[0248] Referring to FIG. 26 and FIG. 27, after the first sub-insulation layer 2331 is formed, a dielectric material is deposited in the first recess 713, covering the bottom of the first recess 713. The dielectric material covering the bottom of the first recess 713 is ion implanted to remove the dielectric material covering the sidewall of the first recess 713 to form the first connection sacrificial layer 714. The first connection sacrificial layer 714 covers the bottom of the first recess 713 and is in contact with the third dielectric layer 271.

[0249] Referring to FIG. 28, after the first connection sacrificial layer 714 is formed, further including forming a first insulation layer 233 in the first recess 713. In this step, as shown in FIG. 28, forming the first insulation layer 233 includes forming a second sub-insulation layer 2332 in the first recess 713, which can be formed by depositing an insulation material in the first recess 713 using one or more thin film deposition processes, such as but not limited to PVD, CVD, ALD. The second sub-insulation layer 2332 and the first sub-insulation layer 2331 together form the first insulation layer 233.

[0250] In some embodiments, as shown in FIG. 29, after the first insulation layer 233 is formed, part of the first stack structure 710 is removed to form the first connection hole 712, wherein removing part of the first stack structure 710 includes removing the first insulation layer 233, removing the first connection sacrificial layer 714, and removing the plurality of third dielectric layers 271 and the plurality of fourth dielectric layers 272 stacked to form the first connection hole 712.

[0251] In this step, an etching process can be used to remove part of the first insulation layer 233, remove part of the first connection sacrificial layer 714, and remove part of the plurality of third dielectric layers 271 and the plurality of fourth dielectric layers 272 stacked to form the first connection hole 712. The etching process includes a dry etching process or a wet etching process.

[0252] As shown in FIG. 29, after forming the first connection hole 712, a sacrificial material can be filled in the first connection hole 712 to facilitate subsequent formation of the second stack structure 720 on the first stack structure 710.

[0253] In some embodiments, as shown in FIG. 29, after filling the sacrificial material in the first connection hole 712, the second stack structure 720 can be formed on the first stack structure 710 by employing one or more thin film deposition processes including, but not limited to, PVD, CVD, ALD.

[0254] In some embodiments, as shown in FIG. 29, after forming the second stack structure 720, and before removing part of the second stack structure 720, the method further comprises: forming a second groove 723, the second groove 723 is located in the second region 102 of the second stack structure 720, and the second groove 723 penetrates part of the second stack structure 720 along the first direction X, wherein the second region 102 of the second stack structure 720 comprises a plurality of fifth dielectric layers 281 and a plurality of sixth dielectric layers 282 alternately stacked along the first direction X, and at least one of the fifth dielectric layers 281 is connected with the second sacrificial layer 721.

[0255] In this step, with continuous reference to FIG. 29, the fifth dielectric layer 281 and the second sacrificial layer 721 can be film layers formed by a one-time patterning process. The sixth dielectric layer 282 and the second dielectric layer 222 can be film layers formed by a one-time patterning process.

[0256] After forming the second groove 723, as shown in FIG. 30, the method further comprises: forming a second connection sacrificial layer 724. The second connection sacrificial layer 724 covers the groove bottom of the second groove 723, and the second connection sacrificial layer 724 is in contact with the fifth dielectric layer 281. The specific preparation method of the second connection sacrificial layer 724 can refer to the preparation method of the first connection sacrificial layer 714 described above, which will not be repeated here.

[0257] After forming the second connection sacrificial layer 724, the method further comprises: forming a second isolation layer 234, the second isolation layer 234 is located in the second groove 723.

[0258] Removing part of the second stack structure 720 to form the second connection hole 722 comprises: removing the second isolation layer 234, removing the second connection sacrificial layer 724, and removing the plurality of fifth dielectric layers 281 and the plurality of sixth dielectric layers 282 stacked to form the second connection hole 722.

[0259] In this step, an etching process can be employed to remove part of the second isolation layer 234, remove part of the second connection sacrificial layer 724, and remove part of the plurality of fifth dielectric layers 281 and the plurality of sixth dielectric layers 282 stacked to form the second connection hole 722. The etching process includes a dry etching process or a wet etching process.

[0260] After the second connection hole 722 is formed, the sacrificial material located in the first connection hole 712 can be removed, so that the first connection hole 712 and the second connection hole 722 are in communication, and the first connection hole 712 and the second connection hole 722 jointly constitute a connection hole 730. For example, when the sacrificial material includes carbon, the process of removing the sacrificial material located in the first connection hole 712 can include Ashing to remove all the sacrificial material located in the first connection hole 712.

[0261] In some embodiments, as shown in FIGS. 31, 32, 33 and 34, forming the first connection structure 230 in the connection hole includes: removing the first connection sacrificial layer 714 and the second connection sacrificial layer 724 to form a first recessed space 715 and a second recessed space 725, the first recessed space 715 being in communication with the first connection hole 712, and the second recessed space 725 being in communication with the second connection hole 722.

[0262] In this step, as shown in FIGS. 31 and 32, the first connection sacrificial layer 714 and the second connection sacrificial layer 724 can be removed by injecting an etching liquid into the connection hole 730. The etching rate of the etching liquid on the third dielectric layer 271 and the fifth dielectric layer 281 is greater than the etching rate of the etching liquid on the fourth dielectric layer 272 and the sixth dielectric layer 282. In addition, the etching rate of the etching liquid on the first connection sacrificial layer 714 and the second connection sacrificial layer 724 can be approximately the same as the etching rate of the etching liquid on the third dielectric layer 271 and the fifth dielectric layer 281, or the etching rate of the etching liquid on the first connection sacrificial layer 714 and the second connection sacrificial layer 724 can be less than the etching rate of the etching liquid on the third dielectric layer 271 and the fifth dielectric layer 281.

[0263] In this step, when the first connection sacrificial layer 714 and the second connection sacrificial layer 724 are removed, part of the third dielectric layer 271 and part of the fifth dielectric layer 281 can also be removed to form a third recessed space 717 and a fourth recessed space 727, the third recessed space 717 being in communication with the first connection hole 712, and the fourth recessed space 727 being in communication with the second connection hole 722.

[0264] Since the first connecting sacrificial layer 714 is in contact with the third dielectric layer 271, and the second connecting sacrificial layer 724 is in contact with the fifth dielectric layer 281, in the first direction X, the thickness of the first connecting sacrificial layer 714 and the third dielectric layer 271 is greater than the thickness of the third dielectric layer 271; in the first direction X, the thickness of the second connecting sacrificial layer 724 and the fifth dielectric layer 281 is greater than the thickness of the fifth dielectric layer 281. Therefore, after the etching solution is injected into the connecting hole 730, in the second direction Y, the third dielectric layer 271 in contact with the first connecting sacrificial layer 714 is etched to a length less than the length of the other third dielectric layer 271; in the second direction Y, the fifth dielectric layer 281 in contact with the second connecting sacrificial layer 724 is etched to a length less than the length of the other fifth dielectric layer 281.

[0265] The first connecting sacrificial layer 714 and the second connecting sacrificial layer 724 are removed to form a first recessed space 715 and a second recessed space 725, wherein the first recessed space 715 is in communication with the first connecting hole 712, and the second recessed space 725 is in communication with the second connecting hole 722. It should be noted that the first connecting sacrificial layer 714 and the second connecting sacrificial layer 724 can be partially removed or completely removed.

[0266] It should be noted that the first isolation layer 233 can protect the third dielectric layer 271 and the fourth dielectric layer 272 around the first isolation layer 233 from being etched, and the second isolation layer 234 can protect the fifth dielectric layer 281 and the sixth dielectric layer 282 around the second isolation layer 234 from being etched. Therefore, in this step, an etching process can be used, and an etching solution with a fast etching rate for the third dielectric layer 271 and the fifth dielectric layer 281 and a slow etching rate for the fourth dielectric layer 272 and the sixth dielectric layer 282 (or no etching of the fourth dielectric layer 272 and the sixth dielectric layer 282) can be selected to remove the portion of the third dielectric layer 271 exposed in the first connecting hole 712 and the portion of the fifth dielectric layer 281 exposed in the second connecting hole 722 to form a third recessed space 717 and a fourth recessed space 727.

[0267] In addition, referring to FIGS. 32 and 33, a third isolation layer 235 can be formed in the third recessed space 717 and a fourth isolation layer 236 can be formed in the fourth recessed space 727 by using one or more thin film deposition processes, not limited to PVD, CVD, ALD, to protect the third dielectric layer 271 and the fifth dielectric layer 281 from being etched in subsequent preparation processes.

[0268] It is to be noted that, in the first direction X, the thickness of the first connecting sacrificial layer 714 and a third dielectric layer 271 is greater than the thickness of the third dielectric layer 271; in the first direction X, the thickness of the second connecting sacrificial layer 724 and a fifth dielectric layer 281 is greater than the thickness of the fifth dielectric layer 281. Therefore, when the third isolation layer 235 is formed in the third recessed space 717 and the fourth isolation layer 236 is formed in the fourth recessed space 727, the third isolation layer 235 formed on the third dielectric layer 271 exposed in the first recessed space 715 is thinner, and the fourth isolation layer 236 formed on the fifth dielectric layer 281 exposed in the second recessed space 725 is thinner. The third isolation layer 235 formed on the third dielectric layer 271 exposed in the first recessed space 715 and the fourth isolation layer 236 formed on the fifth dielectric layer 281 exposed in the second recessed space 725 can be removed by a small amount of etching liquid. And, the third isolation layer 235 formed in the third recessed space 717 and the fourth isolation layer 236 formed in the fourth recessed space 727 are retained.

[0269] After forming the first recessed space 715 and the second recessed space 725, as shown in FIGS. 32 and 33, it further includes: removing the third dielectric layer 271 exposed in the first recessed space 715 and the fifth dielectric layer 281 exposed in the second recessed space 725 to form a first filling space 716 and a second filling space 726, the first filling space 716 communicates with the first recessed space 715, and the second filling space 726 communicates with the second recessed space 725.

[0270] Please refer to FIGS. 33 and 34, after forming the first filling space 716 and the second filling space 726, it further includes: filling a conductive material in the connecting hole 730 to form a first connecting structure 230.

[0271] The disclosure further provides a preparation method of a memory device, as shown in FIG. 35, after forming the first stacked structure 710 and before removing part of the first stacked structure 710, it further includes: forming a third recess 718, the third recess 718 is located in the second region 102 of the first stacked structure 710, and the third recess 718 penetrates part of the first stacked structure 710 along the first direction X, wherein the second region 102 of the first stacked structure 710 includes a plurality of third dielectric layers 271 and fourth dielectric layers 272 arranged alternately along the first direction, and at least one third dielectric layer 271 is connected with the first sacrificial layer 711.

[0272] In this step, the third dielectric layer 271 and the first sacrificial layer 711 can be a film layer formed by a one-time patterning process. The fourth dielectric layer 272 and the first dielectric layer 212 can be a film layer formed by a one-time patterning process.

[0273] After the third recess 718 is formed, as shown in FIG. 35, further comprising: forming a first sub-insulating layer 2331 covering the slot wall of the third recess 718.

[0274] In this step, after the insulating material is deposited in the third recess 718, the insulating material at the slot bottom of the third recess 718 is removed to form the first sub-insulating layer 2331.

[0275] After the first sub-insulating layer 2331 is formed, as shown in FIG. 35, further comprising: forming a second sub-insulating layer 2332 covering the slot bottom of the third recess 718 and contacting the third dielectric layer 271, and the second sub-insulating layer 2332 also covers one side of the first sub-insulating layer 2331.

[0276] After the second sub-insulating layer 2332 is formed, as shown in FIG. 35, further comprising: forming a third sub-insulating layer 2333 in the third recess 718, the third sub-insulating layer 2333 covering the second sub-insulating layer 2332, the first sub-insulating layer 2331, the second sub-insulating layer 2332 and the third sub-insulating layer 2333 together constitute the first insulating layer 233.

[0277] After the second sub-insulating layer 2332 is formed, as shown in FIG. 36, further comprising: removing part of the first stack structure 710 to form a first connection hole 712. The first connection hole 712 penetrates the first stack structure 710, and the first connection hole 712 is located in the first region 101 of the first stack structure 710.

[0278] In this step, as shown in FIG. 35 and FIG. 36, comprising: removing the second sub-insulating layer 2332, the third sub-insulating layer 2333, the plurality of third dielectric layers 271 and the plurality of fourth dielectric layers 272 to form the first connection hole 712. After the first connection hole 712 is formed, a sacrificial material can be deposited in the first connection hole 712 to facilitate the subsequent formation of the second stack structure 720 on the first stack structure 710.

[0279] In some embodiments, as shown in FIG. 37, after the second stack structure 720 is formed and before part of the second stack structure 720 is removed, further comprising: forming a fourth recess 728, the fourth recess 728 being located in the second region 102 of the second stack structure 720, and the fourth recess 728 penetrating part of the second stack structure 720 along the first direction X. Wherein the second region 102 of the second stack structure 720 comprises a plurality of fifth dielectric layers 281 and a plurality of sixth dielectric layers 282 arranged alternately along the first direction X, and at least one fifth dielectric layer 281 is connected with the second sacrificial layer 721.

[0280] In this step, continuing to refer to Figure 37, the fifth dielectric layer 281 and the second sacrificial layer 721 can be film layers formed by a one-time patterning process. The sixth dielectric layer 282 and the second dielectric layer 222 can be film layers formed by a one-time patterning process.

[0281] After the fourth recess 728 is formed, as shown in Figures 37 and 38, it further includes: forming a fourth sub-isolation layer 2341 covering the groove wall of the fourth recess 728. A fifth sub-isolation layer 2342 is formed covering the groove bottom of the fourth recess 728 and the fourth sub-isolation layer 2341, and the fifth sub-isolation layer 2342 is in contact with the fifth dielectric layer 281. A sixth sub-isolation layer 2343 is formed in the fourth recess 728, covering the fifth sub-isolation layer 2342, the fourth sub-isolation layer 2341, the fifth sub-isolation layer 2342 and the sixth sub-isolation layer 2343 together constitute the second isolation layer 234.

[0282] In this step, the method of forming the fourth sub-isolation layer 2341, the fifth sub-isolation layer 2342 and the sixth sub-isolation layer 2343 can refer to the preparation method of the first sub-isolation layer 2331, the second sub-isolation layer 2332 and the third sub-isolation layer 2333 in some of the previous embodiments, which will not be repeated here.

[0283] Please refer to Figures 38 and 39, after the second isolation layer 234 is formed, it further includes: removing part of the second stacked structure 720 to form the second connection hole 722.

[0284] In this step, removing part of the second stacked structure 720 includes: removing the fifth sub-isolation layer 2342, the sixth sub-isolation layer 2343, the plurality of fifth dielectric layers 281 and the plurality of sixth dielectric layers 282 to form the second connection hole 722.

[0285] Please refer to Figures 39 and 40, in the step of removing part of the first stacked structure 710 to form the first connection hole 712, the first gate gap 743 can be formed simultaneously, which is located in the first area 101 of the first stacked structure 710. In the step of removing part of the second stacked structure 720 to form the second connection hole 722, the second gate gap 744 can be formed simultaneously, which is located in the first area 101 of the second stacked structure 720.

[0286] After the second gate gap 744 is formed, the first sacrificial layer 711 can be replaced by the first gate layer 211, and the second sacrificial layer 721 can be replaced by the second gate layer 221.

[0287] In this step, as shown in FIGS. 39 and 40, the method includes: injecting etching liquid in the gate slit 760, removing the first sacrificial layer 711 and the second sacrificial layer 721 to form a fifth filling space 747 and a sixth filling space 748. Depositing a gate material in the fifth filling space 747 and the sixth filling space 748 to form a first gate layer 211 and a second gate layer 221.

[0288] In some embodiments, as shown in FIGS. 35, 40, 41 and 42, forming the first connection structure 230 in the connection hole 730 includes: removing the second sub-isolation layer 2332 located at the bottom of the third groove 718 and the fifth sub-isolation layer 2342 located at the bottom of the fourth groove 728 to form a fifth recessed space 719 and a sixth recessed space 729, the fifth recessed space 719 being in communication with the first connection hole 712, and the sixth recessed space 729 being in communication with the second connection hole 722.

[0289] In this step, as shown in FIGS. 40 and 41, before removing the second sub-isolation layer 2332 located at the bottom of the third groove 718 and the fifth sub-isolation layer 2342 located at the bottom of the fourth groove 728, the method further includes: removing part of the second dielectric layer 222 and part of the fourth dielectric layer 272 to form a seventh recessed space 741 and an eighth recessed space 742, the seventh recessed space 741 being in communication with the first connection hole 712, and the eighth recessed space 742 being in communication with the second connection hole 722. Forming a third isolation layer 235 in the seventh recessed space 741 and forming a fourth isolation layer 236 in the eighth recessed space 742 to protect the second dielectric layer 222 and the fourth dielectric layer 272 from being damaged in subsequent etching processes.

[0290] As shown in FIG. 41, after forming the fifth recessed space 719 and the sixth recessed space 729, the method further includes: removing the third dielectric layer 271 exposed to the fifth recessed space 719, and removing the fifth dielectric layer 281 exposed to the sixth recessed space 729 to form a third filling space 745 and a fourth filling space 746, the third filling space 745 being in communication with the fifth recessed space 719, and the fourth filling space 746 being in communication with the sixth recessed space 729.

[0291] As shown in FIGS. 41 and 42, after forming the third filling space 745 and the fourth filling space 746, the method further includes: filling a conductive material in the connection hole 730 to form the first connection structure 230.

[0292] In some embodiments, as shown in FIG. 43, forming the first stack structure 710 includes: forming a first sub-stack structure 7101, the first sub-stack structure 7101 including a first sub-gate slit 7431 and a first channel hole 751.

[0293] In this step, the first sub-gate slit 7431 and the first channel hole 751 can be formed on the first sub-layer structure 7101 by an etching process. The first sub-gate slit 7431 and the first channel hole 751 are located in the first region 101 of the first sub-layer structure 7101.

[0294] With continued reference to FIG. 43, after the first sub-gate slit 7431 and the first channel hole 751 are formed, a sacrificial material can be filled in the first sub-gate slit 7431 and the first channel hole 751 to facilitate the formation of the second sub-layer structure 7102 on the first sub-layer structure 7101 in subsequent fabrication steps.

[0295] With continued reference to FIG. 43, after the first sub-gate slit 7431 and the first channel hole 751 are formed, a sacrificial material can be filled in the first sub-gate slit 7431 and the first channel hole 751 to facilitate the formation of the second sub-layer structure 7102 on the first sub-layer structure 7101 in subsequent fabrication steps.

[0296] The second sub-layer structure 7102 is formed on the side of the etching stop layer 749 away from the first sub-gate slit 7431 and the first channel hole 751. The second sub-layer structure 7102 and the first sub-layer structure 7101 together form the first layer structure 710.

[0297] In the step of removing part of the first layer structure 710 to form the first connection hole 712, the second sub-gate slit 7432 and the second channel hole 752 are formed. The second sub-gate slit 7432 and the first sub-gate slit together form the first gate slit. The second channel hole 752 and the first channel hole 751 together form the channel hole 750. The first gate slit and the channel hole 750 are located in the first region 101 of the first layer structure 710.

[0298] In this step, as shown in FIG. 43, in the step of removing part of the first layer structure 710, the first connection hole 712, the second sub-gate slit 7432 and the second channel hole 752 are formed. However, the first connection hole 712 penetrates through the first sub-layer structure 7101 and the second sub-layer structure 7102, while the second sub-gate slit 7432 and the second channel hole 752 only penetrate through the second sub-layer structure 7102, i.e., the etching depth of the first connection hole 712 is different from the etching depth of the second sub-gate slit 7432, and the etching depth of the first connection hole 712 is different from the etching depth of the second channel hole 752. Therefore, in this step, the etching stop layer 749 is formed on the first sub-gate slit 7431 and the first channel hole 751 before the second sub-layer structure 7102 is formed, which is beneficial to protect the first sub-gate slit and the first channel hole 751 from being etched when the first connection hole 712, the second sub-gate slit 7432 and the second channel hole 752 are formed, thereby protecting the structural shape of the channel hole 750.

[0299] In this embodiment, the step of forming the first stack structure 710 can include forming a first sub-stack structure 7101 and a second sub-stack structure 7102, and so on. The second stack structure 720 can also be formed by the same preparation steps to form two sub-stack structures, or multiple sub-stack structures.

[0300] Some embodiments of the present disclosure also provide another preparation method of a memory device, which is explained and described below in combination with FIG. 23-44.

[0301] FIG. 44 is a flow chart of a preparation method of a memory device according to some embodiments. As shown in FIG. 44, the preparation method of the memory device includes S5-S7.

[0302] S5, forming a first stack structure, the first stack structure including a plurality of first gate layers and a plurality of first dielectric layers alternately stacked along a first direction.

[0303] In this step, referring to FIG. 42, the plurality of first gate layers 211 and the plurality of first dielectric layers 212 alternately stacked along the first direction X can be formed by using one or more thin film deposition processes including but not limited to PVD, CVD, ALD.

[0304] S6, forming a second stack structure, the second stack structure including a plurality of second gate layers and a plurality of second dielectric layers alternately stacked along the first direction; the second stack structure and the first stack structure being stacked along the first direction.

[0305] In this step, referring to FIG. 42, the plurality of second gate layers 221 and the plurality of second dielectric layers 222 alternately stacked along the first direction X can be formed on the first stack structure 210 by using one or more thin film deposition processes including but not limited to PVD, CVD, ALD.

[0306] S7, forming a first connection structure, the first connection structure including a connection column, at least one first connection layer and at least one second connection layer, the connection column being located at one side of the first stack structure and the second stack structure along a second direction, the first connection layer being parallel to the second direction, one first connection layer connecting the connection column and one first gate layer; the second connection layer being parallel to the second direction, one second connection layer connecting the connection column and one second gate layer; the second direction intersecting the first direction.

[0307] In this step, referring to FIG. 42, the first connection structure 230 can be formed on one side of the first stack structure 210 and the second stack structure 220 along the second direction Y by using etching and deposition processes.

[0308] Exemplarily, the constituent material of the first connection structure 230 can include a conductive material, which includes but is not limited to one or more of a combination of tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, silicide, or can also be other suitable conductive materials.

[0309] The memory device 10 prepared through the above steps can be electrically connected to at least one first gate layer 211 and at least one second gate layer 221 through the first connection structure 230 by one SD device. One first gate layer 211 and one second gate layer 221 can share one first connection structure 230 and share one SD device. Then, when the memory device 10 has two stacked structures (i.e., the first stacked structure 210 and the second stacked structure 220), compared with one first gate layer 211 connected to one SD device through one gate line contact G-CNT and one second gate layer 221 connected to one SD device through one gate line contact G-CNT, the number of the first connection structure 230 in the embodiment is less than the number of the gate line contact G-CNT, and the number of the SD device in the embodiment is also less, so the area occupied by the first connection structure 230 is less than the area occupied by the gate line contact G-CNT, and at the same time, the area occupied by the SD device is also reduced, which is beneficial to improve the storage density of the memory device 10.

[0310] In some embodiments, as shown in FIG. 23, the first stacked structure 210 is formed, including: forming a first laminated structure 710, the first region 101 of the first laminated structure 710 includes a plurality of first sacrificial layers 711 and a plurality of first dielectric layers 212 alternately stacked along a first direction, the first region 101 of the first laminated structure 710 is adjacent to the second region 102 of the first laminated structure 710, and the second region 102 of the first laminated structure 710 is located on one side of the first region 101 of the first laminated structure 710 along a second direction Y, the second direction Y is perpendicular to the first direction X.

[0311] In this step, as shown in FIG. 23, for example, a deposition process can be used to alternately form the first dielectric layer 212 and the first sacrificial layer 711. Exemplarily, the material of the first dielectric layer 212 can be silicon oxide, and the material of the first sacrificial layer 711 can be silicon nitride.

[0312] The second stack structure 220 is formed by forming a second layer stack structure 720, the second layer stack structure 720 is arranged in the first direction with the first layer stack structure 710, the first area 101 of the second layer stack structure 720 comprises a plurality of second sacrificial layers 721 and a plurality of second dielectric layers 222 arranged alternately in the first direction, the first area 101 of the second layer stack structure 720 is adjacent to the second area 102 of the second layer stack structure 720, and the second area 102 of the second layer stack structure 720 is located on one side of the first area 101 of the second layer stack structure 720 in the second direction Y.

[0313] In this step, as shown in FIG. 21, the second dielectric layer 222 and the second sacrificial layer 721 can be alternately formed on the first layer stack structure 710 by using a deposition process. For example, the material of the second dielectric layer 222 can be silicon oxide, and the material of the second sacrificial layer 721 can be silicon nitride.

[0314] After the first layer stack structure 710 is formed and before the second layer stack structure 720 is formed, the first layer stack structure 710 is removed partially to form a first connection hole 712, and the first connection hole 712 is located in the second area 102 of the first layer stack structure 710.

[0315] In this step, as shown in FIG. 21, the first connection hole 712 can be formed by using an etching process.

[0316] The second layer stack structure 720 is removed partially to form a second connection hole 722, the second connection hole 722 penetrates the second area 102 of the second layer stack structure 720, and the second connection hole 722 and the first connection hole 712 jointly form a connection hole.

[0317] As shown in FIG. 33 and FIG. 34, after the second layer stack structure 720 is formed, the first filling space 716 and the second filling space 726 are formed, the first filling space 716 is located in the second area 102 of the first layer stack structure 710, the first filling space 716 communicates with the first connection hole 712, the second filling space 726 is located in the second area 102 of the first layer stack structure 710, and the second filling space 726 communicates with the second connection hole 722.

[0318] The process steps for forming the first filling space 716 and the second filling space 726 can refer to some embodiments described above, which will not be described here.

[0319] As shown in FIG. 30, FIG. 31, FIG. 32 and FIG. 33, the first sacrificial layer 711 is replaced by the first gate layer 211, and the second sacrificial layer 721 is replaced by the second gate layer 221. At least one layer of the first gate layer 211 communicates with the first filling space 716, and at least one layer of the second gate layer 221 communicates with the second filling space 726.

[0320] The process steps of replacing the first sacrificial layers 711 with the first gate layers 211 and replacing the second sacrificial layers 721 with the second gate layers 221 can refer to some embodiments described above, and will not be described here again.

[0321] As shown in FIGS. 33 and 34, the first connection structure 230 is formed by filling the conductive material in the connection holes 730 to form the first connection structure 230; wherein the conductive material filled in the connection holes 730 forms the connection pillars, the conductive material filled in the first filling spaces 716 forms the first connection layers 2312, the conductive material filled in the second filling spaces 726 forms the second connection layers 2322, the first connection layers 2312 are parallel to the second direction, one first connection layer 2312 connects the connection pillar 237 and one first gate layer 211, the second connection layers 2322 are parallel to the second direction, one second connection layer 2322 connects the connection pillar 237 and one second gate layer 221, and the connection pillars, the first connection layers 2312 and the second connection layers 2322 together constitute the first connection structure 230.

[0322] The memory device 10 prepared by the above steps can be electrically connected to at least one first gate layer 211 and at least one second gate layer 221 through the first connection structure 230. One first gate layer 211 and one second gate layer 221 can share one first connection structure 230 and one SD device. This is conducive to controlling the area of the second region 102 and improving the storage density of the memory device 10.

[0323] Some embodiments of the present disclosure also provide another method for manufacturing a memory device, which will be explained and described below in combination with FIGS. 21-46.

[0324] Some embodiments of the present disclosure also provide a method for manufacturing a memory device, as shown in FIG. 45, comprising S8-S12.

[0325] S8, a first stack structure is formed, the first region of the first stack structure comprises a plurality of first sacrificial layers and a plurality of first dielectric layers arranged alternately along a first direction, the first region of the first stack structure is adjacent to a second region of the first stack structure, and the second region of the first stack structure is located on one side of the first region of the first stack structure along a second direction, and the second direction intersects the first direction.

[0326] In this step, as shown in FIG. 23, for example, a deposition process can be used to alternately form the first dielectric layers 212 and the first sacrificial layers 711. Exemplarily, the material of the first dielectric layers 212 can be silicon oxide, and the material of the first sacrificial layers 711 can be silicon nitride.

[0327] S9, a first selection gate is formed, and the first selection gate is located at the first region of the first stack structure.

[0328] In this step, referring to FIG. 46, a first selection gate 261 is formed on the first stack structure 710, and the first selection gate 261 is located at the first region 101 of the first stack structure 710.

[0329] S10, a bit line is formed on the first region of the first stack structure, the bit line is connected with the first selection gate, and an extension direction of the bit line intersects the first direction.

[0330] In this step, referring to FIG. 46, a bit line BL is formed on the first region 101 of the first stack structure 710, and an extension direction of the bit line BL intersects the first direction X. For example, the bit line BL can extend in the Y-Z plane, for example, the extension direction of the bit line BL can be parallel to the third direction Z.

[0331] S11, a second selection gate is formed, the second selection gate is located at a side of the bit line away from the first selection gate, and the second selection gate is connected with the bit line.

[0332] In this step, referring to FIG. 46, a second selection gate 262 is formed at a side of the bit line BL away from the first selection gate 261, and the second selection gate 262 is connected with the bit line BL.

[0333] S12, a second stack structure is formed, the second stack structure is located at a side of the second selection gate away from the first stack structure, a first region of the second stack structure includes a plurality of second sacrificial layers and a plurality of second dielectric layers which are alternately stacked along the first direction, the first region of the second stack structure is adjacent to a second region of the second stack structure, and the second region of the second stack structure is located at a side of the first region of the second stack structure along a second direction.

[0334] In this step, referring to FIG. 21, for example, a deposition process can be used to alternately form a second dielectric layer 222 and a second sacrificial layer 721 at a side of the second selection gate 262 away from the first stack structure 710. For example, the material of the second dielectric layer 222 can be silicon oxide, and the material of the second sacrificial layer 721 can be silicon nitride.

[0335] The memory device 10 prepared in this step has the bit line BL between the first stack structure 210 and the second stack structure 220, and the bit line BL is connected with the channel structure in the first stack structure 210, and the bit line BL is also connected with the channel structure in the second stack structure 220. Therefore, the bit line BL can drive the channel structure in the first stack structure 210 upward, and drive the channel structure in the second stack structure 220 downward. Compared with forming the bit line BL on the second stack structure 220, in this embodiment, the bit line BL is formed between the first stack structure 210 and the second stack structure 220, which is beneficial to improve the current intensity of the channel structure in the first stack structure 210 and the current intensity of the channel structure in the second stack structure 220, and improve the problem that the current intensity of the channel structure far away from the bit line BL is weak.

[0336] In some embodiments, as shown in FIG. 33, after the first stack structure 710 is formed, and before the second stack structure 720 is formed, the method further comprises: removing part of the first stack structure 710 to form a first connection hole 712, the first connection hole 712 is located in the second region 102 of the first stack structure 710. For example, an etching process can be used to remove part of the first stack structure 710.

[0337] After the second stack structure 720 is formed, the method further comprises: removing part of the second stack structure 720 to form a second connection hole 722, the second connection hole 722 is located in the second region 102 of the second stack structure 720, and the second connection hole 722 and the first connection hole 712 jointly constitute a connection hole 730. For example, an etching process can be used to remove part of the second stack structure 720.

[0338] After the connection hole 730 is formed, as shown in FIG. 33 and FIG. 37, the method further comprises: replacing the first sacrificial layer 711 with a first gate layer 211, and replacing the second sacrificial layer 721 with a second gate layer 221. A first connection structure 230 is formed in the connection hole 730, the first connection structure 230 is connected with at least one first gate layer 211, and the first connection structure 230 is connected with at least one second gate layer 221.

[0339] In this step, the first connection structure 230 can be formed in the connection hole 730 by using one or more thin film deposition processes, which include but are not limited to PVD, CVD, ALD.

[0340] The memory device 10 prepared by the above preparation method, one SD device can be electrically connected with at least one first gate layer 211 and at least one second gate layer 221 through the first connection structure 230. One first gate layer 211 and one second gate layer 221 can share one first connection structure 230 and one SD device, which is beneficial to control the occupied area of the second region 102 and improve the storage density.

[0341] Referring to FIGS. 2, 3 and 8, some embodiments of the present disclosure further provide a storage system 1000, which comprises the controller 20 and the memory device 10 provided by some embodiments described above (or the memory device 10 prepared by the preparation method of the memory device provided by some embodiments described above). The controller 20 is connected with the memory device 10. For example, the controller 20 can be configured to manage the data stored in the memory device 10 and communicate with an external device (such as a host), or the controller 20 can also be configured to control the operation of the memory device 10, such as read, erase and program operations, or the controller 20 can also be configured to manage various functions related to the data stored or to be stored in the memory device 10. The storage system 1000 can be integrated into various types of storage devices, which can be referred to some embodiments described above, and will not be described here.

[0342] Referring to FIGS. 1, 2 and 8, some embodiments of the present disclosure further provide an electronic device 3000, which comprises the mainboard 2000 and the storage system 1000 provided by some embodiments described above. The type of the electronic device 3000 can be referred to some embodiments described above, and will not be described here.

[0343] In the present embodiment, the storage system 1000 comprises the memory device 10 provided by some embodiments described above (or the memory device 10 prepared by the preparation method of the memory device provided by some embodiments described above). Since in the memory device 10 provided by some embodiments described above, the plurality of gate layers can be led out to be connected with the SD device through the first connection structure 230, and the plurality of gate layers can share one SD device, it is beneficial to improve the storage density of the memory device 10, and further improve the storage density of the storage system 1000, which is beneficial to improve the internal memory of the electronic device 3000, and is also beneficial to the miniaturization of the electronic device 3000.

[0344] The above merely provides the specific embodiments of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any changes or replacements within the technical scope disclosed by the present disclosure can be easily conceived by those skilled in the art, which shall be covered by the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure shall be subject to the protection scope of the claims.

Claims

1. A memory device, wherein, The memory device comprises: a first stack structure comprising a plurality of first gate layers and a plurality of first dielectric layers alternately stacked along a first direction; a second stack structure comprising a plurality of second gate layers and a plurality of second dielectric layers alternately stacked along the first direction, the second stack structure being stacked along the first direction with the first stack structure; a first connection structure located at one side of the first stack structure and the second stack structure along a second direction, the first connection structure being connected with at least one of the first gate layers and at least one of the second gate layers, the second direction intersecting the first direction; a bit line located between the first stack structure and the second stack structure, an extension direction of the bit line intersecting the first direction.

2. The memory device of claim 1, wherein, The first connection structure comprises a first connection sub-portion and a second connection sub-portion stacked along the first direction. The first connection sub-portion comprises a first connection pillar and at least one first connection layer, the first connection pillar extending along the first direction, and the first connection layer being parallel to the second direction, one first connection layer connecting the first connection pillar and one first gate layer. The second connection sub-portion comprises a second connection pillar and at least one second connection layer, the second connection pillar extending along the first direction and being connected with the first connection pillar. The second connection layer is parallel to the second direction, one second connection layer connecting the second connection pillar and one second gate layer.

3. The memory device of claim 2, wherein, The first connection sub-portion and the second connection sub-portion are an integral structure.

4. The memory device of claim 2, wherein, In the second direction, a size of an end of the first connection pillar close to the second connection pillar is greater than a size of an end of the second connection pillar close to the first connection pillar.

5. The memory device according to claim 4, wherein, In the second direction, a size of an end of the first connection pillar close to the second connection pillar is greater than a size of an end of the first connection pillar away from the second connection pillar. The first connection structure further comprises a first isolation layer and a second isolation layer.

6. The memory device of claim 2, wherein, The first isolation layer is located at one side of the first connection layer close to the second connection layer, and the first isolation layer is arranged around the first connection pillar. The second isolation layer is located at one side of the second connection layer away from the first connection layer, and the second isolation layer is arranged around the second connection pillar. A size of an end of the first isolation layer away from the first connection layer in the second direction is greater than a size of an end of the first isolation layer close to the first connection layer in the second direction. The first connection structure further comprises a third isolation layer and a fourth isolation layer.

7. The memory device of claim 6, wherein, The third isolation layer is located at one side of the first connection layer away from the first isolation layer, the third isolation layer being in contact with the first connection pillar and the third isolation layer being arranged around the first connection pillar.

8. The memory device of claim 6, wherein, The fourth isolation layer is located at one side of the second connection layer away from the second isolation layer, the fourth isolation layer being in contact with the second connection pillar and the fourth isolation layer being arranged around the second connection pillar. ​ The fourth isolation layer is located on a side of the second connection layer away from the second isolation layer; the fourth isolation layer is in contact with the second connection column and the fourth isolation layer is arranged around the second connection column.

9. The memory device of any one of claims 6-8, wherein, The first connection layer comprises a first sub-layer and a second sub-layer arranged in a stack along the first direction, the first sub-layer is located between the first isolation layer and the second sub-layer, and the first isolation layer is arranged around the first sub-layer.

10. The memory device of any one of claims 6-8, wherein, Further comprising: a third connection layer, the third connection layer is arranged around the connection column and connected with the first connection column, in the first direction, the edge of the side of the third connection layer away from the first isolation layer is connected with the first connection layer; The first connection layer is arranged around the third connection layer, and the first connection layer connects the first gate layer.

11. The memory device of claim 10, wherein, The first isolation layer comprises a first sub-isolation layer, a second sub-isolation layer and a third sub-isolation layer; The first sub-isolation layer is arranged around the connection column; The second sub-isolation layer is located between the first sub-isolation layer and the connection column, and the second sub-isolation layer is arranged around the connection column; The third sub-isolation layer is located between the second sub-isolation layer and the connection column, and the third sub-isolation layer is arranged around the connection column.

12. The memory device of claim 11, wherein, The edge of the side of the third connection layer close to the second sub-isolation layer extends towards the direction close to the second sub-isolation layer.

13. The memory device of any one of claims 1-8, wherein, Further comprising: A first selection gate, the first selection gate is located on a side of the first stack structure away from the second stack structure; A second selection gate, the second selection gate is located on a side of the first stack structure close to the second stack structure; A third selection gate, the third selection gate is located on a side of the second stack structure close to the first stack structure; the bit line connects the second selection gate and the third selection gate; A fourth selection gate, the fourth selection gate is located on a side of the second stack structure away from the first stack structure.

14. The memory device of claim 13, wherein, The first stack structure comprises: A first sub-stack structure and a second sub-stack structure arranged in a stack along the first direction; A first channel structure and a second channel structure, the first channel structure penetrates through the first sub-stack structure, and the second channel structure penetrates through the second sub-stack structure; The first channel structure is located between the first selection gate and the second selection gate.

15. The memory device of any one of claims 2-8, wherein, The memory device comprises a first region and a second region, the first region is adjacent to the second region, the first stack structure and the second stack structure are located in the first region, and the first connection structure is located in the second region; The second region is located on a side of the first region; Alternatively, the first region comprises a first sub-region and a second sub-region, and the second region is located between the first sub-region and the second sub-region.

16. The memory device of claim 15, wherein, Further comprising: a third stack structure and a fourth stack structure arranged in a stack along the first direction, the third stack structure and the fourth stack structure are located in the second region; The first connecting column penetrates the third stack structure, the third stack structure comprising a plurality of third dielectric layers and a plurality of fourth dielectric layers alternately stacked along the first direction, at least one of the third dielectric layers being connected with at least one of the first connecting layers; The second connecting column penetrates the fourth stack structure, the fourth stack structure comprising a plurality of fifth dielectric layers and a plurality of sixth dielectric layers alternately stacked along the first direction, at least one of the fifth dielectric layers being connected with at least one of the second connecting layers.

17. The memory device of claim 14, wherein, Further comprising: A second connecting structure; The second connecting structure is located at one side of the first stack structure and the second stack structure along the second direction; One of the first selection gate and the second selection gate is connected with the second connecting structure.

18. A memory device, wherein, Comprising: A first stack structure comprising a plurality of first gate layers and a plurality of first dielectric layers alternately stacked along a first direction; A second stack structure comprising a plurality of second gate layers and a plurality of second dielectric layers alternately stacked along the first direction; The second stack structure and the first stack structure are stacked along the first direction; A first connecting structure comprising: a connecting column, at least one first connecting layer and at least one second connecting layer, the connecting column being located at one side of the first stack structure and the second stack structure along a second direction, the first connecting layer being parallel to the second direction, one of the first connecting layers connecting the connecting column and one of the first gate layers; The second connecting layer is parallel to the second direction, one of the second connecting layers connecting the connecting column and one of the second gate layers; the second direction intersects the first direction.

19. The memory device of claim 18, wherein, Further comprising: A first selection gate, the first selection gate being located at one side of the first stack structure away from the second stack structure; A second selection gate, the second selection gate being located at one side of the first stack structure close to the second stack structure; A third selection gate, the third selection gate being located at one side of the second stack structure close to the first stack structure; A fourth selection gate, the fourth selection gate being located at one side of the second stack structure away from the first stack structure; A second connecting structure, the second connecting structure being located at one side of the first stack structure and the second stack structure along the second direction; One of the first selection gate, the second selection gate, the third selection gate and the fourth selection gate is connected with the second connecting structure.

20. The memory device of claim 19, wherein, Further comprising: A first bit line and a second bit line, the first bit line being located at one side of the first selection gate away from the first stack structure, the second bit line being located at one side of the fourth selection gate away from the first stack structure; the extension direction of the first bit line and the second bit line intersects the first direction.

21. The memory device of claim 18, wherein, The memory device comprises a first region and a second region, the first region and the second region being adjacent in the second direction, the first stack structure and the second stack structure being located in the first region, the first connecting structure being located in the second region; The second region is located at one side of the first region; Alternatively, the first region includes a first sub-region and a second sub-region, and the second region is located between the first sub-region and the second sub-region.

22. A memory device, wherein, Comprise: A first stack structure and a second stack structure are arranged in a first direction, the first stack structure includes a plurality of first gate layers and a plurality of first dielectric layers arranged alternately in the first direction, and the second stack structure includes a plurality of second gate layers and a plurality of second dielectric layers arranged alternately in the first direction; A first selection gate and a second selection gate, the first selection gate is located on one side of the first stack structure close to the second stack structure, and the second selection gate is located on one side of the second stack structure close to the first stack structure; A bit line is located between the first selection gate and the second selection gate, and the extension direction of the bit line intersects the first direction.

23. The memory device of claim 22, wherein, Also include: A first connection structure; The first connection structure is located on one side of the first stack structure and the second stack structure along a second direction, the first connection structure is connected with at least one of the first gate layer, and the first connection structure is connected with at least one of the second gate layer, and the second direction intersects the first direction.

24. The memory device of claim 22, wherein, Also include: A third selection gate and a fourth selection gate, the third selection gate is located on one side of the first stack structure away from the second stack structure, and the fourth selection gate is located on one side of the second stack structure away from the first stack structure; A second connection structure, the second connection structure is located on one side of the first stack structure and the second stack structure along the second direction; One of the first selection gate, the second selection gate, the third selection gate and the fourth selection gate is connected with the second connection structure.

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