Display apparatus, control method, electronic device and computer-readable storage medium

Abstract

A display apparatus, a control method, an electronic device and a computer-readable storage medium. The display apparatus (300) comprises a display substrate (310) and a source driver (320). The source driver (320) comprises a first cache module (322), a second cache module (324), a third cache module (325), an operation conversion module (323) and an output module. The operation conversion module (323) is configured to receive N pieces of initial data transmitted by the first cache module (322), output M pieces of data to the second cache module (324) on the basis of the N pieces of initial data, obtain T pieces of interpolation data on the basis of some of the N pieces of initial data, and output the T pieces of interpolation data to the third cache module (325). The output module is configured to output the M pieces of data of the second cache module (324) to M data signal lines. The operation conversion module (323) is further configured to receive S pieces of initial data transmitted by the first cache module (322), and output (M-T) pieces of data to the second cache module (324) on the basis of the S pieces of initial data. The output module is further configured to output the (M-T) pieces of data of the second cache module (324) and the T pieces of interpolation data of the third cache module (325) to the M data signal lines.

Description

Display device, control method, electronic device, and computer-readable storage medium TECHNICAL FIELD

[0001] Embodiments of the present disclosure relate to a display device, a control method for a display device, an electronic device, and a computer-readable storage medium. BACKGROUND

[0002] With the development of the display industry and the improvement of people's material level, display systems with display panels as display ports have been increasingly integrated into people's daily life, and have advantages such as small size, low power consumption, no radiation, and low manufacturing cost.

[0003] SUMMARY

[0004] At least one embodiment of the present disclosure provides a display device, including a display substrate and a source driver. The display substrate includes a plurality of rows and columns of sub-pixels arranged in an array, a plurality of gate scanning signal lines, and M data signal lines. The plurality of rows and columns of sub-pixels includes an i-th row of sub-pixels, and a plurality of initial data corresponding to the i-th row of sub-pixels is divided into a first group of initial data and a second group of initial data. The first group of initial data includes N initial data, and the second group of initial data includes S initial data. The source driver includes a first cache module, a second cache module, a third cache module, an operation conversion module, and an output module. The first cache module includes M first cache units for caching the N initial data or the S initial data, and each initial data corresponds to one data signal line. The second cache module includes at least M second cache units. The third cache module includes a plurality of third cache units. The operation conversion module is configured to receive the N initial data, output M data to the second cache module based on the N initial data according to a control signal, and obtain T interpolation data based on part of the N initial data and output the T interpolation data to the third cache module. The output module is configured to output the M data of the second cache module to the M data signal lines, respectively. The operation conversion module is further configured to receive the S initial data, output (M-T) data to the second cache module based on the S initial data according to a control signal. The output module is further configured to output the (M-T) data of the second cache module and the T interpolation data of the third cache module to the M data signal lines, respectively. M is a positive integer greater than 2, N and S are positive integers less than M, and T is a positive integer less than N.

[0005] For example, in the display device provided in at least one of the examples of the embodiments of the present disclosure, the N initial data are stored in the M first buffer units in intervals. The operation conversion module is further configured to: send the N initial data to corresponding N second buffer units according to the control signal; calculate (M-N) first interpolation data based on Q initial data in the N initial data and send the (M-N) first interpolation data to (M-N) second buffer units other than the N second buffer units; and calculate T second interpolation data based on P initial data in the N initial data and output the T second interpolation data to T third buffer units.

[0006] For example, in the display device provided in at least one of the examples of the embodiments of the present disclosure, the S initial data are stored in the M first buffer units in intervals. The operation conversion module is further configured to: send the S initial data to corresponding S second buffer units according to the control signal; calculate (M-T-S) third interpolation data based on the S initial data and send the (M-T-S) third interpolation data to (M-T-S) second buffer units respectively. The output module is further configured to: output the T interpolation data of the third buffer module, the S initial data in the second buffer module and the (M-T-S) third interpolation data to the M data signal lines respectively.

[0007] For example, in the display device provided in at least one of the examples of the embodiments of the present disclosure, each row of the plurality of rows of sub-pixels includes a plurality of colors of sub-pixels, and the plurality of colors of sub-pixels are arranged in cycles; each two of the plurality of gate scan signal lines are connected to a row of sub-pixels, and each of the M data signal lines is connected to two columns of sub-pixels; and two sub-pixels connected to the same data signal line and connected to adjacent two of the plurality of gate scan signal lines are different colors of sub-pixels.

[0008] For example, in the display device provided in at least one of the examples of the embodiments of the present disclosure, the plurality of colors of sub-pixels include a first color of sub-pixel, a second color of sub-pixel and a third color of sub-pixel; the first group of initial data includes initial data corresponding to the first color of sub-pixel and initial data corresponding to the second color of sub-pixel; and the second group of initial data includes initial data corresponding to the third color of sub-pixel.

[0009] For example, in the display device provided by at least one of the embodiments of the present disclosure, the operation conversion module comprises M first switching switches, K second switching switches and K operation units; the inputs of the M first switching switches are respectively connected with the outputs of the M first buffer units, the output of each first switching switch is connected with a second buffer unit and at least one operation unit, each first switching switch is configured to close the output of the connected first buffer unit according to a control signal, or output data of the first buffer unit to the connected second buffer unit, or output data of the first buffer unit to the connected operation unit; the inputs of each operation unit are connected with the outputs of at least two first switching switches, the outputs of the K operation units are respectively connected with the inputs of the K second switching switches; each of the first part of the second switching switches is connected with two second buffer units, each of the second part of the second switching switches is connected with two second buffer units and one third buffer unit, each of the third part of the second switching switches is connected with one third buffer unit, each second switching switch is configured to close the output of the connected operation unit according to a control signal, or output data of the operation unit to one of the connected two second buffer units, or output data of the operation unit to the connected third buffer unit; wherein K is a positive integer less than M.

[0010] For example, in the display device provided by at least one of the embodiments of the present disclosure, each two initial data in the N initial data are stored as a sub-group in two adjacent first buffer units, and each two sub-groups are separated by one first buffer unit; each two adjacent initial data in the S initial data are separated by two first buffer units; the jth operation unit in the K operation units is connected with the jth first switching switch and the j+3th first switching switch; the jth second switching switch connected with the jth operation unit is connected with the (j+1)th second buffer unit, the (j+2)th second buffer unit and one third buffer unit; wherein j is a positive integer less than or equal to K.

[0011] For example, in the display device provided by at least one of the embodiments of the present disclosure, the source driver further comprises a controller configured to: in the process of processing the first group of initial data, control the operation conversion module to output two initial data in each of the subgroups to a corresponding two second cache units; control the operation conversion module to calculate a first interpolation data based on the first data in each two adjacent subgroups to obtain the (M-N) first interpolation data, and output the (M-N) interpolation data to the (M-N) second cache units; control the operation conversion module to calculate a second interpolation data based on the second data in each two adjacent subgroups to obtain the T second interpolation data, and output the T second interpolation data to the T third cache units; and control the output module to output the M data of the second cache module.

[0012] For example, in the display device provided by at least one of the embodiments of the present disclosure, the controller is further configured to: in the process of processing the second group of initial data, control the operation conversion module to output the S initial data in the first cache module to a corresponding S second cache units respectively; control the operation conversion module to calculate a third interpolation data based on each two adjacent initial data in the first cache module, and output each of the third interpolation data to a second cache unit; and control the output module to output the (M-T) data of the second cache units and the T second interpolation data of the third cache units to the M data signal lines respectively.

[0013] For example, in the display device provided by at least one of the embodiments of the present disclosure, the plurality of rows and columns of subpixels further comprise an i+rth row of subpixels, a first subpixel and a second subpixel of the ith row of subpixels are connected to a first data signal line, and a first subpixel and a second subpixel of the i+rth row of subpixels are connected to a second data signal line. The source driver is configured to: in the process of processing the initial data corresponding to the ith row of subpixels, cache the N initial data from the first of the M first cache units; and in the process of processing the initial data corresponding to the i+rth row of subpixels, cache the N initial data from the second of the M first cache units; wherein r is a positive integer.

[0014] For example, in the display device provided by at least one of the embodiments of the present disclosure, the output module comprises a digital-to-analog converter and an amplifier, the digital-to-analog converter is configured to convert the signals corresponding to the M data into analog driving signals, and the amplifier is configured to amplify the analog driving signals and output them to the M data signal lines.

[0015] The electronic device includes the display device according to any one of the display devices in the present disclosure.

[0016] The display device includes a display substrate and a source driver, the display substrate includes a plurality of rows and columns of sub-pixels arranged in an array, a plurality of gate scanning signal lines, and M data signal lines, the plurality of rows and columns of sub-pixels include an i-th row of sub-pixels, a plurality of initial data corresponding to the i-th row of sub-pixels are divided into a first group of initial data and a second group of initial data, the first group of initial data includes N initial data, and the second group of initial data includes S initial data. The method includes: controlling the source driver to receive the N initial data and cache the N initial data to M first cache units of the source driver, wherein each initial data corresponds to one data signal line; controlling the source driver to output M data to a second cache module based on the N initial data, obtain T interpolation data based on part of the N initial data, and output the T interpolation data to a third cache module of the source driver; outputting the M data cached by the second cache module to the M data signal lines; controlling the source driver to receive the S initial data and output (M-T) data to the second cache module based on the S initial data; and outputting the (M-T) data of the second cache module and the T interpolation data of the third cache module to the M data signal lines, respectively.

[0017] The electronic device includes a processor, a memory storing one or more computer program modules, and the one or more computer program modules are configured to be executed by the processor to implement the control method provided in any one of the embodiments of the present disclosure.

[0018] The computer readable storage medium stores non-transitory computer readable instructions, and when the non-transitory computer readable instructions are executed by a computer, the control method provided in any one of the embodiments of the present disclosure can be implemented. BRIEF DESCRIPTION OF DRAWINGS

[0019] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly introduced below. Obviously, the drawings in the following description only relate to some of the embodiments of the present disclosure, but not limit the present disclosure.

[0020] FIG. 1 shows a schematic diagram of a display system;

[0021] FIG. 2 shows a schematic diagram of a dual gate pixel architecture;

[0022] FIG. 3 shows a schematic diagram of another dual gate pixel architecture;

[0023] FIG. 4 shows a schematic diagram of yet another dual gate pixel architecture;

[0024] FIG. 5 shows a schematic diagram of pixel data;

[0025] FIG. 6 shows a schematic diagram of a source driver;

[0026] FIG. 7A shows a schematic diagram of data corresponding to a first row of sub-pixels of the pixel architecture shown in FIG. 2 being transmitted in a source driver;

[0027] FIG. 7B shows a schematic diagram of data corresponding to a second row of sub-pixels of the pixel architecture shown in FIG. 2 being transmitted in a source driver;

[0028] FIG. 7C shows a schematic diagram of data corresponding to a third row of sub-pixels of the pixel architecture shown in FIG. 2 being transmitted in a source driver;

[0029] FIG. 7D shows a schematic diagram of data corresponding to a fourth row of sub-pixels of the pixel architecture shown in FIG. 2 being transmitted in a source driver;

[0030] FIG. 8 shows a schematic diagram of data corresponding to a first row of sub-pixels of the pixel architecture shown in FIG. 3 being transmitted in a source driver;

[0031] FIG. 9A shows a schematic diagram of data corresponding to a first row of sub-pixels of the pixel architecture shown in FIG. 4 being transmitted in a source driver;

[0032] FIG. 9B shows a schematic diagram of data corresponding to a second row of sub-pixels of the pixel architecture shown in FIG. 4 being transmitted in a source driver;

[0033] FIG. 10 shows a schematic diagram of a display device according to at least one embodiment of the present disclosure;

[0034] FIG. 11A shows a schematic diagram of data corresponding to a first row of sub-pixels of the pixel architecture shown in FIG. 2 being transmitted in a source driver according to at least one embodiment of the present disclosure;

[0035] FIG. 11B shows a schematic diagram of data corresponding to a second row of sub-pixels of the pixel architecture shown in FIG. 2 being transmitted in a source driver according to at least one embodiment of the present disclosure;

[0036] FIG. 11C shows a schematic diagram of data corresponding to a third row of sub-pixels of the pixel architecture shown in FIG. 2 being transmitted in a source driver according to at least one embodiment of the present disclosure;

[0037] FIG. 11D shows a schematic diagram of data corresponding to a fourth row of sub-pixels of the pixel architecture shown in FIG. 2 being transmitted in a source driver according to at least one embodiment of the present disclosure;

[0038] FIG. 12 shows a schematic diagram of an operation conversion module according to an embodiment of the present disclosure;

[0039] FIG. 13 shows a schematic diagram of the first row of data corresponding to the pixel architecture shown in FIG. 3 being transmitted in a source driver according to an embodiment of the present disclosure;

[0040] FIG. 14 shows a schematic diagram of the operation conversion module processing the first row of data corresponding to the pixel architecture shown in FIG. 3 according to an embodiment of the present disclosure;

[0041] FIG. 15A shows a schematic diagram of the first row of data corresponding to the pixel architecture shown in FIG. 4 being transmitted in a source driver according to an embodiment of the present disclosure;

[0042] FIG. 15B shows a schematic diagram of the second row of data corresponding to the pixel architecture shown in FIG. 4 being transmitted in a source driver according to an embodiment of the present disclosure;

[0043] FIG. 16 shows a schematic diagram of the operation conversion module processing the first row of data and the second row of data corresponding to the pixel architecture shown in FIG. 4 according to an embodiment of the present disclosure;

[0044] FIG. 17 shows a flowchart of a control method for a display device according to an embodiment of the present disclosure;

[0045] FIG. 18 shows a schematic block diagram of an electronic device according to an embodiment of the present disclosure;

[0046] FIG. 19 shows a schematic block diagram of another electronic device according to an embodiment of the present disclosure; and

[0047] FIG. 20 shows a schematic diagram of a computer-readable storage medium according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0048] In order to make the objects, technical solutions, and advantages of the embodiments of the present disclosure clearer, the technical solutions of the embodiments of the present disclosure will be described clearly and completely below with reference to the drawings of the embodiments of the present disclosure. Obviously, the described embodiments are some but not all of the embodiments of the present disclosure. Based on the described embodiments of the present disclosure, all other embodiments obtained by a person of ordinary skill in the art without creative effort belong to the scope of protection of the present disclosure.

[0049] Unless otherwise defined, technical terms or scientific terms used in the present disclosure shall have the meanings as understood by a person of ordinary skill in the art to which the present disclosure pertains. The terms "first", "second", and similar terms used in the present disclosure do not denote any order, quantity, or importance, but are used to distinguish different components. Similarly, the terms "one", "a", or "the" do not denote a quantity of any number, but mean the existence of at least one. The terms "include", "comprise", and similar terms mean that the elements or objects before the terms encompass the elements or objects listed after the terms and equivalents thereof, and do not exclude other elements or objects. The terms "connect" or "connected" or similar terms do not mean only physical or mechanical connections, but can include electrical connections, whether direct or indirect. The terms "upper", "lower", "left", "right", and the like are used only to indicate relative positional relationships, and when the absolute positions of the described objects are changed, the relative positional relationships can also be changed accordingly.

[0050] FIG. 1 shows a schematic diagram of a display system.

[0051] As shown in FIG. 1, the display system generally includes a display panel 110, a timing controller 120, a gate driver 130, and a source driver 140.

[0052] The display panel 110 generally includes gate scan signal lines (G1-G2n), data signal lines (D1-D2m), and pixels. The gate scan signal lines are used to transmit driving signals for turning on pixel switching devices, which are row signals. The data signal lines transmit data signals for adjusting the display gray scale of the pixels, which are column signals. The pixels are the smallest complete display units of the display panel, and each pixel generally includes a plurality of sub-pixels Pxij, which are generally arranged along the direction of the gate scan signal lines. The physical resolution of the display panel 110 is 2m*2n, which means that there are 2m pixels in each row, referred to as horizontal resolution, and 2n pixels in each column, referred to as vertical resolution. Each pixel includes a plurality of sub-pixels, such as red sub-pixels, green sub-pixels, and blue sub-pixels.

[0053] The timing controller 120 is a board that implements a timing conversion function, transmits a clock signal to the gate driver 130, and transmits received display signal data to a source driver chip. The pixel data received and transmitted are one-to-one corresponding, which is commonly referred to as Point to Point (P to P).

[0054] The gate driver 130 is used to generate gate driving signals according to the clock signal and transmit the gate driving signals to a plurality of rows of sub-pixels in time through the gate scan signal lines. For example, the gate driving signals can be transmitted to the plurality of rows of sub-pixels row by row, so that the plurality of rows of sub-pixels are turned on row by row.

[0055] The source driver 140 is responsible for converting the received digital data signal into an analog data signal capable of driving the display of multiple columns of sub-pixels, and its output channels correspond one-to-one to the data signal lines of the display panel.

[0056] In order to reduce the cost and the number of source drivers used, the display panel can adopt a dual gate pixel architecture, the main feature of which is that the number of gate scanning signal lines is doubled and the number of data signal lines is halved, that is, for a row of pixels, two gate scanning signal lines are needed to drive in time, and the data signal line needs to send data signal twice.

[0057] Figure 2 shows a schematic diagram of a dual gate pixel architecture.

[0058] As shown in Figure 2, each row of sub-pixels is connected to two gate scanning signal lines, and each data signal line is connected to two columns of sub-pixels. The sub-pixels are connected to the data signal lines by short connections and long connections (sub-pixels connected to adjacent data signal lines are short connections, and sub-pixels connected to non-adjacent data signal lines are long connections). Two sub-pixels located between adjacent two data signal lines and between adjacent two gate scanning signal lines are connected to the same data signal line, for example, two sub-pixels located between data signal lines D1 and D2 and between gate scanning signal lines G1 and G2 are connected to data signal line G1. The two sub-pixels located between adjacent two data signal lines and between adjacent two gate scanning signal lines are connected to different gate scanning signal lines. The connection rule of the data signal line and the sub-pixel in the horizontal direction is long on the top and short on the bottom, short on the top and long on the bottom, short on the top and long on the bottom, and so on. Alternatively, the connection rule is short on the top and long on the bottom, long on the top and short on the bottom, long on the top and short on the bottom, and so on. The connection mode of the data signal line and the sub-pixel in the vertical direction has a period of two rows of jumps, for example, the first and second rows of sub-pixels and the third and fourth rows of sub-pixels are located on the same side of the data signal line, for example, the first and second rows of sub-pixels are connected from the first data signal line D1, and the third and fourth rows of sub-pixels are connected from the second data signal line D2.

[0059] Figure 3 shows a schematic diagram of another dual gate pixel architecture.

[0060] As shown in Figure 3, each row of sub-pixels is connected to two gate scanning signal lines, and each data signal line is connected to two columns of sub-pixels. The sub-pixels are connected to the data signal lines by short connections, and the two sub-pixel units between adjacent two data signal lines and adjacent two gate scanning signal lines are connected to two data signal lines, but can be connected to one gate scanning signal line or different gate scanning signal lines. The horizontal direction rule is up and down, up and up, and down and down, and the vertical direction rule is the same.

[0061] Figure 4 shows a schematic diagram of a further dual gate pixel architecture.

[0062] As shown in Figure 4, the pixel architecture features similar to the pixel architecture shown in Figure 2, with the difference that the connection rule of the data signal lines and the sub-pixels in the horizontal direction is long on top, short on bottom, long on top, short on bottom, short on top, long on bottom, and so on. Alternatively, the connection rule of the data signal lines and the sub-pixels in the horizontal direction is short on top, long on bottom, short on top, long on bottom, long on top, short on bottom, and so on. The data signal lines and the sub-pixels in the vertical direction are one jump per row, for example, the first and second rows of sub-pixels connected to the same data line are located on the two sides of the data signal line, for example, the first row of sub-pixels is connected from the second data signal line D2, and the second row of sub-pixels is connected from the first data signal line D1.

[0063] In Figures 2 to 4, the boxes of different gray levels represent sub-pixels of different colors, for example, the white boxes represent red sub-pixels, the gray boxes represent green sub-pixels, and the black boxes represent blue sub-pixels.

[0064] For the three architectures above, for the same column of data signal lines, the sub-pixels connected by adjacent two rows of gate scanning signal lines are not sub-pixels of the same color.

[0065] Another feature of the three architectures is that, according to the scanning direction of the gate driving signal from top to bottom and the data driving signal from left to right, i.e. taking the top left corner of the diagram as the starting point, each group of three horizontally adjacent sub-pixels of the same color is formed, wherein the three sub-pixels of one group are all hung on the upper gate scanning signal line, the three sub-pixels of another group are all hung on the lower gate scanning signal line, and the first and third sub-pixels of another group are both hung on the upper gate scanning signal line and the second sub-pixel is hung on the lower gate scanning signal line, i.e. in the upper upper upper, lower lower lower, upper lower upper structure. Taking the structure shown in Figure 2 as an example, for the first row, starting from the leftmost side, the three adjacent red sub-pixels (represented by white boxes) are all connected to the lower gate scanning signal line (i.e. G2), the three adjacent green sub-pixels (represented by gray boxes) are all connected to the upper gate scanning signal line (i.e. G1), and the first and third of the three adjacent blue sub-pixels (represented by black boxes) are connected to the upper gate scanning signal line (i.e. G1) and the second is connected to the lower gate scanning signal line (i.e. G2).

[0066] Figure 5 shows a schematic diagram of pixel data.

[0067] As shown in Figures 2 and 5, for the dual gate architecture shown in Figure 2:

[0068] R1-1 corresponds to sub-pixel G2D1 (sub-pixel G2D1 means a sub-pixel connected with gate scanning signal line G2 and data signal line D1, the same below), that is, R1-1 is the data of sub-pixel G2D1. G1-1 corresponds to sub-pixel G1D1, B1-1 corresponds to sub-pixel G1D2, R1-2 corresponds to sub-pixel G2D2, G1-2 corresponds to sub-pixel G1D3, and B1-2 corresponds to sub-pixel G2D3;

[0069] R2-1 corresponds to sub-pixel G4D1, G2-1 corresponds to sub-pixel G3D1, B2-1 corresponds to sub-pixel G3D2, R2-2 corresponds to sub-pixel G4D2, G2-2 corresponds to sub-pixel G3D3, and B2-2 corresponds to sub-pixel G4D3;

[0070] R3-1 corresponds to sub-pixel G6D2, G3-1 corresponds to sub-pixel G5D2, B3-1 corresponds to sub-pixel G5D3, R3-2 corresponds to sub-pixel G6D3, G3-2 corresponds to sub-pixel G5D4, and B3-2 corresponds to sub-pixel G6D4;

[0071] R4-1 corresponds to sub-pixel G8D2, G4-1 corresponds to sub-pixel G7D2, B4-1 corresponds to sub-pixel G7D3, R4-2 corresponds to sub-pixel G8D3, G4-2 corresponds to sub-pixel G7D4, and B4-2 corresponds to sub-pixel G8D4;

[0072] 4 rows per period, and so on.

[0073] As shown in FIG. 3 and FIG. 5, for the dual gate architecture shown in FIG. 3:

[0074] R1-1 corresponds to sub-pixel G1D1, G1-1 corresponds to sub-pixel G2D2, B1-1 corresponds to sub-pixel G1D2, R1-2 corresponds to sub-pixel G1D3, G1-2 corresponds to sub-pixel G2D3, and B1-2 corresponds to sub-pixel G2D4;

[0075] R2-1 corresponds to sub-pixel G3D1, G2-1 corresponds to sub-pixel G4D2, B2-1 corresponds to sub-pixel G3D2, R2-2 corresponds to sub-pixel G3D3, G2-2 corresponds to sub-pixel G4D3, and B2-2 corresponds to sub-pixel G4D4; and so on.

[0076] As shown in FIG. 4 and FIG. 5, for the dual gate architecture shown in FIG. 4:

[0077] R1-1 corresponds to sub-pixel G1D2, G1-1 corresponds to sub-pixel G2D2, B1-1 corresponds to sub-pixel G1D3, R1-2 corresponds to sub-pixel G2D3, G1-2 corresponds to sub-pixel G2D4, and B1-2 corresponds to sub-pixel G1D4;

[0078] R2-1 corresponds to sub-pixel G3D1, G2-1 corresponds to sub-pixel G4D1, B2-1 corresponds to sub-pixel G3D2, R2-2 corresponds to sub-pixel G4D2, G2-2 corresponds to sub-pixel G4D3, and B2-2 corresponds to sub-pixel G3D3;

[0079] Two rows per period, and so on.

[0080] FIG. 6 shows a schematic diagram of a source driver.

[0081] As shown in FIG. 6, the source driver 200 includes a serial-to-parallel conversion module 210, a first buffer module 220, a second buffer module 230, a digital-to-analog converter 240, and an amplifier 250.

[0082] The serial-to-parallel conversion module 210 receives the serial digital data driving signals sent by the front end, i.e., receives the digital data driving signals of each sub-pixel in sequence, converts the digital data driving signals into parallel digital data driving signals, and stores the parallel digital data driving signals to the first buffer module 220. Then the first buffer module 220 sends the digital data driving signals to the second buffer module 230, the second buffer module 230 is connected to the digital-to-analog converter 240, the digital data driving signals are converted into analog data driving signals by the digital-to-analog converter 240, and the analog data driving signals are sent to the display panel via the amplifier 250. After the digital data driving signals are sent to the second buffer module 230, the serial-to-parallel conversion module 210 starts to receive the data of the next row, i.e., the second buffer module 230 stores the data of the current display row, and the first buffer module 220 stores the data of the next row to be displayed, so two buffers are needed.

[0083] In the dual gate pixel architecture, each row of sub-pixels is driven by two gate driving signals in time division, and the data signals corresponding to each row of sub-pixels are also sent twice. For example, the first row of sub-pixels is connected to the first gate scanning signal line and the second gate scanning signal line, during the period when the first gate scanning signal line outputs the gate driving signal, the plurality of sub-pixels in the first row connected to the first gate scanning signal line are turned on, and during this period, display data can be output to these sub-pixels through a plurality of data signal lines. During the period when the second gate scanning signal line outputs the gate driving signal, the plurality of sub-pixels in the first row connected to the second gate scanning signal line are turned on, and during this period, display data can be output to these sub-pixels through a plurality of data signal lines.

[0084] Fig. 7A shows a schematic diagram of data corresponding to the first row of sub-pixels of the pixel architecture shown in Fig. 2 being transmitted in the source driver. Fig. 7B shows a schematic diagram of data corresponding to the second row of sub-pixels of the pixel architecture shown in Fig. 2 being transmitted in the source driver. Fig. 7C shows a schematic diagram of data corresponding to the third row of sub-pixels of the pixel architecture shown in Fig. 2 being transmitted in the source driver. Fig. 7D shows a schematic diagram of data corresponding to the fourth row of sub-pixels of the pixel architecture shown in Fig. 2 being transmitted in the source driver.

[0085] As shown in Figs. 7A-7D, L1 / L2 represent the first and second cache modules, respectively, and G1-G8 represent the first-eighth row gate scan signal lines, respectively.

[0086] Channels 1-9 in L1 / L2 / G1 correspond to sub-pixels G1D1-G1D9 in Fig. 2, i.e., G1-1 / B1-1 / G1-2 / G1-3 / B1-3 / G1-4 / G1-5 / B1-5 / G1-6, respectively.

[0087] Channels 1-9 in L1 / L2 / G2 correspond to sub-pixels G2D1-G2D9 in Fig. 2, i.e., R1-1 / R1-2 / B1-2 / R1-3 / R1-4 / B1-4 / R1-5 / R1-6 / B1-6, respectively.

[0088] Channels 1-9 in L1 / L2 / G3 correspond to sub-pixels G3D1-G3D9 in Fig. 2, i.e., G2-1 / B2-1 / G2-2 / G2-3 / B2-3 / G2-4 / G2-5 / B2-5 / G2-6, respectively.

[0089] Channels 1-9 in L1 / L2 / G4 correspond to sub-pixels G4D1-G4D9 in Fig. 2, i.e., R2-1 / R2-2 / B2-2 / R2-3 / R2-4 / B2-4 / R2-5 / R2-6 / B2-6, respectively.

[0090] Channels 1-9 in L1 / L2 / G5 correspond to sub-pixels G5D1-G5D9 in Fig. 2, i.e., G5D2-G5D9 correspond to G3-1 / B3-1 / G3-2 / G3-3 / B3-3 / G3-4 / G3-5 / B3-5, but G5D1 has no corresponding pixel unit, i.e., the data sent from the front end is invalid.

[0091] Channels 1-9 in L1 / L2 / G6 correspond to sub-pixels G6D1-G6D9 in Fig. 2, i.e., G6D2-G6D9 correspond to R3-1 / R3-2 / B3-2 / R3-3 / R3-4 / B3-4 / R3-5 / R3-6, but G6D1 has no corresponding pixel unit, i.e., the data sent from the front end is invalid.

[0092] The channels 1-9 in L1 / L2 / G7 correspond to the sub-pixels G7D1-G7D9 in FIG. 2 respectively, wherein G7D2-G6D9 correspond to G4-1 / B4-1 / G4-2 / G4-3 / B4-3 / G4-4 / G4-5 / B4-5, but G7D1 has no corresponding pixel unit, i.e. the data sent from the front end is invalid;

[0093] The channels 1-9 in L1 / L2 / G8 correspond to the sub-pixels G8D1-G8D9 in FIG. 2 respectively, wherein G7D2-G6D9 correspond to R4-1 / R4-2 / B4-2 / R4-3 / R4-4 / B4-4 / R4-5 / R4-6, but G8D1 has no corresponding pixel unit, i.e. the data sent from the front end is invalid;

[0094] It should be noted that the amount of data sent per row is usually the same, so a virtual data is compensated for the sub-pixels G5D1 / G6D1 / G7D1 / G8D1;

[0095] By analogy.

[0096] FIG. 8 shows a schematic diagram of the data corresponding to the first row of sub-pixels of the pixel architecture shown in FIG. 3 being transmitted in the source driver.

[0097] As shown in FIG. 8, the channels 1-9 in L1 / L2 / G1 correspond to the sub-pixels G1D1-G1D9 in FIG. 3 respectively, i.e. R1-1 / B1-1 / R1-2 / R1-3 / B1-3 / R1-4 / R1-5 / B1-5 / R1-6;

[0098] The channels 1-9 in L1 / L2 / G2 correspond to the sub-pixels G2D1-G2D9 in FIG. 3 respectively, i.e. G1-1 / G1-2 / B1-2 / G1-3 / G1-4 / B1-4 / G1-5 / G1-6 / B1-6;

[0099] By analogy.

[0100] FIG. 9A shows a schematic diagram of the data corresponding to the first row of sub-pixels of the pixel architecture shown in FIG. 4 being transmitted in the source driver. FIG. 9B shows a schematic diagram of the data corresponding to the second row of sub-pixels of the pixel architecture shown in FIG. 4 being transmitted in the source driver.

[0101] As shown in FIGS. 9A and 9B, the channels 1-9 in L1 / L2 / G1 correspond to the sub-pixels G1D1-G1D9 in FIG. 4 respectively, i.e. - / R1-1 / B1-1 / B1-2 / R1-3 / B1-3 / B1-4 / R1-5 / B1-5;

[0102] Channels 1-9 in L1 / L2 / G1 correspond to sub-pixels G1D1-G1D9 in FIG. 4, i.e., / G1-1 / R1-2 / G1-2 / G1-3 / R1-4 / G1-4 / G1-5 / R1-6;

[0103] Channels 1-9 in L1 / L2 / G3 correspond to sub-pixels G3D1-G3D9 in FIG. 4, i.e., R2-1 / B2-1 / B2-2 / R2-3 / B2-3 / B2-4 / R2-5 / B2-5 / B2-6;

[0104] Channels 1-9 in L1 / L2 / G4 correspond to sub-pixels G4D1-G4D9 in FIG. 4, i.e., G2-1 / R2-2 / G2-2 / G2-3 / R2-4 / G2-4 / G2-5 / R2-6 / G2-6;

[0105] By analogy.

[0106] The resolution of the display signal needs to match the physical resolution of the display panel, i.e., the data corresponds to the physical sub-pixel one by one. When the resolution of the display signal does not match the physical resolution of the display panel, such as the horizontal resolution of the display signal is only half of the resolution of the display panel, the display panel cannot display. In the case where the resolution of the display signal is less than the physical resolution of the display panel, the display signal can be expanded, for example, the expansion can be performed in the horizontal direction, so that the horizontal resolution of the expanded display signal is consistent with the horizontal resolution of the display panel.

[0107] The dual gate pixel architecture is not suitable for HSR super-division frequency doubling technology, and the existing horizontal resolution expansion scheme cannot realize the horizontal resolution expansion of the dual gate pixel architecture. Therefore, how to realize the horizontal resolution expansion function of the dual gate pixel architecture is a problem to be solved.

[0108] The display substrate includes a plurality of rows and columns of sub-pixels arranged in an array, a plurality of gate scanning signal lines, and M data signal lines, wherein the plurality of rows and columns of sub-pixels include an ith row of sub-pixels, a plurality of initial data corresponding to the ith row of sub-pixels are divided into a first group of initial data and a second group of initial data, the first group of initial data includes N initial data, and the second group of initial data includes S initial data. The source driver includes a first cache module, a second cache module, a third cache module, an operation conversion module, and an output module. The first cache module includes M first cache units for caching the N initial data or the S initial data, each of the initial data corresponding to one of the data signal lines. The second cache module includes at least M second cache units. The third cache module includes a plurality of third cache units. The operation conversion module is configured to receive the N initial data, output M data to the second cache module based on the N initial data according to a control signal, obtain T interpolation data based on part of the N initial data and output the T interpolation data to the third cache module according to the control signal, and output the M data of the second cache module to the M data signal lines respectively. The output module is configured to output the (M-T) data of the second cache module and the T interpolation data of the third cache module to the M data signal lines respectively. M is a positive integer greater than 2, N and S are positive integers less than M, and T is a positive integer less than N.

[0109] According to the display device, by controlling the position of data stored in each level of cache, the method of operation, and the time of output, the horizontal resolution of the Dual gate pixel architecture display panel is expanded.

[0110] FIG. 10 shows a schematic diagram of a display device provided by at least one embodiment of the present disclosure.

[0111] As shown in FIG. 10, the display device 300 includes a display substrate 310 and a source driver 320.

[0112] The display substrate 310 includes a plurality of rows and columns of sub-pixels arranged in an array, a plurality of gate scanning signal lines, and M data signal lines, wherein the plurality of rows and columns of sub-pixels include an ith row of sub-pixels, a plurality of initial data corresponding to the ith row of sub-pixels are divided into a first group of initial data and a second group of initial data, the first group of initial data includes N initial data, and the second group of initial data includes S initial data.

[0113] The source driver 320 includes a first buffer module 322, a second buffer module 324, a third buffer module 325, an operation conversion module 323, and an output module. The first buffer module 322 includes M first buffer units for buffering N initial data or S initial data, each initial data corresponding to a data signal line. The second buffer module 324 includes at least M second buffer units, and the third buffer module 325 includes a plurality of third buffer units.

[0114] The operation conversion module 323 is configured to receive the N initial data, output M data to the second buffer module based on the N initial data according to a control signal, and obtain T interpolation data based on part of the N initial data and output the T interpolation data to the third buffer module. The output module is configured to output the M data of the second buffer module to M data signal lines respectively.

[0115] The operation conversion module is further configured to receive the S initial data, output (M-T) data to the second buffer module based on the S initial data according to a control signal. The output module is further configured to output the (M-T) data of the second buffer module and the T interpolation data of the third buffer module to the M data signal lines respectively.

[0116] For example, M is a positive integer greater than 2, N and S are both positive integers less than M, and T is a positive integer less than N.

[0117] For example, the M first buffer units in the first buffer module 322 correspond to M channels of the source driver respectively, and similarly, the M second buffer units in the second buffer module 324 correspond to the M channels respectively. The third buffer module 325 can include M third buffer units corresponding to the M channels one by one respectively. The M channels of the source driver are respectively used to output data signals to M data signal lines.

[0118] For example, the display substrate 310 can adopt a dual gate pixel architecture. As shown in FIGS. 2 to 4, for example, each row of a plurality of rows of a plurality of columns of sub-pixels includes sub-pixels of a plurality of colors, and the sub-pixels of the plurality of colors are arranged in cycles. Each two of a plurality of gate scan signal lines are connected to a row of sub-pixels, and each of a plurality of data signal lines is connected to two columns of sub-pixels. Two sub-pixels connected to the same data signal line and connected to adjacent two gate scan signal lines respectively are sub-pixels of different colors.

[0119] For example, the display device 300 can further include a gate driver 330 for sequentially shifting and outputting gate scan signals to a plurality of gate scan signal lines. In addition, the display device 300 can further include other devices such as a timing controller. The source driver 320 can further include other modules such as a serial-to-parallel conversion module 321.

[0120] For example, the output module includes a digital-to-analog converter 326 and an amplifier 327, the digital-to-analog converter 325 is configured to convert the signals corresponding to the M data into analog driving signals, and the amplifier 327 is configured to amplify the analog driving signals and output the amplified analog driving signals to the M data signal lines.

[0121] For example, when the first cache module caches the first group of initial data, the N initial data included in the first group of initial data can be stored in the M first cache units at intervals (i.e., not sequentially adjacent). When the first cache module caches the second group of initial data, the S initial data included in the second group of initial data can be stored in the M first cache units at intervals. Each first cache unit can be used to cache one initial data, each cache unit corresponds to one channel, and each channel corresponds to one data signal line. Therefore, each initial data can correspond to one data signal line, and one initial data can be used to output to one sub-pixel.

[0122] For example, unlike the source driver 200 shown in FIG. 6, the source driver 320 of the embodiment of the present disclosure adds an operation conversion module 323 after the first cache module 322 and adds a third cache module 325. The third cache module 325 is parallel to the second cache module 324, and the third cache module 325 is used to store the results output by the operation conversion module 323 and send data to the digital-to-analog converter 326. The operation conversion module 323 can include a plurality of operation units, each operation unit can perform a copy operation or an average operation (or other calculation method operation, which is described below as an average operation). The operation conversion module 323 can send at least part of the data stored in the first cache module 322 to the second cache module 324, or send the operation results of the operation units to the second cache module or the third cache module. The operation conversion module can receive an operation control signal, and the operation control signal is used to control whether the data of the first cache module 322 is output, output to the second cache module 324, or output to the operation unit. The operation conversion module can also receive an output control signal, and the output control signal is used to control whether the operation results of the operation conversion module are output to the second cache module 324 or the third cache module 325, and control the connection between the second cache module 324 and the third cache module 325 and the digital-to-analog converter 326 to be turned on or turned off.

[0123] For example, the initial data corresponding to each row of sub-pixels can be divided into a first group of initial data and a second group of initial data. For example, the sub-pixels of multiple colors in the display substrate can include first sub-pixels, second sub-pixels, and third sub-pixels, the first group of initial data includes initial data corresponding to the first sub-pixels and initial data corresponding to the second sub-pixels, and the second group of initial data includes initial data corresponding to the third sub-pixels.

[0124] For example, there is no repeated data between the first set of initial data and the second set of initial data. For example, in some embodiments, the first color of sub-pixel can be a green sub-pixel, the second color of sub-pixel can be a blue sub-pixel, and the third color of sub-pixel can be a red sub-pixel. In other embodiments, the first set of initial data can include red sub-pixels and green sub-pixels, and the second set of initial data can include blue sub-pixels, or the first set of initial data includes red sub-pixels and blue sub-pixels, and the second set of initial data can include green sub-pixels. The colors of the sub-pixels corresponding to the first set of initial data and the second set of initial data can be determined according to requirements. In other embodiments, the display substrate can also include sub-pixels of other colors, such as white sub-pixels.

[0125] For example, for the first set of initial data and the second set of initial data corresponding to each row of sub-pixels, the source driver can be configured to process the first set of initial data in a first time period and process the second set of initial data in a second time period, the first time period being earlier than the second time period.

[0126] For example, for the first row of sub-pixels, the first row of sub-pixels can be divided into a first part of sub-pixels connected to the first gate scan signal line and a second part of sub-pixels connected to the second gate scan signal line.

[0127] For example, the source driver can first process the first set of initial data corresponding to the first row of sub-pixels. When processing the first set of initial data (N initial data), the first set of initial data can be stored in M first cache units at intervals. The operation conversion module can transmit at least part of the data in the first cache module to the corresponding second cache unit, and can perform interpolation operation on at least part of the data in the first cache module to obtain a plurality of interpolation data. The operation conversion module transmits part of the interpolation data to the second cache unit, so that the second cache unit caches M data, part of which is initial data transmitted from the first cache unit, and another part is interpolation data obtained by processing, and then outputs the M data in the M second cache units to the first part of sub-pixels, realizing the expansion from N data to M data. The operation conversion module can transmit another part of the interpolation data to the third cache module, and leave this part of the first interpolation data for output when processing the second set of initial data.

[0128] For example, when the source driver processes the second group of initial data (S initial data) corresponding to the first row of sub-pixels, the second group of initial data can be stored in the M first cache units at intervals. The operation conversion module can transmit at least part of the data in the first cache module to the corresponding second cache unit, and can perform interpolation operation on at least part of the data in the first cache module to obtain a plurality of interpolation data. The operation conversion module transmits these interpolation data to the second cache unit, so that the second cache unit and the third cache unit jointly store M data, and the M data correspond to M channels respectively. The source driver can output the M data in the second cache unit and the third cache unit to the second part of pixels, thereby realizing the expansion from S data to M data.

[0129] For example, when processing the first group of initial data, the N initial data are stored in the M first cache units at intervals. The operation conversion module is further configured to: according to the control signal, send the N initial data in the first cache module to the corresponding N second cache units respectively; based on Q initial data in the N initial data, calculate (M-N) first interpolation data, and send the (M-N) first interpolation data to the (M-N) second cache units except the N second cache units; based on P initial data in the N initial data, calculate T second interpolation data, and output the T second interpolation data to the T third cache units.

[0130] For example, when processing the second group of initial data, the S initial data are stored in the M first cache units at intervals. The operation conversion module is further configured to: according to the control signal, send the S initial data to the corresponding S second cache units; based on the S initial data, calculate (M-T-S) third interpolation data, and send the (M-T-S) third interpolation data to the (M-T-S) second cache units respectively; the output module is further configured to: output the T interpolation data of the third cache module, the S initial data in the second cache module and the (M-T-S) third interpolation data to the M data signal lines respectively.

[0131] The following describes how the source driver of the embodiment of the present disclosure realizes the horizontal resolution expansion of the display signal of the dual gate pixel architecture in combination with specific embodiments.

[0132] For example, when the first cache module caches N initial data, every two initial data in the N initial data are stored as a sub-group in two adjacent first cache units, and one first cache unit is arranged between every two sub-groups. In other embodiments, every three or more initial data can be stored as a sub-group in three or more adjacent first cache units, and two or more first cache units can be arranged between each sub-group. The arrangement can be set according to actual needs.

[0133] For example, the source driver further includes a controller configured to: in the process of processing the first group of initial data, control the operation conversion module to output two initial data in each sub-group to the corresponding two second cache units; control the operation conversion module to calculate a first interpolation data based on the first data in every two adjacent sub-groups to obtain (M-N) first interpolation data, and output the (M-N) interpolation data to the (M-N) second cache units; control the operation conversion module to calculate a second interpolation data based on the second data in every two adjacent sub-groups to obtain T second interpolation data, and output the T second interpolation data to the T third cache units; and control the output module to output the M data of the second cache module.

[0134] For example, the controller is further configured to: in the process of processing the second group of initial data, control the operation conversion module to output the S initial data in the first cache module to the corresponding S second cache units; control the operation conversion module to calculate a third interpolation data based on every two adjacent initial data in the first cache module, and output each third interpolation data to a second cache unit; and control the output module to output the (M-T) data of the second cache units and the T second interpolation data of the third cache units to the M data signal lines, respectively.

[0135] FIG. 11A shows a schematic diagram of the transmission of the first row data corresponding to the pixel architecture shown in FIG. 2 in the source driver provided in at least one embodiment of the present disclosure.

[0136] As shown in FIG. 11A, the first row of first batch of data (data) can be the first group of initial data corresponding to the first row of sub-pixels, and the first row of second batch of data (data) can be the second group of initial data corresponding to the first row of sub-pixels.

[0137] For example, the first batch of data in the first row includes the sub-pixel data G1-1 / B1-1 / G1-2 / B1-2 / G1-3 / B1-3 / G1-4 / B1-4, etc. in the first row shown in FIG. 5, which are stored in the channels 1 / 2 / 4 / 5 / 7 / 8 / 10 / 11 of the first cache module (L1) in sequence, and so on. The data in each channel of the first cache module is stored into the corresponding channel of the second cache module (L2). Moreover, the data in the channel 1 and the channel 4 of the first cache module are subjected to mean value operation to generate G1-1', which is stored into the third channel of the second cache module; the data in the channel 4 and the channel 7 of the first cache module are subjected to mean value operation to generate G1-2', which is stored into the sixth channel of the second cache module; the data in the channel 7 and the channel 10 of the first cache module are subjected to mean value operation to generate G1-3', which is stored into the ninth channel of the second cache module, and so on.

[0138] For example, the data in the channel 2 and the channel 5 of the first cache module are subjected to mean value operation to generate B1-1', which is stored into the third channel of the third cache module (L3); the data in the channel 5 and the channel 8 of the first cache module are subjected to mean value operation to generate B1-2', which is stored into the sixth channel of the third cache module; the data in the channel 8 and the channel 11 of the first cache module are subjected to mean value operation to generate B1-3', which is stored into the ninth channel of the third cache module, and so on.

[0139] For example, the data stored in each channel of the second cache module, i.e. G1-1 / B1-1 / G1-1' / G1-2 / B1-2 / G1-2' / G1-3 / B1-3 / G1-3', etc., are sent to the corresponding data signal lines of the display panel via the digital-to-analog converter and the amplifier. The data of the third cache module are continuously stored and not transmitted downward at present, but will be transmitted downward when the second batch of data in the first row is processed.

[0140] Through the control of the operation conversion module on the data transmission and interpolation operation between the first cache module and the second cache module, the horizontal resolution expansion of the first batch of data in the first row is realized, and the color arrangement of the group of data (i.e. the M data cached in the second cache module) obtained after the expansion is consistent with the color arrangement of the plurality of sub-pixels connected to the first gate scanning signal line G1, so that the expanded data can be transmitted to the plurality of sub-pixels connected to the first gate scanning signal line G1.

[0141] For example, the first row second batch of data includes the sub-pixel data R1-1 / R1-2 / R1-3 / R1-4 in the first row shown in FIG. 5, which are sequentially stored in the channels 1 / 4 / 7 / 10 of the first cache module, and the like. The data in each channel of the first cache module is stored into the corresponding channel of the second cache module. Moreover, the data in the channel 1 and the channel 4 of the first cache module are subjected to mean value operation to generate R1-1', which is stored into the second channel of the second cache module; the data in the channel 4 and the channel 7 of the first cache module are subjected to mean value operation to generate R1-2', which is stored into the fifth channel of the second cache module; the data in the channel 7 and the channel 10 of the first cache module are subjected to mean value operation to generate R1-3', which is stored into the eighth channel of the second cache module, and the like.

[0142] For example, the data stored in each channel of the second cache module and the data stored in each channel of the third cache module, i.e., R1-1 / R1-1' / B1-1' / R1-2 / R1-2' / B1-2' / R1-3 / R1-3' / B1-3', and the like, are sent to the corresponding data signal lines of the display panel through the digital-to-analog converter and the amplifier.

[0143] For example, if mean value operation cannot be performed when processing the last column of pixel data (including R / G / B three columns of sub-pixels), one more column of pixel data can be sent, which can be the first column of the next source driver or a copy of itself.

[0144] The operation conversion module controls the data transmission and interpolation operation between the first cache module and the second cache module, and simultaneously outputs the data of the second cache module and the data reserved in the third cache module, so that the horizontal resolution expansion of the first row second batch of data is realized, and the color arrangement of the group of expanded data (i.e., M data composed of the data of the second cache module and the data of the third cache module) is consistent with the color arrangement of the plurality of sub-pixels connected to the second gate scanning signal line G2, so that the expanded data can be transmitted to the plurality of sub-pixels connected to the second gate scanning signal line G2.

[0145] FIG. 11B shows a schematic diagram of the transmission of the second row data corresponding to the pixel architecture shown in FIG. 2 in the source driver provided in at least one embodiment of the present disclosure.

[0146] As shown in FIG. 11B, since the arrangement manner of the second row of sub-pixels and the connection manner with the data signal lines are the same as those of the first row, the transmission manner of the second row data in the source driver is the same as that of the first row, which will not be described herein again.

[0147] For example, the multiple rows and multiple columns of sub-pixels further include the i+rth row of sub-pixels, the first and second sub-pixels of the ith row of sub-pixels are connected to the first data signal line, and the first and second sub-pixels of the i+rth row of sub-pixels are connected to the second data signal line. The source driver is configured to: in the process of processing the initial data corresponding to the ith row of sub-pixels, store the N initial data from the first of the M first cache units; in the process of processing the initial data corresponding to the i+rth row of sub-pixels, store the N initial data from the second of the M first cache units; wherein r is a positive integer.

[0148] For example, in the pixel architecture shown in FIG. 2, there are two rows of jumps in the vertical direction, and four rows are a period. In each period, the first two rows are connected from the first data signal line, and the last two rows are connected from the second data signal line. Therefore, for each row of data in the first two rows of data in each period, the data can be stored from the first of the M first cache units; for each row of data in the last two rows of data in each period, the data can be stored from the second of the M first cache units. In this way, the data can correspond to the physical sub-pixels, so that the embodiments of the present disclosure can be applied to pixel architectures with periodic changes in the vertical direction.

[0149] FIG. 11C shows a schematic diagram of the third row of data corresponding to the pixel architecture shown in FIG. 2 being transmitted in the source driver provided by at least one embodiment of the present disclosure.

[0150] As shown in FIG. 11C, the first batch of data in the third row can include the sub-pixel data G3-1 / B3-1 / G3-2 / B3-2 / G3-3 / B3-3 / G3-4 / B3-4, etc. in the third row shown in FIG. 5, which are stored in channels 2 / 3 / 5 / 6 / 8 / 9 / 11 / 12 of the first cache module in sequence. The data in each channel of the first cache module is stored into the corresponding channel of the second cache module. Moreover, the data in channel 2 and channel 5 of the first cache module is subjected to mean value operation to generate G3-1', which is stored into the fourth channel of the second cache module; the data in channel 5 and channel 8 of the first cache module is subjected to mean value operation to generate G3-2', which is stored into the seventh channel of the second cache module; the data in channel 8 and channel 11 of the first cache module is subjected to mean value operation to generate G3-3', which is stored into the tenth channel of the second cache module, and so on.

[0151] For example, the data of channel 3 and channel 6 of the first cache module are subjected to mean value operation to generate B3-1', which is stored in the fourth channel of the third cache module; the data of channel 6 and channel 9 of the first cache module are subjected to mean value operation to generate B3-2', which is stored in the seventh channel of the third cache module; the data of channel 9 and channel 12 of the first cache module are subjected to mean value operation to generate B3-3', which is stored in the tenth channel of the third cache module, and so on.

[0152] For example, the data stored in each channel of the second cache module, i.e., G3-1 / B3-1 / G3-1' / G3-2 / B3-2 / G3-2' / G3-3 / B3-3 / G3-3', is sent to the corresponding data signal line of the display panel through a digital-to-analog converter and an amplifier. For example, the data of the third cache module is continuously stored and not transmitted downward. Based on the above manner, the horizontal resolution expansion of the first batch of data of the third row is realized, and the color arrangement of the group of data obtained after expansion (i.e., the M data stored in the second cache module) is consistent with the color arrangement of the plurality of sub-pixels connected to the fifth gate scanning signal line G5, so that the expanded data can be transmitted to the plurality of sub-pixels connected to the fifth gate scanning signal line G5.

[0153] For example, the second batch of data of the third row can include the sub-pixel data R3-1 / R3-2 / R3-3 / R3-4, etc. in the third row shown in FIG. 5, which are sequentially stored in the channels 2 / 5 / 8 / 11 of the first cache module, and so on. The data of each channel of the first cache module is stored in the corresponding channel of the second cache module. Moreover, the data of channel 2 and channel 5 of the first cache module are subjected to mean value operation to generate R3-1', which is stored in the third channel of the second cache module; the data of channel 5 and channel 8 of the first cache module are subjected to mean value operation to generate R3-2', which is stored in the sixth channel of the second cache module; the data of channel 8 and channel 11 of the first cache module are subjected to mean value operation to generate R3-3', which is stored in the ninth channel of the second cache module, and so on. For example, the data stored in each channel of the second cache module and the data stored in each channel of the third cache module, i.e., R3-1 / R3-1' / B3-1' / R3-2 / R3-2' / B3-2' / R3-3 / R3-3' / B3-3', is sent to the corresponding data signal line of the display panel through a digital-to-analog converter and an amplifier. Based on the above manner, the horizontal resolution expansion of the second batch of data of the third row is realized, and the color arrangement of the group of data obtained after expansion (i.e., the M data obtained by combining the data of the second cache module and the data of the third cache module) is consistent with the color arrangement of the plurality of sub-pixels connected to the sixth gate scanning signal line G6, so that the expanded data can be transmitted to the plurality of sub-pixels connected to the sixth gate scanning signal line G6.

[0154] FIG. 11D shows a schematic diagram of the transmission of the fourth row of data corresponding to the pixel architecture shown in FIG. 2 in the source driver provided in at least one embodiment of the present disclosure.

[0155] As shown in FIG. 11D, since the arrangement of the fourth row of sub-pixels and the connection mode with the data signal line are the same as those of the third row, the transmission mode of the fourth row of data in the source driver is the same as that of the third row of data, and thus is not described herein again.

[0156] For example, for the data processing mode of the fifth row and subsequent rows of sub-pixel data in the source driver, reference can be made to the above-described FIGS. 11A-11D and the related descriptions, and thus is not described herein again.

[0157] Based on the above mode, the expansion of the horizontal resolution of the pixel architecture shown in FIG. 2 is achieved, and the output data is one time more than the received data. Moreover, by controlling the positions of the original data and the interpolated data in the second buffer module or the third buffer module, the correctness of the display is ensured.

[0158] According to at least one embodiment of the present disclosure, by controlling the positions of the data in the respective levels of the buffer, the method of operation, and the time of output, the expansion of the horizontal resolution of the pixel architecture display panel such as Dual gate is achieved.

[0159] According to at least one embodiment of the present disclosure, for each row of the first batch of N initial data of the dual gate pixel architecture, the transmission mode and the interpolation operation of the first batch of data are controlled between the first buffer module and the second buffer module through the operation conversion module, so that the horizontal resolution expansion of each row of the first batch of N initial data is achieved. Moreover, for each row of the second batch of S initial data of the dual gate pixel architecture, the transmission mode and the interpolation operation of the second batch of data are controlled between the first buffer module and the second buffer module through the operation conversion module, and the data of the second buffer module and the data of the third buffer module obtained when the first batch of data is processed are output simultaneously, so that the horizontal resolution expansion of each row of the second batch of S initial data is achieved.

[0160] In addition, at least one embodiment of the present disclosure can also be applied to other types of pixel architectures other than the Dual gate pixel architecture.

[0161] For example, the operation conversion module comprises M first switching switches, K second switching switches and K operation units. The inputs of the M first switching switches are respectively connected with the outputs of M first buffer units, the output of each first switching switch is connected with a second buffer unit and at least one operation unit, and each first switching switch is configured to close the output of the connected first buffer unit, or output the data of the first buffer unit to the connected second buffer unit, or output the data of the first buffer unit to the connected operation unit according to a control signal. The input of each operation unit is connected with the outputs of at least two first switching switches, and the outputs of the K operation units are respectively connected with the inputs of K second switching switches. Each of the first part of the second switching switches is connected with two second buffer units, each of the second part of the second switching switches is connected with two second buffer units and a third buffer unit, and each of the third part of the second switching switches is connected with a third buffer unit. Each second switching switch is configured to close the output of the connected operation unit, or output the data of the operation unit to one of the connected two second buffer units, or output the data of the operation unit to the connected third buffer unit according to a control signal; wherein K is a positive integer less than M.

[0162] FIG. 12 shows a schematic diagram of an operation conversion module provided by at least one embodiment of the present disclosure.

[0163] As shown in FIG. 12, each of the switching switches A1-A8 is a first switching switch, and each of the switching switches B1-B8 is a second switching switch. The switching switch group A (including A1-A8) is connected with the first buffer module, the operation unit group and the second buffer module, the switching switch group B (including B1-B8) is connected with the operation unit group, the second buffer module and the third buffer module, and the second buffer module and the third buffer module are connected with the data signal lines of the display substrate through the digital-to-analog converter and the amplifier.

[0164] For example, the switching switch group A is connected with the operation control signal, and the switching switch group B is connected with the output control signal. The switching switch group A controls whether the data of each first buffer unit is output, is output to the second buffer module or is output to the operation unit according to the operation control signal. The switching switch group B controls whether the operation result of each operation unit is output, is output to which second buffer unit or is output to which third buffer unit according to the output control signal.

[0165] For example, the jth operation unit in the K operation units is connected with the jth first switching switch and the j+3th first switching switch. The jth second switching switch connected with the jth operation unit is connected with the (j+1)th second buffer unit, the (j+2)th second buffer unit and a third buffer unit. Wherein j is a positive integer less than or equal to K.

[0166] For example, as shown in FIG. 12, the operation unit 1 is connected with the switch A1 and the switch A4, the operation unit 2 is connected with the switch A2 and the switch A5, the operation unit 3 is connected with the switch A3 and the switch A6, and so on.

[0167] For example, the switch B1 is connected with the second cache unit 2 and the second cache unit 3, the switch B2 is connected with the second cache unit 3, the second cache unit 4 and the third cache unit 3, the switch B3 is connected with the third cache unit 4, and so on.

[0168] For example, for each row of the first batch of data, the K operation units can be divided into a plurality of first operation units and a plurality of second operation units, each first operation unit is used for processing the first initial data in the adjacent two subgroups, and each second operation unit is used for processing the second initial data in the adjacent two subgroups.

[0169] For example, the controller is further configured to: in the process of processing each row of the first batch of data, control part of the first switches in the M first switches to output the two initial data in each subgroup to the corresponding two second cache units, and output the first initial data in each two adjacent subgroups to the connected first operation unit, so as to calculate the first interpolation data by using the first operation unit; control the second switch connected with each first operation unit to output the first interpolation data calculated by the first operation unit to the latter one of the two second cache units connected with the second switch; output the second initial data in each two adjacent subgroups to the connected second operation unit, so as to calculate the second interpolation data by using the second operation unit; and control the second switch connected with each second operation unit to output the second interpolation data calculated by the second operation unit to the one third cache unit connected with the second switch.

[0170] For example, the controller is further configured to: in the process of processing each row of the second batch of data, control part of the first switches in the M first switches to output each initial data to the corresponding one second cache unit, and output each two initial data to the connected operation unit, so as to calculate the third interpolation data by using the operation unit; control the second switch to output the calculated third interpolation data to the former one of the two second cache units connected with the second switch; and control the second cache module and the third cache module to output the cached data at the same time.

[0171] For example, referring to FIG. 11A and FIG. 12, after the first cache module receives the first row of the first batch of data corresponding to the pixel architecture shown in FIG. 2, the operation conversion module performs action ① shown in FIG. 12, that is:

[0172] The operation control signal controls the switching switch A1 / A2 / A4 / A5 / A7 / A8 of the switching switch A group to send the data of the first buffer module first / second / fourth / fifth / seventh / eighth channel to the corresponding channel of the second buffer module.

[0173] The operation control signal controls the switching switch A1 / A4 / A7 and A2 / A5 / A8 of the switching switch A group to send the data of the first buffer module first / fourth / seventh and second / fifth / eighth channel to the corresponding operation unit 1 / 4 and 2 / 5 respectively.

[0174] The output control signal controls the switching switch B1 and B4 of the switching switch B group to send the operation result of the operation unit 1 / 4 to the third / sixth channel of the second buffer module.

[0175] The output control signal controls the switching switch 2 and 5 of the switching switch B group to send the operation result of the operation unit 2 / 5 to the third / sixth channel of the third buffer module.

[0176] The output control signal controls the second buffer module to send data to the display panel and controls the third buffer module not to send data.

[0177] For example, referring to FIG. 11A and FIG. 12, after the first buffer module receives the first batch of data corresponding to the pixel architecture shown in FIG. 2, the operation conversion module performs action ② shown in FIG. 12, that is:

[0178] The operation control signal controls the switching switch A1 / A4 / A7 of the switching switch A group to send the data of the first buffer module first / fourth / seventh channel to the corresponding channel of the second buffer module.

[0179] The operation control signal controls the switching switch A1 / A4 / A7 of the switching switch A group to send the data of the first buffer module first / fourth / seventh channel to the corresponding operation unit 1 / 4 respectively.

[0180] The output control signal controls the switching switch B1 and B4 of the switching switch B group to send the operation result of the operation unit 1 / 4 to the second / fifth channel of the second buffer module.

[0181] The output control signal controls the second buffer module and the third buffer module to send data to the display panel.

[0182] For example, referring to FIG. 11B and FIG. 12, the action of the first buffer module when receiving the second row of data corresponding to the pixel architecture shown in FIG. 2 is the same as that of the first row.

[0183] For example, referring to FIG. 11C and FIG. 12, after the first buffer module receives the first batch of data corresponding to the pixel architecture shown in FIG. 2, the operation conversion module performs action ③ shown in FIG. 12, that is:

[0184] The operation control signal controls the switching switch A2 / A3 / A5 / A6 / A8 / A9 of the switching switch A group to send the data of the first buffer module 2 / 3 / 5 / 6 / 8 / 9 channel to the corresponding channel of the second buffer module.

[0185] The operation control signal controls the switching switch A2 / A5 / A8, A3 / A6 / A9 of the switching switch A group to send the data of the first buffer module 2 / 5 / 8, 3 / 6 / 9 channel to the corresponding operation unit 2 / 5, 3 / 6 respectively.

[0186] The output control signal controls the switching switch B2 and the switching switch B5 of the switching switch B group to send the operation result of the operation unit 2 / 5 to the 4 / 7 channel of the second buffer module.

[0187] The output control signal controls the switching switch B3 and the switching switch B6 of the switching switch B group to send the operation result of the operation unit 3 / 6 to the 4 / 7 channel of the third buffer module.

[0188] The output control signal controls the second buffer module to send the data to the display panel and controls the third buffer module not to send the data.

[0189] For example, referring to FIG. 11C and FIG. 12, after the first buffer module receives the third row second batch data corresponding to the pixel architecture shown in FIG. 2, the operation conversion module performs the action ④ shown in FIG. 12, that is:

[0190] The operation control signal controls the switching switch A2 / A5 / A8 of the switching switch A group to send the data of the first buffer module 2 / 5 / 8 channel to the corresponding channel of the second buffer module.

[0191] The operation control signal controls the switching switch A2 / A5 / A8 of the switching switch A group to send the data of the first buffer module 2 / 5 / 8 channel to the corresponding operation unit 2 / 5 respectively.

[0192] The output control signal controls the switching switch B2 and the switching switch B5 of the switching switch B group to send the operation result of the operation unit 2 / 5 to the 3 / 6 channel of the second buffer module.

[0193] The output control signal controls the second buffer module and the third buffer module to send the data to the display panel.

[0194] For example, referring to FIG. 11D and FIG. 12, the action when the first buffer module receives the fourth row data corresponding to the pixel architecture shown in FIG. 2 is the same as the third row.

[0195] For example, in some embodiments, the switching switch B group can also be controlled by the operation control signal, or the operation control signal and the output control signal can be one signal, which is distinguished by giving different commands. When the first cache module receives data, it can not be stored in sequence, but can be stored in a designated location. This can be solved by inserting virtual data at the front end, or can be achieved by sending instructions to the source driver. In addition, the data transmission rate remains unchanged when the front end sends data to the source driver. This requirement can be achieved by adding virtual data when sending the second batch of data for each row of pixels.

[0196] For example, the source driver of the embodiments of the present disclosure has a wide range of applications. In addition to being applicable to the pixel architecture shown in FIG. 2, it can also be used for horizontal resolution expansion of more types of dual gate pixel architectures. The following will take the pixel architecture shown in FIG. 3 and the pixel architecture shown in FIG. 4 as examples for illustration.

[0197] FIG. 13 shows a schematic diagram of the transmission of the first row data corresponding to the pixel architecture shown in FIG. 3 in the source driver provided by at least one embodiment of the present disclosure.

[0198] As shown in FIG. 13, the first batch of data of the first row includes the sub-pixel data R1-1 / B1-1 / R1-2 / B1-2 / R1-3 / B1-3 in the first row shown in FIG. 5, which are stored in the channels 1 / 2 / 4 / 5 / 7 / 8 of the first cache module in sequence. By analogy, the data in each channel of the first cache module is stored in the corresponding channel of the second cache module. In addition, the data in the channel 1 and the channel 4 of the first cache module are subjected to mean value operation to generate R1-1', which is stored in the third channel of the second cache module; the data in the channel 4 and the channel 7 of the first cache module are subjected to mean value operation to generate R1-2', which is stored in the sixth channel of the second cache module; the data in the channel 7 and the channel 10 of the first cache module are subjected to mean value operation to generate R1-3', which is stored in the ninth channel of the second cache module, and so on. In addition, the data in the channel 2 and the channel 5 of the first cache module are subjected to mean value operation to generate B1-1', which is stored in the fourth channel of the third cache module; the data in the channel 5 and the channel 8 of the first cache module are subjected to mean value operation to generate B1-2', which is stored in the seventh channel of the third cache module; the data in the channel 8 and the channel 11 of the first cache module are subjected to mean value operation to generate B1-3', which is stored in the tenth channel of the third cache module, and so on. The data stored in each channel of the second cache module, i.e., R1-1 / B1-1 / R1-1' / R1-2 / B1-2 / R1-2' / R1-3 / B1-3 / R1-3', etc., is sent to the corresponding data line of the display panel through the digital-to-analog converter and the amplifier. At this time, the data of the third cache module continues to be stored and is not transmitted downward.

[0199] For example, the second batch of data in the first row shown in FIG. 13 can include the sub-pixel data G1-1 / G1-2 / G1-3 in the first row shown in FIG. 5, which are sequentially stored in the channels 2 / 5 / 8 of the first cache module, and the like. The data in each channel of the first cache module are stored into the corresponding channels of the second cache module, and the data in the channel 2 and the channel 5 of the first cache module are subjected to mean value operation to generate G1-1', which is stored into the third channel of the second cache module; the data in the channel 5 and the channel 8 of the first cache module are subjected to mean value operation to generate G1-2', which is stored into the sixth channel of the second cache module; the data in the channel 8 and the channel 11 of the first cache module are subjected to mean value operation to generate G1-3', which is stored into the ninth channel of the second cache module, and the like. The data stored in each channel of the second cache module and the data stored in each channel of the third cache module, i.e., G1-1 / G1-1' / B1-1' / G1-2 / G1-2' / B1-2' / G1-3 / G1-3' / B1-3', are subjected to digital-to-analog conversion and amplification, and are sent to the corresponding data lines of the display panel.

[0200] The data sending manners of other rows of the pixel architecture shown in FIG. 3 are the same as that of the first row of data, which will not be described herein again.

[0201] FIG. 14 shows a schematic diagram of processing the first row of data corresponding to the pixel architecture shown in FIG. 3 by the operation conversion module according to at least one embodiment of the present disclosure.

[0202] As shown in FIGS. 13 and 14, after the first cache module receives the first batch of data corresponding to the first row of the pixel architecture shown in FIG. 3, the operation conversion module performs action ① shown in FIG. 14, i.e.,

[0203] The operation control signal controls the switching switches A1 / A2 / A4 / A5 / A7 / A8 of the switching switch group A to send the data in the first / second / fourth / fifth / seventh / eighth channels of the first cache module to the corresponding channels of the second cache module.

[0204] The operation control signal controls the switching switches A1 / A4 / A7 and A2 / A5 / A8 of the switching switch group A to send the data in the first / fourth / seventh channels and the second / fifth / eighth channels of the first cache module to the corresponding operation units 1 / 4 and 2 / 5, respectively.

[0205] The output control signal controls the switching switch B1 and the switching switch B4 of the switching switch group B to send the operation results of the operation units 1 / 4 to the third / sixth channels of the second cache module.

[0206] The output control signal controls the switching switch B2 and the switching switch B5 of the switching switch group B to send the operation results of the operation units 2 / 5 to the fourth / seventh channels of the third cache module.

[0207] The output control signal controls the second buffer module to send data to the display panel, and controls the third buffer module to not send data temporarily.

[0208] After the first buffer module receives the first batch of data corresponding to the pixel architecture shown in FIG. 3, the operation conversion module performs action ② shown in FIG. 14, that is:

[0209] The operation control signal controls the switching switches A2 / A5 / A8 of the switching switch group A to send the data of the 2nd / 5th / 8th channels of the first buffer module to the corresponding channels of the second buffer module.

[0210] The operation control signal controls the switching switches A2 / A5 / A8 of the switching switch group A to send the data of the 2nd / 5th / 8th channels of the first buffer module to the corresponding operation units 2 / 5 respectively.

[0211] The output control signal controls the switching switches B2 and B5 of the switching switch group B to send the operation results of the operation units 2 / 5 to the 3rd / 6th channels of the second buffer module.

[0212] The output control signal controls the second buffer module and the third buffer module to send data to the display panel.

[0213] The transmission modes of other rows of data are the same as those of the first row of data, which will not be described herein again.

[0214] FIG. 15A shows a schematic diagram of the transmission of the first row of data corresponding to the pixel architecture shown in FIG. 4 in the source driver provided in at least one embodiment of the present disclosure.

[0215] As shown in FIG. 15A, the first batch of data in the first row includes the sub-pixel data R1-1 / B1-1 / R1-2 / B1-2 / R1-3 / B1-3 in the first row shown in FIG. 5, which are sequentially stored in the channels 2 / 3 / 5 / 6 / 8 / 9 of the first buffer module. The data in each channel of the first buffer module is stored into the corresponding channel of the second buffer module. Moreover, the data in the channel 3 and the channel 6 of the first buffer module is subjected to mean value operation to generate B1-1', which is stored into the fourth channel of the second buffer module; the data in the channel 6 and the channel 9 of the first buffer module is subjected to mean value operation to generate B1-2', which is stored into the seventh channel of the second buffer module; the data in the channel 9 and the channel 12 of the first buffer module is subjected to mean value operation to generate B1-3', which is stored into the tenth channel of the second buffer module, and so on. The data in the channel 2 and the channel 5 of the first buffer module is subjected to mean value operation to generate R1-1', which is stored into the third channel of the third buffer module; the data in the channel 5 and the channel 8 of the first buffer module is subjected to mean value operation to generate R1-2', which is stored into the sixth channel of the third buffer module; the data in the channel 8 and the channel 11 of the first buffer module is subjected to mean value operation to generate R1-3', which is stored into the ninth channel of the third buffer module, and so on. The data stored in each channel of the second buffer module, i.e., R1-1 / B1-1 / B1-1' / R1-2 / B1-2 / B1-2' / R1-3 / B1-3 / B1-3', and so on, is sent to the corresponding data line of the display panel via the digital-to-analog converter and the amplifier. At this time, the data in the third buffer module is continuously stored and not transmitted downward.

[0216] The second batch of data in the first row shown in FIG. 15A includes the sub-pixel data G1-1 / G1-2 / G1-3 in the first row shown in FIG. 5, which are sequentially stored in the channels 2 / 5 / 8 of the first buffer module. The data in each channel of the first buffer module is stored into the corresponding channel of the second buffer module, and moreover, the data in the channel 2 and the channel 5 of the first buffer module is subjected to mean value operation to generate G1-1', which is stored into the fourth channel of the second buffer module; the data in the channel 5 and the channel 8 of the first buffer module is subjected to mean value operation to generate G1-2', which is stored into the seventh channel of the second buffer module; the data in the channel 8 and the channel 11 of the first buffer module is subjected to mean value operation to generate G1-3', which is stored into the tenth channel of the second buffer module, and so on. The data stored in each channel of the second buffer module and the data stored in each channel of the third buffer module, i.e., G1-1 / R1-1' / G1-1' / G1-2 / R1-2' / G1-2' / G1-3 / R1-3' / G1-3', and so on, is sent to the corresponding data line of the display panel via the digital-to-analog converter and the amplifier.

[0217] FIG. 15B shows a schematic diagram of the transmission of the second row data corresponding to the pixel architecture shown in FIG. 4 in the source driver provided in at least one embodiment of the present disclosure.

[0218] As shown in FIG. 15B, the first batch of data of the second row includes the sub-pixel data R2-1 / B2-1 / R2-2 / B2-2 / R2-3 / B2-3 in the first row shown in FIG. 5, which are stored in the channels 1 / 2 / 4 / 5 / 7 / 8 of the first cache module in sequence. The data of each channel of the first cache module is stored into the corresponding channel of the second cache module. Moreover, the data of the channel 2 and the channel 5 of the first cache module is subjected to mean value operation to generate B2-1', which is stored into the third channel of the second cache module; the data of the channel 5 and the channel 8 of the first cache module is subjected to mean value operation to generate B2-2', which is stored into the sixth channel of the second cache module; the data of the channel 8 and the channel 11 of the first cache module is subjected to mean value operation to generate B3-3', which is stored into the ninth channel of the second cache module, and so on. Moreover, the data of the channel 1 and the channel 4 of the first cache module is subjected to mean value operation to generate R2-1', which is stored into the second channel of the third cache module; the data of the channel 4 and the channel 7 of the first cache module is subjected to mean value operation to generate R2-2', which is stored into the fifth channel of the third cache module; the data of the channel 7 and the channel 10 of the first cache module is subjected to mean value operation to generate R2-3', which is stored into the eighth channel of the third cache module, and so on. The data stored in each channel of the second cache module, i.e. R2-1 / B2-1 / B2-1' / R2-2 / B2-2 / B2-2' / R2-3 / B2-3 / B2-3', and so on, is sent to the corresponding data line of the display panel via the digital-to-analog converter and the amplifier. At this time, the data of the third cache module is continuously stored and not transmitted downward.

[0219] The second batch of data of the second row shown in FIG. 15B includes the sub-pixel data G2-1 / G2-2 / G2-3 in the first row shown in FIG. 5, which are stored in the channels 1 / 4 / 7 of the first cache module in sequence, and so on. The data of each channel of the first cache module is stored into the corresponding channel of the second cache module. Moreover, the data of the channel 1 and the channel 4 of the first cache module is subjected to mean value operation to generate G2-1', which is stored into the third channel of the second cache module; the data of the channel 4 and the channel 7 of the first cache module is subjected to mean value operation to generate G2-2', which is stored into the sixth channel of the second cache module; the data of the channel 7 and the channel 10 of the first cache module is subjected to mean value operation to generate G2-3', which is stored into the ninth channel of the second cache module, and so on. The data stored in each channel of the second cache module and the data stored in each channel of the third cache module, i.e. G2-1 / R2-1' / G2-1' / G2-2 / R2-2' / G2-2' / G2-3 / R2-3' / G2-3', and so on, is sent to the corresponding data line of the display panel via the digital-to-analog converter and the amplifier.

[0220] The data sending mode of other rows is the same as that of the first row and the second row, which will not be described herein again.

[0221] The data transmission under the pixel architecture of FIG. 3 can be implemented through the architecture shown in FIG. 12-3.

[0222] FIG. 16 shows a schematic diagram of processing the first row data and the second row data corresponding to the pixel architecture shown in FIG. 4 by the operation conversion module according to at least one embodiment of the present disclosure.

[0223] As shown in FIG. 15A and FIG. 16, after the first cache module receives the first batch of data of the first row corresponding to the pixel architecture shown in FIG. 4, the operation conversion module performs action ① shown in FIG. 16, that is:

[0224] The operation control signal controls the switching switches A2 / A3 / A5 / A6 / A8 / A9 of the switching switch group A to send the data of the 2nd / 3rd / 5th / 6th / 8th / 9th channels of the first cache module to the corresponding channels of the second cache module.

[0225] The operation control signal controls the switching switches A2 / A5 / A8, A3 / A6 / A9 of the switching switch group A to send the data of the 2nd / 5th / 8th, 3rd / 6th / 9th channels of the first cache module to the corresponding operation units 2 / 5, 3 / 6, respectively.

[0226] The output control signal controls the switching switches B3 and B6 of the switching switch group B to send the operation results of the operation units 3 / 6 to the 4th / 7th channels of the second cache module.

[0227] The output control signal controls the switching switches B2 and B5 of the switching switch group B to send the operation results of the operation units 2 / 5 to the 3rd / 6th channels of the third cache module.

[0228] The output control signal controls the data of the second cache module to be sent to the display panel, and controls the data of the third cache module not to be sent temporarily.

[0229] As shown in FIG. 15A and FIG. 16, after the first cache module receives the second batch of data of the first row corresponding to the pixel architecture shown in FIG. 4, the operation conversion module performs action ② shown in FIG. 16, that is:

[0230] The operation control signal controls the switching switches A2 / A5 / A8 of the switching switch group A to send the data of the 2nd / 5th / 8th channels of the first cache module to the corresponding channels of the second cache module.

[0231] The operation control signal controls the switching switches A2 / A5 / A8 of the switching switch group A to send the data of the 2nd / 5th / 8th channels of the first cache module to the corresponding operation units 2 / 5, respectively.

[0232] The output control signal controls the switching switches B2 and B5 of the switching switch group B to send the operation results of the operation units 2 / 5 to the 4th / 7th channels of the second cache module.

[0233] The output control signal controls the second buffer module and the third buffer module to send data to the display panel.

[0234] As shown in FIG. 15B and FIG. 16, after the first buffer module receives the second row of the first batch of data corresponding to the pixel architecture shown in FIG. 4, the operation conversion module performs action ③ shown in FIG. 16, that is:

[0235] The operation control signal controls the switching switches A1 / A2 / A4 / A5 / A7 / A8 of the switching switch group A to send the first buffer module channel 1 / 2 / 4 / 5 / 7 / 8 data to the corresponding channels of the second buffer module;

[0236] The operation control signal controls the switching switches A2 / A5 / A8, A1 / A4 / A7 of the switching switch group A to send the first buffer module channel 2 / 5 / 8, 1 / 4 / 7 data to the corresponding operation units 2 / 5, 1 / 4, respectively;

[0237] The output control signal controls the switching switches B2 and B5 of the switching switch group B to send the operation unit 2 / 5 operation result to the second buffer module channel 3 / 6;

[0238] The output control signal controls the switching switches B1 and B4 of the switching switch group B to send the operation unit 1 / 4 operation result to the third buffer module channel 2 / 5;

[0239] The output control signal controls the second buffer module to send data to the display panel, and controls the third buffer module data to be temporarily not sent.

[0240] As shown in FIG. 15B and FIG. 16, after the first buffer module receives the second row of the second batch of data corresponding to the pixel architecture shown in FIG. 4, the operation conversion module performs action ④ shown in FIG. 16, that is:

[0241] The operation control signal controls the switching switches A1 / A4 / A7 of the switching switch group A to send the first buffer module channel 1 / 4 / 7 data to the corresponding channels of the second buffer module;

[0242] The operation control signal controls the switching switches A1 / A4 / A7 of the switching switch group A to send the first buffer module channel 1 / 4 / 7 data to the corresponding operation units 1 / 4, respectively;

[0243] The output control signal controls the switching switches B1 and B4 of the switching switch group B to send the operation unit 1 / 4 operation result to the second buffer module channel 3 / 6;

[0244] The output control signal controls the second buffer module and the third buffer module to send data to the display panel.

[0245] The third row data transmission mode is the same as the first row data and the second row data, and will not be described again.

[0246] The present disclosure at least one embodiment proposes a hardware super-resolution technology suitable for a Dual gate pixel architecture, including a display panel and a source driver of the Dual gate pixel architecture, compared with the existing source driver, an operation conversion module, a third cache module, an operation control signal and an output control signal are added, by controlling the position of the data stored in each level of the cache, the method of operation and the output time, the expansion of the horizontal resolution of the Dual gate pixel architecture display panel is realized.

[0247] According to at least one embodiment of the present disclosure, the architecture of the display panel is characterized in that: the three continuous sub-pixel units of the same color in the same row of pixels are connected on the same gate line or on two gate lines, and when connected on two gate lines, the first and last two sub-pixel units are connected on the gate line scanned in the previous row, and the middle sub-pixel unit is connected on the gate line scanned in the next row.

[0248] According to at least one embodiment of the present disclosure, the third cache module and the second cache module are parallel, and are located after the operation converter and before the digital-to-analog converter.

[0249] According to at least one embodiment of the present disclosure, the third cache module uses less channels than the second cache module in each round of data transmission, about 1 / 3 of the number of channels used by the second cache module.

[0250] According to at least one embodiment of the present disclosure, the storage channels of the first cache module are no longer arranged in sequence when receiving display data, but are spaced and specified.

[0251] According to at least one embodiment of the present disclosure, the operation converter performs operation on the specified part of the channels of the first cache module and directly transmits the specified part of the channels, and the directly transmitted data is only stored in the second cache module, and the operation result is stored in the specified second cache module and / or third cache module.

[0252] According to at least one embodiment of the present disclosure, the data corresponding to the two continuous gate scanning signal lines corresponding to each row of pixels of the display panel will have part of the data operated, wherein the data corresponding to the first gate scanning signal line is stored in the second cache module and / or the third cache module after being operated, and the data corresponding to the second gate scanning signal line is only stored in the second cache module.

[0253] According to at least one embodiment of the present disclosure, the data stored in the third cache module is not transmitted when the first gate line is driven, but is transmitted when the second gate line is driven.

[0254] The display device provided by any of the embodiments of the present disclosure can be used in an electronic device. For example, the electronic device can be any electronic product with a display function, such as a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, or the like.

[0255] The control method for the display device provided by at least one of the embodiments of the present disclosure can be used in a display device. The display device includes a display substrate and a source driver. The display substrate includes a plurality of rows and columns of sub-pixels arranged in an array, a plurality of gate scanning signal lines, and M data signal lines. The plurality of rows and columns of sub-pixels include an i-th row of sub-pixels. A plurality of initial data corresponding to the i-th row of sub-pixels are divided into a first group of initial data and a second group of initial data. The first group of initial data includes N initial data, and the second group of initial data includes S initial data.

[0256] FIG. 17 shows a flowchart of a control method for a display device according to at least one of the embodiments of the present disclosure.

[0257] As shown in FIG. 17, the method can include steps S410-S450.

[0258] In step S410, the source driver is controlled to receive N initial data, and the N initial data are cached to M first cache units of the source driver, each initial data corresponding to a data signal line.

[0259] In step S420, the source driver is controlled to output M data to a second cache module based on the N initial data, and T interpolation data are obtained based on part of the N initial data and output to a third cache module of the source driver.

[0260] In step S430, the M data cached by the second cache module are output to the M data signal lines.

[0261] In step S440, the source driver is controlled to receive S initial data, and (M-T) data are output to the second cache module based on the S initial data.

[0262] In step S450, the (M-T) data of the second cache module and the T interpolation data of the third cache module are respectively output to the M data signal lines.

[0263] According to the control method of at least one of the embodiments of the present disclosure, by controlling the position of the data stored in each level of the cache, the method of operation, and the time of output, the horizontal resolution of a pixel architecture display panel such as Dual gate is expanded.

[0264] For the control method of the embodiments of the present disclosure, refer to the related description in the foregoing embodiments, which will not be repeated here.

[0265] At least one embodiment of the present disclosure further provides an electronic device including a processor and a memory storing one or more computer program modules. The one or more computer program modules are configured to be executed by the processor to implement the control method described above.

[0266] FIG. 18 is a schematic block diagram of an electronic device according to some embodiments of the present disclosure. As shown in FIG. 18, the electronic device 500 includes a processor 510 and a memory 520. The memory 520 stores non-transitory computer-readable instructions (e.g., one or more computer program modules). The processor 510 is configured to execute the non-transitory computer-readable instructions, which, when executed by the processor 510, perform one or more steps of the control method described above. The memory 520 and the processor 510 can be interconnected by a bus system and / or other forms of connection mechanisms (not shown). For the specific implementation of the steps of the control method and related explanations, reference can be made to the embodiments of the control method described above, and the repeated parts will not be described herein.

[0267] It should be noted that the components of the electronic device 500 shown in FIG. 18 are exemplary only, and are not intended to be limiting. The electronic device 500 can also have other components depending on the actual application needs.

[0268] For example, the processor 510 and the memory 520 can communicate with each other directly or indirectly.

[0269] For example, the processor 510 and the memory 520 can communicate through a network. The network can include a wireless network, a wired network, and / or any combination of a wireless network and a wired network. The processor 510 and the memory 520 can also communicate with each other through a system bus, which is not limited by the present disclosure.

[0270] For example, the processor 510 and the memory 520 can be disposed at a server end (or cloud end).

[0271] For example, the processor 510 can control other components in the electronic device 500 to perform desired functions. For example, the processor 510 can be a central processing unit (CPU), a graphics processing unit (GPU), or other forms of processing units having data processing capabilities and / or program execution capabilities. For example, the central processing unit (CPU) can be of X86 or ARM architecture, etc. The processor 510 can be a general-purpose processor or a special-purpose processor, and can control other components in the electronic device 500 to perform desired functions.

[0272] For example, the memory 520 can include any combination of one or more computer program products. The computer program product can include various forms of computer-readable storage media, for example, volatile memory and / or non-volatile memory. The volatile memory, for example, can include random access memory (RAM), cache memory, and / or the like. The non-volatile memory, for example, can include read-only memory (ROM), hard disk, erasable programmable read-only memory (EPROM), compact disc read-only memory (CD-ROM), USB memory, flash memory, and / or the like. One or more computer program modules can be stored on the computer-readable storage media, and the processor 510 can execute the one or more computer program modules to implement various functions of the electronic device 500. Various application programs and various data used and / or generated by the application programs, and the like can also be stored in the computer-readable storage media.

[0273] For example, in some embodiments, the electronic device 500 can be a mobile phone, a tablet computer, a television, a display, a notebook computer, a wearable electronic device, a smart home device, and / or the like. For example, the electronic device 500 can include a display apparatus.

[0274] It should be noted that, in the embodiments of the present disclosure, the specific functions and technical effects of the electronic device 500 can refer to the description of the control method above, and will not be described here again.

[0275] FIG. 19 is a schematic block diagram of another electronic device according to some embodiments of the present disclosure. The electronic device 600 is suitable for implementing the control method according to some embodiments of the present disclosure, for example. The electronic device 600 can be a terminal device, and / or the like. It should be noted that the electronic device 600 shown in FIG. 19 is merely an example, and should not be construed as limiting the functions and usage range of the embodiments of the present disclosure.

[0276] As shown in FIG. 19, the electronic device 600 can include a processing apparatus (for example, a central processing unit, a graphics processing unit, and / or the like) 610, which can perform various appropriate actions and processes according to programs stored in a read-only memory (ROM) 620 or loaded from a storage apparatus 680 to a random access memory (RAM) 630. Various programs and data required for the operation of the electronic device 600 are also stored in the RAM 630. The processing apparatus 610, the ROM 620, and the RAM 630 are connected to each other through a bus 640. An input / output (I / O) interface 650 is also connected to the bus 640.

[0277] In general, the following devices can be connected to the I / O interface 650: input devices 660 including, for example, a touch screen, a touch pad, a keyboard, a mouse, a camera, a microphone, an accelerometer, a gyroscope, and the like; output devices 670 including, for example, a liquid crystal display (LCD), a speaker, a vibrator, and the like; storage devices 680 including, for example, a magnetic tape, a hard disk, and the like; and communication devices 690. The communication devices 690 can allow the electronic device 600 to communicate wirelessly or wiredly with other electronic devices to exchange data. While FIG. 19 illustrates the electronic device 600 having various devices, it is understood that all of the illustrated devices are not required to be implemented or possessed, and the electronic device 600 can instead implement or possess more or fewer devices.

[0278] For example, according to embodiments of the present disclosure, the above-described control method can be implemented as a computer software program. For example, embodiments of the present disclosure include a computer program product including a computer program carried on a non-transitory computer readable medium, the computer program including program codes for executing the above-described control method. In such embodiments, the computer program can be downloaded and installed from a network through the communication devices 690, or installed from the storage devices 680, or installed from the ROM 620. When the computer program is executed by the processing devices 610, the functions defined in the control method provided by embodiments of the present disclosure can be implemented.

[0279] At least one embodiment of the present disclosure also provides a computer readable storage medium storing non-transitory computer readable instructions which, when executed by a computer, can implement the above-described control method.

[0280] FIG. 20 is a schematic diagram of a storage medium according to some embodiments of the present disclosure. As shown in FIG. 20, the storage medium 700 stores non-transitory computer readable instructions 710. For example, when the non-transitory computer readable instructions 710 are executed by a computer, one or more steps of the control method according to the above are performed.

[0281] For example, the storage medium 700 can be applied in the above-described electronic device 500. For example, the storage medium 700 can be the memory 520 in the electronic device 500 shown in FIG. 18. For example, the relevant description regarding the storage medium 700 can refer to the corresponding description of the memory 520 in the electronic device 500 shown in FIG. 18, which will not be repeated here.

[0282] The above description merely illustrates the preferred embodiments of the present disclosure and the principles of the technology applied. It should be understood by those skilled in the art that the disclosed scope of the present disclosure is not limited to the technical solutions formed by the specific combinations of the above technical features, and should also cover other technical solutions formed by the combinations of the above technical features or their equivalent features without departing from the above disclosed concept. For example, the technical solutions formed by replacing the above features with the technical features disclosed in the present disclosure (but not limited to) having similar functions.

[0283] In addition, although each operation is described in a particular order, this should not be understood as requiring the operations to be performed in the specific order shown or in a sequential order. In certain circumstances, multitasking and parallel processing can be advantageous. Similarly, although several implementation details are included in the above discussion, these should not be interpreted as limiting the scope of the present disclosure. Certain features described in the context of separate embodiments can also be combined in a single embodiment. Conversely, various features described in the context of a single embodiment can also be implemented separately or in any suitable subcombination.

[0284] Although the subject matter has been described in language specific to structural features and / or methodological acts, it is to be understood that the subject defined in the appended claims is not necessarily limited to the specific features or acts described above. Rather, the specific features and acts described above are merely illustrative of example forms of implementing the claims.

[0285] For the present disclosure, the following points need to be explained:

[0286] (1) The drawings of the embodiments of the present disclosure only relate to the structures involved in the embodiments of the present disclosure, and other structures can refer to the general design.

[0287] (2) In the case of no conflict, the embodiments of the present disclosure and the features in the embodiments can be combined with each other to obtain new embodiments.

[0288] The above is merely a specific implementation of the present disclosure, but the protection scope of the present disclosure is not limited thereto, and the protection scope of the present disclosure should be subject to the protection scope of the claims.

Claims

1. A display device comprising: a display substrate comprising a plurality of rows and columns of sub-pixels arranged in an array, a plurality of gate scan signal lines, and M data signal lines, wherein the plurality of rows and columns of sub-pixels comprises an ith row of sub-pixels, a plurality of initial data corresponding to the ith row of sub-pixels is divided into a first group of initial data and a second group of initial data, the first group of initial data comprises N initial data, and the second group of initial data comprises S initial data; and a source driver comprising: a first cache module comprising M first cache units configured to cache the N initial data or the S initial data, each of the initial data corresponding to one of the data signal lines; a second cache module comprising at least M second cache units; a third cache module comprising a plurality of third cache units; an operation conversion module configured to receive the N initial data, output M data to the second cache module based on the N initial data according to a control signal, and obtain T interpolation data based on part of the N initial data and output the T interpolation data to the third cache module; an output module configured to output the M data of the second cache module to the M data signal lines, respectively; wherein the operation conversion module is further configured to receive the S initial data, output (M-T) data to the second cache module based on the S initial data according to the control signal; the output module is further configured to output the (M-T) data of the second cache module and the T interpolation data of the third cache module to the M data signal lines, respectively; wherein M is a positive integer greater than 2, N and S are positive integers less than M, and T is a positive integer less than N.

2. The display device of claim 1, wherein: the N initial data are stored in the M first cache units at intervals; the operation conversion module is further configured to: send the N initial data to corresponding N second cache units according to the control signal; calculate (M-N) first interpolation data based on Q initial data of the N initial data and send the (M-N) first interpolation data to (M-N) second cache units other than the N second cache units; and calculate T second interpolation data based on P initial data of the N initial data and output the T second interpolation data to T third cache units.

3. The display device of claim 2, wherein: the S initial data are stored in the M first cache units at intervals; the operation conversion module is further configured to: send the S initial data to corresponding S second cache units according to the control signal; calculate (M-T-S) third interpolation data based on the S initial data and send the (M-T-S) third interpolation data to (M-T-S) second cache units, respectively. ​ The output module is further configured to output T interpolation data of the third cache module, S initial data in the second cache module and (M-T-S) third interpolation data to the M data signal lines respectively.

4. The display device of any one of claims 1-3, wherein, Each of the plurality of rows of the plurality of columns of sub-pixels includes a plurality of colors of sub-pixels, and the plurality of colors of sub-pixels are arranged in a cycle; Each two of the plurality of gate scanning signal lines are connected to a row of sub-pixels, and each of the M data signal lines is connected to two columns of sub-pixels; Two sub-pixels connected to the same data signal line and connected to adjacent two of the plurality of gate scanning signal lines are different colors of sub-pixels.

5. The display device of claim 4, wherein, The plurality of colors of sub-pixels include a first color of sub-pixel, a second color of sub-pixel and a third color of sub-pixel; The first group of initial data includes initial data corresponding to the first color of sub-pixel and initial data corresponding to the second color of sub-pixel; The second group of initial data includes initial data corresponding to the third color of sub-pixel.

6. The display device according to any one of claims 1 to 5, wherein The operation conversion module includes M first switching switches, K second switching switches and K operation units; The inputs of the M first switching switches are connected to the outputs of the M first cache units respectively, the output of each of the first switching switches is connected to a second cache unit and at least one operation unit, and each of the first switching switches is configured to close the output of the connected first cache unit, or output data of the first cache unit to the connected second cache unit, or output data of the first cache unit to the connected operation unit according to a control signal. The inputs of each of the operation units are connected to the outputs of at least two of the first switching switches, and the outputs of the K operation units are connected to the inputs of the K second switching switches respectively. Each of the first part of the second switching switches is connected to two of the second cache units, each of the second part of the second switching switches is connected to two of the second cache units and one of the third cache units, and each of the third part of the second switching switches is connected to one of the third cache units, and each of the second switching switches is configured to close the output of the connected operation unit, or output data of the operation unit to one of the two connected second cache units, or output data of the operation unit to the connected third cache unit according to a control signal. K is a positive integer less than M.

7. The display device of claim 3, wherein, Each two of the N initial data are stored in adjacent two of the first cache units as a sub-group, and each two of the sub-groups are separated by one of the first cache units; Each two of the S initial data are separated by two of the first cache units; The jth operation unit of the K operation units is connected to the jth first switching switch and the j+3th first switching switch; The jth second switching switch connected to the jth operation unit is connected to the (j+1)th second cache unit, the (j+2)th second cache unit and one of the third cache units; ​ Wherein, j is a positive integer less than or equal to K.

8. The display device of claim 7, wherein, The source driver further comprises a controller configured to: In the process of processing the first group of initial data, the operation conversion module is controlled to output two initial data in each of the subgroups to two corresponding second cache units; The operation conversion module is controlled to calculate a first interpolation data based on the first data in each two adjacent subgroups to obtain the (M-N) first interpolation data, and output the (M-N) interpolation data to the (M-N) second cache units; The operation conversion module is controlled to calculate a second interpolation data based on the second data in each two adjacent subgroups to obtain the T second interpolation data, and output the T second interpolation data to the T third cache units; The output module is controlled to output the M data of the second cache module.

9. The display device according to claim 7 or 8, wherein The controller is further configured to: In the process of processing the second group of initial data, the operation conversion module is controlled to output the S initial data in the first cache module to S corresponding second cache units respectively; The operation conversion module is controlled to calculate a third interpolation data based on each two adjacent initial data in the first cache module, and output each of the third interpolation data to a second cache unit; The output module is controlled to output the (M-T) data of the second cache unit and the T second interpolation data of the third cache unit to the M data signal lines respectively.

10. The display device according to any one of claims 1 to 9, wherein, The multiple rows and multiple columns of subpixels further comprise an i+rth row of subpixels, a first subpixel and a second subpixel of the ith row of subpixels are connected with a first data signal line, a first subpixel and a second subpixel of the i+rth row of subpixels are connected with a second data signal line; The source driver is configured to: In the process of processing the initial data corresponding to the ith row of subpixels, the N initial data are cached from the first of the M first cache units; In the process of processing the initial data corresponding to the i+rth row of subpixels, the N initial data are cached from the second of the M first cache units; Wherein, r is a positive integer.

11. The display device according to any one of claims 1 to 10, wherein The output module comprises: a digital-to-analog converter configured to convert the signals corresponding to the M data into analog driving signals; an amplifier configured to amplify the analog driving signals and output them to the M data signal lines.

12. An electronic device comprising the display device of any one of claims 1-11.

13. A control method for a display device, the display device comprising a display substrate and a source driver, the display substrate comprising a plurality of rows and columns of subpixels arranged in an array, a plurality of gate scanning signal lines, and M data signal lines, the plurality of rows and columns of subpixels comprising an ith row of subpixels, a plurality of initial data corresponding to the ith row of subpixels being divided into a first group of initial data and a second group of initial data, the first group of initial data comprising N initial data, and the second group of initial data comprising S initial data, the method comprising: The source driver receives the N initial data and controls the source driver to cache the N initial data to M first cache units of the source driver, wherein each initial data corresponds to one data signal line; The source driver receives the N initial data and controls the source driver to cache the N initial data to M first cache units of the source driver, wherein each initial data corresponds to one data signal line; The source driver receives the N initial data and controls the source driver to cache the N initial data to M first cache units of the source driver, wherein each initial data corresponds to one data signal line; The source driver receives the N initial data and controls the source driver to cache the N initial data to M first cache units of the source driver, wherein each initial data corresponds to one data signal line; The source driver receives the N initial data and controls the source driver to cache the N initial data to M first cache units of the source driver, wherein each initial data corresponds to one data signal line; 14.An electronic device, comprising: a processor; a memory storing one or more computer program modules; wherein the one or more computer program modules are configured to be executed by the processor to implement the control method of claim 13. 15.A computer-readable storage medium storing non-transitory computer-readable instructions that, when executed by a computer, implement the control method of claim 13. ​

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