Time compensation method and system for interference test device

Abstract

The present invention provides a time compensation method and system for an interference test device. The method comprises: acquiring a first delay time and a second delay time; decomposing the first delay time and the second delay time to obtain a nanosecond-level delay time corresponding to the first delay time and a picosecond-level delay time corresponding to the second delay time; performing lead compensation on the nanosecond-level delay time by means of a configurable lead compensation and output module to obtain a nanosecond-level lead compensation time; performing lag compensation on the picosecond-level delay time by means of a delay compensation module to obtain a picosecond-level delay compensation time, and calculating the sum of the nanosecond-level lead compensation time and the picosecond-level delay compensation time to obtain a picosecond-level lead compensation time; and on the basis of the picosecond-level lead compensation time, applying an interference signal on a CAN bus. Thus, the picosecond-level delay compensation time is realized in a mode of cascading a plurality of timing controllers in a delay compensation module.

Description

Time compensation method and system for interference test equipment

[0001] The present application claims priority from a Chinese patent application filed on May 22, 2024, with the Chinese Patent Office and application number 202410642768.2, and entitled "Time compensation method and system for interference test equipment", the content of which is incorporated herein in its entirety. TECHNICAL FIELD

[0002] The present application relates to the technical field of vehicle-mounted communication testing, and in particular to a time compensation method and system for interference test equipment. BACKGROUND

[0003] Vehicle-mounted CAN(FD) bus technology is a communication technology applied to the monitoring and control of various devices in the vehicle-mounted communication field. The CAN(FD) bus technology includes a signal error processing mechanism, which can be used to ensure the correctness of the identified logic level signal. In order to ensure that the CAN(FD) bus technology automobile electronic controller can still communicate stably and accurately match the sampling points under the bus interference scene, the prior art uses a CAN(FD) bus interference test equipment to generate signal interference, thereby implementing fault injection and sampling point testing.

[0004] However, the main chip of the interference test equipment is generally a microcontroller (MCU) or a programmable logic gate array (FPGA), and its working clock frequency is at most hundreds of megahertz, and the clock period is at the nanosecond (ns) level, so that the interference test equipment cannot achieve high-precision time compensation with a resolution lower than the nanosecond level, and thus cannot guarantee the accuracy of the interference signal and the test error of the sampling points.

[0005] SUMMARY

[0006] Therefore, the embodiments of the present application provide a time compensation method and system for interference test equipment to solve the problem that the prior art cannot achieve high-precision time compensation with a resolution lower than the nanosecond level.

[0007] To achieve the above object, the embodiments of the present application provide the following technical solutions:

[0008] The first aspect of the embodiments of the present application discloses a time compensation method for interference test equipment, the method comprising:

[0009] obtaining a first delay time and a second delay time;

[0010] decomposing the first delay time and the second delay time to obtain a nanosecond-level delay time corresponding to the first delay time and a picosecond-level delay time corresponding to the second delay time;

[0011] The nanosecond-level delay time is pre-compensated by a configurable pre-compensation and output module to obtain a nanosecond-level pre-compensation time; wherein the configurable pre-compensation and output module is composed of preset logic codes;

[0012] The picosecond-level delay time is lag-compensated by a delay compensation module to obtain a picosecond-level delay compensation time, and a sum of the nanosecond-level pre-compensation time and the picosecond-level delay compensation time is calculated to obtain a picosecond-level pre-compensation time; wherein the delay compensation module is composed of a plurality of time sequence controllers connected in cascade, and the plurality of time sequence controllers are used to adjust the delay of the picosecond-level delay time;

[0013] Based on the picosecond-level pre-compensation time, an interference signal is applied to the CAN bus.

[0014] Optionally, in the time compensation method of the interference test equipment, the method further comprises:

[0015] Obtaining a bus parameter on the CAN bus;

[0016] Based on the bus parameter, a current acquisition signal on the CAN bus at the current time is obtained;

[0017] The current acquisition signal is analyzed to obtain an interference position of the current acquisition signal on the CAN RX signal line;

[0018] According to the interference position, a target interference signal is applied to the CAN bus.

[0019] Optionally, in the time compensation method of the interference test equipment, the method further comprises:

[0020] The baud rate and the sampling point of the CAN bus are extracted from the bus parameter;

[0021] The CAN(FD) communication basic parameters corresponding to the baud rate and the sampling point are searched from a preset table;

[0022] According to the CAN(FD) communication basic parameters, the current acquisition signal at the current time is obtained from the CAN bus.

[0023] Optionally, in the time compensation method of the interference test equipment, after the interference signal is applied to the CAN bus based on the picosecond-level pre-compensation time, the method further comprises:

[0024] When the interference signal is a high level, it is determined that the delay compensation time of the CAN bus is the opening time of a transistor switch;

[0025] determining that the delay compensation time of the CAN bus is a total delay time when the interference signal is a low level; wherein the total delay time refers to a sum of a delay time from a CAN PHY bus to a CAN RX signal line and a delay time from a CAN TX signal line to the CAN PHY bus.

[0026] Optionally, in the time compensation method of the interference test equipment, the method further includes:

[0027] obtaining the picosecond-level delay compensation time;

[0028] dividing the picosecond-level delay compensation time into equal parts according to a preset threshold to obtain a plurality of divided delay times, and distributing the plurality of divided delay times to a plurality of the time sequence controllers.

[0029] Optionally, in the time compensation method of the interference test equipment, the method further includes:

[0030] obtaining a temperature voltage and a tap number corresponding to the picosecond-level delay compensation time;

[0031] calibrating the temperature voltage by using an IDelayCtrl unit in the delay compensation module;

[0032] adjusting the tap number corresponding to the picosecond-level delay compensation time based on the calibrated temperature voltage, so that delay times of all time sequence controller units in the delay compensation module are the same.

[0033] Optionally, in the time compensation method of the interference test equipment, the leading compensation of the nanosecond-level delay time by the configurable leading compensation and output module to obtain the nanosecond-level leading compensation time includes:

[0034] obtaining a frequency of a system clock and a position of a current time on the CAN bus;

[0035] performing nanosecond-level tapping on the nanosecond-level delay time by the configurable leading compensation and output module according to the frequency and the position to obtain the nanosecond-level leading compensation time.

[0036] Optionally, in the time compensation method of the interference test equipment, the lag compensation of the picosecond-level delay time by the delay compensation module to obtain the picosecond-level delay compensation time includes:

[0037] obtaining a system clock, the nanosecond-level leading compensation time, and a user-configurable delay parameter;

[0038] calculating a picosecond-level delay value by using the user-configurable delay parameter through a delay tap number distribution module in the delay compensation module.

[0039] adjusting the picosecond-level delay time by each timing controller in the delay compensation module according to the system clock, the nanosecond-level advance compensation time and the picosecond-level delay value to obtain a picosecond-level delay compensation time.

[0040] The second aspect of the embodiment of the present application discloses a time compensation system of an interference test device, which comprises a user configuration parameter analysis module, a configurable advance compensation and output module and a delay compensation module.

[0041] The user configuration parameter analysis module is used to obtain a first delay time and a second delay time, and to decompose the first delay time and the second delay time to obtain a nanosecond-level delay time corresponding to the first delay time and a picosecond-level delay time corresponding to the second delay time.

[0042] The configurable advance compensation and output module is used to advance compensate the nanosecond-level delay time to obtain a nanosecond-level advance compensation time; wherein the configurable advance compensation and output module is composed of preset logic codes.

[0043] The delay compensation module is used to lag compensate the picosecond-level delay time to obtain a picosecond-level delay compensation time, to calculate the sum of the nanosecond-level advance compensation time and the picosecond-level delay compensation time to obtain a picosecond-level advance compensation time, and to impose the interference signal on the CAN bus based on the picosecond-level advance compensation time; wherein the delay compensation module is composed of a plurality of timing controllers connected in cascade, and the picosecond-level delay time is adjusted by the plurality of timing controllers.

[0044] Optionally, in the time compensation system of the interference test device, it is further used for:

[0045] The user configuration parameter analysis module is used to obtain bus parameters on the CAN bus, and to obtain a current acquisition signal on the CAN bus at the current time based on the bus parameters.

[0046] The analysis module is used to analyze the current acquisition signal to obtain an interference position of the current acquisition signal on the CAN RX signal line.

[0047] The delay compensation module is used to impose a target interference signal on the CAN bus according to the interference position.

[0048] Optionally, in the time compensation system of the interference test device, the user configuration parameter parsing module is configured to acquire a current collection signal on the CAN bus at a current time based on the bus parameter, and specifically configured to:

[0049] extract a baud rate and a sampling point of the CAN bus from the bus parameter;

[0050] find a CAN(FD) communication basic parameter corresponding to the baud rate and the sampling point from a preset table;

[0051] acquire a current collection signal on the CAN bus at a current time according to the CAN(FD) communication basic parameter.

[0052] Optionally, in the time compensation system of the interference test device, the time compensation system is further configured to:

[0053] the delay compensation module is configured to determine the delay compensation time of the CAN bus as an on time of a transistor switch when the interference signal is a high level;

[0054] the delay compensation module is configured to determine the delay compensation time of the CAN bus as a total delay time when the interference signal is a low level, wherein the total delay time refers to a sum of a delay time from a CAN PHY bus to a CAN RX signal line and a delay time from a CAN TX signal line to the CAN PHY bus.

[0055] Optionally, in the time compensation system of the interference test device, the time compensation system is further configured to:

[0056] the delay compensation module is configured to acquire the picosecond-level delay compensation time, and configured to divide the picosecond-level delay compensation time into multiple divided delay times according to a preset threshold, and configured to distribute the multiple divided delay times to the multiple time sequence controllers.

[0057] Optionally, in the time compensation system of the interference test device, the time compensation system is further configured to:

[0058] the delay compensation module is configured to acquire a temperature voltage and a tap number corresponding to the picosecond-level delay compensation time, and configured to calibrate the temperature voltage by using an IDelayCtrl unit in the delay compensation module, and configured to adjust the tap number corresponding to the picosecond-level delay compensation time based on the calibrated temperature voltage, so that delay times of all time sequence controller units in the delay compensation module are the same.

[0059] Optionally, in the time compensation system of the interference test device, the configurable leading compensation and output module performs leading compensation on the nanosecond delay time to obtain a nanosecond leading compensation time, and the nanosecond leading compensation time is used for:

[0060] obtaining a frequency of a system clock and a position on the CAN bus at a current time;

[0061] The configurable leading compensation and output module performs nanosecond-level beat on the nanosecond delay time according to the frequency and the position to obtain a nanosecond leading compensation time.

[0062] Optionally, in the time compensation system of the interference test device, the delay compensation module performs lag compensation on the picosecond delay time to obtain a picosecond delay compensation time, and the picosecond delay compensation time is used for:

[0063] obtaining a system clock, the nanosecond leading compensation time, and a user-configurable delay parameter;

[0064] The delay tap number distribution module in the delay compensation module calculates a picosecond delay value by using the user-configurable delay parameter;

[0065] Each timing controller in the delay compensation module performs picosecond adjustment on the picosecond delay time according to the system clock, the nanosecond leading compensation time, and the picosecond delay value to obtain a picosecond delay compensation time.

[0066] Based on the time compensation method of the interference test device provided in the embodiment of the application, the first delay time and the second delay time are obtained, and then the first delay time and the second delay time are decomposed to obtain a nanosecond delay time corresponding to the first delay time and a picosecond delay time corresponding to the second delay time. Then, the configurable leading compensation and output module performs leading compensation on the nanosecond delay time to obtain a nanosecond leading compensation time. Then, the delay compensation module performs lag compensation on the picosecond delay time to obtain a picosecond delay compensation time. The sum of the nanosecond leading compensation time and the picosecond delay compensation time is calculated to obtain a picosecond leading compensation time. The delay compensation module is composed of a plurality of timing controllers connected in cascade. Finally, the interference signal is applied on the CAN bus based on the picosecond leading compensation time. Thus, the picosecond delay compensation time is realized by the cascade connection of the plurality of timing controllers in the delay compensation module, and the interference signal applied on the CAN bus can achieve the precision of picosecond resolution. BRIEF DESCRIPTION OF DRAWINGS

[0067] In order to make the technical solutions in the embodiments of the present application or the prior art clearer, the accompanying drawings needed in the embodiments or prior art description will be briefly introduced. Obviously, the accompanying drawings in the following description only aim to explain part of the embodiments of the present application, and all other embodiments obtained by those of ordinary skill in the art without any creative effort based on the provided drawings also belong to the protection scope of the present application.

[0068] Fig. 1 is a structural schematic diagram of a time compensation system disclosed by an embodiment of the present application;

[0069] Fig. 2 is a time compensation waveform diagram of a CAN(FD) interference signal disclosed by an embodiment of the present application;

[0070] Fig. 3 is a flowchart of a time compensation method of an interference test device disclosed by an embodiment of the present application;

[0071] Fig. 4 is a flowchart of a method for obtaining nanosecond-level advance compensation time disclosed by another embodiment of the present application;

[0072] Fig. 5 is a structural schematic diagram of a delay compensation module disclosed by an embodiment of the present application;

[0073] Fig. 6 is a flowchart of a method for obtaining picosecond-level delay compensation time disclosed by another embodiment of the present application;

[0074] Fig. 7 is a flowchart of a calibration method of a delay compensation time disclosed by another embodiment of the present application;

[0075] Fig. 8 is a flowchart of a processing method of temperature voltage disclosed by another embodiment of the present application;

[0076] Fig. 9 is a flowchart of a method for applying an interference signal disclosed by another embodiment of the present application;

[0077] Fig. 10 is a flowchart of a method for obtaining a current acquisition signal disclosed by another embodiment of the present application;

[0078] Fig. 11 is a structural schematic diagram of a time compensation system of an interference test device disclosed by another embodiment of the present application. DETAILED DESCRIPTION

[0079] The technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, and not all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without any creative effort also belong to the protection scope of the present application.

[0080] In this disclosure, the terms "comprising" or "comprise", or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but can also include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by an occurrence of "comprising" does not exclude the presence of additional identical elements in the process, method, article, or apparatus including the element.

[0081] The embodiment of the present application provides a time compensation method of interference test equipment, which is applied to a time compensation system to solve the problem of inability to realize high-precision time compensation with resolution lower than nanosecond level caused by the prior art.

[0082] It should be noted that the time compensation system is combined and cascaded through internal self-defined logic in an editable gate array device (FPGA) and a plurality of time sequence controller units, so that high-precision time compensation with picosecond resolution is realized, and the accuracy of the applied interference signal is ensured, and the test error of the sampling point is reduced.

[0083] Optionally, as shown in FIG. 1, the embodiment of the present application provides a time compensation system, which comprises a host computer, a ZYNQ chip and a CAN PHY chip.

[0084] The host computer is used to accelerate the data transmission rate, and will transmit and compress the control parameters required by a plurality of board cards and a signal in the process of CAN bus signal transmission according to the communication protocol between the host computer and the ZYNQ chip.

[0085] The ZYNQ chip is a chip based on an FPGA and an ARM processor, which integrates the FPGA and the processor core of the ARM into the same chip, and provides powerful hardware acceleration and flexible software processing capability. The ZYNQ chip comprises a PS end and a PL end. Specifically, the PL end refers to the FPGA controller in the ZYNQ chip, and the PS end refers to the ARM controller in the ZYNQ chip.

[0086] It should be noted that the PS end comprises a user configuration parameter analysis module, and the PL end comprises an analysis module, a CAN(FD) interference delay and advance compensation automatic allocation module, a CAN(FD) interference signal configurable advance compensation and output module and a delay compensation module composed of ODELAYE3 and IDELAYE3 multi-stage cascades. The ODELAYE3 and the IDELAYE3 are both time sequence controllers, and are both used for picosecond delay adjustment of time.

[0087] It should be noted that the user configuration parameter analysis module can include a USB data analysis module, a CAN(FD) configurable delay parameter module, and a CAN(FD) configurable control parameter module. Specifically, the USB data analysis module is configured to reverse analyze USB CDC serial port data into control parameters required by multiple boards based on a communication protocol between the host computer and the ZYNQ, that is, the analysis data described in the following embodiments.

[0088] The CAN(FD) configurable delay parameter module is configured to send the analysis data into the CAN(FD) interference delay and advance compensation automatic allocation module in the PL end through the ZYNQ internal AXI bus when the analysis data is a delay time.

[0089] The CAN(FD) configurable control parameter module is configured to send the analysis data into the high-speed analysis module in the PL end through the ZYNQ internal AXI bus when the analysis data is a parameter.

[0090] The analysis module includes a CAN(FD) data high-speed analysis module and a CAN(FD) real-time state analysis module. The CAN(FD) data high-speed analysis module is configured to analyze the parameter to obtain a numerical value corresponding to the parameter and send the numerical value to the CAN(FD) real-time state analysis module. The CAN(FD) real-time state analysis module is configured to analyze a position of a CAN(FD) protocol in which a signal is located according to the numerical value corresponding to the parameter.

[0091] The CAN(FD) interference delay and advance compensation automatic allocation module is configured to allocate the delay time to a CAN(FD) interference signal configurable advance compensation and output module and a delay compensation module.

[0092] The CAN(FD) interference signal configurable advance compensation and output module is configured to process the delay time to provide an advance compensation interference signal with a time of a nanosecond level and a resolution not higher than a frequency of an internal system clock of an FPGA (160MHz≥f≥16MHz).

[0093] The delay compensation module composed of the ODELAYE3 and the IDELAYE3 multi-stage cascades is configured to combine the advance compensation interference signal with a nanosecond level and a picosecond level lag compensation signal provided by itself, and finally realize the application of a picosecond level resolution interference signal on the CAN(FD).

[0094] The CAN PHY chip comprises a CAN TX signal line, a CAN RX signal line and a CAN bus. During the transmission of the CAN(FD) message signal, the CAN(FD) message signal is converted from the CAN bus to the CAN RX signal line through the PHY chip, and the subsequent interference signal is converted from the CAN TX signal line to the CAN bus through the PHY chip. Therefore, when the CAN(FD) message signal is converted by the PHY chip and sent to the upper computer, the upper computer sends the CAN(FD) message signal to the ZYNQ chip through the USB protocol to determine the picosecond-level delay compensation time, and then based on the delay time, the interference signal is transmitted to the CAN TX signal line and then applied to the CAN bus through the PHY chip. Specifically, refer to the time compensation waveform diagram of the CAN(FD) interference signal shown in FIG. 2.

[0095] The embodiment of the present application provides a time compensation method of an interference test device, as shown in FIG. 3, and specifically comprises the following steps:

[0096] S301, acquiring a first delay time and a second delay time.

[0097] It should be noted that, during the conversion of the CAN(FD) message signal from the CAN bus to the CAN RX signal line through the PHY chip and the conversion of the interference signal from the CAN TX signal line to the CAN bus through the PHY chip, there is a signal conversion delay time. Therefore, in order to compensate for the signal conversion delay time when the interference signal is applied to the CAN bus subsequently, the delay time needs to be obtained. Therefore, in the embodiment of the present application, a high-precision oscilloscope is used to analyze the current acquisition signal to determine the delay time (nanosecond-level error) of the current acquisition signal converted from the CAN bus to the CAN RX signal line through the PHY chip, that is, the first delay time, and the delay time (picosecond-level error) of the CAN TX signal line converted to the CAN bus through the PHY chip, that is, the second delay time.

[0098] S302, decomposing the first delay time and the second delay time to obtain a nanosecond-level delay time corresponding to the first delay time and a picosecond-level delay time corresponding to the second delay time.

[0099] It should be noted that, after the first delay time and the second delay time are obtained by using the high-precision oscilloscope, the two delay times are transmitted to the USB data analysis module in the PS end of the ZYNQ chip through the USB protocol by the upper computer interface program for decomposition.

[0100] Specifically, the first delay time is decomposed by the FPGA basic logic inside the system, so that the nanosecond delay time corresponding to the first delay time is obtained, and then the second delay time is decomposed by the FPGA primitive logic inside the system, so that the picosecond delay time corresponding to the second delay time is obtained.

[0101] S303, the nanosecond delay time is precompensated by the configurable precompensation and output module to obtain the nanosecond precompensation time.

[0102] The configurable precompensation and output module is composed of preset logic code.

[0103] Specifically, the nanosecond delay time is precompensated by the FPGA internal self-defined logic in the configurable precompensation and output module, so that the nanosecond precompensation time is obtained, that is, the nanosecond precompensation time obtained by the system clock inside the FPGA.

[0104] Optionally, in another embodiment of the present application, a specific implementation of step S303 includes the following steps as shown in FIG. 4.

[0105] S401, the frequency of the system clock and the position of the current time on the CAN bus are obtained.

[0106] It should be noted that in order for the configurable precompensation and output module to accurately output the nanosecond precompensation time, the frequency of the system clock and the position of the current time on the CAN bus need to be obtained in advance, so that the configurable precompensation and output module can output the nanosecond precompensation time according to the frequency and the position. Specifically, on the Windows platform, the QueryPerformanceFrequency function can be used to obtain the frequency of the system clock. On the Linux platform, you can use the clock_getres function to obtain the frequency of the system clock, or use a programming language to obtain it. Optionally, the embodiment of the present application is not limited to the means of obtaining the frequency of the system clock, and can be set according to the requirements. And the position of the current time on the CAN bus can be encapsulated as a CAN message by using a suitable CAN bus communication library or driver, and sent out through the CAN bus, so that the position of the current time on the CAN bus can be obtained.

[0107] S402, the nanosecond delay time is precompensated by the configurable precompensation and output module according to the frequency and the position, so that the nanosecond precompensation time is obtained.

[0108] Specifically, the nanosecond delay time is tapped at the nanosecond level according to the frequency and the position by calling the FPGA internal system clock through the configurable advance compensation and the output module, and the nanosecond advance compensation time is obtained.

[0109] In S304, the picosecond delay time is compensated by the delay compensation module to obtain the picosecond delay compensation time, and the sum of the nanosecond advance compensation time and the picosecond delay compensation time is calculated to obtain the picosecond advance compensation time.

[0110] The delay compensation module is composed of a plurality of time sequence controllers connected in cascade, and the picosecond delay time is adjusted by the plurality of time sequence controllers.

[0111] It should be emphasized that the structure diagram of the delay compensation module is shown in FIG. 5, and specifically, the delay compensation module shown in FIG. 5 is constructed by the plurality of ODELAYE3, IDELAYE3 and IDELAYCTRL, wherein the CASC_OUT interface of the IDELAYE3 and the ODELAYE3 is connected with the CASC_IN interface of the next stage, and the DATAOUT interface is connected with the CASC_RETURN interface of the previous stage, so that the multi-stage cascade is formed by the connection mode, and the FPGA internal high-speed signal link is constructed, and the final delay chain is formed. In the multi-stage cascade delay chain, the attribute of the first-stage ODELAYE3 unit is MASTER, which is used to control the final delay signal output, the attributes of the IDELAYE3 and the ODELAYE3 units in the middle of the delay chain are SLAVE_MIDDLE, and the attributes of the IDELAYE3 or the ODELAYE3 unit at the end of the delay chain are SLAVE_END. The FPGA internal high-speed delay link is constructed by the above units, and a larger adjustable delay range is provided for the first-stage ODELAYE3 unit, so that the picosecond resolution delay compensation time can be obtained by compensating the picosecond delay time by the delay compensation module.

[0112] It should be noted that when the interference signal is applied to the CAN bus subsequently, in order to apply the interference signal at a proper time to achieve a specific test, safety evaluation or attack detection purpose. Therefore, the proper time is calculated to apply the interference signal to the CAN bus in advance, so that the picosecond advance compensation time is obtained by combining the nanosecond advance compensation time and the picosecond delay compensation time through the delay compensation module, so that the picosecond resolution time compensation scheme on the CAN(FD) interference test equipment is finally realized.

[0113] Optionally, in another embodiment of the present application, a specific implementation of step S304 is shown in FIG. 6, which includes the following steps.

[0114] S601, obtain the system clock, the nanosecond level advance compensation time and the user configurable delay parameter.

[0115] It can be understood that the user configurable delay parameter is used to calculate the picosecond level delay value subsequently, so that the picosecond level delay time is known by the delay value subsequently.

[0116] Optionally, the system clock can be obtained by using the API function provided by the operating system or the third party library, and the configuration interface can be provided to the user for setting the delay parameter. These parameters can include the delay time that needs to be compensated, the compensation strategy (such as static compensation or dynamic compensation), the source of the compensation value (such as user input or sensor measurement), the unit of the compensation value (such as nanosecond, microsecond, etc.), etc.

[0117] S602, the delay tap number distribution module in the delay compensation module calculates the picosecond level delay value by using the user configurable delay parameter.

[0118] It can be understood that the delay tap number distribution module in the delay compensation module can design the delay compensation algorithm according to the user configurable delay parameter, to ensure that the delay compensation can be performed at the picosecond level. Then the delay value calculated according to the delay compensation algorithm.

[0119] The specific delay compensation algorithm can be:

[0120] Input parameter: user configurable delay parameter

[0121] User set delay time (unit: picosecond)

[0122] Delay compensation strategy (static or dynamic)

[0123] Source of delay value (such as user input, sensor measurement, etc.)

[0124] Static delay compensation:

[0125] If the delay compensation strategy is static, the user set delay time is directly used as the delay compensation value.

[0126] Dynamic delay compensation:

[0127] If the delay compensation strategy is dynamic, the delay value is obtained in real time according to the source of the delay value, and is converted into the picosecond level delay value.

[0128] The delay value measured by the sensor or other real time data can be used to calculate the dynamic delay compensation value.

[0129] Picosecond level delay value calculation:

[0130] Add the user-set delay time to the static or dynamic delay compensation value to obtain the final picosecond-level delay value.

[0131] Output: the picosecond-level delay value.

[0132] It should be noted that this is only an example of a delay compensation algorithm.

[0133] S603, adjust the picosecond-level delay time by picoseconds according to the system clock, the nanosecond-level advance compensation time, and the picosecond-level delay value through each timing controller in the delay compensation module to obtain the picosecond-level delay compensation time.

[0134] It can be understood that each timing controller is configured to receive the system clock signal, the picosecond-level delay value, and the nanosecond-level advance compensation time, and adjust the delay in each timing controller according to the received system clock signal, the picosecond-level delay value, and the nanosecond-level advance compensation time to achieve picosecond-level delay compensation for the picosecond-level delay time.

[0135] Specifically, the picosecond-level delay compensation time is achieved through hardware in the delay compensation module and the wiring layout of each timing controller.

[0136] S305, based on the picosecond-level advance compensation time, apply the interference signal on the CAN bus.

[0137] Specifically, since the interference signal needs to be applied on the CAN bus in advance by a certain time to offset a subsequent delay compensation time inside the CAN bus and to ensure the accuracy of applying the interference signal to a certain extent, the interference signal with the delay compensation time is applied on the CAN bus based on the advance time, so as to achieve picosecond-level advance compensation of the interference signal.

[0138] For example, the system wants to apply the interference signal at the ACK SLOT position on the CAN bus. However, since there is a certain nanosecond-level delay time and picosecond-level delay time (for example, the delay time is 65.15 nanoseconds) when the CAN PHY is in signal conversion or transistor action. Therefore, in order to ensure the accuracy of applying the interference signal, it is necessary to apply the interference signal in advance by a certain time. At this time, the nanosecond-level advance compensation time and the picosecond-level delay compensation time can be added to obtain 65.15 nanoseconds (picosecond-level advance compensation time). At this time, the system needs to apply the interference signal on the CAN TX signal line in advance by 65.15 nanoseconds. At this time, the interference signal can be applied to the start position of the ACK SLOT on the CAN bus after conversion by the CAN PHY.

[0139] It should be noted that the interference signal applied to the CAN bus is applied according to the required level of the CAN bus, so the interference signal can be high and low.

[0140] Optionally, after the interference signal is applied to the CAN bus, the CAN bus itself generates a delay compensation time according to the level value corresponding to the interference signal, so after step S305 is performed, in another embodiment of the application, a method for determining the delay compensation time is provided, which specifically includes the following steps:

[0141] When the interference signal is high, the delay compensation time of the CAN bus is determined as the opening time of the transistor switch.

[0142] It should be noted that when the applied interference signal is high, the transistor inside the CAN bus will first be turned on, and at this time the opening time of the transistor switch is the delay compensation time of the CAN bus, and the picosecond level advance compensation time is used to offset the opening time of the transistor switch, so as to ensure the accuracy of the applied interference signal, so at this time the high level interference signal is applied to the high speed transistor in the CAN bus.

[0143] When the interference signal is low, the delay compensation time of the CAN bus is determined as the total delay time.

[0144] The total delay time refers to the sum of the delay time from the CAN PHY bus to the CAN RX signal line and the delay time from the CAN TX signal line to the CAN PHY bus.

[0145] It should be noted that when the interference signal is low, the delay time from the CAN PHY bus to the CAN RX signal line and the delay time from the CAN TX signal line to the CAN PHY bus need to be considered to ensure that the interference signal can interfere with the CAN(FD) waveform being transmitted on the CAN bus at the appropriate time, so that an error frame is generated. Therefore, when the interference signal is low, the delay compensation time of the CAN bus is the sum of the delay time from the CAN PHY bus to the CAN RX signal line and the delay time from the CAN TX signal line to the CAN PHY bus, at this time the low level interference signal is applied to the CAN TX signal line, and then the interference signal applied to the CAN TX signal line is converted to the interference signal applied to the CAN bus by the CAN PHY chip.

[0146] Optionally, in order to ensure the time compensation accuracy of the overall system, the picosecond level delay compensation time generated by the delay compensation module needs to be calibrated, so in another embodiment of the application, a calibration method for the delay compensation time is provided, as shown in FIG. 7, which specifically includes the following steps:

[0147] S701, obtain picosecond-level delay compensation time.

[0148] S702, according to a preset threshold, divide the picosecond-level delay compensation time into equal parts to obtain a plurality of segmented delay times, and distribute the plurality of segmented delay times to a plurality of timing controllers.

[0149] Specifically, in order to achieve more precise interference delay control in the system, so that the system is more flexible when performing delay compensation, and can adjust the delay time in smaller steps, thereby more accurately controlling the arrival time of the interference signal, therefore, in the embodiment of the application, the segmented time is used, the picosecond-level delay compensation time is divided into n equal parts according to the preset threshold n, each part has a fixed delay (1000 / (nf)) ps, thereby ensuring the time compensation accuracy of the overall system.

[0150] For example, assuming that the nanosecond-level delay time is 65.15 nanoseconds, since the clock frequency used by the FPGA is 160MHz, 65.15 nanoseconds corresponds to a time of 6.25 nanoseconds. First, the configurable advance compensation and output module in the FPGA can realize the advance compensation time in multiples of 6.25 nanoseconds. In this example, the advance compensation time in multiples of 6.25 nanoseconds is 68.75 nanoseconds of advance compensation time (since the delay compensation module can only generate delay compensation, it cannot generate advance compensation, so the advance compensation time provided by the configurable advance compensation and output module must be greater than the actual required compensation time). At this time, 68.75-65.15 nanoseconds=3.6 nanoseconds of delay needs to be generated by the delay compensation module. At this time, the portion of the delay time divided into n parts in the multi-stage cascaded unit of IDELAYE3 and ODELAYE3 in the delay compensation module needs to be adjusted to find the value closest to 3.6 nanoseconds of delay, thereby finally realizing the picosecond-level delay compensation time.

[0151] Optionally, in order to ensure that the delay time output by each timing controller in the delay compensation module is the same under different environments, the temperature and voltage need to be processed. Therefore, in another embodiment of the application, a temperature and voltage processing method is provided, as shown in FIG. 8, which specifically includes the following steps:

[0152] S801, obtain the tap number corresponding to the temperature and voltage and the picosecond-level delay compensation time.

[0153] It can be understood that, in order to dynamically adjust each timing controller in the delay compensation module according to the temperature and voltage changes under the current environmental conditions, so as to maintain the stability and performance of the system, it is necessary to obtain the tap number corresponding to the temperature and voltage and the picosecond-level delay compensation time in advance.

[0154] S802, calibrate the temperature voltage by using the IDelayCtrl unit in the delay compensation module.

[0155] Specifically, since the changes of temperature and voltage may affect the working speed and performance of the chip, and further affect the accuracy of the delay unit, it is necessary to calibrate the temperature voltage by using the IDelayCtrl unit in the delay compensation module to ensure that the system can maintain stable delay precision.

[0156] S803, based on the calibrated temperature voltage, adjust the number of taps corresponding to the picosecond level delay compensation time to make the delay time of all timing controller units in the delay compensation module the same.

[0157] Specifically, according to the calibrated temperature voltage, the number of taps required for picosecond level delay compensation time is determined, and then according to the determined number of taps, the number of taps corresponding to the picosecond level delay compensation time generated by each timing controller is adjusted to achieve the required picosecond level delay compensation time, so as to ensure that the picosecond level delay compensation time generated by each timing controller is the same.

[0158] Optionally, in addition to being able to apply interference signals in advance on the CAN bus based on the picosecond level advance compensation time, it is also possible to find a precise interference position on the CAN bus to apply interference signals. Therefore, in another embodiment of the present application, a method for applying interference signals is provided, as shown in Figure 9, which specifically includes the following steps:

[0159] S901, obtain the bus parameters on the CAN bus.

[0160] It should be noted that in order to subsequently apply interference signals at the CAN(FD) sampling point measurement process in the position of the collected signal, thereby reducing the measurement error of the CAN(FD) sampling point, it is necessary to obtain the bus parameters on the CAN bus from the host computer through the USB protocol, so that the bus parameters of the CAN(FD) can provide higher bandwidth, flexibility, real-time and reliability, thereby enabling subsequent effective acquisition of the current collected signal on the CAN bus at the current time.

[0161] S902, based on the bus parameters, obtain the current collected signal on the CAN bus at the current time.

[0162] Specifically, first, the CAN interface device is connected to the CAN bus to be monitored. The CAN interface device can be a CAN(FD) interface card, a USB-to-CAN adapter or a CAN interface module on an embedded system, then the CAN interface device is initialized using the corresponding programming library or driver, then the logic of collecting the CAN bus is set in the program to read the collected signal from the CAN bus, and finally the current collection signal at the current time is collected from the CAN bus based on the bus parameters.

[0163] Optionally, in another embodiment of the application, a specific implementation of step S902 includes the following steps as shown in FIG. 10.

[0164] S1001, extracting the baud rate and sampling point of the CAN bus from the bus parameters.

[0165] It can be understood that the bus parameters contain data in the CAN bus, but not all data can be used to collect data on the CAN bus, so in order to collect data on the CAN bus flexibly and quickly subsequently, it is necessary to extract the parameters that are beneficial to the collection signal from the bus parameters in advance, that is, the baud rate and sampling point of the CAN bus.

[0166] S1002, finding the CAN(FD) communication basic parameters corresponding to the baud rate and sampling point from the preset table.

[0167] It should be noted that in the CAN protocol, the required parameters in the CAN protocol are recorded by constructing a table, that is, the CAN(FD) communication basic parameters. Since there is a specific relationship between the baud rate, the sampling point and the interference parameters, the corresponding CAN(FD) communication basic parameters can be found from the table through the baud rate and the sampling point, so that the current collection signal at the current time can be collected from the CAN bus based on the CAN(FD) communication basic parameters subsequently. The CAN(FD) communication basic parameters can include TSEG1, TSEG2 and SJW. According to the CAN protocol, TSEG1 represents the time of the synchronization segment, TSEG2 represents the time of the post segment, and SJW represents the re-synchronization jump width.

[0168] S1003, obtaining the current collection signal at the current time from the CAN bus according to the CAN(FD) communication basic parameters.

[0169] Specifically, the current collection signal at the current time is obtained from the CAN bus based on TSEG1, TSEG2 and SJW.

[0170] S903, analyzing the current collection signal to obtain the interference position of the current collection signal on the CAN RX signal line.

[0171] Specifically, since the current acquisition signal contains a lot of data on the CAN(FD) bus, such as IP address, port, position of the signal on the bus, etc., it is necessary to analyze the CAN(FD) message in which the current acquisition signal is located at the current time from the current acquisition signal through the CAN(FD) real-time state analysis module, which CAN(FD) bit, the first clock slice under the current bit, and the soft synchronization compensation width, so that the interference position of the current acquisition signal on the CAN RX signal line at the current time can be obtained.

[0172] S904, according to the interference position, a target interference signal is applied on the CAN bus.

[0173] Specifically, first, the interference position of the target interference signal is located on the CAN bus, and then the picosecond resolution target interference signal is sent to the CAN bus through the delay compensation module, so that the target interference signal is applied on the CAN bus at the interference position, so that the delay time compensation of picosecond resolution can be realized through the cascade mode of the delay compensation module, and the interference signal applied on the CAN bus at the interference position can also achieve the precision of picosecond resolution.

[0174] It should be noted that the target interference signal can be high or low, and specific explanations can be referred to the specific embodiments of the above-mentioned method for determining the delay compensation time, which will not be repeated here.

[0175] The time compensation method of the interference test equipment provided by the application obtains the first delay time and the second delay time, then decomposes the first delay time and the second delay time to obtain the nanosecond delay time corresponding to the first delay time and the picosecond delay time corresponding to the second delay time, then performs lead compensation on the nanosecond delay time through the configurable lead compensation and output module to obtain the nanosecond lead compensation time, then performs lag compensation on the picosecond delay time through the delay compensation module to obtain the picosecond delay compensation time, and calculates the sum of the nanosecond lead compensation time and the picosecond delay compensation time to obtain the picosecond lead compensation time. The delay compensation module is composed of a plurality of time sequence controllers connected in cascade. Finally, the interference signal is applied on the CAN bus based on the picosecond lead compensation time. Thus, through the cascade mode of the plurality of time sequence controllers in the delay compensation module, the delay compensation time of picosecond level is realized, and thus the interference signal applied on the CAN bus can achieve the precision of picosecond resolution.

[0176] Another embodiment of the present application provides a time compensation system of an interference test device, as shown in Fig. 11, the time compensation system comprises: a user configuration parameter analysis module 1101, a configurable advance compensation and output module 1102, and a delay compensation module 1103.

[0177] The user configuration parameter analysis module 1101 is configured to obtain the first delay time and the second delay time, and to decompose the first delay time and the second delay time to obtain a nanosecond delay time corresponding to the first delay time and a picosecond delay time corresponding to the second delay time.

[0178] The configurable advance compensation and output module 1102 is configured to advance compensate the nanosecond delay time to obtain a nanosecond advance compensation time. The configurable advance compensation and output module is composed of preset logic codes.

[0179] The delay compensation module 1103 is configured to lag compensate the picosecond delay time to obtain a picosecond delay compensation time, to calculate the sum of the nanosecond advance compensation time and the picosecond delay compensation time to obtain a picosecond advance compensation time, and to impose an interference signal on the CAN bus based on the picosecond advance compensation time. The delay compensation module is composed of a plurality of time sequence controllers connected in cascade, and the plurality of time sequence controllers are used to adjust the delay of the picosecond delay time.

[0180] It should be noted that the specific working processes of the above modules in the embodiments of the present application can be correspondingly referred to steps S301-S305 in the above method embodiments, which will not be described here.

[0181] Optionally, another embodiment of the present application provides a time compensation system of an interference test device, which is further configured to:

[0182] The user configuration parameter analysis module is configured to obtain bus parameters on the CAN bus, and to obtain a current acquisition signal on the CAN bus at the current moment based on the bus parameters.

[0183] The analysis module is configured to analyze the current acquisition signal to obtain an interference position of the current acquisition signal on a CAN RX signal line.

[0184] The delay compensation module is configured to impose a target interference signal on the CAN bus according to the interference position.

[0185] Optionally, in the time compensation system of the interference test device provided by another embodiment of the present application, the user configuration parameter analysis module is configured to obtain the current acquisition signal on the CAN bus at the current moment based on the bus parameters, and specifically configured to:

[0186] Extract the baud rate and the sampling point of the CAN bus from the bus parameters.

[0187] Look up the CAN(FD) communication basic parameters corresponding to the baud rate and the sampling point from the preset table.

[0188] According to the CAN(FD) communication basic parameters, obtain the current acquisition signal at the current time from the CAN bus.

[0189] Optionally, another embodiment of the present application provides a time compensation system of an interference test device, and further used for:

[0190] The delay compensation module is configured to determine the delay compensation time of the CAN bus as the turn-on time of the transistor switch when the interference signal is at a high level.

[0191] The delay compensation module is configured to determine the delay compensation time of the CAN bus as the total delay time when the interference signal is at a low level, wherein the total delay time refers to the sum of the delay time from the CAN PHY bus to the CAN RX signal line and the delay time from the CAN TX signal line to the CAN PHY bus.

[0192] Optionally, another embodiment of the present application provides a time compensation system of an interference test device, and further used for:

[0193] The delay compensation module is configured to obtain the picosecond-level delay compensation time, and to divide the picosecond-level delay compensation time into multiple segmented delay times according to a preset threshold, and to send the multiple segmented delay times to the multiple time sequence controllers.

[0194] Optionally, another embodiment of the present application provides a time compensation system of an interference test device, and further used for:

[0195] The delay compensation module is configured to obtain the tap number corresponding to the temperature voltage and the picosecond-level delay compensation time, and to calibrate the temperature voltage by using the IDelayCtrl unit in the delay compensation module, and to adjust the tap number corresponding to the picosecond-level delay compensation time based on the calibrated temperature voltage, so that the delay times of all the time sequence controller units in the delay compensation module are the same.

[0196] Optionally, another embodiment of the present application provides a time compensation system of an interference test device, and the nanosecond-level delay time is forward compensated by the configurable forward compensation and output module to obtain the nanosecond-level forward compensation time, and specifically used for:

[0197] Obtain the frequency of the system clock and the position on the CAN bus at the current time.

[0198] The nanosecond-level delay time is tapped at the nanosecond level by the configurable leading compensation and the output module according to the frequency and the position, and the nanosecond-level leading compensation time is obtained.

[0199] Optionally, another embodiment of the present application provides a time compensation system of an interference test device, wherein the picosecond-level delay time is compensated by the delay compensation module to obtain the picosecond-level delay compensation time, and the time compensation system is specifically used for:

[0200] The system clock, the nanosecond-level leading compensation time and the user-configurable delay parameter are obtained.

[0201] The picosecond-level delay value is calculated by the delay tap number distribution module in the delay compensation module using the user-configurable delay parameter.

[0202] The picosecond-level delay time is adjusted by each timing controller in the delay compensation module according to the system clock, the nanosecond-level leading compensation time and the picosecond-level delay value to obtain the picosecond-level delay compensation time.

[0203] It should be noted that the specific working processes of the various modules provided in the above embodiments of the present application can be correspondingly referred to the corresponding steps in the above method embodiments, which will not be described here.

[0204] Each of the embodiments in the specification is described in a progressive manner, and the same or similar parts between the embodiments can be referred to each other, and each embodiment mainly describes the difference from other embodiments. Especially, for the system or system embodiment, since it is basically similar to the method embodiment, it is described more simply, and the related parts can be referred to the part of the method embodiment. The above-described system and system embodiment are only illustrative, wherein the units described as separate components can be or can not be physically separated, and the components displayed as units can be or can not be physical units, that is, they can be located in one place, or can be distributed on multiple network units. According to the actual needs, part or all of the modules can be selected to achieve the purpose of the embodiment scheme. Those skilled in the art can understand and implement without creative labor.

[0205] Those skilled in the art will further realize that the mechanisms of the various examples described herein are capable of being implemented using any number of combinations of the described features. Accordingly, these examples are not limited to the mechanisms described herein, but rather, the intent is to cover all modifications and alternatives equivalent thereto. The preceding description of the examples is illustrative, and not restrictive. Many other examples will be apparent to those of skill in the art upon reviewing the above description. The scope of the examples should, therefore, be determined not with reference to the above description, but instead should be given to the appended claims, along with their full scope of equivalents.

[0206] The above description of disclosed examples is intended to be illustrative, and not restrictive. Many other examples will be apparent to those of skill in the art upon reviewing the above description. The scope of the examples should, therefore, be determined not with reference to the above description, but instead should be given to the appended claims, along with their full scope of equivalents.

Claims

1. A time compensation method for an interference test device, characterized in that, The method comprises the following steps: acquiring a first delay time and a second delay time; decomposing the first delay time and the second delay time to obtain a nanosecond-level delay time corresponding to the first delay time and a picosecond-level delay time corresponding to the second delay time; performing lead compensation on the nanosecond-level delay time through a configurable lead compensation and output module to obtain a nanosecond-level lead compensation time; wherein the configurable lead compensation and output module is composed of preset logic codes; performing lag compensation on the picosecond-level delay time through a delay compensation module to obtain a picosecond-level delay compensation time, and calculating the sum of the nanosecond-level lead compensation time and the picosecond-level delay compensation time to obtain a picosecond-level lead compensation time; wherein the delay compensation module is composed of a plurality of time sequence controllers connected in cascade, and the plurality of time sequence controllers are used to adjust the delay time of the picosecond-level delay time; applying an interference signal to the CAN bus based on the picosecond-level lead compensation time.

2. The method of claim 1, wherein, Further comprising: acquiring a bus parameter on the CAN bus; based on the bus parameter, acquiring a current acquisition signal on the CAN bus at the current time; analyzing the current acquisition signal to obtain an interference position of the current acquisition signal on the CAN RX signal line; applying a target interference signal to the CAN bus according to the interference position.

3. The method of claim 2, wherein, The method comprises the following steps: extracting the baud rate and the sampling point of the CAN bus from the bus parameter; finding the CAN(FD) communication basic parameter corresponding to the baud rate and the sampling point from a preset table; acquiring the current acquisition signal at the current time from the CAN bus according to the CAN(FD) communication basic parameter.

4. The method according to any one of claims 1 to 3, characterized in that, After applying the interference signal to the CAN bus based on the picosecond-level lead compensation time, the method further comprises the following steps: when the interference signal is high, determining the delay compensation time of the CAN bus as the turn-on time of the transistor switch; when the interference signal is low, determining the delay compensation time of the CAN bus as the total delay time; wherein the total delay time refers to the sum of the delay time from the CAN PHY bus to the CAN RX signal line and the delay time from the CAN TX signal line to the CAN PHY bus.

5. The method of claim 1, wherein, Further comprising: acquiring the picosecond-level delay compensation time; dividing the picosecond-level delay compensation time into equal parts according to a preset threshold to obtain a plurality of divided delay times, and distributing the plurality of divided delay times to a plurality of time sequence controllers.

6. The method of claim 1, wherein, Further comprising: acquiring a temperature voltage and a tap number corresponding to the picosecond-level delay compensation time; calibrating the temperature voltage by using an IDelayCtrl unit in the delay compensation module; based on the calibrated temperature voltage, adjusting the tap number corresponding to the picosecond-level delay compensation time so that the delay times of all time sequence controller units in the delay compensation module are the same.

7. The method of claim 1, wherein, The nanosecond-level delay time is precompensated by the configurable precompensation and output module to obtain a nanosecond-level precompensation time, including: The frequency of a system clock and a position of a current time on the CAN bus are acquired; The nanosecond-level delay time is precompensated by the configurable precompensation and output module according to the frequency and the position to obtain a nanosecond-level precompensation time.

8. The method according to claim 1 or 7, characterized in that, The picosecond-level delay time is lag-compensated by the delay compensation module to obtain a picosecond-level delay compensation time, including: The system clock, the nanosecond-level precompensation time and a user-configurable delay parameter are acquired; The picosecond-level delay value is calculated by a delay tap number distribution module in the delay compensation module using the user-configurable delay parameter; The picosecond-level delay time is adjusted by each timing controller in the delay compensation module according to the system clock, the nanosecond-level precompensation time and the picosecond-level delay value to obtain a picosecond-level delay compensation time.

9. A time compensation system for an interference test apparatus, characterized by The time compensation system includes a user configuration parameter analysis module, a configurable precompensation and output module and a delay compensation module; The user configuration parameter analysis module is configured to acquire a first delay time and a second delay time, and to decompose the first delay time and the second delay time to obtain a nanosecond-level delay time corresponding to the first delay time and a picosecond-level delay time corresponding to the second delay time; The configurable precompensation and output module is configured to precompensate the nanosecond-level delay time to obtain a nanosecond-level precompensation time, wherein the configurable precompensation and output module is composed of preset logic code; The delay compensation module is configured to lag-compensate the picosecond-level delay time to obtain a picosecond-level delay compensation time, to calculate a sum of the nanosecond-level precompensation time and the picosecond-level delay compensation time to obtain a picosecond-level precompensation time, and to apply the interference signal on the CAN bus based on the picosecond-level precompensation time, wherein the delay compensation module is composed of a plurality of timing controllers connected in cascade, and the picosecond-level delay time is adjusted by the plurality of timing controllers.

10. The system of claim 9, wherein, The user configuration parameter analysis module is configured to acquire a bus parameter on the CAN bus, and to acquire a current acquisition signal on the CAN bus at a current time based on the bus parameter; The analysis module is configured to analyze the current acquisition signal to obtain an interference position of the current acquisition signal on a CAN RX signal line; The delay compensation module is configured to apply a target interference signal on the CAN bus according to the interference position. ​

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