Array substrate, display panel and display apparatus

Abstract

An array substrate, a display panel and a display apparatus, which are used for alleviating the problem in the prior art whereby reducing the number of COFs of a display panel also leads to a decrease in the resolution of the display panel. The array substrate comprises a base, a plurality of pixel electrode groups (1) located on one side of the base, a plurality of gate line groups (2) extending in a first direction (X), a plurality of data lines (3) extending in a second direction (Y), and a plurality of transistors (T), wherein the pixel electrode groups (1) are located in a region formed by means of the intersection of the gate line groups (2) and the data lines (3), and each gate line group (2) comprises two gate lines (20) extending in the first direction (X); and each pixel electrode group (1) comprises two pixel electrodes (10), two pixel electrodes (10) of the same pixel electrode group (1) are electrically connected to the same data line (3) by means of different transistors (T), and the length of the pixel electrodes (10) in the first direction (X) is greater than the length thereof in the second direction (Y).

Description

Array substrate, display panel and display device

[0001] Cross Reference to Related Applications

[0002] This application claims priority to the Chinese patent application No. 202410623113.0, filed on May 20, 2024, and entitled "Array substrate, display panel and display device", the entire content of which is incorporated herein by reference. TECHNICAL FIELD

[0003] The present application relates to the technical field of display, in particular to an array substrate, a display panel and a display device. BACKGROUND

[0004] With the continuous development of display technology, liquid crystal display has occupied a dominant position in the display industry. The display product using the Advanced Super Dimension Switch (ADS) structure has become the mainstream display mode due to its wide viewing angle, fast response speed and high contrast ratio.

[0005] SUMMARY

[0006] The present application provides an array substrate, a display panel and a display device. The array substrate comprises a substrate, a plurality of pixel electrode groups on one side of the substrate, a plurality of gate lines extending along a first direction, a plurality of data lines extending along a second direction, and a plurality of transistors; wherein the pixel electrode groups are located in the regions formed by the intersection of the gate lines and the data lines, and the gate lines comprise two gate lines extending along the first direction.

[0007] The pixel electrode group comprises two pixel electrodes, and the two pixel electrodes of the same pixel electrode group are electrically connected to the same data line through different transistors, and the length of the pixel electrode in the first direction is greater than the length in the second direction.

[0008] In a possible implementation, the two pixel electrodes of the pixel electrode group are a first pixel electrode and a second pixel electrode, and the second pixel electrode is located on the side of the first pixel electrode away from the data line to which the first pixel electrode is electrically connected; and the first pixel electrode and the second pixel electrode are alternately arranged in the same pixel electrode row.

[0009] The array substrate comprises a plurality of pixel electrode columns extending along the second direction and arranged along the first direction; and the first pixel electrode and the second pixel electrode are alternately arranged in the same pixel electrode column.

[0010] In a possible implementation, the array substrate comprises: a plurality of pixel electrode rows extending along the first direction and arranged along the second direction; the pixel electrode row comprises a plurality of pixel electrodes;

[0011] The light emitted from the same pixel electrode row has the same color.

[0012] In a possible implementation, the layer where the gate line is located further comprises: a first connecting part extending along the first direction; the first connecting part is in direct contact with the second pixel electrode and is electrically connected to the second pixel electrode through the first connecting part.

[0013] In a possible implementation, the first connecting part comprises: a first sub-connecting part extending along the first direction, and a second sub-connecting part connected to one end of the first sub-connecting part; the width of the second sub-connecting part in the second direction is greater than the width of the first sub-connecting part in the second direction.

[0014] The first sub-connecting part is in direct contact with the second pixel electrode and is electrically connected to the second pixel electrode; the second sub-connecting part overlaps the transistor in the orthographic projection of the substrate.

[0015] In a possible implementation, the line width of the first sub-connecting part in the second direction is less than the minimum distance between the first connecting part and the gate line.

[0016] In a possible implementation, the first pixel electrode has a first outer edge along the first direction and close to one side of the first connecting part, and the second pixel electrode has a second outer edge along the first direction and close to one side of the first connecting part.

[0017] The extension line of the second outer edge in the orthographic projection of the substrate is located in the area between the first outer edge in the orthographic projection of the substrate and the first connecting part in the orthographic projection of the substrate.

[0018] In a possible implementation, the array substrate comprises a first data line and a second data line adjacent to the pixel electrode group; the pixel electrodes of the pixel electrode group are electrically connected to the first data line through different transistors; the second pixel electrode is located on the side of the first pixel electrode away from the first data line.

[0019] The minimum distance between the second pixel electrode and the second data line in the first direction is greater than the minimum distance between the first pixel electrode and the first data line in the first direction.

[0020] In a possible implementation, the first pixel electrode has a first outer protrusion on a side facing the first data line, and the second pixel electrode has a second outer protrusion on a side facing the second data line.

[0021] A length of the first outer protrusion along the first direction is greater than a length of the second outer protrusion along the first direction.

[0022] In a possible implementation, the array substrate further includes a plurality of common electrode strips extending along the first direction.

[0023] The common electrode strip includes a plurality of common electrode portions distributed along the first direction; the common electrode portion includes a first sub-common electrode portion, a second sub-common electrode portion on a side of the first sub-common electrode portion along the first direction, and a third sub-common electrode portion on another side of the first sub-common electrode portion along the first direction; a width of the second sub-common electrode portion and a width of the third sub-common electrode portion along the second direction are both less than a width of the first sub-common electrode portion along the first direction.

[0024] An overlapping area of the second sub-common electrode portion and the first pixel electrode in the substrate orthographic projection is greater than an overlapping area of the third sub-common electrode portion and the second pixel electrode in the substrate orthographic projection.

[0025] In a possible implementation, the common electrode strip further includes a common connection portion connecting adjacent common electrode portions along the first direction.

[0026] The common connection portion in the substrate orthographic projection overlaps the data line in the substrate orthographic projection, and a width of the common connection portion along the second direction is less than a width of the second sub-common electrode portion along the second direction and less than a width of the third sub-common electrode portion along the second direction.

[0027] In a possible implementation, the layer where the data line is located further includes a plurality of first common wires extending along the second direction; the array substrate further includes a second common wire in the same layer as the common electrode strip and extending along the second direction; the second common wire in the substrate orthographic projection overlaps the first common wire in the substrate orthographic projection.

[0028] The second common wire is electrically connected to the first common wire through a hole, so that adjacent common electrode strips along the second direction are electrically connected.

[0029] In a possible implementation, the transistor includes a first electrode and a second electrode; the first electrode is electrically connected to the data line.

[0030] The first electrode has a first branch extending along the first direction and a second branch extending along the first direction, and the second electrode extends along the first direction, and the second electrode is located in the area between the first branch and the second branch in the orthographic projection of the substrate.

[0031] In a possible implementation, the transistor comprises: a first electrode electrically connected to the data line; the first electrode comprises: a first electrode first part and a first electrode second part; the first electrode first part extends along the first direction, one end of which is electrically connected to the data line, and the other end is electrically connected to the first electrode second part;

[0032] The first electrode first part is located in the area between two gate lines of the same gate line group in the orthographic projection of the substrate; and the first electrode second part is located in the area between two pixel electrodes of the same pixel electrode group in the orthographic projection of the substrate.

[0033] In a possible implementation, the first electrode second part comprises: a first main part, a first branch connected to one end of the first main part and extending along the second direction, and a second branch connected to the other end of the first main part and extending along the second direction.

[0034] In a possible implementation, the maximum length of the first electrode in the first direction is greater than or equal to the maximum length of the pixel electrode in the first direction.

[0035] In a possible implementation, the data line comprises: a plurality of data line main parts and a plurality of data line connection parts, the data line main parts and the data line connection parts extend along the second direction and are alternately distributed along the second direction;

[0036] The data line main part is located in the area between two adjacent pixel electrodes in the orthographic projection of the substrate in the first direction; and the data line connection part overlaps with the gate line group in the orthographic projection of the substrate in the first direction.

[0037] The maximum length of the first electrode in the first direction is greater than the length of the data line main part in the second direction.

[0038] In a possible implementation, the width of the data line main part in the first direction is greater than the width of the data line connection part in the first direction.

[0039] In a possible implementation, the transistor further includes: a second electrode; the second electrode includes: a second electrode first part, and a second electrode second part; the second electrode first part extends along the second direction; the second electrode second part extends along the first direction and is connected to one end of the second electrode first part;

[0040] The pixel electrode includes: a pixel electrode main part, and a pixel electrode protruding part; the pixel electrode protruding part is located on a side of the pixel electrode main part away from the data line;

[0041] The second electrode first part is located in a region between the first branch part and the second branch part in the substrate projection; the second electrode second part overlaps the pixel electrode protruding part in the substrate projection and is electrically connected by perforation at the overlapping position.

[0042] In a possible implementation, the array substrate further includes: a plurality of common electrode strips extending along the first direction and arranged along the second direction, and a first trace arranged in the same layer as the pixel electrode and extending along the second direction;

[0043] At least part of the first trace in the substrate projection is located in a region between two pixel electrodes of the same pixel electrode group in the substrate projection; the common electrode strip is electrically connected by perforation at the overlapping position with the first trace.

[0044] In a possible implementation, the common electrode strip includes: a plurality of common electrode groups arranged along the first direction; the common electrode group overlaps the pixel electrode group in the substrate projection in the substrate projection; the common electrode group includes: a first sub-common electrode extending along the first direction and distributed along the first direction, a second sub-common electrode, a first lap joint connected to a side of the first sub-common electrode facing the second sub-common electrode, and a second lap joint connected to a side of the second sub-common electrode facing the first sub-common electrode;

[0045] The first trace includes: a first trace main part, a third lap joint connected to a side of the first trace main part, and a fourth lap joint connected to the other side of the first trace main part;

[0046] The first lap joint overlaps the third lap joint in the substrate projection and is electrically connected by perforation at the overlapping position; the second lap joint overlaps the fourth lap joint in the substrate projection and is electrically connected by perforation at the overlapping position.

[0047] In a possible implementation, the third overlap portion and the pixel electrode protrusion portion of the first pixel electrode are both on the same side of the first trace main portion in the substrate projection.

[0048] The fourth overlap portion and the pixel electrode protrusion portion of the second pixel electrode are both on the same side of the first trace main portion in the substrate projection.

[0049] In a possible implementation, the pixel electrode protrusion portion has a third outer edge extending along the first direction.

[0050] The third overlap portion and the fourth overlap portion are on different sides of the third outer edge in the substrate projection.

[0051] In a possible implementation, the common electrode strip further includes a first common connection portion, the first common connection portion overlaps the data line in the substrate projection, and the first common connection portion connects two adjacent common electrode groups in the first direction.

[0052] A maximum width of the first common connection portion in the second direction is less than a maximum width of the first sub-common electrode and / or the second sub-common electrode in the second direction.

[0053] In a possible implementation, the common electrode strip further includes a second common connection portion, the second common connection portion overlaps the first trace in the substrate projection, and the second common connection portion connects the first overlap portion and the second overlap portion in the common electrode group.

[0054] The second common connection portion extends along a third direction, and a maximum line width of the third common electrode portion perpendicular to the third direction is less than the maximum width of the first sub-common electrode and / or the second sub-common electrode in the second direction.

[0055] Embodiments of the present application further provide a display panel including the array substrate provided by the embodiments of the present application.

[0056] Embodiments of the present application further provide a display device including the display panel provided by the embodiments of the present application. BRIEF DESCRIPTION OF DRAWINGS

[0057] FIG. 1A is a schematic structural diagram of an array substrate provided by an embodiment of the present application;

[0058] Figure 1B is a schematic diagram of a single film layer of the pixel electrode layer in Figure 1A;

[0059] Figure 1C is a schematic diagram of a single film layer of the layer in which the gate lines are located in Figure 1A;

[0060] Figure 1D is a schematic diagram of a single film layer of the layer in which the data lines are located in Figure 1A;

[0061] Figure 1E is a schematic diagram of the stack of the pixel electrode layer and the layer in which the gate lines are located in Figure 1A;

[0062] Figure 2A is a schematic diagram of the structure of the array substrate after the common electrode layer is added according to an embodiment of the present application;

[0063] Figure 2B is a schematic diagram of a single film layer of the common electrode layer in Figure 2A;

[0064] Figure 3 is a schematic diagram of a larger range of array substrate according to an embodiment of the present application;

[0065] Figure 4 is a schematic diagram of a pixel architecture according to an embodiment of the present application;

[0066] Figure 5A is a schematic diagram of the structure of the array substrate according to an embodiment of the present application;

[0067] Figure 5B is a schematic diagram of a single film layer of the common electrode layer in Figure 5A;

[0068] Figure 5C is a schematic diagram of a single film layer of the gate lines in Figure 5A;

[0069] Figure 5D is a schematic diagram of a single film layer of the data lines in Figure 5A;

[0070] Figure 5E is a schematic diagram of a single film layer of the pixel electrode layer in Figure 5A;

[0071] Figure 5F is a schematic diagram of a single film layer of the black matrix in Figure 5A;

[0072] Figure 5G is a schematic diagram of a single film layer of the spacers in Figure 5A;

[0073] Figure 6A is a schematic diagram of a single film layer of the pixel electrode layer in Figure 6E;

[0074] Figure 6B is a schematic diagram of the layer in which the gate lines are located in Figure 6E;

[0075] Figure 6C is a schematic diagram of the layer in which the data lines are located in Figure 6E;

[0076] Figure 6D is a schematic diagram of the common electrode layer in Figure 6E;

[0077] Figure 6E is a schematic diagram of an array substrate according to an embodiment of the present application;

[0078] Figure 6F is a schematic diagram of a single film layer of the pixel electrode layer in Figure 6K;

[0079] FIG. 6G is a schematic view of the gate line layer in FIG. 6K;

[0080] FIG. 6H is a schematic view of the data line layer in FIG. 6K;

[0081] FIG. 6I is a schematic view of the common electrode layer in FIG. 6K;

[0082] FIG. 6J is a schematic view of the spacers in FIG. 6K;

[0083] FIG. 6K is a schematic view of another array substrate provided by embodiments of the present disclosure;

[0084] FIG. 7A is a pixel architecture diagram corresponding to FIG. 6A at frame inversion;

[0085] FIG. 7B is a pixel architecture diagram corresponding to FIG. 6A at 2dot inversion. DETAILED DESCRIPTION

[0086] In order to make the objectives, technical solutions, and advantages of the embodiments of the present disclosure clearer, the technical solutions of the embodiments of the present disclosure will be described clearly and completely below with reference to the drawings of the embodiments of the present disclosure. Obviously, the described embodiments are some, but not all, of the embodiments of the present disclosure. Based on the described embodiments of the present disclosure, all other embodiments obtained by those of ordinary skill in the art without creative effort belong within the scope of the present disclosure.

[0087] Unless otherwise defined, technical terms or scientific terms used in the present disclosure shall have the ordinary meanings as understood by those of ordinary skill in the art to which the present disclosure pertains. The terms "first", "second", and similar terms used in the present disclosure do not denote any order, quantity, or importance, but are used to distinguish different components. The terms "include", "contain", and similar terms mean that the elements or objects before the terms encompass the elements or objects listed after the terms and their equivalents, and do not exclude other elements or objects. The terms "connect" or "connected" and similar terms are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. The terms "upper", "lower", "left", "right", and the like are used only to represent relative positional relationships, and when the absolute positions of the described objects are changed, the relative positional relationships can also be changed accordingly.

[0088] As used herein, "about" or "approximately" includes the stated value and means within an acceptable range of deviation for a particular value as determined by one of ordinary skill in the art to which the discussion pertains and which relates to the error in measurement of the particular quantity (i.e., limitations of the measurement system). For example, "approximately" can mean that the difference with respect to the stated value is within one or more standard deviations, or within a range of ±30%, 20%, 10%, 5%.

[0089] In the drawings, the thicknesses of layers, films, panels, regions, etc., are exaggerated for clarity. Exemplary embodiments are described herein with reference to cross-sectional illustrations that are schematic illustrations of idealized embodiments. As such, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and / or tolerances, are to be expected. Thus, embodiments described herein are not to be construed as being limited to the particular shapes of regions as illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, an area illustrated or described as flat can typically have rough and / or nonlinear features. Moreover, sharp angles that are illustrated can be rounded. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the precise shape of a region and are not intended to limit the scope of the present claims.

[0090] In order to keep the following description of the embodiments of the present disclosure clear and concise, detailed descriptions of known functions and known components are omitted.

[0091] In recent years, TV products are constantly developing products with reduced costs while improving product specifications. For example, the pixel structure has undergone Single Gate → Dual Gate → Triple Gate technical evolution. Dual Gate display products can reduce the number of COFs by 1 / 2, and Triple Gate display products can reduce the number of COFs by 2 / 3. However, the current display panel reduces the number of COFs, which also reduces the resolution of the display panel.

[0092] Therefore, referring to FIGS. 1A-1E, 3, 4, 5A-5E, wherein FIG. 1B is a single film layer schematic diagram of the pixel electrode layer in FIG. 1A, FIG. 1C is a single film layer schematic diagram of the layer where the gate lines are located in FIG. 1A, FIG. 1D is a single film layer schematic diagram including the layer where the data lines are located in FIG. 1A, and FIG. 1E is a schematic diagram of the stack of the pixel electrode layer and the gate line layer in FIG. 1A, an array substrate is provided in the embodiments of the present application, comprising: a substrate, a plurality of pixel electrode groups 1 located on one side of the substrate, a plurality of gate line groups 2 extending along a first direction X, a plurality of data lines 3 extending along a second direction Y, and a plurality of transistors T; wherein the pixel electrode groups 1 are located in the area formed by the intersection of the gate line groups 2 and the data lines 3, the gate line groups 2 include two gate lines 20 extending along the first direction X; the two gate lines 20 of the same gate line group 2 can be located between two adjacent pixel electrode rows;

[0093] The pixel electrode group 1 includes two pixel electrodes 10, the two pixel electrodes 10 of the same pixel electrode group 1 are electrically connected to the same data line 3 through different transistors T, and the length a1 of the pixel electrode 10 in the first direction X is greater than the length a2 in the second direction Y. Specifically, in combination with FIG. 1A, the pixel electrode group 1 includes a first pixel electrode 11 and a second pixel electrode 12, the first pixel electrode 11 is electrically connected to the left data line 3 through the first transistor T1, and the second pixel electrode 12 is electrically connected to the left data line 3 through the second transistor T2.

[0094] In the embodiment of the present application, the length a1 of the pixel electrode 10 in the first direction X is greater than the length a2 in the second direction Y, the pixel electrode 10 adopts a horizontal placement mode, the two pixel electrodes 10 of the same pixel electrode group 1 are electrically connected to the same data line 3 through different transistors T, compared with the conventional single-gate structure display product, the number of flexible circuit boards COF (and / or control chips IC) driving the data line 3 can be greatly reduced without loss of resolution, for example, it can be 1 / 6 of the original, reducing production cost; moreover, the pixel architecture data line 3 can realize pixel-level 2dot flipping by frame flipping, that is, in combination with FIG. 4, for example, the periphery of two positive polarity sub-pixels is negative polarity sub-pixel, compared with the two-column positive polarity or two-column negative polarity sub-pixel distribution mode shown in FIG. 7A, the pixel architecture shown in FIG. 4 can make the panel brightness uniformity better; moreover, the conventional 2dot flipping mode needs to load positive polarity signals on two rows of sub-pixels on the same data line within one frame, and two rows of sub-pixels load negative polarity signals, while frame flipping is to load positive polarity signals or negative polarity signals on the same data line within one frame, frame flipping has the advantages of low power consumption and less heat of integrated circuit chip (IC) compared with 2dot flipping mode, and the embodiment of the present application can realize the effect of 2dot flipping by frame flipping, which can make the display panel have the advantages of low power consumption and less heat of integrated circuit chip (IC) under the condition of better display panel brightness uniformity.

[0095] In a possible implementation, referring to FIGS. 1A-1E and FIG. 4, the two pixel electrodes of the pixel electrode group 1 are respectively a first pixel electrode 11 and a second pixel electrode 12, the second pixel electrode 12 is located on a side of the first pixel electrode 11 away from the data line 3 to which the first pixel electrode 11 is electrically connected; the layer where the gate line 20 is located further includes: a first connecting part 4 extending along the first direction X; the first connecting part 4 is in direct contact with the second pixel electrode 12 and is electrically connected thereto, and the second pixel electrode 12 is electrically connected to the transistor T through the first connecting part 4. In the process of forming the array substrate, the pixel electrode layer can be formed first, and then the gate line 20 layer is formed. The pixel electrode layer and the gate line layer can be prepared using the same mask, and the pixel electrode 10 and the gate line 20 are spaced apart from each other to achieve mutual insulation. The first connecting part 4 of the gate line 20 layer can be overlapped with the second pixel electrode 12 to achieve electrical connection between the first connecting part 4 and the second pixel electrode 12. The first connecting part 4 can serve as part of the second electrode TB of the transistor electrically connected to the second pixel electrode 12. The second electrode TB of the transistor made of the gate line 20 layer can reduce the wiring resistance (relative to the material of the pixel electrode layer or the common electrode layer).

[0096] In a possible implementation, referring to FIG. 1C, the first connecting part 4 includes: a first sub-connecting part 41 extending along the first direction X, and a second sub-connecting part 42 connected to one end of the first sub-connecting part 41; the width b2 of the second sub-connecting part 42 in the second direction Y is greater than the width b1 of the first sub-connecting part 41 in the second direction Y; the first sub-connecting part 41 is in direct contact with the second pixel electrode 12 and is electrically connected thereto; the orthographic projection of the second sub-connecting part 42 on the substrate overlaps the orthographic projection of the transistor T on the substrate. In the embodiment of the present application, the first sub-connecting part 41 has a small line width, which can avoid the problem that a large line width of the first sub-connecting part 41 affects the transmittance of the array substrate, and the second sub-connecting part 42 has a large line width, which can achieve good lapping with the transistor.

[0097] It should be noted that the first sub-connecting part 41 extends along the first direction X, which can be understood as that the main direction of the first sub-connecting part 41 extends along the first direction X, but there can be a bending part at a local position, for example, the first sub-connecting part 41 has a bending part at the position overlapped with the common wiring 7.

[0098] In a possible implementation, referring to FIG. 1C, the line width b1 of the first sub-connecting part 41 in the second direction Y is less than the minimum distance b3 between the first connecting part 4 and the gate line 20. That is, by setting the line width of the first sub-connecting part 41 to be small, the problem that a large line width of the first sub-connecting part 41 affects the transmittance of the array substrate can be avoided.

[0099] Optionally, the minimum distance b3 between the first connecting part 4 and the gate line 20 can be in the range of 5.5 μm to 9 μm, so as to avoid short circuit connection between the first connecting part 4 and the gate line 20. For example, the minimum distance b3 between the first connecting part 4 and the gate line 20 can be 5.5 μm, 6 μm, 7 μm, 8 μm or 9 μm; and the line width b1 of the first sub connecting part 41 in the second direction Y can be in the range of 4 μm to 5 μm.

[0100] In a possible implementation, as shown in FIG. 1B and FIG. 1E, the first pixel electrode 11 has a first outer edge w1 along the first direction X and close to one side of the first connecting part 4, and the second pixel electrode 12 has a second outer edge w2 along the first direction X and close to one side of the first connecting part 4; the extension line of the second outer edge w2 in the orthographic projection of the substrate is located in the region between the orthographic projection of the first outer edge w1 on the substrate and the orthographic projection of the first connecting part 4 on the substrate. That is, as shown in FIG. 1B, in the embodiment of the present application, the second outer edge w2 of the second pixel electrode 12 is convex to the first outer edge w1 of the first pixel electrode 11, so as to realize the overlap between the second pixel electrode 12 and the first connecting part 4, and the first pixel electrode 11 does not contact the first connecting part 4.

[0101] In a possible implementation, as shown in FIG. 1A, the array substrate includes a first data line 31 and a second data line 32 adjacent to the pixel electrode group 1; wherein the pixel electrode 10 in the pixel electrode group 1 is electrically connected to the first data line 31 through different transistors T; the second pixel electrode 12 is located on the side of the first pixel electrode 11 away from the first data line 31; that is, the data lines 3 on both sides of the pixel electrode group 1 can be divided into the first data line 31 and the second data line 32, wherein the data line 3 electrically connected to the two pixel electrodes 10 in the pixel electrode group 1 is taken as the first data line 31, and the data line 3 not electrically connected to the two pixel electrodes 10 in the pixel electrode group 1 is taken as the second data line 32. For example, as shown in FIG. 1A, the two pixel electrodes 10 in the pixel electrode group 1 on the top are electrically connected to the data line 3 on the left, so the data line 3 on the left can be taken as the first data line 31, and the data line 3 on the right can be taken as the second data line 32.

[0102] Referring to FIG. 1A, the minimum spacing c2 between the second pixel electrode 12 and the second data line 32 in the first direction X is greater than the minimum spacing c1 between the first pixel electrode 11 and the first data line 31 in the first direction. Since the second outer edge w2 of the second pixel electrode 12 protrudes outwardly beyond the first outer edge w1 of the first pixel electrode 11, the overlapping area of the second pixel electrode 12 with the common electrode layer in the second direction Y is greater than the overlapping area of the first pixel electrode 11 with the common electrode layer. In the embodiment of the present application, the second pixel electrode 12 and the second data line 32 have a large gap therebetween, i.e., the maximum length of the second pixel electrode 12 in the first direction X is less than the maximum length of the first pixel electrode 11 in the first direction X, so as to reduce the overlapping area of the second pixel electrode 12 with the subsequently formed common electrode layer in the first direction X, and further make the overlapping area of the entire first pixel electrode 11 with the common electrode layer substantially equal to the overlapping area of the entire second pixel electrode 12 with the common electrode layer, so as to avoid the problem that the display abnormalities (e.g., causing poor pixel brightness uniformity) occur at the same time.

[0103] In a possible implementation, as shown in FIG. 1B, the first pixel electrode 11 has a first outward protruding portion 110 on the side facing the first data line 31, and the second pixel electrode 12 has a second outward protruding portion 120 on the side facing the second data line 32; the length d1 of the first outward protruding portion 110 in the first direction X is greater than the length d2 of the second outward protruding portion 120 in the first direction X, so as to achieve that the second pixel electrode 12 and the second data line 32 have a large gap therebetween, the maximum length of the second pixel electrode 12 in the first direction X is less than the maximum length of the first pixel electrode 11 in the first direction X, and further reduce the overlapping area of the second pixel electrode 12 with the subsequently formed common electrode layer in the first direction X.

[0104] In a possible implementation, as shown in FIGS. 2A and 2B, the array substrate further includes: a plurality of common electrode strips 6 extending in the first direction; optionally, the common electrode strips 6 can be located on the side of the layer where the data lines face away from the substrate; the common electrode strips 6 include: a plurality of common electrode portions 60 distributed in the first direction X; the common electrode portions 60 include: a first sub-common electrode portion 61, a second sub-common electrode portion 62 located on the side of the first sub-common electrode portion 61 along the first direction X, and a third sub-common electrode portion 63 located on the other side of the first sub-common electrode portion 61 along the first direction X; the widths of the second sub-common electrode portion 62 and the third sub-common electrode portion 63 in the second direction Y are both less than the width f1 of the first sub-common electrode portion 61 in the first direction; optionally, the width of the second sub-common electrode portion 62 in the second direction Y can be equal to the width of the third sub-common electrode portion 63 in the second direction Y, both being f2.

[0105] In combination with FIG. 1B, FIG. 2A and FIG. 2B, the overlapping area of the second sub-common electrode part 62 and the first pixel electrode 11 in the substrate orthographic projection is larger than the overlapping area of the third sub-common electrode part 63 and the second pixel electrode 12 in the substrate orthographic projection, wherein the overlapping area of the second sub-common electrode part 62 and the first pixel electrode 11 can be the orthographic projection area of the first outer convex part 110 on the substrate, and the overlapping area of the third sub-common electrode part 63 and the second pixel electrode 12 can be the orthographic projection area of the second outer convex part 120 on the substrate. Since the length of the second outer convex part 120 in the first direction X is smaller than the length of the first outer convex part 110 in the first direction X, the overlapping area of the second sub-common electrode part 62 and the first pixel electrode 11 in the substrate orthographic projection is larger than the overlapping area of the third sub-common electrode part 63 and the second pixel electrode 12 in the substrate orthographic projection, which can make the overlapping area of the first pixel electrode 11 and the common electrode layer in the first direction X larger than the overlapping area of the second pixel electrode 12 and the common electrode layer in the first direction X.

[0106] In a possible implementation, in combination with FIG. 2B, the common electrode strip 6 further includes: a common connection part 64 connecting adjacent common electrode parts 60 in the first direction X; the orthographic projection of the common connection part 64 on the substrate overlaps the orthographic projection of the data line 3 on the substrate, and the width f3 of the common connection part 64 in the second direction Y is smaller than the width of the second sub-common electrode part 62 in the second direction Y and smaller than the width f2 of the third sub-common electrode part 63 in the second direction Y. In the embodiment of the present application, the width f3 of the common connection part 64 in the second direction Y is smaller than the width f2 of the second sub-common electrode part 62 in the second direction Y and / or the width f2 of the third sub-common electrode part 63 in the second direction Y, which can reduce the overlapping area of the common electrode strip 6 and the data line 3, and further reduce the coupling capacitance of the two, thereby avoiding adverse problems on the normal display of the display panel.

[0107] In a possible implementation, in combination with FIG. 1D and FIG. 2B, the layer where the data line is located further includes: a plurality of first common wires 5 extending along the second direction Y; the array substrate further includes: a second common wire 7 in the same layer as the common electrode strip 6 and extending along the second direction Y; the orthographic projection of the second common wire 7 on the substrate overlaps the orthographic projection of the first common wire 5 on the substrate; the second common wire 7 is electrically connected to the first common wire 5 through a third via hole K3, so as to electrically connect adjacent common electrode strips 6 in the second direction Y. Optionally, in combination with FIG. 2A, the second common wire 7 is electrically connected to the first common wire 5 through the third via hole K3, wherein the orthographic projection of the third via hole K3 on the substrate is located in the region between the two gate lines 20 of the gate line group 2.

[0108] In a possible implementation, referring to FIG. 4, the array substrate includes a plurality of pixel electrode rows P1 extending along the first direction X and arranged along the second direction Y; the pixel electrode row P1 includes a plurality of pixel electrodes 10; the light emitted from the region where the same pixel electrode row P1 is located has the same color.

[0109] In a possible implementation, referring to FIG. 4, in the same pixel electrode row P1, the first pixel electrode 11 and the second pixel electrode 12 are alternately arranged; the array substrate includes a plurality of pixel electrode columns P2 extending along the second direction Y and arranged along the first direction X; in the same pixel electrode column P2, the first pixel electrode 11 and the second pixel electrode 12 are alternately arranged.

[0110] In a possible implementation, referring to FIG. 1A and FIG. 1D, the transistor T includes a first electrode TA and a second electrode TB; the first electrode TA is electrically connected with the data line 3; the first electrode TA has a first branch TA1 extending along the first direction X and a second branch TA2, and the second electrode TB extends along the first direction X, and the second electrode TB, in the orthographic projection of the substrate, is located in the region between the orthographic projection of the first branch TA1 on the substrate and the orthographic projection of the second branch TA2 on the substrate. In the embodiment of the present application, the first electrode TA has the first branch TA1 extending along the first direction X and the second branch TA2, and the second electrode TB extends along the first direction X, that is, the transistor T adopts an inverted design, which can improve the pixel aperture ratio of the display panel.

[0111] In a possible implementation, referring to FIG. 1A and FIG. 1D, the array substrate includes a first transistor T1 and a second transistor T2; the first transistor T1 is electrically connected with the first pixel electrode 11, and the second transistor T2 is electrically connected with the second pixel electrode 12; the length d3 of the second electrode TB of the first transistor T1 in the first direction X is equal to the length d4 of the second electrode TB of the second transistor T2 in the first direction X.

[0112] Referring to FIG. 1A-1D, 2A and 2B, in the embodiment of the present application, the layer where the gate line 20 is located can be located on the side of the pixel electrode layer away from the substrate, and the layer where the data line is located can be located on the side of the layer where the gate line 20 is located away from the pixel electrode layer; the common electrode layer can be located on the side of the layer where the data line 3 is located away from the layer where the gate line 20 is located; the common electrode layer and the layer where the data line is located can have a passivation layer therebetween, the passivation layer can have a plurality of first vias K1 and a plurality of second vias K2, and the layer where the common electrode strip 6 is located can further include a plurality of transfer portions 8; wherein the first pixel electrode 11 can be electrically connected to the second terminal TB of the first transistor T1 through the first via K1; and the first connecting portion 4 can be electrically connected to the second terminal TB of the second transistor T2 through the second via K2 via the transfer portion 8; wherein the array substrate can include an active layer arranged in a stack with the data line 3, the pattern of the active layer can be the same as the pattern of the layer of the data line 3, and the active layer is formed using one mask plate, thereby saving the manufacturing process of the display panel.

[0113] In a possible implementation, referring to FIG. 2A, 5F and 5G, the display panel further includes a black matrix layer and a plurality of spacers PS; the black matrix can include a plurality of black matrix openings (as shown by the black thick line frame in FIG. 2A); and the spacer PS can be located in the region between two adjacent gate lines 20 of the gate line group 2, and the spacer PS and the data line 3 overlap in the orthographic projection on the substrate.

[0114] In a possible implementation, the array substrate shown in FIG. 2A can adopt a 5Mask (4Mask can also be used, the pixel electrode layer and the gate line layer are formed using one mask, and 6Mask can also be used, the HTM is split into an active layer and a data line layer) process flow, that is, the pixel electrode layer→the gate line layer→the half-tone mask (HTM) data line layer→the passivation layer→the common electrode layer; there is no insulating layer between the pixel electrode layer and the gate line layer, and therefore the spacing between the two layers of patterns is generally 5μm-6μm; finally, the second pixel electrode 12 is connected to the second transistor T2 by punching and covering the transfer portion 8; the data line layer forms a vertical data line, the first terminal TA and the second terminal TB of the transistor T, and a vertical first common wire 5; the passivation layer is used to form a via connection pattern; the pixel electrode 1 can be a block electrode, the common electrode strip 6 can be grooved to form a slit structure, and an edge field is formed with the pixel electrode, thereby driving the liquid crystal to rotate. The common electrode strip in the common electrode layer is designed to be through from left to right and from top to bottom, forming a network structure, and is connected to the vertical first common wire 5 of the data line layer through the via, thereby reducing the resistance of the common electrode. The counter substrate part of the display panel adopts a 5Mask process flow, that is, the black matrix layer→the red color resist layer→the green color resist layer→the blue color resist layer→the spacer PS process flow. The spacer PS is located on the base formed by the data line 3, and is surrounded by the double-layer metal of the gate line layer and the data line layer, thereby reducing the sliding range of the spacer PS and improving the aperture ratio.

[0115] In a possible implementation, referring to FIGS. 5A-5E, FIG. 5B is a schematic diagram of a single film layer of the common electrode layer in FIG. 5A, FIG. 5C is a schematic diagram of a single film layer of the layer where the gate lines are located in FIG. 5A, FIG. 5D is a schematic diagram of a single film layer of the layer where the data lines are located in FIG. 5A, and FIG. 5E is a schematic diagram of a single film layer of the pixel electrode layer in FIG. 5A, an array substrate is provided in an embodiment of the present application, and the transistor includes a first electrode TA electrically connected to the data line 3. The first electrode TA includes a first electrode first part TA3 and a first electrode second part TA4. The first electrode first part TA3 extends along the first direction X, one end of which is electrically connected to the data line 3, and the other end of which is electrically connected to the first electrode second part TA4. The first electrode first part TA3 in the orthographic projection of the substrate is located in the region between the orthographic projections of two gate lines 20 of the same gate line group 2 on the substrate. The first electrode second part TA4 in the orthographic projection of the substrate is located in the region between two pixel electrodes 10 of the same pixel electrode group 1 in the orthographic projection of the substrate.

[0116] In an embodiment of the present application, while the pixel electrode 10 is transversely arranged, the transistor T and the pixel electrode 10 are connected in long and short connection to reduce the number of COFs, and the long and short connection is realized by the first electrode TA (source electrode) of the transistor T. Compared with the long and short connection realized by the first connection part 4 of the gate line layer shown in FIG. 2A, the connection mode shown in FIG. 5A can reduce the spacing between the multiple wires arranged in the region between adjacent pixel electrode rows, and can further improve the aperture ratio.

[0117] In a possible implementation, referring to FIG. 5D, the first electrode second part TA4 includes a first main part TA40, a first branch part TA41 connected to one end of the first main part TA40 and extending along the second direction Y, and a second branch part TA42 at the other end of the first main part TA40 and extending along the second direction Y. The first main part TA40, the first branch part TA41, and the second branch part TA42 can form a U-shaped structure with an opening facing the second direction Y. In an embodiment of the present application, the first branch part TA41 and the second branch part TA42 of the first electrode second part TA4 extend along the second direction Y, which can improve the aperture ratio of the display panel.

[0118] In a possible implementation, referring to FIG. 5D, the maximum length e1 of the first electrode TA in the first direction X is greater than or equal to the maximum length a1 of the pixel electrode 20 in the first direction X.

[0119] In a possible implementation, as shown in FIG. 5D, the data line 3 includes a plurality of data line main parts 301 and a plurality of data line connecting parts 302, the data line main parts 301 and the data line connecting parts 302 extend along the second direction Y and are alternately distributed along the second direction Y; the data line main part 301 is in the area between the projections of the two adjacent pixel electrodes 10 on the substrate along the first direction X; the data line connecting part 302 overlaps the projection of the gate line group 2 on the substrate, that is, the data line 3 in the area of the pixel electrode row is the data line main part 301, and the data line 3 in the area of the gate line group 2 is the data line connecting part 302; the maximum length e1 of the first electrode TA along the first direction X is greater than the length e2 of the data line main part 301 along the second direction Y.

[0120] In a possible implementation, as shown in FIG. 5D, the width e3 of the data line main part 301 along the first direction X is greater than the width e4 of the data line connecting part 302 along the first direction X. That is, the width of the data line connecting part 302 is less than the width of the data line main part 301, so as to reduce the overlapping area of the data line 3 and the gate line 20 at the intersection, and reduce the coupling capacitance of the two.

[0121] In a possible implementation, as shown in FIG. 5D, the transistor T further includes a second electrode TB; the second electrode TB includes a second electrode first part TB1 and a second electrode second part TB2; the second electrode first part TB1 extends along the second direction Y; the second electrode second part TB2 extends along the first direction X and is connected to one end of the second electrode first part TB1; as shown in FIG. 5E, the pixel electrode 10 includes a pixel electrode main part PA and a pixel electrode protruding part PB.

[0122] In combination with FIGS. 5A, 5D and 5E, the pixel electrode protruding part PB is located on the side of the pixel electrode main part PA away from the data line 3; the projection of the second electrode first part TB1 on the substrate is located in the area between the projection of the first branch TA41 on the substrate and the projection of the second branch TA42 on the substrate; the projection of the second electrode second part TB2 on the substrate overlaps the projection of the pixel electrode protruding part PB on the substrate, and is electrically connected by perforation at the overlapping position.

[0123] In a possible implementation, as shown in FIGS. 5B and 5E, the array substrate further includes a plurality of common electrode strips 6 extending along the first direction X and arranged along the second direction Y, and a first wire 13 arranged in the same layer as the pixel electrode 10 and extending along the second direction Y; at least part of the projection of the first wire 13 on the substrate is located in the area between the projections of the two pixel electrodes 10 of the same pixel electrode group 1 on the substrate; the common electrode strip 6 and the first wire 13 are electrically connected by perforation at the overlapping position.

[0124] In a possible implementation, referring to FIG. 5B, the common electrode strip 6 includes: a plurality of common electrode groups 60 arranged along the first direction X; the common electrode group 60 is in the orthographic projection of the substrate, and overlaps with the orthographic projection of the pixel electrode group 1 on the substrate; the common electrode group 60 includes: a first sub-common electrode 61 extending along the first direction X and distributed along the first direction, a second sub-common electrode 62, a first lap joint 63 connected to the first side of the first sub-common electrode 61 towards the second sub-common electrode 62, and a second lap joint 64 connected to the second side of the second sub-common electrode 62 towards the first sub-common electrode 61;

[0125] Referring to FIG. 5E, the first wire 13 includes: a first wire main part 130, a third lap joint 131 connected to one side of the first wire main part 130, and a fourth lap joint 132 connected to the other side of the first wire main part 130; the orthographic projection of the first lap joint 63 on the substrate overlaps with the orthographic projection of the third lap joint 131 on the substrate, and is electrically connected by punching at the overlapping position, for example, in combination with FIG. 5A, the first lap joint 63 and the third lap joint 131 are electrically connected by the fourth via hole K4 at the overlapping position; the orthographic projection of the second lap joint 64 on the substrate overlaps with the orthographic projection of the fourth lap joint 132 on the substrate, and is electrically connected by punching at the overlapping position, for example, in combination with FIG. 5A, the second lap joint 64 and the fourth lap joint 132 are electrically connected by the fifth via hole K5 at the overlapping position. In this way, the plurality of common electrode strips 6 extending along the first direction X are connected as a whole by the first wire 13 extending along the second direction Y, so that the common electrode forms a mesh structure.

[0126] In a possible implementation, referring to FIG. 5E, the first wire main part 130 can be a whole extending along the second direction Y, but there is a bending structure in a local part; optionally, the first wire main part 130 can include: a plurality of wire units 133 arranged along the second direction Y in sequence, and a wire connection part 137 connecting adjacent wire units 133; the orthographic projection of the wire unit 133 on the substrate can be located in the area between the orthographic projections of the adjacent two pixel electrodes 10 on the substrate in the first direction X; the orthographic projection of the wire connection part 137 on the substrate overlaps with the orthographic projection of the gate line group 2 on the substrate, that is, the first wire main part 130 located in the area of the pixel electrode row can be taken as the wire unit 133, and the first wire main part 130 at the area of the gate line group 2 can be taken as the wire connection part 137. The wire connection part 137 can extend along the third direction Z1; the included angle formed by the third direction Z1 and the first direction X can range from 0° to 90°, for example, it can be 45°.

[0127] In a possible implementation, as shown in FIG. 5E, the wiring unit 133 can include a first sub-wiring unit 134, a second sub-wiring unit 135, and a third sub-wiring unit 136 connecting the first sub-wiring unit 134 and the second sub-wiring unit 135; the first sub-wiring unit 134 and the second sub-wiring unit 135 can each extend along the second direction Y, and the extension lines do not coincide; the third sub-wiring unit 136 can extend along the fourth direction Z2; the included angle formed by the fourth direction Z2 and the first direction X can range from 90° to 180°, for example, can be 145°.

[0128] In a possible implementation, as shown in FIGS. 5A, 5B, and 5E, the third lap joint 63 is on the same side of the first-wire main part 130 in the substrate projection, and the pixel electrode protruding part PB of the first pixel electrode 11 is on the same side of the first-wire main part 130 in the substrate projection; the fourth lap joint 64 is on the same side of the first-wire main part 130 in the substrate projection, and the pixel electrode protruding part PB of the second pixel electrode 12 is on the same side of the first-wire main part 130 in the substrate projection.

[0129] In a possible implementation, as shown in FIGS. 5A, 5B, and 5E, the pixel electrode protruding part PB has a third outer edge f1 extending along the first direction; the third lap joint 131 is on different sides of the third outer edge f1 in the substrate projection, and the fourth lap joint 132 is on different sides of the third outer edge f1 in the substrate projection. In this way, the wiring space of the area before the two adjacent pixel electrodes 10 in the first direction X is saved, and the electrical connection between different patterns is avoided.

[0130] In a possible implementation, as shown in FIG. 5B, the common electrode strip 6 further includes a first common connection part 65; the first common connection part 65 in the substrate projection overlaps the data line 3 in the substrate projection, and the first common connection part 65 connects two adjacent common electrode groups 60 in the first direction X; the maximum width g1 of the first common connection part 65 in the second direction Y is less than the maximum width g2 of the first sub-common electrode 61 and / or the second sub-common electrode 62 in the second direction Y.

[0131] In a possible implementation, as shown in FIGS. 5A, 5B, and 5E, the common electrode strip 6 further includes a second common connection part 66; the second common connection part 66 in the substrate projection overlaps the first wire 13 in the substrate projection, and the second common connection part 66 connects the first lap joint 63 and the second lap joint 64 in the common electrode group 60; the second common connection part 66 extends along the third direction Z, and the maximum line width g3 of the second common connection part 66 perpendicular to the third direction Z is less than the maximum width g2 of the first sub-common electrode 61 and / or the second sub-common electrode 62 in the second direction Y.

[0132] In a possible implementation, referring to FIG. 5C, the array substrate further includes a fifth overlap portion 25 located at the layer of the gate line 20, and the fifth overlap portion 25 can overlap the third overlap portion 63 and / or the fourth overlap portion 64 in the orthographic projection of the substrate; in a possible implementation, the fifth overlap portion 25 can be directly connected in electrical contact with the third overlap portion 63 and / or the fourth overlap portion 64, so as to reduce the wiring resistance when the third overlap portion 63 and / or the fourth overlap portion 64 is electrically connected with the first wiring 13.

[0133] In a possible implementation, in the array substrate structure shown in FIG. 5A, the first layer of indium tin oxide (ITO) shown in FIG. 5B can be used as a common electrode layer, and the second layer of indium tin oxide (ITO) shown in FIG. 5E can be used as a pixel electrode layer.

[0134] In a possible implementation, the array substrate shown in FIG. 5A can adopt a 1+4 mask (Mask) process (4Mask can also be used, the common electrode layer and the gate line layer are completed by using one Mask, 6Mask can also be used, the HTM is split into an active layer+data line two-layer design) process flow, that is, common electrode layer→gate line layer→half-tone mask (HTM) data line layer→passivation layer→pixel electrode layer; the common electrode layer can be free of an insulating layer between the common electrode layer and the gate line layer; the common electrode strip can be a block electrode, and the pixel electrode 1 can be grooved to form a slit structure, and the two form an edge field, thereby driving the liquid crystal to rotate. The common electrode strip in the common electrode layer is designed to be through from left to right and from top to bottom, forming a network structure, and is connected to the vertical first wiring 13 of the pixel electrode layer through a via, thereby reducing the common electrode resistance. The counter substrate part of the display panel adopts a 5Mask process flow, that is, black matrix layer→red color resist layer→green color resist layer→blue color resist layer→spacer PS process flow.

[0135] In a possible implementation, referring to FIGS. 5A-5E, the first electrode (source electrode) of the transistor T can be connected long and short, which can reduce the wiring spacing and improve the aperture ratio. The line width of the first electrode (source electrode) of the transistor T can be 4 μm-5 μm, and the spacing from the gate line 20 is ensured to be 2 μm-3 μm, thereby reducing the lateral field capacitance.

[0136] In a possible implementation, referring to FIGS. 5A-5E, the common electrodes of the first layer of indium tin oxide (ITO) are directly connected left and right, the first wiring 13 in the second layer of indium tin oxide (ITO) is vertically extended, and the common electrodes of the first layer of indium tin oxide (ITO) are connected to form a network structure through a via.

[0137] In a possible implementation, as shown in FIGS. 5A-5E, the spacers PS can be placed in the area where the data lines 3 are located; in a possible implementation, as shown in FIGS. 5A-5E, the black matrix BM at the location where the data lines 3 are located can have a width in the range of 80 μm to 90 μm, for example, can be 84 μm, and the black matrix BM at the location where the transistors T are located can have a width in the range of 59.9 μm to 100.7 μm, the difference is small, which improves the aperture ratio without generating vertical dark lines.

[0138] In a possible implementation, referring to FIGS. 6A-6K, 7A and 7B, another schematic diagram of an array substrate structure provided by an embodiment of the present application is shown, wherein FIG. 6E is a schematic diagram of an array substrate provided by an embodiment of the present application, FIG. 6K is another schematic diagram of an array substrate provided by an embodiment of the present application, FIG. 6A is a schematic diagram of a single film layer of a pixel electrode layer in FIG. 6E, FIG. 6B is a schematic diagram of a gate line layer in FIG. 6E, FIG. 6C is a schematic diagram of a data line layer in FIG. 6E, FIG. 6D is a schematic diagram of a common electrode layer in FIG. 6E, FIG. 6F is a schematic diagram of a single film layer of a pixel electrode layer in FIG. 6K, FIG. 6G is a schematic diagram of a gate line layer in FIG. 6K, FIG. 6H is a schematic diagram of a data line layer in FIG. 6K, FIG. 6I is a schematic diagram of a common electrode layer in FIG. 6K, and FIG. 6J is a schematic diagram of a spacer in FIG. 6K. A pixel can be composed of three R / G / B sub-pixels, and the sub-pixels have the same size, which is 1 / 3 of the size of the pixel. The sub-pixels adopt a horizontal placement structure, and the sub-pixels in the same row are of the same color. The colors are arranged in the order of B→G→R or R→G→B from top to bottom. The data lines are vertical, and sequentially pass through the transistors to connect the pixels. The transistors are all short connections (the transistors connect the nearest pixels). The two rows of gate lines in the pixel are adjacent, and the gate lines are driven by a gate drive circuit GOA. Compared with a conventional single gate display product, the number of the gate drive circuit GOA shown in FIGS. 6A-6K, 7A and 7B is increased by 6 times, and the number of the COF (IC) driving the data lines is changed to 1 / 6. Taking an FHD product as an example, the number of the COF of a single gate product is 6, and the number of the COF can be reduced to 1 according to the scheme. Taking an UHD product as an example, the number of the COF of a single gate product is 12, and the number of the COF can be reduced to 2 according to the scheme. Taking an 8K product as an example, the number of the COF of a single gate product is 24, and the number of the COF can be reduced to 4 according to the scheme. When the data of the data lines adopts frame inversion, the polarity of the pixel is shown in FIG. 7A, and the polarities of the two adjacent pixels are the same. When the data of the data lines adopts 2dot inversion, the polarity of the pixel is shown in FIG. 7B, and the display uniformity of the panel is better. Since the color of the sub-pixel vertically changes, the shaking lines are not easily generated when the polarities of the two adjacent sub-pixels are the same. The array substrate structure shown in FIG. 6E is different from the array substrate structure shown in FIG. 6K in that the line width of the first common wire 5 can be different, and the line width of the first common wire 5 of the array substrate structure shown in FIG. 6E is narrower, so that the display panel has a higher pixel aperture ratio.

[0139] In a possible implementation, referring to FIG. 6D and FIG. 6I, the array substrate includes: a plurality of common electrode strips 6 extending along the first direction X; the common electrode strip 6 includes: a plurality of common electrode portions 60 distributed along the first direction X (optionally, one common electrode portion 60 can correspond to two pixel electrodes), and a common connection portion 64 connecting adjacent common electrode portions 60 in the first direction X; the common connection portion 64 is overlapped with the projection of the data line 3 on the substrate; optionally, in combination with FIG. 5D, the common connection portion 64 extends along a third direction Z1 to avoid the transistor and / or the pixel electrode, so as to prevent the common electrode strip 6 from being short-circuited with the transistor and / or the pixel electrode, wherein the third direction Z1 forms an angle with the first direction X in a range of 20°-80°, for example, the third direction Z1 forms an angle with the first direction X in a range of 45°.

[0140] In a possible implementation, referring to FIG. 6D and FIG. 6I, the array substrate further includes: a second common wire 7 in the same layer as the common electrode strip 6 and extending along the second direction Y; the second common wire 7 is overlapped with the projection of the first common wire 5 on the substrate; the second common wire 7 is electrically connected with the first common wire 5 through a third via hole K3, so as to electrically connect adjacent common electrode strips 6 in the second direction Y. Optionally, in combination with FIG. 6K, the second common wire 7 of the common electrode layer is electrically connected with the first common wire 5 of the data line layer through the third via hole K3, wherein the third via hole K3 is located in the region between two gate lines 20 of the gate line group 2.

[0141] In a possible implementation, referring to FIG. 6D and FIG. 6I, the second common wire 7 can include: a second common wire main portion 71, a second common wire connection portion 72, and a second common wire overlap portion 73; the second common wire main portion 71 extends along the second direction Y and is located in the region between adjacent pixel electrodes 10 in the first direction X on the substrate; the second common wire connection portion 72 extends along the second direction Y and connects adjacent second common wire main portions 71; the second common wire overlap portion 73 is electrically connected with the first common wire 5 through the third via hole K3.

[0142] In a possible implementation, as shown in FIG. 6I, the width of the second common line main part 71 in the first direction X is greater than the width of the second common line overlap part 73 in the first direction X; and the width of the second common line overlap part 73 in the first direction X is greater than the width of the second common line connecting part 72 in the first direction X. In a possible implementation, as shown in FIG. 6D, the width of the second common line overlap part 73 in the first direction X is greater than the width of the second common line connecting part 72 in the first direction X; and the width of the second common line main part 71 in the first direction X can be equal to the width of the second common line connecting part 72 in the first direction X.

[0143] In a possible implementation, as shown in FIG. 6I, the second common line main part 71 can be a block electrode; and the common electrode part 60 can have a plurality of slits.

[0144] In a possible implementation, as shown in FIGS. 6H and 6I, the second common line 7 can have a shape similar to the shape of the first common line 5 in the orthographic projection of the substrate; and optionally, the second common line 7 can coincide with the first common line 5 in the orthographic projection of the substrate.

[0145] In a possible implementation, as shown in FIGS. 6C and 6H, the first common line 5 can include a first common line main part 51, a first common line connecting part 52, and a first common line overlap part 53; the first common line main part 51 extends along the second direction Y and is located in the area between the orthographic projections of the adjacent pixel electrodes 10 in the first direction X in the orthographic projection of the substrate; the first common line connecting part 52 extends along the second direction Y and connects the adjacent first common line main parts 51; and the first common line overlap part 53 is electrically connected to the second common line 7 through the third via K3.

[0146] In a possible implementation, as shown in FIGS. 6B and 6G, the gate line 20 includes a gate line bending part 25; the gate line bending part 25 is arranged around the periphery of the first common line overlap part 53 in the orthographic projection of the substrate to avoid the first common line overlap part 53; and optionally, the gate line bending part 25 does not overlap with the first common line overlap part 53 in the orthographic projection of the substrate.

[0147] In a possible implementation, as shown in FIG. 6E, the display panel can further include a black matrix, and the black matrix can have a plurality of black matrix openings BM0; and the black matrix openings BM0 can overlap with the pixel electrodes in the orthographic projection of the substrate.

[0148] Based on the same inventive concept, the present application also provides a display panel including the array substrate provided by the embodiments of the present application.

[0149] Based on the same inventive concept, the embodiment of the present application also provides a display device comprising the display panel provided by the embodiment of the present application. The implementation of the display device can refer to the above-mentioned embodiments of the display panel, and the repeated parts will not be described herein.

[0150] In the implementation, the display device in the embodiment of the present application can be any product or component with display function, such as a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, etc. Other essential components of the display device are understood by those skilled in the art, and will not be described herein, and should not be considered as a limitation on the present disclosure.

[0151] Although the preferred embodiments of the present disclosure have been described, those skilled in the art can make further changes and modifications to the embodiments once they know the basic inventive concept. Therefore, the appended claims are intended to be interpreted as including all the preferred embodiments and all the changes and modifications falling within the scope of the present disclosure.

[0152] Obviously, those skilled in the art can make various modifications and variations to the present application without departing from the spirit and scope of the present application. Thus, if these modifications and variations of the present application fall within the scope of the claims of the present application and their equivalent technologies, the present application also intends to include these modifications and variations.

Claims

An array substrate, wherein The array substrate comprises a substrate, a plurality of pixel electrode groups located on one side of the substrate, a plurality of gate lines extending along a first direction, a plurality of data lines extending along a second direction, and a plurality of transistors; wherein the pixel electrode groups are located in regions formed by the intersection of the gate line groups and the data lines, and the gate line groups comprise two gate lines extending along the first direction. The pixel electrode groups comprise two pixel electrodes, and the two pixel electrodes of the same pixel electrode group are electrically connected to the same data line through different transistors; and the length of the pixel electrodes in the first direction is greater than the length in the second direction. The two pixel electrodes of the pixel electrode group are a first pixel electrode and a second pixel electrode, and the second pixel electrode is located on the side of the first pixel electrode away from the data line to which the first pixel electrode is electrically connected; and the first pixel electrodes and the second pixel electrodes are alternately arranged in the same pixel electrode row. The array substrate as claimed in claim 1, wherein, The array substrate comprises a plurality of pixel electrode columns extending along the second direction and arranged along the first direction. The first pixel electrodes and the second pixel electrodes are alternately arranged in the same pixel electrode column. The array substrate comprises a plurality of pixel electrode rows extending along the first direction and arranged along the second direction; and the pixel electrode rows comprise a plurality of pixel electrodes. The array substrate according to claim 1 or 2, wherein, The light emitted from the regions where the same pixel electrode rows are located has the same color. The layer where the gate lines are located further comprises a first connecting portion extending along the first direction; the first connecting portion is directly in contact with and electrically connected to the second pixel electrode, and the second pixel electrode is electrically connected to the transistor through the first connecting portion. The array substrate according to any one of claims 1 to 3, wherein The first connecting portion comprises a first sub-connecting portion extending along the first direction and a second sub-connecting portion connected to one end of the first sub-connecting portion; the width of the second sub-connecting portion in the second direction is greater than the width of the first sub-connecting portion in the second direction. The array substrate as claimed in claim 4, wherein, The first sub-connecting portion is directly in contact with and electrically connected to the second pixel electrode; and the second sub-connecting portion overlaps the transistor in the orthographic projection of the substrate. The line width of the first sub-connecting portion in the second direction is less than the minimum distance between the first connecting portion and the gate line. The first pixel electrode has a first outer edge along the first direction and close to one side of the first connecting portion, and the second pixel electrode has a second outer edge along the first direction and close to one side of the first connecting portion. The array substrate as claimed in claim 5, wherein, The extension line of the second outer edge in the orthographic projection of the substrate is located in the region between the orthographic projection of the first outer edge and the orthographic projection of the first connecting portion on the substrate. The array substrate according to any one of claims 4-6, wherein, The array substrate comprises a first data line and a second data line adjacent to the pixel electrode groups; the pixel electrodes of the pixel electrode groups are electrically connected to the first data line through different transistors; and the second pixel electrode is located on the side of the first pixel electrode away from the first data line. ​ The array substrate according to any one of claims 4-6, wherein, ​ The minimum distance between the second pixel electrode and the second data line in the first direction is greater than the minimum distance between the first pixel electrode and the first data line in the first direction. The array substrate as claimed in claim 8, wherein, The first pixel electrode has a first outer protrusion on a side facing the first data line, and the second pixel electrode has a second outer protrusion on a side facing the second data line. The length of the first outer protrusion in the first direction is greater than the length of the second outer protrusion in the first direction. The array substrate according to any one of claims 4-9, wherein, The array substrate further comprises a plurality of common electrode strips extending in the first direction. The common electrode strip comprises a plurality of common electrode portions distributed in the first direction; the common electrode portion comprises a first sub-common electrode portion, a second sub-common electrode portion on one side of the first sub-common electrode portion in the first direction, and a third sub-common electrode portion on the other side of the first sub-common electrode portion in the first direction; the second sub-common electrode portion and the third sub-common electrode portion have a width in the second direction, which is less than the width of the first sub-common electrode portion in the first direction. The overlapping area of the second sub-common electrode portion and the first pixel electrode in the substrate orthographic projection is greater than the overlapping area of the third sub-common electrode portion and the second pixel electrode in the substrate orthographic projection. The common electrode strip further comprises a common connection portion connecting adjacent common electrode portions in the first direction. The array substrate as claimed in claim 10, wherein, The common connection portion in the substrate orthographic projection overlaps the data line in the substrate orthographic projection, and the width of the common connection portion in the second direction is less than the width of the second sub-common electrode portion in the second direction and less than the width of the third sub-common electrode portion in the second direction. The layer where the data line is located further comprises a plurality of first common wires extending in the second direction; the array substrate further comprises a second common wire in the same layer as the common electrode strip and extending in the second direction; the second common wire in the substrate orthographic projection overlaps the first common wire in the substrate orthographic projection; The array substrate according to claim 10 or 11, wherein, The second common wire is electrically connected to the first common wire through a hole, so that adjacent common electrode strips in the second direction are electrically connected. The transistor comprises a first electrode and a second electrode; the first electrode is electrically connected to the data line; The array substrate according to any one of claims 4-12, wherein, The first electrode has a first branch portion and a second branch portion extending in the first direction, and the second electrode extends in the first direction; the second electrode in the substrate orthographic projection is located in the region between the first branch portion in the substrate orthographic projection and the second branch portion in the substrate orthographic projection. The transistor comprises a first electrode electrically connected to the data line; the first electrode comprises a first electrode first portion and a first electrode second portion; the first electrode first portion extends in the first direction, one end of which is electrically connected to the data line, and the other end is electrically connected to the first electrode second portion; The array substrate according to any one of claims 1 to 3, wherein The first electrode first portion in the substrate orthographic projection is located between two gate lines of the same gate line group. ​ The first electrode second part is in the region between the projections of the two pixel electrodes of the same pixel electrode group on the substrate. The array substrate of claim 14, wherein, The first electrode second part includes a first main part, a first branch part connected to one end of the first main part and extending in the second direction, and a second branch part connected to the other end of the first main part and extending in the second direction. The array substrate according to claim 14 or 15, wherein, The maximum length of the first electrode in the first direction is greater than or equal to the maximum length of the pixel electrode in the first direction. The array substrate according to any one of claims 14-16, wherein, The data line includes a plurality of data line main parts and a plurality of data line connection parts, the data line main parts and the data line connection parts extend in the second direction and are alternately distributed in the second direction. The projection of the data line main part on the substrate is in the region between the projections of the two pixel electrodes adjacent in the first direction on the substrate; the projection of the data line connection part on the substrate overlaps the projection of the gate line group on the substrate. The maximum length of the first electrode in the first direction is greater than the length of the data line main part in the second direction. The array substrate of claim 17, wherein, The width of the data line main part in the first direction is greater than the width of the data line connection part in the first direction. The array substrate according to any one of claims 14-18, wherein, The transistor further includes a second electrode; the second electrode includes a second electrode first part and a second electrode second part; the second electrode first part extends in the second direction; the second electrode second part extends in the first direction and is connected to one end of the second electrode first part; The pixel electrode includes a pixel electrode main part and a pixel electrode protruding part; the pixel electrode protruding part is located on the side of the pixel electrode main part away from the data line; The projection of the second electrode first part on the substrate is in the region between the projection of the first branch part on the substrate and the projection of the second branch part on the substrate; the second electrode second part The projection of the second electrode first part on the substrate is in the region between the projection of the first branch part on the substrate and the projection of the second branch part on the substrate; the second electrode second part The array substrate of claim 19, wherein, The array substrate further includes a plurality of common electrode strips extending in the first direction and arranged in the second direction, and a first trace arranged in the same layer as the pixel electrode and extending in the second direction; The projection of the first trace on the substrate is in the region between the projections of the two pixel electrodes of the same pixel electrode group on the substrate; the common electrode strip and the first trace are electrically connected at the overlapping position. The array substrate as claimed in claim 20, wherein, The common electrode strip includes a plurality of common electrode groups arranged in the first direction; the projection of the common electrode group on the substrate overlaps the projection of the pixel electrode group on the substrate; the common electrode group includes a first sub-common electrode extending in the first direction and distributed in the first direction, a second sub-common electrode, a first lap part connected to the side of the first sub-common electrode facing the second sub-common electrode, and a second lap part connected to the side of the second sub-common electrode facing the first sub-common electrode; The first wire includes a first wire main part, a third overlapping part connected to one side of the first wire main part, and a fourth overlapping part connected to the other side of the first wire main part. The first overlapping part overlaps the third overlapping part in the projection of the substrate, and is electrically connected by punching at the overlapping position; and the second overlapping part overlaps the fourth overlapping part in the projection of the substrate, and is electrically connected by punching at the overlapping position. The array substrate of claim 21, wherein, The third overlapping part and the pixel electrode protruding part of the first pixel electrode in the projection of the substrate are located on the same side of the projection of the first wire main part in the projection of the substrate. The fourth overlapping part and the pixel electrode protruding part of the second pixel electrode in the projection of the substrate are located on the same side of the projection of the first wire main part in the projection of the substrate. The array substrate as claimed in claim 22, wherein, The pixel electrode protruding part has a third outer edge extending along the first direction. The third overlapping part in the projection of the substrate and the fourth overlapping part in the projection of the substrate are located on different sides of the third outer edge in the projection of the substrate. The common electrode strip further includes a first common connecting part; the first common connecting part overlaps the data line in the projection of the substrate, and the first common connecting part connects two adjacent common electrode groups in the first direction. The array substrate according to any one of claims 21-23, wherein, The maximum width of the first common connecting part in the second direction is smaller than the maximum width of the first sub-common electrode and / or the second sub-common electrode in the second direction. The common electrode strip further includes a second common connecting part; the second common connecting part overlaps the first wire in the projection of the substrate, and the second common connecting part connects the first overlapping part and the second overlapping part in the common electrode group. The array substrate according to any one of claims 21-24, wherein, The second common connecting part extends along a third direction, and the maximum line width of the third common electrode part perpendicular to the third direction is smaller than the maximum width of the first sub-common electrode and / or the second sub-common electrode in the second direction. The array substrate includes any one of claims 1-25. A display panel, wherein, The display panel includes claim 26. A display device, wherein, ​

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