Clock control circuit, memory and clock control method

Abstract

Provided in the embodiments of the present disclosure are a clock control circuit, a memory and a clock control method. The clock control circuit comprises: a delay adjustment circuit, which is used for receiving a first phase clock signal, a second phase clock signal, a third phase clock signal, a fourth phase clock signal and a determination result signal and, in a duty ratio adjustment training mode and on the basis of the determination result signal, adjusting the delays of the second phase clock signal, the third phase clock signal and the fourth phase clock signal, or adjusting the delays of the first phase clock signal, the second phase clock signal and the fourth phase clock signal; and a determination circuit, which is used for recording the phase sequence of the first phase clock signal and the third phase clock signal at a self-refresh mode exiting moment, comparing same with the phase sequence at the previous self-refresh mode exiting moment, and outputting a determination result signal on the basis of whether the two phase sequences are consistent with each other. The embodiments of the present disclosure at least help to ameliorate the phase difference of four phase clock signals.

Description

Clock control circuit, memory and clock control method

[0001] The present application claims priority from the Chinese patent application No. 202410651361.6 filed on May 21, 2024, and entitled "Clock control circuit, memory and clock control method", the content of which is incorporated herein by reference in its entirety. TECHNICAL FIELD

[0002] Embodiments of the present disclosure relate to the field of semiconductor technology, in particular to a clock control circuit, a memory and a clock control method. BACKGROUND

[0003] Clock is a very important component in digital circuits, which provides a stable time reference, so that each part of the digital circuit can work according to the predetermined timing.

[0004] In the memory, the clock also plays a very important role. The data in the memory is usually transmitted in a certain timing. The clock signal can control the input and output of data, ensuring that the data is read or written at the correct time point. Through the synchronization of the clock, the memory can work in coordination with other digital circuit components to ensure the accuracy and reliability of data transmission. However, due to environmental influences, the external clock signal received by the memory may have a duty cycle variation, which may affect the normal operation of the internal clock of the memory.

[0005] SUMMARY

[0006] Embodiments of the present disclosure provide a clock control circuit, a memory and a clock control method, which at least have the advantage of improving the phase difference between four-phase clock signals.

[0007] In a first aspect, embodiments of the present disclosure provide a clock control circuit, applied to a memory, comprising:

[0008] The delay adjustment circuit is configured to receive a first phase clock signal, a second phase clock signal, a third phase clock signal, a fourth phase clock signal and a judgment result signal, and when the memory is in a duty cycle adjustment training mode, adjust the delay of the second phase clock signal, the third phase clock signal and the fourth phase clock signal according to the judgment result signal, or adjust the delay of the first phase clock signal, the second phase clock signal and the fourth phase clock signal, and output a first target clock signal, a second target clock signal, a third target clock signal and a fourth target clock signal.

[0009] The judgment circuit is electrically connected with the delay adjustment circuit, and is configured to record the phase sequence of the first phase clock signal and the third phase clock signal at the self-refresh mode exit time of the memory, compare the phase sequence of the first phase clock signal and the third phase clock signal at the last self-refresh mode exit time with the phase sequence of the first phase clock signal and the third phase clock signal at the self-refresh mode exit time, and output the judgment result signal according to whether the phase sequences at the two times are consistent.

[0010] In some embodiments, the recording of the phase sequence of the first phase clock signal and the third phase clock signal at the self-refresh mode exit time of the memory comprises: the memory receiving a no-operation command NOP at the self-refresh mode exit time, if the no-operation command NOP is sampled by the rising edge of the first phase clock signal, recording that the phase of the first phase clock signal leads the phase of the third phase clock signal, and if the no-operation command NOP is sampled by the rising edge of the third phase clock signal, recording that the phase of the first phase clock signal lags behind the phase of the third phase clock signal; the comparison of the phase sequence of the first phase clock signal and the third phase clock signal at the last self-refresh mode exit time with the phase sequence of the first phase clock signal and the third phase clock signal at the self-refresh mode exit time, and the output of the judgment result signal according to whether the phase sequences at the two times are consistent, comprise: if the phase sequences at the two times are consistent, outputting the judgment result signal with a logic value of 1, and if the phase sequences at the two times are inconsistent, outputting the judgment result signal with a logic value of 0.

[0011] In some embodiments, the delay adjustment circuit comprises: a control circuit configured to receive a first group of control codes, a second group of control codes and the judgment result signal, output the first group of control codes as target control codes if the logic value of the judgment result signal is 1, and output the second group of control codes as the target control codes if the logic value of the judgment result signal is 0; the first group of control codes are used to adjust the delay of the second phase clock signal, the third phase clock signal and the fourth phase clock signal, and the second group of control codes are used to adjust the delay of the first phase clock signal, the second phase clock signal and the fourth phase clock signal; a delay circuit electrically connected with the control circuit, configured to receive the first phase clock signal, the second phase clock signal, the third phase clock signal, the fourth phase clock signal and the target control codes, adjust the delay of the second phase clock signal, the third phase clock signal and the fourth phase clock signal according to the target control codes, or adjust the delay of the first phase clock signal, the second phase clock signal and the fourth phase clock signal, and output the first target clock signal, the second target clock signal, the third target clock signal and the fourth target clock signal.

[0012] In some embodiments, the target control codes include a first target control code, a second target control code, a third target control code, and a fourth target control code, and the delay circuit includes: a first delay sub-circuit configured to receive the first phase clock signal and the first target control code, adjust the delay of the first phase clock signal according to the first target control code, and output the first target clock signal; a second delay sub-circuit configured to receive the second phase clock signal and the second target control code, adjust the delay of the second phase clock signal according to the second target control code, and output the second target clock signal; a third delay sub-circuit configured to receive the third phase clock signal and the third target control code, adjust the delay of the third phase clock signal according to the third target control code, and output the third target clock signal; and a fourth delay sub-circuit configured to receive the fourth phase clock signal and the fourth target control code, adjust the delay of the fourth phase clock signal according to the fourth target control code, and output the fourth target clock signal.

[0013] In some embodiments, the first group of control codes includes, in sequence, a ground signal, a second phase control code, a third phase control code, and a fourth phase control code; the second group of control codes includes, in sequence, the third phase control code, the fourth phase control code, a ground signal, and the second phase control code; and the control circuit includes: a first selection unit configured to receive the ground signal, the third phase control code, and the judgment result signal, output the ground signal as the first target control code if the logic value of the judgment result signal is 1, and output the third phase control code as the first target control code if the logic value of the judgment result signal is 0; a second selection unit configured to receive the second phase control code, the fourth phase control code, and the judgment result signal, output the second phase control code as the second target control code if the logic value of the judgment result signal is 1, and output the fourth phase control code as the second target control code if the logic value of the judgment result signal is 0; a third selection unit configured to receive the third phase control code, a ground signal, and the judgment result signal, output the third phase control code as the third target control code if the logic value of the judgment result signal is 1, and output the ground signal as the third target control code if the logic value of the judgment result signal is 0; and a fourth selection unit configured to receive the fourth phase control code, the second phase control code, and the judgment result signal, output the fourth phase control code as the fourth target control code if the logic value of the judgment result signal is 1, and output the second phase control code as the fourth target control code if the logic value of the judgment result signal is 0.

[0014] In some embodiments, the second phase control code, the third phase control code and the fourth phase control code are stored and outputted by a mode register.

[0015] In some embodiments, the first delay sub-circuit comprises a first capacitor unit and an even number of first inverters, the even number of first inverters are connected in sequence, an input terminal of a first inverter at the head receives the first phase clock signal, an output terminal of a first inverter at the tail outputs the first target clock signal, the first capacitor unit receives the first target control code and is connected to an output terminal of a certain first inverter; the second delay sub-circuit comprises a second capacitor unit and an even number of second inverters, the even number of second inverters are connected in sequence, an input terminal of a second inverter at the head receives the second phase clock signal, an output terminal of a second inverter at the tail outputs the second target clock signal, the second capacitor unit receives the second target control code and is connected to an output terminal of a certain second inverter; the third delay sub-circuit comprises a third capacitor unit and an even number of third inverters, the even number of third inverters are connected in sequence, an input terminal of a third inverter at the head receives the third phase clock signal, an output terminal of a third inverter at the tail outputs the third target clock signal, the third capacitor unit receives the third target control code and is connected to an output terminal of a certain third inverter; the fourth delay sub-circuit comprises a fourth capacitor unit and an even number of fourth inverters, the even number of fourth inverters are connected in sequence, an input terminal of a fourth inverter at the head receives the fourth phase clock signal, an output terminal of a fourth inverter at the tail outputs the fourth target clock signal, the fourth capacitor unit receives the fourth target control code and is connected to an output terminal of a certain fourth inverter.

[0016] In some embodiments, the judging circuit comprises: a latch configured to receive a first flag signal and a second flag signal, the first flag signal being used to represent that the NOP is sampled by a rising edge of the first phase clock signal at a self-refresh mode exit time, the second flag signal being used to represent that the NOP is sampled by a rising edge of the third phase clock signal at the self-refresh mode exit time, outputting a first level of phase representation signal if the first flag signal is in a valid state, and outputting a second level of the phase representation signal if the second flag signal is in the valid state; and a comparison unit electrically connected to the latch, configured to receive and store the phase representation signal, and compare a level state of the phase representation signal received at a current self-refresh mode exit time with a level state of the phase representation signal received at a last self-refresh mode exit time, outputting the judging result signal with a logic value of 1 if the level states of the two times are consistent, and outputting the judging result signal with a logic value of 0 if the level states of the two times are inconsistent.

[0017] In some embodiments, the latch is an SR latch, a first end of the SR latch receiving the first flag signal, a second end of the SR latch receiving the second flag signal, and an output end of the SR latch outputting the phase representation signal.

[0018] In the second aspect, the embodiments of the present disclosure provide a memory, which at least comprises the clock control circuit according to the first aspect.

[0019] In some embodiments, the memory further comprises: a receiving circuit configured to receive an external clock signal and output an internal clock signal, the internal clock signal having a same frequency as the external clock signal; a frequency divider electrically connected to the receiving circuit and configured to receive the internal clock signal, divide the internal clock signal by two, and generate the first phase clock signal, the second phase clock signal, the third phase clock signal, and the fourth phase clock signal; and a delay-locked loop electrically connected to the frequency divider and the clock control circuit, and configured to adjust a delay of at least one of the first phase clock signal, the second phase clock signal, the third phase clock signal, and the fourth phase clock signal, so that a phase difference between the at least one of the first phase clock signal, the second phase clock signal, the third phase clock signal, and the fourth phase clock signal and the external clock signal is less than a preset value.

[0020] In some embodiments, the memory conforms to a DDR5 specification.

[0021] In a third aspect, the embodiments of the present disclosure provide a clock control method applied to a memory, comprising: recording phase sequences of a first phase clock signal and a third phase clock signal at a self-refresh mode exit moment of the memory, and comparing the phase sequences of the first phase clock signal and the third phase clock signal at the self-refresh mode exit moment with phase sequences of the first phase clock signal and the third phase clock signal at a last self-refresh mode exit moment, to determine whether the phase sequences at the two moments are consistent; if the phase sequences at the two moments are consistent, adjusting time delays of a second phase clock signal, the third phase clock signal and a fourth phase clock signal when the memory is in a duty cycle adjustment training mode; if the phase sequences at the two moments are inconsistent, adjusting time delays of the first phase clock signal, the second phase clock signal and the fourth phase clock signal when the memory is in the duty cycle adjustment training mode.

[0022] In some embodiments, the recording of the phase sequences of the first phase clock signal and the third phase clock signal at the self-refresh mode exit moment of the memory comprises: the memory receiving a no-operation command NOP at the self-refresh mode exit moment, and if the no-operation command NOP is sampled by a rising edge of the first phase clock signal, it is recorded that the phase of the first phase clock signal leads the phase of the third phase clock signal; if the no-operation command NOP is sampled by a rising edge of the third phase clock signal, it is recorded that the phase of the first phase clock signal lags behind the phase of the third phase clock signal.

[0023] In some embodiments, the adjusting of the time delays of the second phase clock signal, the third phase clock signal and the fourth phase clock signal when the memory is in the duty cycle adjustment training mode if the phase sequences at the two moments are consistent, and the adjusting of the time delays of the first phase clock signal, the second phase clock signal and the fourth phase clock signal when the memory is in the duty cycle adjustment training mode if the phase sequences at the two moments are inconsistent, comprises: if the phase sequences at the two moments are consistent, using a first group of control codes to adjust the time delays of the second phase clock signal, the third phase clock signal and the fourth phase clock signal when the memory is in the duty cycle adjustment training mode; if the phase sequences at the two moments are inconsistent, using a second group of control codes to adjust the time delays of the first phase clock signal, the second phase clock signal and the fourth phase clock signal when the memory is in the duty cycle adjustment training mode.

[0024] The technical solutions provided by the embodiments of the present disclosure have at least the following advantages:

[0025] The clock control circuit is applied to the memory and comprises: a delay adjustment circuit configured to receive a first phase clock signal, a second phase clock signal, a third phase clock signal, a fourth phase clock signal and a judgment result signal, adjust the delay of the second phase clock signal, the third phase clock signal and the fourth phase clock signal or adjust the delay of the first phase clock signal, the second phase clock signal and the fourth phase clock signal according to the judgment result signal when the memory is in a duty cycle adjustment training mode, and output a first target clock signal, a second target clock signal, a third target clock signal and a fourth target clock signal; and a judgment circuit electrically connected with the delay adjustment circuit and configured to record the phase sequence of the first phase clock signal and the third phase clock signal at the moment when the memory exits a self-refresh mode, compare the phase sequence with the phase sequence of the first phase clock signal and the third phase clock signal at the last time when the memory exits the self-refresh mode, and output the judgment result signal according to whether the two phase sequences are consistent. When the memory is in the self-refresh mode, no external clock signal is accepted, when the memory exits the self-refresh mode, the external clock signal is received again, at this time, the duty cycle adjustment training needs to be performed to adjust the phase difference between the four phase clock signals. The phase sequence of the first phase clock signal and the third phase clock signal at the current time and the last time when the memory exits the self-refresh mode is recorded and compared, and the delay of the second phase clock signal, the third phase clock signal and the fourth phase clock signal or the delay of the first phase clock signal, the second phase clock signal and the fourth phase clock signal is adjusted according to whether the two phase sequences are consistent, which is beneficial to more accurately and quickly adjusting the phase difference between the four phase clock signals in the duty cycle adjustment training mode, saves the time of the duty cycle adjustment training, improves the accuracy of the four phase clock signals, and ensures the quality of the final memory output data. BRIEF DESCRIPTION OF DRAWINGS

[0026] One or more embodiments are illustrated by way of example in the figures that form a part of this disclosure and which are shown by way of illustration in the drawings. Wherever possible, the same reference numbers will be used throughout the drawings to refer to same or like elements that do not necessarily have a direct relationship to each other. Embodiments may be implemented in any of a variety of ways, and that the application encompasses all such variations which become apparent to those of ordinary skill in the art once given the benefit of this disclosure. Any and all embodiments may include one, some or all of the features discussed herein. In the drawings:

[0027] FIG. 1 is a flowchart of a running process of a memory according to an embodiment of the present disclosure;

[0028] FIG. 2a is a clock signal waveform diagram of a memory in a case according to an embodiment of the present disclosure;

[0029] Figure 2b is a clock signal waveform diagram of the memory in another case according to an embodiment of the present disclosure;

[0030] Figure 2c is a clock signal waveform diagram of the memory in yet another case according to an embodiment of the present disclosure;

[0031] Figure 3 is a structural schematic diagram of a clock control circuit according to an embodiment of the present disclosure;

[0032] Figure 4 is a structural schematic diagram of a delay adjustment circuit according to an embodiment of the present disclosure;

[0033] Figure 5 is a structural schematic diagram of a delay circuit according to an embodiment of the present disclosure;

[0034] Figure 6 is a structural schematic diagram of a control circuit according to an embodiment of the present disclosure;

[0035] Figure 7 is a structural schematic diagram of a first delay sub-circuit according to an embodiment of the present disclosure;

[0036] Figure 8 is a structural schematic diagram of a judgment circuit according to an embodiment of the present disclosure;

[0037] Figure 9 is a structural schematic diagram of a memory according to an embodiment of the present disclosure;

[0038] Figure 10 is another structural schematic diagram of a memory according to an embodiment of the present disclosure;

[0039] Figure 11 is a flowchart of a clock control method according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0040] The technical solutions in the embodiments of the present disclosure will be described clearly and completely in the following with reference to the drawings in the embodiments of the present disclosure. It can be understood that the specific embodiments described herein are only used to explain the related application, and not to limit the application. In addition, it should be noted that, for the convenience of description, only the parts related to the application are shown in the drawings. Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the present disclosure belongs. The terms used herein are only for the purpose of describing the embodiments of the present disclosure, and are not intended to limit the present disclosure. In the following description, “some embodiments” are described, which describe a subset of all possible embodiments, but it can be understood that “some embodiments” can be the same subset or different subset of all possible embodiments, and can be combined with each other without conflict. It should be noted that the terms “first”, “second”, “third” involved in the embodiments of the present disclosure are only used to distinguish similar objects, and do not represent a specific order of the objects. It can be understood that “first”, “second”, “third” can be interchanged in a specific order or sequence as allowed, so that the embodiments of the present disclosure described herein can be implemented in an order other than that illustrated or described herein.

[0041] Dynamic Random Access Memory (DRAM)

[0042] Synchronous Dynamic Random Access Memory (SDRAM)

[0043] Double Data Rate SDRAM (DDR)

[0044] Low Power DDR (LPDDR)

[0045] DDRn Specification (DDRn), such as DDR3, DDR4, DDR5, DDR6

[0046] LPDDRn Specification (LPDDRn), such as LPDDR3, LPDDR4, LPDDR5, LPDDR6

[0047] Self Refresh Exit (SRX)

[0048] No Operation (NOP)

[0049] duty cycle adjust training (DCA training)

[0050] Clock is a very important component in digital circuits, it provides a stable time reference, so that the various parts of the digital circuit can work according to the predetermined timing. In the memory, the clock also plays a very important role. The data in the memory is usually transmitted in a certain timing. Clock signal can control the input and output of data, to ensure that the data is read or written at the right time point. Through the synchronization of the clock, the memory can work with other digital circuit components, to ensure the accuracy and reliability of data transmission.

[0051] With the increasing frequency of memory, the frequency of the received external clock signal is getting higher and higher, it is necessary to divide frequency inside the memory, to generate internal multi-phase clock signal, for data processing. The phase difference between the multi-phase clock signal is related to the quality of the final output data of the memory. When the duty cycle of the external clock signal changes, the phase difference of the internal multi-phase clock signal after frequency division will also change, causing the signal quality of the memory output data to decline, so it is necessary to carry out duty cycle adjust training (DCA Training) to adjust the phase difference between the internal multi-phase clock signal. However, the applicant found that in some cases, after the duty cycle adjust training, the phase difference between the internal multi-phase clock signal of the memory becomes even greater, or it takes a lot of time to complete the adjustment of the phase difference. The applicant found through analysis that this is related to the order of the multi-phase clock signal when the memory exits the self-refresh mode each time.

[0052] For example, in order to realize high-frequency operation of the memory, four-phase clock signals are generated in the memory based on an external clock signal for data processing. Ideally, the four-phase clock signals include four clock signals with a phase difference of 90 degrees. However, in a high-frequency environment, when the duty cycle of the external clock signal changes, the phase difference between the four-phase clock signals in the memory also changes. Therefore, the DDR5 standard specifies that the duty cycle adjustment training needs to be performed at high frequencies to adjust the phase difference between the four-phase clock signals in the memory. The delay of the four-phase clock signals can be set through a mode register to adjust the phase difference between them. Referring to FIG. 1, a flowchart of the operation of the memory in a case is shown. When the memory is in a self-refresh mode, it does not receive an external clock signal, and the four-phase clock signals are not generated in the memory. When the memory exits the self-refresh mode, it receives the external clock signal again and generates the four-phase clock signals. At this time, the duty cycle adjustment training needs to be performed to adjust the phase difference between the four-phase clock signals in the memory. The memory exits the self-refresh mode in response to a self-refresh exit (SRX) command and subsequently receives a no operation (NOP) command. That is, when the self-refresh mode is exited, the memory receives the SRX and NOP commands in sequence.

[0053] Referring to FIG. 2a, which corresponds to the waveform diagram in the first self-refresh mode exit and duty cycle adjustment training mode in FIG. 1. As shown in FIG. 2a, the duty cycle of the external clock signal CKT received by the memory is unstable, and the phase difference between the four-phase clock signals output by the frequency divider is not ideal 90 degrees, and there is a large gap. The four-phase clock signals include a first-phase clock signal ICLK, a second-phase clock signal QCLK, a third-phase clock signal IBCLK, and a fourth-phase clock signal QBCLK. Ideally, the phases of ICLK, QCLK, IBCLK, and QBCLK should have a phase difference of 90 degrees in sequence, but the phase difference between the four-phase clock signals output by the frequency divider is not 90 degrees. In the duty cycle adjustment training mode, the delay of the second-phase clock signal QCLK, the third-phase clock signal IBCLK, and the fourth-phase clock signal QBCLK is adjusted by setting the parameters in the mode register to adjust the phase difference between the four-phase clock signals in the memory, so that the difference between the phase difference and 90 degrees is less than a predetermined value, i.e., the phase difference between the four-phase clock signals in the memory is close to 90 degrees. In this process, the delay of the first-phase clock signal ICLK is fixed, i.e., the delay of ICLK is not adjusted.

[0054] Referring to Fig. 2b, it corresponds to the waveform diagram in the second time self-refresh mode exit and duty cycle adjustment training mode in Fig. 1. As shown in Fig. 2b, when the second time self-refresh mode exit, the order of the four-phase clock signals generated by the frequency divider is inconsistent with the order when the first time self-refresh mode exit. When the first time self-refresh mode exit, ICLK, QCLK, IBCLK and QBCLK are generated in turn, and the first rising edge of the external clock signal CKT received after the self-refresh mode exit corresponds to the rising edge of ICLK generated. While the second time self-refresh mode exit, IBCLK, QBCLK, ICLK and QCLK are generated in turn, and the first rising edge of the external clock signal CKT received after the self-refresh mode exit corresponds to the rising edge of IBCLK generated. At this time, if the parameters set in the mode register in the last duty cycle adjustment training mode are still used to adjust the delay of the second phase clock signal QCLK, the third phase clock signal IBCLK and the fourth phase clock signal QBCLK, the phase difference between the four-phase clock signals will become worse. Because the parameters stored in the mode register at this time are suitable for the order of the four-phase clock signals when the first time self-refresh mode exit. In the current duty cycle adjustment training mode, if the parameters set in the mode register are re-adjusted, it will take a long time to make the phase difference between the internal four-phase clock signals reach the ideal condition. The applicant analyzes that if the parameters set in the mode register in the last duty cycle adjustment training mode are still used, the parameters originally used to control the delay of QCLK need to be switched to control the delay of QBCLK, the parameters originally used to control the delay of QBCLK need to be switched to control the delay of QCLK, the parameters originally used to control the delay of IBCLK need to be switched to control the delay of ICLK, and the delay of IBCLK is fixed and not adjusted. In this way, as shown in Fig. 2c, the phase difference between the internal four-phase clock signals can be adjusted as soon as possible, so that the difference between the phase difference and 90 degrees is less than the preset value, that is, the phase difference between the internal four-phase clock signals approaches 90 degrees. By switching the delay control of the four-phase clock signals, in the case that the order of the four-phase clock signals generated when the memory exits the self-refresh mode changes, the parameters set in the last mode register can still be used to quickly and accurately adjust the phase difference between the four-phase clock signals in the subsequent duty cycle adjustment training mode. The essence of switching the delay control of the four-phase clock signals is to fix the delay of the first clock signal generated by the frequency divider each time and adjust the delay of the last three clock signals.That is, if the first rising edge of the external clock signal CKT received after exiting the self-refresh mode corresponds to the rising edge of ICLK, that is, the first clock signal generated by the frequency divider is ICLK, the delay of ICLK is fixed, and the delays of QCLK, IBCLK and QBCLK are adjusted; if the first rising edge of the external clock signal CKT received after exiting the self-refresh mode corresponds to the rising edge of IBCLK, that is, the first clock signal generated by the frequency divider is IBCLK, the delay of IBCLK is fixed, and the delays of QBCLK, ICLK and QCLK are adjusted.

[0055] Based on this, the embodiment of the present disclosure provides a clock control circuit applied to a memory, comprising: a delay adjustment circuit configured to receive a first phase clock signal, a second phase clock signal, a third phase clock signal, a fourth phase clock signal and a judgment result signal, and adjust the delays of the second phase clock signal, the third phase clock signal and the fourth phase clock signal or adjust the delays of the first phase clock signal, the second phase clock signal and the fourth phase clock signal according to the judgment result signal when the memory is in a duty cycle adjustment training mode, and output a first target clock signal, a second target clock signal, a third target clock signal and a fourth target clock signal; a judgment circuit electrically connected with the delay adjustment circuit and configured to record the phase sequence of the first phase clock signal and the third phase clock signal at the moment when the memory exits a self-refresh mode, compare the phase sequence with the phase sequence of the first phase clock signal and the third phase clock signal at the moment when the memory exited the self-refresh mode last time, and output the judgment result signal according to whether the two phase sequences are consistent. When the memory is in the self-refresh mode, the external clock signal is not accepted, and when the memory exits the self-refresh mode, the external clock signal is received again. At this time, duty cycle adjustment training is needed to adjust the phase difference between the four internal phase clock signals. The phase sequence of the first phase clock signal and the third phase clock signal at the moment when the memory exits the self-refresh mode is recorded and compared with the phase sequence at the moment when the memory exited the self-refresh mode last time, and the delays of the second phase clock signal, the third phase clock signal and the fourth phase clock signal are adjusted or the delays of the first phase clock signal, the second phase clock signal and the fourth phase clock signal are adjusted according to whether the two phase sequences are consistent. This is conducive to more accurately and quickly adjusting the phase difference between the four phase clock signals in the duty cycle adjustment training mode, saving the time of duty cycle adjustment training, improving the accuracy of the four phase clock signals, and ensuring the quality of the final memory output data.

[0056] The embodiments of the present disclosure will be described in detail below with reference to the drawings.

[0057] In an embodiment of the present disclosure, referring to FIG. 3, a structural schematic diagram of a clock control circuit 10 provided by the embodiment of the present disclosure is shown. As shown in FIG. 3, the clock control circuit 10 comprises:

[0058] The delay adjustment circuit 11 is configured to receive the first phase clock signal ICLK, the second phase clock signal QCLK, the third phase clock signal IBCLK, the fourth phase clock signal QBCLK and the judgment result signal, and adjust the delay of the second phase clock signal QCLK, the third phase clock signal IBCLK and the fourth phase clock signal QBCLK or adjust the delay of the first phase clock signal ICLK, the second phase clock signal QCLK and the fourth phase clock signal QBCLK according to the judgment result signal when the memory is in the duty cycle adjustment training mode, and output the first target clock signal ICLK_out, the second target clock signal QCLK_out, the third target clock signal IBCLK_out and the fourth target clock signal QBCLK_out.

[0059] The judgment circuit 12 is electrically connected with the delay adjustment circuit 11 and is configured to record the phase sequence of the first phase clock signal ICLK and the third phase clock signal IBCLK at the time when the memory exits the self-refresh mode, and compare the phase sequence with the phase sequence of the first phase clock signal ICLK and the third phase clock signal IBCLK at the last time when the memory exits the self-refresh mode, and output the judgment result signal according to whether the two phase sequences are consistent.

[0060] It should be noted that the clock control circuit 10 of the embodiments of the present disclosure can be applied to a memory, such as DRAM, SDRAM, etc. When the memory is in the self-refresh mode, the external clock signal is not accepted, and the four-phase clock signal is not generated internally, when the memory exits the self-refresh mode, the external clock signal is received again, and the four-phase clock signal is generated, at this time, the duty cycle adjustment training needs to be performed to adjust the phase difference between the internal four-phase clock signals.

[0061] The judgment circuit 12 records and compares the phase sequence of the first phase clock signal ICLK and the third phase clock signal IBCLK at the current time and the last time when the self-refresh mode is exited. According to whether the phase sequences at the two times are consistent, the delay adjustment circuit 11 adjusts the delay of the second phase clock signal QCLK, the third phase clock signal IBCLK and the fourth phase clock signal QBCLK, or adjusts the delay of the first phase clock signal ICLK, the second phase clock signal QCLK and the fourth phase clock signal QBCLK, and outputs the first target clock signal ICLK_out, the second target clock signal QCLK_out, the third target clock signal IBCLK_out and the fourth target clock signal QBCLK_out. In this way, it is beneficial to more accurately and quickly adjust the phase difference between the four-phase clock signals in the duty cycle adjustment training mode, so that the first target clock signal ICLK_out, the second target clock signal QCLK_out, the third target clock signal IBCLK_out and the fourth target clock signal QBCLK_out are sequentially different by 90 degrees. The time for duty cycle adjustment training is saved, the accuracy of the four-phase clock signals is improved, and the quality of the final memory output data is ensured.

[0062] It should be understood that the embodiments of the present disclosure allow certain errors for the phase difference. That is, the phases between the first target clock signal, the second target clock signal, the third target clock signal and the fourth target clock signal are sequentially different by 90 degrees within the error allowed range. Subsequent related limitations on phase values, signal alignment or signal waveforms all refer to within the error allowed range.

[0063] In some embodiments, the recording of the phase sequence of the first phase clock signal ICLK and the third phase clock signal IBCLK at the self-refresh mode exit time point of the memory comprises: the memory receives a no operation command NOP at the self-refresh mode exit time point, if the no operation command NOP is sampled by the rising edge of the first phase clock signal ICLK, it is recorded that the phase of the first phase clock signal ICLK leads the phase of the third phase clock signal IBCLK; if the no operation command NOP is sampled by the rising edge of the third phase clock signal IBCLK, it is recorded that the phase of the first phase clock signal ICLK lags behind the phase of the third phase clock signal IBCLK. As known from the foregoing, the memory exits the self-refresh mode in response to a self-refresh exit (SRX) command, and subsequently receives a no operation (NOP) command. That is, when the memory exits the self-refresh mode, it will receive the SRX and NOP commands in sequence. When the memory exits the self-refresh mode, the external clock signal is re-received, four-phase clock signals are generated, and the received commands are sampled. Based on this, by recording which rising edge of which phase clock signal samples the NOP command, it can be known which phase clock signal is generated first after exiting the self-refresh mode, that is, the phase sequence of the first phase clock signal ICLK and the third phase clock signal IBCLK.

[0064] In some embodiments, the phase sequence of the first phase clock signal ICLK and the third phase clock signal IBCLK at the last self-refresh mode exit time point is compared with the phase sequence of the first phase clock signal ICLK and the third phase clock signal IBCLK at the current self-refresh mode exit time point, and a judgment result signal is output according to whether the two phase sequences are consistent, which comprises: if the two phase sequences are consistent, a judgment result signal with a logic value of 1 is output, and if the two phase sequences are inconsistent, a judgment result signal with a logic value of 0 is output. In this way, a judgment result signal with a logic value of 0 or 1 is output according to whether the two phase sequences are consistent, so that the delay adjustment circuit 11 connected thereto selects to adjust the delay of certain phase clock signals in the four-phase clock signals according to the specific logic value of the judgment result signal. In addition, according to different actual application requirements, it can also be set that if the two phase sequences are consistent, a judgment result signal with a logic value of 0 is output, and if the two phase sequences are inconsistent, a judgment result signal with a logic value of 1 is output.

[0065] In some embodiments, as shown in FIG. 4, the delay adjustment circuit 11 comprises:

[0066] The control circuit 111 is configured to receive the first group of control codes, the second group of control codes and the judgment result signal, output the first group of control codes as the target control code if the logic value of the judgment result signal is 1, and output the second group of control codes as the target control code if the logic value of the judgment result signal is 0; the first group of control codes are used to adjust the delay of the second phase clock signal QCLK, the third phase clock signal IBCLK and the fourth phase clock signal QBCLK, and the second group of control codes are used to adjust the delay of the first phase clock signal ICLK, the second phase clock signal QCLK and the fourth phase clock signal QBCLK.

[0067] The delay circuit 112 is electrically connected with the control circuit 111 and is configured to receive the first phase clock signal ICLK, the second phase clock signal QCLK, the third phase clock signal IBCLK, the fourth phase clock signal QBCLK and the target control code, adjust the delay of the second phase clock signal QCLK, the third phase clock signal IBCLK and the fourth phase clock signal QBCLK according to the target control code, or adjust the delay of the first phase clock signal ICLK, the second phase clock signal QCLK and the fourth phase clock signal QBCLK, and output the first target clock signal ICLK_out, the second target clock signal QCLK_out, the third target clock signal IBCLK_out and the fourth target clock signal QBCLK_out.

[0068] It can be understood that the delay circuit 112 adjusts the delay of some phase clock signals in the four-phase clock signal according to the target control code, so it is necessary to determine the target control code according to the logic value of the judgment result signal in advance by the control circuit 111. In this way, the phase difference between the four-phase clock signals can be adjusted more quickly during the duty cycle adjustment training, the time of the duty cycle adjustment training is saved, and the accuracy of the four-phase clock signal is improved.

[0069] In some embodiments, as shown in FIG. 5, the target control code includes a first target control code, a second target control code, a third target control code and a fourth target control code, and the delay circuit 112 includes: a first delay sub-circuit 1121 configured to receive the first phase clock signal ICLK and the first target control code, adjust the delay of the first phase clock signal ICLK according to the first target control code, and output a first target clock signal ICLK_out; a second delay sub-circuit 1122 configured to receive the second phase clock signal QCLK and the second target control code, adjust the delay of the second phase clock signal QCLK according to the second target control code, and output a second target clock signal QCLK_out; a third delay sub-circuit 1123 configured to receive the third phase clock signal IBCLK and the third target control code, adjust the delay of the third phase clock signal IBCLK according to the third target control code, and output a third target clock signal IBCLK_out; and a fourth delay sub-circuit 1124 configured to receive the fourth phase clock signal IBCLK and the fourth target control code, adjust the delay of the fourth phase clock signal IBCLK according to the fourth target control code, and output a fourth target clock signal IBCLK_out.

[0070] It should be noted that the first delay sub-circuit 1121, the second delay sub-circuit 1122, the third delay sub-circuit 1123 and the fourth delay sub-circuit 1124 have the same structure, and the first target control code, the second target control code, the third target control code and the fourth target control code can respectively control the delay of the input signal of each delay sub-circuit, so as to finally obtain a group of target clock signals (i.e., ICLK_out, QCLK_out, IBCLK_out and IBCLK_out) with a phase difference of 90 degrees.

[0071] In some embodiments, as shown in FIG. 6, the first group of control codes comprises, in sequence, a ground signal VSS, a second phase control code MRS Q, a third phase control code MRS IB and a fourth phase control code MRS QB; the second group of control codes comprises, in sequence, the third phase control code MRS IB, the fourth phase control code MRS QB, the ground signal VSS and the second phase control code MRS Q; and the control circuit 111 comprises: a first selection unit 1111 configured to receive the ground signal VSS, the third phase control code MRS IB and a judgment result signal, and output the ground signal VSS as a first target control code if the logic value of the judgment result signal is 1, or output the third phase control code MRS IB as the first target control code if the logic value of the judgment result signal is 0; a second selection unit 1112 configured to receive the second phase control code MRS Q, the fourth phase control code MRS QB and the judgment result signal, and output the second phase control code MRS Q as a second target control code if the logic value of the judgment result signal is 1, or output the fourth phase control code MRS QB as the second target control code if the logic value of the judgment result signal is 0; a third selection unit 1113 configured to receive the third phase control code MRS IB, the ground signal VSS and the judgment result signal, and output the third phase control code MRS IB as a third target control code if the logic value of the judgment result signal is 1, or output the ground signal VSS as the third target control code if the logic value of the judgment result signal is 0; and a fourth selection unit 1114 configured to receive the fourth phase control code MRS QB, the second phase control code MRS Q and the judgment result signal, and output the fourth phase control code MRS QB as a fourth target control code if the logic value of the judgment result signal is 1, or output the second phase control code MRS Q as the fourth target control code if the logic value of the judgment result signal is 0.

[0072] It can be understood that if the logic value of the judgment result signal is 1, that is, the phase sequence of the first phase clock signal ICLK and the third phase clock signal IBCLK is consistent at the current time and the last time when the self-refresh mode is exited, the first target control code, the second target control code, the third target control code and the fourth target control code output by the control circuit 111 are VSS, MRS_Q, MRS_IB and MRS_QB in turn, and the delay circuit 112 adjusts the delays of QCLK, IBCLK and QBCLK respectively in response to the target control codes. That is, the second delay sub-circuit 1122 adjusts the delay of QCLK in response to MRS_Q, the third delay sub-circuit 1123 adjusts the delay of IBCLK in response to MRS_IB, and the fourth delay sub-circuit 1124 adjusts the delay of QBCLK in response to MRS_QB. At this time, the first target control code received by the first delay sub-circuit 1121 is the ground signal VSS, so the first phase clock signal ICLK is not adjusted in delay, that is, the delay of ICLK is fixed. If the logic value of the judgment result signal is 0, that is, the phase sequence of the first phase clock signal ICLK and the third phase clock signal IBCLK is inconsistent at the current time and the last time when the self-refresh mode is exited, the first target control code, the second target control code, the third target control code and the fourth target control code output by the control circuit 111 are MRS_IB, MRS_QB, VSS and MRS_Q in turn, and the delay circuit 112 adjusts the delays of ICLK, QCLK and QBCLK respectively in response to the target control codes. That is, the first delay sub-circuit 1121 adjusts the delay of ICLK in response to MRS_IB, the second delay sub-circuit 1122 adjusts the delay of QCLK in response to MRS_QB, and the fourth delay sub-circuit 1124 adjusts the delay of QBCLK in response to MRS_Q. At this time, the third target control code received by the third delay sub-circuit 1123 is the ground signal VSS, so the third phase clock signal IBCLK is not adjusted in delay, that is, the delay of IBCLK is fixed.

[0073] In this way, the specific values of the second phase control code MRS_Q, the third phase control code MRS_IB and the fourth phase control code MRS_QB do not need to be changed, and only the control circuit 111 needs to select the first group of control codes or the second group of control codes as the target control codes according to the judgment result signal, that is, select the second phase control code MRS_Q, the third phase control code MRS_IB and the fourth phase control code MRS_QB to control which phase clock signals, so as to switch the delay control of the four phase clock signals. In the case that the sequence of the four phase clock signals generated when the memory exits the self-refresh mode changes, the parameters set in the mode register at the last time can still be used to quickly and accurately adjust the phase difference between the four phase clock signals in the subsequent duty cycle adjustment training mode.

[0074] In some embodiments, the second phase control code MRS Q, the third phase control code MRS IB and the fourth phase control code MRS QB are stored and outputted by a mode register. In the duty cycle adjustment training mode, the phase difference between the internal four-phase clock signals is adjusted by setting parameters in the mode register to adjust the delay of the four-phase clock signals, so that the difference between the phase difference and 90 degrees is less than a preset value, i.e. the phase difference between the internal four-phase clock signals approaches 90 degrees.

[0075] In some embodiments, as shown in FIG. 7, the first delay sub-circuit 1121 includes a first capacitor unit 11211 and an even number of first inverters connected in sequence, the input terminal of the first inverter at the head receives the first phase clock signal ICLK, the output terminal of the last inverter outputs the first target clock signal ICLK_out, the first capacitor unit 11211 receives the first target control code and is connected to the output terminal of a certain first inverter; the second delay sub-circuit includes a second capacitor unit and an even number of second inverters connected in sequence, the input terminal of the second inverter at the head receives the second phase clock signal QCLK, the output terminal of the last inverter outputs the second target clock signal QCLK_out, the second capacitor unit receives the second target control code and is connected to the output terminal of a certain second inverter; the third delay sub-circuit includes a third capacitor unit and an even number of third inverters connected in sequence, the input terminal of the third inverter at the head receives the third phase clock signal IBCLK, the output terminal of the last inverter outputs the third target clock signal IBCLK_out, the third capacitor unit receives the third target control code and is connected to the output terminal of a certain third inverter; the fourth delay sub-circuit includes a fourth capacitor unit and an even number of fourth inverters connected in sequence, the input terminal of the fourth inverter at the head receives the fourth phase clock signal QBCLK, the output terminal of the last inverter outputs the fourth target clock signal QBCLK_out, the fourth capacitor unit receives the fourth target control code and is connected to the output terminal of a certain fourth inverter.

[0076] It should be noted that the first delay sub-circuit 1121, the second delay sub-circuit 1122, the third delay sub-circuit 1123 and the fourth delay sub-circuit 1124 have the same structure, and here the first delay sub-circuit 1121 is taken as an example. In FIG. 7, the first delay sub-circuit 1121 includes two first inverters INV1 and INV2, the input terminal of the first inverter INV1 at the head receives the first phase clock signal ICLK, the output terminal of the INV1 is connected with the input terminal of the first inverter INV2 at the tail, the output terminal of the INV2 outputs the first target clock signal ICLK_out, and the first capacitor unit 11211 is connected at the output terminal of the INV1 to adjust the delay on the transmission path. It can be understood that in other embodiments, the number of first inverters can also be 4, 6, 8, etc. even number, and the first capacitor unit can also be connected at the output terminal of any first inverter to adjust the delay on the transmission path.

[0077] The first capacitor unit 11211 is composed of MOS capacitor, as shown in FIG. 7, including N PMOS and N NMOS, the gates of all PMOS and NMOS are connected together, and are connected with the output terminal of a certain first inverter. The first target control code includes Code <n:1>and CodeN <n:1>the source and drain of each PMOS are connected and receive the first target control code Code <n:1>One of the NMs, the source and drain of each NM are connected and receive the first target control code CodeN <n:1>one of the codes. Among them, Code <n:1>CodeN <n:1>Each bit of the corresponding middle phase is opposite to each other, for example Code CodeN are inverses of each other, i is less than or equal to N, and i is greater than or equal to 1. In this way, the received Code and CodeN equivalent capacitance value of a pair of PMOS and NMOS controlled by Code and CodeN In this way, the equivalent capacitance value of the first capacitance unit 11211 can be adjusted by adjusting the first target control code, so as to adjust the delay of the first delay sub-circuit 1121. The initial value of the first target control code is 0, so when the judgment result signal is 1 and the first target control code is the ground signal VSS, the first target control code still maintains the initial value and does not adjust the delay of the first delay sub-circuit 1121. When the judgment result signal is 0 and the first target control code is MRS IB, the first delay sub-circuit 1121 adjusts the delay of ICLK in response to MRS IB.

[0078] In addition, according to different actual application requirements, the first capacitance unit 11211 can also be composed of other capacitance structures with adjustable capacitance values.

[0079] In some embodiments, as shown in FIG. 8, the judgment circuit 12 includes: a latch 121 configured to receive a first flag signal and a second flag signal, the first flag signal being used to represent that the no operation command NOP is sampled by the rising edge of the first phase clock signal ICLK at the self-refresh mode exit time, and the second flag signal being used to represent that the no operation command NOP is sampled by the rising edge of the third phase clock signal IBCLK at the self-refresh mode exit time, if the first flag signal is in the effective state, a first level phase representation signal is output, if the second flag signal is in the effective state, a second level phase representation signal is output; a comparison unit 122, which is electrically connected with the latch 121 and is configured to receive and store the phase representation signal, and compare the level state of the phase representation signal received at the current self-refresh mode exit time with the level state of the phase representation signal received at the last self-refresh mode exit time, if the level states of the two times are consistent, a judgment result signal with a logic value of 1 is output, if the level states of the two times are inconsistent, a judgment result signal with a logic value of 0 is output.

[0080] For example, at the moment when the self-refresh mode is exited, the no-operation command NOP received by the memory is sampled by the rising edge of the first phase clock signal ICLK, the first flag signal is in the active state, for example, low level, the latch 121 outputs the phase representation signal of the first level, representing that the phase of the first phase clock signal ICLK is ahead of the phase of the third phase clock signal IBCLK; at the moment when the self-refresh mode is exited, the no-operation command NOP received by the memory is sampled by the rising edge of the third phase clock signal IBCLK, the second flag signal is in the active state, for example, low level, the latch 121 outputs the phase representation signal of the second level, representing that the phase of the first phase clock signal ICLK is behind the phase of the third phase clock signal IBCLK. The comparison unit 122 stores and compares the phase representation signals received in the current time and the last time, and outputs the judgment result signal by comparing the level states of the phase representation signals received in the current time and the last time, so as to know whether the phases of the first phase clock signal ICLK and the third phase clock signal IBCLK are consistent at the moments when the self-refresh mode is exited in the current time and the last time.

[0081] In some embodiments, the latch is an SR latch, the first end of the SR latch receives the first flag signal, the second end of the SR latch receives the second flag signal, and the output end outputs the phase representation signal. When the first flag signal is low level, the phase representation signal output by the SR latch is high level, and when the second flag signal is low level, the phase representation signal output by the SR latch is low level. At this time, the first level is high level and the second level is low level.

[0082] In summary, for a high-speed memory, the clock control circuit 10 provided by the embodiment of the present disclosure comprises: a delay adjustment circuit 11 configured to receive a first phase clock signal ICLK, a second phase clock signal QCLK, a third phase clock signal IBCLK, a fourth phase clock signal QBCLK and a judgment result signal, and adjust the delay of the second phase clock signal QCLK, the third phase clock signal IBCLK and the fourth phase clock signal QBCLK, or adjust the delay of the first phase clock signal ICLK, the second phase clock signal QCLK and the fourth phase clock signal QBCLK according to the judgment result signal when the memory is in a duty cycle adjustment training mode, and output a first target clock signal ICLK_out, a second target clock signal QCLK_out, a third target clock signal IBCLK_out and a fourth target clock signal QBCLK_out; a judgment circuit 12 electrically connected with the delay adjustment circuit 11 and configured to record the phase sequence of the first phase clock signal ICLK and the third phase clock signal IBCLK at the moment when the memory exits a self-refresh mode, and compare the phase sequence with the phase sequence of the first phase clock signal ICLK and the third phase clock signal IBCLK at the moment when the memory exited the self-refresh mode last time, and output the judgment result signal according to whether the two phase sequences are consistent. When the memory is in the self-refresh mode, the external clock signal is not accepted, and when the memory exits the self-refresh mode, the external clock signal is received again. At this time, duty cycle adjustment training is needed to adjust the phase difference between the internal four-phase clock signals. The phase sequence of the first phase clock signal and the third phase clock signal at the moment when the memory exits the self-refresh mode is recorded and compared with the phase sequence at the moment when the memory exited the self-refresh mode last time, and the delay of the second phase clock signal, the third phase clock signal and the fourth phase clock signal is adjusted, or the delay of the first phase clock signal, the second phase clock signal and the fourth phase clock signal is adjusted according to whether the two phase sequences are consistent. This is conducive to more accurately and quickly adjusting the phase difference between the four-phase clock signals in the duty cycle adjustment training mode, saving the time of duty cycle adjustment training, improving the accuracy of the four-phase clock signals, and ensuring the quality of the final memory output data.

[0083] In another embodiment of the present disclosure, referring to FIG. 9, a schematic structural diagram of a memory 50 provided by the embodiment of the present disclosure is shown. As shown in FIG. 9, the memory 50 at least comprises the aforementioned clock control circuit 10.

[0084] In some embodiments, the memory at least meets one of the following specifications: DDR3, DDR4, DDR5, DDR6, LPDDR3, LPDDR4, LPDDR5 and LPDDR6.

[0085] In some embodiments, as shown in FIG. 10, the memory 50 further comprises: a receiving circuit 20 configured to receive an external clock signal CKT and output an internal clock signal, the internal clock signal having the same frequency as the external clock signal; a frequency divider 30 electrically connected to the receiving circuit 20 and configured to receive the internal clock signal, divide the internal clock signal by two, and generate a first phase clock signal ICLK, a second phase clock signal QCLK, a third phase clock signal IBCLK, and a fourth phase clock signal QBCLK; and a delay-locked loop 40 electrically connected to the frequency divider 30 and the clock control circuit 10 and configured to adjust the phase of at least one of the first phase clock signal ICLK, the second phase clock signal QCLK, the third phase clock signal IBCLK, and the fourth phase clock signal QBCLK so that the phase difference between the at least one of the first phase clock signal ICLK, the second phase clock signal QCLK, the third phase clock signal IBCLK, and the fourth phase clock signal QBCLK and the external clock signal CKT is less than a preset value.

[0086] The frequency of the first phase clock signal ICLK, the second phase clock signal QCLK, the third phase clock signal IBCLK, and the fourth phase clock signal QBCLK generated by the frequency divider 30 is half of the frequency of the external clock signal CKT. Ideally, the phases of ICLK, QCLK, IBCLK, and QBCLK should be 90 degrees apart in sequence. However, in a high-frequency environment, the duty cycle of the external clock signal CKT received by the memory is unstable, and the phase difference between the four-phase clock signals output by the frequency divider is not ideally 90 degrees, and there is a large gap. In the duty cycle adjustment training mode, the clock control circuit 10 adjusts the phase difference between the four-phase clock signals so that the difference between the phase difference and 90 degrees is less than a preset value, i.e., so that the phase difference between the internal four-phase clock signals approaches 90 degrees. The delay-locked loop (DLL) 40 is used to synchronize the internal clock signal with the external clock signal CKT, so that the rising edge of at least one of ICLK, QCLK, IBCLK, and QBCLK is aligned with the rising edge of the external clock signal CKT within an error tolerance range, i.e., so that the phase difference between the at least one of ICLK, QCLK, IBCLK, and QBCLK and the external clock signal CKT is less than a preset value. In this way, the quality of the memory data output can be ensured.

[0087] In the embodiment of the present disclosure, for the memory 50, when the memory is in the self-refresh mode, the external clock signal is not accepted, when the memory exits the self-refresh mode, the external clock signal is received again, at this time, the duty cycle adjustment training needs to be performed to adjust the phase difference between the internal four-phase clock signals. The phase sequence of the first phase clock signal and the third phase clock signal at the current and last self-refresh mode exit time is recorded and compared, and according to whether the phase sequences at the two times are consistent, the delay of the second phase clock signal, the third phase clock signal and the fourth phase clock signal is adjusted, or the delay of the first phase clock signal, the second phase clock signal and the fourth phase clock signal is adjusted, which is beneficial to more accurately and quickly adjust the phase difference between the four-phase clock signals in the duty cycle adjustment training mode, saves the time of duty cycle adjustment training, improves the accuracy of the four-phase clock signals, and ensures the quality of the final memory output data.

[0088] In another embodiment of the present disclosure, referring to FIG. 11, a flowchart of a clock control method provided by the embodiment of the present disclosure is shown. As shown in FIG. 11, the method can include:

[0089] S101, recording the phase sequence of the first phase clock signal and the third phase clock signal at the self-refresh mode exit time of the memory, and comparing the phase sequence of the first phase clock signal and the third phase clock signal at the current and last self-refresh mode exit time, to determine whether the phase sequences at the two times are consistent;

[0090] S102, if the phase sequences at the two times are consistent, adjusting the delay of the second phase clock signal, the third phase clock signal and the fourth phase clock signal when the memory is in the duty cycle adjustment training mode; if the phase sequences at the two times are inconsistent, adjusting the delay of the first phase clock signal, the second phase clock signal and the fourth phase clock signal when the memory is in the duty cycle adjustment training mode.

[0091] In some embodiments, specifically including: the memory receives a no operation command NOP at the self-refresh mode exit time, if the no operation command NOP is sampled by the rising edge of the first phase clock signal, it is recorded that the phase of the first phase clock signal leads the phase of the third phase clock signal; if the no operation command NOP is sampled by the rising edge of the third phase clock signal, it is recorded that the phase of the first phase clock signal lags behind the phase of the third phase clock signal.

[0092] In some embodiments, if the phase sequence of the two times is consistent, the first set of control codes is used to adjust the delay of the second phase clock signal, the third phase clock signal and the fourth phase clock signal when the memory is in the duty cycle adjustment training mode; if the phase sequence of the two times is inconsistent, the second set of control codes is used to adjust the delay of the first phase clock signal, the second phase clock signal and the fourth phase clock signal when the memory is in the duty cycle adjustment training mode.

[0093] The clock control method provided by the embodiments of the present disclosure can record and compare the phase sequence of the first phase clock signal and the third phase clock signal at the current time and the time when the self-refresh mode is exited last time, and adjust the delay of the second phase clock signal, the third phase clock signal and the fourth phase clock signal or adjust the delay of the first phase clock signal, the second phase clock signal and the fourth phase clock signal according to whether the phase sequence of the two times is consistent, which is beneficial to more accurately and quickly adjust the phase difference between the four-phase clock signals in the duty cycle adjustment training mode, save the time of duty cycle adjustment training, improve the accuracy of the four-phase clock signals, and ensure the quality of the final memory output data.

[0094] The above merely describes preferred embodiments of the present disclosure and is not intended to limit the protection scope of the present disclosure. It should be noted that in the present disclosure, the terms "comprise", "contain" or any other variants thereof are intended to cover non-exclusive inclusion, so that the process, method, article or device including a series of elements not only includes those elements, but also includes other elements not explicitly listed or inherent to such process, method, article or device. Without more limitations, the element defined by the statement "comprises a…" does not exclude the presence of another identical element in the process, method, article or device including the element. The above sequence number of the embodiments of the present disclosure only describes the embodiments and does not represent the advantages and disadvantages of the embodiments. The methods disclosed in the several method embodiments provided by the present disclosure can be combined arbitrarily without conflict to obtain new method embodiments. The features disclosed in the several product embodiments provided by the present disclosure can be combined arbitrarily without conflict to obtain new product embodiments. The features disclosed in the several method or device embodiments provided by the present disclosure can be combined arbitrarily without conflict to obtain new method or device embodiments. The above merely describes specific embodiments of the present disclosure, but the protection scope of the present disclosure is not limited thereto, and any person skilled in the art can easily think of changes or replacements within the technical range disclosed by the present disclosure, which should be covered within the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be subject to the protection scope of the claims.

Claims

1. A clock control circuit (10), characterized by, The application is applied to a memory (50), comprising: a delay adjustment circuit (11) configured to receive a first phase clock signal, a second phase clock signal, a third phase clock signal, a fourth phase clock signal and a judgment result signal, and to adjust the delay of the second phase clock signal, the third phase clock signal and the fourth phase clock signal or the delay of the first phase clock signal, the second phase clock signal and the fourth phase clock signal according to the judgment result signal when the memory is in a duty cycle adjustment training mode, and to output a first target clock signal, a second target clock signal, a third target clock signal and a fourth target clock signal; a judgment circuit (12) electrically connected with the delay adjustment circuit and configured to record the phase sequence of the first phase clock signal and the third phase clock signal at the time when the memory exits from a self-refresh mode, to compare the phase sequence with the phase sequence of the first phase clock signal and the third phase clock signal at the time when the memory exits from the self-refresh mode last time, and to output the judgment result signal according to whether the two phase sequences are consistent.

2. The clock control circuit of claim 1, wherein, The recording of the phase sequence of the first phase clock signal and the third phase clock signal at the time when the memory exits from the self-refresh mode comprises: the memory receives a no operation command (NOP) at the time when the memory exits from the self-refresh mode, and if the no operation command (NOP) is sampled by the rising edge of the first phase clock signal, it is recorded that the phase of the first phase clock signal leads the phase of the third phase clock signal; if the no operation command (NOP) is sampled by the rising edge of the third phase clock signal, it is recorded that the phase of the first phase clock signal lags behind the phase of the third phase clock signal; the comparison of the phase sequence of the first phase clock signal and the third phase clock signal at the time when the memory exits from the self-refresh mode with the phase sequence of the first phase clock signal and the third phase clock signal at the time when the memory exits from the self-refresh mode last time according to whether the two phase sequences are consistent, and the output of the judgment result signal, comprise: if the two phase sequences are consistent, the judgment result signal with a logic value of 1 is output; if the two phase sequences are not consistent, the judgment result signal with a logic value of 0 is output.

3. The clock control circuit of claim 2, wherein, The delay adjustment circuit comprises: a control circuit (111) configured to receive a first group of control codes, a second group of control codes and the judgment result signal, to output the first group of control codes as target control codes if the logic value of the judgment result signal is 1, and to output the second group of control codes as the target control codes if the logic value of the judgment result signal is 0; the first group of control codes are used to adjust the delay of the second phase clock signal, the third phase clock signal and the fourth phase clock signal, and the second group of control codes are used to adjust the delay of the first phase clock signal, the second phase clock signal and the fourth phase clock signal; a delay circuit (112) electrically connected with the control circuit and configured to receive the first phase clock signal, the second phase clock signal, the third phase clock signal, the fourth phase clock signal and the target control codes, Adjusting the time delay of the second phase clock signal, the third phase clock signal and the fourth phase clock signal according to the target control code, or adjusting the time delay of the first phase clock signal, the second phase clock signal and the fourth phase clock signal, and outputting the first target clock signal, the second target clock signal, the third target clock signal and the fourth target clock signal.

4. The clock control circuit of claim 3, wherein, The target control code comprises a first target control code, a second target control code, a third target control code and a fourth target control code, and the time delay circuit comprises: a first time delay sub-circuit (1121) configured to receive the first phase clock signal and the first target control code, adjust the time delay of the first phase clock signal according to the first target control code, and output the first target clock signal; a second time delay sub-circuit (1122) configured to receive the second phase clock signal and the second target control code, adjust the time delay of the second phase clock signal according to the second target control code, and output the second target clock signal; a third time delay sub-circuit (1123) configured to receive the third phase clock signal and the third target control code, adjust the time delay of the third phase clock signal according to the third target control code, and output the third target clock signal; a fourth time delay sub-circuit (1124) configured to receive the fourth phase clock signal and the fourth target control code, adjust the time delay of the fourth phase clock signal according to the fourth target control code, and output the fourth target clock signal.

5. The clock control circuit of claim 4, wherein, The first group of control codes comprises, in sequence, a ground signal, a second phase control code, a third phase control code and a fourth phase control code; the second group of control codes comprises, in sequence, the third phase control code, the fourth phase control code, a ground signal and the second phase control code; and the control circuit comprises: a first selection unit (1111) configured to receive a ground signal, the third phase control code and a judgment result signal, output the ground signal as the first target control code if the logic value of the judgment result signal is 1, and output the third phase control code as the first target control code if the logic value of the judgment result signal is 0; a second selection unit (1112) configured to receive the second phase control code, the fourth phase control code and the judgment result signal, output the second phase control code as the second target control code if the logic value of the judgment result signal is 1, and output the fourth phase control code as the second target control code if the logic value of the judgment result signal is 0; a third selection unit (1113) configured to receive the third phase control code, a ground signal and the judgment result signal, output the third phase control code as the third target control code if the logic value of the judgment result signal is 1, and output the ground signal as the third target control code if the logic value of the judgment result signal is 0; and a fourth selection unit (1114) configured to receive the fourth phase control code, the second phase control code and the judgment result signal, output the fourth phase control code as the fourth target control code if the logic value of the judgment result signal is 1, and output the second phase control code as the fourth target control code if the logic value of the judgment result signal is 0. A fourth selection unit (1114) is configured to receive the fourth phase control code, the second phase control code and the judgment result signal, output the fourth phase control code as the fourth target control code if the logic value of the judgment result signal is 1, and output the second phase control code as the fourth target control code if the logic value of the judgment result signal is 0.

6. The clock control circuit of claim 5, wherein, The second phase control code, the third phase control code and the fourth phase control code are stored and output by a mode register.

7. The clock control circuit of claim 4, wherein The first delay sub-circuit comprises a first capacitor unit and an even number of first inverters, the even number of first inverters are connected in sequence, an input terminal of a first inverter at the head receives the first phase clock signal, an output terminal of a first inverter at the tail outputs the first target clock signal, and the first capacitor unit receives the first target control code and is connected to an output terminal of a certain first inverter; The second delay sub-circuit comprises a second capacitor unit and an even number of second inverters, the even number of second inverters are connected in sequence, an input terminal of a second inverter at the head receives the second phase clock signal, an output terminal of a second inverter at the tail outputs the second target clock signal, and the second capacitor unit receives the second target control code and is connected to an output terminal of a certain second inverter; The third delay sub-circuit comprises a third capacitor unit and an even number of third inverters, the even number of third inverters are connected in sequence, an input terminal of a third inverter at the head receives the third phase clock signal, an output terminal of a third inverter at the tail outputs the third target clock signal, and the third capacitor unit receives the third target control code and is connected to an output terminal of a certain third inverter; The fourth delay sub-circuit comprises a fourth capacitor unit and an even number of fourth inverters, the even number of fourth inverters are connected in sequence, an input terminal of a fourth inverter at the head receives the fourth phase clock signal, an output terminal of a fourth inverter at the tail outputs the fourth target clock signal, and the fourth capacitor unit receives the fourth target control code and is connected to an output terminal of a certain fourth inverter.

8. The clock control circuit of claim 2, wherein, The judgment circuit comprises: A latch (121) is configured to receive a first flag signal and a second flag signal, the first flag signal is used to represent that the no operation command NOP is sampled by the rising edge of the first phase clock signal at the self-refresh mode exit time, the second flag signal is used to represent that the no operation command NOP is sampled by the rising edge of the third phase clock signal at the self-refresh mode exit time, output a first level of phase representation signal if the first flag signal is in an effective state, and output a second level of the phase representation signal if the second flag signal is in an effective state; A comparison unit (122) is electrically connected with the latch and is configured to receive and store the phase representation signal, and output a first phase control code if the first level of the phase representation signal is received, output a second phase control code if the second level of the phase representation signal is received, and output a third phase control code if the first level and the second level of the phase representation signal are both received. The phase representation signal received at the current self-refresh mode exit time is compared with the phase representation signal received at the last self-refresh mode exit time, and if the level states of the two times are consistent, the determination result signal with a logic value of 1 is output, and if the level states of the two times are inconsistent, the determination result signal with a logic value of 0 is output.

9. The clock control circuit of claim 8, wherein, The latch is an SR latch, a first end of the SR latch receives the first flag signal, a second end of the SR latch receives the second flag signal, and an output end of the SR latch outputs the phase representation signal.

10. A memory (50) characterized by, The clock control circuit comprises the memory and the clock control circuit according to any one of claims 1-9.

11. The memory of claim 10, wherein, Further comprising: a receiving circuit (20) configured to receive an external clock signal and output an internal clock signal, the internal clock signal having the same frequency as the external clock signal; a frequency divider (30) electrically connected with the receiving circuit and configured to receive the internal clock signal, divide the internal clock signal by two, and generate the first phase clock signal, the second phase clock signal, the third phase clock signal and the fourth phase clock signal; a delay-locked loop (40) electrically connected with the frequency divider and the clock control circuit and configured to adjust the delay of at least one of the first phase clock signal, the second phase clock signal, the third phase clock signal and the fourth phase clock signal, so that the phase difference between the at least one of the first phase clock signal, the second phase clock signal, the third phase clock signal and the fourth phase clock signal and the external clock signal is less than a preset value.

12. The memory of claim 11, wherein, The memory meets the DDR5 specification.

13. A clock control method, characterized by, The memory meets the DDR5 specification. The memory meets the DDR5 specification. At the self-refresh mode exit time of the memory, the phase sequence of the first phase clock signal and the third phase clock signal is recorded, and the phase sequence of the first phase clock signal and the third phase clock signal at the last self-refresh mode exit time is compared to determine whether the phase sequences of the two times are consistent (S101); 14. The clock control method according to claim 13, wherein If the phase sequences of the two times are consistent, the delay of the second phase clock signal, the third phase clock signal and the fourth phase clock signal is adjusted when the memory is in the duty cycle adjustment training mode, and if the phase sequences of the two times are inconsistent, the delay of the first phase clock signal, the second phase clock signal and the fourth phase clock signal is adjusted when the memory is in the duty cycle adjustment training mode (S102). The memory meets the DDR5 specification. The memory receives a no-operation command NOP at the self-refresh mode exit time, and if the no-operation command NOP is sampled by the rising edge of the first phase clock signal, it is recorded that the phase of the first phase clock signal leads the phase of the third phase clock signal, and if the no-operation command NOP is sampled by the rising edge of the third phase clock signal, it is recorded that the phase of the first phase clock signal lags behind the phase of the third phase clock signal.

15. The clock control method according to claim 13, wherein if the phase sequence is consistent, adjusting the time delay of the second phase clock signal, the third phase clock signal and the fourth phase clock signal when the memory is in the duty cycle adjustment training mode; if the phase sequence is inconsistent, adjusting the time delay of the first phase clock signal, the second phase clock signal and the fourth phase clock signal when the memory is in the duty cycle adjustment training mode, comprising: if the phase sequence is consistent, adjusting the time delay of the second phase clock signal, the third phase clock signal and the fourth phase clock signal using a first group of control codes when the memory is in the duty cycle adjustment training mode; if the phase sequence is inconsistent, adjusting the time delay of the first phase clock signal, the second phase clock signal and the fourth phase clock signal using a second group of control codes when the memory is in the duty cycle adjustment training mode.

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