Cache performance evaluation method and apparatus, and electronic device and readable storage medium

Abstract

The embodiments of the present application relate to the technical field of computers. Provided are a cache performance evaluation method and apparatus, and an electronic device and a readable storage medium. The method comprises: in response to multiple memory access operations for each memory access request in a test program, acquiring memory access statistical information of the test program, wherein the memory access statistical information at least comprises a hit count of each memory access request in a cache to be evaluated; and evaluating the performance of said cache on the basis of the memory access statistical information and a memory access mode of each memory access request.

Description

Cache performance evaluation method and device, electronic equipment and readable storage medium

[0001] The present application claims priority to the Chinese patent application No. 202410634793.6, filed on May 21, 2024, and entitled "Cache performance evaluation method and device, electronic equipment and readable storage medium", the whole content of which is incorporated herein by reference. TECHNICAL FIELD

[0002] The present application relates to the technical field of computer, in particular to a cache performance evaluation method and device, electronic equipment and readable storage medium. BACKGROUND

[0003] With the development of computer technology, the design requirements of central processing unit (CPU) are also getting higher and higher, so it is necessary to evaluate the performance of the designed CPU.

[0004] Among them, the cache is an important part of the CPU, which is used to store data or instructions that the CPU needs to access frequently, and can improve the running speed and efficiency of the CPU. The performance of the cache has a great influence on the performance of the CPU, therefore, how to evaluate the performance of the cache has become a problem to be solved.

[0005] SUMMARY

[0006] The embodiments of the present application provide a cache performance evaluation method and device, electronic equipment and readable storage medium, which can solve the problem of how to evaluate the performance of the cache in the prior art.

[0007] In order to solve the above problem, the embodiments of the present application disclose a cache performance evaluation method, which comprises:

[0008] In response to a plurality of memory access operations of each memory access request in a test program, obtaining memory access statistical information of the test program; the memory access statistical information at least includes the hit number of each memory access request in the cache to be evaluated;

[0009] Based on the memory access statistical information and the memory access mode of each memory access request, the performance of the cache to be evaluated is evaluated.

[0010] On the other hand, the embodiments of the present application disclose a cache performance evaluation device, which comprises:

[0011] The acquisition module is configured to acquire memory access statistical information of the test program in response to a plurality of memory access operations of each memory access request in the test program, wherein the memory access statistical information at least includes a hit number of each memory access request in the cache to be evaluated.

[0012] The first evaluation module is configured to evaluate the performance of the cache to be evaluated based on the memory access statistical information and a memory access mode of each memory access request.

[0013] In another aspect, the embodiments of the present application further disclose an electronic device, which comprises a processor, a memory, a communication interface and a communication bus, the processor, the memory and the communication interface complete communication with each other through the communication bus; the memory is used to store executable instructions, and the executable instructions make the processor execute the cache performance evaluation method.

[0014] The embodiments of the present application further disclose a readable storage medium, when the instructions in the readable storage medium are executed by the processor of the electronic device, the electronic device can execute the cache performance evaluation method.

[0015] The embodiments of the present application further disclose a computer program product comprising instructions which, when executed on a computer, cause the computer to perform the cache performance evaluation method.

[0016] The embodiments of the present application have the following advantages:

[0017] The embodiments of the present application provide a cache performance evaluation method, which comprises the following steps: acquiring memory access statistical information of a test program in response to a plurality of memory access operations of each memory access request in the test program, wherein the memory access statistical information at least includes a hit number of each memory access request in a cache to be evaluated; and evaluating the performance of the cache to be evaluated based on the memory access statistical information and a memory access mode of each memory access request. In this way, the performance of the cache can be evaluated by acquiring the hit number of the memory access request in the cache. Meanwhile, the performance of the cache can be evaluated from the dimension of different memory access modes by using the memory access statistical information and the memory access mode of each memory access request, so that multi-dimensional evaluation is realized, and the accuracy and interpretability of the cache performance evaluation are improved.

[0018] The above description is only a summary of the technical solutions of the present application, in order to more clearly understand the technical means of the present application, the specific embodiments of the present application can be implemented according to the content of the description, and in order to make the above and other purposes, characteristics and advantages of the present application more obvious and easy to understand, the following specific embodiments of the present application are described. BRIEF DESCRIPTION OF DRAWINGS

[0019] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings needed to be used in the embodiments or prior art description. Obviously, the drawings in the following description are some embodiments of the present application, and other drawings can be obtained by those skilled in the art without any creative effort on the basis of these drawings.

[0020] Fig. 1 is a flow chart of steps of an embodiment of a cache performance evaluation method of the present application;

[0021] Fig. 2 is a schematic diagram of obtaining a hit number according to an embodiment of the present application;

[0022] Fig. 3 is a schematic diagram of obtaining a memory access mode according to an embodiment of the present application;

[0023] Fig. 4 is a schematic diagram of a statistical result according to an embodiment of the present application;

[0024] Fig. 5 is another schematic diagram of a statistical result according to an embodiment of the present application;

[0025] Fig. 6 is a structural block diagram of an embodiment of a cache performance evaluation device of the present application;

[0026] Fig. 7 is a structural block diagram of an electronic device for cache performance evaluation according to an embodiment of the present application. Specific embodiments

[0027] In order to make the objectives, technical solutions and advantages of the embodiments of the present application clearer, the following will combine the drawings in the embodiments of the present application to make a clear and complete description of the technical solutions in the embodiments of the present application. Obviously, the described embodiments are some of the embodiments of the present application, but not all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without any creative effort fall within the scope of protection of the present application.

[0028] Those skilled in the art should understand that in the disclosure of the present application, the terms "first", "second", "third", "fourth", "fifth" and the like are only used to distinguish different structures, and do not limit the number, connection relationship and the like of specific structures. In addition, the orientation or position relationship indicated by "longitudinal", "transverse", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer" and the like is based on the orientation or position relationship shown in the drawings. It is only for the convenience of describing the present application and simplifying the description, and does not indicate or imply that the indicated device or element must have a particular orientation, be constructed and operated in a particular orientation. Therefore, the above terms cannot be understood as a limitation on the present application.

[0029] Method embodiments

[0030] Referring to FIG. 1, a flow chart of steps of an embodiment of a cache performance evaluation method is shown. The method can include the following steps:

[0031] In step 101, in response to a plurality of memory access operations of each memory access request in a test program, memory access statistics of the test program are obtained. The memory access statistics at least include a hit number of each memory access request in a cache to be evaluated.

[0032] In step 102, based on the memory access statistics and a memory access pattern of each memory access request, a performance of the cache to be evaluated is evaluated.

[0033] It should be noted that for the above steps 101-102, the cache in the present application can be a cache system design with a cache function, which can belong to a processor to be evaluated. It can be understood that a processor usually includes modules or systems with different functions, and in order to evaluate the functions of the processor, different modules or systems are usually evaluated respectively. The embodiment of the present application is an evaluation of the cache system. Alternatively, the embodiment of the present application can be applied to a processor to be evaluated, or can be applied to a processor simulator, for example, gem5. The cache to be evaluated can be built on gem5. Gem5 is a cycle-accurate processor simulator, and the processor core simulation is cycle-accurate. The simulation of the cache system can be performed once at a certain frequency, for example, every update period (a variable in the simulator for indicating how many times the processor state is updated per second, TICK). The memory access statistics are obtained once every clock cycle.

[0034] The test program can be pre-built, randomly built, or built according to certain test requirements. The embodiment of the present application does not limit this. Specifically, the test program can include a plurality of different memory access requests. The memory access patterns of each memory access request can be the same or different. In addition, the memory access request in the embodiment of the present application refers to a load instruction (load).

[0035] Specifically, the embodiment of the present application can pre-build a plurality of memory access requests with different memory access patterns to obtain a test program. The memory access pattern refers to a memory access type of the memory access request, which can include step-by-step memory access, indirect memory access, etc.

[0036] The embodiment of the present application can obtain the memory access statistical information of the test program when each memory access request performs a memory access operation. It should be noted that the memory access statistical information at least includes the hit times of each memory access request in the cache to be evaluated. Specifically, the cache refers to the memory between the CPU and the memory, which usually has a small capacity but a high speed. When the processor performs a memory access request, it usually obtains data from the cache first. When the required data exists in the cache, it indicates that the memory access request hits the cache, and the memory does not need to be accessed at this time. Correspondingly, when the required data does not exist in the cache, it indicates that the memory access request misses the cache, and the required data needs to be obtained from the memory. When the CPU reads the data in the memory, it usually reads part of the data to be loaded in the cache, so that the data to be read subsequently by the CPU already exists in the cache, which can effectively improve the performance. Further, since the efficiency of obtaining data from the cache is higher than that of obtaining data from the memory, the more the times of the memory access request hitting the cache, the higher the efficiency of the processor in executing the memory access request, that is, the better the performance of the cache, and the better the performance of the processor. Therefore, the embodiment of the present application can evaluate the performance of the cache by obtaining the memory access statistical information of the test program.

[0037] In the embodiment of the present application, one memory access request corresponds to one static load instruction. During the execution of the test program, one static load instruction can be executed as a dynamic instruction multiple times. Further, in the embodiment of the present application, one memory access request can be executed multiple times, so as to obtain the hit times of each memory access request in the cache during multiple executions.

[0038] Specifically, the above-mentioned operation of obtaining the memory access statistical information can be obtained by the performance counter of the processor. The performance counter of the processor can count the memory access behavior of the processor when executing the test program, and can count the hit times of different memory access requests in the cache and in the memory during multiple executions. The embodiment of the present application can read the performance counter by a specified software tool (for example, the performance analysis tool perf), to obtain the hit times of each memory access request in the cache. Further, the above-mentioned memory access mode can be that the test program containing different memory access modes is constructed in advance when constructing the test program, so as to ensure that the memory access mode of each memory access request is known. Alternatively, the test program in the embodiment of the present application can also be constructed randomly. After obtaining the memory access statistical information, each memory access request can be output and displayed, so that the relevant staff evaluates the memory access mode of each memory access request, so as to obtain the memory access mode of each memory access request by receiving the input information of the relevant staff. In the embodiment of the present application, the memory access operation can be data access or instruction access.

[0039] It can be understood that the more the access request hits in the cache, the better the performance of the cache. For the same cache system, the performance of the access request for different access modes may be different, and therefore, the embodiments of the present application can evaluate the performance of the cache in combination with the access mode of each access request. Specifically, the embodiments of the present application can pre-divide different performance levels, and determine the performance level of the cache for different access modes according to the hit number of each access request in the cache and the access mode of each access request. For example, different performance levels of different access modes can be associated with respective hit number intervals in the cache. The performance level can be used to represent the performance. The higher the performance level, the larger the interval value of the hit number interval in the cache. Further, different weight coefficients can be set for different access modes according to actual access requirements, and the performance level of each access mode is obtained by weighting calculation, and then the performance level corresponding to the cache to be evaluated is obtained.

[0040] Further, the method provided by the embodiments of the present application can be applied to a processor, so that the above different performance levels can be pre-uploaded to the processor.

[0041] For example, there are access request A and access request B in the test program, the access mode of A is indirect access, and the access mode of B is step access. If the access statistics information indicates that the hit number of A in the cache is 1850707 times, the hit number in the memory is 3059 times, and the hit number of B in the cache is 2584088 times, and the hit number in the memory is 645 times, it can be obtained that the access performance of the cache for step access is better, and the access performance of the cache for indirect access is worse. Further, the performance of the cache to be evaluated for different access modes can be further divided according to the preset performance level.

[0042] The cache performance evaluation method provided by the embodiments of the present application can obtain the access statistics information of the test program by responding to the multiple access operations of each access request in the test program. The access statistics information at least includes the hit number of each access request in the cache to be evaluated. The performance of the cache to be evaluated is evaluated based on the access statistics information and the access mode of each access request. In this way, the performance of the cache can be evaluated by obtaining the hit number of the access request in the cache. At the same time, the performance of the cache can be evaluated from the dimension of different access modes by the access statistics information and the access mode of each access request, multi-dimensional evaluation is realized, and the accuracy and interpretability of the cache performance evaluation are improved.

[0043] Further, the embodiment of the present application evaluates the performance of the cache based on the hit times and the memory access modes of the memory access requests. Compared with the evaluation manner using the cache miss rate or the average instruction per cycle (IPC), the cache miss rate can only reflect the proportion of the misses in the memory access requests received by the cache, and cannot locate the missing time. The program segments with the same miss rate can have different influences on the IPC due to the different missing times, and thus the program segments with greater influences on the performance of the cache cannot be determined. The IPC is sensitive to the branch prediction and other factors, and cannot directly reflect the coverage of the cache system on the memory access. The embodiment of the present application can evaluate the performance of the cache from the dimensions of different memory access modes through the hit times of the memory access requests and the memory access modes of the memory access requests, realize multi-dimensional evaluation, determine the memory access modes with greater influences on the performance of the cache, and improve the accuracy of the cache performance evaluation.

[0044] In an optional embodiment of the present application, the storage hierarchy of the cache to be evaluated comprises at least two levels; and the operation of obtaining the memory access statistical information of the test program in response to the multiple memory access operations of the memory access requests in the test program in step 101 can specifically include the following steps:

[0045] The hit times of the memory access requests in the caches of each level are obtained as the memory access statistical information in response to the multiple memory access operations of the memory access requests in the test program.

[0046] The above level refers to different memory hierarchies. In the case where the storage hierarchy of the cache comprises at least two levels, the cache is a multi-level cache system, and the caches of different levels have different speeds. The processor often accesses the caches of different levels in the order of levels, that is, the highest level cache, that is, the first level cache (L1 cache) is accessed first to obtain the required data. When the L1 cache hits, the data is returned. When the L1 cache does not exist, the second level cache (L2 cache) is accessed. When the lowest level cache, that is, the last level cache still does not hit, the memory is accessed. Meanwhile, the higher the level of the cache, the smaller the capacity and the faster the reading speed. Correspondingly, the more the hit times of the memory access requests in the cache of a higher level, the better the performance of the cache system, and the more the hit times of the memory access requests in the cache of a lower level, the general performance of the cache system.

[0047] Specifically, when the storage hierarchy of the cache to be evaluated comprises at least two levels, the memory access statistics can also be obtained by a performance counter, which can count the number of hits of the memory access requests in the caches of different levels respectively, and the hit distribution in the storage hierarchy can be obtained.

[0048] Further, when the cache to be evaluated comprises at least two levels of caches, the number of hits of each memory access request in the caches of each level can be obtained as the memory access statistics in the embodiment of the application, so that the performance of the cache can be evaluated more accurately and more finely according to the number of hits of the caches of different levels.

[0049] Optionally, the operation of obtaining the number of hits of each memory access request in the caches of each level can specifically comprise the following steps in the embodiment of the application:

[0050] S11, setting a plurality of hit counters for each memory access request, wherein different hit counters correspond to different levels of caches.

[0051] S12, for each memory access operation of each memory access request, encapsulating the memory access request as a request packet and setting a level parameter in the request packet.

[0052] S13, during the return of the request packet from a target level, the level parameter in the request packet is increased by 1 every time a level is passed, wherein the target level is the level of the cache where the request packet hits.

[0053] S14, determining the target level of the memory access request based on the value of the level parameter in the returned request packet, and increasing the hit counter corresponding to the target level by 1 from the hit counter corresponding to the memory access request.

[0054] S15, when the evaluation condition is met, obtaining the number of hits of each memory access request in the caches of each level based on the current values of the hit counters corresponding to each memory access request.

[0055] Specifically, for the steps S11-S15, the embodiment of the application can set a plurality of hit counters for each memory access request, wherein different hit counters can correspond to different levels of caches, so that each hit counter of each memory access request can count the number of hits of different levels of caches respectively.

[0056] The request packet is a message packet. Encapsulating the memory access request as a request packet can facilitate the transmission of the request packet in each level of the cache. Further, the application embodiment sets a level parameter in the request packet, and the level parameter is used to represent the level of the cache hit by the request packet. Specifically, a variable can be created as the level parameter in the request packet. Further, the initial value of the level parameter can be set as 0 after the creation of the level parameter. Specifically, the level parameter can be an integer variable, and can also be a floating-point number, which is not limited in the application embodiment.

[0057] Further, after the request packet is sent out, the request packet is first transmitted to the L1 cache. If the target data required to be accessed exists in the L1 cache, the target data is added to the request packet, and the request packet is returned. If the target data does not exist in the L1 cache, the request packet is continuously transmitted to the L2 cache, and the request packet is returned from the hit level in sequence until the target data is accessed. In the application embodiment, the level parameter in the request packet is increased by 1 when the request packet is returned from each level. In this way, the level of the cache hit by the request packet can be determined by the level parameter, which facilitates the hit counter to count.

[0058] Correspondingly, after the returned request packet is obtained, the target level of the cache hit by the memory access request can be determined according to the value of the level parameter, so that the hit counter corresponding to the target level is increased by 1, and the hit times of different levels are counted.

[0059] The evaluation condition can be that the execution times of the test program reach a preset number threshold, or the execution time of the test program reaches an execution time threshold, which can be set according to actual needs, and the application embodiment is not limited in this regard. Further, after the evaluation condition is met, the current value of each hit counter corresponding to each memory access request can be determined as the hit times of each memory access request in each level of the cache.

[0060] Further, the program counter (PC value) of each memory access request can be used as the index value of the memory access request in the application embodiment, and the PC value can be used to distinguish the hit counter corresponding to different memory access requests, that is, the PC value of the memory access request is used as the identifier of the hit counter corresponding to the memory access request. Correspondingly, after the returned request packet is received, the hit counters corresponding to all memory access requests can be indexed based on the PC value of the memory access request carried in the request packet, and the hit counter with the same identifier as the PC value is determined as the hit counter of the memory access request corresponding to the request packet.

[0061] In the embodiments of the present application, a plurality of hit counters are set for each memory access request; different hit counters correspond to different levels of cache; for each memory access operation of each memory access request, the memory access request is encapsulated as a request packet, and a level parameter is set in the request packet; during the return of the request packet from a target level, the level parameter in the request packet is increased by 1 every time a level is passed; the target level is the level of the cache where the request packet hits; the target level of the memory access request is determined based on the value of the level parameter in the returned request packet, and the hit counter corresponding to the target level is increased by 1 from the hit counter corresponding to the memory access request; in the case of meeting the evaluation condition, the hit times of each memory access request in the cache at each level are obtained based on the current values of the hit counters corresponding to each memory access request. In this way, by setting the level parameter, the level of the cache hit by the memory access request can be determined, and by setting a plurality of hit counters for one memory access request, the hit times of the memory access request in the caches at different levels can be counted separately.

[0062] Exemplarily, referring to FIG. 2, a schematic diagram of obtaining the hit times is shown, and in FIG. 2, a cache containing three levels of cache is taken as an example, which are private first-level data cache, private second-level cache and shared third-level cache. The processor core 1 can execute a test program to obtain memory access statistical information through a performance counter in the processor. The cache queue refers to the Load Store queue. The other core refers to the processor core other than the processor core 1.

[0063] Specifically, a memory access request (Load instruction) at A completes address calculation and sends a memory access request to the cache. The memory access request is encapsulated in a message packet (Message Packet), and is passed in each level of the cache. The message packet stores metadata, which can include a level parameter d, the source of the cache line, the priority of the replacement algorithm corresponding to the cache line, etc. According to FIG. 2, the message packet hits the first-level cache, and the message packet is returned directly, at which time the level parameter is still 0, indicating that the target level of the message packet is the first-level cache. The metadata of the message packet is recorded in the Load Store queue of the processor performance model.

[0064] The message packet corresponding to a Load instruction at B is returned from the hit storage level. According to FIG. 2, the message packet hits the memory, and when the message packet is returned, the level parameter in the request packet is increased by 1 every time a level is passed, and when the message packet is returned to the cache queue, the level parameter in the message packet is 3, indicating that the target level of the message packet is the memory. A Load instruction at C is processed and completed, at which time the response of the memory access instruction in the cache system can be counted according to the metadata stored in the Load Store queue.

[0065] As shown in FIG. 2, the performance counter can include five table entries, i.e., a program counter, a level 1 cache hit counter, a level 2 cache hit counter, a level 3 cache hit counter and a main memory access counter, wherein the program counter is used to record the PC value of the memory access request. As shown in FIG. 2, it indicates that the memory access request with PC value 0xABC hits K times in the level 1 cache, hits L times in the level 2 cache, hits M times in the level 3 cache and hits N times in the main memory.

[0066] Further, according to the proportion returned by each level of cache in each Load instruction, the efficiency of the cache system can be reflected. If a memory access request is returned by the L3 cache or the main memory more, the IPC of the program segment where the memory access request is located is usually also low.

[0067] Optionally, the memory access statistical information further includes an index value of each memory access request. After the operation of obtaining the memory access statistical information of the test program, the embodiment of the present application can further include the following steps:

[0068] S21, based on the index value of each memory access request, output the source code corresponding to each index value to an information display interface.

[0069] S22, receive mode information input by a user for the source code corresponding to each index value based on the information display interface, and determine each mode information as the memory access mode of the memory access request corresponding to each index value.

[0070] The index value refers to the PC value of the memory access request. For a static instruction, the PC value is unique and fixed, so the embodiment of the present application can obtain the source code of the corresponding memory access request through the PC value, and output the source code to the information display interface for analysis by the relevant test personnel. Specifically, the source code corresponding to each PC value can be obtained through addr2line. The addr2line is a debugging information reading tool, which can correspond a program counter (PC) to a line of source code.

[0071] Further, the embodiment of the present application can output the source code corresponding to each index value to the information display interface in sequence, and the relevant test personnel can analyze the memory access mode by the displayed source code. The user can input the memory access mode as input information, and then the embodiment of the present application can determine the memory access mode corresponding to the source code by receiving the mode information input by the user.

[0072] Exemplarily, referring to FIG. 3, an acquisition diagram of a memory access mode of the application is shown, in which a high-level language source file refers to a source program of a test program, a compiler can generate a binary executable file containing a code and a data segment and debugging information (for example, DWARF format debugging information, Debugging With Arbitrary Record Formats, DWARF is a debugging information file format used by many compilers and debuggers to support source-level debugging) in a compilation stage, and the debugging information can contain a mapping of a source code and a PC value. When the test program is run on a processor, a performance counter can obtain a statistical result (memory access statistical information). A debugging information reading tool can read a source code corresponding to each memory access request based on the mapping relationship of the source code and the PC value in the debugging information and the statistical result of the performance counter, that is, a high-level language code. Further, the memory access mode of each memory access request can be determined through the high-level language code.

[0073] Further, the embodiment of the application can evaluate the performance of the cache or the effect of the optimization algorithm based on the memory access mode, the cache hit count at each level in the memory access statistical information, and the cache hit ratio at each level.

[0074] In the embodiment of the application, the memory access statistical information further includes index values of the memory access requests; the source code corresponding to each index value is output to an information display interface based on the index values of the memory access requests; mode information input by a user for the source code corresponding to each index value based on the information display interface is received, and the mode information is determined as the memory access mode of the memory access request corresponding to each index value. In this way, by setting the information display interface, the memory access mode corresponding to each memory access request can be determined by receiving the input of the user.

[0075] Optionally, the operation of evaluating the performance of the cache to be evaluated based on the memory access statistical information and the memory access mode of each memory access request can specifically include the following steps:

[0076] S31, for each memory access request, acquiring a reference hit count corresponding to the memory access mode of the memory access request.

[0077] S32, evaluating the performance of the cache to be evaluated based on the hit count and the reference hit count of each memory access request.

[0078] The reference hit count can be set in advance, and can be the hit count of the memory access request of each memory access mode in the cache with performance meeting the requirements, so that the performance of the cache to be evaluated can be evaluated by the reference hit count of different memory access modes in the embodiment of the application.

[0079] Specifically, for any access request, the reference hit number can be taken as a performance threshold, and in a case where the hit number of the access request is not less than the reference hit number corresponding to the access mode of the access request, it is determined that the cache performance of the to-be-evaluated cache for the access mode meets the requirement. Correspondingly, in a case where the hit number of the access request is less than the reference hit number corresponding to the access mode of the access request, it is determined that the cache performance of the to-be-evaluated cache for the access mode does not meet the requirement.

[0080] Optionally, the embodiments of the present application can also pre-set reference hit numbers of caches at different levels, which can be hit numbers of access requests of each access mode in each level of cache whose performance meets the requirement. Correspondingly, the above evaluation method can also be combined with the hit numbers in caches at different levels and the reference hit numbers.

[0081] The embodiments of the present application obtain, for each access request, a reference hit number corresponding to an access mode of the access request; and evaluate the performance of the to-be-evaluated cache based on the hit number of each access request and the reference hit number. By setting the reference hit number, the performance of the cache can be effectively evaluated.

[0082] Optionally, the embodiments of the present application can further include:

[0083] S41, using a first optimization algorithm to optimize the to-be-evaluated cache, and based on the optimized cache, re-executing the operation of obtaining the access statistics information of the test program to obtain second access statistics information, and taking the access statistics information corresponding to the cache before optimization as first access statistics information; the second access statistics information includes the hit number of each access request in the optimized cache and the optimization state of the first optimization algorithm when each access request hits the optimized cache.

[0084] S42, evaluating the optimization effect of the first optimization algorithm based on the first access statistics information, the second access statistics information and the access mode of each access request.

[0085] For the above steps S41-S42, the first optimization algorithm refers to an optimization technology for the cache, which can be any prefetcher, prefetching technology, prefetching algorithm or replacement strategy, etc. The first optimization algorithm can be selected according to actual needs, and the embodiments of the present application do not limit this. It can be understood that the first optimization algorithm can optimize the performance of the cache, and the optimization effects of different optimization algorithms are different, and the embodiments of the present application can evaluate the optimization effect of the first optimization algorithm.

[0086] Specifically, the embodiments of the present application can evaluate the optimization effect of the first optimization algorithm from the perspective of different memory access modes. Specifically, for the memory access mode of any memory access request, the hit number of the memory access request can be obtained from the first memory access statistical information as a first number, and the hit number of the memory access request can be obtained from the second memory access statistical information as a second number. If the second number is greater than the first number, it indicates that the first optimization algorithm can improve the processing efficiency of the cache for the memory access mode. Further, if the second number is greater than the first number, and the difference between the two is greater than a preset threshold, it indicates that the first optimization algorithm can greatly improve the processing efficiency of the cache for the memory access mode, and the optimization effect is better.

[0087] Exemplarily, referring to FIG. 4, a statistical result diagram of the present application is shown. As shown in FIG. 4, it shows 6 memory access requests, and the PC values thereof are 0x119fa, 0x119fe, 0x119ea, 0x119f0, 0x119f8, and 0x119f4. The row where each PC value is located corresponds to the hit number of the memory access request corresponding to the PC value in the level 1 cache, the level 2 cache, the level 3 cache, and the memory. Taking the memory access modes of 0x119fa and 0x119fe as indirect memory access, and the other requests as step-by-step memory access as an example, it can be seen that 0x119fa and 0x119fe have more hit numbers in the level 3 cache and the memory than other memory access requests. It can be known that the performance of the cache for the indirect memory access mode is poor, and the performance for the step-by-step memory access mode is good.

[0088] Exemplarily, referring to FIG. 5, another statistical result diagram of the present application is shown. As shown in FIG. 5, it is the statistical result after the cache is optimized by using a certain hardware prefetching technology. It can be seen that the hardware prefetching technology can increase the hit number of indirect memory access 0x119fa and 0x119fe in the level 1 cache, and reduce the hit number in the level below the level 2 cache, which can effectively improve the processing efficiency of the cache system for the indirect memory access mode.

[0089] In addition, this statistical result also reflects that the prefetching technology still has room for improvement. The prefetching technology uses step-by-step memory access predictor and indirect memory access identification technology to handle the prefetching of the level 1 indirect memory access. Ideally, the number of indirect memory access instructions returned from the level 1 cache should be similar to the step-by-step memory access it depends on. However, in the actual result, the number of indirect memory access returned from the level 1 cache is still less than the step-by-step memory access it depends on. Therefore, it can be concluded that the prefetching technology still has room for improvement.

[0090] Meanwhile, after the pre-fetching technology is applied, the IPC of the test program does not increase, which can be caused by other modules in the processor core, such as branch prediction. If the prior art is used to evaluate the pre-fetching technology only by using the IPC, a conclusion that the pre-fetching technology is useless will be obtained. According to the number of hits and the access mode, the embodiment of the present application can be used to evaluate that when the number of cache hits increases, the number of requests sent to the second cache also decreases, so that the hit rate of the second cache decreases. If the cache hit rate is used to evaluate the technology, an intuitive result cannot be obtained, or an incorrect conclusion that the technology reduces the hit rate of the second cache is obtained, and the evaluation effect is poor.

[0091] The present application can solve the difficulty of evaluating the pre-fetcher and the replacement algorithm of the cache optimization mechanism by the traditional method, and the poor evaluation effect.

[0092] Further, the embodiment of the present application can also record the reasons for cache hits at each level in the metadata of the message packet, which can be a hit after pre-fetching by the pre-fetching technology 1, a hit after pre-fetching by the pre-fetching technology 2, or a previous access to the address. Further, the reasons for cache misses can also be recorded in the metadata, such as a first access not covered by the pre-fetcher, a pre-fetcher covered but not retrieved in time, replaced out of the cache due to capacity reasons, replaced out of the cache due to conflict reasons, and the like. Further, the cache and the optimization algorithm can be further refined and evaluated according to the metadata.

[0093] Further, the second access statistical information can include the optimization state of the first optimization algorithm when each access request hits the optimized cache. The optimization state refers to the optimization parameter of the optimization algorithm, which is different for different optimization algorithms. For example, when the first optimization algorithm is a replacement algorithm, the optimization state can be the least recently used distance (LRU) of the least recently used replacement algorithm or the re-reference interval predicted by the re-reference interval prediction replacement algorithm (RRIP). Specifically, the optimization state can be obtained by reading the current value of the optimization parameter of the optimization algorithm.

[0094] The embodiment of the present application optimizes the to-be-evaluated cache by using a first optimization algorithm, re-executes the operation of obtaining the memory access statistical information of the test program based on the optimized cache, obtains second memory access statistical information, and takes the memory access statistical information corresponding to the cache before optimization as first memory access statistical information; and evaluates the optimization effect of the first optimization algorithm based on the first memory access statistical information, the second memory access statistical information and the memory access mode of each memory access request. In this way, effective evaluation of the first optimization algorithm can be realized.

[0095] Optionally, the embodiment of the present application can further include the following.

[0096] S51, optimizing the optimized cache by using a second optimization algorithm, and re-executing the operation of obtaining the memory access statistical information of the test program to obtain third memory access statistical information; the third memory access statistical information includes the optimization state of the first optimization algorithm and the optimization state of the second optimization algorithm when each memory access request hits the optimized cache.

[0097] S52, evaluating the optimization effect of the first optimization algorithm and the second optimization algorithm based on the second memory access statistical information and the third memory access statistical information.

[0098] The second optimization algorithm refers to an optimization technology for a cache, which can be any prefetcher, prefetch technology, prefetch algorithm or replacement strategy different from the first optimization algorithm, and can be selected according to actual needs, and the embodiment of the present application does not limit this.

[0099] Specifically, in some cases, a cache system can use two or more optimization technologies at the same time, and the effects of different optimization technologies can be superimposed on each other or offset each other to make the cache effect worse. For example, if a hardware prefetch technology and a replacement strategy can both effectively optimize the performance of a computer system when compared with a baseline alone, but when both methods are used at the same time, the hardware prefetch may increase memory access traffic and access the data earlier than normal, which does not meet the assumptions of the replacement algorithm design, so the effect of using both methods at the same time can be worse than using either method alone.

[0100] On this basis, the embodiment of the application further optimizes the cache using a second optimization algorithm after optimizing the cache using the first optimization algorithm. At this time, the cache applies the first optimization algorithm and the second optimization algorithm simultaneously. At this time, the embodiment of the application can use a test program to perform multiple access operations to obtain third memory access statistical information. The third memory access statistical information can include the optimization state of the first optimization algorithm and the optimization state of the second algorithm when each memory access request hits the cache.

[0101] Further, the embodiment of the application can evaluate the overall optimization effect of the first optimization algorithm and the second optimization algorithm through the second memory access statistical information and the third memory access statistical information. Specifically, the optimization state in the second memory access statistical information can be compared with the optimization state of the first optimization algorithm in the third memory access statistical information. If the optimization state of the first optimization algorithm in the third memory access statistical information deteriorates, it can be concluded that the optimization effect of the first optimization algorithm and the second optimization algorithm applied simultaneously is poor.

[0102] For example, taking the first optimization algorithm as a replacement algorithm and the second optimization algorithm as a hardware prefetching technology as an example, before the hardware prefetching technology is added, the reference interval (optimization state) predicted by the replacement algorithm for a certain memory access request is relatively long. However, after the hardware prefetching technology is added, the reference interval predicted for the memory access instruction becomes shorter. Therefore, it can be evaluated that the replacement algorithm is affected by the prefetching, resulting in poor comprehensive optimization effect.

[0103] In summary, the embodiment of the application provides a cache performance evaluation method. The method obtains memory access statistical information of a test program by responding to multiple memory access operations of each memory access request in the test program. The memory access statistical information at least includes the hit times of each memory access request in the cache to be evaluated. The performance of the cache to be evaluated is evaluated based on the memory access statistical information and the memory access mode of each memory access request. In this way, the performance of the cache can be evaluated by obtaining the hit times of the memory access request in the cache. At the same time, the performance of the cache can be evaluated from different dimensions of memory access mode through the memory access statistical information and the memory access mode of each memory access request, realizing multi-dimensional evaluation and improving the accuracy of cache performance evaluation.

[0104] Further, the embodiment of the present application evaluates the performance of the cache based on the hit times and the memory access modes of the memory access requests. Compared with the evaluation manner using the cache miss rate or the average instruction per cycle (IPC), the cache miss rate can only reflect the proportion of the misses in the memory access requests received by the cache, and cannot locate the timing of the misses. The program segments with the same miss rate can have different influences on the IPC due to different timing of the misses, and thus the program segments with greater influences on the performance of the cache cannot be determined. The IPC is sensitive to the branch prediction and other factors, and cannot directly reflect the coverage of the cache system on the memory access. The embodiment of the present application can evaluate the performance of the cache from the dimensions of different memory access modes through the hit times of the memory access requests and the memory access modes of the memory access requests, implement multi-dimensional evaluation, determine the memory access modes with greater influences on the performance of the cache, and improve the accuracy and interpretability of the cache performance evaluation.

[0105] Further, the embodiment of the present application can also provide a basis for the design optimization of the cache system and the improvement of the optimization algorithm. The embodiment of the present application can assist the design of the hardware cache system, and can also be conveniently used in the simulator or the simulation environment.

[0106] It should be noted that, for the method embodiments, in order to simply describe, they are all described as a series of action combinations, but those skilled in the art should know that the embodiments of the present application are not limited to the order of the actions described, because according to the embodiments of the present application, certain steps can be performed in other order or simultaneously. Secondly, those skilled in the art should know that the embodiments described in the specification all belong to preferred embodiments, and the actions involved are not necessarily the necessary of the embodiments of the present application.

[0107] Device embodiment

[0108] Referring to FIG. 6, a structural block diagram of an embodiment of a cache performance evaluation device of the present application is shown, and the device 20 can specifically include:

[0109] The obtaining module 201 is configured to obtain memory access statistical information of a test program in response to multiple memory access operations of each memory access request in the test program, and the memory access statistical information at least includes the hit times of each memory access request in a cache to be evaluated;

[0110] The first evaluation module 202 is configured to evaluate the performance of the cache to be evaluated based on the memory access statistical information and the memory access modes of each memory access request.

[0111] Optionally, the cache storage hierarchy to be evaluated comprises at least two levels; and the obtaining module 201 is specifically configured to:

[0112] In response to a plurality of memory access operations of each memory access request in the test program, the number of hits of each memory access request in each level of cache is obtained as the memory access statistical information.

[0113] Optionally, the obtaining module 201 comprises:

[0114] a setting sub-module configured to set a plurality of hit counters for each memory access request, wherein different hit counters correspond to different levels of cache;

[0115] a packaging sub-module configured to, for each memory access operation of each memory access request, package the memory access request into a request packet and set a level parameter in the request packet;

[0116] a parameter sub-module configured to, in a process of returning of the request packet from a target level, increase the level parameter in the request packet by 1 each time a level is passed, wherein the target level is a level of cache where the memory access request hits;

[0117] a determining sub-module configured to determine a target level of the memory access request based on a value of the level parameter in the returned request packet, and increase, from a hit counter corresponding to the memory access request, a hit counter corresponding to the target level by 1;

[0118] a number obtaining sub-module configured to, in a case where an evaluation condition is met, obtain the number of hits of each memory access request in each level of cache based on current values of the hit counters corresponding to each memory access request.

[0119] Optionally, the memory access statistical information further comprises an index value of each memory access request; and the apparatus further comprises:

[0120] an output module configured to output source code corresponding to each index value to an information display interface based on the index value of each memory access request;

[0121] a receiving module configured to receive mode information input by a user for the source code corresponding to each index value based on the information display interface, and determine the mode information as a memory access mode of the memory access request corresponding to each index value.

[0122] Optionally, the first evaluation module comprises:

[0123] a reference obtaining sub-module configured to, for each memory access request, obtain a reference hit number corresponding to a memory access mode of the memory access request;

[0124] The evaluation submodule is configured to evaluate the performance of the cache to be evaluated based on the hit times of the memory access requests and the reference hit times.

[0125] Optionally, the apparatus further comprises:

[0126] The first optimization module is configured to optimize the cache to be evaluated by using a first optimization algorithm, re-execute the operation of obtaining the memory access statistical information of the test program based on the optimized cache to obtain second memory access statistical information, and take the memory access statistical information corresponding to the cache before optimization as first memory access statistical information; the second memory access statistical information comprises the hit times of the memory access requests in the optimized cache and the optimization state of the first optimization algorithm when the memory access requests hit the optimized cache.

[0127] The second evaluation module is configured to evaluate the optimization effect of the first optimization algorithm based on the first memory access statistical information, the second memory access statistical information and the memory access mode of each memory access request.

[0128] Optionally, the apparatus further comprises:

[0129] The second optimization module is configured to optimize the optimized cache by using a second optimization algorithm, and re-execute the operation of obtaining the memory access statistical information of the test program to obtain third memory access statistical information; the third memory access statistical information comprises the optimization state of the first optimization algorithm and the optimization state of the second optimization algorithm when the memory access requests hit the optimized cache.

[0130] The third evaluation module is configured to evaluate the optimization effect of the first optimization algorithm and the second optimization algorithm based on the second memory access statistical information and the third memory access statistical information.

[0131] In summary, the embodiment of the present application provides a cache performance evaluation apparatus, which obtains memory access statistical information of a test program by responding to multiple memory access operations of each memory access request in the test program; the memory access statistical information at least comprises hit times of each memory access request in a cache to be evaluated; and the performance of the cache to be evaluated is evaluated based on the memory access statistical information and the memory access mode of each memory access request. In this way, the performance of the cache can be evaluated by obtaining the hit times of the memory access requests in the cache. Meanwhile, the performance of the cache can be evaluated from the dimension of different memory access modes by using the memory access statistical information and the memory access mode of each memory access request, multi-dimensional evaluation is realized, and the accuracy of the cache performance evaluation is improved.

[0132] For the system embodiment, as it is basically similar to the method embodiment, the description is relatively simple, and the relevant parts are referred to the part of the method embodiment.

[0133] Each embodiment in the specification is described in a progressive manner, and each embodiment focuses on the difference from other embodiments. The same and similar parts between embodiments are referred to each other.

[0134] For the cache performance evaluation device in the above embodiments, the specific manner in which each module performs the operation has been described in detail in the embodiment related to the method, and will not be described in detail here.

[0135] The embodiment of the present application also provides an electronic device, comprising: a processor, a memory for storing processor-executable instructions, wherein the processor is configured to perform the cache performance evaluation method described above.

[0136] Referring to FIG. 7, it is a structural schematic diagram of an electronic device provided by the embodiment of the present application. As shown in FIG. 7, the electronic device comprises: a processor, a memory, a communication interface and a communication bus, the processor, the memory and the communication interface complete the communication among each other through the communication bus; the memory is used to store at least one executable instruction, and the executable instruction makes the processor execute the cache performance evaluation method of the foregoing embodiment.

[0137] It should be noted that the electronic device in the embodiment of the present application includes a mobile electronic device and a non-mobile electronic device.

[0138] The processor can be a CPU (Central Processing Unit, central processor), a general-purpose processor, a DSP (Digital Signal Processor, digital signal processor), an ASIC (Application Specific Integrated Circuit, application specific integrated circuit), an FPGA (Field Programmable Gate Array, field programmable gate array) or other programmable device, transistor logic device, hardware component or any combination thereof. The processor can also be a combination of computing functions, such as one or more microprocessor combinations, combinations of DSP and microprocessor, etc.

[0139] The communication bus can include a path for transmitting information between the memory and the communication interface. The communication bus can be a PCI (Peripheral Component Interconnect) bus, an EISA (Extended Industry Standard Architecture) bus, or the like. The communication bus can be divided into an address bus, a data bus, a control bus, and the like. For ease of representation, only one line is shown in FIG. 7, but it does not mean that there is only one bus or only one type of bus.

[0140] The memory can be a ROM (Read Only Memory) or other type of static storage device that can store static information and instructions, a RAM (Random Access Memory) or other type of dynamic storage device that can store information and instructions, an EEPROM (Electrically Erasable Programmable Read Only Memory), a CD-ROM (Compact Disc Read Only Memory), a magnetic tape, a floppy disk, an optical data storage device, or the like.

[0141] The embodiment of the present application further provides a non-transitory computer readable storage medium, when instructions in the storage medium are executed by a processor of an electronic device (a server or a terminal), the processor can execute the cache performance evaluation method shown in FIG. 1.

[0142] The embodiment of the present application further provides a computer program product containing instructions, when the computer program product is run on a computer, the computer can execute the cache performance evaluation method shown in FIG. 1.

[0143] The embodiment of the present application further provides a chip, the chip includes a processor and a communication interface, the communication interface and the processor are coupled, the processor is used for running a program or instructions, realizes each process of the cache performance evaluation method embodiment, and can achieve the same technical effect, to avoid repetition, here is not repeated.

[0144] It should be understood that the chip mentioned in the embodiment of the present application can also be referred to as a system-level chip, a system chip, a chip system, or a system-on-chip, and the like.

[0145] Each embodiment in the specification is described in a progressive manner, and each embodiment focuses on the difference from other embodiments. The same and similar parts between each embodiment can be referred to each other.

[0146] Those skilled in the art should understand that the embodiments of the present application can be provided as a method, device, or computer program product. Therefore, the embodiments of the present application can be realized wholly or partially by software, hardware, firmware, or any combination thereof. When realized by software, the embodiments of the present application can be realized wholly or partially in the form of a computer program product. The computer program product includes one or more computer instructions. When loaded and executed by a computer, the computer instructions wholly or partially produce the processes or functions described in the embodiments of the present application. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable devices. The computer instructions can be stored in a computer-readable storage medium or transferred from one computer-readable storage medium to another computer-readable storage medium, for example, the computer instructions can be transferred from one website, computer, server, or data center to another website, computer, server, or data center through a wired (for example, coaxial cable, optical fiber, digital subscriber line (DSL)) or wireless (for example, infrared, wireless, microwave, etc.) manner. The computer-readable storage medium can be any available medium accessible by a computer or a data storage device such as a server, data center, etc. that includes one or more available media sets. The available medium can be a magnetic medium (for example, a floppy disk, a hard disk, a magnetic tape), an optical medium (for example, a DVD), or a semiconductor medium (for example, a solid state disk (SSD)), etc.

[0147] The embodiments of the present application are described with reference to flowcharts and / or block diagrams according to the processes of the method, terminal device (system), and computer program product of the embodiments of the present application. It should be understood that each flow and / or block in the flowcharts and / or block diagrams, and the combination of the flows and / or blocks in the flowcharts and / or block diagrams can be realized by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing terminal device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing terminal device produce the apparatus for implementing the functions specified in one or more flows in the flowcharts and / or one or more blocks in the block diagrams.

[0148] These computer program instructions can also be stored in a computer-readable storage medium that can cause the computer or other programmable data processing terminal device to work in a predictive manner, so that the instructions stored in the computer-readable storage medium produce a manufactured product including instruction apparatus that implements the functions specified in one or more flows in the flowcharts and / or one or more blocks in the block diagrams.

[0149] These computer program instructions can also be loaded into a computer or other programmable data processing devices, so that a series of operation steps are performed on the computer or other programmable devices to generate computer-implemented processes, thus the instructions executed on the computer or other programmable devices provide the steps for implementing the functions specified in one or more flows in the flowchart and / or one or more blocks in the block diagram.

[0150] Although the preferred embodiments of the application have been described, those skilled in the art will be able to make additional changes and modifications to these embodiments once they grasp the fundamental inventive concepts. Therefore, the appended claims are intended to cover all the changes and modifications within the scope of the embodiments of the application.

[0151] Those skilled in the art can clearly understand that the units and algorithm steps of the examples described in combination with the embodiments disclosed herein can be realized by electronic hardware or a combination of computer software and electronic hardware. Whether the functions are realized in hardware or software mode depends on the specific application and design constraints of the technical solutions. The skilled person can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of the present disclosure.

[0152] Those skilled in the art can clearly understand that, for the convenience and brevity of the description, the specific working processes of the above-described system, device and unit can refer to the corresponding processes in the foregoing method embodiments, which will not be repeated here.

[0153] In the embodiments provided by the present application, it should be understood that the disclosed apparatus and method can be implemented in other ways. For example, the above-described device embodiments are merely schematic, for example, the division of the units is only a logical function division, and actual implementation can have another division manner, for example, a plurality of units or components can be combined or integrated into another system, or some features can be ignored or not executed. In addition, the coupling or direct coupling or communication connection between the units shown or discussed can be indirect coupling or communication connection through some interfaces, devices or units, and can be electrical, mechanical or other forms.

[0154] The units described as separate components can or can not be physically separate, and the components shown as units can or can not be physical units, i.e. can be located in one place, or can be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the embodiments.

[0155] In addition, each functional unit in each embodiment of the present disclosure can be integrated in one processing unit, or each unit can exist physically, or two or more units can be integrated in one unit.

[0156] It can be understood that the embodiments described in the embodiments of the present disclosure can be implemented by hardware, software, firmware, middleware, microcode or a combination thereof. For hardware implementation, the modules, units, sub-units can be implemented in one or more application specific integrated circuits (ASICs), digital signal processors (DSPs), digital signal processing devices (DSPDs), programmable logic devices (PLDs), field programmable gate arrays (FPGAs), general purpose processors, controllers, microcontrollers, microprocessors, other electronic units for performing the functions described in the present disclosure, or a combination thereof.

[0157] For software implementation, the technologies described in the embodiments of the present disclosure can be implemented by modules (such as processes, functions, etc.) for performing the functions described in the embodiments of the present disclosure. The software code can be stored in a memory and executed by a processor. The memory can be implemented in the processor or outside the processor.

[0158] Each embodiment in the specification is described in a relevant manner, and the same or similar parts between each embodiment can be referred to each other. Each embodiment focuses on the difference from other embodiments. In particular, for system embodiments, since they are basically similar to method embodiments, the description is relatively simple, and the relevant parts can be referred to the part of the method embodiment.

[0159] It should be noted that the acquisition of various data related processes in the embodiments of the present application is carried out on the premise of complying with the corresponding data protection regulations and policies of the country where the device is located, and obtaining the authorization given by the corresponding device owner.

[0160] Finally, it needs to be mentioned that in this document, relational terms such as first and second and the like can only be used to distinguish one entity or action from another entity or action, without necessarily requiring or implying any actual such relationship or order between or among the entities or actions. Moreover, the terms "comprises", "comprising", or any other variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but can include other elements not expressly listed or inherent to such process, method, article, or apparatus. An element proceeded by "comprises... a" does not, without more constraints, exclude the presence of additional identical elements in the process, method, article, or apparatus that comprises the element.

Claims

1. A method of cache performance evaluation, wherein, The method comprises: obtaining memory access statistics of the test program in response to a plurality of memory access operations of each memory access request in the test program; the memory access statistics at least comprising a hit number of each memory access request in the cache to be evaluated; evaluating the performance of the cache to be evaluated based on the memory access statistics and a memory access mode of each memory access request.

2. The method of claim 1, wherein, The storage hierarchy of the cache to be evaluated comprises at least two levels; the obtaining of the memory access statistics of the test program in response to a plurality of memory access operations of each memory access request in the test program comprises: obtaining, as the memory access statistics, a hit number of each memory access request in the cache of each level in response to a plurality of memory access operations of each memory access request in the test program.

3. The method of claim 2, wherein, The obtaining of the hit number of each memory access request in the cache of each level comprises: setting a plurality of hit counters for each memory access request; different hit counters correspond to different levels of caches; for any memory access operation of each memory access request, encapsulating the memory access request as a request package and setting a level parameter in the request package; in the process of returning of the request package from a target level, each time a level is passed, the level parameter in the request package is increased by 1; the target level is the level of the cache where the request package hits; determining the target level of the memory access request based on the value of the level parameter in the returned request package, and increasing the hit counter corresponding to the target level in the hit counter corresponding to the memory access request by 1; under the condition of meeting the evaluation condition, obtaining the hit number of each memory access request in the cache of each level based on the current values of the hit counters corresponding to each memory access request.

4. The method of claim 1, wherein, The memory access statistics further comprise index values of each memory access request; after the obtaining of the memory access statistics of the test program, the method further comprises: outputting source code corresponding to each index value to an information display interface based on the index values of each memory access request; receiving mode information input by a user for the source code corresponding to each index value based on the information display interface, and determining the mode information as the memory access mode of the memory access request corresponding to each index value.

5. The method of claim 1, wherein, The evaluating of the performance of the cache to be evaluated based on the memory access statistics and the memory access mode of each memory access request comprises: for each memory access request, obtaining a reference hit number corresponding to the memory access mode of the memory access request; evaluating the performance of the cache to be evaluated based on the hit number and the reference hit number of each memory access request.

6. The method according to any one of claims 1 to 5, wherein, The method further comprises: The first optimization algorithm is used to optimize the cache to be evaluated, and the operation of obtaining the memory access statistical information of the test program is re-executed based on the optimized cache to obtain second memory access statistical information, and the memory access statistical information corresponding to the cache before optimization is taken as first memory access statistical information; the second memory access statistical information includes the hit times of each memory access request in the optimized cache and the optimization state of the first optimization algorithm when each memory access request hits the optimized cache; The optimization effect of the first optimization algorithm is evaluated based on the first memory access statistical information, the second memory access statistical information and the memory access mode of each memory access request.

7. The method of claim 6, wherein, The method further comprises: The second optimization algorithm is used to optimize the optimized cache, and the operation of obtaining the memory access statistical information of the test program is re-executed to obtain third memory access statistical information; the third memory access statistical information includes the optimization state of the first optimization algorithm and the optimization state of the second optimization algorithm when each memory access request hits the optimized cache; The optimization effect of the first optimization algorithm and the second optimization algorithm is evaluated based on the second memory access statistical information and the third memory access statistical information.

8. The method of claim 1, wherein, The method further comprises: According to a preset performance level, the performance of the cache to be evaluated for different memory access modes is divided.

9. The method according to any one of claims 1-5, wherein, The cache comprises a cache system with a cache function.

10. A cache performance evaluation apparatus, wherein, The device comprises: The obtaining module is configured to obtain memory access statistical information of a test program in response to multiple memory access operations of each memory access request in the test program; the memory access statistical information at least includes the hit times of each memory access request in a cache to be evaluated. The first evaluation module is configured to evaluate the performance of the cache to be evaluated based on the memory access statistical information and the memory access mode of each memory access request.

11. The apparatus of claim 10, wherein, The storage hierarchy of the cache to be evaluated comprises at least two levels; the obtaining module 201 is configured to: In response to multiple memory access operations of each memory access request in a test program, obtain the hit times of each memory access request in each level of cache as the memory access statistical information.

12. The apparatus of claim 10, wherein, The obtaining module comprises: The setting submodule is configured to set multiple hit counters for each memory access request; different hit counters correspond to different levels of cache; The packaging submodule is configured to package each memory access request as a request packet for any memory access operation of each memory access request, and set a level parameter in the request packet; The parameter submodule is configured to increase the level parameter in the request packet by 1 every time a level is passed during the return of the request packet from a target level; the target level is the level of the cache where the request packet hits; The determining submodule is configured to determine the target level of the memory access request based on the value of the level parameter in the returned request packet, and increase the hit counter corresponding to the target level by 1 from the hit counter corresponding to the memory access request. The number of times obtaining submodule is configured to obtain the number of times of each memory access request hitting each level of cache based on the current value of each hit counter corresponding to each memory access request when the evaluation condition is met.

13. The apparatus of claim 10, wherein, The memory access statistics further include index values of each memory access request; and the device further includes: An output module is configured to output source code corresponding to each index value to an information display interface based on the index value of each memory access request. A receiving module is configured to receive mode information input by a user for the source code corresponding to each index value based on the information display interface, and determine the mode information as the memory access mode of the memory access request corresponding to each index value.

14. The apparatus of claim 10, wherein, The first evaluation module includes: A reference obtaining submodule is configured to obtain a reference hit number corresponding to the memory access mode of each memory access request. An evaluation submodule is configured to evaluate the performance of the cache to be evaluated based on the hit number and the reference hit number of each memory access request.

15. The apparatus of any one of claims 10 to 14, wherein, The device further includes: A first optimization module is configured to optimize the cache to be evaluated using a first optimization algorithm, re-execute the operation of obtaining the memory access statistics of the test program based on the optimized cache to obtain second memory access statistics, and take the memory access statistics of the cache before optimization as first memory access statistics; the second memory access statistics include the hit number of each memory access request in the optimized cache and the optimization state of the first optimization algorithm when each memory access request hits the optimized cache; A second evaluation module is configured to evaluate the optimization effect of the first optimization algorithm based on the first memory access statistics, the second memory access statistics, and the memory access mode of each memory access request.

16. The apparatus of claim 15, wherein, The device further includes: A second optimization module is configured to optimize the optimized cache using a second optimization algorithm, and re-execute the operation of obtaining the memory access statistics of the test program to obtain third memory access statistics; the third memory access statistics include the optimization state of the first optimization algorithm and the optimization state of the second optimization algorithm when each memory access request hits the optimized cache; A third evaluation module is configured to evaluate the optimization effect of the first optimization algorithm and the second optimization algorithm based on the second memory access statistics and the third memory access statistics.

17. An electronic device, comprising: The electronic device includes a processor, a memory, a communication interface, and a communication bus, the processor, the memory, and the communication interface complete communication with each other through the communication bus; the memory is used to store executable instructions, and the executable instructions make the processor execute the cache performance evaluation method in any one of claims 1 to 9.

18. A readable storage medium, wherein, When the instructions in the readable storage medium are executed by the processor of the electronic device, the processor can execute the cache performance evaluation method in any one of claims 1 to 9.

19. A chip, wherein, The chip comprises a processor and a communication interface, the communication interface is coupled with the processor, and the processor is configured to run programs or instructions to implement the cache performance evaluation method according to any one of claims 1 to 9.

20. A synchronization control apparatus / device, wherein, The apparatus / device is configured to perform the cache performance evaluation method according to any one of claims 1 to 9.

Images