Prefetch control method and apparatus, and electronic device and readable storage medium

Abstract

The embodiments of the present application relate to the technical field of computers. Provided are a prefetch control method and apparatus, and an electronic device and a readable storage medium. The method comprises: dividing an address space of a target cache into at least two cache areas; dynamically monitoring a cache miss popularity and a first prefetch accuracy of each cache area within a preset period; when a target prefetcher corresponding to the target cache satisfies a throttling condition, determining an allowed prefetch count in the cache area on the basis of the cache miss popularity and the first prefetch accuracy; and within the next period, controlling, on the basis of the allowed prefetch count, the sending of a prefetch request corresponding to the cache area.

Description

Prefetch control method and device, electronic equipment and readable storage medium

[0001] Cross-reference of Related Applications

[0002] The present application claims priority to the Chinese patent application No. 202410642924.5, filed on May 22, 2024, and entitled "Prefetch control method and device, electronic equipment and readable storage medium", the whole content of which is incorporated herein by reference. TECHNICAL FIELD

[0003] The present application relates to the technical field of computer, and in particular to a prefetch control method and device, electronic equipment and readable storage medium. BACKGROUND

[0004] In modern processors, a hardware prefetcher predicts the data locations that are likely to be accessed in the future, and fetches these data into the cache in advance, so as to reduce the data access delay when the actual storage access occurs. The prefetch request produced by the hardware prefetcher has no difference with the access request produced by the memory access instruction in the implementation process and the used resources, but the prefetch has problems such as occupying memory access resources, polluting the cache and increasing the memory bus bandwidth. SUMMARY

[0005] The embodiments of the present application provide a prefetch control method and device, electronic equipment and readable storage medium, which can reduce the traffic overhead caused by prefetching while ensuring the performance of the prefetcher, and improve the overall performance of the processor system.

[0006] In one aspect, the embodiments of the present application disclose a prefetch control method, which comprises:

[0007] dividing the address space of a target cache into at least two cache regions;

[0008] dynamically monitoring the cache miss heat and the first prefetch accuracy of each cache region in a preset period;

[0009] in a case where a target prefetcher corresponding to the target cache meets a throttling condition, determining the allowed prefetch quantity of the cache region according to the cache miss heat and the first prefetch accuracy;

[0010] in the next period, controlling the sending of the prefetch request corresponding to the cache region according to the allowed prefetch quantity.

[0011] Optionally, before the sending of the prefetch request corresponding to the cache region is controlled according to the allowed prefetch quantity in the next period, the method further comprises:

[0012] record cache miss heat, first prefetch accuracy and allowed prefetch number of the cache region in the cache region heat table;

[0013] The sending of the prefetch request corresponding to the cache region is controlled according to the allowed prefetch number in the next cycle, including:

[0014] In the case of monitoring the prefetch request sent by the target prefetcher, the cache region heat table is queried according to the prefetch address carried by the prefetch request;

[0015] If there is a first cache region matching the prefetch address in the cache region heat table, the allowed prefetch number and the first prefetch accuracy of the first cache region are read;

[0016] In the case that the allowed prefetch number is greater than 0 and the first prefetch accuracy is greater than or equal to the first threshold, the prefetch request is sent to the prefetch queue, and the value of the allowed prefetch number of the first cache region in the cache region heat table is reduced by n, n is greater than 0.

[0017] Optionally, the method further comprises:

[0018] In the case of meeting the first condition, the prefetch request is intercepted;

[0019] The first condition includes at least one of the following:

[0020] There is no first cache region matching the prefetch address in the cache region heat table;

[0021] The allowed prefetch number of the first cache region is equal to 0;

[0022] The first prefetch accuracy of the first cache region is less than the first threshold.

[0023] Optionally, the address space of the target cache is divided into at least two cache regions, including:

[0024] The cache addresses in the target cache are grouped according to the high bits of the cache addresses as tags, and at least two cache regions are obtained; the cache addresses in the same cache region have the same tags.

[0025] Optionally, the dynamic monitoring of the cache miss heat and the first prefetch accuracy of each cache region in a preset period includes:

[0026] In the prefetch period, the cache miss number, the first prefetch number and the first prefetch hit number corresponding to each cache region are monitored;

[0027] determine a cache miss heat of the cache region according to the cache miss times;

[0028] calculate a first prefetch accuracy rate in the cache region according to the first prefetch issue times and the first prefetch hit times.

[0029] Optionally, the method further comprises:

[0030] acquire a request proportion from the target prefetcher in memory access requests sent by a first cache to a memory in the preset period; the first cache is a cache closest to the memory in a processor system;

[0031] monitor second prefetch issue times and second prefetch hit times of the target prefetcher in the preset period;

[0032] determine a second prefetch accuracy rate of the target prefetcher according to the second prefetch issue times and the second prefetch hit times;

[0033] calculate a prefetch flow of the target prefetcher according to the request proportion and the second prefetch accuracy rate; the prefetch flow is used to indicate an additional memory bus bandwidth flow caused by incorrect prefetches of the target prefetcher;

[0034] in a case where the prefetch flow is greater than a second threshold, determine that the prefetcher meets a throttling condition.

[0035] In another aspect, an embodiment of the present application discloses a prefetch control device, the device comprising:

[0036] a division module configured to divide an address space of a target cache into at least two cache regions;

[0037] a first monitoring module configured to dynamically monitor a cache miss heat and a first prefetch accuracy rate of each cache region in a preset period;

[0038] a first determination module configured to, in a case where a target prefetcher corresponding to the target cache meets a throttling condition, determine an allowed prefetch number of the cache region according to the cache miss heat and the first prefetch accuracy rate;

[0039] a control module configured to, in a next period, control sending of a prefetch request corresponding to the cache region according to the allowed prefetch number.

[0040] Optionally, the device further comprises:

[0041] a recording module configured to record the cache miss heat, the first prefetch accuracy rate and the allowed prefetch number of the cache region in a cache region heat table;

[0042] The control module comprises:

[0043] The query submodule is configured to, in response to monitoring that the target prefetcher sends a prefetch request, query the cache area hotness table according to a prefetch address carried by the prefetch request.

[0044] The reading submodule is configured to, if the cache area hotness table contains a first cache area matching the prefetch address, read a number of allowed prefetches and a first prefetch accuracy of the first cache area.

[0045] The sending submodule is configured to, in response to the number of allowed prefetches being greater than 0 and the first prefetch accuracy being greater than or equal to a first threshold, send the prefetch request to a prefetch queue and reduce the number of allowed prefetches of the first cache area in the cache area hotness table by n, where n is greater than 0.

[0046] Optionally, the control module further comprises:

[0047] The interception submodule is configured to, in response to a first condition being met, intercept the prefetch request.

[0048] The first condition comprises at least one of the following:

[0049] The cache area hotness table does not contain a first cache area matching the prefetch address.

[0050] The number of allowed prefetches of the first cache area is equal to 0.

[0051] The first prefetch accuracy of the first cache area is less than the first threshold.

[0052] Optionally, the segmentation module comprises:

[0053] The segmentation submodule is configured to group cache addresses in the target cache according to high-order bits of the cache addresses as tags, to obtain at least two cache areas; cache addresses in a same cache area have the same tag.

[0054] Optionally, the first monitoring module comprises:

[0055] The monitoring submodule is configured to, in a prefetch period, monitor a cache miss number, a first prefetch sending number and a first prefetch hit number corresponding to each cache area.

[0056] The cache miss hotness determination submodule is configured to determine cache miss hotness of the cache area according to the cache miss number.

[0057] The pre-fetch accuracy rate calculation submodule is configured to calculate a first pre-fetch accuracy rate in the cache area according to the first pre-fetch issuing times and the first pre-fetch hit times.

[0058] Optionally, the apparatus further comprises:

[0059] The acquisition module is configured to acquire a request proportion from the target pre-fetcher in memory access requests sent by a first cache to the memory in the preset period; the first cache is a cache closest to the memory in a processor system.

[0060] The second monitoring module is configured to monitor second pre-fetch issuing times and second pre-fetch hit times of the target pre-fetcher in the preset period.

[0061] The second determination module is configured to determine a second pre-fetch accuracy rate of the target pre-fetcher according to the second pre-fetch issuing times and the second pre-fetch hit times.

[0062] The traffic calculation module is configured to calculate a pre-fetch traffic of the target pre-fetcher according to the request proportion and the second pre-fetch accuracy rate; the pre-fetch traffic is used to indicate an additional memory bus bandwidth traffic caused by incorrect pre-fetching of the target pre-fetcher.

[0063] The throttling determination module is configured to determine that the pre-fetcher satisfies a throttling condition when the pre-fetch traffic is greater than a second threshold.

[0064] In still another aspect, an electronic device is disclosed, which includes a processor, a memory, a communication interface, and a communication bus. The processor, the memory, and the communication interface complete communication with each other through the communication bus. The memory is used to store executable instructions, and the executable instructions make the processor execute the pre-fetch control method described above.

[0065] An embodiment of the present application further discloses a readable storage medium. When instructions in the readable storage medium are executed by a processor of an electronic device, the electronic device can execute the pre-fetch control method described above.

[0066] An embodiment of the present application further discloses a chip, which includes a processor and a communication interface. The communication interface and the processor are coupled. The processor is used to run programs or instructions to implement the pre-fetch control method described above.

[0067] An embodiment of the present application further discloses a pre-fetch control apparatus / device, which includes the apparatus / device (configured to) implement the pre-fetch control method described above.

[0068] Embodiments of the present application include the following advantages:

[0069] The embodiment of the present application provides a pre-fetch control method, the address space of a target cache is divided, the cache miss heat and the first pre-fetch accuracy in each cache area are periodically monitored, in the case that the target pre-fetcher meets the throttling condition, how many pre-fetch requests are sent to the cache area in the next period is determined based on the cache miss heat and the first pre-fetch accuracy of the cache area, the pre-fetch quantity of each cache area is individually controlled, the throttling is performed on a certain cache area, and the normal pre-fetch process of other cache areas in the target cache is not affected, the blindness of global throttling of the target cache is avoided, and the pre-fetch control precision is improved. Moreover, the embodiment of the present application triggers the throttling control only in the case that the target pre-fetcher meets the throttling condition, can ensure that the pre-fetch request generated by the target pre-fetcher is retained as much as possible when the target pre-fetcher does not have a traffic problem, reduces the traffic overhead caused by pre-fetching while ensuring the pre-fetch performance of the target pre-fetcher, and is beneficial to improving the overall performance of the processor system. BRIEF DESCRIPTION OF DRAWINGS

[0070] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings needed to be used in the description of the embodiments of the present application will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative labor.

[0071] Fig. 1 is a step flowchart of an embodiment of a pre-fetch control method of the present application;

[0072] Fig. 2 is an architecture schematic diagram of a processor system of the present application;

[0073] Fig. 3 is a structural block diagram of an embodiment of a pre-fetch control device of the present application;

[0074] Fig. 4 is a structural block diagram of an electronic device provided by the present application. DETAILED DESCRIPTION

[0075] The technical solutions of the embodiments of the present application will be described clearly and completely in combination with the drawings in the embodiments of the present application. Obviously, the described embodiments are some embodiments of the present application, not all embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative labor are within the protection scope of the present application.

[0076] The terms "first", "second", etc. in the specification and claims of the present application are used to distinguish similar objects, and are not used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged under appropriate circumstances, so that the embodiments of the present application can be implemented in an order other than those illustrated or described herein, and the objects distinguished by "first", "second", etc. are generally a class, not limited to the number of objects, for example, the first object can be one or more. In addition, the term "and / or" in the specification and claims is used to describe the relationship between the associated objects, which means that there are three relationships, for example, A and / or B can represent the three cases of A alone, A and B together, and B alone. The character " / " generally represents an "or" relationship between the associated objects. The term "multiple" in the embodiments of the present application means two or more, and other quantifiers are similar.

[0077] Method embodiments

[0078] Referring to FIG. 1, a flowchart of steps of an embodiment of a prefetch control method of the present application is shown, which can specifically include the following steps:

[0079] Step 101, dividing an address space of a target cache into at least two cache regions;

[0080] Step 102, dynamically monitoring cache miss heat and a first prefetch accuracy rate of each cache region in a preset period;

[0081] Step 103, in the case that a target prefetcher corresponding to the target cache meets a throttling condition, determining a number of allowed prefetches of the cache region according to the cache miss heat and the first prefetch accuracy rate;

[0082] Step 104, in the next period, controlling transmission of a prefetch request corresponding to the cache region according to the number of allowed prefetches.

[0083] The prefetch control method provided by the embodiments of the present application can perform throttling control on a hardware prefetcher (i.e. the target prefetcher in the present application). Exemplarily, the prefetch control method provided by the embodiments of the present application can be applied to a prefetch control device, which is deployed on the same layer cache as the target prefetcher, can monitor cache miss events and cache hit events occurring in the current layer cache, and receive a prefetch request generated by the target prefetcher, and decide whether to pass the prefetch request to a subsequent memory access component, such as a prefetch queue. The target prefetcher is used to generate a prefetch request according to memory access information of a target cache. The prefetch control device can prevent any prefetch request triggered from accessing the next layer cache according to a throttling strategy, so as to achieve the purpose of throttling prefetch.

[0084] Referring to FIG. 2, an architecture schematic diagram of a processor system provided by an embodiment of the present application is shown. As shown in FIG. 2, the processor system includes a processor core, a cache, a memory, a target prefetcher, a miss status holding register (MSHR), a prefetch queue, and a prefetch control device. The cache includes multiple levels of caches, including a target cache, which is any level of cache in the multiple levels of caches. When the target cache is the cache closest to the processor end, the target cache is connected to the processor core and the next level of cache, respectively. When the target cache is the cache closest to the memory end, the target cache is connected to the next level of cache and the memory, respectively. The MSHR is used to record the pending memory access requests in the cache, and can combine multiple requests for the same cache line to prevent repeated sending. The prefetch queue is used to temporarily store the prefetch requests and send the prefetch requests to the MSHR, thereby triggering the target cache to perform data prefetching from the next level of cache or the memory.

[0085] The effectiveness and quantity distribution of prefetching in different address regions differ greatly, which is derived from the spatial locality characteristics of application behavior and the prefetch algorithm design itself, i.e., the application tends to access and use data concentratedly, and the prefetch strategy designed according to the application characteristics also often contains this characteristic. Based on this regional difference of prefetching, an embodiment of the present application divides the address space of the target cache into at least two cache regions, and performs separate prefetch throttling control for each cache region.

[0086] Specifically, the embodiments of the present application dynamically monitor the cache miss heat and the first prefetch accuracy of each cache region in a preset period. The cache miss heat is used to indicate the frequency of cache miss of the cache region, which can be determined according to the number of cache misses in the cache region in the preset period. For example, the number of cache misses in the cache region in the preset period can be directly used as the value of the cache miss heat of the cache region, or the cache miss heat can be calculated according to the ratio of the number of accesses received by the cache region in the preset period to the number of cache misses, etc. The cache miss heat can be used to estimate the space in which the potential prefetch of the cache region can play a role. If the cache miss heat of the cache region in the preset period is low, the number of prefetches of the cache region can be limited in a relatively low range; otherwise, if the cache miss heat of the cache region in the preset period is high, it means that the prefetch demand of the cache region is high, and multiple prefetches are needed to meet the data demand of the received access request. The first prefetch accuracy is used to indicate the proportion of the effective prefetch of the cache region in all prefetches in the preset period, which can be determined according to the number of prefetch hits and the number of prefetches of the cache region in the preset period. The prefetch hit means that the data block prefetched is accessed subsequently, and the number of prefetches means the number of prefetch requests of the target prefetcher for the cache region. The first prefetch accuracy can be used to estimate the prefetch quality of the target prefetcher for the cache region. If the first prefetch accuracy of the cache region in the preset period is low, it means that the prefetch quality of the target prefetcher for the cache region is low, and the number of prefetch requests of the cache region can be reduced to reduce the overhead caused by the wrong prefetch and improve the prefetch performance of the target prefetcher; if the first prefetch accuracy of the cache region in the preset period is high, it means that the prefetch quality of the target prefetcher for the cache region is high, and the prefetch request of the cache region can be normally sent.

[0087] It should be noted that the preset period in the embodiments of the present application can be a preset time period, and the time span of each period is the same. The period length of the preset period can also be defined according to events, and the number of a certain specific event occurring in each period is the same, for example, 128 cache misses of the target cache can be set as a period, etc.

[0088] If the target prefetcher meets the throttle condition, the allowed prefetch number of each cache region can be determined according to the cache miss heat and the first prefetch accuracy of each cache region, and then the sending of the prefetch request of each cache region can be individually controlled according to the allowed prefetch number.

[0089] The throttling condition is used to determine whether the target prefetcher needs to be throttled. For example, the number of prefetch requests sent by the target prefetcher and the number of prefetch hits can be monitored to determine the prefetch accuracy of the target prefetcher. If the prefetch accuracy of the target prefetcher is less than a certain threshold, for example, less than 20%, it can be determined that the target prefetcher meets the throttling condition. The number of false prefetches can be reduced by throttling the target prefetcher, thereby reducing the pollution of the target cache and the memory access overhead caused by false prefetches triggered by the target prefetcher, and improving the prefetch performance of the target prefetcher. In another embodiment, the proportion of access requests that cause cache misses in the cache closest to the memory end can also be monitored. The memory bus bandwidth traffic generated by the target prefetcher can be estimated according to the proportion. If the memory bus bandwidth traffic generated by the target prefetcher is greater than a certain threshold, for example, greater than 50%, it can be determined that the target prefetcher meets the throttling condition. The memory bus bandwidth traffic generated by the target prefetcher can be reduced by throttling the target prefetcher, thereby improving the overall performance of the processor system.

[0090] The allowed prefetch quantity of the cache region can be calculated according to the cache miss heat and the first prefetch accuracy of the cache region. As an example, the allowed prefetch quantity = a x cache miss heat x first prefetch accuracy, where a is a preset coefficient, and the value of a can be set according to actual needs.

[0091] After determining the allowed prefetch quantity of each cache region, the sending of the prefetch request corresponding to each cache region can be controlled according to the allowed prefetch quantity in the next cycle. In the next cycle, the number of prefetch requests corresponding to each cache region sent to the subsequent memory access component is less than or equal to the allowed prefetch quantity of the cache region.

[0092] Taking the processor system shown in FIG. 2 as an example, after receiving the access request (including the prefetch request of the upper-level cache), the target cache feeds back the cache hit condition to the target prefetcher. The target prefetcher predicts the data that may be accessed in the future according to the cache hit condition of the target cache, and generates a prefetch request to prefetch the data to the target cache in advance. The target cache prefetches data from the next-level cache or the memory according to the prefetch request, and backfills the data into the current-level cache. The MSHR merges the requests for the same cache line in the target cache to avoid sending the same request to the next-level cache or the memory repeatedly. The target cache feeds back the hit condition (i.e., the prefetch hit) of the data prefetched in the subsequent access and the cache hit condition to the prefetch control device. The prefetch control device determines the first prefetch accuracy of each cache region in the target cache according to the prefetch hit condition of the target cache, and determines the cache miss heat of the target cache according to the cache hit condition of the target cache.

[0093] In the processor system shown in FIG. 2, the prefetch control module monitors the prefetch requests issued by the target prefetcher. In the case where the target prefetcher meets the throttling condition, the prefetch control module can determine the cache region corresponding to each prefetch request issued by the target prefetcher according to the prefetch address carried in the prefetch request, and if the allowed prefetch quantity of the cache region corresponding to the prefetch request is not 0, the transmission of the prefetch request can not be intervened, and the prefetch request will be normally sent to the prefetch queue to wait to be sent to the MSHR for subsequent prefetch process. Moreover, the prefetch control module can reduce the allowed prefetch quantity of the cache region by 1 after the prefetch request corresponding to the cache region is normally issued. If the allowed prefetch quantity of the cache region corresponding to the prefetch request is equal to 0, the prefetch request is intercepted, and the prefetch request intercepted by the prefetch control module will not be sent to the prefetch queue any more, and the subsequent prefetch process will not be triggered.

[0094] The prefetch control method provided by the embodiments of the present application divides the address space of the target cache, periodically monitors the cache miss heat and the first prefetch accuracy in each cache region, and determines how many prefetch requests are issued for the cache region in the next period based on the cache miss heat and the first prefetch accuracy of the cache region in the case where the target prefetcher meets the throttling condition, so as to realize the individual control of the prefetch quantity of each cache region, throttle a certain cache region, and will not affect the normal prefetch process of other cache regions in the target cache, avoid the blindness of global throttling of the target cache, and improve the prefetch control precision. Moreover, the embodiments of the present application trigger the throttling control only in the case where the target prefetcher meets the throttling condition, can ensure that the prefetch requests generated by the target prefetcher are retained as much as possible in the case where the target prefetcher does not have traffic problems, reduces the traffic overhead caused by prefetching while ensuring the prefetch performance of the target prefetcher, and is beneficial to improving the overall performance of the processor system.

[0095] It should be noted that many active prefetch throttling technologies in the related art control the aggressiveness and prefetch distance of the prefetcher based on the indicators such as prefetch accuracy, coverage, last level cache (LLC) pollution, and dynamic random access memory (DRAM) bandwidth, and a scheme for controlling the aggressiveness and prefetch distance needs to be specially proposed for each prefetcher, which is usually represented by the targeted adjustment of the threshold. These throttling technologies mainly have the following problems:

[0096] (1) Throttling aggressiveness may cause too many valid prefetches to be prevented, resulting in the performance of the prefetcher deteriorating.

[0097] (2) Throttling may cause invalid prefetch to continue to be issued, which cannot play a role in alleviating cache pollution and other problems.

[0098] The pre-fetch control method provided in the embodiments of the present application first determines whether the target pre-fetcher meets the throttling condition before throttling the target pre-fetcher. If the target pre-fetcher meets the throttling condition, a throttling mechanism is triggered, and the sending of a pre-fetch request is controlled according to the allowed pre-fetch quantity of each cache region in the target cache. If the target pre-fetcher does not meet the throttling condition, pre-fetching is triggered directly according to the pre-fetch request. Compared with the active throttling technology in the related art, the embodiments of the present application can retain the pre-fetch request as much as possible when the target pre-fetcher does not have a traffic problem, thereby avoiding excessive valid pre-fetching caused by aggressive throttling and ensuring the pre-fetching performance of the target pre-fetcher. Moreover, the embodiments of the present application divide the target cache into regions, calculate the allowed pre-fetch quantity based on the cache miss heat and the pre-fetch accuracy of the cache region, and do not directly disable or enable the pre-fetching of the region, thereby avoiding the blindness of global throttling and improving the precision of throttling control.

[0099] In addition, the embodiments of the present application can determine whether the cache region needs to solve the storage problem through pre-fetching based on the cache miss heat of the cache region, and can avoid issuing invalid pre-fetching to the target. The first pre-fetch accuracy of the cache region can be used to evaluate whether the pre-fetching effectively solves the storage problem of the cache region. The allowed pre-fetch quantity of the cache region can be determined in combination with the two pieces of information, which can reduce the issuance of invalid pre-fetching, alleviate the pollution of the cache caused by incorrect pre-fetching, reduce the memory access overhead, and thus improve the overall performance of the processor system.

[0100] Optionally, the step 101 of dividing the address space of the target cache into at least two cache regions comprises: grouping the cache addresses in the target cache by using the high bits of the cache addresses as tags to obtain at least two cache regions; and the cache addresses in the same cache region have the same tag.

[0101] In the embodiments of the present application, the cache addresses in the target cache can be grouped according to the high bits of the cache addresses, so as to directly divide the address space of the target cache into at least two cache regions. For example, the high 18 bits of the cache addresses can be used as tags to group the cache addresses.

[0102] It can be understood that the number of bits corresponding to the tag can be set according to actual needs, so as to adjust the size of the cache region to be divided by adjusting the number of bits of the tag.

[0103] Optionally, the step 102 of dynamically monitoring the cache miss heat and the first pre-fetch accuracy of each cache region in a preset period comprises:

[0104] Step S11, in a prefetch period, monitoring a cache miss number, a first prefetch sending number and a first prefetch hit number corresponding to each cache region;

[0105] Step S12, determining a cache miss heat of the cache region according to the cache miss number;

[0106] Step S13, calculating a first prefetch accuracy in the cache region according to the first prefetch sending number and the first prefetch hit number.

[0107] In the embodiment of the present application, the cache miss number in the cache region in a preset period can be directly taken as the value of the cache miss heat of the cache region, or the cache miss heat can be calculated according to the ratio of the access number to the cache miss number received by the cache region in the preset period, etc.

[0108] The first prefetch hit number refers to the number of times that the data block prefetched from the cache region is accessed subsequently. The first prefetch sending number refers to the number of prefetch requests sent by the target prefetcher for the cache region. The first prefetch accuracy of the cache region can be determined according to the first prefetch sending number and the first prefetch hit number of the cache region, and the first prefetch accuracy = the first prefetch hit number / the first prefetch sending number.

[0109] In an optional embodiment of the present application, before the step 103, in the next prefetch period, according to the allowed prefetch number, the sending of the prefetch request corresponding to the cache region, the method further comprises:

[0110] Step S21, recording the cache miss heat, the first prefetch accuracy and the allowed prefetch number of the cache region in the cache region heat table;

[0111] The step 103, in the next prefetch period, according to the allowed prefetch number, sending the prefetch request corresponding to the cache region, comprises:

[0112] Step S22, in the case that the prefetch request sent by the target prefetcher is monitored, querying the cache region heat table according to the prefetch address carried by the prefetch request;

[0113] Step S23, if the first cache region matching the prefetch address exists in the cache region heat table, reading the allowed prefetch number and the first prefetch accuracy of the first cache region;

[0114] Step S24, in the case that the allowed prefetch number is greater than 0 and the first prefetch accuracy is greater than or equal to the first threshold value, sending the prefetch request to the prefetch queue, and reducing the value of the allowed prefetch number of the first cache region in the cache region heat table by n, n is greater than 0.

[0115] In the embodiment of the present application, the cache miss heat of each cache region (or the number of cache misses), the number of first prefetch hits, the number of first prefetch issues and the number of allowed prefetches can be recorded by a cache region heat table. Referring to Table 1, a cache region heat table provided by the embodiment of the present application is shown.

[0116] Table 1

[0117] In Table 1, the number of allowed prefetches = a x the number of cache misses x (the number of first prefetch hits / the number of first prefetch issues), and a = 2.

[0118] In the embodiment of the present application, if a prefetch request issued by a target prefetcher is monitored and the target prefetcher meets the throttling condition, the cache region heat table can be queried according to the prefetch address carried by the prefetch request. If the first cache region Ri matching the prefetch address exists in the cache region heat table, the number of allowed prefetches and the first prefetch accuracy of the first cache region Ri can be read from the cache region heat table to determine whether to issue the prefetch request. If the current number of allowed prefetches of the first cache region Ri is greater than 0 and the first prefetch accuracy is greater than or equal to the first threshold, the prefetch request can be normally sent to the prefetch queue to trigger the subsequent prefetch process. Then, the value of the number of allowed prefetches of the first cache region Ri in the cache region heat table is reduced by n, and n is greater than 0. The value of n can be determined according to the initial value of the number of allowed prefetches. For example, when the calculated number of allowed prefetches = a x the cache miss heat x the first prefetch accuracy, and the value of the coefficient a is large, n can be an integer greater than 1, for example, 2 or 3, so as to correct the value of the coefficient a and avoid the case that the number of actually issued prefetch requests is large when the value of the coefficient a is large, which results in the failure to achieve the throttling effect. When the value of the coefficient a is small, n can be equal to 1.

[0119] The first threshold can be set according to actual needs. For example, the first threshold can be 20%.

[0120] Optionally, the method further includes: intercepting the prefetch request in the case of meeting a first condition.

[0121] The first condition includes at least one of the following:

[0122] A1. The cache region heat table does not have a first cache region matching the prefetch address;

[0123] A2. The number of allowed prefetches of the first cache region is equal to 0;

[0124] A3. The first prefetch accuracy of the first cache region is less than the first threshold.

[0125] It should be noted that if the prefetch address of the prefetch request belongs to the address space of a certain cache region, it can be considered that the prefetch request matches the cache region. Illustratively, the high bits of the prefetch address can be compared with the tag of the cache region, and if the high bits of the prefetch address are the same as the tag of the cache region, it can be considered that the prefetch request matches the cache region.

[0126] In the embodiment of the application, if there is no first cache region in the cache region hotness table that matches the prefetch address carried in the prefetch request, the prefetch request can be intercepted. Alternatively, if there is a first cache region in the cache region hotness table that matches the prefetch address carried in the prefetch request, but the current allowed prefetch quantity of the first cache region is 0, or the first prefetch accuracy rate is less than the first threshold, the prefetch request is intercepted.

[0127] Illustratively, in the processor system shown in FIG. 2, the prefetch control module monitors the prefetch request issued by the target prefetcher, and in the case of determining that interception is needed, the prefetch request is not sent to the prefetch queue, and the subsequent prefetch process is no longer triggered.

[0128] The embodiment of the application determines whether to issue a prefetch request according to the allowed prefetch quantity and the first prefetch accuracy rate of the cache region, which can reduce the number of times of issuing incorrect prefetches while reducing prefetch traffic, thereby reducing the memory access overhead caused by incorrect prefetches and improving the prefetch performance of the target prefetcher.

[0129] Optionally, the method further comprises:

[0130] Step S31, obtaining a request proportion from the target prefetcher in the memory access request sent by a first cache to a memory in a preset period; the first cache is a cache closest to the memory in a processor system;

[0131] Step S32, monitoring a second prefetch issuing frequency and a second prefetch hit frequency of the target prefetcher in the preset period;

[0132] Step S33, determining a second prefetch accuracy rate of the target prefetcher according to the second prefetch issuing frequency and the second prefetch hit frequency;

[0133] Step S34, calculating a prefetch traffic of the target prefetcher according to the request proportion and the second prefetch accuracy rate; the prefetch traffic is used to indicate the additional memory bus bandwidth traffic caused by incorrect prefetches issued by the target prefetcher;

[0134] Step S35, determining that the prefetcher meets the throttling condition in the case that the prefetch traffic is greater than a second threshold.

[0135] In the embodiment of the present application, the second prefetch issuing times and the second prefetch hit times of the target prefetcher in a preset period can be monitored, and the second prefetch accuracy rate can be calculated. The second prefetch issuing times refer to the number of prefetch requests sent by the target prefetcher to the subsequent memory access component (for example, a prefetch queue). The second prefetch hit times refer to the number of times that the data prefetched by the target prefetcher in the prefetch request is accessed in subsequent memory access. The second prefetch accuracy rate = the second prefetch hit times / the second prefetch issuing times.

[0136] The first cache refers to the cache closest to the memory in the processor system. The proportion of the prefetch request issued by the target prefetcher in the memory access request sent by the first cache to the memory is counted, that is, the request proportion of the target prefetcher in the memory access request sent by the first cache to the memory. Then, according to the request proportion and the second prefetch accuracy rate of the target prefetcher, the additional memory bus bandwidth flow caused by the false prefetch triggered by the target prefetcher is estimated. For example, when the second prefetch accuracy rate of the target prefetcher is 20%, and the request proportion of the target prefetcher in the cache miss request of the first cache is 50%, it can be estimated that the false prefetch at this time causes about 50% x (1-20%) = 40% of the prefetch flow. It should be noted that the correct prefetch replaces the role of normal access, and therefore does not cause additional memory bus bandwidth flow.

[0137] According to the prefetch flow of the target prefetcher, it can be determined whether the target prefetcher needs to be throttled. For example, if the prefetch flow is greater than the second threshold, it can be determined that the target prefetcher meets the throttling condition, and at this time, the throttling control of the target prefetcher can be triggered. The second threshold can be set according to actual control requirements, for example, the second threshold can be 30%.

[0138] In summary, the embodiment of the present application provides a prefetch control method, which divides the address space of the target cache, periodically monitors the cache miss heat and the first prefetch accuracy rate in each cache region, and determines how many prefetch requests are issued to the cache region in the next period based on the cache miss heat and the first prefetch accuracy rate of the cache region when the target prefetcher meets the throttling condition, thereby realizing the individual control of the number of prefetches for each cache region, throttling a certain cache region, without affecting the normal prefetch process of other cache regions in the target cache, avoiding the blindness of global throttling of the target cache, and improving the prefetch control accuracy. Moreover, the embodiment of the present application triggers the throttling control only when the target prefetcher meets the throttling condition, which can ensure that the prefetch request generated by the target prefetcher is retained as much as possible when the target prefetcher does not have flow problems, thereby ensuring the prefetch performance of the target prefetcher while reducing the flow overhead caused by prefetching, and being beneficial to improving the overall performance of the processor system.

[0139] It should be noted that, for the method embodiments, the series of acts described is merely an example and that the application embodiments can be implemented in other sequences than the one described, or in a different order, or even at the same time. Furthermore, it should be noted that the application embodiments can be implemented in a computer system comprising a processor and a memory, the memory comprising instructions executable by the processor to implement the application embodiments. Alternatively, the application embodiments can be implemented in a computer system comprising a processor and a memory, the memory comprising instructions executable by the processor to implement the application embodiments.

[0140] Device embodiments

[0141] Referring to FIG. 3, a structural block diagram of a prefetch control device according to the application is shown, which can specifically include:

[0142] The division module 301 is configured to divide an address space of a target cache into at least two cache regions.

[0143] The first monitoring module 302 is configured to dynamically monitor a cache miss heat and a first prefetch accuracy of each cache region in a preset period.

[0144] The first determination module 303 is configured to, in a case where a target prefetcher corresponding to the target cache satisfies a throttling condition, determine an allowed prefetch quantity of the cache region according to the cache miss heat and the first prefetch accuracy.

[0145] The control module 304 is configured to, in a next period, control sending of a prefetch request corresponding to the cache region according to the allowed prefetch quantity.

[0146] Optionally, the device further includes:

[0147] The recording module is configured to record the cache miss heat, the first prefetch accuracy and the allowed prefetch quantity of the cache region in a cache region heat table.

[0148] The control module includes:

[0149] The query submodule is configured to, in a case where a prefetch request sent by the target prefetcher is monitored, query the cache region heat table according to a prefetch address carried by the prefetch request.

[0150] The reading submodule is configured to, if there is a first cache region matching the prefetch address in the cache region heat table, read the allowed prefetch quantity and the first prefetch accuracy of the first cache region.

[0151] The sending sub-module is configured to, in the case that the allowed prefetch quantity is greater than 0 and the first prefetch accuracy is greater than or equal to the first threshold, send the prefetch request to a prefetch queue and decrease the value of the allowed prefetch quantity of the first cache area in the cache area hotness table by n, where n is greater than 0.

[0152] Optionally, the control module further comprises:

[0153] The intercepting sub-module is configured to intercept the prefetch request in the case that a first condition is met.

[0154] The first condition comprises at least one of the following:

[0155] There is no first cache area in the cache area hotness table that matches the prefetch address;

[0156] The allowed prefetch quantity of the first cache area is equal to 0;

[0157] The first prefetch accuracy of the first cache area is less than the first threshold.

[0158] Optionally, the dividing module comprises:

[0159] The dividing sub-module is configured to group cache addresses in the target cache according to high-order bits of the cache addresses as tags to obtain at least two cache areas; cache addresses in a same cache area have the same tag.

[0160] Optionally, the first monitoring module comprises:

[0161] The monitoring sub-module is configured to monitor, in a prefetch period, a cache miss number, a first prefetch issuing number and a first prefetch hit number corresponding to each cache area.

[0162] The cache miss hotness determining sub-module is configured to determine cache miss hotness of the cache area according to the cache miss number.

[0163] The prefetch accuracy calculating sub-module is configured to calculate a first prefetch accuracy in the cache area according to the first prefetch issuing number and the first prefetch hit number.

[0164] Optionally, the apparatus further comprises:

[0165] The obtaining module is configured to obtain a request proportion from the target prefetcher in memory access requests sent by a first cache to a memory in a preset period; the first cache is a cache closest to the memory in a processor system.

[0166] The second monitoring module is configured to monitor a second pre-fetch issuing frequency and a second pre-fetch hit frequency of the target pre-fetcher in the preset period.

[0167] The second determining module is configured to determine a second pre-fetch accuracy of the target pre-fetcher according to the second pre-fetch issuing frequency and the second pre-fetch hit frequency.

[0168] The flow calculation module is configured to calculate a pre-fetch flow of the target pre-fetcher according to the request ratio and the second pre-fetch accuracy, where the pre-fetch flow is used to indicate an extra memory bus bandwidth flow caused by the error pre-fetch of the target pre-fetcher.

[0169] The throttling determining module is configured to determine that the pre-fetcher meets a throttling condition when the pre-fetch flow is greater than a second threshold.

[0170] To sum up, the embodiment of the present application provides a pre-fetch control device, which divides the address space of a target cache, periodically monitors the cache miss heat and the first pre-fetch accuracy in each cache region, and determines how many pre-fetch requests are issued for the cache region in the next period based on the cache miss heat and the first pre-fetch accuracy of the cache region when the target pre-fetcher meets a throttling condition, so as to realize the individual control of the pre-fetch quantity of each cache region, throttle a certain cache region, and not affect the normal pre-fetch process of other cache regions in the target cache, avoid the blindness of global throttling of the target cache, and improve the pre-fetch control precision. Moreover, the embodiment of the present application triggers throttling control only when the target pre-fetcher meets a throttling condition, can ensure that the pre-fetch request generated by the target pre-fetcher is retained as much as possible when there is no flow problem of the target pre-fetcher, reduces the flow overhead caused by pre-fetching while ensuring the pre-fetch performance of the target pre-fetcher, and is beneficial to improving the overall performance of the processor system.

[0171] For the device embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and the related parts refer to the part of the method embodiment.

[0172] Each embodiment in the specification is described in a progressive manner, and each embodiment mainly describes the difference from other embodiments. The same and similar parts of each embodiment can be referred to each other.

[0173] As to the processor in the above embodiment, the specific manner in which each module performs the operation has been described in detail in the embodiment related to the method, and will not be described in detail here.

[0174] Referring to FIG. 4, it is a structural block diagram of an electronic device provided by an embodiment of the present application. As shown in FIG. 4, the electronic device comprises a processor, a memory, a communication interface and a communication bus, the processor, the memory and the communication interface complete communication with each other through the communication bus; the memory is used for storing executable instructions, and the executable instructions make the processor execute the prefetch control method of the foregoing embodiments.

[0175] The processor can be a CPU (Central Processing Unit, central processor), a general-purpose processor, a DSP (Digital Signal Processor, digital signal processor), an ASIC (Application Specific Integrated Circuit, application specific integrated circuit), an FPGA (Field Programmable Gate Array, field programmable gate array) or other programmable device, transistor logic device, hardware component or any combination thereof. The processor can also be a combination of computing functions, such as one or more microprocessor combinations, combinations of DSP and microprocessor, etc.

[0176] The communication bus can include a channel for transmitting information between the memory and the communication interface. The communication bus can be a PCI (Peripheral Component Interconnect, peripheral component interconnect) bus or an EISA (Extended Industry Standard Architecture, extended industry standard architecture) bus, etc. The communication bus can be divided into an address bus, a data bus, a control bus, etc. For ease of representation, only one line is shown in FIG. 4, but it does not mean that there is only one bus or only one type of bus.

[0177] The memory can be a ROM (Read Only Memory, read only memory) or other type of static storage device that can store static information and instructions, a RAM (Random Access Memory, random access memory) or other type of dynamic storage device that can store information and instructions, and can also be an EEPROM (Electrically Erasable Programmable Read Only Memory, electrically erasable programmable read only memory), a CD-ROM (Compact Disc Read Only Memory, compact disc read only memory), a magnetic tape, a floppy disk and an optical data storage device, etc.

[0178] The embodiment of the present application further provides a non-transitory computer readable storage medium, when instructions in the storage medium are executed by a processor of an electronic device (a server or a terminal), the processor can execute the prefetch control method shown in FIG. 1.

[0179] Each of the embodiments in the specification is described in a progressive manner, and each embodiment focuses on the difference from other embodiments, and the same or similar parts between the embodiments can be referred to each other.

[0180] Those skilled in the art should understand that the embodiments of the present application can be provided as a method, device or computer program product. Therefore, the embodiments of the present application can adopt a completely hardware embodiment, a completely software embodiment or an embodiment combining software and hardware aspects. Moreover, the embodiments of the present application can adopt the form of a computer program product implemented on one or more computer usable storage media (including but not limited to disk memory, CD-ROM, optical memory, etc.) containing computer usable program codes.

[0181] The embodiments of the present application are described with reference to flowcharts and / or block diagrams of the method, terminal device (system) and computer program product according to the embodiments of the present application. It should be understood that each flow and / or block in the flowcharts and / or block diagrams and the combination of the flows and / or blocks in the flowcharts and / or block diagrams can be realized by computer program instructions. These computer program instructions can be provided to the processor of a general-purpose computer, special-purpose computer, embedded processor or other programmable data processing terminal device to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing terminal device generate the device for realizing the functions specified in one or more flows in the flowcharts and / or one or more blocks in the block diagrams.

[0182] These computer program instructions can also be stored in a computer readable storage medium which can guide the computer or other programmable data processing terminal device to work in a predictable manner, so that the instructions stored in the computer readable storage medium generate a product including instruction devices, which realize the functions specified in one or more flows in the flowcharts and / or one or more blocks in the block diagrams.

[0183] These computer program instructions can also be loaded into a computer or other programmable data processing terminal device, so that a series of operation steps are executed on the computer or other programmable terminal device to generate a computer implemented process, so that the instructions executed on the computer or other programmable terminal device provide steps for realizing the functions specified in one or more flows in the flowcharts and / or one or more blocks in the block diagrams.

[0184] Although the preferred embodiments of the application have been described, those skilled in the art will be able to make additional changes and modifications to these embodiments once they have the basic inventive concept. Therefore, the appended claims are intended to cover all changes and modifications that fall within the scope of the embodiments of the application.

[0185] Those skilled in the art can clearly understand that the units and algorithm steps of the examples described in combination with the embodiments disclosed herein can be realized by electronic hardware or a combination of computer software and electronic hardware. Whether the functions are realized in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to realize the described functions for each specific application, but such implementation should not be considered beyond the scope of the present disclosure.

[0186] Those skilled in the art can clearly understand that, for the convenience and brevity of the description, the specific working processes of the above-described system, device and unit can refer to the corresponding processes in the foregoing method embodiments, which will not be repeated here.

[0187] In the embodiments provided in the present application, it should be understood that the disclosed devices and methods can be implemented in other ways. For example, the device embodiments described above are only schematic. The division of the units is only a logical function division. In actual implementation, additional division can be made, for example, a plurality of units or components can be combined or integrated into another system, or some features can be omitted or not executed. In addition, the coupling or direct coupling or communication connection between the units shown or discussed can be indirect coupling or communication connection through some interface, device or unit, which can be electrical, mechanical or in other forms.

[0188] The units described as separate components can or can not be physically separated, and the components shown as units can or can not be physical units, i.e. they can be located in one place or distributed on multiple network units. Some or all of the units can be selected to achieve the purpose of the embodiments according to actual needs.

[0189] In addition, the functional units in each embodiment of the present disclosure can be integrated in one processing unit, or each unit can be physically present separately, or two or more units can be integrated in one unit.

[0190] It can be understood that the embodiments described in the embodiments of the present disclosure can be implemented by hardware, software, firmware, middleware, microcode or a combination thereof. For hardware implementation, the modules, units, sub-units can be implemented in one or more application specific integrated circuits (ASICs), digital signal processors (DSPs), digital signal processing devices (DSPDs), programmable logic devices (PLDs), field programmable gate arrays (FPGAs), general purpose processors, controllers, micro-controllers, microprocessors, other electronic units for performing the functions described in the present disclosure, or a combination thereof.

[0191] For software implementation, the technologies described in the embodiments of the present disclosure can be implemented by modules (such as processes, functions, etc.) for performing the functions described in the embodiments of the present disclosure. The software code can be stored in a memory and executed by a processor. The memory can be implemented in the processor or outside the processor.

[0192] Finally, it should also be noted that in this document, relational terms such as first and second and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises", "comprising", or any other variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or terminal device that comprises a list of elements does not include only those elements but can include other elements not expressly listed or inherent to such process, method, article, or terminal device. Without more limitations, an element defined by the statement "comprising a" does not exclude the existence of additional identical elements in the process, method, article, or terminal device that includes the element.

[0193] The above provides a pre-fetch control method and device, electronic equipment and readable storage medium, the principle and implementation mode of the present application are described in detail in the text, the above example is only used to help understand the method and core idea of the present application; At the same time, for those skilled in the art, according to the idea of the present application, the specific implementation mode and application range will be changed; The above description should not be understood as the limitation of the present application.

Claims

1. A prefetch control method, wherein, The method comprises: dividing an address space of a target cache into at least two cache regions; dynamically monitoring cache miss heat and first prefetch accuracy of each cache region in a preset period; in a case where a target prefetcher corresponding to the target cache meets a throttling condition, determining a number of allowed prefetches of the cache region according to the cache miss heat and the first prefetch accuracy; in a next period, controlling sending of a prefetch request corresponding to the cache region according to the number of allowed prefetches.

2. The method of claim 1, wherein, Before the step of in the next period, controlling sending of the prefetch request corresponding to the cache region according to the number of allowed prefetches, the method further comprises: recording the cache miss heat, the first prefetch accuracy and the number of allowed prefetches of the cache region in a cache region heat table; the step of in the next period, controlling sending of the prefetch request corresponding to the cache region according to the number of allowed prefetches, comprises: in a case where a prefetch request sent by the target prefetcher is monitored, querying the cache region heat table according to a prefetch address carried by the prefetch request; if there is a first cache region matching the prefetch address in the cache region heat table, reading the number of allowed prefetches and the first prefetch accuracy of the first cache region; in a case where the number of allowed prefetches is greater than 0 and the first prefetch accuracy is greater than or equal to a first threshold, sending the prefetch request to a prefetch queue, and reducing a value of the number of allowed prefetches of the first cache region in the cache region heat table by n, n is greater than 0.

3. The method of claim 2, wherein, The method further comprises: in a case where a first condition is met, intercepting the prefetch request; wherein the first condition comprises at least one of the following: there is no first cache region matching the prefetch address in the cache region heat table; the number of allowed prefetches of the first cache region is equal to 0; the first prefetch accuracy of the first cache region is less than the first threshold.

4. The method of claim 1, wherein, The step of dividing an address space of a target cache into at least two cache regions, comprises: grouping cache addresses in the target cache according to high bits of the cache addresses as tags, to obtain at least two cache regions; cache addresses in a same cache region have the same tag.

5. The method of claim 1, wherein, The step of dynamically monitoring cache miss heat and first prefetch accuracy of each cache region in a preset period, comprises: monitoring a cache miss number, a first prefetch sending number and a first prefetch hit number corresponding to each cache region in a prefetch period; determining cache miss heat of the cache region according to the cache miss number; calculating first prefetch accuracy in the cache region according to the first prefetch sending number and the first prefetch hit number.

6. The method of claim 1, wherein, The method further comprises: obtaining a request proportion from the target prefetcher in a memory access request sent by a first cache to a memory in the preset period; the first cache is a cache closest to the memory in a processor system; monitoring a second prefetch sending number and a second prefetch hit number of the target prefetcher in the preset period; determine a second prefetch accuracy of the target prefetcher according to the second prefetch issuing times and the second prefetch hit times; calculate a prefetch flow of the target prefetcher according to the request proportion and the second prefetch accuracy, the prefetch flow being used to indicate an extra memory bus bandwidth flow caused by an error prefetch of the target prefetcher; determine that the prefetcher meets a throttling condition in a case where the prefetch flow is greater than a second threshold.

7. The method of claim 1, wherein, The cache miss heat is used to indicate a frequency of cache miss of the cache region, and the cache miss heat is determined according to a number of cache misses of the cache region in a preset period. The first prefetch accuracy is used to indicate a proportion of effective prefetch of the cache region in all prefetches in a preset period, and the first prefetch accuracy is determined according to a prefetch hit times and a prefetch issuing times of the cache region in the preset period.

8. The method of claim 1, wherein, The target cache is any one of multiple levels of caches. If the target cache is a cache closest to a processor end, the target cache is connected with a processor core and a next level of cache respectively. If the target cache is a cache closest to a memory end, the target cache is connected with a previous level of cache and a memory respectively.

9. A prefetch control apparatus, wherein, The apparatus comprises: a splitting module configured to split an address space of a target cache into at least two cache regions; a first monitoring module configured to dynamically monitor a cache miss heat and a first prefetch accuracy of each cache region in a preset period; a first determining module configured to determine an allowed prefetch quantity of the cache region according to the cache miss heat and the first prefetch accuracy in a case where a target prefetcher corresponding to the target cache meets a throttling condition; a control module configured to control sending of a prefetch request corresponding to the cache region according to the allowed prefetch quantity in a next period.

10. The apparatus of claim 9, wherein, The apparatus further comprises: a recording module configured to record the cache miss heat, the first prefetch accuracy and the allowed prefetch quantity of the cache region in a cache region heat table; the control module comprises: a query submodule configured to query the cache region heat table according to a prefetch address carried by the prefetch request in a case where the prefetch request sent by the target prefetcher is monitored; a reading submodule configured to read the allowed prefetch quantity and the first prefetch accuracy of a first cache region in a case where the first cache region matching the prefetch address exists in the cache region heat table; a sending submodule configured to send the prefetch request to a prefetch queue and reduce a value of the allowed prefetch quantity of the first cache region in the cache region heat table by n (n>0) in a case where the allowed prefetch quantity is greater than 0 and the first prefetch accuracy is greater than or equal to a first threshold.

11. The apparatus of claim 10, wherein, The control module further comprises: an intercepting submodule configured to intercept the prefetch request in a case where a first condition is met; the first condition comprises at least one of the following: the first cache region matching the prefetch address does not exist in the cache region heat table; the allowed prefetch quantity of the first cache region is equal to 0. The first prefetch accuracy of the first cache area is less than the first threshold.

12. The apparatus of claim 9, wherein, The segmentation module comprises: The segmentation sub-module is configured to group cache addresses in the target cache according to high-order bits of the cache addresses as tags, to obtain at least two cache areas; cache addresses in a same cache area have the same tag.

13. The apparatus of claim 9, wherein, The first monitoring module comprises: The monitoring sub-module is configured to monitor, in a prefetch period, a cache miss number, a first prefetch issuing number and a first prefetch hit number corresponding to each cache area; The cache miss heat determination sub-module is configured to determine a cache miss heat of the cache area according to the cache miss number. The prefetch accuracy calculation sub-module is configured to calculate a first prefetch accuracy in the cache area according to the first prefetch issuing number and the first prefetch hit number.

14. The apparatus of claim 9, wherein, The apparatus further comprises: The acquisition module is configured to acquire a request proportion from the target prefetcher in memory access requests sent by a first cache to a memory in a preset period; the first cache is a cache closest to the memory in a processor system; The second monitoring module is configured to monitor a second prefetch issuing number and a second prefetch hit number of the target prefetcher in the preset period; The second determination module is configured to determine a second prefetch accuracy of the target prefetcher according to the second prefetch issuing number and the second prefetch hit number; The flow calculation module is configured to calculate a prefetch flow of the target prefetcher according to the request proportion and the second prefetch accuracy; the prefetch flow is used to indicate an additional memory bus bandwidth flow caused by incorrect prefetching of the target prefetcher; The throttling determination module is configured to determine that the prefetcher satisfies a throttling condition if the prefetch flow is greater than a second threshold.

15. The apparatus of claim 9, wherein, The cache miss heat is used to indicate a frequency of cache miss of a cache area, and the cache miss heat is determined according to a cache miss number in a cache area in a preset period. The first prefetch accuracy is used to indicate a proportion of effective prefetching of a cache area in all prefetching in a preset period, and the first prefetch accuracy is determined according to a prefetch hit number and a prefetch issuing number of the cache area in the preset period.

16. The apparatus of claim 9, wherein, The target cache is any one of multiple levels of caches; If the target cache is a cache closest to a processor end, the target cache is connected with a processor core and a next level of cache respectively; If the target cache is a cache closest to a memory end, the target cache is connected with a previous level of cache and a memory respectively.

17. An electronic device, comprising: The electronic device comprises a processor, a memory, a communication interface and a communication bus, the processor, the memory and the communication interface complete communication with each other through the communication bus; the memory is used to store executable instructions, and the executable instructions make the processor execute the prefetch control method in any one of claims 1 to 8.

18. A readable storage medium, wherein, When the instructions in the readable storage medium are executed by the processor of the electronic device, the processor can execute the prefetch control method in any one of claims 1 to 8.

19. A chip comprising a processor and a communication interface, the communication interface and the processor coupled, the processor configured to run a program or instructions to implement the prefetch control method of any one of claims 1 to 8.

20. A prefetch control apparatus / device comprising the apparatus / device configured to perform the prefetch control method of any one of claims 1 to 8.

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