Method for producing an array comprising UV light-emitting diodes, and array

Abstract

The invention relates to a method for producing an array (31), and to an array (31). The method provides the following: producing an array substrate (1), wherein apertures (2) having inclined side walls (3) are formed in a semiconductor substrate by means of etching; arranging light-emitting chips (32), which are designed to emit UV light, on a carrier substrate (30) such that a component spacing is formed between adjacent light-emitting chips (32); and forming a housing (33) for the light-emitting chips (32) on the carrier substrate (30), wherein in this case the array substrate (1) is arranged on the carrier substrate (30) such that a single light-emitting chip (32) is arranged in each of the apertures (2) and such that UV light emitted laterally by the light-emitting chip (32) in the aperture (2) is reflected to a side facing away from the carrier substrate (30), through a housing opening (34), by means of the inclined side walls (3) of the aperture (2). In the light-emitting chips (32), a total side surface comprising all side surfaces (32a) of the light-emitting chip (32) forms at least 60% of a light-emitting total surface which is formed by the side surfaces (32a) and a top surface (32b) of the light-emitting chip (32).

Description

[0001] Method for manufacturing an array with UV light emitting diodes and array

[0002] The invention relates to a method for manufacturing an array of UV light-emitting diodes and to an array of UV light-emitting diodes.

[0003] These arrays provide planar arrangements of UV light-emitting diodes that can be used as a UV light source for various purposes. Several UV light-emitting chips are arranged on a substrate and electrically interconnected so that the chips can be operated to emit light.

[0004] According to document EP 2 481 091 B1, a housing can be provided for electronic components such as light-emitting chips. The document discloses a method for manufacturing an arrangement with a component on a support substrate.The method comprises the following steps: providing a substrate, producing one or more depressions in the area of ​​a selected surface of the substrate, arranging the cover substrate on the selected surface of the substrate in such a way that at least one depression cavity is formed, and forming separate spacer elements which, together with the cover substrate, define at least one cavity that is open in the area of ​​the opposite surface of the substrate, arranging a component on a cover surface of a support substrate, and arranging the spacer elements formed on the cover substrate on the support substrate in such a way that the component is arranged in the at least one cavity and this cavity is closed.To produce the separate spacer elements, the substrate is thinned from a surface opposite the selected surface, such that at least one cavity is opened. A contour of the spacer elements facing the cavity is formed by partial contouring both during the formation of the one or more cavities and during the thinning of the substrate.

[0005] Document CN 1 15 458 637 A discloses a method for manufacturing an array of UV light-emitting chips. An array of openings with inclined sidewalls is created in a silicon wafer by etching. UV light-emitting chips are arranged in these openings. Document DE 10 2020 126 391 A1 discloses an LED package for UV light with an optoelectronic component, which is specifically designed as a volume emitter. The component is arranged on a substrate with two contact pads for electrical contact.Furthermore, a frame surrounding the component and mounted on the carrier is provided, with a gas-tight outlet area facing a main radiation direction, such that a hermetically sealed cavity encompassing an interior area of ​​the carrier is formed, wherein the side walls of the frame facing the optoelectronic component are chamfered and open towards the main radiation direction. An ESD protection element mounted outside the interior area on the carrier is electrically connected to at least one of the two contact pads.

[0006] Summary

[0007] The object of the invention is to provide a method for manufacturing an array of UV light emitting chips and an array of UV light emitting chips with which the UV light emitted by the semiconductor chips can be efficiently extracted and made available for light irradiation.

[0008] To solve this problem, a method for manufacturing an array of UV-light-emitting chips according to independent claim 1 and an array of UV-light-emitting chips according to dependent claim 15 are provided. Embodiments are the subject of dependent subclaims.

[0009] According to one aspect, a method for manufacturing an array of UV light-emitting chips has been created, which comprises the following: providing a semiconductor substrate; manufacturing an array substrate, whereby openings with inclined sidewalls are formed in the semiconductor substrate by etching; arranging light-emitting chips, which are configured to emit UV light, on a support substrate, such that a component spacing is formed between adjacent light-emitting diodes;and forming a housing for the light-emitting chips on the substrate, wherein the array substrate is arranged on the substrate such that a single light-emitting chip is arranged in each of the openings and that, by means of the inclined side walls of the opening, UV light emitted laterally from the light-emitting chip in the opening is reflected through a housing opening to a side facing away from the substrate. In the case of the light-emitting chips, a total side surface encompassing all side surfaces of the light-emitting chip constitutes at least 60% of a total light-emitting area of ​​the light-emitting chip, which is formed by the side surfaces and a top surface of the light-emitting chip.

[0010] According to another aspect, an array comprises the following: an array substrate with openings formed in a semiconductor substrate by etching with inclined sidewalls; light-emitting chips designed to emit UV light on a support substrate, such that a component spacing is formed between adjacent light-emitting diodes; and a housing for the light-emitting chips on the support substrate, wherein the array substrate is arranged on the support substrate, such that a single light-emitting chip is arranged in each opening and that, by means of the inclined sidewalls of the opening, UV light emitted laterally from the light-emitting chip in the opening is reflected through a housing opening to a side facing away from the support substrate.In light-emitting chips, a total side surface encompassing all side surfaces of the light-emitting chip forms at least 60% of a total light-emitting area of ​​the light-emitting chip, which is formed by the side surfaces and a top surface of the light-emitting chip.

[0011] The proposed technology enables the efficient extraction of light emitted by UV light-emitting chips, particularly via their side surfaces, making it available for use. By means of angled sidewalls surrounding the openings, positioned opposite the side surfaces of the light-emitting chip and forming light reflectors, the UV light emitted laterally from the chip is effectively extracted. The etched semiconductor substrate (array substrate) thus provides a multifunctional housing for the UV light-emitting chips.On the other hand, the etched semiconductor substrate simultaneously enables an effective light extraction device. The light emitted laterally by the UV-emitting chips is reflected by the inclined side walls (reflectors) of the cutouts towards the housing opening (top-side opening of the cutout) and thus extracted. Not only the UV light emitted via the top surface of the light-emitting chip, but especially the light emitted via the side surfaces of the light-emitting chip, which constitute an even larger proportion of the chip's total light-emitting area, is utilized in this way. For light-emitting chips with a high proportion of side surfaces relative to the total area, the efficiency—that is, the ratio of optical power to electrical power input—is particularly high.The so-called wall-plug efficiency of these particularly small UV light-emitting chips can be almost doubled compared to standard light-emitting chips with a total side area of ​​less than 60%. An array of multiple UV light-emitting chips with a side area of ​​at least 60% relative to the total area makes it possible to almost double the power density per chip area compared to standard UV light-emitting chips.

[0012] Since chip manufacturing costs are primarily determined by the size or surface area of ​​the light-emitting chips, the proposed technology is particularly well-suited to reducing these costs. Furthermore, the yield of the light-emitting chips is largely determined by the defect density on the wafer. For very small UV light-emitting chips, the ratio of surface area to yield is particularly favorable.

[0013] When manufacturing the array substrate, the semiconductor substrate can, for example, be anisotropically etched.

[0014] In one embodiment, it may be provided that a Si semiconductor substrate is used as the semiconductor substrate, which can, for example, be anisotropically etched to produce the breakthroughs.

[0015] In this or other embodiments, etching can be carried out by means of a masking on a front side of the semiconductor substrate, which then forms a side of the array substrate facing away from the support substrate when the array substrate is arranged on the support substrate.

[0016] The UV light emitting chips can, for example, be formed with a layer system grown epitaxially on a sapphire substrate.

[0017] For example, a silicon wafer can be used to fabricate the array substrate, in which the openings are produced by etching. In one embodiment of the etching process, the silicon single crystal can form sidewalls with a typical inclined surface at an angle of approximately 54.7° to the main direction. With a different surface orientation, the sidewalls can be produced with different flank angles. Dry etching processes allow for the fabrication and targeted adjustment of flank angles that deviate from the standard. For example, shallower angles, such as 30° to 45°, or steeper angles, such as 60° to 90°, can be produced. Optionally, parabolic or spherical slopes can be produced using ion beam etching.

[0018] In light-emitting chips, the total side surface area can constitute at least 70% of the total light-emitting area, preferably at least 90%. In these embodiments, the side surfaces of the light-emitting chip, through which a portion of the UV light is emitted from the chip, occupy an even larger proportion of the chip's total light-emitting area, which is why the efficient light extraction by reflection on the (opposite) side walls is further improved.

[0019] In the light-emitting chips, all edge lengths of the chip can be less than or equal to 0.5 mm, preferably less than or equal to 0.3 mm, and more preferably less than or equal to 0.2 mm. In this way, an array with an arrangement of UV light-emitting chips with short edge lengths can be provided.

[0020] The light-emitting chips can have a chip thickness between 0.1 mm and 0.5 mm, preferably between 0.2 mm and 0.4 mm.

[0021] The light-emitting chips can be integrated into the cutouts with a height that is less than the height of the array substrate measured from the support substrate. Thus, the height of the UV light-emitting chip within the cutout on the support substrate is below the top surface (facing away from the support substrate) of the array substrate.

[0022] In an alternative embodiment, the height of the UV light-emitting chip corresponds approximately to the height of the array substrate. Light-emitting chips can be used that emit UV light with a wavelength of at most 350 nm, preferably at most 320 nm, and more preferably at most 280 nm.

[0023] In the wall sections of the array substrate that define the openings, a first wall section extending from the substrate can have a first height, and a second wall section, different from the first, can also extend from the substrate and have a second height that differs from the first. This allows, for example, one or more of the light-emitting chips to be surrounded by wall sections with inclined side walls of varying heights. These different heights can be achieved through appropriate etching techniques.

[0024] If the top substrate is then optionally placed on the array substrate, it rests on the respective top surface of the wall sections of the array substrate with greater height, whereas wall sections with less height, especially their top surface, have a gap to the back (the side facing the support substrate) of the top substrate. This also means that, due to this gap, an opening or passage is formed between adjacent openings, each of which forms a build or receiving space (housing) for a light-emitting chip. In one example, the gap can be approximately 50 pm to approximately 100 pm.

[0025] In one embodiment, the first wall section can be a partition between adjacent openings, each containing a chip, which can also be referred to as a housing partition. The second wall section can, for example, be an edge wall, which can also be referred to as an edge housing wall, and defines an opening towards the edge of the array substrate. In one example, all partitions in the array substrate can be designed with a lower profile than all edge wall sections.

[0026] For electrical contacting of the light-emitting chips, electrical contacts can be made on the front and back of the substrate, with at least some of these contacts being electrically connected via one or more vias, and the light-emitting chips being connected to these electrical contacts. The electrical contacts on the front and back of the substrate enable efficient electrical contacting of the UV light-emitting chip, particularly with regard to optionally additional electronic components associated with the light-emitting chip.

[0027] To dissipate the heat generated during operation of the light-emitting chips, one or more heat sinks can be integrated into the substrate and thermally connected to the chips. These heat sinks, also known as heat pads, promote efficient operation of the UV light-emitting chips. The heat sink(s) can be bonded to the substrate via a metallization process.

[0028] A recess for receiving an electronic component can be created in a wall section of the array substrate surrounding one of the openings. This recess can provide a depression in the array substrate.

[0029] The recess can be produced on the back side of the array substrate, i.e., on the side of the array substrate that faces the substrate during mounting. In this or other embodiments, the recess can be produced by etching the semiconductor substrate during the fabrication of the array substrate. For example, it may be possible to produce one or more recesses on the semiconductor substrate in a process step by means of an etching step on one side of the semiconductor substrate, particularly the back side. In a further process step, another etching step can be performed before or after to form the openings.

[0030] When the recess is created on the back of the array substrate, the recess opens, in particular, towards the support substrate. When the array substrate is then positioned on the support substrate, the electronic component can be inserted into the recess through this opening. In this way, the array substrate forms a housing for the electronic component. In one embodiment, the array substrate can have several recesses, for example, at least as many as the number of openings in the array substrate. In this way, at least one associated recess can be created for each opening, which can accommodate one or more electronic components associated with the light-emitting chip in the respective opening, for example, a Zener diode to protect the light-emitting chip from improper current supply.

[0031] The use of Zener diodes can be implemented for each individual light-emitting chip. Alternatively, individual rows of light-emitting chips in the array can each be protected by a Zener diode assigned to that row. It is also possible to protect an entire array of UV-emitting chips with a single protective diode. In each case, the protective diode is connected in parallel to the light-emitting chip, the chip row, or the entire array.

[0032] It may be possible to use one or more recesses to accommodate a protection diode.

[0033] When arranging the array substrate on the support substrate, the electronic component can be placed in the recess. The electronic component, which is itself mounted on the support substrate, can be partially or completely enclosed in the recess. For example, the electronic component could be a Zener diode that is associated with and electrically connected to one or more UV light-emitting chips.

[0034] A reflective coating can be applied to the sidewalls that reflect the UV light emitted laterally by the light-emitting chips in the openings. This reflective coating can be metallic, for example, an aluminum coating. In this way, the reflective coating can be optimized for UV light reflection.

[0035] Depending on the wavelength range of the light emitted by the light-emitting chips, various metals or dielectric coatings can be used. For UV-C radiation (deep UV), an aluminum coating is suitable. The reflective coating can be applied either across the entire surface of the array substrate or selectively to only the side walls.

[0036] The housing opening can be sealed with a cover substrate that is optically transparent or transparent to the UV light emitted by the light-emitting chips. To improve the efficiency of light extraction, the cover substrate may have an anti-reflective coating on the front and / or back. It may be possible to use preferred materials for the cover substrate depending on the wavelength of the UV light emitted by the light-emitting chips. For wavelengths up to 300 nm, for example, borosilicate glass may be used. For wavelengths up to [missing value], pure quartz glass may be used, for example. The use of sapphire glass is also possible.

[0037] In particular, wall sections of the array substrate, which form partitions between adjacent openings, can be produced with a cross-sectional profile that tapers away from the support substrate, optionally up to a pointed end shape.

[0038] The light-emitting chips can be arranged on the substrate using a flip-chip process. In flip-chip assembly, the contacting of unpackaged semiconductor chips is achieved via contact bumps. The semiconductor chip is mounted directly, without any additional connecting wires, with the contact side of the chip facing downwards, i.e., towards the substrate. This further facilitates short conductor lengths and small dimensions of the chip package. In this way, heat generated during operation is optimally dissipated within the epitaxial layer system towards the thermally coupled substrate.

[0039] In one embodiment, an silicon semiconductor substrate can be used for the support substrate. When using a silicon semiconductor substrate for the support substrate, one embodiment provides for the integration of a blocking or protection diode associated with the light-emitting chip, for example, a Zener diode, as a pn junction into the silicon semiconductor substrate. Silicon support substrates can be fabricated using wafer-level processes. In addition to the electrical contacts and vias, a suitable diode can be directly and efficiently integrated into the silicon semiconductor substrate using conventional doping processes. Alternatively, the protection diode can be accommodated in a recess on the back side of a wall section of the array substrate, for example, when using an aluminum nitride array substrate.Alternatively or additionally, one or more protection diodes can also be applied peripherally to the substrate, i.e., outside the array substrate. The array can be fabricated at the wafer level, so that it is produced as a wafer assembly. Subsequently, the wafer can be separated into several sub-arrays, each containing multiple UV-emitting chips with their own packages based on the array substrate.

[0040] It is possible to fabricate the array substrate and the top substrate at the wafer level and also to bond them together at the wafer level. Subsequently, the composite of array substrate and top substrate can be separated into the desired XY array format, for example, by sawing. A semi-finished product produced in this way, with the array substrate in the desired XY format and top substrate, is then mounted onto a carrier substrate populated with the light-emitting chips. This mounting then takes place at the "chip level" or "sub-array level." Alternatively, when using a silicon wafer as the carrier substrate, it is possible to bond a silicon carrier substrate populated with the light-emitting chips to the substrate composite consisting of the top substrate and the array substrate at the wafer level.

[0041] Each of the packaged light-emitting chips in the array can be associated with an optical lens mounted on the deck substrate. This lens is configured to focus the UV light emitted by the respective light-emitting chip, resulting in a focused beam of light exiting the package. One possible method for connecting the optical lenses to the deck substrate is to serially connect them via metallizations applied to the underside of the optical lens and correspondingly to the top side of the deck substrate. This involves soldering the optical lenses individually to the deck substrate. Alternatively, the optical lenses can be individually bonded to the top side of the deck substrate using adhesive bonding processes. Another option is to perform the process of applying the optical lenses at the wafer level. This requires the fabrication of a lens substrate at the wafer level.For example, it may be possible to produce a suitable substrate at this point, for instance by means of mechanical embossing, and then align the produced substrate with the array substrate. Alternatively, desired lens geometries can also be transferred into the top substrate 20 using mask-supported plasma etching processes or serial ion beam processes.

[0042] In one example, a method for manufacturing a semi-finished product and the semi-finished product itself may be provided. The method comprises the following: providing a semiconductor substrate; manufacturing an array substrate, in which openings with inclined sidewalls are formed in the semiconductor substrate by etching; placing a cover substrate on the array substrate such that the openings on a front side opposite the inclined sidewalls are closed by the cover substrate, while the openings on the respective back side remain open. The semi-finished product thus manufactured can then optionally be mounted with its back side facing a carrier substrate, such that one or more electronic components, previously mounted on the carrier substrate, are accommodated in each of the openings, for example, UV-emitting diodes.In conjunction with the semi-finished product, the configurations described above in connection with the array substrate and / or the top substrate can be provided accordingly. For example, it can be provided that for the wall sections of the array substrate that define the openings, a first wall section, starting from the back, has a first build height, and a second wall section, which differs from the first wall section and also starts from the back, has a second build height that differs from the first build height. The different build heights can be achieved by appropriately designing the etching process(es).When the top substrate is then placed on the array substrate, it rests on the respective top surface of the taller wall sections of the array substrate, whereas the shorter wall sections, particularly their top surfaces, have a gap to the rear (the side facing the array substrate) of the top substrate. In conjunction with the mounting of the semi-finished product, for example on the support substrate, this also means that, due to this gap, an opening or passage is formed between adjacent openings, each of which forms a build or receiving space (housing) for one or more electronic components.

[0043] In conjunction with the array of multiple UV light emitting chips, the previously described configurations in connection with the manufacturing process can be provided accordingly.

[0044] Further examples of implementation are described below with reference to figures of a

[0045] The drawing is explained in more detail. It shows:

[0046] Fig. 1 shows a schematic representation of an array substrate with an arrangement of openings;

[0047] Fig. 2 shows a schematic representation of an arrangement with the array substrate from Fig. 1 and a cover substrate arranged on it, in perspective and in section from the side;

[0048] Fig. 3 shows a schematic cross-sectional representation of an array of UV light emitting chips;

[0049] Fig. 4 shows a schematic cross-sectional representation of another array of UV light emitting chips;

[0050] Fig. 5 shows a schematic representation of the array from Fig. 3 with a cover substrate in section;

[0051] Fig. 6 shows a schematic representation of the array from Fig. 4 with a cover substrate in section;

[0052] Fig. 7 shows a schematic cross-sectional representation of another array with UV light emitting chips;

[0053] Fig. 8 shows a schematic representation of the other array from Fig. 7 with a cover substrate in section;

[0054] Fig. 9 shows a schematic representation of yet another array with UV light emitting chips in cross-section and

[0055] Fig. 10 shows a schematic perspective view of an array of light-emitting chips and their associated protective diodes in top view.

[0056] Fig. 1 shows a schematic representation of an array substrate 1. The array substrate 1 is produced by anisotropic etching starting from a semiconductor substrate, in particular from a Si semiconductor substrate. For example, wet etching of Si (silicon) in a 100° orientation over an aqueous KOH solution can be carried out.

[0057] By means of wet chemical etching, an arrangement of openings 2 and the sidewalls 3 surrounding each opening 2 are produced in the array substrate 1. The sidewalls 3 are inclined or tilted relative to the surface normal in Fig. 1. During fabrication, for example, a Si wafer is first coated over its entire surface and on both sides with a masking material (for example, silicon nitride). In a subsequent step, the masking material is then opened in the areas of the future openings 2 and etched anisotropically, for example, in a potassium hydroxide solution. In this etching process, in one embodiment, inclined

[0111] crystal planes, typical for the Si single crystal in

[0100] orientation, are formed at an angle of approximately 54.7° to the main direction.

[0058] With a different surface orientation, the side walls 3 can be manufactured with different flank angles. Dry etching processes allow for the production and targeted adjustment of flank angles that deviate from the standard. This enables the creation of shallower angles, for example, 30 degrees to 45 degrees, or steeper angles, for example, 60 degrees to 90 degrees. Optionally, parabolic or spherical slopes can be produced using ion beam etching.

[0059] The use of silicon as a semiconductor substrate has the advantage of high thermal conductivity, which facilitates the dissipation of heat generated during operation.

[0060] According to Fig. 1, the array substrate 1 has first wall sections in the form of partition or spacer walls 4a between the openings 2, which are arranged between adjacent openings 2. In addition, second wall sections in the form of edge walls 4b are formed, which delimit the openings 2 towards the edge of the array substrate 1.

[0061] Fig. 2 shows schematic representations of an arrangement with the array substrate 1, on which a cover substrate 20 is arranged, covering build or receiving spaces 21 that are formed in the openings 2 in the array substrate 1 and are laterally bounded by the respective side walls 3. The array substrate 1 from Fig. 1 or the arrangement from Fig. 2, in which the cover substrate 20 is arranged on the array substrate 1, can then be arranged on a support substrate 30, which is explained in more detail below with reference to Figs. 3 to 8 for various embodiments.

[0062] Figures 3 and 5 show schematic representations of an array 31 in which the array substrate 1 (see Figure 3) or the arrangement with array substrate 1 and cover substrate 20 (see Figure 2) is arranged or mounted on the support substrate 30, such that UV light-emitting chips 32, which may optionally be pre-mounted on the support substrate 30, can be arranged in the openings 2 on the support substrate 30. In this way, a housing 33 is produced for the UV light-emitting chips 32, either in an open design (see Figure 3) or in a closed design (see Figure 5).

[0063] The array substrate 1 is connected to the support substrate 30 via contact surfaces 30a. Depending on the requirements, this connection can be achieved by adhesive bonding or soldering. In the latter case, both the array substrate 1 and the support substrate 30 are provided with appropriate metallizations.

[0064] In the UV light-emitting chips 32, a total side area comprising all side surfaces 32a of the light-emitting chip 32 constitutes at least 60% of the total light-emitting area of ​​the light-emitting chip 32, which is formed by the side surfaces 32a and a top surface 32b of the light-emitting chip 32. Alternatively, the total side area of ​​the light-emitting chip 32 can constitute at least 70% of the total light-emitting area. In another embodiment, the total side area constitutes at least 90% of the total light-emitting area of ​​the UV light-emitting chip 32.

[0065] The light-emitting chips 32 emit UV light via both the side surfaces 32a and the top surface 32b. The light emitted via the side surfaces 32a is reflected at the side walls 3 and exits the housing 33 via a housing opening 34 (top-side opening of the opening 2) (see, for example, arrow A in Fig. 3).

[0066] To improve the extraction of light from the side walls of the UV-emitting chip 32, the side walls 3 have a reflective coating 35, which can be optimized for the reflection of UV light. For this purpose, a metallic coating, such as an aluminum coating, is provided. Dielectric coatings can also be used.

[0067] Electrical contacts 36a and 36b are produced on the front and back surfaces of the substrate 30, which is, for example, a printed circuit board. These contacts are formed, for example, as conductive traces. The front and back electrical contacts 36a and 36b can be connected via vias 37. The UV light-emitting chips 32 are mounted on the substrate 30, for example, using a flip-chip process, and are thus connected to the electrical contacts 36a and 36b. Alternatively, the connections can be made via wire bonds.

[0068] The electrical contact between light-emitting chips 32 and the substrate 30 is achieved by means of electrical contacts 36a, 36b. These electrical contacts can be structured, for example, by sputtering and plating processes, etching, or lift-off processes. The electrical contacts 36a, 36b can consist of suitable metal stacks. In addition to adhesion-promoting layers such as Ti or WTi, the stacks can include electrically and thermally conductive metals such as copper. To prevent subsequent alloying and thus delamination of the electrical contacts 36a, 36b during the soldering process, metals such as Pd or Ni can be used as an alloy stop. The actual contact with the solder during assembly can be formed on final wetting layers, for example, made of gold.

[0069] These provisions also apply to the rear electrical contacts 36b and to the metallization of a heat pad 38. This serves for the subsequent thermal contact of the substrate 30, for example, to a heat sink (not shown). Dissipating the generated heat is essential for the operation of the light-emitting chips 32, as the efficiency of the chips decreases significantly at excessively high temperatures. The maximum operating temperature in the housing, the so-called junction temperature, is between 100 °C and 120 °C for the light-emitting chips. Preferably, the light-emitting chips 32 are operated at approximately 80 °C.

[0070] For example, the assembly of the light-emitting chips 32 may involve the use of an Au / Sn (gold / tin) solder. This is melted at temperatures of approximately 320°C and then forms the eutectic solder joint between the light-emitting chip 32 and the support substrate 30 at approximately 280°C.

[0071] To prevent the solder joint between the light-emitting chip 32 and the substrate 30 from remelting, solders with a lower processing temperature are selected for the subsequent electrical and thermal contacting of the substrate 30. Solders made of tin and silver are particularly suitable. These can be applied advantageously using a wave soldering process and have a processing temperature of approximately 250°C. As explained above, other combinations of solders are also suitable. Alternatively, the light-emitting chips 32 can be contacted using a tin / silver solder. In this case, a low-melting-point solder joint, such as an indium solder joint, is suitable for the electrical and thermal contacting of the array.

[0072] For example, aluminum nitride can be used as the material for the support substrate 30. This material has a very high thermal conductivity of 200 W / m*K. Through-hole plated submounts made of silicon are also conceivable here. So-called IMS substrates (Insulated Metal Substrates) made of copper or aluminum can also be used.

[0073] In the embodiment shown in Fig. 5, the housing opening 34 on the top side is closed by the top substrate 20. To further improve the extraction of UV light, the top substrate 20 can be provided with an anti-reflective coating on its front and / or back side.

[0074] Depending on the requirements, the connection between the top substrate 20 and the array substrate 1 can be quasi-hermetically or hermetically sealed. The "hermetically sealed" configuration refers to cases where the connection is made, for example, via a direct bonding process. Such processes include anodic bonding, which requires the direct joining of silicon to an alkali-containing glass at high temperature and under an applied electrical voltage. Alternatively, an anodic bonding process can also be used directly between aluminum and an alkali-containing borosilicate glass.

[0075] For direct bonding processes, the actual bonding surface on the array substrate 1 is exposed by removing the coating from the side walls 3, for example, with aluminum. This is typically achieved technologically by spraying the coating onto the 3D structure and lithographically removing the coating from the side walls 3. After subsequent deposition of the metal on the angled side walls 3 and subsequent lift-off of the coating on the top surface of the array substrate 1, the actual surface is then exposed for the anodic bonding process.

[0076] Since alkali-containing, anodically bondable borosilicate glasses are only suitable for the near-UV range due to their transmission, pure quartz glasses are used as the top substrate 20 for applications in the far-UV-C range (deep-UV). However, unlike alkali-containing borosilicate glasses, these cannot be anodically bonded. In these cases, plasma-activated direct fusion bonding processes are preferred. Here, a very good surface roughness of no more than 5 nm, combined with high surface energy, is used to form covalent bonds through plasma activation at the substrate contact. Since direct contact between the top substrate 20 and the array substrate 1 is also required here, the deposition of the aluminum is structured as described previously.

[0077] Alternatively, for applications in the far-UV range, the connection of a quartz cover glass to the array substrate 1 can also be achieved by joining a solderable metallization. In this case, a suitable metallization must be applied to both the cover substrate 20 and the surface of the array substrate 1. The actual joining is then carried out, as previously described, using a suitable soldering process.

[0078] The top substrate 20 can also be connected to the array substrate 1 using a laser welding process. However, this process is serial and therefore time-consuming and expensive.

[0079] In quasi-hermetic bonding processes, adhesives or structurable polymers are used. However, these bonding processes have a disadvantage, particularly in applications in the far-UV range, that these joining organic materials tend to degrade when irradiated with very short-wavelength light, resulting in inadequate encapsulation.

[0080] Alternatively, sapphire substrates can be used in plasma-activated direct bonding or soldering processes with metallic layers. However, these are difficult to obtain in sufficient quality for the bonding process and are also very expensive.

[0081] The top substrate 20 can be provided with coatings. For example, coatings for anti-reflective properties in the desired spectral range (AR coatings) can be applied. These coatings can be applied to one or both sides. The coatings can be microstructured. In the examples in Figures 3 and 5, the partition walls 4a, extending from the carrier substrate 30, have the same height as the edge walls 4b, so that the top substrate 20, as shown in Figure 5, rests on both the partition walls 4a and the edge walls 4b.

[0082] Figures 4 and 6 show schematic representations of another array 50 with UV light-emitting chips. The same reference numerals are used in Figures 4 and 6 as in Figures 3 and 5 for identical features.

[0083] In contrast to the embodiments shown in Figures 3 and 5, the partition or spacer walls 4a have a lower height than the edge walls 4b. As a result, in the embodiment shown in Figure 6, a gap 40 is formed between the partition wall 4a and the top substrate 20, so that an opening or passage is created between the two adjacent openings 3.

[0084] The following procedure can be used to manufacture the embodiment: In a first masking step, a first cavity is anisotropically etched into the semiconductor substrate, although a complete breakthrough does not yet occur. In a second masking step, further silicon reflectors (sidewalls) with a shallower overall height are created in the already recessed cavity. In this second masking and etching step, the outer, taller reflectors are also completely etched through. The result is array-limiting tall reflectors (edge ​​walls 4b) in combination with shallower, inner reflectors (partition walls 4a).

[0085] Compared to Fig. 3, this arrangement has the advantage that the narrower reflectors inside the array substrate 1 allow for a reduction in the spacing between the light-emitting chips 32. This also reduces the overall size of the array, and with an adapted board design, more light-emitting chips 32 can be mounted on the same area. This further optimizes the ratio of module area to optical output.

[0086] In the examples shown in Figures 4 and 6, the partition 4a has a greater height than the UV light-emitting chips 32. Alternatively, the height of the light-emitting chips 32 and the height of the partitions 4a can be essentially the same.

[0087] Figures 7 and 8 show another embodiment of an array 60. The same reference numerals are used in Figures 7 and 8 for identical features as in Figures 3 to 6.

[0088] A recess 61 is formed in the edge wall 4b by etching, in which an electronic component 62 is accommodated when the array substrate 1 is mounted on the support substrate 30, as shown in Figures 7 and 8. The recess 61 provides a space for the electronic component 62, which is, for example, a Zener diode associated with the light-emitting chip 32.

[0089] The electronic component 62 can, for example, be mounted on the substrate 30 using a flip-chip method and is connected to the electrical contacts 36a, 36b and the via 37. In the illustrated embodiment, the recess 61 forms a closed installation space or a closed housing for the electronic component 62.

[0090] Fig. 9 shows a schematic representation of yet another array 70 with a similar construction to the array 31 of Fig. 5. Each housed light-emitting chip 32 of the array 70 is associated with an optical lens 71 formed on the top substrate 20. The optical lens 71 focuses the light emitted by the light-emitting chip 32, thus focusing the light exiting the housing. One method for connecting the optical lenses 71 to the top substrate 20 consists of serially connecting the optical lenses 71 via metallizations applied to the underside edge of the optical lens 71 and correspondingly to the top surface of the top substrate 20, i.e., soldering the optical lenses 71 individually onto the top substrate 20.

[0091] The optical lenses 71 can alternatively be individually applied to the top surface of the cover substrate 20 using adhesive bonding processes. Alternatively, the process of applying the optical lenses 71 can be carried out at the wafer level. This requires the production of a lens substrate at the wafer level. For example, a suitable substrate can be produced, perhaps by mechanical embossing, and then the produced substrate aligned with the array substrate 1. Alternatively, desired lens geometries can also be transferred to the cover substrate 20 using mask-supported plasma etching processes or serial ion beam processes.

[0092] Depending on the cover substrate 20 used and the wavelength employed, the optical lenses 71 consist of borosilicate glass, quartz glass or sapphire glass.

[0093] In another embodiment, the optical lenses 71 can be designed as Fresnel lenses. Mask-supported plasma etching processes or serial ion beam processes are used for the microstructuring of the Fresnel lenses. Alternatively, Fresnel lenses made of borosilicate glass, silicon dioxide, or aluminum oxide can be deposited and structured directly onto the substrate using a photolithographic lift-off process.

[0094] In addition to the use of optical lenses 71 in the optical beam path, the exit angle of the light can also be influenced by the height of the reflecting side walls 3. Particularly high spacer walls 4a can direct the emerging light and thus reduce the exit angle.

[0095] Fig. 10 shows another array 80 in an exemplary 6x5 configuration with a support substrate 30, an array substrate 1, and a top substrate 20, wherein light-emitting chips 32 are arranged in the receiving spaces 21. Protection diodes 81, for example Zener diodes, are mounted laterally on the support substrate 30 outside the array substrate 20 and are associated with the light-emitting chips 32. In the example shown, each of the protection diodes 81 is connected in parallel with a row of five light-emitting chips 32.

[0096] The features disclosed in the foregoing description, the claims and the drawing can be important for the realization of the various embodiments, both individually and in any combination.

Claims

Claims 1. Method for fabricating an array (31 ; 50; 60; 70; 80) with UV light emitting chips, comprising: - Providing a semiconductor substrate; - Production of an array substrate (1) wherein openings (2) with inclined side walls (3) are formed in the semiconductor substrate by etching; - Arranging light-emitting chips (32) designed to emit UV light on a support substrate (30) such that a component spacing is formed between adjacent light-emitting chips (32); and - Forming a housing (33) for the light-emitting chips (32) on the support substrate (30), wherein the array substrate (1) is arranged on the support substrate (30) such that a single light-emitting chip (32) is arranged in each of the openings (2) and that UV light emitted laterally from the light-emitting chip (32) in the opening (2) is reflected by means of the inclined side walls (3) of the opening (2) to a side facing away from the support substrate (30) through a housing opening (34); wherein in the light-emitting chips (32) a total side surface encompassing all side surfaces (32a) of the light-emitting chip (32) forms at least 60% of a total light-emitting area of ​​the light-emitting chip (32), which is formed by the side surfaces (32a) and a top surface (32b) of the light-emitting chip (32).

2. Method according to claim 1, characterized in that in the light-emitting chips (32) the total side area forms at least 70% of the total light-emitting area, preferably at least 90% of the total light-emitting area.

3. Method according to claim 1 or 2, characterized in that in the light-emitting chips (32) all lengths of edges of the chip are less than or equal to 0.5 mm, preferably less than or equal to 0.3 mm, more preferably less than or equal to 0.2 mm.

4. Method according to at least one of the preceding claims, characterized in that the light-emitting chips (32) have a chip thickness between 0.1 mm and 0.5 mm, preferably between 0.2 mm and 0.4 mm.

5. Method according to at least one of the preceding claims, characterized in that the light-emitting chips (32) in the openings (2) are formed with a height that is smaller than the height of the array substrate (1) starting from the support substrate (30).

6. Method according to at least one of the preceding claims, characterized in that light-emitting chips (32) are arranged which emit UV light with a wavelength of at most 350 nm, preferably at most 320 nm and further preferably at most 280 nm.

7. Method according to at least one of the preceding claims, characterized in that, for the openings (2) limiting wall sections of the array substrate (1), a first wall section starting from the support substrate (30) has a first height and a second wall section, which is different from the first wall section, starting from the support substrate (30) has a second height which is different from the first height.

8. Method according to at least one of the preceding claims, characterized in that electrical contacts (36a, 36b) are made on the front and back of the carrier substrate (30) for electrical contacting the light-emitting chips (32), wherein at least a part of the electrical contacts (36a, 36b) are electrically connected via a through-hole (37) and the light-emitting chips (32) are connected to the electrical contacts (36a, 36b).

9. Method according to at least one of the preceding claims, characterized in that, in order to dissipate operating heat generated during the operation of the light-emitting chips (32), heat sinks are formed on the support substrate (30) which are thermally connected to the light-emitting chips (32).

10. Method according to at least one of the preceding claims, characterized in that a recess (61) for receiving an electronic component (62) is produced in a wall section of the array substrate (1) which surrounds one of the openings (2).

11. Method according to claim 10, characterized in that the recess (61) is produced on the back side of the array substrate (1).

12. Method according to claim 10 or 11, characterized in that when arranging the array substrate (1) on the support substrate (30) the electronic component (62) is received in the recess (61).

13. Method according to at least one of the preceding claims, characterized in that a mirrored coating (35) is produced on the side walls (3) which reflect the UV light emitted laterally by the light-emitting chips (32) in the openings (2).

14. Method according to at least one of the preceding claims, characterized in that the housing opening (34) is closed with a cover substrate (20) which is transparent to the UV light emitted by the light-emitting chips (32).

15. Array (31; 50; 60; 70; 80), with: - an array substrate (1) with openings (2) formed in a semiconductor substrate by etching with inclined sidewalls (3); - light-emitting chips (32) designed to emit UV light, on a support substrate (30) such that a component spacing is formed between adjacent light-emitting chips (32); and - a housing (33) for the light-emitting chips (32) on the substrate (30), wherein the array substrate (1) is arranged on the substrate (30) such that a single light-emitting chip (32) is arranged in each of the openings (2) and that UV light emitted laterally from the light-emitting chip (32) in the opening (2) is reflected by means of the inclined side walls (3) of the opening (2) to a side facing away from the substrate (30) through a housing opening (34); wherein, in the case of the light-emitting chips (32), a total side surface comprising all side surfaces (32a) of the light-emitting chip (32) forms at least 60% of a total light-emitting area of ​​the light-emitting chip (32), which is formed by the side surfaces (32a) and a top surface (32b) of the light-emitting chip (32).

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