Test structure and fabricating method thereof

Abstract

The test structure comprises a polished surface (122) that comprises a plurality of groups (GROUP 1, GROUP 2, GROUP 3) of at least four lines (104C) of at least two different operational material layers (110, 112, 114, 116). Thickness (T) of said four lines (110, 112, 114, 116) of a group of the plurality of the groups (GROUP 1, GROUP 2, GROUP 3) is between 5 nm and 200 nm. The groups (GROUP 1, GROUP 2, GROUP 3) of the lines (104C) are 2 µm to 10 µm apart. The lines (104C) of the at least two different operational materials layer (110, 112, 114, 116) form a cross section of a shape of a wedge within the test structure (10), the angle of the wedge following a known crystal orientation of material of a substrate (10) of the test structure (10). The test structure (10) enables an area selective bottom- up process for imitating a fabricating phase of an electrical component, and analysis of the polished surface (118).

Description

[0001] Test structure and fabricating method thereof

[0002] Field

[0003] The invention relates to a test structure and its fabrication method.

[0004] Background

[0005] Area selective deposition (ASD) method is considered a useful bottom- up fabricating method for semiconductor devices, particularly at extreme linewidths. As the dimension scale-down of semiconductor devices continues, the top-down fabrication approach has dominated by lithography, but etching starts to hit limitations regarding the structuring of minimum feature sizes close to, at or below 100 nm, for example. The atomic layer deposition (ALD) process development, as well as precursor development, are critical steps at the moment before the ASD processes or materials can be adapted into the existing process flow of the advanced semiconductor devices. Test chips with narrow linewidths to test the process steps of ASD with or without the ALD are thus needed.

[0006] Brief description

[0007] The present invention seeks to provide an improvement in the test structures and their fabrication.

[0008] The invention is defined by the independent claims. Embodiments are defined in the dependent claims.

[0009] If one or more of the embodiments is considered not to fall under the scope of the independent claims, such an embodiment is or such embodiments are still useful for understanding features of the invention.

[0010] List of drawings

[0011] Example embodiments of the present invention are described below, by way of example only, with reference to the accompanying drawings, in which Figures 1 to 7B illustrate examples of successive fabrication phases of a test structure;

[0012] Figure 8 illustrates a test structure with four line areas;

[0013] Figure 9 illustrates a test structure with a roof; and

[0014] Figure 10 illustrates of an example of a flow chart of a fabrication method.

[0015] Description of embodiments

[0016] The following embodiments are only examples. Although the specification may refer to "an" embodiment in several locations, this does not necessarily mean that each such reference is to the same embodiment's), or that the feature only applies to a single embodiment.

[0017] Single features of different embodiments may also be combined to provide other embodiments. Furthermore, words "comprising" and "including" should be understood as not limiting the described embodiments to consist of only those features that have been mentioned and such embodiments may also contain features / structures that have not been specifically mentioned. All combinations of the embodiments are considered possible if their combination does not lead to structural or logical contradiction.

[0018] A test structure which may be a test chip or test substrate, should have patterns of different materials at the planar surface of the test structure. The patterns should be lines with the linewidths about 200 nm or less. Materials at the surface prohibits or slows down the growth of certain deposition materials such as titanium oxide, TiOz, TiN, SiOz, SisN4 etc. by the atomic layer deposition (ALD). Typical fabrication methods of narrow line patterns thus require extreme ultraviolet (EUV), ebeam litography or some other advanced patterning methods which are very slow and expensive method. Therefore, narrow line test structures for ASD are poorly accessible.

[0019] Typical fabrication methods require high-resolution photolithography utilizing 193 nm optical radiation. Use of such lithography equipment is possible only in leading-edge semiconductor lab facilities. Additionally, the ALD equipment add complexity and cost to the process.

[0020] Figs 1 to 7B illustrate examples of a test structure at various fabrication phases. In Fig. 1, a hard mask layer 102 is deposited on the surface of a substrate 100. The substrate 100, which typically is silicon, has a known crystal orientation. Silicon has a similar lattice structure to diamond. The crystal orientation may be defined by the Miller indices that contain three digits. The crystal orientation may be measured by a system utilizing X-ray diffraction. The silicon material may be cut to a desired plane such as <100>, <111> or <110>, for example. The surface on which the hard mask layer 102 is deposited is a crystal plane <100>. Other materials may also be used as a substrate, such as gallium nitride (GaN) or gallium arsenide GaAs, without limiting to these. They also have a known crystal orientation. A person skilled in the art is familiar with crystal orientations of silicon and other materials, perse.

[0021] The hard mask layer 102 on the silicon substrate 100 is then patterned lithographically for revealing the surface of the silicon substrate 100 in forms of a plurality of lines 104A of the hard mask layer 102 as illustrated in Figs 2A and 2B, where Fig. 2A illustrate the silicon substrate 100 seen from side and Fig. 2B illustrates the silicon substrate 100 seen from above. A person skilled in the art is familiar with lithography, perse. A width of each of the lines 104A of the hard mask layer 102 being about 1 gm or more and the lines 104A being about 1 gm or more apart. The hard mask is an etch mask that is not made of polymer (a polymer mask is called a soft mask). The hard mask may be made of silicon dioxide, silicon nitride, gold, silver and / or tantalum or the like. A person skilled in the art is familiar with the hard mask.

[0022] Grooves 106 are etched to the surface of the silicon substrate 100 at locations the lines 104A which are not covered by the hard mask layer 102 as illustrated in Fig. 3. The etching is guided by the known crystal orientation of the silicon material. Each of the grooves 106 has the shape of a cross section of a wedge. The wedge shape is caused by the angle between the crystal planes <100> and <111> of silicon, the angle being 35.3° with respect to a normal N1 of the surface of the silicon substrate 100. Depths D of the grooves may be in a range about 1 gm to about 2 gm, for example. The angle of the wedge follows the known crystal orientation of material of the substrate 10.

[0023] The shape of the wedge means that each of the grooves 106 is broadest at the level of the surface of the silicon substrate 100 and tapers toward the other end of the groove 106. The bottom of the groove 106 may have a V-shaped cross section that has a sharp angle or the groove 106 may have a flat bottom. In both cases, the walls of the groove 106 are the closer to each other the deeper in the groove 106 a distance between the walls is measured. The depth of the grooves 106 may be in a range of about lgm to about 2 gm, for example.

[0024] By performing the fabrication in this manner, off-orientation pattern and a line-edge-roughness will be corrected by undercut (see in Fig. 3, potential under etch). That would lead to a wider groove than the width of the line 104A of the hard mask layer 102. Still, the groove 106 will have accurately formed walls because silicon has been etched along the crystal orientation.

[0025] The hard mask layer 102 is removed as illustrated in Figs 4A and 4B, where Fig. 4A illustrates the silicon substrate 100 seen from side and Fig. 4B illustrates the silicon substrate 100 seen from above. The surface of the silicon substrate 100 has the lines 104B of the grooves 106 surrounded by a polished surface area 108 beside the lines 104B of the grooves 106. The polished area 108 is planar. The lines 104B of the grooves 106 are similar to those of lines 104A of the hard mask layer 102. A width of each of the lines 104B is about 1 gm to about 5 gm and the lines 104B being about 2 gm to about 10 gm apart. The removal of hard mask makes the following thin film deposition more accurate on the sidewall of the silicon substrate 100.

[0026] At least two different operational material layers 110, 112 are deposited on the substrate 100. In more detail, the first layer 110 is deposited directly on the silicon substrate 100 with the lines of the grooves 106, and the second layer 112 is deposited on the first layer 110. Any operational material layer after the first operational material layer 110 is deposited on a previous operational material layer. As shown in Fig. 5, A combined material thickness T1 of the at least two operational material layers 110, 112, 114, 116 is smaller than a depth of any of the grooves 106. A thickness T2 of a single layer 110, 112, 114, 116 may be in a range 5 nm to 200 nm. All layers 110, 112, 114, 116 may have the same thickness, or at least two layers 110, 112, 114, 116 may have different thicknesses.

[0027] A filling layer 118 that fills the grooves 106 is then deposited as illustrated in Fig. 6. At the grooves 106, the filling layer 118 extends at least up to a level of the operational layer 116 directly below the filling layer 118 or the polished area 108. This means that when the filling layer 118 is within the grooves 106, the upper surface of the filling layer 118 may be at a lower level than between the grooves 106. Still, the upper surface of the filling layer 118 at the grooves 116 is at the same level as the uppermost operational layer 116 or above it between the grooves 106.

[0028] In an embodiment, materials of the at least two different operational material layers 110, 112, 114, 116 may include at least two of the following: silicon, silicon nitride, silicon oxide and one or more metals. In an embodiment, the one or more metals may refer to copper, molybdenum, titanium dioxide and hafnium oxide, without limiting to these.

[0029] Finally, an upper section 120 of the silicon substrate 100 with the deposited layers 110, 112, 114, 116 on the polished area 108 is removed for finalizing the test structure 10, as illustrated in Figs 7A and 7B. Said upper section 120 is limited to the operational layer 112, 116 that is deposited last and that is directly below the filling layer 120. The upper section 120 thus refers to material layer of a constant thickness such that the silicon substrate 100 with the at least two operational material layers 110, 112, 114, 116 and the filling layer 118 is removed between a level of the polished area 118 and the deepest point of the filling layer 118 within the grooves 106. The limits of the material removal are at or below the level of the polished area 108 and above the deepest point of the filling layer 118 within the grooves 106. In that manner, the whole area of the test structure 10 becomes the polished surface 122. The polished surface 122 is planar, and its average deviation from a flat surface or a plane is less than about 5 nm, i.e. the surface planarity < 5nm. The surface planarity may also be called the surface flatness or sometimes also surface roughness.

[0030] The test structure 10 comprises the plurality of the separate lines 104C that are formed by the at least two different operational material layers 110, 112, 114, 116 within the filled grooves 106. Additionally, the filling layer 118 is among the lines 104C as can be understood based on Fig. 7A. Each of the filled groove 106 has all the operational material layers 110, 112, 114, 116 and the filling layer 118. The depositions of the hard mask 102 and the at least two operational material layers 110, 112, 114, 116 may be performed using a chemical vapor deposition (CVD) process, sputtering, a spin-on process, plasma enhanced atomic layer deposition (PEALD), plasma enhanced CVD (PECVD), epitaxy without limiting to these. A person skilled in the art is familiar with the deposition processes, perse.

[0031] In this document, the polished area 108 and the polished surface 122 refers to a regular surface that has no irregularities such as lumps, bulges and / or indentations. The regular surface may be flat.

[0032] In an embodiment, the upper section 120 of the silicon substrate 100 may be removed by chemical mechanical polishing (CMP) process for causing the polished surface 122 on the test structure 10. That leads to a smooth surface 122.

[0033] Chemical mechanical planarization (or polishing) may be used in the final fabrication process phase of the test structure 10 to remove excess material of the silicon substrate 100 and create the polished surface 122. The CMP utilizes both mechanical abrasion and chemical reactions for removing material and making the surface clean and smooth.

[0034] In an embodiment, the test structure 10 may be bondable with a chip by wafer bonding method to provide a roof on top of the test structure 10. The roof and the test silicon substrate 100 with the lines may then have a gap that can be defined in the fabrication process. This provides a lateral high aspect ratio structure for conformality measurement of the area selective deposition.

[0035] In an embodiment, alternating materials may be selected according to application of area selective deposition experimental needs. In an embodiment, the test structure 10 may be made for forming, growing or depositing at least one additional layer on the polished surface 122, which imitates a fabricating phase of an electrical component, optical component, mechanical component or any combination of these. The test structure 10 enables an analysis of the polished surface 122 with the at least one additional layer by at least one of the following: optical ellipsometry, optical reflectometry, optical scatterometry, optical critical dimension (OCD) metrology, scanning probe microscopy, atomic force microscopy (AFM), scanning electron microscopy and transmission electron microscopy.

[0036] The test structure 10 is measurable with AFM, OCD (scatterometry or ellipsometry) or other relevant measurement methods after area selective deposition to determine the selectivity, growth rate difference or defects on growth uniformity of the thin film on different material surfaces at the narrow linewidth. The OCD based measurement accuracy improves when the patterns with repeated structures cover larger area than the measurement spot which is diffraction limited (A. / 2). The minimum total width of the structure is 1 gm and the favourable number of patterns >100. The V-groove material dimensions can be optimized to enable optical field manipulation of the probing light so that it is sensitive to the properties of the area selective deposited material. The field manipulation can be based on the interference properties of the V-groove materials or their waveguide properties.

[0037] The analysis can be made directly without any preparations because only the polished surface 122 needs to be examined and analysed.

[0038] In an embodiment, an angle of the cross section of the wedge of the grooves 106 is based on crystal planes of planes 111 and 100 of silicon.

[0039] In an embodiment, silicon oxide, silicon nitride, gold, silver or tantalum layer may be deposited on the silicon substrate 100 as the hard mask layer 102. A plasma etching method, or a reactive-ion etching may be used for patterning the hard mask since it can maintain the critical dimension better than wet etch with chemicals, e.g. HF etching of SiOz.

[0040] In an embodiment, the silicon substrate 100 may be etched in a selfterminating process based on the known crystal orientation by potassium hydroxide (KOH) and / or tetramethylammonium hydroxide (TMAH). The selfterminating process means that when the bottom of the wedge formed grooves 106 has been reached, the grooves 106 do not deepen any longer.

[0041] In an embodiment, the at least two different operational material layers 110, 112, 114, 116 with a single layer having thicknesses between 5 nm and 200 nm may be deposited on the silicon substrate 100.

[0042] In an embodiment, the at least two different operational material layers 110, 112, 114, 116 may be deposited on the silicon substrate 100 with the lines 104B of the grooves 106. Materials of the at least two different operational material layers 110, 112, 114, 116 may comprise silicon nitride and silicon oxide. The materials used depend on the ASD process. Examples of materials are copper, molybdenum, titanium dioxide and hafnium oxide. In any case, one of the operational materials may be silicon.

[0043] Note also that the test structure 10 and / or the lines 104C may be exposed to various treatments which may include a thermal treatment, gas treatment, inhibition treatment or the like. Additionally, the test structure 10 and / or the lines 104C may be exposed to any combination of treatments. A person skilled in the art is familiar with various treatments, per se. The treatments may improve the quality of the test structure 10 and / or modify surface chemistry features.

[0044] All in all, the test structure 10 may be fabricated according to the fabricating method of claim 1. The test structure 10 comprises a polished surface 122 that comprises a plurality of groups GROUP 1, GROUP 2, GROUP 3 of at least four lines 104C of at least two different operational materials as shown in Figs 7A and 7B, where Fig. 7A illustrate the silicon substrate 100 seen from side and Fig. 7B illustrates the silicon substrate 100 seen from above. A thickness of each of the four lines 104C belonging to the groups GROUP 1, GROUP 2, GROUP 3 is between about 5 nm and about 200 nm. The number of lines 104C may be even. The groups GROUP 1, GROUP 1, GROUP 3 of the lines 104C are about 2 gm to about 10 gm apart.

[0045] A cross section of the at least two different operational materials 110, 112, 114, 116 of the lines 104C within the test structure 10 is a wedge. The test structure 10 makes an area selective bottom-up process possible for imitating a fabricating phase of an electrical component. Desired material may be grown on some of the lines 104C of operation material while other lines of different operational material may not have growth of the desired material, or the material growth may be minimal. A direct analysis of the polished surface 122 of the test structure 10 with or without material grown on the lines 104C can then be performed.

[0046] This kind of growth is called area-selective deposition (ASD), and it refers to formation of a material layer on a desired lines 104C without a mask layer on lines or areas that may not have the material grown on them. The growth or non-growth of material on the line 104C depends on the material of the line 104C. Additional material may alternatively be grown outside the lines 104C.

[0047] In an embodiment, surfaces of the grooves 106 and correspondingly the surfaces of the lines 104C of at least two different operational materials in the grooves 106 may form an angle a deviating from a normal N1 of a polished surface 122 of the test structure 10 based on a known crystal orientation of silicon. That means, the walls of the grooves 106 may not meet the surface of the polished surface 122 at right angle. The angle a may be about 35.3°.

[0048] In an embodiment, the angle a may deviate from the normal N1 of the polished surface 122 based on crystal planes 111 and 100 of silicon.

[0049] In an embodiment, the materials of the at least two different operational material layers 110, 112, 114, 116 may comprise silicon nitride Sis^and silicon oxide SiOz.

[0050] Fig. 8 illustrates an example of a test chip. Its size may be about 15 mm x 15mm, for example, where the test structure area may be 6mm x 6 mm, for example, and it may have four line areas 800, 802, 804, 806. Each line area may have about 1200 lines, for example. The lines of each line areas 800, 802, 804, 806 may parallel, or at least two line areas 800, 802, 804, 806 may have directions of lines that deviate from each other. Two line areas 800, 802 may have directions of lines that are orthogonal to the directions of lines of line areas 804, 806, for example. In an embodiment, an area within which the parallel lines 104C are may be about 1 m2or larger. In an embodiment, an area within which the parallel lines 104C are may be about 50 gm2, for example. The area may be even larger. The size of the area comprising lines the 104C may depend on the analysis methods relating to the test structure. Thus, the area may depend on whether the analysis method is optical or electron microscopical, for example. The size where the lines 104C are may thus be made suitable for the analysis.

[0051] The number of lines in the test structure may be at least two. In an embodiment, the number of the lines in the test structure may be in the range 50 to 100, for example. In an embodiment, the number of the lines in the test structure may be in a range 100 to 1000, for example. The number of lines may vary but there may be up to tens of thousands of parallel lines regularly arranged in a single area. The number of lines may be even larger than that. The lines 104C form repeated patterns in one or more areas.

[0052] Fig. 9A to 9C illustrate fabrication of the test structure 10 with a roof structure. Then the test structure 10 comprises a first part 850 that comprises the polished surface 122 with the groups of the lines 104 which is explained in Figs 1 to 8, and a second part 852, the word GROUPS referring to GROUP 1, GROUP 2, GROUP 3 in Fig. 7A. The second part 850, which is a potential but not a compulsory structure of the test structure, may be fabricated in a similar manner to the first part 850 in Figs 1 to Fig. 2A, or Fig. 1 to Fig. 4. The second part 852 may alternatively be fabricated in a different method. The second part 850 comprises one or more recesses 854 between layers 102. Alternatively, the one or more recesses 854 may be formed as grooves 106. The one or more recesses 854 do not need to have wedges as a shape of a cross section but their cross section may resemble a square or a rectangle instead.

[0053] In Fig. 9A the readymade second part 852 is above the first part 850. In Fig. 9B the second part 852 is in contact with the first part 850. The second part 852 then covers the groups of the lines 104C of the first part 850 such that the at least one recesses 854 face the lines 104C. Then the second part 850 and the groups of lines 104C have a non-zero distance therebetween at the one or more recesses 854, and there is a cavity 856 inside the test structure 10. The second party 852 thus forms a roof over the groups of lines 104C. The first part 850 and the second part 852 may be bonded together. A person skilled in the art is familiar with bonding, per se.

[0054] In an embodiment an example of which is illustrated in Fig. 9C, the second part 854 may be made thinner. The thinning method may be the chemical mechanical planarization, for example, without limiting to that. Additionally, a hole 858 may be made to each of the cavities 856 for enabling the ASD. Furthermore, the second part 854 may have one or more pillars 860 (an example of a pillar is shown in Figs 9A and 9C but not in Fig. 9B). The one or more pillars 860 may alternatively or additionally be made to the first part 850. The one or more pillars 860 support the roof.

[0055] Technical advantages include that the test structure makes the ASD process characterization fast, accurate and accessible.

[0056] Figure 10 is a flow chart of the fabrication method. In step 900, a hard mask layer 102 is deposited on a surface of silicon substrate 100, the silicon substrate 100 having a known crystal orientation.

[0057] In step 902, the hard mask layer 102 is patterned lithographically for revealing the surface of the silicon substrate 100 in forms of a plurality of lines 104A of the hard mask layer 102, a width of each of said lines 104A being 1 gm to 5 gm and said lines 104A being 2 gm to 10 gm apart.

[0058] In step 904 grooves 106 are etched to the surface of the silicon substrate 100 at locations of the lines 104A of the hard mask layer 102, the etching being guided by the known crystal orientation and forming the grooves 106 each having a cross section of a wedge.

[0059] In step 906, the hard mask layer 102 is removed, and then the surface of the silicon substrate 100 comprises lines 104B of the grooves 106 surrounded by a polished area 108 beside the lines 104B of the grooves 106.

[0060] In step 908, at least two different operational material layers 110, 112, 114, 116 are deposited on the silicon substrate 100 that has the lines 104B of the grooves 106, a combined material thickness T of the at least two different operational material layers 110, 112, 114, 116 being smaller than a depth D of any of the grooves 106.

[0061] In step 910 a filling layer 118 that covers the silicon substrate 100 and fills the grooves 106 is deposited on the at least two different operational material layers 110, 112, 114, 116.

[0062] In step 912, an upper section 120 of the silicon substrate 100 with the deposited layers 110, 112, 114, 116 is removed, said upper section 120 being limited to an operational layer of the operational layers 116 directly below the filling layer 118 within the grooves 106 for making a whole area of the test structure 10 with the plurality of the lines 104C of the at least two different operational material layers 110, 112, 114, 116 a polished surface 122, each of the filled groove 106 having all the operational layers 110, 112, 114, 116 and the filling layer 118.

[0063] It will be obvious to a person skilled in the art that, as technology advances, the inventive concept can be implemented in various ways. The invention and its embodiments are not limited to the example embodiments described above but may vary within the scope of the claims.

Claims

What is claimed is:

1. The test structure, characterized in that the test structure comprises a polished surface (122) that comprises a plurality of groups (GROUP, GROUP 1, GROUP 2, GROUP 3) of at least four lines (104C) of at least two different operational material layers (110, 112, 114, 116), thickness (Tl) of each of said four lines (110, 112, 114, 116) of a group of the plurality of the groups (GROUP 1, GROUP 2, GROUP 3) being between 5 nm and 200 nm; the groups (GROUP, GROUP 1, GROUP 2, GROUP 3) of the lines (104C) being 2 gm to 10 gm apart; and the lines (104C) of the at least two different operational material layers (110, 112, 114, 116) forming a cross section of a shape of a wedge within the test structure (10), the angle of the wedge following a known crystal orientation of material of a substrate (10) of the test structure (10).

2. The test structure of claim 1, characterized in that the lines (110, 112, 114, 116) of at least two different operational materials form an angle deviating from a normal of a polished surface (118) of the test structure based on a known crystal orientation of silicon.

3. The test structure of claim 2, characterized in that the angle is configured to deviate from the normal (Nl) of the polished surface (118) based on crystal planes (111) and (100) of silicon.

4. The test structure of claim 1, characterized that the material of at least one of the operational material layers (110, 112, 114, 116) is one of the following: silicon, silicon nitride, silicon oxide and one or more metals. In an embodiment, the one or more metals may refer to copper, molybdenum, titanium dioxide and hafnium oxide.

5. The test structure of claim 1, characterized in that the test structure comprises at least one additional layer on the polished surface (122) of the test structure (10) that is configured to imitate at least one of the following: anelectrical component, optical component, mechanical component and a combination of these at a fabricating phase for enabling analysis of the polished surface (122) with the at least one additional layer by at least one of the following: optical ellipsometry, optical reflectometry, optical scatterometry, optical critical dimension (OCD) metrology, scanning probe microscopy, atomic force microscopy (AFM), scanning electron microscopy and transmission electron microscopy.

6. The test structure of claim 1, characterized in that the test structure comprises thousands of the lines (104C).

7. The test structure of claim 1, characterized in that a size of an area comprising lines (104C) may depend on the analysis methods.

8. The test structure of claim 1, characterized in that the test structure comprises a first part (850) that comprises the polished surface (122) with the lines (104C) and second part (852) that is attached to the first part (850), the second part (852) comprises a recess (854), and the second part (852) is configured to cover the lines (104C) the recess (854) facing the lines (104C) for the second part (852) and the lines (104C) having a non-zero distance therebetween.

9. A fabricating method of a test structure, characterized by depositing (900) a hard mask layer (102) on a surface of silicon substrate (100), the silicon substrate (100) having a known crystal orientation; pattering (902) the hard mask layer (102) lithographically for revealing the surface of the silicon substrate (100) in forms of a plurality of lines (104A) of the hard mask layer (102), a width of each of said lines (104A) being 1 gm to 5 gm and said lines (104A) being 2 gm to 10 gm apart; etching (904) grooves (106) to the surface of the silicon substrate (100) at locations of the lines (104A) of the hard mask layer (102), the etching being guided by the known crystal orientation and forming the grooves (106) each having a cross section of a wedge;removing (906) the hard mask layer (102), the surface of the silicon substrate (100) having lines (104B) of the grooves (106) surrounded by a polished area (108) beside the lines (104B) of the grooves (106); depositing (908) at least two different operational material layers (110, 112, 114, 116) on the silicon substrate (100) that has the lines (104B) of the grooves (106), a combined material thickness (Tl) of the at least two different operational material layers (110, 112, 114, 116) being smaller than a depth (D) of any of the grooves (106) and each line (104C) having thickness (T2) 5 nm to 200 nm; depositing (910) a filling layer (118) that covers the silicon substrate (100) and fills the grooves (106); removing (912) an upper section (120) of the silicon substrate (100) with the deposited layers (110, 112, 114, 116), said upper section (120) being limited to an operational layer of the operational layers (116) directly below the filling layer (118) within the grooves (106) for making a polished surface (122) of a whole area of the test structure (10) to have the plurality of the lines (104C) of the at least two different operational material layers (110, 112, 114, 116), each of the filled groove (106) having all the operational layers (110, 112, 114, 116) and the filling layer (118).

10. The method of claim 9, c h a r a c t e r i z e d in that depositing at least one additional layer on the polished surface (122) of the test structure (10) to imitate a fabricating phase of an electrical component for enabling analysis of the polished surface (122) with the at least one additional layer by at least one of the following: ellipsometry, refractometry, atomic force microscopy, scanning electron microscope and transmission electron microscope.

11. The method of claim 9, c h a r a c t e r i z e d in that an angle of the cross section of the wedge of the grooves (106) is based on crystal planes of planes (111) and (100) of silicon.

12. The method of claim 9, characterized by depositing silicon oxide, silicon nitride, gold, silver or tantalum layer on the silicon substrate as the hard mask layer (102), and patterning the hard mask layer (102) by hydrofluoric acid or buffered hydrofluoric acid.

13. The method of claim 9, characterized by etching the silicon substrate (100) in a self-terminating process based on the known crystal orientation by potassium hydroxide (KOH) and / or tetramethylammonium hydroxide (TMAH).

14. The method of claim 9, characterized by depositing the at least two different operational material layers (110, 112, 114, 116) with thicknesses between 5 nm and 200 nm on the silicon substrate (100).

15. The method of claim 9, characterized by depositing the at least two different operational material layers (110, 112, 114, 116) on the silicon substrate (100) with the lines of the grooves (104B), materials of the at least two different operational material layers (110, 112, 114, 116) including at least two of the following: silicon nitride, silicon oxide and one or more metals.

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