Semiconductor device

Abstract

Provided is a semiconductor device that is easily miniaturized. This semiconductor device includes a first conductive layer, a second conductive layer, a third conductive layer, a semiconductor layer, a first insulating layer, and a second insulating layer. The first insulating layer is located on the first conductive layer and has a slit that reaches the first conductive layer. The second conductive layer is located on the first insulating layer. The semiconductor layer has a first portion in contact with the second conductive layer, a second portion extending along the side surface of the first insulating layer inside the slit, and a third portion in contact with the upper surface of the first conductive layer inside the slit. The second insulating layer covers the semiconductor layer inside the slit, and the third conductive layer covers the second insulating layer inside the slit. The first conductive layer and the second conductive layer have different crystallinity, and the other is amorphous. The semiconductor layer has a crystal region having a continuous crystal orientation across the first portion, the second portion, and the third portion.

Description

Semiconductor Devices

[0001] 1. Field of the Invention One embodiment of the present invention relates to a semiconductor device, a transistor, or a memory device.

[0002] Note that one embodiment of the present invention is not limited to the above technical field. Examples of the technical field of one embodiment of the present invention disclosed in this specification and the like include semiconductor devices, display devices, light-emitting devices, power storage devices, memory devices, electronic devices, lighting devices, input devices, input / output devices, driving methods thereof, and manufacturing methods thereof. A semiconductor device refers to any device that can function by utilizing semiconductor characteristics.

[0003] In recent years, semiconductor devices have been developed, and LSIs such as CPUs (Central Processing Units), memories, and other large-scale integrated circuits (LSIs) are mainly used in semiconductor devices. A CPU is an assembly of semiconductor elements that have been processed from a semiconductor wafer and have semiconductor integrated circuits (at least transistors and memories) formed into chips, and on which electrodes serving as connection terminals are formed.

[0004] 2. Description of the Related Art A CPU, a memory, or other LSI semiconductor circuit (IC chip) is mounted on a circuit board, such as a printed wiring board, and is used as one of the components of various electronic devices.

[0005] Furthermore, a technique for constructing a transistor using a semiconductor thin film formed on a substrate having an insulating surface has attracted attention. Such transistors are widely applied to electronic devices such as integrated circuits and image display devices (also simply referred to as display devices). While silicon-based semiconductor materials are widely known as semiconductor thin films applicable to transistors, oxide semiconductors have also attracted attention as other materials.

[0006] Furthermore, it is known that a transistor including an oxide semiconductor has an extremely small leakage current in a non-conducting state. For example, Patent Document 1 discloses a low-power consumption CPU that utilizes the property of a small leakage current. Furthermore, Patent Document 2 discloses a memory device that can retain stored data for a long period of time.

[0007] In recent years, along with the trend toward smaller and lighter electronic devices, there has been an increasing demand for higher density integrated circuits. There is also a demand for improved productivity of semiconductor devices including integrated circuits. For example, Patent Document 3 discloses a technique for increasing the density of integrated circuits by stacking a first transistor using an oxide semiconductor film and a second transistor using an oxide semiconductor film to provide multiple memory cells in a superimposed manner. Patent Document 4 also discloses a vertical transistor in which a side surface of an oxide semiconductor is covered with a gate electrode via a gate insulator.

[0008] JP 2012-257187 A JP 2011-151383 A WO 2021 / 053473 JP 2013-211537 A

[0009] Takashi Koida, "High Mobility Transparent Conductive Film," National Institute of Advanced Industrial Science and Technology, AIST Photovoltaic Power Generation Research Results Report 2019, Internet <URL: https: / / unit.aist.go.jp / rpd-envene / PV / ja / results / 2019 / oral / T13.pdf>

[0010] An object of one embodiment of the present invention is to provide a semiconductor device that can be easily miniaturized. Another object is to provide a semiconductor device that enables high integration. Another object is to provide a semiconductor device in which a wiring load is reduced. Another object is to provide a highly reliable semiconductor device. Another object is to provide a semiconductor device that exhibits favorable electrical characteristics. Another object is to provide a semiconductor device with high operating speed.

[0011] An object of one embodiment of the present invention is to provide a semiconductor device, a memory device, or an electronic device having a novel structure. An object of one embodiment of the present invention is to alleviate at least one of the problems of the prior art.

[0012] Note that the description of these problems does not preclude the existence of other problems. Note that one embodiment of the present invention does not necessarily solve all of these problems. Note that problems other than these can be extracted from the description of the specification, drawings, claims, etc.

[0013] One embodiment of the present invention is a semiconductor device having a first conductive layer, a second conductive layer, a third conductive layer, a semiconductor layer, a first insulating layer, and a second insulating layer. The first insulating layer is located on the first conductive layer and has a slit reaching the first conductive layer. The second conductive layer is located on the first insulating layer. The semiconductor layer has a first portion in contact with the second conductive layer, a second portion along a side surface of the first insulating layer inside the slit, and a third portion in contact with the first conductive layer inside the slit. The second insulating layer covers the semiconductor layer inside the slit, and the third conductive layer covers the second insulating layer inside the slit. The first conductive layer and the second conductive layer have different crystallinity. The semiconductor layer has a crystalline region with a continuous crystal orientation across the first portion, second portion, and third portion.

[0014] Another embodiment of the present invention is a semiconductor device including a first conductive layer, a second conductive layer, a third conductive layer, a fourth conductive layer, a semiconductor layer, a first insulating layer, a second insulating layer, a third insulating layer, and a fourth insulating layer. The first insulating layer is located on the first conductive layer and has a first slit reaching the first conductive layer. The second conductive layer is located on the first insulating layer. The semiconductor layer has a first portion in contact with the second conductive layer, a second portion along a side surface of the first insulating layer inside the first slit, and a third portion in contact with the first conductive layer inside the first slit. The second insulating layer covers the semiconductor layer inside the first slit, and the third conductive layer covers the second insulating layer inside the first slit. The third insulating layer is located below the first insulating layer and has a second slit. The fourth conductive layer has a portion along a side surface of the third insulating layer inside the second slit. The first conductive layer has a portion located inside the second slit. The fourth insulating layer is located inside the second slit between the first conductive layer and the fourth conductive layer. The first conductive layer and the second conductive layer have different crystallinity. The semiconductor layer has a crystalline region with a continuous crystal orientation across the first portion, the second portion, and the third portion.

[0015] In any of the above, the semiconductor layer preferably contains an oxide containing indium. Furthermore, the first conductive layer is preferably polycrystalline and contains an oxide containing indium and tin. Furthermore, the second conductive layer is preferably amorphous and contains an oxide containing indium, tin, and silicon.

[0016] Alternatively, in any of the above, the semiconductor layer preferably contains an oxide containing indium.Furthermore, the first conductive layer is preferably amorphous and contains an oxide containing indium, tin, and silicon.Furthermore, the second conductive layer is preferably polycrystalline and contains an oxide containing indium and tin.

[0017] In the above, the first slit and the second slit preferably extend in a first direction. The third conductive layer preferably extends in the first direction within the first slit. The fourth conductive layer preferably extends in the first direction within the second slit.

[0018] In the above, the first slit preferably extends in a first direction. The second slit preferably extends in a second direction intersecting the first direction. The third conductive layer preferably extends in the first direction within the first slit. The fourth conductive layer preferably extends in the second direction within the second slit.

[0019] In the above, it is preferable that the semiconductor device further includes a fifth conductive layer and a connection electrode. In this case, it is preferable that the first slit extends in a first direction. It is also preferable that the third conductive layer extends in the first direction within the first slit. It is also preferable that the fifth conductive layer is located on the third conductive layer and extends in a second direction intersecting the first direction. It is also preferable that the connection electrode connects the fifth conductive layer and the second conductive layer.

[0020] In the above, it is preferable that the semiconductor device further includes a fifth conductive layer. In this case, it is preferable that the first slit extends in a first direction. It is preferable that the second conductive layer extends in the first direction. It is also preferable that the fifth conductive layer contacts the third conductive layer and extends in a second direction intersecting the first direction.

[0021] In the above, the first conductive layer preferably has a recess in a region overlapping with the first slit, and the semiconductor layer, the second insulating layer, and the third conductive layer preferably have bottoms that are provided along the recess.

[0022] In the above, it is preferable that the semiconductor device further includes a sixth conductive layer. In this case, it is preferable that the second slit reaches the sixth conductive layer. It is also preferable that the fourth conductive layer contacts the sixth conductive layer inside the second slit.

[0023] In the above, the fourth insulating layer preferably has a film exhibiting ferroelectricity. In this case, the film exhibiting ferroelectricity is preferably a film containing hafnium oxide, zirconium oxide, or hafnium zirconium oxide.

[0024] In the above, the semiconductor layer, the second insulating layer, and the third conductive layer preferably have flattened upper surfaces, and the semiconductor layer preferably contacts a side surface of the second conductive layer.

[0025] According to one embodiment of the present invention, a semiconductor device that can be easily miniaturized, a semiconductor device that enables high integration, a semiconductor device in which the load on wiring is reduced, a highly reliable semiconductor device, a semiconductor device that exhibits favorable electrical characteristics, or a semiconductor device that operates at a high speed can be provided.

[0026] According to one aspect of the present invention, it is possible to provide a semiconductor device, a memory device, or an electronic device having a novel configuration. According to one aspect of the present invention, it is possible to at least alleviate at least one of the problems of the prior art.

[0027] Note that the description of these effects does not preclude the existence of other effects. Note that one embodiment of the present invention does not necessarily have all of these effects. Note that effects other than these can be extracted from the description in the specification, drawings, claims, etc.

[0028] FIGS. 1A to 1D are diagrams illustrating an example of a method for manufacturing a metal oxide film. FIGS. 2A to 2D are diagrams illustrating an example of a method for manufacturing a metal oxide film. FIGS. 3A to 3D are diagrams illustrating an example of a method for manufacturing a metal oxide film. FIGS. 4A and 4B are structural examples of a semiconductor device. FIG. 5 is a structural example of a semiconductor device. FIGS. 6A and 6B are structural examples of a semiconductor device. FIG. 7 is a structural example of a semiconductor device. FIG. 8 is a structural example of a semiconductor device. FIGS. 9A and 9B are structural examples of a semiconductor device. FIG. 10 is a structural example of a semiconductor device. FIG. 11 is a structural example of a semiconductor device. FIG. 12 is a structural example of a semiconductor device. FIGS. 13A and 13B are structural examples of a semiconductor device. FIGS. 14A and 14B are structural examples of a semiconductor device. FIGS. 15A and 15B are structural examples of a semiconductor device. FIGS. 16A and 16B are structural examples of a semiconductor device. FIGS. 17A and 17B are structural examples of a semiconductor device. FIGS. 18A and 18B are diagrams illustrating a structural example of a semiconductor device. FIGS. 19A and 19B are diagrams illustrating a structural example of a semiconductor device. FIGS. 20A to 20C are diagrams illustrating a manufacturing method example of a semiconductor device. FIGS. 21A to 21C are diagrams illustrating a manufacturing method example of a semiconductor device. FIGS. 22A and 22B are diagrams illustrating a manufacturing method example of a semiconductor device. FIGS. 23A and 23B are diagrams illustrating a manufacturing method example of a semiconductor device. FIGS. 24A and 24B are diagrams illustrating a manufacturing method example of a semiconductor device. FIGS. 25A and 25B are diagrams illustrating a manufacturing method example of a semiconductor device. FIGS. 26A and 26B are diagrams illustrating a manufacturing method example of a semiconductor device. FIGS. 27A and 27B are diagrams illustrating carrier concentration dependence of Hall mobility. FIG. 27C is a cross-sectional view illustrating an indium oxide film. FIG. 28 is a block diagram illustrating a structural example of a semiconductor device. FIGS. 29A to 29H are diagrams illustrating circuit configuration examples of memory cells. Fig. 30A and Fig. 30B are perspective views illustrating a configuration example of a semiconductor device. Fig. 31 is a block diagram illustrating a CPU. Figs. 32A and 32B are perspective views of a semiconductor device. Figs. 33A and 33B are perspective views of a semiconductor device. Figs. 34A and 34B are configuration examples of electronic components. Figs. 35A to 35C are configuration examples of a mainframe computer.Fig. 36A shows an example of the configuration of space equipment, and Fig. 36B shows an example of the configuration of a storage system.

[0029] Hereinafter, embodiments will be described with reference to the drawings. However, it will be readily understood by those skilled in the art that the embodiments can be implemented in many different ways and that various changes in form and details can be made without departing from the spirit and scope of the present invention. Therefore, the present invention should not be interpreted as being limited to the following description of the embodiments.

[0030] In the configuration of the invention described below, the same parts or parts having similar functions are denoted by the same reference numerals in different drawings, and repeated explanations thereof will be omitted. Furthermore, when referring to similar functions, the same hatching pattern may be used and no particular reference numeral may be assigned.

[0031] In the drawings described in this specification, the size of each component, the thickness of a layer, or an area may be exaggerated for clarity, and therefore, the drawings are not necessarily limited to the scale.

[0032] In this specification, ordinal numbers such as "first" and "second" are used to avoid confusion of components and do not limit the number.

[0033] A transistor is a type of semiconductor element that can perform functions such as amplifying current or voltage and performing switching operations to control conduction or non-conduction. The term "transistor" as used herein includes an insulated gate field effect transistor (IGFET) and a thin film transistor (TFT).

[0034] Furthermore, the functions of "source" and "drain" may be interchangeable when transistors of different polarities are used, or when the direction of current flow changes during circuit operation, etc. For this reason, the terms "source" and "drain" may be used interchangeably in this specification.

[0035] Furthermore, in this specification, "electrically connected" includes connection via "something that has some kind of electrical action." Here, "something that has some kind of electrical action" is not particularly limited as long as it allows electrical signals to be transmitted and received between the connected objects. For example, "something that has some kind of electrical action" includes electrodes or wiring, as well as switching elements such as transistors, resistive elements, coils, and other elements with various functions.

[0036] In this specification, when two nodes are connected via an insulator such as a dielectric of a capacitive element, a gate insulating film of a transistor, or an interlayer insulating film, this is not considered to be an "electrical connection."

[0037] In this specification, the phrase "top surface shapes generally match" refers to the overlap of at least a portion of the contours between stacked layers. For example, this includes cases where the upper and lower layers are processed using the same mask pattern or a portion of the same mask pattern. However, strictly speaking, the contours may not overlap, and the upper layer may be located inside the lower layer, or outside the lower layer. In these cases, the phrase "top surface shapes generally match" may also be used.

[0038] In this specification, the top surface shape of a certain component refers to the contour shape of the component in a plan view. The plan view refers to a view from the normal direction of the surface on which the component is formed or the surface of a support (e.g., a substrate) on which the component is formed.

[0039] In the following description, expressions indicating directions such as "upper" and "lower" are basically used in accordance with the directions in the drawings. However, for ease of explanation, the directions indicated by "upper" or "lower" in the specification may not match those in the drawings. For example, when explaining the stacking order (or formation order) of a laminate, etc., even if the surface on which the laminate is provided (such as a forming surface, a supporting surface, an adhesive surface, or a flat surface) is located above the laminate in the drawings, the forming surface side may be expressed as "lower" and the laminate side as "upper."

[0040] In this specification, the channel length direction of a transistor refers to one of the directions parallel to the line connecting the source region and the drain region at the shortest distance. In other words, the channel length direction corresponds to one of the directions of current flowing through the semiconductor layer when the transistor is in an on-state. The channel width direction refers to a direction perpendicular to the channel length direction. Depending on the structure or shape of the transistor, the channel length direction and the channel width direction may not be defined as a single direction.

[0041] In addition, in this specification and the like, the terms "film" and "layer" are interchangeable. For example, the term "insulating layer" may be interchangeable with the term "insulating film."

[0042] Unless otherwise specified, in this specification and the like, the off-state current refers to the drain current when a transistor is in an off state (also referred to as a non-conducting state or a cut-off state). Unless otherwise specified, the off-state refers to a state in which the gate-source voltage Vgs is lower than the threshold voltage Vth for an n-channel transistor (higher than Vth for a p-channel transistor).

[0043] Embodiment 1 In this embodiment, a metal oxide film of one embodiment of the present invention and a method for manufacturing the metal oxide film will be described.

[0044] One embodiment of the present invention is a crystalline metal oxide film formed along the side surface of an insulating layer. The metal oxide film is a metal oxide (also referred to as an oxide semiconductor) film having semiconductor properties and can be used as a semiconductor layer of a transistor.

[0045] The insulating layer is provided on the first conductive layer and processed so that its side surface is located on the first conductive layer. A second conductive layer is provided on the top surface of the insulating layer. The metal oxide film is provided in contact with the top surface of the first conductive layer, the side surface of the insulating layer, and the top surface and side surface of the second conductive layer. When such a configuration is applied to a transistor, the first conductive layer, the second conductive layer, and the metal oxide film function as one of the source and drain electrodes, the other of the source and drain electrodes, and the semiconductor layer of the transistor, respectively. A region of the semiconductor layer in contact with the side surface of the insulating layer functions as a channel formation region.

[0046] Here, the metal oxide film can be a single crystal film or a polycrystalline film. Furthermore, the metal oxide film preferably has a single continuous crystal grain extending from the upper end to the lower end of the side surface of the insulating layer. In other words, it is preferable that the crystal orientation be continuous from the portion in contact with the source electrode to the portion in contact with the side surface of the insulating layer to the portion in contact with the drain electrode, and that the metal oxide film has a single crystalline region without crystal grain boundaries within it. This prevents crystal grain boundaries (also called grain boundaries) that would obstruct current from crossing the current path between the source and drain electrodes, thereby improving the field-effect mobility of the transistor. Furthermore, crystal grain boundaries can act as carrier traps, which can affect the electrical characteristics of a transistor. Therefore, eliminating such crystal grain boundaries along the current path can achieve a highly reliable transistor.

[0047] Such a metal oxide film can be formed by forming an amorphous metal oxide film and then crystallizing it through heat treatment. In this case, it is preferable to use oxide conductive films with different crystallinity for the first conductive layer and the second conductive layer. For example, a crystalline oxide conductive film can be used for one of the first conductive layer and the second conductive layer, and an amorphous oxide conductive film can be used for the other. As a result, during the formation of the metal oxide film, a crystalline region reflecting the crystallinity of the oxide conductive film is formed in the portion of the metal oxide film that contacts the crystalline oxide conductive film. Then, by subsequent heat treatment, crystallization progresses starting from the crystalline region, thereby forming a metal oxide film having a single crystal grain extending from the upper end to the lower end of the side surface of the insulating layer.

[0048] Here, as the two oxide conductive films with different crystallinity, for example, one can be an amorphous film and the other can be a film with crystallinity such as single crystal, polycrystalline, or microcrystalline. Alternatively, both can be polycrystalline films. Regarding the crystallinity of polycrystalline films, the larger the crystal grains, the higher the crystallinity. Alternatively, the smaller the proportion of crystal grain boundaries in the film, the higher the crystallinity. The size of the crystal grains of an oxide conductive film or the area of ​​the aggregated grain boundaries per unit area can be estimated by observing a planar or cross-sectional view.

[0049] For example, when a polycrystalline film is formed on both of the two conductive layers, the portion of the metal oxide film that is close to the region in contact with the conductive layer with high crystallinity tends to crystallize preferentially, which may allow the size of the crystal grains in the channel formation region to be larger than when the two conductive layers are made of conductive films with the same crystallinity.

[0050] When a crystalline oxide conductive film is used for the first conductive layer, it is preferable to use an amorphous oxide conductive film for the second conductive layer. As a result, crystal growth of the metal oxide film starts from a crystalline region formed on the first conductive layer and progresses upward along the side surface of the insulating layer toward the second conductive layer. On the other hand, when a crystalline oxide conductive film is used for the second conductive layer and an amorphous oxide conductive film is used for the first conductive layer, crystal growth progresses downward along the side surface of the insulating layer from the second conductive layer toward the first conductive layer. As a result, a metal oxide film having a single crystal grain can be formed between the source electrode and the drain electrode.

[0051] As the metal oxide film, indium oxide is preferably used.

[0052] Furthermore, the indium oxide film preferably has crystallinity. For example, the indium oxide film preferably has crystal grains. Examples of films having crystal grains include single-crystal films, polycrystalline films, and amorphous films containing crystal grains. A polycrystalline film is composed of two or more crystal grains, whereas a single-crystal film can be considered to be composed of one crystal grain. While crystal grain boundaries are observed in polycrystalline films, crystal grain boundaries are not observed in single-crystal films.

[0053] Unlike polycrystalline films, grain boundaries are not observed in the channel formation region of single-crystal films. Impurities (typically, insulating impurities, insulating oxides, etc.) that hinder carrier flow are likely to segregate at grain boundaries. Therefore, when grain boundaries are present in the channel formation region, variations in transistor characteristics become significant. On the other hand, in the single-crystal film according to one embodiment of the present invention, grain boundaries are not observed in the channel formation region, which provides an excellent effect of suppressing variations in transistor characteristics due to the grain boundaries.

[0054] In this specification and the like, a semiconductor layer in which no crystal grain boundary is observed in the channel formation region, a semiconductor layer in which the channel formation region is included in one crystal grain, or a semiconductor layer in which the crystal axis direction is the same in at least two regions in the channel formation region can be called a single crystal film. Alternatively, a semiconductor layer in which at least one crystal orientation is oriented in one direction in the channel formation region can be called a single crystal film.

[0055] The channel formation region refers to a region of the semiconductor layer that overlaps (or faces) the gate electrode via the gate insulating layer and is located between the region in contact with the source electrode and the region in contact with the drain electrode. A semiconductor layer in which no crystal grain boundaries are observed in the region in contact with the source electrode and the region in contact with the drain electrode, a semiconductor layer in which the region in contact with the source electrode and the region in contact with the drain electrode is included in a single crystal grain, or a semiconductor layer in which the crystal axis direction is the same in at least two regions located between the region in contact with the source electrode and the region in contact with the drain electrode can also be called a single-crystalline film. Alternatively, a semiconductor layer in which at least one crystal orientation is oriented in one direction in the region in contact with the source electrode and the region in contact with the drain electrode can also be called a single-crystalline film.

[0056] In the channel formation region, the current path is the shortest distance between the source electrode and the drain electrode. Therefore, the crystal grains, crystal grain boundaries, crystal axes, crystal orientations, etc. in the channel formation region or in the region between the region in contact with the source electrode and the region in contact with the drain electrode can be confirmed by observing a cross section including the semiconductor layer, the source electrode, and the drain electrode.

[0057] A more specific example will be described below with reference to the drawings.

[0058] 1A to 1D are perspective schematic views showing a method for forming a metal oxide film.

[0059] First, a conductive layer 24, an insulating layer 41, and a conductive layer 25 are formed on an insulating layer 11 (FIG. 1A).

[0060] The insulating layer 11 functions as a base insulating layer. The substrate may be used without providing the insulating layer 11.

[0061] The conductive layer 24 provided on the insulating layer 11 includes an amorphous conductive metal oxide (oxide conductor). For example, it is preferable to use indium tin oxide (ITSO) containing silicon oxide at a concentration of 2 wt % to 10 wt %. By containing silicon at a concentration within this range, an amorphous film can be obtained while maintaining high conductivity. For example, the conductive layer 24 can be formed by a sputtering method using a target containing indium tin oxide (ITO) and silicon oxide at a concentration of 2 wt % to 10 wt %.

[0062] The insulating layer 41 functions as a spacer that electrically insulates the conductive layer 24 from the conductive layer 25. The insulating layer 41 is provided to cover the conductive layer 24, and has side surfaces that reach the top surface of the conductive layer 24. The insulating layer 41 may be provided with an opening or a groove (slit) that reaches the conductive layer 24, or may be processed into an island shape. The insulating layer 41 is preferably amorphous. This can prevent the semiconductor film 21f from crystallizing when it is formed.

[0063] The conductive layer 25 is provided on the insulating layer 41. FIG. 1A shows an example in which the side surfaces of the conductive layer 25 and the insulating layer 41 roughly coincide with each other in a planar view. It is preferable that the side surfaces of the conductive layer 25 and the insulating layer 41 are located as close as possible in a planar view. This prevents grain boundaries and crystal grains from being formed between the crystal grains formed on the upper surface of the conductive layer 25 and the crystal grains located on the side surfaces of the insulating layer 41 in the semiconductor film 21f, allowing these to form a single crystal grain. For example, by continuously processing the conductive layer 25 and the insulating layer 41 using the same resist mask, the side surfaces of the conductive layer 25 and the insulating layer 41 can be brought closer to each other. The distance between the side surfaces of the conductive layer 25 and the insulating layer 41 in a planar view is 0 to 5 μm, preferably 0 to 2 μm, and more preferably 0 to 1 μm.

[0064] The conductive layer 25 includes a crystalline conductive metal oxide. For example, a microcrystalline film, a polycrystalline film, or a single-crystalline film can be used, and a polycrystalline film or a single-crystalline film is more preferable. The crystalline nature of the conductive layer 25 allows the portion of the semiconductor film 21f formed on the conductive layer 25 that is in contact with the conductive layer 25 to be crystallized.

[0065] Indium-tin oxide (ITO) is particularly suitable for use as the conductive layer 25. ITO has high conductivity and is easily crystallized, so that a polycrystalline or single-crystalline film can be easily obtained.

[0066] It is preferable to use a material having a crystal structure with a small degree of lattice mismatch with the crystal structure of the material constituting the semiconductor film 21f as the conductive layer 25. This makes it easier for heteroepitaxial growth to occur when the semiconductor film 21f is formed on the conductive layer 25, and makes it easier to crystallize a portion of the semiconductor film 21f.

[0067] One method for evaluating the degree of lattice mismatch is to use the value of the lattice mismatch shown below. The lattice mismatch Δa [%] of the crystals of the formed film with respect to the crystals of the film to be formed is expressed as Δa = ((L １ -L ２ ) / L ２ ) × 100, where L １ is the length or lattice constant of the unit lattice vector of the crystal of the formed film, and L ２ is the length of the unit lattice vector or the lattice constant of the crystal of the film to be formed.

[0068] The smaller the absolute value of the lattice mismatch Δa between the conductive layer 25 and the semiconductor film 21f, the more preferable, and it is most preferable that it is 0. For example, Δa can be set to −5% or more and 5% or less, preferably −4% or more and 4% or less, more preferably −3% or more and 3% or less, and even more preferably −2% or more and 2% or less.

[0069] The conductive layer 25 preferably contains, for example, a metal oxide containing the same metal element as the semiconductor film 21f. In particular, both the conductive layer 25 and the semiconductor film 21f preferably contain one or more of indium, tin, and zinc. In particular, it is more preferable that both the conductive layer 25 and the semiconductor film 21f contain indium.

[0070] As an example of a combination of the conductive layer 25 and the semiconductor film 21f, for example, ITO may be used for the conductive layer 25, and indium oxide or indium-gallium-zinc oxide (IGZO) may be used for the semiconductor film 21f. Alternatively, indium-zinc oxide may be used for the conductive layer 25, and indium oxide or IGZO may be used for the semiconductor film 21f. Alternatively, ITO or tin oxide may be used for the conductive layer 25, and IGZO or indium-tin-zinc oxide may be used for the semiconductor film 21f. Note that the combination is not limited to these, and various combinations that satisfy the above may be used.

[0071] Next, a semiconductor film 21f is formed in contact with the upper and side surfaces of the conductive layer 25, the side surfaces of the insulating layer 41, and the upper surface of the conductive layer 24 (FIG. 1B). The semiconductor film 21f is a film containing a metal oxide (oxide semiconductor) that exhibits semiconductor properties.

[0072] The semiconductor film 21f can be formed by sputtering using a metal oxide target. At this time, it is preferable to form the film under conditions that make crystallization as difficult as possible. For example, an amorphous semiconductor film 21f can be formed by forming the film under conditions in which the substrate temperature during film formation is from room temperature to 100°C, preferably from room temperature to 80°C, and more preferably from room temperature to 50°C. In particular, it is preferable to form the film without heating the substrate. Also, conditions that make crystallization difficult can be achieved by lowering the oxygen content in the film formation gas. For example, the ratio of oxygen gas (O ２ The ratio of the flow rate of the gas) can be set to 0% or more and 10% or less, preferably 0% or more and 5% or less.

[0073] Immediately after the semiconductor film 21f is formed, a crystalline region 21C is formed in the region in contact with the conductive layer 25, and an amorphous region 21A is formed in the region in contact with the side surface of the insulating layer 41 and the top surface of the conductive layer 24. The region 21C has a crystal orientation that reflects the crystal orientation of the conductive layer 25. In FIG. 1B, the region 21C and the region 21A are indicated by different hatching patterns, and the boundary between them is indicated by a dashed line.

[0074] Next, heat treatment is performed ( FIG. 1C ). The heat treatment temperature can be 100°C or higher and 700°C or lower, preferably 100°C or higher and 500°C or lower, more preferably 100°C or higher and 400°C or lower, and even more preferably 150°C or higher and 400°C or lower. The heat treatment is performed in a nitrogen gas or inert gas atmosphere, or in an atmosphere containing 10 ppm or higher, 1% or higher, or 10% or higher oxygen gas. For example, when the heat treatment is performed in a mixed atmosphere of nitrogen gas and oxygen gas, the oxygen gas concentration can be approximately 20%. The heat treatment can also be performed under reduced pressure. The heat treatment time can be, for example, 15 minutes to 8 hours, preferably 30 minutes to 4 hours, more preferably 45 minutes to 2 hours, and typically 1 hour.

[0075] The heating device used for the heat treatment is not particularly limited, and may be a device that heats the workpiece by thermal conduction or thermal radiation from a heating element such as a resistance heating element. For example, an electric furnace or an RTA (Rapid Thermal Anneal) device such as an LRTA (Lamp Rapid Thermal Anneal) device or a GRTA (Gas Rapid Thermal Anneal) device can be used. The LRTA device is a device that heats the workpiece by radiation of light (electromagnetic waves) emitted from a lamp such as a halogen lamp, a metal halide lamp, a xenon arc lamp, a carbon arc lamp, a high-pressure sodium lamp, or a high-pressure mercury lamp. The GRTA device is a device that performs heat treatment using high-temperature gas.

[0076] When an RTA apparatus is used, the heat treatment time can be shortened, and may be set to 1 second or more and 5 minutes or less.

[0077] During the heat treatment, crystal growth proceeds from region 21C as a starting point, thereby expanding crystalline region 21C. The arrows in Fig. 1C indicate the direction in which crystal growth occurs, and crystal growth proceeds from top to bottom in the portion of semiconductor film 21f that contacts the side surface of insulating layer 41.

[0078] 1D, it is preferable that the crystalline region of the semiconductor film 21f extends to the portion in contact with the upper surface of the conductive layer 24. If the heat treatment is insufficient, an amorphous region may remain in the portion located above the conductive layer 24.

[0079] In this way, a highly crystalline semiconductor film 21f can be formed. In the semiconductor film 21f, the region between the source electrode and the drain electrode is composed of a single crystal grain, and no crystal grain boundary exists across the current path, so that a transistor having both high field-effect mobility and high reliability can be realized.

[0080] In the above, a crystalline conductive metal oxide is used for the conductive layer 25. However, as shown in FIGS. 2A to 2D , a crystalline conductive metal oxide may be used for the conductive layer 24, and an amorphous conductive metal oxide may be used for the conductive layer 25.

[0081] As shown in FIG. 2B, at the stage when the semiconductor film 21f is formed, a crystalline region 21C is formed in the portion in contact with the upper surface of the conductive layer 24, and an amorphous region 21A is formed in the portion in contact with the side surface of the insulating layer 41 and the portion in contact with the conductive layer 25.

[0082] Subsequently, by performing a heat treatment, as shown in Fig. 2C, crystal growth progresses from bottom to top in the portion of the semiconductor film 21f that contacts the insulating layer 41. After the heat treatment is completed, it is preferable that the crystalline region has expanded to the portion that contacts the conductive layer 25, as shown in Fig. 2D.

[0083] If the conductive layer 25 or the conductive layer 24 is polycrystalline, immediately after the semiconductor film 21f is formed, the portion of the semiconductor film 21f in contact with the conductive layer 25 or the conductive layer 24 may also become polycrystalline. Even in this case, since there is no grain boundary between the conductive layers 24 and 25 that straddles the current path, a transistor having both high field-effect mobility and high reliability can be realized.

[0084] 3A shows an example in which a polycrystalline conductive film is used for conductive layer 25 and an amorphous conductive film is used for conductive layer 24. Semiconductor film 21f has a polycrystalline structure, and a grain boundary 21gb exists between two adjacent crystal grains. In FIG. 3A, no grain boundary exists in the portion of semiconductor film 21f that contacts the side surface of insulating layer 41. Therefore, the channel formation region of semiconductor film 21f can be considered to be single crystal.

[0085] 3B shows an example in which crystal grain boundaries 21gb are present in a portion of semiconductor film 21f in contact with the side surface of insulating layer 41. In the portion in contact with the side surface of insulating layer 41, crystal grain boundaries 21gb are formed extending in the vertical direction so as to connect conductive layer 25 and conductive layer 24. Even in this configuration, no crystal grain boundaries 21gb that cross the current path between conductive layer 25 and conductive layer 24 are present, and therefore, in a broad sense, the channel formation region of semiconductor film 21f can be considered to be single crystal.

[0086] 3C and 3D show examples in which a polycrystalline conductive film is used for the conductive layer 24 and an amorphous conductive film is used for the conductive layer 25, respectively.

[0087] It is also possible to use a polycrystalline conductive film for both the conductive layer 24 and the conductive layer 25. This allows the conductive layer 24 and the conductive layer 25 to be formed under the same conditions, thereby reducing manufacturing costs. In this case, a crystal grain boundary may be formed so as to straddle the current path in the channel formation region of the semiconductor film 21f.

[0088] By using the method for forming a metal oxide film according to one embodiment of the present invention, a transistor in which no grain boundary that straddles a current path in a channel formation region exists can be realized, thereby realizing a transistor having both high field-effect mobility and high reliability.

[0089] This embodiment mode can be implemented by appropriately combining at least a part thereof with other embodiment modes described in this specification.

[0090] In this embodiment, a structural example of a semiconductor device according to one embodiment of the present invention and an example of a manufacturing method thereof will be described. The semiconductor device exemplified below can be applied to a memory device. The semiconductor film 21f exemplified in Embodiment 1 can be applied to a semiconductor layer of a transistor exemplified below.

[0091] A semiconductor device according to one embodiment of the present invention includes a plurality of memory cells, each of which includes one transistor and one memory element. The memory element can be any of various elements capable of storing stored data, such as a capacitor, a variable resistance element, a ferroelectric element, a charge trap element, and a floating gate element.

[0092] In a transistor included in a memory cell, a source electrode and a drain electrode are located at different heights, and a current flows in a semiconductor layer in a height direction. In other words, it can be said that the channel length direction has a component in the height direction (vertical direction). Therefore, one embodiment of the present invention can be called a VFET (Vertical Field Effect Transistor), a vertical transistor, a vertical channel transistor, a vertical channel transistor, or the like.

[0093] More specifically, a first insulating layer functioning as a spacer is provided above a lower electrode (first conductive layer) that is one of the source electrode and drain electrode, and an upper electrode (second conductive layer) that is the other of the source electrode and drain electrode is provided above the first insulating layer. A slit (first slit) extending in a first direction and reaching the lower electrode is provided in the first insulating layer. The slit has side surfaces that are approximately perpendicular to the substrate surface. The semiconductor layer has a portion that contacts the upper electrode, a portion that contacts the side surface of the first insulating layer inside the slit, and a portion that contacts the lower electrode inside the slit. Furthermore, a gate insulating layer (second insulating layer) is provided inside the slit to cover the semiconductor layer. Furthermore, a gate electrode (third conductive layer) is provided inside the slit to cover the gate insulating layer. The gate electrode is preferably provided so as to fill the slit.

[0094] The capacitor of the memory cell can be provided below the transistor. By stacking the transistor and the capacitor, memory cells can be arranged at high density. The capacitor can be a so-called MIM (Metal-Insulator-Metal) capacitor having a dielectric between a pair of electrodes. In this case, it is preferable that the lower electrode of the transistor also serves as the upper electrode of the capacitor. In this case, it is preferable that the upper electrode of the transistor functions as a bit line. Furthermore, by using a ferroelectric material for the dielectric of the capacitor, a ferroelectric capacitor can be formed. This makes it possible to realize a nonvolatile memory device.

[0095] The capacitor element has a portion located inside a slit (second slit) provided in a third insulating layer located below the first insulating layer. Specifically, the capacitor element has a lower electrode (fourth conductive layer) provided along the side and bottom surfaces inside the slit in the third insulating layer, a portion of the first conductive layer located inside the slit and functioning as an upper electrode of the capacitor element, and an insulating layer (fourth insulating layer) sandwiched between them, covering the lower electrode inside the slit and functioning as a dielectric. By configuring the capacitor element to have such a three-dimensional structure rather than a parallel plate type, it is possible to achieve both large capacitance and a small occupation area (footprint), thereby achieving high density memory cells.

[0096] The semiconductor layer is preferably made of a metal oxide (oxide semiconductor) that exhibits semiconductor properties. For example, silicon, a typical semiconductor material, needs to be doped with impurities that function as donors or acceptors to form source and drain regions. However, in the vertical transistor of one embodiment of the present invention, it may be difficult to dope impurities into the semiconductor layer with high precision because the source and drain regions are different in height and the channel formation region is located vertically relative to the substrate surface. On the other hand, an oxide semiconductor can be well connected to source and drain electrodes without doping with such impurities, and therefore a transistor having a three-dimensional structure as in one embodiment of the present invention can be manufactured with high yield.

[0097] Here, the upper electrode and the lower electrode of the transistor preferably have a stacked structure in which a first conductive film and a second conductive film are stacked thereon. In this case, the second conductive film is in contact with the semiconductor layer. Furthermore, the second conductive film preferably contains a conductive metal oxide (oxide conductor). Using a metal oxide for the conductive film in contact with the metal oxide-containing semiconductor layer is preferable because it can reduce the contact resistance between them and the wiring load. In particular, a configuration in which the second conductive film contains one or more of the same metal elements as the metal elements contained in the semiconductor layer is preferable because it can further reduce the contact resistance. Specifically, the semiconductor layer and the first conductive film preferably contain one or more of In, Sn, Zn, Ga, and Ti, and particularly preferably contains In. Furthermore, a low-resistance metal material can be used for the first conductive film. This makes it possible to reduce both the contact resistance and the wiring resistance, thereby further reducing the wiring load.

[0098] A more specific example will be described below with reference to the drawings.

[0099] [Configuration Example] Fig. 4A shows a schematic top view of a semiconductor device 50. Fig. 5 shows a perspective view of the semiconductor device 50. Figs. 6A, 6B, and 7 show schematic cross-sectional views taken along the cutting lines A-B, C-D, and E-F shown in Fig. 4A, respectively. Note that some components (insulating layers, etc.) are omitted from Figs. 4A and 5. Arrows indicating the X, Y, and Z directions are also shown in each figure.

[0100] The semiconductor device 50 has a configuration in which a plurality of memory cells 15 are arranged in the X and Y directions. In the semiconductor device 50, a conductive layer 26 functioning as a bit line extends in the X direction, and a conductive layer 23 functioning as a word line extends in the Y direction. As shown in FIG. 5 and other figures, the memory cell 15 has a transistor 10 and a capacitance element 30 therebelow.

[0101] 4B shows a circuit diagram corresponding to the semiconductor device 50. This diagram shows a plurality of wirings BL functioning as bit lines, a plurality of wirings WL functioning as word lines and intersecting (preferably perpendicular to) each bit line, and wirings CL. While FIG. 4B shows an example in which the wirings CL are parallel to the wirings BL, they may also be parallel to the wirings WL or may be arranged in a grid pattern. Alternatively, the wirings CL may be flat conductive films.

[0102] The memory cell 15 includes one transistor 10 and one capacitor 30. The transistor 10 has a gate connected to a wiring WL, one of a source and a drain connected to a wiring BL, and the other connected to one electrode of the capacitor 30. The other electrode of the capacitor 30 is connected to a wiring CL.

[0103] The wiring BL functions as a wiring for writing and reading data. The wiring WL functions as a wiring for controlling the on / off (conducting state or non-conducting state) of the transistor 10 functioning as a switch. The wiring CL functions as a constant potential line connected to the capacitor 30.

[0104] 5 and other drawings, the transistor 10 and the capacitor 30 are provided over an insulating layer 11 that is provided over a substrate (not shown). The insulating layer 11 functions as a base insulating layer.

[0105] The transistor 10 includes a semiconductor layer 21, an insulating layer 22 functioning as a gate insulating layer, a conductive layer 23 functioning as a gate electrode, a conductive layer 24 functioning as one of a source electrode and a drain electrode, and a conductive layer 25 functioning as the other electrode. Here, an example is shown in which the conductive layer 24 includes a conductive film 24a and a conductive film 24b located thereon, and the conductive layer 25 includes a conductive film 25a and a conductive film 25b located thereon.

[0106] Here, the crystalline semiconductor film 21f exemplified in Embodiment 1 can be applied to the semiconductor layer 21. The semiconductor layer 21 can be formed by removing unnecessary portions of the semiconductor film 21f by etching and processing it into a desired shape. The semiconductor layer 21 is made of a metal oxide (oxide semiconductor) that has crystallinity and exhibits semiconductor characteristics. In this case, conductive metal oxide (oxide conductor) is preferably used for the conductive layers 24 and 25 in contact with the semiconductor layer 21. By using metal oxide for the conductive films in contact with the metal oxide-containing semiconductor layer 21, the contact resistance therebetween can be reduced, the load on the wiring can be reduced, and the on-state current of the transistor 10 can be increased.

[0107] The capacitor 30 is provided on a conductive layer 55 that functions as a wiring CL. The capacitor 30 includes a conductive layer 51 that functions as a lower electrode, a conductive layer 24 that functions as an upper electrode, and an insulating layer 52 that is disposed between the conductive layer 51 and the conductive layer 24 and functions as a dielectric. In this manner, the conductive layer 24 preferably serves as both the lower electrode of the transistor 10 and the upper electrode of the capacitor 30. This simplifies the manufacturing process and reduces manufacturing costs. As shown in FIG. 5 and other figures, when the conductive layer 24 has a stacked structure of conductive films 24a and 24b, the lower conductive film 24a can function as the upper electrode of the capacitor 30. In this case, the upper conductive film 24b can also function as a connection electrode for connecting the conductive film 24a to the semiconductor layer 21.

[0108] A conductive layer 55 is provided on the insulating layer 11. Here, an example is shown in which the conductive layer 55 has a two-dimensional flat plate shape, but it may also be a wiring extending in the X direction, the Y direction, or another direction. Alternatively, it may have a lattice shape that combines two or more portions extending in different directions.

[0109] An insulating layer functioning as a protective insulating layer can be provided between the insulating layer 11 and the conductive layer 55. Alternatively, the insulating layer 11 may function as the protective insulating layer. The protective insulating layer has a function of preventing impurities such as hydrogen from diffusing into the semiconductor layer 21 from the insulating layer 11 or from below the insulating layer 11. For example, a film through which hydrogen is less likely to diffuse than a silicon oxide film (having barrier properties against hydrogen), such as a silicon nitride film, a silicon nitride oxide film, an aluminum oxide film, a magnesium oxide film, a hafnium oxide film, or a gallium oxide film, can be used. In particular, it is preferable to use a silicon nitride film or a silicon nitride oxide film.

[0110] In this specification and elsewhere, an oxynitride refers to a material having a higher content of oxygen atoms than nitrogen atoms, and a nitride oxide refers to a material having a higher content of nitrogen atoms than oxygen atoms. For example, silicon oxynitride refers to a material having a higher content of oxygen atoms than nitrogen atoms, and silicon nitride oxide refers to a material having a higher content of nitrogen atoms than oxygen atoms.

[0111] An insulating layer 46 is provided on the conductive layer 55. The insulating layer 46 functions as an interlayer insulating layer. A plurality of slits 40 are provided in the insulating layer 46, reaching the conductive layer 55. The slits 40 extend in the Y direction. A plurality of capacitive elements 30 corresponding to a plurality of memory cells 15 arranged in the Y direction are provided in the slits 40. It is preferable that the side surfaces of the insulating layer 46 within the slits 40 are approximately perpendicular to the substrate surface. It is preferable that the height of the insulating layer 46 is greater than its width in the X direction.

[0112] In this specification, "two surfaces are perpendicular" refers to a state in which the interior angle between them is 80 degrees or more and 100 degrees or less. "Two surfaces are approximately perpendicular" refers to a state in which the interior angle between them is 60 degrees or more and 120 degrees or less (including perpendicular). "Two surfaces are parallel" refers to a state in which the interior angle between them is -10 degrees or more and 10 degrees or less. "Two surfaces are approximately parallel" refers to a state in which the interior angle between them is -30 degrees or more and 30 degrees or less (including parallel).

[0113] The conductive layer 51 has a portion provided along the side surface of the insulating layer 46 at the slit 40 and a portion in contact with the upper surface of the conductive layer 55. The conductive layer 51 has a U-shaped cross section parallel to the X-Z plane and has a recess. The insulating layer 52 has a portion provided along the recess of the conductive layer 51, a portion in contact with the upper surface of the conductive layer 51, and a portion in contact with the upper surface of the insulating layer 46. The conductive layer 24 is provided so as to fill the recess of the conductive layer 51 via the insulating layer 52. The conductive layer 24 also has a portion provided on the insulating layer 46 via the insulating layer 52. The conductive layer 51 is provided so as to extend in the Y direction inside the slit 40. That is, the conductive layer 51 is provided in common to multiple capacitive elements 30 located in the Y direction. On the other hand, the conductive layer 24 is provided individually for each memory cell 15.

[0114] 8 shows a cross-sectional view taken along a plane G parallel to the X-Y plane shown in FIG. 7 , viewed from the Z direction. As shown in FIG. 8 , the conductive layer 51 is provided along the extension direction (Y direction) of the slit 40. Within the slit 40, the conductive films 24a are provided at equal intervals in the Y direction. Furthermore, at the Y-direction end of the slit 40, the conductive layer 51 and the insulating layer 52 are provided along the side surface of the insulating layer 44 (not shown), so that the conductive layer 51 and the insulating layer 52 each have a circular cross-sectional shape.

[0115] 5 and 6B show an example in which the bottom of the conductive layer 51 is rounded (has a concave curved surface). Furthermore, the bottom of the insulating layer 52 provided along the conductive layer 51 and the bottom of the conductive layer 24 provided along the insulating layer 52 also have a rounded shape (a convex curved surface). By configuring the conductive layer 51, which forms the surface on which the insulating layer 52 is formed, to have no corners, it is possible to prevent the insulating layer 52 from becoming locally thin. Furthermore, since the bottom of the conductive layer 51 has no corners, it is possible to prevent localized concentration of the electric field. This suppresses leakage current in the capacitance element, thereby improving reliability.

[0116] Furthermore, a rounded recess is provided on the top surface of the conductive layer 55, and the bottom of the conductive layer 51 is provided to fit into the recess. With this configuration, the contact area between the conductive layer 55 and the conductive layer 51 is increased compared to when the contact surface between the conductive layer 55 and the conductive layer 51 is flat, thereby reducing the contact resistance therebetween. The recess in the conductive layer 55 can be formed by etching a portion of the upper part of the conductive layer 55 when forming the slit 40 in the insulating layer 46.

[0117] The conductive film 24a is preferably made of a conductive material having a lower resistance than the conductive film 24b, and particularly preferably contains a metal material. The conductive film 24b is preferably made of a conductive metal oxide (oxide conductor).

[0118] Using a conductive metal oxide for the conductive film 24b in contact with the semiconductor layer 21 containing a metal oxide reduces the contact resistance between them and the wiring load, which is preferable. In particular, a configuration in which the conductive film 24b contains one or more of the same metal elements as the metal elements contained in the semiconductor layer 21 is preferable because the contact resistance can be further reduced. Specifically, it is preferable that both the semiconductor layer 21 and the conductive film 24b contain the same one or more elements selected from In, Sn, Zn, Ga, and Ti. In particular, it is preferable that the semiconductor layer 21 and the conductive film 24b contain In. Furthermore, using a metal material with a lower resistance than the conductive film 24b for the conductive film 24a reduces both the contact resistance and the wiring resistance, which makes it possible to further reduce the wiring load.

[0119] An insulating layer 41 is provided above the conductive layer 24 and the insulating layer 52. The insulating layer 41 has a strip-shaped slit 20 extending in the Y direction. It is preferable that the side surface of the insulating layer 41 within the slit 20 is approximately perpendicular to the substrate surface. It is preferable that the height of the insulating layer 41 is greater than its width in the X direction.

[0120] The conductive layer 25 is provided on the insulating layer 41. Here, an example is shown in which the conductive layer 25 has a laminated structure of a conductive film 25a and a conductive film 25b thereon. The conductive layer 25 is also provided with a slit that overlaps with the slit 20, and is divided by the slit. That is, a pair of conductive layers 25 is provided on the insulating layer 41 so as to sandwich one slit 20 therebetween. Furthermore, as shown in FIG. 5 , island-shaped conductive layers 25 are arranged at equal intervals along the extension direction of the slit 20 (Y direction).

[0121] Here, a polycrystalline conductive film is used for one of the conductive films 24b and 25b, and an amorphous conductive film is used for the other. Here, an amorphous conductive film is used for the conductive film 24b, and a polycrystalline conductive film is used for the conductive film 25b. Alternatively, an amorphous conductive film may be used for the conductive film 25b, and a polycrystalline conductive film may be used for the conductive film 24b.

[0122] The semiconductor layer 21, the insulating layer 22, and the conductive layer 23 have portions located inside the slit 20. The semiconductor layer 21 and the insulating layer 22 are provided along the side surface of the insulating layer 41 and the top surface of the conductive layer 24 inside the slit 20. The conductive layer 23 is provided so as to fill the recessed portion of the insulating layer 22.

[0123] The semiconductor layer 21 has portions in contact with the upper surface and side surfaces of the conductive layer 25, portions in contact with the side surfaces of the insulating layer 41 within the slits 20, and portions in contact with the upper surface of the conductive film 24b. It is preferable to use a conductive metal oxide similar to the conductive film 24b described above for one of the conductive films 25a and 25b of the conductive layer 25. It is also preferable to use a low-resistance metal material for the other. By stacking a conductive film with low contact resistance with the semiconductor layer 21 and a conductive film with low wiring resistance, it is possible to reduce both the contact resistance and the wiring resistance, thereby further reducing the wiring load.

[0124] Because the semiconductor layer 21 and the insulating layer 22 are formed along the inner walls of the slits 20 in the insulating layer 41, the thickness of these portions may be thin depending on the film formation method. For example, in film formation methods such as sputtering or plasma CVD (chemical vapor deposition), films formed on surfaces inclined or perpendicular to the substrate surface tend to be thinner than films formed on surfaces parallel to the substrate surface. On the other hand, film formation methods such as atomic layer deposition (ALD) or thermal CVD can form films of uniform thickness regardless of the angle of the surface on which they are formed. For example, when the angle of the sidewalls of the slits 20 in the insulating layer 41 relative to the substrate surface is 75 degrees or more, 80 degrees or more, or 85 degrees or more, it is preferable to form the semiconductor layer 21 and the insulating layer 22 using the ALD method.

[0125] It is preferable that the conductive film 24b and the conductive film 25b contain one or more of the same metal elements as the metal elements contained in the semiconductor layer 21, because this further reduces contact resistance. Specifically, it is preferable that the conductive film 25b and the semiconductor layer 21 contain the same one or more elements selected from In, Sn, and Zn. It is particularly preferable that the conductive film 25b and the semiconductor layer 21 contain In.

[0126] In the transistor 10, the source electrode and the drain electrode are located at different heights, and therefore, a current flows in the height direction through the semiconductor. That is, it can be said that the channel length direction has a component in the height direction (vertical direction). Therefore, the transistor of one embodiment of the present invention can also be called a VFET, a vertical transistor, a vertical channel transistor, or the like. Since the transistor 10 can have two or more of the source electrode, the semiconductor, and the drain electrode stacked, the occupied area can be significantly reduced compared to a so-called planar transistor (which can also be called a lateral transistor, LFET (lateral FET), or the like) in which the semiconductor is arranged on a plane.

[0127] Furthermore, the channel length of the transistor 10 can be precisely controlled by the thickness of the insulating layer 41, which functions as a spacer. This significantly reduces the variation in channel length compared to planar transistors. Furthermore, by thinning the insulating layer 41, transistors with extremely short channel lengths can be fabricated. For example, transistors with channel lengths of 2 μm or less, 1 μm or less, 500 nm or less, 300 nm or less, 200 nm or less, 100 nm or less, 50 nm or less, 30 nm or less, or 20 nm or less, and 5 nm or more, 7 nm or more, or 10 nm or more, can be fabricated. Therefore, transistors with extremely short channel lengths that could not be achieved using mass-production exposure equipment can be realized. Furthermore, transistors with channel lengths of less than 10 nm can be fabricated without using the extremely expensive exposure equipment used in cutting-edge LSI technology.

[0128] Although various semiconductor materials can be used for the semiconductor layer 21, it is particularly preferable to use an oxide semiconductor containing a metal oxide. By using an oxide semiconductor formed under appropriate conditions, a transistor having both a high on-state current and an extremely low off-state current can be realized at low cost. Unless otherwise specified, a configuration example in which an oxide semiconductor is used for the semiconductor layer 21 will be described below.

[0129] 5 shows an example in which the upper surface of the region of the conductive film 24b that overlaps with the slit 20 has a rounded recess (concave surface). As a result, inside the slit 20, the bottoms of the semiconductor layer 21, the insulating layer 22, and the conductive layer 23 are each provided along the concave surface of the conductive film 24b, and have a rounded protrusion (convex surface). This makes it possible to realize a configuration in which the electric field is less likely to concentrate, similar to the conductive layer 51 of the capacitance element 30. As a result, a transistor with low leakage current and high reliability can be realized.

[0130] An insulating layer 44 that functions as an interlayer insulating layer is provided to cover the insulating layer 22 and the conductive layer 23. Furthermore, a conductive layer 26 that functions as a bit line is provided on the insulating layer 44. A plug 27 that connects the conductive layer 25 and the conductive layer 26 is provided in an opening provided in the insulating layer 44, the insulating layer 22, and the semiconductor layer 21. This allows the conductive layer 26 to connect the multiple conductive layers 25 arranged in the X direction with the slit 20 between them.

[0131] Here, an example is shown in which the plug 27 penetrates the conductive film 25b and is provided so as to be in contact with the conductive film 25a. This configuration in which the low-resistance conductive film 25a and the plug 27 are in contact with each other is preferable because it reduces the contact resistance between them and reduces the load on the wiring. It should be noted that the bottom surface of the plug 27 may also be configured to be in contact with the conductive film 25b or the semiconductor layer 21.

[0132] Here, since the conductive layer 51 extends in the Y direction, the conductive layer 55 does not necessarily have to be located over the entire bottom surface of the conductive layer 51. Figures 9A and 9B show a configuration in which the conductive layer 55 extending in the X direction is disposed only near the ends of the slits 40 and is connected to the multiple conductive layers 51 provided in each slit 40. Figures 9A and 9B are cross-sectional views corresponding to the cut lines A-B and E-F in Figure 4A, respectively. In this case, the conductive layer 51 functions as a wiring extending in the Y direction, and the conductive layer 55 functions as a wiring extending in the X direction. For all memory cells 15, the conductive layer 51 is connected to the conductive layer 55 near the ends of the slits 40.

[0133] An insulating layer 35 is provided on insulating layer 11, and an insulating layer 46 is provided on insulating layer 35. Slit 40 is provided so as to reach insulating layer 35. A recess is formed in insulating layer 35 so as to overlap slit 40. Conductive layer 51 contacts the upper surface of insulating layer 35 at the bottom of slit 40.

[0134] 9B , the conductive layer 55 is provided at the end (end in the Y direction) of the slit 40. The conductive layer 55 is located between the insulating layer 35 and the insulating layer 46. A portion of the conductive layer 55 overlaps with the slit 40. Therefore, within the slit 40, the conductive layer 51 and the conductive layer 55 are in contact with each other.

[0135] 9A and 9B show an example in which the insulating layer 41 has a laminated structure in which an insulating layer 41a, an insulating layer 41b, and an insulating layer 41c are laminated in this order from the insulating layer 52 side.

[0136] The semiconductor layer 21 is provided in contact with the inner wall of the slit 20 of the insulating layer 41. It is preferable to use an oxide insulating film for the insulating layer 41b. In particular, it is preferable to use an oxide insulating film that releases oxygen when heated. Furthermore, it is preferable to have a structure in which the insulating layer 41b is sandwiched between insulating layers 41a and 41c that have a barrier property against oxygen. This makes it possible to confine oxygen contained in the insulating layer 41b in a region surrounded by the insulating layers 41a, 41c, and the semiconductor layer 21. Furthermore, it is possible to prevent oxygen in the insulating layer 41b from being desorbed and reduced during the process. This makes it possible to more efficiently supply oxygen to the semiconductor layer 21.

[0137] The portion of the semiconductor layer 21 that is in contact with the insulating layer 41b is a region in which oxygen vacancies are reduced and can be said to be an i-type region. On the other hand, the portion that is not in contact with the insulating layer 41b is preferably an n-type region containing many carriers. That is, the portion of the semiconductor layer 21 that is in contact with the insulating layer 41b can be called a channel formation region, and the region outside that can be called a low-resistance region (also called a source region or a drain region).

[0138] The insulating layer 41b is preferably a film containing as little hydrogen as possible because it is in contact with the semiconductor layer 21. Carriers are generated when oxygen vacancies in the semiconductor layer 21 combine with hydrogen, which may affect the threshold voltage of the transistor 10, for example. Therefore, an insulating film other than an oxide insulating film through which hydrogen is less likely to diffuse may be used as the insulating layer 41b. For example, a single layer of an insulating film having a barrier property against hydrogen and oxygen may be used as the insulating layer 41.

[0139] The insulating layer 41b can be used as an interlayer insulating film. For example, it is preferably formed by a film formation method such as a sputtering method or a plasma CVD method. In particular, when a sputtering method is used, hydrogen is not used as a film formation gas, and therefore a film with an extremely low hydrogen content can be obtained. Therefore, the supply of hydrogen to the semiconductor layer 21 can be suppressed, and the electrical characteristics of the transistor 10 can be stabilized.

[0140] The insulating layer 41b is preferably formed using an oxide insulating film because it is in contact with a channel formation region of the semiconductor layer 21. In particular, it is preferably formed using an oxide insulating film that releases oxygen when heated. An oxide insulating film that can be used for a gate insulating layer, which will be described later, can be used as the insulating layer 41b.

[0141] Furthermore, since the insulating layer 41b functions as an interlayer insulating layer, it is preferable to use a film formation method that allows film formation at a high film formation rate compared to other insulating layers. For example, the insulating layer 41 can be formed by depositing TEOS (Tetra-Ethyl-Ortho-Silicate, chemical formula: Si(OC)) by plasma CVD. ２ H ５ ) ４ ) may be used as an insulating film, which can improve productivity.

[0142] The insulating layers 41 a and 41 c are preferably made of films that do not easily diffuse hydrogen. By sandwiching the insulating layer 41 b between the insulating layers 41 a and 41 c, which do not easily diffuse hydrogen, it is possible to prevent external hydrogen from being mixed into the insulating layer 41 b that contacts the semiconductor layer 21.

[0143] The insulating layer 41 a and the insulating layer 41 c can be made of, for example, one or more of silicon nitride, silicon nitride oxide, silicon oxynitride, aluminum oxide, aluminum oxynitride, aluminum nitride, hafnium oxide, and hafnium aluminate. In particular, silicon nitride and silicon nitride oxide are suitable for use as the insulating layer 41 a and the insulating layer 41 c because they emit little impurities (for example, water and hydrogen) and are less permeable to oxygen and hydrogen.

[0144] Furthermore, an insulating layer 32 is provided within the slit 40 between the side surface of the insulating layer 46 and the conductive layer 51. The insulating layer 32 functions as a barrier film that prevents the diffusion of impurities such as hydrogen. For example, when a ferroelectric is used for the insulating layer 52 of the capacitance element 30, the inclusion of impurities (typically hydrogen) may result in a decrease in crystallinity and a decrease in ferroelectricity. Therefore, by providing the insulating layer 32, which functions as a barrier film, between the insulating layer 46, which functions as an interlayer insulating film, and the capacitance element 30, a ferroelectric capacitor exhibiting good electrical characteristics can be realized.

[0145] As a barrier film for preventing the diffusion of hydrogen, etc., a film in which hydrogen is less likely to diffuse than a silicon oxide film (having barrier properties against hydrogen), such as a silicon nitride film, a silicon nitride oxide film, an aluminum oxide film, a magnesium oxide film, a hafnium oxide film, or a gallium oxide film, can be used. In particular, it is preferable to use a silicon nitride film or a silicon nitride oxide film.

[0146] Furthermore, the insulating layer 32 is preferably formed by stacking an insulating film functioning as a barrier film described above and an insulating film having a function of capturing or fixing hydrogen closer to the insulating layer 52 than the insulating film. This allows hydrogen to be captured or fixed by the insulating film due to heat or the like applied during the manufacturing process of the transistor 10 or the memory cell 15, thereby reducing the concentration of hydrogen contained in the insulating layer 52. Therefore, a highly reliable memory cell 15 with favorable electrical characteristics can be realized. As the insulating film that captures or fixes hydrogen, a hafnium oxide film, a hafnium silicate film, an aluminum oxide film, a hafnium zirconium oxide film, or the like is preferably used.

[0147] Here, a material that functions as a ferroelectric and that can be used for the insulating layer 52 of the capacitance element 30 will be described.

[0148] Ferroelectric materials include oxides such as hafnium oxide, zirconium oxide, and hafnium zirconium oxide. It is also preferable to use materials in which a Group 3 (IIIa) element is added to these oxides. For example, it is preferable to include one or more of scandium, yttrium, and lanthanoid elements. Yttrium, lanthanum, or scandium are particularly preferable because they are relatively easy to handle and have high compatibility with semiconductor manufacturing processes. Adding such elements not only stabilizes ferroelectricity but also suppresses degradation of characteristics during repeated rewriting, improving reliability. It also improves the breakdown voltage of the insulating layer 52. For example, these elements are preferably added at a ratio of 0.5 at% to 10 at%. Other additive elements include silicon, aluminum, gadolinium, and scandium. The insulating layer 52 can be made of not only ferroelectric materials but also antiferroelectric materials.

[0149] Oxides containing either or both of hafnium and zirconium easily exhibit ferroelectricity even in extremely thin films prepared using thin film deposition methods such as sputtering and ALD, and therefore have high compatibility with semiconductor manufacturing processes, enabling reduction in manufacturing costs.

[0150] Furthermore, the insulating layer 52 may be made of piezoelectric ceramics having a perovskite structure, such as barium titanate, lead titanate, strontium titanate, barium strontium titanate (BST), lead zirconate titanate (PZT), strontium bismuth tantalate (SBT), or bismuth ferrite (BFO).

[0151] Alternatively, the insulating layer 52 may be made of an organic ferroelectric material such as polyvinylidene fluoride (PVDF) or a copolymer of vinylidene fluoride (VDF) and trifluoroethylene (TrFE).

[0152] The ferroelectric material may be, for example, a mixture or compound of multiple materials selected from the materials listed above. Alternatively, the insulating layer 52 may have a layered structure made of multiple materials selected from the materials listed above.

[0153] Among these, hafnium oxide, a material containing hafnium oxide and zirconium oxide (HZO), and a material containing yttrium in addition to HZO (HZYO) are preferred as materials exhibiting ferroelectricity because they exhibit ferroelectricity even in thin films of only a few nanometers. By using a film containing hafnium oxide, HZO, or HZYO, the film thickness of insulating layer 52 can be set to 3 nm or more and 100 nm or less, preferably 3 nm or more and 50 nm or less, more preferably 3 nm or more and 20 nm or less, and even more preferably 4 nm or more and 10 nm or less.

[0154] Furthermore, hafnium zirconium oxide (HfZrO Ｘ When X (where X is a real number greater than 0) is used, it is preferable to form the film by the ALD method, particularly the thermal ALD method. It is also preferable to use the ALD method (including the thermal ALD method) in which reactivity is enhanced by using plasma (PEALD method: Plasma Enhanced ALD).

[0155] Furthermore, when using the thermal ALD method, a material containing an organometallic compound can be used as a precursor. For example, when using hafnium zirconium oxide, an organometallic compound such as tetrakis(ethylmethylamido)hafnium (TEMAHf) can be used as a precursor containing hafnium, and tetrakis(ethylmethylamido)zirconium (TEMAZr) can be used as a precursor containing zirconium. Alternatively, a material that does not contain hydrocarbons (also called hydrocarbons) can be used. For example, a chlorine-based material can be used as a precursor that does not contain hydrocarbons. Note that when hafnium zirconium oxide is used, the precursor can be HfCl. ４ , ZrCl ４ Chlorine-based precursors such as the following can be used.

[0156] When an oxide such as hafnium oxide, zirconium oxide, or hafnium zirconium oxide is used for the insulating layer 52, the remanent polarization may be increased by adding an appropriate amount of carbon. In this case, it is preferable to add these elements in a ratio of 0.5 at % to 10 at %, for example.

[0157] When hafnium zirconium oxide is used for the insulating layer 52, it is preferable to form the film using a thermal ALD method or an ALD method using plasma so that the hafnium and zirconium have a composition ratio of 1:1.

[0158] The oxidizing agent used in the thermal ALD method or the plasma-based ALD method is H ２ O or O ３ However, the oxidizing agent is not limited to this, and O ２ , O ３ , N ２ O, NO ２ , H ２ O, H ２ O ２ In particular, in order to reduce the hydrogen concentration and nitrogen concentration in the film, O as an oxidizing agent can be used. ２ or O ３ It is preferable to use O ３ It is more preferable to use

[0159] The film used for the insulating layer 52 preferably has a low hydrogen concentration in the film. This prevents hydrogen from diffusing from the insulating layer 52 to the semiconductor layer 21, which can prevent the carrier concentration in the semiconductor layer 21 from increasing. Specifically, the hydrogen concentration in the film is 5×10 ２０ atoms / cm ３ Preferably, 1×10 ２０ atoms / cm ３ The following is more preferred:

[0160] The crystalline structure of the film used for the insulating layer 52 is not particularly limited as long as it is a crystal structure that does not have centrosymmetrical structure and has polarity. For example, a crystal system other than a cubic system may be used. The film used for the insulating layer 52 may have a single crystal structure, a polycrystalline structure, or a composite structure having an amorphous structure and a crystalline structure.

[0161] The conductive layer 51 and the conductive film 24a, which are in contact with or near the insulating layer 52, are preferably made of a conductive material having a function of absorbing oxygen. This allows oxygen to be absorbed from the insulating layer 52, thereby increasing the oxygen vacancy concentration in the insulating layer 52. This increases the remnant polarization of the insulating layer 52. As the conductive material having a function of absorbing oxygen, it is preferable to use a metal or an alloy. In particular, it is preferable to use tungsten, molybdenum, titanium, tantalum, or the like. Furthermore, tungsten is particularly preferable because it easily increases the remnant polarization of the insulating layer 52 from the viewpoint of stress.

[0162] It is also preferable to use a conductive material that does not easily diffuse oxygen for the conductive layer 51 and the conductive film 24a. This improves the breakdown voltage of the insulating layer 52 and improves the rewrite durability of the ferroelectric capacitor. In particular, it is preferable to use a metal nitride such as titanium nitride or tantalum nitride.

[0163] The conductive film 24a may have a stacked structure. In this case, it is preferable to use a low-resistance conductive material on the side not in contact with the insulating layer 52. For example, a metal or alloy containing one or more selected from aluminum, chromium, copper, silver, gold, platinum, zinc, tantalum, nickel, titanium, iron, cobalt, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, lanthanum, etc. can be used. In particular, using a high-melting-point material such as tungsten, molybdenum, tantalum, ruthenium, or hafnium is preferable because it allows for a higher temperature for subsequent heat treatment. In addition to the above low-resistance conductive materials, oxide materials such as indium tin oxide, indium tin oxide with added silicon, indium zinc oxide, and indium gallium zinc oxide may also be used.

[0164] Although the above example shows that the slits 20 and 40 extend in the same direction (here, the Y direction), the slits 20 and 40 may extend in different directions (i.e., extend in directions that intersect with each other). Figure 10 shows an example where the slit 40 extends in the Y direction.

[0165] With this configuration, even if the minimum feature size shrinks due to improved performance of the exposure apparatus, the capacitance of the capacitance element 30 can be kept constant, eliminating the need to increase the depth of the slit 40 to maintain the capacitance, thereby preventing a decrease in yield. This is because the capacitance of the capacitance element 30 depends on the width in the X direction of the portion of the conductive film 24a located within the slit 40, and this width is limited by the width of the slit 20. Since the width of the slit 20 is limited by the width (thickness) in the X direction of the semiconductor layer 21, insulating layer 22, and conductive layer 23 provided inside the slit 20, the width of the slit 20 is maintained at a predetermined size even if the minimum feature size shrinks, and thereby the capacitance of the capacitance element 30 can also be maintained.

[0166] Here, the semiconductor device 50 preferably has a layer in which the memory cells 15 are provided and a layer in which the functional circuits are provided stacked. The functional circuits may include, for example, a driver circuit for driving the memory cells 15, an arithmetic circuit, a power supply circuit, etc. The driver circuit may include, for example, one or more of a row decoder, a column decoder, a row driver, a column driver, an input circuit, an output circuit, a sense amplifier, etc. This not only reduces the footprint of the semiconductor chip including the semiconductor device 50, but also shortens the wiring length compared to when the functional circuits and the memory cells 15 are arranged side by side, thereby achieving high-speed operation and low power consumption.

[0167] 11 shows an example in which a layer 80 in which a memory cell 15 is provided and a transistor 90 constituting a functional circuit are arranged below the layer 80. In this example, one of a source electrode and a drain electrode of the transistor 90 is connected to a conductive layer 26 that functions as a bit line.

[0168] The transistor 90 is a transistor in which a channel is formed in a part of a substrate 91, which is a single-crystal semiconductor substrate. The substrate 91 can typically be made of single-crystal silicon. The substrate 91 can be made of a semiconductor made of a single element such as germanium, or a compound semiconductor made of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, gallium oxide, or gallium nitride. Alternatively, the substrate 91 can be a semiconductor substrate having an insulator region therein, such as an SOI (Silicon On Insulator) substrate.

[0169] The transistor 90 is provided on a substrate 91 and includes a conductive layer 94 functioning as a gate, an insulating layer 93 functioning as a gate insulating layer, a semiconductor region 92 formed of part of the substrate 91, and low-resistance regions 95a and 95b functioning as source and drain regions. The transistor 90 can be either a p-channel type or an n-channel type. An element isolation layer 98 is provided in the substrate 91 between two adjacent transistors 90.

[0170] The transistor 90 has a semiconductor region 92 in which a channel is formed that has a convex shape (fin shape). Although not shown in Fig. 11, a conductive layer 94 is provided to cover the side and top surfaces of the semiconductor region 92 in the Y direction via an insulating layer 93. Such a transistor 90 is also called a FIN-type transistor.

[0171] An insulating layer 96 is provided covering the transistor 90, an insulating layer 86 is provided on the insulating layer 96, and an insulating layer 87 is provided on the insulating layer 86. A conductive layer 81 is provided so as to be embedded in the insulating layer 87. An insulating layer 88 is provided covering the conductive layer 81 and the insulating layer 87, an insulating layer 45 is provided on the insulating layer 88, and an insulating layer 11 is provided on the insulating layer 45. A plug 82 is provided inside an opening provided in the insulating layer 96 and the insulating layer 86, and the plug 82 connects the conductive layer 81 to the low-resistance region 95b. A conductive layer 84 is provided on the insulating layer 45, and a plug 83 is provided inside an opening provided in the insulating layer 45 and the insulating layer 88, connecting the conductive layer 84 to the conductive layer 81. The conductive layer 84 and the conductive layer 26 are connected via a plug 85 provided inside an opening provided in each insulating layer between them. This connects one of the source and drain of the transistor 90 to the conductive layer 26.

[0172] Note that although an example of providing a conductive layer 81 as a wiring layer has been shown here, a structure in which interlayer insulating layers and wiring layers are alternately stacked (also referred to as a multilayer wiring layer) can be used between the layer in which the transistor 90 is provided and the layer 80 in which the memory cell 15 is provided.

[0173] Here, in a region outside the memory cell array having memory cells 15 or outside the functional circuit including transistor 90, each insulating layer constituting layer 80 is etched, and insulating layer 47 is provided covering the top and side surfaces of the insulating layers. Insulating layer 47 contacts the top surface of insulating layer 45. This allows all memory cells 15 included in layer 80 to be surrounded by insulating layer 47 and insulating layer 45.

[0174] The above-described films having a barrier property against hydrogen can be used for the insulating layers 45 and 47. In particular, a silicon nitride film or a silicon nitride oxide film is preferably used.

[0175] Furthermore, the insulating layer 45 and the insulating layer 47 preferably have a stacked structure in which an insulating film functioning as the above-described barrier film and an insulating film having a function of capturing or fixing hydrogen are stacked inside the insulating film (on the transistor 10 side). For example, a hafnium oxide film, a hafnium silicate film, an aluminum oxide film, a hafnium zirconium oxide film, or the like is preferably used.

[0176] This suppresses the diffusion of hydrogen from the outside into the region surrounded by the insulating layers 45 and 47, and further reduces the concentration of hydrogen contained therein, thereby effectively reducing hydrogen that can diffuse into the semiconductor layer 21 of the transistor 10, thereby achieving a highly reliable transistor 10.

[0177] 12 shows an example in which layers 80 each having a memory cell 15 are stacked. In FIG. 12, an example in which three layers 80 (layers 80[1] to 80[3] from the substrate 91 side) are stacked is shown, but two layers or four or more layers may be stacked.

[0178] The plug 85 connects the conductive layer 84 to the conductive layer 26 of the layer 80[1]. The plug 89 connects the conductive layers 26 of the two layers 80 to each other. As a result, the three conductive layers 26 of the layers 80[1] to 80[3] are connected to one of the source and drain of the transistor 90.

[0179] The insulating layer 47 is provided so as to surround the layers 80[1] to 80[3]. However, the present invention is not limited to this, and a configuration in which an insulating layer 47 is provided for each layer 80 may be adopted.

[0180] Although the configuration shown here is one in which the layer 80 is stacked directly on the substrate 91 on which the transistor 90 is provided, the present invention is not limited to this. For example, the substrate 91 on which the transistor 90 is provided and the substrate on which the memory cell 15 is provided may be bonded together. For example, the two substrates may be bonded together by direct bonding (hybrid bonding) using a direct bonding technique, such as Cu-Cu bonding. Alternatively, a method may be used in which two or more layers are bonded together with their insulating films, and then through electrodes are formed to connect the electrodes provided on each layer. In particular, using a method using direct bonding or through electrodes allows the pitch of the connection electrodes to be extremely narrow, making it possible to arrange a large number of connection electrodes at a high density, which is preferable because it increases the amount of data transmitted between layers.

[0181] When bonding two layers, any of CoC (chip-on-chip) bonding, CoW (chip-on-wafer) bonding, and WoW (wafer-on-wafer) bonding may be used. WoW bonding is superior in productivity because wafers are bonded together, but since all chips, including both good and bad, are bonded together, the yield may be reduced. On the other hand, CoW bonding, which bonds a chip to a wafer, and CoC bonding, which bonds chips together, are inferior to WoW bonding in terms of productivity, but the yield is significantly improved because good chips can be bonded together. Furthermore, CoC bonding is inferior in productivity to the other two, but is highly versatile because it can bond two layers even when the sizes of the two layers are significantly different.

[0182] A wiring layer such as an interposer may be provided between the two layers, which eliminates the need to align the positions of bonding electrodes between two adjacent layers, increasing the degree of freedom in designing each layer and enabling the realization of a semiconductor device with higher performance.

[0183] [Regarding Components] <Substrate> Substrates on which transistors are formed can be, for example, insulating substrates, semiconductor substrates, or conductive substrates. Examples of insulating substrates include glass substrates, quartz substrates, sapphire substrates, stabilized zirconia substrates (e.g., yttria-stabilized zirconia substrates), and resin substrates. Examples of semiconductor substrates include semiconductor substrates made of silicon or germanium, or compound semiconductor substrates made of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, gallium oxide, and gallium nitride. Examples of semiconductor substrates include those having an insulating region within the semiconductor substrate, such as an SOI substrate. Examples of conductive substrates include graphite substrates, metal substrates, alloy substrates, and conductive resin substrates. Substrates containing metal nitrides and substrates containing metal oxides can also be used. Examples of substrates include an insulating substrate with a conductive layer or semiconductor layer, a semiconductor substrate with a conductive layer or insulating layer, and a conductive substrate with a semiconductor layer or insulating layer. Alternatively, a substrate provided with elements may be used, such as a capacitor, a resistor, a switch (including a transistor), a light-emitting element, a memory element, or the like.

[0184] <Semiconductor Layer> The semiconductor layer 21 preferably contains a metal oxide (oxide semiconductor).

[0185] The semiconductor layer 21 is preferably made of indium oxide.

[0186] Examples of metal oxides that can be used for the semiconductor layer 21 include Ga oxide and Zn oxide. The metal oxide preferably contains at least In or Zn. The metal oxide preferably contains two or three elements selected from In, element M, and Zn. The element M is a metal element or semimetal element with a high bond energy with oxygen, such as a metal element or semimetal element with a bond energy with oxygen higher than that of indium. Specific examples of the element M include Al, Ga, Sn, Y, Ti, V, Cr, Mn, Fe, Co, Ni, Zr, Mo, Hf, Ta, W, La, Ce, Nd, Mg, Ca, Sr, Ba, B, Si, Ge, and Sb. The element M contained in the metal oxide is preferably one or more of the above elements, and is particularly preferably one or more selected from Al, Ga, Y, and Sn, with Ga being more preferred. Hereinafter, a metal oxide having In, M, and Zn may be referred to as an In-M-Zn oxide. In this specification and the like, metal elements and metalloid elements may be collectively referred to as "metal elements," and the "metal elements" described in this specification and the like may include metalloid elements.

[0187] When the metal oxide is an In-M-Zn oxide, the atomic ratio of In in the In-M-Zn oxide is preferably equal to or greater than the atomic ratio of M. For example, the atomic ratios of metal elements in such an In-M-Zn oxide may be In:M:Zn = 1:1:1, In:M:Zn = 1:1:1.2, In:M:Zn = 2:1:3, In:M:Zn = 3:1:2, In:M:Zn = 4:2:3, In:M:Zn = 4:2:4.1, In:M:Zn = 5:1:3, In:M:Zn = 5:1:6, In:M:Zn = 5:1:7, In:M:Zn = 5:1:8, In:M:Zn = 6:1:6, In:M:Zn = 5:2:5, or compositions in the vicinity thereof. Note that the term "composition in the vicinity" refers to a range of ±30% of the desired atomic ratio. By increasing the atomic ratio of indium in the metal oxide, the on-state current, field-effect mobility, and the like of a transistor can be increased.

[0188] Furthermore, the atomic ratio of In in the In-M-Zn oxide may be less than the atomic ratio of M. For example, the atomic ratio of metal elements in such an In-M-Zn oxide may be In:M:Zn=1:3:2, In:M:Zn=1:3:3, In:M:Zn=1:3:4, or a composition close to these. By increasing the atomic ratio of M in the metal oxide, the generation of oxygen vacancies can be suppressed.

[0189] The semiconductor layer 21 can be made of, for example, In oxide, In—Zn oxide, In—Ga oxide, In—Sn oxide, In—Ti oxide, In—Ga—Al oxide, In—Ga—Sn oxide, In—Ga—Zn oxide, In—Sn—Zn oxide, In—Al—Zn oxide, In—Ti—Zn oxide, In—Ga—Sn—Zn oxide, In—Ga—Al—Zn oxide, or the like. Ga—Zn oxide may also be used. A material that does not contain Zn, such as indium oxide, is preferred because it enhances compatibility with the LSI manufacturing process. On the other hand, a material that contains Zn is preferred because it facilitates high crystallinity.

[0190] Note that the metal oxide may contain one or more metal elements with higher period numbers in the periodic table instead of or in addition to indium. The greater the overlap of the orbitals of metal elements, the greater the carrier conduction in the metal oxide tends to be. Therefore, including a metal element with a higher period number may improve the field-effect mobility of a transistor. Examples of metal elements with higher period numbers include metal elements belonging to the fifth period and the sixth period. Specific examples of such metal elements include Y, Zr, Ag, Cd, Sn, Sb, Ba, Pb, Bi, La, Ce, Pr, Nd, Pm, Sm, and Eu. Note that La, Ce, Pr, Nd, Pm, Sm, and Eu are called light rare earth elements.

[0191] The metal oxide may also contain one or more nonmetallic elements, which may increase the field-effect mobility of the transistor. Examples of nonmetallic elements include carbon, nitrogen, phosphorus, sulfur, selenium, fluorine, chlorine, bromine, and hydrogen.

[0192] The metal oxide can be preferably formed by sputtering or atomic layer deposition (ALD). In particular, it is preferable to form the metal oxide film by the ALD method, which has excellent coating properties. When forming the metal oxide by the sputtering method, the composition of the metal oxide film may differ from that of the target. In particular, the zinc content in the metal oxide film may decrease to about 50% of that of the target.

[0193] In this specification, the content of a metal element in a metal oxide refers to the ratio of the number of atoms of that element to the total number of atoms of the metal element contained in the metal oxide. For example, if a metal oxide contains metal elements X, Y, and Z, and the number of atoms of each of metal elements X, Y, and Z contained in the metal oxide is A, then Ｘ , A Ｙ , A Ｚ When the content of the metal element X is Ｘ / (A Ｘ +A Ｙ +A Ｚ ) In addition, the ratio of the number of atoms of the metal element X, the metal element Y, and the metal element Z in the metal oxide (atomic number ratio) can be expressed as follows: Ｘ : B Ｙ : B Ｚ When the content of the metal element X is expressed as B Ｘ / (B Ｘ +B Ｙ +B Ｚ ) can be shown as

[0194] For example, in the case of a metal oxide containing In, a transistor with a large on-current can be realized by increasing the In content.

[0195] By using a metal oxide that does not contain Ga or has a low Ga content in the semiconductor layer 21, a transistor with high reliability against positive bias application can be obtained. That is, a transistor with a small amount of threshold voltage fluctuation in a PBTS (Positive Bias Temperature Stress) test can be obtained. Furthermore, when using a metal oxide that contains Ga, it is preferable to make the Ga content lower than the In content. This makes it possible to realize a transistor with high mobility and high reliability.

[0196] On the other hand, by increasing the Ga content, a transistor with high reliability against light can be obtained. That is, a transistor with a small amount of variation in threshold voltage in a Negative Bias Temperature Illumination Stress (NBTIS) test can be obtained. Specifically, a metal oxide in which the atomic ratio of Ga is equal to or greater than the atomic ratio of In has a larger band gap, and the amount of variation in threshold voltage of the transistor in the NBTIS test can be reduced.

[0197] Furthermore, by increasing the zinc content, the metal oxide becomes highly crystalline, which can suppress the diffusion of impurities in the metal oxide, thereby suppressing fluctuations in the electrical characteristics of the transistor and improving its reliability.

[0198] The semiconductor layer 21 may have a stacked structure including two or more metal oxide layers. The two or more metal oxide layers included in the semiconductor layer 21 may have the same or substantially the same composition. By using a stacked structure of metal oxide layers with the same composition, for example, the same sputtering target can be used for formation, thereby reducing manufacturing costs. A stacked structure in which two or more oxide semiconductor layers with different compositions are stacked may also be used. Furthermore, by using the ALD method, it is possible to form a metal oxide layer whose composition varies continuously in the thickness direction. This not only broadens the range of design options compared to using a film with a fixed composition, but also prevents the generation of interface states between two layers with different compositions, thereby improving electrical characteristics and reliability. Furthermore, a metal oxide layer having a stacked structure may be formed using both the sputtering method and the ALD method.

[0199] When the semiconductor layer 21 has a two-layer structure, it is preferable to use a material with higher mobility (higher conductivity) in the second layer, i.e., the side closer to the gate electrode, than in the first layer. This allows for a normally-off transistor with a large on-current. This makes it possible to achieve both low power consumption and high performance. Alternatively, a material with higher mobility than in the second layer may be used in the first layer, i.e., the side in contact with the source electrode and drain electrode. This reduces the contact resistance between the semiconductor layer 21 and the source electrode or drain electrode, thereby reducing parasitic resistance and enabling a transistor with a large on-current.

[0200] Furthermore, when the semiconductor layer 21 has a three-layer structure, it is preferable to use a material for the second layer that has a higher mobility than the first and third layers, thereby realizing a transistor with a high on-current and high reliability.

[0201] The difference in the mobility and conductivity described above can be expressed, for example, by the indium content. In addition, whether or not an element other than indium that contributes to improving conductivity is contained, or the content of that element, also affects the mobility and conductivity. Examples of high-mobility materials include In:Ga:Zn = 4:2:3 [atomic ratio] and materials in the vicinity thereof, In:Zn = 1:1 [atomic ratio] and materials in the vicinity thereof, In:Zn = 2:1 [atomic ratio] and materials in the vicinity thereof, In:Zn = 4:1 [atomic ratio] and materials in the vicinity thereof, and In:Sn:Zn = 40:X:10 [atomic ratio] (X is 0.1 or more and 5 or less, typically X = 1) and materials in the vicinity thereof. On the other hand, examples of materials having lower mobility or conductivity than the above-mentioned materials include In:Ga:Zn=1:3:2 [atomic ratio] and materials in the vicinity thereof, In:Ga:Zn=1:3:4 [atomic ratio] and materials in the vicinity thereof, In:Ga:Zn=2:2:1 [atomic ratio] and materials in the vicinity thereof, In:Ga:Zn=1:1:1 [atomic ratio] and materials in the vicinity thereof, and In:Ga:Zn=1:1:2 [atomic ratio] and materials in the vicinity thereof.

[0202] It is preferable to use a crystalline metal oxide layer for the semiconductor layer 21. For example, a metal oxide layer having a c-axis aligned crystal (CAAC) structure, a polycrystalline structure, a nanocrystalline (nc) structure, or the like can be used. By using a crystalline metal oxide layer for the semiconductor layer 21, the defect level density in the semiconductor layer 21 can be reduced, and a highly reliable semiconductor device can be realized.

[0203] The higher the crystallinity of the metal oxide layer used in the semiconductor layer 21, the more the density of defect states in the semiconductor layer 21 can be reduced. On the other hand, by using a metal oxide layer with low crystallinity, a transistor capable of passing a large current can be realized.

[0204] A transistor using an oxide semiconductor (hereinafter referred to as an OS transistor) has significantly higher field-effect mobility than a transistor using amorphous silicon. Furthermore, an OS transistor has significantly lower source-drain leakage current in an off state (hereinafter also referred to as an off-state current) and can hold charge accumulated in a capacitor connected in series with the transistor for a long period of time. Furthermore, the use of an OS transistor can reduce the power consumption of a semiconductor device.

[0205] The semiconductor device according to one embodiment of the present invention can be applied to, for example, a processor, a memory device, or various ICs. The transistor according to one embodiment of the present invention is capable of passing a large current and has an extremely low off-state current, and therefore, high-speed operation of a circuit and low power consumption can be achieved at the same time.

[0206] A semiconductor device according to one embodiment of the present invention can also be applied to a display device, for example. To increase the emission luminance of a light-emitting device included in a pixel circuit of a display device, it is necessary to increase the amount of current flowing through the light-emitting device. To achieve this, it is necessary to increase the source-drain voltage of a driving transistor included in the pixel circuit. Since an OS transistor has a higher withstand voltage between the source and drain than a transistor using silicon (hereinafter referred to as a Si transistor), a high voltage can be applied between the source and drain of the OS transistor. Therefore, by using an OS transistor as the driving transistor included in the pixel circuit, it is possible to increase the amount of current flowing through the light-emitting device and increase the emission luminance of the light-emitting device.

[0207] When a transistor operates in the saturation region, an OS transistor can reduce the change in source-drain current with respect to a change in gate-source voltage compared to a Si transistor. Therefore, by using an OS transistor as a driving transistor included in a pixel circuit, the amount of current flowing through the light-emitting device can be precisely controlled. This allows for a larger number of gray levels in the pixel circuit. Furthermore, even if the electrical characteristics (e.g., resistance) of the light-emitting device fluctuate or vary, a stable current can flow.

[0208] As described above, by using an OS transistor for a driving transistor included in a pixel circuit, it is possible to achieve "suppression of black floating," "increase in light emission luminance," "multiple gradations," "suppression of the influence of manufacturing variations in light-emitting devices," and the like.

[0209] OS transistors exhibit little change in electrical characteristics due to radiation exposure, i.e., have high radiation resistance, and therefore can be suitably used in environments where radiation may be incident. It can also be said that OS transistors have high reliability against radiation. For example, OS transistors can be suitably used in pixel circuits of X-ray flat panel detectors. Furthermore, OS transistors can be suitably used in semiconductor devices used in outer space. Examples of radiation include electromagnetic radiation (e.g., X-rays and gamma rays) and particle radiation (e.g., alpha rays, beta rays, proton rays, and neutron rays).

[0210] The semiconductor layer 21 is preferably crystalline, and is particularly preferably a single-crystal semiconductor or a polycrystalline semiconductor. Use of a crystalline semiconductor is preferable because it can suppress deterioration of transistor characteristics.

[0211] <Gate Insulating Layer> The insulating layer 22 functions as a gate insulating layer of a transistor. When an oxide semiconductor is used for the semiconductor layer 21, it is preferable to use an oxide insulating film for at least the film of the insulating layer 22 that is in contact with the semiconductor layer 21. For example, one or more of silicon oxide, silicon oxynitride, aluminum oxide, aluminum oxynitride, hafnium oxide, hafnium oxynitride, gallium oxide, gallium oxynitride, yttrium oxide, yttrium oxynitride, and Ga—Zn oxide can be used. Alternatively, a nitride insulating film such as silicon nitride, silicon nitride oxide, aluminum nitride, or aluminum nitride oxide can also be used for the insulating layer 22. Furthermore, the insulating layer 22 may have a stacked structure, for example, a stacked structure including one or more oxide insulating films and one or more nitride insulating films.

[0212] Furthermore, the insulating layer 22 is preferably formed by laminating insulating materials having a high dielectric constant (high-k material), and preferably by using a laminate structure of a high-k material and a material having a higher dielectric strength than the high-k material. For example, the insulating layer 22 can be formed by laminating an insulating film (also referred to as ZAZ) in which zirconium oxide, aluminum oxide, and zirconium oxide are stacked in this order. Alternatively, the insulating film (also referred to as ZAZA) can be formed by laminating zirconium oxide, aluminum oxide, zirconium oxide, and aluminum oxide in this order. Alternatively, the insulating film can be formed by laminating hafnium zirconium oxide, aluminum oxide, hafnium zirconium oxide, and aluminum oxide in this order. By using a laminate of insulators with a relatively high dielectric strength, such as aluminum oxide, the dielectric strength is improved, and electrostatic breakdown of the capacitor element can be suppressed.

[0213] Furthermore, a material exhibiting ferroelectricity may be used for the insulating layer 22. Examples of the material exhibiting ferroelectricity include hafnium oxide, zirconium oxide, and HfZrO. Ｘ (X is a real number greater than 0). Ｘ It is also possible to use a metal oxide in which Y (yttrium) is added to HfZrO. ＸBy adding Y to the above, the ferroelectricity can be enhanced.

[0214] When the insulating layer 22 has a two-layer structure, it is preferable to use an insulating film having a function of capturing or fixing hydrogen as the film in contact with the semiconductor layer 21, and to use an insulating film having a barrier property against hydrogen as the film located on the conductive layer 23 side that functions as the gate electrode. This makes it possible to suppress diffusion of hydrogen from the conductive layer 23 side to the semiconductor layer 21, thereby realizing a highly reliable transistor.

[0215] As an insulating film that captures or fixes hydrogen, it is preferable to use a hafnium oxide film, a hafnium silicate film, an aluminum oxide film, etc. Furthermore, as an insulating film having a barrier property against hydrogen, it is preferable to use a silicon nitride film, a silicon nitride oxide film, an aluminum oxide film, a magnesium oxide film, a hafnium oxide film, a gallium oxide film, etc.

[0216] Alternatively, an insulating film that releases oxygen when heated may be used as a film in contact with the semiconductor layer 21, and an insulating film having a barrier property against hydrogen may be used as a film located on the conductive layer 23 side. Alternatively, an insulating film that releases oxygen when heated may be used as a film in contact with the semiconductor layer 21, and an insulating film that has a function of capturing or fixing hydrogen may be used as a film located on the conductive layer 23 side.

[0217] When the insulating layer 22 has a three-layer structure, it is preferable to use an insulating film made of a material through which oxygen easily diffuses as the film in contact with the semiconductor layer 21, an insulating film having barrier properties against hydrogen and oxygen as the film located on the conductive layer 23 side, and an insulating film having the function of capturing or fixing hydrogen as the film located between them. Silicon oxide or silicon oxynitride can be used as the material through which oxygen easily diffuses. With this structure, oxygen can be supplied to the semiconductor layer 21 from the film in contact with the semiconductor layer 21. Furthermore, the film located on the conductive layer 23 side prevents oxygen from diffusing toward the conductive layer 23, thereby suppressing oxidation of the conductive layer 23.

[0218] As the insulating film having a barrier property against oxygen, it is preferable to use an aluminum oxide film, a silicon nitride film, a hafnium oxide film, a hafnium silicate film, etc. As the insulating film having a barrier property against oxygen and hydrogen, it is preferable to use an aluminum oxide film, a silicon nitride film, a hafnium oxide film, etc.

[0219] When the insulating layer 22 has a four-layer structure, it is preferable to use an insulating film having a barrier property against oxygen as the film in contact with the semiconductor layer 21, followed by an insulating film made of a material through which oxygen easily diffuses, an insulating film having a function of capturing or fixing hydrogen, and an insulating film having a barrier property against hydrogen and oxygen, from the side closer to the semiconductor layer 21. That is, in addition to the above-mentioned three-layer structure, a configuration can be obtained in which a film in contact with the semiconductor layer 21 is added. By using an insulating film having a barrier property against oxygen as the film in contact with the semiconductor layer 21, oxygen can be prevented from being desorbed from the semiconductor layer 21. In this case, it is preferable to use an aluminum oxide film as the film in contact with the semiconductor layer 21. Aluminum oxide not only has a barrier property against oxygen but also has a function of capturing or fixing hydrogen, and therefore has the effect of preventing hydrogen from diffusing into the semiconductor layer 21.

[0220] When the insulating layer 22 has a stacked structure, each insulating film is preferably a thin film. For example, the thickness of the insulating layer 22 is 1 nm to 20 nm, preferably 3 nm to 10 nm, to reduce the subthreshold swing (also referred to as the S value) of the transistor. The thickness of each insulating film is preferably 0.1 nm to 10 nm, more preferably 0.1 nm to 5 nm, more preferably 0.5 nm to 5 nm, still more preferably 1 nm to less than 5 nm, and even more preferably 1 nm to 3 nm.

[0221] As a specific example, it is preferable to use a four-layer structure in which an aluminum oxide film, a silicon oxide film, a hafnium oxide film, and a silicon nitride film are stacked in this order from the semiconductor layer 21 side, and to set the thicknesses of these films to 1 nm, 2 nm, 2 nm, and 1 nm from the semiconductor layer 21 side.

[0222] In this specification and the like, the barrier property refers to a property that makes it difficult for a corresponding substance to diffuse (also referred to as a property that makes it difficult for a corresponding substance to permeate, a property that the permeability of a corresponding substance is low, or a function that suppresses the diffusion of a corresponding substance). Note that when hydrogen is described as a corresponding substance, it can refer to, for example, a hydrogen atom, a hydrogen molecule, a water molecule, and OH. − Furthermore, unless otherwise specified, impurities when described as corresponding substances refer to impurities in the channel formation region or semiconductor layer, and include, for example, hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, and nitrogen oxide molecules (N ２ O, NO, NO ２ The term "oxygen" refers to at least one of an oxygen atom, an oxygen molecule, etc., when described as a corresponding substance.

[0223] Here, a transistor using a metal oxide film can have stable electrical characteristics by being surrounded by an insulating film that has a function of suppressing the permeation of impurities and oxygen. Examples of insulating films that have a function of suppressing the permeation of impurities and oxygen include insulating films containing one or more elements selected from boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, and tantalum, and the insulating films can be used in a single layer or a stacked layer. Specifically, examples of materials that can be used for the insulating film that has a function of suppressing the permeation of impurities and oxygen include metal oxides such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide, and metal nitrides such as aluminum nitride.

[0224] Specifically, examples of insulating film materials that have the function of suppressing the permeation of impurities such as water and hydrogen and oxygen include metal oxides such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide. Examples of insulating film materials that have the function of suppressing the permeation of impurities such as water and hydrogen and oxygen include oxides containing aluminum and hafnium (hafnium aluminate). Examples of insulating film materials that have the function of suppressing the permeation of impurities such as water and hydrogen and oxygen include metal nitrides such as aluminum nitride.

[0225] Examples of insulating film materials capable of capturing or adhering hydrogen include metal oxides such as oxides containing hafnium, oxides containing magnesium, oxides containing aluminum, and oxides containing aluminum and hafnium (hafnium aluminate). These metal oxides may further contain zirconium, such as oxides containing hafnium and zirconium. Metal oxides with an amorphous structure have dangling bonds in some oxygen atoms, which enhance their ability to capture or adhering hydrogen. Therefore, these metal oxides preferably have an amorphous structure. For example, an amorphous structure may be achieved by including silicon in these oxides. For example, it is preferable to use an oxide containing hafnium and silicon (hafnium silicate). Metal oxides may have crystalline regions and / or grain boundaries in some regions.

[0226] <Conductive Layer> The conductive layer 24 and the conductive layer 25 are in contact with the semiconductor layer 21. When an oxide semiconductor is used as the semiconductor layer 21, if an easily oxidized metal such as aluminum is used in the portion of the conductive layer 24 or the conductive layer 25 in contact with the semiconductor layer 21, an insulating oxide (e.g., aluminum oxide) may be formed between the conductive layer 24 or the conductive layer 25 and the semiconductor layer 21, preventing electrical conduction therebetween. Therefore, it is preferable to use a conductive material that is resistant to oxidation, a conductive material that maintains low electrical resistance even when oxidized, or a conductive oxide material for at least the portion of the conductive layer 24 and the conductive layer 25 in contact with the semiconductor layer 21.

[0227] As the conductive film in contact with the semiconductor layer 21, it is preferable to use, for example, titanium, tantalum nitride, titanium nitride, nitride containing titanium and aluminum, nitride containing tantalum and aluminum, ruthenium, ruthenium oxide, ruthenium nitride, oxide containing strontium and ruthenium, oxide containing lanthanum and nickel, etc. These are conductive materials that are difficult to oxidize, or materials that maintain conductivity even when oxidized, and are therefore preferable.

[0228] Alternatively, conductive oxides such as indium oxide, zinc oxide, In—Sn oxide, In—Zn oxide, In—W oxide, In—W—Zn oxide, In—Ti oxide, In—Ti—Sn oxide, In—Sn—Si oxide, and Ga—Zn oxide can be used. Conductive oxides containing indium are particularly preferred because of their high conductivity. Alternatively, oxide materials such as In—Ga—Zn oxide that can be used for the semiconductor layer 21 can also be used as a conductive layer by increasing the carrier concentration.

[0229] For example, the conductive layer 24 and the conductive layer 25 may each be a single-layer structure of the conductive oxide film, a three-layer structure in which a titanium nitride film, a tungsten film, and a titanium nitride film are stacked in this order, a two-layer structure in which a ruthenium film or a ruthenium oxide film is stacked on tungsten, a two-layer structure in which a ruthenium film or a ruthenium oxide film is stacked on the conductive oxide film, or a two-layer structure in which the conductive oxide film is stacked on a ruthenium film or a ruthenium oxide film. Note that ruthenium is a material that is difficult to etch, so when ruthenium is used, the thinner the film, the better, and it is preferably used in a thickness of, for example, 0.1 nm to 2 nm.

[0230] The conductive layer 23 functions as a gate electrode and can be made of various conductive materials. For example, a metal element selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, cobalt, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, lanthanum, etc., or an alloy containing such a metal element, may be used. Alternatively, nitrides of the above metals or alloys, or oxides of the above metals or alloys, may be used. For example, tantalum nitride, titanium nitride, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, oxides containing lanthanum and nickel, etc. may be used. Alternatively, semiconductors with high electrical conductivity, such as polycrystalline silicon containing impurity elements such as phosphorus, or silicides such as nickel silicide may be used.

[0231] The conductive layer 23 may be made of the nitride or oxide that can be used for the conductive layers 24 and 25 .

[0232] Since the conductive layer 23 also functions as wiring, it is preferable to use a stack of low-resistance conductive materials. For example, the conductive film 24 a and the conductive film 25 a can also be made of the low-resistance conductive material that can be used for the conductive layer 23 described above.

[0233] <Insulating Layer> The insulating layer 41 can be used as an interlayer insulating film. For example, it is preferably formed by a film formation method such as a sputtering method or a plasma CVD method. In particular, when a sputtering method is used, hydrogen is not used as a film formation gas, and therefore a film with an extremely low hydrogen content can be obtained. Therefore, the supply of hydrogen to the semiconductor layer 21 can be suppressed, and the electrical characteristics of the transistor 10 can be stabilized.

[0234] The insulating layer 41 is preferably an oxide insulating film because it is in contact with the channel formation region of the semiconductor layer 21. In particular, it is preferably an oxide insulating film that releases oxygen when heated. The oxide insulating film that can be used for the gate insulating layer can be used as the insulating layer 41.

[0235] Furthermore, since the insulating layer 41 functions as an interlayer insulating layer, it is preferable to use a film formation method that allows film formation at a higher film formation rate than other insulating layers. For example, the insulating layer 41 may be a silicon oxide film (also called a TEOS film) formed using TEOS by a plasma CVD method. This can improve productivity.

[0236] The insulating layer 11, the insulating layer 35, the insulating layer 42, the insulating layer 44, the insulating layer 46, and the insulating layer 47 each function as an interlayer insulating layer. The insulating layer 11, the insulating layer 35, the insulating layer 42, the insulating layer 44, the insulating layer 46, and the insulating layer 47 can be made of the same insulating material as can be used for the insulating layer 41.

[0237] The insulating layer 52 functions as a dielectric for the capacitance element 30. The insulating layer 52 can be made of the same insulating material as the insulating layer 22. Furthermore, by using the ferroelectric material for the insulating layer 52, the capacitance element 30 can be made into a ferroelectric capacitor, thereby realizing a nonvolatile memory device. Note that the capacitance element 30 can also be a resistance change type memory element that utilizes the electric field induced giant resistance change (CER: Colossal Electro-Resistance) effect.

[0238] This concludes the description of the components.

[0239] [Modification] The following describes an example in which the configuration is partially different from the above-described configuration example. Note that the same reference numerals are used to designate the same parts as those described above, and descriptions thereof will be omitted.

[0240] 13A and 13B are a cross-sectional view and a perspective view, respectively, of a semiconductor device exemplified below. The configurations shown in Fig. 13A and 13B differ from the above-described configuration examples mainly in that the shapes of the semiconductor layer 21, the insulating layer 22, and the upper portions of the conductive layer 23 are different, and that an insulating layer 43 is provided.

[0241] The semiconductor layer 21, the insulating layer 22, and the conductive layer 23 have flattened upper portions, and the heights of their upper surfaces (e.g., heights from the substrate surface) are approximately the same. Furthermore, the heights of the upper surfaces of the semiconductor layer 21, the insulating layer 22, and the conductive layer 23 are approximately the same as the height of the upper surface of the conductive layer 25 (specifically, the conductive film 25b). With this configuration, the conductive layer 25 and the conductive layer 23 do not overlap in a planar view, thereby reducing the parasitic capacitance between the conductive layer 25 and the conductive layer 23. This makes it possible to realize a semiconductor device capable of high-speed operation.

[0242] An insulating layer 43 is provided in contact with the upper surface of the conductive layer 25, the upper surface of the semiconductor layer 21, the upper surface of the insulating layer 22, and the upper surface of the conductive layer 23. The insulating layer 43 functions as a barrier film that prevents impurities such as hydrogen from diffusing from above into the semiconductor layer 21. For example, a film through which hydrogen is less likely to diffuse than a silicon oxide film (having barrier properties against hydrogen), such as a silicon nitride film, a silicon nitride oxide film, an aluminum oxide film, a magnesium oxide film, a hafnium oxide film, or a gallium oxide film, can be used. In particular, it is preferable to use a silicon nitride film or a silicon nitride oxide film.

[0243] Furthermore, the insulating layer 43 preferably includes a stack of an insulating film functioning as a barrier film and an insulating film having a function of capturing or fixing hydrogen, the stack being closer to the semiconductor layer 21 than the insulating film. This allows hydrogen that may diffuse into the semiconductor layer 21 due to heat or the like applied during the manufacturing process of the transistor 10 or the memory cell 15 to be captured or fixed by the insulating film, thereby reducing the concentration of hydrogen contained in the semiconductor layer 21. This makes it possible to realize a highly reliable transistor 10 or semiconductor device 50 with good electrical characteristics. As the insulating film that captures or fixes hydrogen, a hafnium oxide film, a hafnium silicate film, an aluminum oxide film, a hafnium zirconium oxide film, or the like is preferably used.

[0244] An insulating layer 44 that functions as an interlayer insulating film is provided on the insulating layer 43. The insulating layer 44 does not have to be provided if it is not necessary.

[0245] A conductive layer 26 functioning as a bit line is provided on the insulating layer 44. Furthermore, a plug 27 connecting the conductive layer 25 and the conductive layer 26 is provided through an opening provided in the insulating layer 44 and the insulating layer 43. This allows the conductive layer 26 to connect the multiple conductive layers 25 arranged in the X direction with the slit 20 therebetween.

[0246] [Modification 2] The configuration shown in FIGS. 14A and 14B differs from the above-described configuration example mainly in that the extending directions of the word lines and bit lines are interchanged.

[0247] The conductive layer 23 is processed into an island shape and is connected to a conductive layer 29 located above it, which functions as a word line. The conductive layer 29 extends in the X direction. On the other hand, the conductive layer 25 extends in the same direction as the slit 20, i.e., the Y direction. The conductive layer 25 functions as a bit line.

[0248] An insulating layer 44 is provided on the insulating layer 41, and a portion of the conductive layer 23 is provided so as to be embedded in the insulating layer 44. The upper surface of the conductive layer 23 is flattened, and the height of the substrate surface is approximately the same as the upper surface of the insulating layer 44. The conductive layer 29 is provided on the conductive layer 23 and the insulating layer 44.

[0249] Furthermore, the insulating layer 22 and the semiconductor layer 21 each have a top surface shape that is approximately the same as that of the conductive layer 23. For example, the insulating layer 22 and the semiconductor layer 21 can be configured to be added using the same etching mask as that used for the conductive layer 23.

[0250] Furthermore, an insulating layer 43 is provided between the insulating layer 44 and each of the semiconductor layer 21, the insulating layer 22, the conductive layer 23, the conductive layer 25, and the insulating layer 41. The insulating layer 43 can prevent impurities such as hydrogen from diffusing from the insulating layer 44 to the semiconductor layer 21.

[0251] [Modification 3] The configuration shown in FIGS. 15A and 15B differs from Modification 2 above mainly in that two transistors (transistors 10a) are provided in one slit 20.

[0252] The semiconductor layer 21, the insulating layer 22, the conductive layer 23, and the conductive layer 24 are divided into two parts within the slit 20 along the extension direction of the slit 20. The semiconductor layer 21 and the insulating layer 22 are provided along one of a pair of side surfaces of the insulating layer 41 within the slit 20.

[0253] A capacitance element 30 is provided in each of the pair of divided conductive layers 24. This allows one slit 20 to be shared by two memory cells 15. In this case, two slits 40 are provided for one slit 20. The slits 40 are provided at positions shifted in the X direction from the center of the slit 20.

[0254] Furthermore, an insulating layer 48 is provided along the side surfaces of the conductive layer 23, the insulating layer 22, the semiconductor layer 21, and the conductive layer 24, and along the top surface of the insulating layer 52. A recess is formed in the top surface of the insulating layer 48, and an insulating layer 44a is provided on the insulating layer 48 so as to fill the recess. The insulating layer 44a can be made of the same material as the insulating layer 44. Like the insulating layer 43, the insulating layer 48 preferably functions as a barrier film against impurities. This can prevent impurities such as hydrogen contained in the insulating layer 44a from diffusing into the semiconductor layer 21.

[0255] [Modification 4] The configuration shown in FIGS. 16A and 16B differs from the above-described modification 3 mainly in that two capacitance elements (capacitance elements 30a) are provided in one slit 40.

[0256] The conductive film 24a is divided into two parts within the slit 40. An insulating layer 46a is provided so as to fill the gap between the two conductive films 24a within the slit 40. The insulating layer 48 is not in contact with the insulating layer 52, but is provided in contact with a part of the conductive film 24a and the upper surface of the insulating layer 46a.

[0257] With this configuration, the slit 20 and the slit 40 can be shared by two memory cells 15. This allows the memory cells 15 to be integrated at a higher density than in the configuration illustrated in FIG.

[0258] [Variation 5] The configuration shown in Figures 17A and 17B shows an example in which the configuration in which two transistors are provided within the slit 20, as exemplified in Variation 3 above, is applied to the configuration exemplified in the above configuration example.

[0259] Two transistors 10b are provided in one slit 20. A pair of conductive layers 23 provided in the slit 20 each extend in the Y direction and function as a word line. A conductive layer 26 extending in the X direction functions as a bit line.

[0260] The insulating layer 48 is provided to cover the side and top surfaces of the conductive layer 23 and to cover the top surface of the insulating layer 22. The insulating layer 44 is provided to cover the insulating layer 48. A portion of the insulating layer 44 is provided to fill the gap between the pair of conductive layers 23.

[0261] 18A and 18B show an example in which the configuration exemplified in the above configuration example is applied to the configuration in which two capacitance elements 30a are provided within the slit 40, as exemplified in Modification Example 4. The configuration shown in Figures 18A and 18B has a pair of capacitance elements 30a that share the slit 40 and a pair of transistors 10b that share the slit 20.

[0262] [Modification 6] The configuration shown in FIGS. 19A and 19B is an example in which the transistor 10 and the capacitive element 30b are arranged side by side.

[0263] The transistor 10 has a configuration similar to that of the above-described example. The capacitance element 30b is provided in the insulating layer 44, the insulating layer 22, the insulating layer 43, and the insulating layer 41 (insulating layers 41c, 41b, and 41a), and is located inside the slit 40a that reaches the conductive layer 24.

[0264] The capacitance element 30b has a conductive layer 51, an insulating layer 52, and a conductive layer 53. The conductive layer 53 functions as a wiring (e.g., wiring CL) extending in the Y direction. Within the slit 40a, the conductive layer 51 is divided into individual capacitance elements, as shown in FIG. 19B . The conductive layer 51 contacts the conductive layer 24 at the bottom of the slit 40a. One conductive layer 51 and one conductive layer 24 are provided for each memory cell 15.

[0265] The insulating layer 52 is provided to cover the insulating layer 44. Furthermore, an insulating layer 33 is provided to cover the insulating layer 52 and the conductive layer 53, and an insulating layer 49 is provided on the insulating layer 33. A conductive layer 26 is provided on the insulating layer 49 and is connected to the conductive layer 25 (conductive film 25a) via a plug 27. The insulating layer 33 functions as a barrier film, similar to the insulating layer 43. The insulating layer 49 functions as an interlayer insulating film, similar to the insulating layer 44. By providing the insulating layer 33, impurities such as hydrogen contained in the insulating layer 49 can be prevented from diffusing into the semiconductor layer 21.

[0266] With this structure, the transistor 10 and the capacitor 30b can share some components, which reduces manufacturing costs compared to a structure in which the transistor and the capacitor are stacked.

[0267] The above is a description of the modified example.

[0268] [Manufacturing Method Example] An example of a manufacturing method of a semiconductor device according to one embodiment of the present invention will be described below, taking a semiconductor device including the memory cell 15 exemplified in the above structure example as an example.

[0269] Thin films (insulating films, semiconductor films, conductive films, etc.) constituting the semiconductor device can be formed by sputtering, chemical vapor deposition (CVD), vacuum evaporation, pulsed laser deposition (PLD), atomic layer deposition, or the like.

[0270] Furthermore, thin films (insulating films, semiconductor films, conductive films, etc.) constituting the semiconductor device can be formed by methods such as spin coating, dipping, spray coating, inkjet, dispensing, screen printing, offset printing, doctor knife, slit coating, roll coating, curtain coating, and knife coating.

[0271] Sputtering methods include RF sputtering, which uses a high-frequency power supply as the sputtering power source; DC sputtering, which uses a direct current power supply; and pulsed DC sputtering, which changes the voltage applied to the electrode in a pulsed manner. RF sputtering is preferably used for film formation using an insulating target. DC sputtering is mainly used when forming films using a conductive target. In addition to forming conductive films, DC sputtering can also form insulating films by reactive sputtering using pulsed DC sputtering. Specifically, pulsed DC sputtering can be used when forming films of compounds such as oxides, nitrides, and carbides using reactive sputtering.

[0272] CVD methods can be classified into plasma-enhanced chemical vapor deposition (PECVD), which uses plasma, thermal CVD (TCVD), which uses heat, and photo-CVD (photo-CVD), which uses light. CVD methods can also be further classified into metal CVD (MCVD) and metal organic CVD (MOCVD), depending on the source gas used.

[0273] The plasma CVD method can produce high-quality films at relatively low temperatures. Furthermore, since the thermal CVD method does not use plasma, it is possible to reduce plasma damage to the workpiece. Furthermore, since the thermal CVD method does not cause plasma damage during film formation, it can produce films with fewer defects.

[0274] As the ALD method, a thermal ALD method in which a reaction between a precursor and a reactant is carried out using only thermal energy, a PEALD method in which a plasma-excited reactant is used, or the like can be used.

[0275] Unlike sputtering, CVD and ALD are film formation methods that are less affected by the shape of the workpiece and have good step coverage. In particular, ALD has excellent step coverage and excellent thickness uniformity, making it suitable for coating the surface of an opening with a high aspect ratio. However, because ALD has a relatively slow film formation rate, it may be preferable to use it in combination with other film formation methods, such as CVD, which have a faster film formation rate.

[0276] In the CVD method, a film of any composition can be formed by adjusting the flow rate ratio of the source gases. For example, in the CVD method, a film with a continuously changing composition can be formed by changing the flow rate ratio of the source gases while forming the film. When forming a film while changing the flow rate ratio of the source gases, the time required for film formation can be shortened compared to when forming a film using multiple film formation chambers because no time is required for transportation or pressure adjustment. Therefore, the productivity of semiconductor devices can be increased in some cases.

[0277] In the ALD method, a film of any composition can be formed by simultaneously introducing multiple different precursors. Alternatively, when multiple different precursors are introduced, a film of any composition can be formed by controlling the number of cycles of each precursor. Furthermore, as with the CVD method, a film with a continuously changing composition can be formed.

[0278] The thin film constituting the semiconductor device can be processed using a photolithography method or the like. Alternatively, the thin film may be processed using a nanoimprint method, a sandblasting method, a lift-off method or the like. Alternatively, the island-shaped thin film may be directly formed by a film formation method using a shielding mask such as a metal mask.

[0279] There are two typical photolithography methods: one is to form a resist mask on the thin film to be processed, process the thin film by etching or the like, and then remove the resist mask; the other is to form a photosensitive thin film, and then process the thin film into the desired shape by exposure and development.

[0280] In photolithography, the light used for exposure can be, for example, i-line (wavelength 365 nm), g-line (wavelength 436 nm), h-line (wavelength 405 nm), or a mixture of these. Other light sources that can be used include ultraviolet light, KrF laser light, ArF laser light, etc. Exposure can also be performed by immersion exposure technology. Extreme ultraviolet (EUV) light or X-rays can also be used as the light used for exposure. An electron beam can also be used instead of light used for exposure. Extreme ultraviolet light, X-rays, or an electron beam are preferred because they enable extremely fine processing. When exposure is performed by scanning a beam such as an electron beam, a photomask is not required.

[0281] For etching the thin film, dry etching, wet etching, sandblasting, or the like can be used.

[0282] 20A to 26B are schematic cross-sectional views corresponding to each step in the fabrication method exemplified below. In each figure, the cross section corresponding to FIG. 6A is shown on the left side of the dashed dotted line, and the cross section corresponding to FIG. 6B is shown on the right side.

[0283] First, a substrate (not shown) is prepared, and an insulating layer 11 is formed on the substrate.

[0284] The substrate may be a substrate having heat resistance sufficient to withstand at least the subsequent heat treatment.

[0285] An inorganic insulating film such as a silicon oxide film or a silicon oxynitride film can be used as the insulating layer 11. The insulating layer 11 can be formed by a sputtering method, a CVD method, a molecular beam epitaxy (MBE), a PLD method, an ALD method, or the like. If the surface on which the insulating layer 11 is to be formed is not flat, a planarization process may be performed after the insulating layer 11 is formed so that the upper surface of the insulating layer 11 becomes flat.

[0286] Next, a conductive film that will become the conductive layer 55 is formed on the insulating layer 11. The conductive film can be formed by a film formation method such as a sputtering method, an ALD method, or a CVD method. Next, a resist mask is formed on the conductive film, and unnecessary portions of the conductive film are removed by etching to form the conductive layer 55. The conductive layer 55 can have a plate-like, line-like, or lattice-like shape.

[0287] Subsequently, an insulating film may be formed to cover the conductive layer 55, and then planarization treatment may be performed until the top surface of the conductive layer 55 is exposed. This allows the conductive layer 55 to be embedded in an insulating layer (not shown). Note that although an example in which an insulating layer (not shown) is formed after the conductive layer 55 is shown here, the conductive layer 55 and the insulating layer may be formed by forming an insulating film, forming an opening (or a recess) in the insulating film for embedding the conductive layer 55, and then forming a conductive film to become the conductive layer 55, and performing planarization treatment until the surface of the insulating film is exposed. For the planarization treatment, for example, CMP (Chemical Mechanical Polishing), dry etching, or the like may be used.

[0288] Subsequently, the insulating layer 46 is formed on the conductive layer 55 (FIG. 20A). The insulating layer 46 can be formed by a film formation method such as a sputtering method, an ALD method, or a CVD method.

[0289] In addition, if the conductive layer 55 is not embedded in an insulating layer (not shown), after the insulating layer 46 is formed, an uneven shape that reflects the shape of the conductive layer 55 may be formed on the upper surface of the insulating layer 46. In this case, it is preferable to perform a planarization process on the upper surface of the insulating layer 46.

[0290] Next, slits 40 are formed in the insulating layer 46, reaching the conductive layer 55 (FIG. 20B). At this time, part of the upper surface of the conductive layer 55 may be etched. It is preferable to perform the etching so that a curved surface is formed on the upper part of the conductive layer 55.

[0291] Next, a conductive film 51f that will become the conductive layer 51 is formed to cover the upper surface of the insulating layer 46, the side surfaces of the insulating layer 46 in the slits 40, and the upper surface of the conductive layer 55 ( FIG. 20C ). The conductive film 51f can be formed by a method such as CVD, ALD, or sputtering. From the viewpoint of coverage, it is particularly preferable to form the conductive film 51f by the CVD method.

[0292] A sacrificial layer is formed on the conductive film so as to cover the recess of the slit 40, a planarization process is performed until the top surface of the insulating layer 46 is exposed, and the sacrificial layer is removed, thereby forming a conductive layer 51 that is located only inside the slit 40 (Figure 21A).

[0293] Here, during the planarization process or removal of the sacrificial layer, the height of the upper surface of the conductive layer 51 may become lower than the upper surface of the insulating layer 46. Furthermore, the corners of the upper end of the conductive layer 51 and the upper end of the slit 40 of the insulating layer 46 may be scraped off and rounded.

[0294] Next, an insulating layer 52 is formed along the surfaces of the insulating layer 46 and the conductive layer 51. The insulating layer 52 can be formed by a film formation method such as sputtering, ALD, or CVD, but ALD is preferable from the viewpoint of coverage. Next, a conductive film 24af that will become the conductive film 24a is formed on the insulating layer 52 so as to fill the recesses in the slits 40 of the insulating layer 46. Thereafter, the upper surface of the conductive film 24af may be planarized as necessary. Next, a conductive film 24bf that will become the conductive film 24b is formed on the conductive film 24af ( FIG. 21B ). The conductive films 24af and 24bf can each be formed by a film formation method such as sputtering, ALD, or CVD.

[0295] Next, a resist mask is formed on the conductive film 24bf, and unnecessary portions of each conductive film are removed by etching to form the conductive layer 24 including the conductive film 24a and the conductive film 24b (FIG. 21C). At this point, the capacitor element 30 can be formed.

[0296] Subsequently, an insulating layer 41 is formed to cover the conductive layer 24, and a planarization process is performed on the upper surface of the insulating layer 41. The insulating layer 41 can be formed by a film formation method such as a sputtering method, an ALD method, or a CVD method.

[0297] The insulating layer 41 is preferably an oxide film containing a large amount of oxygen to such an extent that oxygen is released by heating and a small amount of hydrogen. The insulating layer 41 can be formed by a film formation method such as a PECVD method, a sputtering method, or an ALD method, but is preferably formed by a sputtering method. In particular, by forming the insulating layer 41 using a gas containing oxygen and not a gas containing hydrogen as a film formation gas, an insulating film containing an extremely small amount of hydrogen and an excess amount of oxygen can be formed. By forming the insulating layer 41 in this manner, oxygen can be supplied from the insulating layer 41 to the channel formation region of the semiconductor layer 21, thereby reducing oxygen vacancies.

[0298] Subsequently, heat treatment may be performed. The heat treatment is preferably performed at a temperature of 250° C. or higher and 650° C. or lower, preferably 300° C. or higher and 500° C. or lower, more preferably 320° C. or higher and 450° C. or lower. Note that the heat treatment is performed in a nitrogen gas or inert gas atmosphere, or an atmosphere containing an oxidizing gas at 10 ppm or higher, 1% or higher, or 10% or higher. For example, when the heat treatment is performed in a mixed atmosphere of nitrogen gas and oxygen gas, the oxygen gas concentration is preferably about 20%. The heat treatment may be performed under reduced pressure. Alternatively, the heat treatment may be performed in a nitrogen gas or inert gas atmosphere, and then in an atmosphere containing an oxidizing gas at 10 ppm or higher, 1% or higher, or 10% or higher to compensate for desorbed oxygen. By performing the above heat treatment, impurities such as water and hydrogen contained in the insulating layer 41 or the like can be reduced before the formation of an oxide semiconductor film to be a semiconductor layer.

[0299] The gas used in the heat treatment is preferably highly purified. For example, the amount of moisture contained in the gas used in the heat treatment is set to 1 ppb (0.001 ppm) or less, preferably 0.1 ppb or less, and more preferably 0.05 ppb or less. By performing the heat treatment using a highly purified gas, it is possible to prevent moisture and the like from being introduced into the insulating layer 41 and the like as much as possible.

[0300] A process for supplying oxygen may be performed after the insulating layer 41 is formed. This allows oxygen to be supplied from the insulating layer 41 to the semiconductor film 21f by heat or the like applied after the semiconductor film 21f is formed.

[0301] Examples of the treatment for supplying oxygen include heat treatment in an oxygen-containing atmosphere and plasma treatment (including microwave plasma treatment) in an oxygen-containing atmosphere. Alternatively, oxygen may be supplied to the insulating layer by forming an oxide film (preferably a metal oxide film) in an oxygen-containing atmosphere by sputtering. The formed oxide film may be removed immediately or may be left as it is. Note that the oxygen-containing atmosphere may be oxygen gas (O ２ ) as well as ozone (O ３ ), nitrous oxide (N ２ The atmosphere may include a gas containing an oxygen-containing compound such as oxygen (O).

[0302] Next, a conductive film 25af that will become the conductive film 25a and a conductive film 25bf that will become the conductive film 25b are stacked and formed on the insulating layer 41 (FIG. 22A). The conductive films 25af and 25bf can be formed by a film formation method such as a sputtering method, an ALD method, or a CVD method.

[0303] Next, a resist mask is formed on the conductive film 25bf, and unnecessary portions of each conductive film are removed to form the conductive film 25a and the conductive film 25b. Next, an insulating film that will become the insulating layer 42 is formed, and a planarization process is performed until the top surface of the conductive film 25b is exposed, thereby forming the insulating layer 42 (FIG. 22B). This allows the conductive film 25a and the conductive film 25b to be embedded in the insulating layer 42.

[0304] The insulating layer 42 may not be provided if it is not necessary.

[0305] Next, a resist mask is formed on the conductive film 25b and the insulating layer 42, and a slit 20 is formed in the conductive film 25b, the conductive film 25a, the insulating layer 42, and the insulating layer 41 ( FIG. 23A ). When forming the slit 20, it is preferable to etch a portion of the conductive film 24a located at the bottom of the slit 20 to form a recess in the conductive film 24b. At this time, it is preferable to perform etching so that a concave curved surface is formed on the upper part of the conductive film 24a. Furthermore, as shown on the right side of FIG. 23A , it is preferable that a concave curved surface is also formed on the upper surface of the insulating layer 41 in the portion where the conductive film 24a is not provided.

[0306] When forming the slit 20, it is preferable to process the conductive film 25b, the conductive film 25a, the insulating layer 42, and the insulating layer 41 by anisotropic dry etching so that the side walls of the slit 20 (the side surfaces of the conductive film 25b, the conductive film 25a, the insulating layer 42, and the insulating layer 41) are each approximately vertical. Depending on the processing conditions, the side walls of the slit 20 may be inclined with respect to the direction perpendicular to the surface on which they are formed, resulting in a tapered shape.

[0307] Next, a semiconductor film 21f that will become the semiconductor layer 21 is formed to cover the upper and side surfaces of the conductive film 25b, the side surfaces of the conductive film 25a, the side surfaces and upper surface of the insulating layer 42, and the side surfaces of the insulating layer 41 (FIG. 23B).

[0308] The semiconductor film 21f can be formed by the method exemplified in the first embodiment, and reference can be made to this. The semiconductor film 21f is formed by forming an amorphous film and then performing a heat treatment, thereby forming a film in which at least the portion in contact with the side surface of the insulating layer 41 is crystallized.

[0309] The metal oxide film that becomes the semiconductor film 21f can be formed by appropriately using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, etc. In particular, it is preferable to use a sputtering method.

[0310] After the metal oxide film is formed, it is preferable to perform a treatment to enhance the crystallinity of the metal oxide film. Examples of treatments to enhance the crystallinity of the metal oxide film include heat treatment, plasma treatment, microwave (typically 2.45 GHz) treatment, microwave plasma treatment, and light (e.g., ultraviolet light) irradiation treatment. Note that a plurality of these treatments may be performed simultaneously or sequentially. For example, heat treatment and microwave plasma treatment may be performed simultaneously. Alternatively, microwave plasma treatment may be performed after heat treatment.

[0311] The treatment for increasing the crystallinity of the metal oxide film may be performed directly on the metal oxide film after deposition, or may be performed through another film, such as an insulating film, formed on the metal oxide film. For example, a microwave plasma treatment may be performed after the metal oxide film is formed, or an insulating film (e.g., a silicon nitride film, a silicon oxide film, or an aluminum oxide film) may be formed after the metal oxide film is formed, and then a heat treatment or a microwave plasma treatment may be performed on the metal oxide film through the insulating film.

[0312] The above-described treatment for increasing the crystallinity of a metal oxide film can also serve as a treatment for removing impurities contained in the metal oxide film. For example, carbon, hydrogen, nitrogen, and the like contained in the metal oxide film can be preferably removed. Alternatively, by performing the treatment for increasing the crystallinity of a metal oxide film in an oxygen gas atmosphere, oxygen vacancies in the metal oxide film can be reduced.

[0313] When performing a treatment to increase the crystallinity of a metal oxide film, it is preferable to set the temperature of the heat treatment (or the temperature of the substrate) to room temperature (e.g., 25°C) or higher, 100°C or higher and 700°C or lower, 100°C or higher and 600°C or lower, or 300°C or higher and 450°C or lower.

[0314] By increasing the crystallinity of the metal oxide film, a highly reliable transistor can be realized.

[0315] The metal oxide film can be formed by, for example, a sputtering method using a metal oxide target.

[0316] The metal oxide film is preferably a dense film with as few defects as possible. Furthermore, the metal oxide film is preferably a high-purity film with as few impurities as possible, such as hydrogen and water, as reduced as possible. In particular, it is preferable to use a crystalline metal oxide film as the metal oxide film.

[0317] Furthermore, when forming a metal oxide film, oxygen gas may be mixed with an inert gas (e.g., helium gas, argon gas, xenon gas, etc.). Note that the higher the ratio of oxygen gas to the total deposition gas when forming the metal oxide film (hereinafter also referred to as the oxygen flow ratio), the higher the crystallinity of the metal oxide film can be, and a highly reliable transistor can be realized. On the other hand, the lower the oxygen flow ratio, the lower the crystallinity of the metal oxide film can be, and a transistor with a higher on-state current can be obtained.

[0318] When forming a metal oxide film, the higher the substrate temperature, the higher the crystallinity and density of the metal oxide film, whereas the lower the substrate temperature, the lower the crystallinity and electrical conductivity of the metal oxide film.

[0319] Alternatively, a metal oxide film may be formed using an ALD method. In this case, it is preferable to use a film formation method such as a thermal ALD method or a PEALD method. The thermal ALD method is preferable because it exhibits extremely high step coverage. The PEALD method is also preferable because it exhibits high step coverage and allows low-temperature film formation.

[0320] For example, when a metal oxide is used for the semiconductor layer 21, the semiconductor layer 21 can be formed by the ALD method using a precursor containing the constituent metal element and an oxidizing agent.

[0321] For example, when forming an indium oxide film, a precursor containing indium and an oxidizing agent can be used.

[0322] For example, when forming an In—Ga—Zn oxide film, three precursors, i.e., a precursor containing indium, a precursor containing gallium, and a precursor containing zinc, can be used, or two precursors, i.e., a precursor containing indium and a precursor containing gallium and zinc, can be used.

[0323] Examples of precursors that can be used that contain indium include trimethylindium, triethylindium, tris(2,2,6,6-tetramethyl-3,5-heptanedionate)indium, cyclopentadienylindium, indium(III) chloride, and (3-(dimethylamino)propyl)dimethylindium.

[0324] Furthermore, examples of precursors that can be used that contain gallium include trimethylgallium, triethylgallium, tris(dimethylamido)gallium(III), gallium(III) acetylacetonate, tris(2,2,6,6-tetramethyl-3,5-heptanedionate)gallium, dimethylchlorogallium, diethylchlorogallium, and gallium(III) chloride.

[0325] Furthermore, as a precursor containing zinc, dimethyl zinc, diethyl zinc, zinc bis(2,2,6,6-tetramethyl-3,5-heptanedionate), zinc chloride, etc. can be used.

[0326] Examples of oxidizing agents include ozone (O ３ ), oxygen (O ２ ), water (H ２ O), hydrogen peroxide (H ２ O ２ ) etc. can be used.

[0327] Methods for controlling the composition of the resulting film include adjusting the flow rate ratio of the source gases, the time for which the source gases are flowed, the order in which the source gases are flowed, etc. By adjusting these, it is also possible to form a film whose composition changes continuously. It is also possible to form two or more films with different compositions continuously.

[0328] The gas used in the heat treatment after the formation of the metal oxide film is preferably highly purified. For example, the moisture content of the gas used in the heat treatment is preferably 1 ppb or less, preferably 0.1 ppb or less, more preferably 0.05 ppb or less. By performing the heat treatment using a highly purified gas, it is possible to prevent moisture and the like from being incorporated into the metal oxide film as much as possible.

[0329] Next, a resist mask is formed on the semiconductor film 21f. At this time, in order to suppress variations in the thickness of the resist mask, an organic or inorganic material formed by a coating method may be provided between the resist mask and the semiconductor film 21f as a planarizing film that fills the slits 20. More specifically, a coating type insulating film such as an SOC (Spin On Carbon) film or an SOG (Spin On Glass) film may be used.

[0330] Next, the portions of the semiconductor film 21f not covered by the resist mask are removed by etching, and then the resist mask is removed, thereby forming the semiconductor layer 21 ( FIG. 24A ). Because it is difficult to remove the portions of the semiconductor layer 21 that contact the side surfaces of the insulating layer 41 by anisotropic dry etching alone, it is preferable to perform etching by combining isotropic dry etching and wet etching. Alternatively, the regions of the semiconductor film 21f not covered by the resist mask may be treated in advance to alter part of the semiconductor film 21f so that it is easier to etch. Examples of such treatment include plasma treatment, doping (including ion implantation), and wet treatment.

[0331] Next, an insulating layer 22 is formed to cover the semiconductor layer 21 and the insulating layer 41 ( FIG. 24B ). The insulating layer 22 can be formed by a film formation method such as sputtering, ALD, or CVD. It is preferable that the insulating layer 22 be provided on the surface of the vertical portion of the semiconductor layer 21 with as uniform a thickness as possible. Therefore, it is particularly preferable to form the insulating layer 22 by the ALD method, which is a film formation method with extremely excellent coverage. Note that when the sidewalls of the insulating layer 41 are tapered, the insulating layer 22 can be formed by a film formation method such as sputtering or CVD.

[0332] Next, a conductive film 23f, which will later become the conductive layer 23, is formed to cover the insulating layer 22 (FIG. 25A). The conductive film 23f can be formed by a method such as CVD, ALD, or sputtering. From the viewpoint of coverage, it is particularly preferable to form the conductive film 23f by CVD.

[0333] Subsequently, the upper part of the conductive film 23f is etched without using a photomask until the upper surface of the insulating layer 22 is exposed, thereby forming the conductive layer 23 embedded inside the slit 20 (FIG. 25B).

[0334] At this time, it is preferable to process the conductive film 23f so that the upper surface of the conductive layer 23 is located higher than the lower surface of the conductive film 25a. If the height of the upper surface of the conductive layer 23 is lower than the height of the lower surface of the conductive film 25a, a so-called offset region is formed in which a gate electric field is not applied to the semiconductor layer 21. On the other hand, if the height of the upper surface of the conductive layer 23 is higher than the lower surface of the conductive layer 25a, no offset region is formed, and a transistor with a high on-current can be realized.

[0335] At this point, transistor 10 can be formed.

[0336] Subsequently, an insulating layer 44 is formed to cover the conductive film 25b, the semiconductor layer 21, the insulating layer 22, and the conductive layer 23 (FIG. 26A). The insulating layer 44 can be formed by a CVD method, an ALD method, a sputtering method, or the like.

[0337] Next, an opening reaching the conductive film 25 a is formed in the insulating layer 44, the insulating layer 22, the semiconductor layer 21, and the conductive film 25 b. Thereafter, a conductive film is formed to fill the opening, and a planarization process is performed until the upper surface of the insulating layer 44 is exposed, thereby forming the plug 27.

[0338] Subsequently, a conductive film is formed on the insulating layer 44 and the plugs 27, and unnecessary portions are removed by etching to form the conductive layer 26 (FIG. 26B).

[0339] Through the above steps, a semiconductor device including a memory cell 15 including the transistor 10 and the capacitor 30 can be manufactured.

[0340] The above is a description of an example of the manufacturing method.

[0341] Embodiment 3 In this embodiment, an indium oxide film that can be used for a semiconductor layer of a transistor according to one embodiment of the present invention will be described.

[0342] In this specification and the like, indium oxide having at least a crystalline portion or a crystalline region in a film is referred to as crystalline indium oxide (crystal IO) or crystalline indium oxide (crystalline IO). Examples of crystalline IO or crystalline IO include single-crystalline indium oxide, polycrystalline indium oxide, and microcrystalline indium oxide.

[0343] Indium oxide is a semiconductor material having physical properties that are completely different from those of oxide semiconductors such as In—Ga—Zn oxide (hereinafter also referred to as IGZO) and zinc oxide.

[0344] The carrier concentration dependence of the Hall mobility of indium oxide, silicon, and IGZO will be explained. Figure 27A shows the carrier concentration dependence of the Hall mobility of silicon (Si) and indium oxide (InO Ｘ ) and FIG. 27B is a schematic diagram showing the carrier concentration dependence of the hole mobility for IGZO.

[0345] First, IGZO tends to exhibit higher hole mobility as the carrier concentration increases, as shown by the arrows in Figure 27B. On the other hand, indium oxide tends to exhibit higher hole mobility as the carrier concentration decreases, as shown by the arrows in Figure 27A (see Non-Patent Document 1). This trend is similar to that of silicon; the lower the dopant (impurity) concentration in the material, the less impurity scattering there is and the higher the hole mobility. In other words, the higher the purity and intrinsic indium oxide, the higher the hole mobility. From these results, it can be said that indium oxide, unlike IGZO, is a material with physical properties similar to those of silicon. Note that the characteristics of indium oxide shown in Figure 27A are assumed to be single crystal. Therefore, when indium oxide is non-single crystal (e.g., polycrystalline), the characteristics may differ from those shown in Figure 27A.

[0346] 27A, the range R1 of low carrier concentration has extremely high hole mobility, and therefore can be said to be a range of carrier concentration suitable for, for example, a channel formation region of a transistor. For example, in the case of indium oxide, the range R1 is a range where the carrier concentration value is 1×10 １５ cm −３ The range includes, for example, 1×10１４ cm −３ That's it, 1 x 10 １８ cm −３ By sufficiently reducing the carrier concentration, the Hall mobility value can be increased to 270 cm ２ It is expected that the resistance can be increased to about / (V·s).

[0347] In addition, in indium oxide, the region where the carrier concentration is in the range R1 may contain an element that lowers the carrier concentration. Examples of elements that lower the carrier concentration include magnesium, calcium, zinc, cadmium, and copper. By substituting these elements for indium, the carrier concentration can be lowered. Examples of elements that lower the carrier concentration include nitrogen, phosphorus, arsenic, and antimony. For example, by substituting nitrogen, phosphorus, arsenic, or antimony for oxygen, the carrier concentration can be lowered.

[0348] On the other hand, the range R2 with a high carrier concentration has a low electrical resistance, and can be said to be a range of carrier concentrations suitable for, for example, the source and drain regions of a transistor, a resistor, or a transparent conductive film. ２０ cm −３ The range includes, for example, 1×10 １９ cm −３ That's it, 1 x 10 ２２ cm −３ By increasing the carrier concentration sufficiently, the resistivity can be reduced to 1×10 −４ It is expected that the resistivity can be reduced to Ω·cm or less.

[0349] In addition, in indium oxide, the region where the carrier concentration is in the range R2 may contain an element that increases the carrier concentration. For example, it is preferable that the indium oxide contains an element that is common to the source electrode and drain electrode of the transistor. Examples of elements that increase the carrier concentration include titanium, zirconium, hafnium, tantalum, tungsten, molybdenum, tin, silicon, and boron. In particular, it is more preferable to use an element whose oxide has conductive or semiconducting properties. Note that, as a method for supplying an element that increases the carrier concentration, a method of forming a film containing the element and diffusing it, ion implantation, ion doping, plasma immersion ion implantation, or plasma treatment can be used. Note that, unless otherwise specified in this specification, the presence or absence of mass separation is not limited. For example, in this specification, a method of supplying ions after mass separation is referred to as an ion implantation method, and a method of supplying ions without mass separation is referred to as an ion doping method.

[0350] In this way, indium oxide uses a region with a low carrier concentration as the channel formation region of a transistor, and a region with a high carrier concentration as the source and drain regions of the transistor. In other words, indium oxide can be said to be an oxide capable of valence electron control. Note that IGZO may experience strain in the source and drain regions due to stress from electrodes in contact with the IGZO, resulting in the formation of n-type regions. On the other hand, unlike IGZO, indium oxide is capable of valence electron control, and therefore does not require strain to be formed in the film as with IGZO. Less strain in the film is expected to improve reliability. For example, by separately creating a region with a carrier concentration in the range R1 shown in FIG. 27A and a region with a carrier concentration in the range R2 in the indium oxide film, a so-called n-i-n junction (a junction between an n-type region, an i-type region, and an n-type region) can be created. Note that valence electron control in transistors using silicon is generally known. On the other hand, valence electron control in transistors using indium oxide is a novel technical concept that would not normally be conceived.

[0351] By using the above technical concept, the transistor having indium oxide in this specification and the like has two or more, preferably three or more, more preferably four or more, and most preferably five of the following characteristics (1) to (5): (1) high on-current (in other words, high mobility); (2) low off-current; (3) normally-off operation; (4) high reliability; and (5) high cutoff frequency (fT). For example, the transistor having indium oxide in this specification and the like has high mobility, low off-current, and is normally-off operation. The transistor has high mobility and is different from a normally-on transistor.

[0352] In addition, a semiconductor being i-type can be rephrased as having the same Fermi level (Ef) and intrinsic Fermi level (Ei) (Ef = Ei). As shown in FIG. 27B, in IGZO, the lower the carrier concentration, the smaller the hole mobility. Therefore, when Ef = Ei is finally achieved, the carriers disappear (in other words, the physical properties become similar to those of an insulator), and the transistor may no longer function. On the other hand, in indium oxide, as shown in FIG. 27A, the lower the carrier concentration, the higher the hole mobility. When Ef = Ei is finally achieved, the hole mobility is maximized. In other words, a transistor containing indium oxide can achieve high field-effect mobility by setting Ef = Ei. Note that a transistor containing indium oxide is likely to be normally-off due to its low carrier concentration. Therefore, a transistor containing indium oxide can be normally-off and achieve high field-effect mobility.

[0353] Note that normally-off refers to a state in which no current flows through a transistor when no potential is applied to the gate or when the gate-source voltage is 0 V. Furthermore, normally-off can be evaluated by the threshold voltage (Vth) or shift value (Vsh) of the transistor. Unless otherwise specified, Vth is calculated by a constant current method. More specifically, Vth refers to a state in which the value of drain current (Id) × channel length (L) ÷ channel width (W) in the Id-Vg characteristics of a transistor is 1 nA (1 × 10 −９ A). Vsh is the gate voltage (Vg) when the drain current (Id) in the Id-Vg characteristic of the transistor is expressed logarithmically and the tangent of the maximum slope is Id = 1 pA (1 × 10 −１２ The gate voltage (Vg) is the intersection point between the line of Id = 1 pA and the line extrapolated from two points where the slope of Id is maximum when Id is expressed logarithmically in the Id-Vg characteristics of the transistor. For example, if either or both of Vth and Vsh are zero or a positive value, the transistor can be considered to be normally-off.

[0354] In addition, in a transistor containing indium oxide, in order to make the semiconductor i-type, that is, to achieve Ef = Ei, the film structure in contact with the indium oxide film is important. For example, in a transistor containing indium oxide, a film structure in which a silicon oxide film in contact with the indium oxide film, a hafnium oxide film, and a silicon nitride film are stacked is exemplified. By using this film structure, a semiconductor device with high reliability and Ef = Ei can be obtained.

[0355] In the above film configuration, a film containing oxygen, such as a silicon oxynitride film, a silicon nitride oxide film, an aluminum oxide film, or a gallium oxide film, can be used instead of the silicon oxide film. Also, in the above film configuration, a silicon nitride oxide film, a silicon oxynitride film, or the like can be used instead of the silicon nitride film. The hafnium oxide film, which is located closer to the indium oxide film than the silicon nitride film, functions as a gettering site for hydrogen.

[0356] The above film configuration can also be considered as a stacked structure of a film (e.g., a silicon oxide film) capable of supplying oxygen to the indium oxide film from the indium oxide film side, a film (e.g., a hafnium oxide film) capable of gettering hydrogen, and a film (e.g., a silicon nitride film) that suppresses the penetration of oxygen and hydrogen. With this configuration, oxygen vacancies in the indium oxide film are filled with oxygen in the silicon oxide film. Hydrogen in the indium oxide film is captured by the hafnium oxide film by heat treatment or the like. Furthermore, the provision of the silicon nitride film results in a film configuration that reduces the penetration of oxygen and hydrogen from the outside. That is, with the above film configuration, the indium oxide film can be made closer to i-type. Therefore, a transistor having the above-described indium oxide film has high field-effect mobility and high reliability.

[0357] Next, an indium oxide film applied to a transistor will be described. The indium oxide film preferably has crystallinity (i.e., has crystal grains). Examples of films having crystal grains include single-crystal films, polycrystalline films, and amorphous films containing crystal grains (also called microcrystalline films). In particular, the indium oxide film is preferably a polycrystalline film, and more preferably a single-crystal film. A single-crystal film does not have grain boundaries. Impurities (typically, insulating impurities, insulating oxides, etc.) that hinder carrier flow tend to segregate at grain boundaries. The use of a single-crystal film can suppress carrier scattering at grain boundaries, thereby realizing a transistor exhibiting high field-effect mobility. Furthermore, the use of a single-crystal film has the excellent effect of suppressing variations in transistor characteristics due to the grain boundaries.

[0358] Furthermore, polycrystalline films are preferable because they can reduce carrier scattering and exhibit high field-effect mobility compared to microcrystalline or amorphous films. When using a polycrystalline film, it is preferable to use a film with as large a crystal grain size as possible and with few crystal grain boundaries. Note that in a transistor using an indium oxide polycrystalline film, if there is no crystal grain boundary in the channel formation region or no crystal grain boundary is observed, the channel formation region is located within a single crystal region included in the polycrystalline film, and therefore the transistor can be considered to be using single-crystal indium oxide.

[0359] The crystallinity of indium oxide can be analyzed by, for example, X-ray diffraction (XRD), transmission electron microscope (TEM), or electron diffraction (ED). Alternatively, a combination of these methods may be used for analysis.

[0360] In this specification and the like, a semiconductor layer in which no crystal grain boundary is observed in the channel formation region, a semiconductor layer in which the channel formation region is included in one crystal grain, or a semiconductor layer in which the crystal axis direction is the same in at least two regions in the channel formation region can be called a single crystal film. Also, a semiconductor layer in which, in the channel formation region, within one crystal grain, the direction of another crystal axis continuously changes around a certain crystal axis or a certain crystal orientation as the axis of rotation can be called a single crystal film.

[0361] The channel formation region refers to a region of the semiconductor layer that overlaps (or faces) the gate electrode via the gate insulating layer, and is located between the region in contact with the source electrode and the region in contact with the drain electrode. The current path in the channel formation region is the shortest distance between the source electrode and the drain electrode. Therefore, the crystal grains, crystal grain boundaries, crystal axes, crystal orientation, etc. in the channel formation region can be confirmed by observing a cross section including the semiconductor layer, the source electrode, and the drain electrode.

[0362] The indium oxide film in the channel formation region preferably has a lower impurity concentration. Impurities in the indium oxide film in the channel formation region can be a scattering source of carriers, which can lead to a decrease in field-effect mobility. These impurities can also hinder the crystal growth of the indium oxide film. Examples of impurities in the indium oxide film include boron and silicon. The indium oxide film preferably contains these impurities at concentrations of 0.1% or less, and more preferably 0.01% (100 ppm) or less. Carbon, hydrogen, and other elements may be contained in the film-forming gas or precursor during film formation, and may remain in the indium oxide film in greater amounts than the above-mentioned impurities.

[0363] The indium oxide film in the channel formation region may contain an element that can become the same trivalent cation as indium, as long as the crystal maintains a cubic crystal structure (bixbyite type). Examples of such an element include Group 13 elements of the periodic table, such as gallium and aluminum, and Group 3 elements of the periodic table. These elements exist mainly as trivalent cations in oxides, and therefore the carrier concentration of indium oxide can be maintained low.

[0364] In addition, the indium oxide film in this specification and the like has a high film density. ２ O ３ The film densities of the films are shown in Table 1.

[0365]

[0366] As shown in Table 1, the film density of the indium oxide film was evaluated at six levels, Sample 1 to Sample 6. In Table 1, Condition 1 is the condition of the underlayer film for the indium oxide film, Samples 1 to 3 are glass, Sample 4 is a SiOx film formed by sputtering, and Samples 5 and 6 are yttria-stabilized zirconia (YSZ). Condition 2 is the film formation condition for the indium oxide film, Samples 1 to 3 are film formation by sputtering (SP), and Samples 4 to 6 are film formation by ALD. Condition 3 is the heat treatment condition after the formation of the indium oxide film, with Sample 1, Sample 4, and Sample 5 being no heat treatment (as-deposited), Sample 2 being baked at 350°C in a CDA atmosphere, Sample 3 being baked at 650°C in a CDA atmosphere, and Sample 6 being baked at 250°C in a vacuum atmosphere.

[0367] In Table 1, CDA stands for clean dry air. It is preferable that the atmosphere used in the heat treatment (condition 3) after the formation of the indium oxide film contains as little hydrogen and water as possible. It is preferable to use a high-purity gas with a dew point of −60° C. or lower, preferably −100° C. or lower, as the atmosphere.

[0368] As shown in Table 1, the indium oxide film tends to have a higher film density when subjected to heat treatment compared to when not subjected to heat treatment (Sample 1, Sample 4, or Sample 5). This is because the heat treatment removes impurity elements (e.g., carbon, nitrogen, hydrogen, argon, etc.) from the film, thereby increasing the purity of the indium oxide film. Furthermore, as shown in Samples 5 and 6, the indium oxide film on YSZ has a film density of 7.00 g / cm. ３ The theoretical film density of an indium oxide film is 7.18 g / cm ３ In this specification, the range of the film density of the indium oxide film is 6.70 g / cm ３ 7.18g / cm or more ３ Preferably, it is 6.90 g / cm or less.３ 7.18g / cm or more ３ More preferably, it is 7.00 g / cm or less. ３ 7.18g / cm or more ３ The following is the result.

[0369] The film density can be evaluated by, for example, Rutherford backscattering spectroscopy (RBS) or X-ray reflectometry (XRR). Differences in film density can sometimes be evaluated by cross-sectional transmission electron microscope (TEM) images. In TEM observation, a high film density results in a dense (dark) transmission electron (TE) image, whereas a low film density results in a faint (bright) transmission electron (TE) image.

[0370] By using such an indium oxide film in a transistor, the field effect mobility of the transistor can be increased to 50 cm ２ / (V·s) or more, preferably 100 cm ２ / (V·s) or more, more preferably 150 cm ２ / (V·s) or more, more preferably 200 cm ２ / (V·s) or more, more preferably 250 cm ２ / (V·s) or more.

[0371] One of the features of an indium oxide film is that it has higher oxygen permeability (diffusibility) than an IGZO film. As shown in FIG. 27C, Ｘ Oxygen (O) diffusing into the indium oxide film passes through the indium oxide film and becomes oxygen molecules (O ２ ) and is released as water molecules (H ２ O) may be released in the film. Ｏ In the case where an indium oxide film is present, oxygen atoms diffuse to compensate for the oxygen vacancies. Since oxygen diffuses easily in the indium oxide film, it can be said that oxygen vacancies are more easily compensated for in the indium oxide film than in the IGZO film.

[0372] As described above, an indium oxide film can more easily reduce oxygen vacancies in the film than an IGZO film. Therefore, by using such an indium oxide film in a transistor, a transistor with extremely high reliability can be realized.

[0373] Furthermore, as shown in FIG. 27C, the indium oxide film diffuses hydrogen. Hydrogen that diffuses into the indium oxide film from the outside passes through the indium oxide film and becomes hydrogen molecules (H ２ ) or reacts with the oxygen contained in the membrane and is released as water molecules.

[0374] A transistor using an indium oxide film is an accumulation-type transistor that uses electrons as majority carriers. Assuming that the carrier relaxation time is constant, the smaller the effective mass of the electrons (carriers), the higher the electron mobility. In other words, by using indium oxide, which has a small effective mass of electrons, for a transistor, the on-state current or field-effect mobility of the transistor can be increased.

[0375] Table 2 shows the results of single crystal indium oxide (here, In ２ O ３ ) and single-crystal silicon (Si). As shown in Table 2, indium oxide is characterized by a small effective mass of electrons and a large effective mass of holes. Indium oxide also has the characteristic that the effective mass of electrons is almost independent of the crystal orientation. Therefore, by using crystalline indium oxide in a transistor, a transistor with high field-effect mobility and high frequency characteristics (also called f characteristics) can be realized. Furthermore, since the effective mass of holes is large, a transistor with extremely small off-current can be realized. For example, by applying an indium oxide film to a vertical transistor, the off-current per 1 μm of channel width can be reduced to 1 fA (1×10) in an environment of 125° C. −１５ A) or less, or 1aA (1 x 10 −１８ A) or less, and under room temperature (25°C) conditions, −１８ A) or less, or 1zA (1 x 10 −２１Furthermore, as shown in Table 2, indium oxide has a smaller effective mass of electrons and a larger effective mass of holes than silicon, and therefore may be able to realize a transistor with higher field-effect mobility and lower off-state current than a Si transistor.

[0376]

[0377] It is preferable to provide a seed layer so as to be in contact with at least a portion of the crystalline indium oxide film. The seed layer is preferably made of a material containing crystals with a small difference in lattice constant (also called lattice mismatch) with indium oxide. This can improve the crystallinity of the indium oxide film. Note that a substrate (e.g., a single-crystal substrate) may be used as one of the layers in contact with at least a portion of the crystalline indium oxide film.

[0378] One method for evaluating the degree of lattice mismatch is to use the value of the lattice mismatch shown below. The lattice mismatch Δa [%] of the crystals of the formed film (here, the indium oxide film) with respect to the crystals of the seed layer is expressed as Δa = ((L １ -L ２ ) / L ２ ) × 100, where L １ is the length or lattice constant of the unit lattice vector of the crystal of the formed film, and L ２ is the length of the unit cell vector or the lattice constant of the crystal of the seed layer.

[0379] The smaller the absolute value of the lattice mismatch Δa between the seed layer and the indium oxide film, the more preferable, and it is most preferably 0. For example, Δa can be set to −5% or more and 5% or less, preferably −4% or more and 4% or less, more preferably −3% or more and 3% or less, and even more preferably −2% or more and 2% or less.

[0380] Here, the indium oxide crystal has a cubic crystal structure (bixbyite type). For example, the crystal of yttria-stabilized zirconia (YSZ) can have a cubic crystal structure (fluorite type). The lattice mismatch of the indium oxide crystal with the cubic YSZ crystal is in the range of −2% to 2%, and a single crystal film of indium oxide can be epitaxially grown on the YSZ substrate.

[0381] It should be noted that the crystal structure of the seed layer and the crystal structure of the indium oxide film may not necessarily have the same crystal system or crystal orientation. For example, a film having crystals of a hexagonal or trigonal structure may be used under an indium oxide film having crystals of a cubic structure. For example, by setting the crystal orientation of the surface of the seed layer to

[001] and the crystal orientation of the underside of the indium oxide film to

[111] , the requirements related to the crystal orientation necessary for epitaxial growth can be satisfied. Examples of hexagonal or trigonal crystals include wurtzite structure, YbFe ２ O ４ Type structure, Yb ２ Fe ３ O ７ YbFeFe alloys have the following structures: ２ O ４ Type structure or Yb ２ Fe ３ O ７ An example of a crystal having a crystalline structure is IGZO. It should be noted that a single crystal film of indium oxide can be formed not only on a YSZ substrate but also on an insulating film. On the other hand, it is difficult to form a single crystal film of silicon on an insulating film. Silicon crystals have a diamond structure. As such, indium oxide and silicon have similar properties in terms of single crystal. However, when comparing indium oxide and silicon in terms of whether they can be formed as single crystals on an insulating film, they have different properties.

[0382] This embodiment mode can be implemented by appropriately combining at least a part thereof with other embodiment modes described in this specification.

[0383] Embodiment 4 In this embodiment, a semiconductor device 900 according to one embodiment of the present invention, which is different from the above embodiment, will be described. The semiconductor device 900 can function as a memory device.

[0384] Fig. 28 is a block diagram showing a configuration example of a semiconductor device 900. The semiconductor device 900 shown in Fig. 28 has a driver circuit 910 and a memory array 920. The memory array 920 has one or more memory cells 950. Fig. 28 shows an example in which the memory array 920 has a plurality of memory cells 950 arranged in a matrix.

[0385] The memory cell 15 exemplified in the above embodiment can be applied to the memory cell 950 .

[0386] The drive circuit 910 includes a PSW 931 (power switch), a PSW 932, and a peripheral circuit 915. The peripheral circuit 915 includes a peripheral circuit 911, a control circuit 912, and a voltage generation circuit 928.

[0387] In the semiconductor device 900, each circuit, signal, and voltage can be appropriately selected or omitted as needed. Alternatively, other circuits or signals may be added. The signals BW, CE, GW, CLK, WAKE, ADDR, WDA, PON1, and PON2 are input signals from the outside, and the signal RDA is an output signal to the outside. The signal CLK is a clock signal.

[0388] Furthermore, signals BW, CE, and GW are control signals. Signal CE is a chip enable signal, signal GW is a global write enable signal, and signal BW is a byte write enable signal. Signal ADDR is an address signal. Signal WDA is a write data signal, and signal RDA is a read data signal. Signals PON1 and PON2 are power gating control signals. Note that signals PON1 and PON2 may be generated by the control circuit 912.

[0389] The control circuit 912 is a logic circuit having a function of controlling the overall operation of the semiconductor device 900. For example, the control circuit 912 performs a logical operation on the signals CE, GW, and BW to determine the operation mode (e.g., write operation, read operation) of the semiconductor device 900. Alternatively, the control circuit 912 generates a control signal for the peripheral circuit 911 so that this operation mode is executed.

[0390] The voltage generating circuit 928 has a function of generating a negative voltage. The signal WAKE has a function of controlling the input of the signal CLK to the voltage generating circuit 928. For example, when an H-level signal is given as the signal WAKE, the signal CLK is input to the voltage generating circuit 928, and the voltage generating circuit 928 generates a negative voltage.

[0391] The peripheral circuit 911 is a circuit for writing and reading data to and from the memory cells 950. The peripheral circuit 911 includes a row decoder 941, a column decoder 942, a row driver 923, a column driver 924, an input circuit 925, an output circuit 926, and a sense amplifier 927.

[0392] The row decoder 941 and the column decoder 942 have the function of decoding the signal ADDR. The row decoder 941 is a circuit for specifying a row to be accessed, and the column decoder 942 is a circuit for specifying a column to be accessed. The row driver 923 has the function of selecting the row specified by the row decoder 941. The column driver 924 has the function of writing data to the memory cells 950, reading data from the memory cells 950, and retaining the read data.

[0393] The input circuit 925 has a function of holding a signal WDA. The data held by the input circuit 925 is output to the column driver 924. The output data of the input circuit 925 is data (Din) to be written to the memory cell 950. The data (Dout) read from the memory cell 950 by the column driver 924 is output to the output circuit 926. The output circuit 926 has a function of holding Dout. In addition, the output circuit 926 has a function of outputting Dout to the outside of the semiconductor device 900. The data output from the output circuit 926 is a signal RDA.

[0394] The PSW 931 has a function of controlling the supply of VDD to the peripheral circuit 915. The PSW 932 has a function of controlling the supply of VHM to the row driver 923. In this example, the high power supply voltage of the semiconductor device 900 is VDD, and the low power supply voltage is GND (ground potential). VHM is a high power supply voltage used to set the word line to a high level and is higher than VDD. The on / off of the PSW 931 is controlled by a signal PON1, and the on / off of the PSW 932 is controlled by a signal PON2. In FIG. 28, the number of power domains to which VDD is supplied in the peripheral circuit 915 is one, but multiple domains may also be used. In this case, it is preferable to provide a power switch for each power domain.

[0395] 29A to 29H, other examples of memory cell configurations that can be applied to the memory cell 950 will be described.

[0396] In the following, when two components are described as being connected, this includes being electrically connected via a circuit element (such as a transistor, a switch, a diode, or a resistor). Electrical connection means that a current can flow between the two components. Note that when two components are connected via a switch or a transistor, this is also included in the term "electrical connection," because a current can flow when these are in the on state.

[0397] 29A shows an example of a circuit configuration of a memory cell of a dynamic random access memory (DRAM). In this specification and the like, a DRAM using an OS transistor is referred to as a dynamic oxide semiconductor random access memory (DOSRAM). The memory cell 951 includes a transistor M1 and a capacitor CA.

[0398] The transistor M1 may have a front gate (sometimes simply referred to as a gate) and a back gate. In this case, the back gate may be connected to a wiring that supplies a constant potential or a signal, or the front gate and the back gate may be connected to each other.

[0399] A first terminal of the transistor M1 is connected to a first terminal of the capacitance element CA, a second terminal of the transistor M1 is connected to the wiring BIL, and a gate of the transistor M1 is connected to the wiring WOL. The second terminal of the capacitance element CA is connected to the wiring CAL.

[0400] The wiring BIL functions as a bit line, and the wiring WOL functions as a word line. The wiring CAL functions as a wiring for applying a predetermined potential to the second terminal of the capacitance element CA. When writing and reading data, it is preferable to apply a low-level potential (sometimes referred to as a reference potential) to the wiring CAL.

[0401] Data is written and read by applying a high-level potential to the wiring WOL, turning on the transistor M1, and bringing the wiring BIL and the first terminal of the capacitor CA into a conductive state (a state in which current can flow).

[0402] Furthermore, the memory cell that can be used as the memory cell 950 is not limited to the memory cell 951, and the circuit configuration can be changed. For example, the memory cell 950 can have the configuration of a memory cell 952 as shown in FIG. 29B . The memory cell 952 is an example in which the memory cell 952 does not include a capacitor CA and a wiring CAL. The first terminal of the transistor M1 is in an electrically floating state.

[0403] In the memory cell 952, the potential written through the transistor M1 is held in a capacitance (also referred to as a parasitic capacitance) between the first terminal and the gate, which is indicated by a dashed line. With this configuration, the configuration of the memory cell can be significantly simplified.

[0404] Note that an OS transistor is preferably used as the transistor M1. An OS transistor has a characteristic of extremely low off-state current. By using an OS transistor as the transistor M1, the leakage current of the transistor M1 can be significantly reduced. That is, written data can be held by the transistor M1 for a long time, so that the frequency of refreshing the memory cell can be reduced. Alternatively, the refresh operation of the memory cell can be eliminated. Furthermore, because the leakage current is extremely low, multilevel data or analog data can be held in the memory cell 951 and the memory cell 952.

[0405] 29C shows an example circuit configuration of a gain cell type memory cell having two transistors and one capacitor. The memory cell 953 includes a transistor M2, a transistor M3, and a capacitor CB. In this specification and the like, a storage device having a gain cell type memory cell in which the transistor M2 is an OS transistor is referred to as a nonvolatile oxide semiconductor RAM (NOSRAM).

[0406] The first terminal of transistor M2 is connected to the first terminal of capacitance element CB, the second terminal of transistor M2 is connected to wiring WBL, and the gate of transistor M2 is connected to wiring WOL. The second terminal of capacitance element CB is connected to wiring CAL. The first terminal of transistor M3 is connected to wiring RBL, the second terminal of transistor M3 is connected to wiring SL, and the gate of transistor M3 is connected to the first terminal of capacitance element CB.

[0407] The wiring WBL functions as a write bit line, the wiring RBL functions as a read bit line, and the wiring WOL functions as a word line. The wiring CAL functions as a wiring for applying a predetermined potential to the second terminal of the capacitance element CB. When writing data, while retaining data, and when reading data, it is preferable to apply a low-level potential (sometimes referred to as a reference potential) to the wiring CAL.

[0408] Data is written by applying a high-level potential to the wiring WOL, turning on the transistor M2, and establishing electrical continuity between the wiring WBL and the first terminal of the capacitor CB. Specifically, when the transistor M2 is on, a potential corresponding to the information to be recorded is applied to the wiring WBL, and the potential is written to the first terminal of the capacitor CB and the gate of the transistor M3. Then, a low-level potential is applied to the wiring WOL, turning off the transistor M2, thereby maintaining the potential of the first terminal of the capacitor CB and the potential of the gate of the transistor M3.

[0409] Data is read by applying a predetermined potential to the wiring SL. The current flowing between the source and drain of the transistor M3 and the potential of the first terminal of the transistor M3 are determined by the potential of the gate of the transistor M3 and the potential of the second terminal of the transistor M3. Therefore, the potential held in the first terminal of the capacitor CB (or the gate of the transistor M3) can be read by reading the potential of the wiring RBL connected to the first terminal of the transistor M3. In other words, information written in this memory cell can be read from the potential held in the first terminal of the capacitor CB (or the gate of the transistor M3).

[0410] Alternatively, for example, the wiring WBL and the wiring RBL may be combined into a single wiring BIL. An example circuit configuration of such a memory cell is shown in Figure 29D. The memory cell 954 is configured such that the wiring WBL and the wiring RBL of the memory cell 953 are combined into a single wiring BIL, and the second terminal of the transistor M2 and the first terminal of the transistor M3 are connected to the wiring BIL. In other words, the memory cell 954 is configured to operate as a write bit line and a read bit line using a single wiring BIL.

[0411] 29E is an example in which the capacitor element CB and the wiring CAL are omitted from the memory cell 953. Also, the memory cell 956 shown in Fig. 29F is an example in which the capacitor element CB and the wiring CAL are omitted from the memory cell 954. With such a configuration, the integration degree of the memory cells can be increased.

[0412] Note that at least the transistor M2 is preferably an OS transistor, and in particular, the transistors M2 and M3 are preferably OS transistors.

[0413] Since the OS transistor has an extremely low off-state current, written data can be held by the transistor M2 for a long time, which reduces the frequency of refreshing the memory cell. Alternatively, the refresh operation of the memory cell can be eliminated. Furthermore, since the leakage current is extremely low, multilevel data or analog data can be held in the memory cell 953, the memory cell 954, the memory cell 955, and the memory cell 956.

[0414] The memory cell 953, the memory cell 954, the memory cell 955, and the memory cell 956, in which an OS transistor is used as the transistor M2, are one embodiment of an NOSRAM.

[0415] Note that a Si transistor may be used as the transistor M3. The Si transistor can increase the field effect mobility and can also be used as a p-channel transistor, thereby increasing the degree of freedom in circuit design.

[0416] When an OS transistor is used as the transistor M3, the memory cell can be configured using only n-channel transistors.

[0417] 29G shows a three-transistor, one-capacitor gain cell type memory cell 957. The memory cell 957 has transistors M4 to M6 and a capacitative element CC.

[0418] The first terminal of transistor M4 is connected to the first terminal of capacitor CC, the second terminal of transistor M4 is connected to wiring BIL, and the gate of transistor M4 is connected to wiring WOL. The second terminal of capacitor CC is connected to the first terminal of transistor M5 and wiring GNDL. The second terminal of transistor M5 is connected to the first terminal of transistor M6, and the gate of transistor M5 is connected to the first terminal of capacitor CC. The second terminal of transistor M6 is connected to wiring BIL, and the gate of transistor M6 is connected to wiring RWL.

[0419] The wiring BIL functions as a bit line, the wiring WOL functions as a write word line, and the wiring RWL functions as a read word line. The wiring GNDL is a wiring that applies a low-level potential.

[0420] Data is written by applying a high-level potential to the wiring WOL, turning on the transistor M4, and establishing electrical continuity between the wiring BIL and the first terminal of the capacitor CC. Specifically, when the transistor M4 is on, a potential corresponding to the information to be recorded is applied to the wiring BIL, and the potential is written to the first terminal of the capacitor CC and the gate of the transistor M5. Then, a low-level potential is applied to the wiring WOL, turning off the transistor M4, thereby maintaining the potential of the first terminal of the capacitor CC and the potential of the gate of the transistor M5.

[0421] Data is read by precharging the wiring BIL to a predetermined potential, then electrically floating the wiring BIL, and applying a high-level potential to the wiring RWL. Because the wiring RWL is at a high-level potential, the transistor M6 is turned on, and the wiring BIL and the second terminal of the transistor M5 are electrically connected. At this time, the potential of the wiring BIL is applied to the second terminal of the transistor M5. The potential of the second terminal of the transistor M5 and the potential of the wiring BIL change depending on the potential held in the first terminal of the capacitor CC (or the gate of the transistor M5). By reading the potential of the wiring BIL, the potential held in the first terminal of the capacitor CC (or the gate of the transistor M5) can be read. In other words, information written in this memory cell can be read from the potential held in the first terminal of the capacitor CC (or the gate of the transistor M5).

[0422] Note that at least the transistor M4 is preferably an OS transistor.

[0423] Note that Si transistors may be used as the transistors M5 and M6. As described above, Si transistors may have higher field-effect mobility than OS transistors depending on the crystalline state of silicon used in the semiconductor layer.

[0424] When OS transistors are used as the transistors M5 and M6, the memory cell can be configured using only n-channel transistors.

[0425] 29H shows an example of an SRAM (Static Random Access Memory) using an OS transistor. In this specification and the like, an SRAM using an OS transistor is referred to as an OS-SRAM (Oxide Semiconductor-SRAM). Note that a memory cell 958 shown in FIG. 29H is a memory cell of an SRAM capable of backing up data.

[0426] The memory cell 958 includes transistors M7 to M10, transistors MS1 to MS4, and capacitors CD1 and CD2. Note that the transistors MS1 and MS2 are p-channel transistors, and the transistors MS3 and MS4 are n-channel transistors.

[0427] A first terminal of transistor M7 is connected to wiring BIL, and a second terminal of transistor M7 is connected to a first terminal of transistor MS1, a first terminal of transistor MS3, the gate of transistor MS2, the gate of transistor MS4, and a first terminal of transistor M10. The gate of transistor M7 is connected to wiring WOL. A first terminal of transistor M8 is connected to wiring BILB, and a second terminal of transistor M8 is connected to a first terminal of transistor MS2, the first terminal of transistor MS4, the gate of transistor MS1, the gate of transistor MS3, and a first terminal of transistor M9. The gate of transistor M8 is connected to wiring WOL.

[0428] A second terminal of the transistor MS1 is connected to the wiring VDL. A second terminal of the transistor MS2 is connected to the wiring VDL. A second terminal of the transistor MS3 is connected to the wiring GNDL. A second terminal of the transistor MS4 is connected to the wiring GNDL.

[0429] A second terminal of the transistor M9 is connected to a first terminal of the capacitor CD1, and a gate of the transistor M9 is connected to the wiring BRL. A second terminal of the transistor M10 is connected to a first terminal of the capacitor CD2, and a gate of the transistor M10 is connected to the wiring BRL.

[0430] A second terminal of the capacitance element CD1 is connected to the wiring GNDL, and a second terminal of the capacitance element CD2 is connected to the wiring GNDL.

[0431] The wirings BIL and BILB function as bit lines, the wiring WOL functions as a word line, and the wiring BRL is a wiring that controls the on / off states of the transistors M9 and M10.

[0432] The wiring VDL is a wiring that applies a high-level potential, and the wiring GNDL is a wiring that applies a low-level potential.

[0433] Data is written by applying a high-level potential to the wiring WOL and a high-level potential to the wiring BRL. Specifically, when the transistor M10 is on, a potential corresponding to information to be written is applied to the wiring BIL, and the potential is written to the second terminal of the transistor M10.

[0434] Since the memory cell 958 includes an inverter loop formed by the transistors MS1 and MS2, an inverted signal of the data signal corresponding to the potential is input to the second terminal of the transistor M8. Because the transistor M8 is on, the potential applied to the wiring BIL, i.e., the inverted signal of the signal input to the wiring BIL, is output to the wiring BILB. Because the transistors M9 and M10 are on, the potentials of the second terminals of the transistors M7 and M8 are held in the first terminals of the capacitors CD2 and CD1, respectively. Then, a low-level potential is applied to the wiring WOL and a low-level potential is applied to the wiring BRL to turn off the transistors M7 to M10, thereby holding the potentials of the first terminals of the capacitors CD1 and CD2.

[0435] Data reading will now be described. First, the wirings BIL and BILB are precharged to a predetermined potential. Next, a high-level potential is applied to the wiring WOL, and a high-level potential is applied to the wiring BRL. At this time, the potential of the first terminal of the capacitor CD1 is refreshed by the inverter loop of the memory cell 958 and output to the wiring BILB. The potential of the first terminal of the capacitor CD2 is refreshed by the inverter loop of the memory cell 958 and output to the wiring BIL. The potentials of the wirings BIL and BILB change from the precharged potentials to the potentials of the first terminals of the capacitor CD2 and the first terminals of the capacitor CD1, respectively, so that the potential held in the memory cell can be read from the potential of the wiring BIL or the wiring BILB.

[0436] Note that OS transistors are preferably used as the transistors M7 to M10. This allows written data to be held by the transistors M7 to M10 for a long time, which reduces the frequency of refreshing the memory cells. Alternatively, refreshing the memory cells can be eliminated.

[0437] Note that Si transistors may be used as the transistors MS1 to MS4.

[0438] The driver circuit 910 and memory array 920 of the semiconductor device 900 may be provided on the same plane. Alternatively, as shown in FIG. 30A, the driver circuit 910 and memory array 920 may be provided overlapping each other. By providing the driver circuit 910 and memory array 920 overlapping each other, the signal propagation distance can be shortened. Alternatively, as shown in FIG. 30B, the memory array 920 may be provided in multiple layers on the driver circuit 910.

[0439] Next, an example of a processing unit that can include a semiconductor device such as the memory device will be described.

[0440] 31 shows a block diagram of the arithmetic device 960. The arithmetic device 960 shown in FIG. 31 can be applied to, for example, a CPU. The arithmetic device 960 can also be applied to processors such as a GPU (Graphics Processing Unit), a TPU (Tensor Processing Unit), and an NPU (Neural Processing Unit) that have a larger number (several tens to several hundreds) of processor cores capable of parallel processing than a CPU.

[0441] The arithmetic device 960 shown in FIG. 31 has an ALU 991 (ALU: Arithmetic logic unit, arithmetic circuit), an ALU controller 992, an instruction decoder 993, an interrupt controller 994, a timing controller 995, a register 996, a register controller 997, a bus interface 998, a cache 999, and a cache interface 989 on a substrate 990. The substrate 990 may be a semiconductor substrate, an SOI substrate, a glass substrate, or the like. It may also have a rewritable ROM and a ROM interface. The cache 999 and the cache interface 989 may also be provided on separate chips.

[0442] The cache 999 is connected to a main memory provided on a separate chip via a cache interface 989. The cache interface 989 has a function of supplying part of the data held in the main memory to the cache 999. The cache interface 989 also has a function of outputting part of the data held in the cache 999 to the ALU 991, register 996, etc. via the bus interface 998.

[0443] As will be described later, a memory array 920 can be provided by stacking it on the arithmetic unit 960. The memory array 920 can be used as a cache. In this case, the cache interface 989 may have a function of supplying data held in the memory array 920 to the cache 999. In this case, it is preferable that a drive circuit 910 be included as part of the cache interface 989.

[0444] It is also possible to use only the memory array 920 as a cache without providing the cache 999 .

[0445] The arithmetic device 960 shown in FIG. 31 is merely an example of a simplified configuration, and actual arithmetic devices 960 have a wide variety of configurations depending on their applications. For example, it is preferable to use a configuration including the arithmetic device 960 shown in FIG. 31 as one core, and to include multiple such cores, each of which operates in parallel, in a so-called multi-core configuration. The greater the number of cores, the higher the computational performance. The greater the number of cores, for example, two, preferably four, more preferably eight, even more preferably twelve, and even more preferably sixteen or more. Furthermore, when extremely high computational performance is required, such as for server applications, a multi-core configuration having 16 or more, preferably 32 or more, and even more preferably 64 or more cores is preferable. Furthermore, the number of bits that the arithmetic device 960 can handle in its internal computation circuit, data bus, etc. can be, for example, 8 bits, 16 bits, 32 bits, 64 bits, etc.

[0446] An instruction input to the arithmetic unit 960 via the bus interface 998 is input to the instruction decoder 993, decoded, and then input to the ALU controller 992, interrupt controller 994, register controller 997, and timing controller 995.

[0447] The ALU controller 992, interrupt controller 994, register controller 997, and timing controller 995 perform various controls based on the decoded instructions. Specifically, the ALU controller 992 generates signals for controlling the operation of the ALU 991. Furthermore, the interrupt controller 994 determines and processes interrupt requests from external input / output devices, peripheral circuits, etc. based on their priority, mask status, etc. while the arithmetic unit 960 is executing a program. The register controller 997 generates addresses for registers 996 and performs read and write operations on the registers 996 depending on the state of the arithmetic unit 960.

[0448] Furthermore, the timing controller 995 generates signals that control the timing of the operations of the ALU 991, the ALU controller 992, the instruction decoder 993, the interrupt controller 994, and the register controller 997. For example, the timing controller 995 includes an internal clock generation unit that generates an internal clock signal based on a reference clock signal, and supplies the internal clock signal to the various circuits described above.

[0449] In the arithmetic unit 960 shown in FIG. 31 , a register controller 997 selects a holding operation in a register 996 in accordance with an instruction from the ALU 991. That is, it selects whether data is to be held by a flip-flop or by a capacitive element in the memory cell of the register 996. If holding data by a flip-flop is selected, a power supply voltage is supplied to the memory cell in the register 996. If holding data in a capacitive element is selected, the data is rewritten to the capacitive element, and the supply of power supply voltage to the memory cell in the register 996 can be stopped.

[0450] The memory array 920 and the arithmetic unit 960 can be provided overlapping each other. Perspective views of a semiconductor device 970A are shown in Figures 32A and 32B. The semiconductor device 970A has a layer 930 on which memory arrays are provided above the arithmetic unit 960. The layer 930 is provided with memory arrays 920L1, 920L2, and 920L3. The arithmetic unit 960 and each memory array have overlapping regions. To make the configuration of the semiconductor device 970A easier to understand, the arithmetic unit 960 and the layer 930 are shown separately in Figure 32B.

[0451] By stacking the layer 930 having the memory array and the arithmetic unit 960, the connection distance between them can be shortened, thereby increasing the communication speed between them. In addition, the short connection distance reduces power consumption.

[0452] As a method for stacking the layer 930 having a memory array and the arithmetic device 960, a method (also called monolithic stacking) in which the layer 930 having a memory array is stacked directly on the arithmetic device 960 may be used, or a method in which the arithmetic device 960 and the layer 930 are formed on different substrates, and the two substrates are bonded together and connected using a through-via or conductive film bonding technology (such as Cu-Cu bonding) may be used. The former method does not require consideration of misalignment during bonding, and therefore can not only reduce the chip size but also reduce manufacturing costs.

[0453] Here, the arithmetic unit 960 does not have a cache 999, and the memory arrays 920L1, 920L2, and 920L3 provided in the layer 930 can each be used as a cache. In this case, for example, the memory array 920L1 can be used as an L1 cache (also referred to as a level 1 cache), the memory array 920L2 can be used as an L2 cache (also referred to as a level 2 cache), and the memory array 920L3 can be used as an L3 cache (also referred to as a level 3 cache). Of the three memory arrays, the memory array 920L3 has the largest capacity and the lowest access frequency. Furthermore, the memory array 920L1 has the smallest capacity and the highest access frequency.

[0454] When the cache 999 provided in the arithmetic unit 960 is used as an L1 cache, each memory array provided in the layer 930 can be used as a lower-level cache or a main memory. The main memory has a larger capacity than the cache and is accessed less frequently.

[0455] 32B, a driving circuit 910L1, a driving circuit 910L2, and a driving circuit 910L3 are provided. The driving circuit 910L1 is connected to the memory array 920L1 via a connection electrode 940L1. Similarly, the driving circuit 910L2 is connected to the memory array 920L2 via a connection electrode 940L2, and the driving circuit 910L3 is connected to the memory array 920L3 via a connection electrode 940L3.

[0456] Although the number of memory arrays functioning as caches is three in this example, the number may be one or two, or four or more.

[0457] When the memory array 920L1 is used as a cache, the driver circuit 910L1 may function as part of the cache interface 989, or may be configured to be connected to the cache interface 989. Similarly, the driver circuits 910L2 and 910L3 may also function as part of the cache interface 989, or may be configured to be connected thereto.

[0458] Whether the memory array 920 is made to function as a cache or as a main memory is determined by a control circuit 912 included in each drive circuit 910. The control circuit 912 can cause some of the memory cells 950 included in the semiconductor device 900 to function as RAM based on a signal supplied from the arithmetic device 960.

[0459] The semiconductor device 900 can cause some of the memory cells 950 to function as a cache and the other memory cells to function as a main memory. That is, the semiconductor device 900 can function as both a cache and a main memory. The semiconductor device 900 according to one embodiment of the present invention can function as, for example, a universal memory.

[0460] Furthermore, a layer 930 having one memory array 920 may be provided over the arithmetic device 960. Figure 33A shows a perspective view of a semiconductor device 970B.

[0461] In the semiconductor device 970B, one memory array 920 can be divided into multiple areas, each of which can be used for a different function. Figure 33A shows an example in which area L1 is used as an L1 cache, area L2 is used as an L2 cache, and area L3 is used as an L3 cache.

[0462] Furthermore, in the semiconductor device 970B, the capacity of each of the areas L1 to L3 can be changed depending on the situation. For example, if it is desired to increase the capacity of the L1 cache, this can be achieved by increasing the area of ​​the area L1. This configuration can improve the efficiency of calculation processing and increase the processing speed.

[0463] Also, multiple memory arrays may be stacked. Figure 33B shows a perspective view of a semiconductor device 970C.

[0464] The semiconductor device 970C includes a layer 930L1 having a memory array 920L1, a layer 930L2 having a memory array 920L2 on top of that, and a layer 930L3 having a memory array 920L3 on top of that. The memory array 920L1, which is physically closest to the arithmetic unit 960, can be used as a higher-level cache, and the memory array 920L3, which is farthest, can be used as a lower-level cache or main memory. This configuration allows the capacity of each memory array to be increased, thereby further improving processing power.

[0465] This embodiment mode can be implemented by appropriately combining at least a part thereof with other embodiment modes described in this specification.

[0466] Embodiment 5 In this embodiment, an application example of a semiconductor device of one embodiment of the present invention will be described. The semiconductor device of one embodiment of the present invention can be used for, for example, electronic components, electronic devices, mainframes, space equipment, and data centers (also referred to as data centers (DCs)). Electronic components, electronic devices, mainframes, space equipment, and data centers using the semiconductor device of one embodiment of the present invention are effective in achieving high performance, such as low power consumption.

[0467] [Electronic Component] FIG. 34A shows a perspective view of a substrate (mounting substrate 704) on which electronic component 700 is mounted. Electronic component 700 shown in FIG. 34A has semiconductor device 710 inside mold 711. FIG. 34A omits some parts to show the interior of electronic component 700. Electronic component 700 has lands 712 on the outside of mold 711. Lands 712 are electrically connected to electrode pads 713, and electrode pads 713 are electrically connected to semiconductor device 710 via wires 714. Electronic component 700 is mounted on, for example, a printed circuit board 702. A plurality of such electronic components are combined and electrically connected on printed circuit board 702 to complete mounting substrate 704.

[0468] The semiconductor device 710 also includes a drive circuit layer 715 and a memory layer 716. The memory layer 716 has a configuration in which multiple memory cell arrays are stacked. The stacked configuration of the drive circuit layer 715 and the memory layer 716 can be a monolithic stacked configuration. In a monolithic stacked configuration, the layers can be connected without using through-electrode technology such as a TSV (Through Silicon Via) or a bonding technology such as Cu-Cu direct bonding. By configuring the drive circuit layer 715 and the memory layer 716 as a monolithic stacked configuration, for example, a so-called on-chip memory configuration can be achieved in which the memory is formed directly on the processor. The on-chip memory configuration enables the operation of the interface between the processor and the memory to be faster.

[0469] Furthermore, by configuring an on-chip memory, the size of the connection wiring can be reduced compared to technologies that use through electrodes such as TSVs, and the number of connection pins can be increased. Increasing the number of connection pins enables parallel operation, which makes it possible to improve the memory bandwidth (also called memory bandwidth).

[0470] It is also preferable that the memory cell arrays included in the memory layer 716 are formed using OS transistors and the memory cell arrays are monolithically stacked. By forming the memory cell arrays in a monolithic stacked structure, one or both of the memory bandwidth and the memory access latency can be improved. Note that the bandwidth is the amount of data transferred per unit time, and the access latency is the time from access to the start of data exchange. Note that when Si transistors are used for the memory layer 716, it is more difficult to form a monolithic stacked structure than when OS transistors are used. Therefore, it can be said that OS transistors have a superior structure to Si transistors in a monolithic stacked structure.

[0471] The semiconductor device 710 may also be referred to as a die. In this specification, a die refers to a chip piece obtained by forming a circuit pattern on, for example, a disk-shaped substrate (also called a wafer) and dicing it into cubes during the semiconductor chip manufacturing process. Examples of semiconductor materials that can be used for the die include silicon (Si), silicon carbide (SiC), and gallium nitride (GaN). For example, a die obtained from a silicon substrate (also called a silicon wafer) may be called a silicon die.

[0472] 34B shows a perspective view of electronic component 730. Electronic component 730 is an example of a SiP (System in Package) or MCM (Multi-Chip Module). Electronic component 730 has an interposer 731 provided on a package substrate 732 (printed circuit board), and a semiconductor device 735 and a plurality of semiconductor devices 710 provided on interposer 731.

[0473] The electronic component 730 shows an example in which the semiconductor device 710 is used as a high bandwidth memory (HBM). The semiconductor device 735 can be used in an integrated circuit such as a CPU, a GPU, an NPU, or an FPGA (Field Programmable Gate Array).

[0474] For example, a ceramic substrate, a plastic substrate, or a glass epoxy substrate can be used as the package substrate 732. For example, a silicon interposer or a resin interposer can be used as the interposer 731.

[0475] The interposer 731 has multiple wirings and functions to electrically connect multiple integrated circuits with different terminal pitches. The multiple wirings are provided in a single layer or multiple layers. The interposer 731 also functions to electrically connect the integrated circuits provided on the interposer 731 to electrodes provided on the package substrate 732. For these reasons, the interposer is sometimes called a "rewiring substrate" or "intermediate substrate." In addition, through electrodes may be provided in the interposer 731, and the integrated circuits and the package substrate 732 may be electrically connected using the through electrodes. In addition, with a silicon interposer, a TSV may also be used as the through electrode.

[0476] In an HBM, many wirings must be connected to achieve a wide memory bandwidth. Therefore, the interposer on which the HBM is mounted must have fine and high-density wiring. Therefore, it is preferable to use a silicon interposer for the interposer on which the HBM is mounted.

[0477] Furthermore, in SiPs, MCMs, and the like that use silicon interposers, a decrease in reliability due to differences in the coefficient of expansion between the integrated circuit and the interposer is unlikely to occur. Furthermore, because the silicon interposer has a highly flat surface, poor connection between the integrated circuit mounted on the silicon interposer and the silicon interposer is unlikely to occur. In particular, it is preferable to use silicon interposers in 2.5D packages (2.5-dimensional packaging) in which multiple integrated circuits are arranged horizontally on an interposer.

[0478] On the other hand, when electrically connecting multiple integrated circuits with different terminal pitches using a silicon interposer, a TSV, or the like, a space is required, such as the width of the terminal pitch. Therefore, when attempting to reduce the size of the electronic component 730, the width of the terminal pitch becomes an issue, and it may be difficult to provide the many wirings necessary to achieve a wide memory bandwidth. Therefore, as described above, a monolithic stacked structure using OS transistors is preferable. A composite structure may be formed by combining a memory cell array stacked using TSVs and a monolithically stacked memory cell array.

[0479] A heat sink (heat dissipation plate) may be provided overlapping the electronic component 730. When a heat sink is provided, it is preferable to align the height of an integrated circuit provided on the interposer 731. For example, in the electronic component 730 shown in this embodiment, it is preferable to align the height of the semiconductor device 710 and the height of the semiconductor device 735.

[0480] Electrodes 733 may be provided on the bottom of package substrate 732 in order to mount electronic component 730 on another substrate. FIG. 34B shows an example in which electrodes 733 are formed with solder balls. By providing solder balls in a matrix on the bottom of package substrate 732, BGA (Ball Grid Array) mounting can be achieved. Electrodes 733 may also be formed with conductive pins. By providing conductive pins in a matrix on the bottom of package substrate 732, PGA (Pin Grid Array) mounting can be achieved.

[0481] The electronic component 730 can be mounted on other substrates using various mounting methods, including, but not limited to, BGA and PGA, such as a staggered pin grid array (SPGA), a land grid array (LGA), a quad flat package (QFP), a quad flat J-leaded package (QFJ), and a quad flat non-leaded package (QFN).

[0482] 35A shows a perspective view of a mainframe computer 5600. The mainframe computer 5600 has a rack 5610 housing a plurality of rack-mounted computers 5620. The mainframe computer 5600 may also be called a supercomputer.

[0483] 35B shows a perspective view of an example of a computer 5620. The computer 5620 has a motherboard 5630. The motherboard 5630 is provided with a plurality of slots 5631 and a plurality of connection terminals. A PC card 5621 is inserted into the slot 5631. In addition, the PC card 5621 has connection terminals 5623, 5624, and 5625, which are each connected to the motherboard 5630.

[0484] Fig. 35C shows an example of a PC card 5621. The PC card 5621 is a processing board equipped with, for example, a CPU, a GPU, a storage device, etc. The PC card 5621 has a board 5622 and connection terminals 5623, 5624, 5625, electronic components 5626, 5627, 5628, and 5629 mounted on the board 5622. Note that Fig. 35C illustrates components other than electronic components 5626, 5627, and 5628.

[0485] The connection terminal 5629 has a shape that allows it to be inserted into a slot 5631 of the motherboard 5630, and the connection terminal 5629 functions as an interface for connecting the PC card 5621 and the motherboard 5630. An example of the standard for the connection terminal 5629 is PCIe.

[0486] The connection terminals 5623, 5624, and 5625 can be, for example, interfaces for supplying power to the PC card 5621, inputting signals, etc. Furthermore, they can be, for example, interfaces for outputting signals calculated by the PC card 5621. Examples of standards for the connection terminals 5623, 5624, and 5625 include USB (Universal Serial Bus), SATA (Serial ATA), and SCSI (Small Computer System Interface). Furthermore, when a video signal is output from the connection terminals 5623, 5624, and 5625, examples of the respective standards include HDMI (registered trademark).

[0487] The electronic component 5626 has a terminal (not shown) for inputting and outputting signals, and the electronic component 5626 and the board 5622 can be electrically connected by inserting the terminal into a socket (not shown) provided on the board 5622.

[0488] The electronic components 5627 and 5628 have multiple terminals, and can be mounted on wiring provided on the board 5622 by, for example, reflow soldering the terminals. Examples of the electronic component 5627 include an FPGA, a GPU, and a CPU. For example, the electronic component 730 can be used as the electronic component 5627. For example, the electronic component 5628 includes a storage device. For example, the electronic component 700 can be used as the electronic component 5628.

[0489] The mainframe computer 5600 can also function as a parallel computer. By using the mainframe computer 5600 as a parallel computer, it is possible to perform large-scale calculations required for, for example, learning and inference in artificial intelligence.

[0490] [Space Equipment] The semiconductor device of one embodiment of the present invention can be suitably used in space equipment.

[0491] A semiconductor device according to one embodiment of the present invention includes an OS transistor. The OS transistor exhibits small changes in electrical characteristics due to radiation exposure. That is, the OS transistor has high radiation resistance and can be suitably used in an environment where radiation may be incident. For example, the OS transistor can be suitably used in outer space. Specifically, the OS transistor can be used as a transistor for a semiconductor device provided in a space shuttle, an artificial satellite, or a space probe. Examples of radiation include X-rays and neutrons. Note that outer space refers to an altitude of 100 km or higher, and the outer space described in this specification includes one or more of the thermosphere, the mesosphere, and the stratosphere.

[0492] Fig. 36A shows an artificial satellite 6800 as an example of space equipment. The artificial satellite 6800 has a body 6801, a solar panel 6802, an antenna 6803, a secondary battery 6805, and a control device 6807. Note that Fig. 36A shows a planet 6804 in space as an example.

[0493] 36A , a battery management system (also referred to as a BMS) or a battery control circuit may be provided for the secondary battery 6805. The use of an OS transistor in the battery management system or the battery control circuit is preferable because it consumes low power and has high reliability even in space.

[0494] Furthermore, outer space is an environment with radiation levels 100 times higher than on Earth. Examples of radiation include electromagnetic waves (electromagnetic radiation) such as X-rays and gamma rays, and particle radiation such as alpha rays, beta rays, neutron rays, proton rays, heavy ion rays, and meson rays.

[0495] When sunlight is irradiated onto the solar panel 6802, the power required for the operation of the satellite 6800 is generated. However, for example, in a situation where sunlight is not irradiated onto the solar panel or where the amount of sunlight irradiating the solar panel is small, the generated power is small. Therefore, there is a possibility that the power required for the operation of the satellite 6800 will not be generated. In order to operate the satellite 6800 even in a situation where the generated power is small, it is preferable to provide a secondary battery 6805 on the satellite 6800. Note that the solar panel may be called a solar cell module.

[0496] The satellite 6800 can generate a signal. The signal is transmitted via an antenna 6803, and can be received by, for example, a receiver installed on the ground or another satellite. By receiving the signal transmitted by the satellite 6800, the position of the receiver that received the signal can be determined. As described above, the satellite 6800 can constitute a satellite positioning system.

[0497] The control device 6807 has a function of controlling the satellite 6800. The control device 6807 is configured using, for example, one or more selected from a CPU, a GPU, and a storage device. Note that a semiconductor device including an OS transistor, which is one embodiment of the present invention, is preferably used for the control device 6807. The OS transistor has smaller fluctuations in electrical characteristics due to radiation exposure than a Si transistor. That is, the OS transistor has high reliability even in an environment where radiation may be incident, and can be preferably used.

[0498] The artificial satellite 6800 can also be configured to include a sensor. For example, by including a visible light sensor, the artificial satellite 6800 can have the function of detecting sunlight reflected from an object on the ground. Alternatively, by including a thermal infrared sensor, the artificial satellite 6800 can have the function of detecting thermal infrared rays emitted from the earth's surface. As described above, the artificial satellite 6800 can function as, for example, an earth observation satellite.

[0499] Although an artificial satellite is described as an example of space equipment in this embodiment, the present invention is not limited thereto. For example, the semiconductor device of one embodiment of the present invention can be suitably used in space equipment such as a spaceship, a space capsule, or a space probe.

[0500] As described above, OS transistors have excellent advantages over Si transistors, such as the ability to achieve a wide memory bandwidth and high radiation resistance.

[0501] [Data Center] The semiconductor device of one embodiment of the present invention can be suitably used in a storage system applied to, for example, a data center. The data center is required to perform long-term management of data, such as ensuring data immutability. Managing long-term data requires a large-scale building, such as installing storage and servers for storing a huge amount of data, ensuring a stable power supply for maintaining the data, or ensuring cooling equipment required for maintaining the data.

[0502] By using the semiconductor device of one embodiment of the present invention in a storage system applied to a data center, it is possible to reduce the power required to store data and the size of the semiconductor device that stores data. Therefore, it is possible to reduce the size of the storage system, the size of the power supply for storing data, the scale of the cooling equipment, and the like. Therefore, it is possible to reduce the space required for the data center.

[0503] Furthermore, the semiconductor device of one embodiment of the present invention has low power consumption, which allows heat generation from the circuit to be reduced. Therefore, adverse effects of the heat generation on the circuit itself, peripheral circuits, and modules can be reduced. Furthermore, by using the semiconductor device of one embodiment of the present invention, a data center that operates stably even in a high-temperature environment can be realized. Therefore, the reliability of the data center can be improved.

[0504] Fig. 36B shows a storage system applicable to a data center. The storage system 6000 shown in Fig. 36B has a plurality of servers 6001sb as hosts 6001 (illustrated as Host Computers). It also has a plurality of storage devices 6003md as storage 6003 (illustrated as Storage). The host 6001 and storage 6003 are shown connected via a storage area network 6004 (illustrated as SAN: Storage Area Network) and a storage control circuit 6002 (illustrated as Storage Controller).

[0505] The host 6001 corresponds to a computer that accesses data stored in the storage 6003. The hosts 6001 may be connected to each other via a network.

[0506] Although the storage 6003 uses flash memory to reduce the data access speed, i.e., the time required to store and output data, this time is significantly longer than the time required for DRAM, which can be used as cache memory within the storage. In order to solve the problem of the long access speed of the storage 6003, a storage system typically provides cache memory within the storage to reduce the time required to store and output data.

[0507] The cache memory described above is used in the storage control circuit 6002 and the storage 6003. Data exchanged between the host 6001 and the storage 6003 is stored in the cache memory in the storage control circuit 6002 and the storage 6003, and then output to the host 6001 or the storage 6003.

[0508] By using OS transistors as transistors for storing data in the cache memory and holding a potential corresponding to the data, the frequency of refresh operations can be reduced, and power consumption can be reduced.

[0509] Note that the application of the semiconductor device of one embodiment of the present invention to any one or more selected from electronic components, electronic devices, mainframe computers, space equipment, and data centers is expected to have an effect of reducing power consumption. Therefore, while energy demand is expected to increase with the improvement in performance or high integration of semiconductor devices, the use of the semiconductor device of one embodiment of the present invention can contribute to the reduction of carbon dioxide (CO ２ Furthermore, the semiconductor device of one embodiment of the present invention is effective as a countermeasure against global warming because it consumes low power.

[0510] This embodiment mode can be implemented by appropriately combining at least a part thereof with other embodiment modes described in this specification.

[0511] 10: transistor, 10a: transistor, 10b: transistor, 11: insulating layer, 15: memory cell, 20: slit, 21: semiconductor layer, 21A: region, 21C: region, 21f: semiconductor film, 21gb: grain boundary, 22: insulating layer, 23: conductive layer, 23f: conductive film, 24: conductive layer, 24a: conductive film, 24af: conductive film, 24b: conductive film, 24bf: conductive film, 25: conductive layer, 25a: conductive film, 25af: conductive film, 25b: conductive film, 25bf: conductive film, 26: conductive layer, 27: plug, 29: conductive layer, 30: capacitance element, 30a: capacitance element, 30b: capacitance element, 32: insulating layer, 33: insulating layer, 35: insulating layer, 40: slit, 40a: slit, 41: insulating layer, 41a: insulating layer, 41b: insulating layer, 41c: insulating layer, 42: insulating layer, 43: insulating layer, 44: insulating layer, 44a: insulating layer, 45: insulating layer, 46: insulating layer, 46a: insulating layer, 47: insulating layer, 48: insulating layer, 49: insulating layer, 50: semiconductor device, 51: conductive layer, 51f: conductive film, 52: insulating layer, 53: conductive layer, 55: conductive layer, 80: layer, 81: conductive layer, 82: plug, 83: plug, 84: conductive layer, 85: plug, 86: insulating layer, 87: insulating layer, 88: insulating layer, 8 9: plug, 90: transistor, 91: substrate, 92: semiconductor region, 93: insulating layer, 94: conductive layer, 95a: low resistance region, 95b: low resistance region, 96: insulating layer, 98: element isolation layer, 700: electronic component, 702: printed circuit board, 704: mounting substrate, 710: semiconductor device, 711: mold, 712: land, 713: electrode pad, 714: wire, 715: drive circuit layer, 716: memory layer, 730: electronic component, 731: interposer, 732: package substrate, 733: electrode, 735: semiconductor device, 900: semiconductor device, 910: drive circuit, 911: periphery Circuit, 912: control circuit, 915: peripheral circuit, 920: memory array, 923: row driver, 924: column driver, 925: input circuit, 926: output circuit, 927: sense amplifier, 928: voltage generation circuit, 930: layer, 931: PSW, 932: PSW, 941: row decoder, 942: column decoder, 950: memory cell, 951: memory cell, 952: memory cell, 953: memory cell, 954: memory cell, 955: memory cell, 956: memory cell, 957: memory cell, 958: memory cell, 960: arithmetic unit, 970A: semiconductor device,970B: semiconductor device, 970C: semiconductor device, 989: cache interface, 990: substrate, 991: ALU, 992: ALU controller, 993: instruction decoder, 994: interrupt controller, 995: timing controller, 996: register, 997: register controller, 998: bus interface, 999: cache, 5600: mainframe computer, 5610: rack, 5620: computer, 5621: PC card, 5622: board, 5623: connection terminal Child, 5624: connection terminal, 5625: connection terminal, 5626: electronic component, 5627: electronic component, 5628: electronic component, 5629: connection terminal, 5630: motherboard, 5631: slot, 6000: storage system, 6001: host, 6001sb: server, 6002: storage control circuit, 6003: storage, 6003md: storage device, 6800: artificial satellite, 6801: aircraft, 6802: solar panel, 6803: antenna, 6804: planet, 6805: secondary battery, 6807: control device,

Claims

a first conductive layer, a second conductive layer, a third conductive layer, a semiconductor layer, a first insulating layer, and a second insulating layer; the first insulating layer is located on the first conductive layer and has a slit reaching the first conductive layer; the second conductive layer is located on the first insulating layer; the semiconductor layer has a first portion in contact with the second conductive layer, a second portion along a side surface of the first insulating layer inside the slit, and a third portion in contact with the first conductive layer inside the slit; the second insulating layer covers the semiconductor layer inside the slit; the third conductive layer covers the second insulating layer inside the slit; the first conductive layer and the second conductive layer have different crystallinity; the semiconductor layer has a crystalline region with a continuous crystal orientation across the first portion, the second portion, and the third portion; Semiconductor device. 　 a first conductive layer, a second conductive layer, a third conductive layer, a fourth conductive layer, a semiconductor layer, a first insulating layer, a second insulating layer, a third insulating layer, and a fourth insulating layer; the first insulating layer is located on the first conductive layer and has a first slit reaching the first conductive layer; the second conductive layer is located on the first insulating layer; the semiconductor layer has a first portion in contact with the second conductive layer, a second portion along a side surface of the first insulating layer inside the first slit, and a third portion in contact with the first conductive layer inside the first slit; the second insulating layer covers the semiconductor layer inside the first slit; the third conductive layer covers the second insulating layer inside the first slit; the third insulating layer is located below the first insulating layer and has a second slit; the fourth conductive layer has a portion along a side surface of the third insulating layer inside the second slit, the first conductive layer has a portion located inside the second slit; the fourth insulating layer is located inside the second slit and between the first conductive layer and the fourth conductive layer; the first conductive layer and the second conductive layer have different crystallinity; the semiconductor layer has a crystalline region with a continuous crystal orientation across the first portion, the second portion, and the third portion; Semiconductor device. 　 In claim 1 or claim 2, the semiconductor layer includes an oxide containing indium, the first conductive layer is polycrystalline and includes an oxide containing indium and tin; the second conductive layer is amorphous and includes an oxide containing indium, tin, and silicon; Semiconductor device. 　 In claim 1 or claim 2, the semiconductor layer includes an oxide containing indium, the first conductive layer is amorphous and includes an oxide containing indium, tin, and silicon; the second conductive layer is polycrystalline and includes an oxide containing indium and tin; Semiconductor device. 　 In claim 2, the first slit and the second slit each extend in a first direction; the third conductive layer extends in the first direction within the first slit; the fourth conductive layer extends in the first direction within the second slit; Semiconductor device. 　 In claim 2, the first slit extends in a first direction; the second slit extends in a second direction intersecting the first direction; the third conductive layer extends in the first direction within the first slit; the fourth conductive layer extends in the second direction within the second slit; Semiconductor device. 　 In claim 2, a fifth conductive layer and a connection electrode; the first slit extends in a first direction; the third conductive layer extends in the first direction within the first slit; the fifth conductive layer is located on the third conductive layer and extends in a second direction intersecting the first direction; the connection electrode connects the fifth conductive layer and the second conductive layer; Semiconductor device. 　 In claim 2, a fifth conductive layer; the first slit extends in a first direction; the second conductive layer extends in the first direction; the fifth conductive layer is in contact with the third conductive layer and extends in a second direction intersecting the first direction; Semiconductor device. 　 In claim 2, the first conductive layer has a recess in a region overlapping with the first slit, the semiconductor layer, the second insulating layer, and the third conductive layer each have a bottom portion provided along the recess; Semiconductor device. 　 In claim 2, a sixth conductive layer; the second slit reaches the sixth conductive layer; the fourth conductive layer is in contact with the sixth conductive layer inside the second slit; Semiconductor device. 　 In claim 2, the fourth insulating layer has a film exhibiting ferroelectricity, The ferroelectric film is a film containing hafnium oxide, zirconium oxide, or hafnium zirconium oxide. Semiconductor device. 　 In claim 2, the semiconductor layer, the second insulating layer, and the third conductive layer have planarized upper surfaces; the semiconductor layer contacts a side surface of the second conductive layer; Semiconductor device.

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