Semiconductor device and method for producing semiconductor device

Abstract

Provided is a highly reliable transistor. This semiconductor device includes a transistor and an interlayer film. The transistor has an oxide semiconductor layer as a semiconductor layer. The oxide semiconductor layer has a source region and a drain region of the transistor, and a channel formation region located between the source region and the drain region. The interlayer film has an opening having a region overlapping the oxide semiconductor layer. The opening is provided with a gate insulating layer and a gate electrode. The gate insulating layer has a region in contact with the source region and a region in contact with the drain region. The gate insulating layer has a region located between the oxide semiconductor layer and the interlayer film. The interlayer film has a region located on the gate insulating layer.

Description

Semiconductor device and method for manufacturing the same

[0001] 1. Field of the Invention One embodiment of the present invention relates to a semiconductor device, a memory device, and an electronic device. Another embodiment of the present invention relates to a manufacturing method of a semiconductor device.

[0002] One embodiment of the present invention is not limited to the above technical field, and examples of the technical field of one embodiment of the present invention include semiconductor devices, display devices, light-emitting devices, power storage devices, memory devices, electronic devices, lighting devices, input devices (e.g., touch sensors), input / output devices (e.g., touch panels), driving methods thereof, and manufacturing methods thereof.

[0003] In this specification and the like, a semiconductor device is a device that utilizes semiconductor characteristics, and refers to a circuit including a semiconductor element (transistor, diode, photodiode, etc.), a device having such a circuit, etc. Also, it refers to any device that can function by utilizing semiconductor characteristics. For example, an integrated circuit, a chip including an integrated circuit, and an electronic component in which a chip is housed in a package are examples of semiconductor devices. Furthermore, a memory device, a display device, a light-emitting device, a lighting device, and an electronic device may themselves be semiconductor devices and each may have a semiconductor device.

[0004] A technology for constructing transistors using semiconductor thin films formed on substrates with insulating surfaces has attracted attention. Such transistors are widely used in electronic devices such as integrated circuits (ICs) and display devices. While silicon-based semiconductor materials are widely known as semiconductor materials applicable to transistors, oxide semiconductors have also attracted attention as other materials.

[0005] Furthermore, it is known that a transistor using an oxide semiconductor has an extremely small leakage current in an off state. For example, Patent Document 1 discloses a low-power central processing unit (CPU) that utilizes the low leakage current characteristic of a transistor using an oxide semiconductor. Furthermore, Patent Document 2 discloses a memory device that can retain stored data for a long period of time by utilizing the low leakage current characteristic of a transistor using an oxide semiconductor.

[0006] Examples of oxide semiconductors that can be used for the active layer of a transistor include indium oxide, indium gallium zinc oxide, etc. Non-Patent Document 1 discloses a thin-film transistor that uses hydrogenated polycrystalline indium oxide formed by low-temperature solid-phase crystallization for the active layer.

[0007] JP 2012-257187 A JP 2011-151383 A

[0008] Y. Magari et al., "High-mobility hydrogenated polycrystalline InO(InO:H) thin-film transistors", Nature Communications, 13, 1078 (2022) Takashi Koida, "High-mobility transparent conductive film", National Institute of Advanced Industrial Science and Technology, AIST Photovoltaic Power Generation Research Results Report 2019, Internet <URL: https: / / unit.aist.go.jp / rpd-envene / PV / ja / results / 2019 / oral / T13.pdf>

[0009] An object of one embodiment of the present invention is to provide a transistor with favorable electrical characteristics.An object of one embodiment of the present invention is to provide a transistor with high on-state current.An object of one embodiment of the present invention is to provide a highly reliable transistor, semiconductor device, or memory device.An object of one embodiment of the present invention is to provide a transistor, semiconductor device, or memory device that can be miniaturized or highly integrated.An object of one embodiment of the present invention is to provide a semiconductor device or memory device with low power consumption.An object of one embodiment of the present invention is to provide a memory device with high operating speed.An object of one embodiment of the present invention is to provide a manufacturing method of the transistor, semiconductor device, or memory device.

[0010] Note that the description of these problems does not preclude the existence of other problems. One embodiment of the present invention does not necessarily have to solve all of these problems. Problems other than these can be extracted from the description in the specification, drawings, and claims.

[0011] One embodiment of the present invention provides a transistor and a first insulating layer. The transistor includes an oxide semiconductor layer, a second insulating layer, a first conductive layer, a second conductive layer, and a third conductive layer. The oxide semiconductor layer includes a source region, a drain region, and a channel formation region located between the source region and the drain region. The first insulating layer is located over the oxide semiconductor layer. The first insulating layer has a first opening overlapping with the channel formation region, a second opening overlapping with the source region, and a third opening overlapping with the drain region. The semiconductor device has a second insulating layer located within the first opening, the second insulating layer contacting the source region, the drain region, and a lower surface of the first insulating layer, a first conductive layer located on the second insulating layer within the first opening, a second conductive layer located within the second opening, the second conductive layer contacting the source region, a third conductive layer located within the third opening, the third conductive layer contacting the drain region, and the concentrations of impurity elements in the source region and the drain region are higher than the concentrations of impurity elements in the channel formation region.

[0012] Alternatively, one embodiment of the present invention provides a transistor and a first insulating layer. The transistor includes an oxide semiconductor layer, a second insulating layer, a first conductive layer, a second conductive layer, and a third conductive layer. The oxide semiconductor layer has a source region, a drain region, and a recessed portion located between the source region and the drain region. The oxide semiconductor layer has a channel formation region below the recessed portion. The first insulating layer is located over the oxide semiconductor layer. The first insulating layer has a first opening having a region overlapping with the channel formation region, a second opening having a region overlapping with the source region, and a third opening having a region overlapping with the drain region. The second insulating layer has a first insulating layer in the first opening. and in the recess, the second insulating layer contacts the source region, the drain region, and a lower surface of the first insulating layer, the first conductive layer is located on the second insulating layer in the first opening, the second conductive layer is located in the second opening, the second conductive layer is in contact with the source region, the third conductive layer is located in the third opening, the third conductive layer is in contact with the drain region, the height from a reference plane of the lower surface of the second insulating layer in the region overlapping with the first insulating layer is higher than the height from the reference plane of the lower surface of the second insulating layer in the recess, and the concentrations of impurity elements in the source region and the drain region are higher than the concentrations of impurity elements in the channel formation region.

[0013] Alternatively, in the above aspect, the oxide semiconductor layer may include a first region and a second region, the first region being in contact with a side surface of the source region and a lower surface of the second insulating layer, the second region being in contact with a side surface of the drain region and a lower surface of the second insulating layer, the first region and the second region overlapping with the first insulating layer, the concentration of the impurity element in the first region being lower than the concentration of the impurity element in the source region and higher than the concentration of the impurity element in the channel formation region, and the concentration of the impurity element in the second region being lower than the concentration of the impurity element in the drain region and higher than the concentration of the impurity element in the channel formation region.

[0014] Alternatively, in the above embodiment, the impurity element may be a metal element.

[0015] Alternatively, in the above embodiment, the oxide semiconductor layer may contain indium, and the impurity element may be at least one of titanium, tin, and antimony.

[0016] Alternatively, one embodiment of the present invention includes a first step of forming an oxide semiconductor layer and a first impurity layer located over the oxide semiconductor layer and having a thickness thinner than that of the oxide semiconductor layer; a second step of forming a first insulating layer over the first impurity layer; a third step of processing the first insulating layer and the first impurity layer to form a first opening having a region overlapping with the oxide semiconductor layer in the first insulating layer and forming a second impurity layer and a third impurity layer; a fourth step of forming the second insulating layer so that the second insulating layer has a region located within the first opening, a region in contact with a side surface of the second impurity layer, and a region in contact with a side surface of the third impurity layer; a fifth step of forming a first conductive layer over the second insulating layer; a sixth step of performing heat treatment to form a first region containing an element contained in the second impurity layer in a region of the oxide semiconductor layer overlapping with the second impurity layer and to form a second region containing an element contained in the third impurity layer in a region of the oxide semiconductor layer overlapping with the third impurity layer; a seventh step of forming, in the first insulating layer, a second opening reaching the first region and a third opening reaching the second region; and an eighth step of forming a second conductive layer in the second opening so as to be in contact with the first region and a third conductive layer in the third opening so as to be in contact with the second region.

[0017] Alternatively, in the above aspect, in the third step, the second impurity layer and the third impurity layer may be formed so that the side surface of the first opening of the first insulating layer has a region that protrudes relative to the second impurity layer and a region that protrudes relative to the third impurity layer.

[0018] Alternatively, in the above embodiment, the element may be a metal element.

[0019] Alternatively, in the above embodiment, in the first step, the oxide semiconductor layer and the first impurity layer may each contain indium, and the element may be at least one of titanium, tin, and antimony.

[0020] According to one embodiment of the present invention, a transistor with favorable electrical characteristics can be provided. According to one embodiment of the present invention, a transistor with large on-state current can be provided. According to one embodiment of the present invention, a highly reliable transistor, semiconductor device, or memory device can be provided. According to one embodiment of the present invention, a transistor, semiconductor device, or memory device that can be miniaturized or highly integrated can be provided. According to one embodiment of the present invention, a semiconductor device or memory device with low power consumption can be provided. According to one embodiment of the present invention, a memory device with high operating speed can be provided. According to one embodiment of the present invention, a manufacturing method of the above transistor, semiconductor device, or memory device can be provided.

[0021] Note that the description of these effects does not preclude the existence of other effects. One embodiment of the present invention does not necessarily have all of these effects. Effects other than these can be extracted from the description in the specification, drawings, and claims.

[0022] FIG. 1A is a plan view showing a structural example of a semiconductor device. FIGS. 1B to 1D are cross-sectional views showing a structural example of a semiconductor device. FIGS. 2A and 2B are cross-sectional views showing a structural example of a semiconductor device. FIGS. 3A and 3B are cross-sectional views showing a structural example of a semiconductor device. FIG. 4A is a plan view showing a structural example of a semiconductor device. FIGS. 4B and 4C are cross-sectional views showing a structural example of a semiconductor device. FIGS. 5A and 5B are diagrams illustrating carrier concentration dependence of Hall mobility. FIG. 5C is a cross-sectional view illustrating an indium oxide film. FIGS. 6A and 6B are cross-sectional views showing a structural example of a semiconductor device. FIGS. 7A to 7C are cross-sectional views showing a structural example of a semiconductor device. FIG. 8A is a plan view showing an example of a method for manufacturing a semiconductor device. FIGS. 8B to 8D are cross-sectional views showing an example of a method for manufacturing a semiconductor device. FIG. 9A is a plan view showing an example of a method for manufacturing a semiconductor device. FIGS. 9B to 9D are cross-sectional views showing an example of a method for manufacturing a semiconductor device. FIG. 10A is a plan view showing an example of a method for manufacturing a semiconductor device. FIGS. 10B to 10D are cross-sectional views showing an example of a method for manufacturing a semiconductor device. FIG. 11A is a plan view illustrating an example of a method for manufacturing a semiconductor device. FIGS. 11B to 11D are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device. FIG. 12A is a plan view illustrating an example of a method for manufacturing a semiconductor device. FIGS. 12B to 12D are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device. FIG. 13A is a plan view illustrating an example of a method for manufacturing a semiconductor device. FIGS. 13B to 13D are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device. FIG. 14A is a plan view illustrating an example of a method for manufacturing a semiconductor device. FIGS. 14B to 14D are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device. FIGS. 15A and 15B are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device. FIGS. 16A and 16B are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device. FIGS. 17A to 17C are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device. FIGS. 18A and 18B are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device. FIG. 19 is a block diagram illustrating a configuration example of a semiconductor device. FIGS. 20A to 20G are diagrams illustrating an example of a circuit configuration of a memory cell. FIG. 21 is a cross-sectional view showing an example of a semiconductor device.22A and 22B are perspective views illustrating an example of the configuration of a semiconductor device. FIG. 23 is a cross-sectional view showing an example of a semiconductor device. FIG. 24 is a block diagram illustrating a CPU. FIGS. 25A and 25B are perspective views of a semiconductor device. FIGS. 26A and 26B are perspective views of a semiconductor device. FIG. 27 is a conceptual diagram illustrating the hierarchy of a storage device. FIGS. 28A and 28B are diagrams illustrating an example of electronic components. FIGS. 29A to 29C are diagrams illustrating an example of a mainframe computer. FIG. 29D is a diagram illustrating an example of space equipment. FIG. 29E is a diagram illustrating an example of a storage system applicable to a data center. FIGS. 30A to 30F are diagrams illustrating an example of electronic equipment.

[0023] The embodiments will be described in detail with reference to the drawings. However, the present invention is not limited to the following description, and it will be readily understood by those skilled in the art that various changes can be made in form and detail without departing from the spirit and scope of the present invention. Therefore, the present invention should not be interpreted as being limited to the description of the embodiments shown below.

[0024] In the configuration of the invention described below, the same parts or parts having similar functions are denoted by the same reference numerals in different drawings, and repeated explanations thereof will be omitted. Furthermore, when referring to similar functions, the same hatching pattern may be used and no particular reference numeral may be assigned.

[0025] Furthermore, for ease of understanding, the position, size, range, etc. of each component shown in the drawings may not represent the actual position, size, range, etc. Therefore, the disclosed invention is not necessarily limited to the position, size, range, etc. disclosed in the drawings.

[0026] In this specification, ordinal numbers such as "first" and "second" are used to avoid confusion between components, and do not indicate any order or ranking, such as the order of processes, stacking order, or arrangement order. Furthermore, even if a term is not accompanied by an ordinal number in this specification, ordinal numbers may be accompanied in the claims to avoid confusion between components. Furthermore, even if a term is accompanied by an ordinal number in this specification, ordinal numbers may be accompanied by a different ordinal number in the claims. Furthermore, even if a term is accompanied by an ordinal number in this specification, ordinal numbers may be omitted in the claims.

[0027] A transistor is a type of semiconductor element that can perform functions such as amplifying current or voltage and performing a switching operation to control conduction or non-conduction. The term "transistor" as used herein includes an insulated gate field effect transistor (IGFET) and a thin film transistor (TFT).

[0028] In this specification and the like, a transistor using an oxide semiconductor or a metal oxide for a semiconductor layer and a transistor having an oxide semiconductor or a metal oxide for a channel formation region may be referred to as an OS (oxide semiconductor) transistor. A transistor having silicon for a channel formation region may be referred to as a Si transistor.

[0029] In this specification and the like, a transistor is an element having at least three terminals including a gate, a drain, and a source. A transistor has a region (also referred to as a channel formation region) where a channel is formed between the drain (drain terminal, drain region, or drain electrode) and the source (source terminal, source region, or source electrode), and current can flow between the source and the drain through the channel formation region. Note that in this specification and the like, the channel formation region refers to a region through which current mainly flows.

[0030] Furthermore, the functions of "source" and "drain" may be interchanged when transistors of different polarities are used, or when the direction of current flow changes during circuit operation, etc. Therefore, in this specification, the terms "source" and "drain" may be used interchangeably.

[0031] Note that impurities in a semiconductor refer to, for example, elements other than the main components constituting the semiconductor. For example, an element with a concentration of less than 0.1 atomic % can be considered an impurity. The presence of impurities may increase the density of defect states in the semiconductor or reduce the crystallinity, for example. When the semiconductor is an oxide semiconductor, impurities that change the characteristics of the semiconductor include, for example, Group 1 elements, Group 2 elements, Group 13 elements, Group 14 elements, Group 15 elements, and transition metals other than the main components of the oxide semiconductor. Specific examples include hydrogen, lithium, sodium, silicon, boron, phosphorus, carbon, and nitrogen. Note that water may also function as an impurity. For example, the inclusion of impurities may cause oxygen deficiency (V) in the oxide semiconductor. Ｏ (also called) may be formed.

[0032] In this specification and the like, an oxynitride refers to a material whose composition contains more oxygen than nitrogen. A nitride oxide refers to a material whose composition contains more nitrogen than oxygen. For example, silicon oxynitride refers to a material whose composition contains more oxygen than nitrogen, and silicon nitride oxide refers to a material whose composition contains more nitrogen than oxygen.

[0033] To analyze the content of elements such as hydrogen, oxygen, carbon, or nitrogen contained in a film, for example, secondary ion mass spectrometry (SIMS) or X-ray photoelectron spectroscopy (XPS) or electron spectroscopy for chemical analysis (ESCA) can be used. XPS is suitable when the content of the target element is high (e.g., 0.5 atomic% or more, or 1 atomic% or more). On the other hand, SIMS is suitable when the content of the target element is low (e.g., 0.5 atomic% or less, or 1 atomic% or less). When comparing the content of elements, it is more preferable to perform a combined analysis using both SIMS and XPS analytical methods.

[0034] In this specification and the like, the term "content" refers to the ratio of a component contained in a film. For example, when an oxide semiconductor layer contains a metal element X, a metal element Y, and a metal element Z, the number of atoms of each of the metal elements X, Y, and Z contained in the oxide semiconductor layer is expressed as A. Ｘ , A Ｙ , A Ｚ When the content of the metal element X is Ｘ / (A Ｘ +A Ｙ +A Ｚ In addition, the ratio of the number of atoms of the metal element X, the metal element Y, and the metal element Z in the oxide semiconductor layer (atomic ratio) can be expressed as follows: Ｘ : B Ｙ : B Ｚ When the content of the metal element X is expressed as B Ｘ / (B Ｘ +B Ｙ +B Ｚ ) can be shown as

[0035] It should be noted that the terms "film" and "layer" can be interchangeable depending on the circumstances. For example, the term "conductive layer" can be changed to the term "conductive film." Or, for example, the term "insulating film" can be changed to the term "insulating layer."

[0036] Furthermore, in this specification, "parallel" refers to a state in which two straight lines are arranged at an angle of -10 degrees or more and 10 degrees or less. Therefore, it also includes cases where the angle is -5 degrees or more and 5 degrees or less. Furthermore, "substantially parallel" refers to a state in which two straight lines are arranged at an angle of -20 degrees or more and 20 degrees or less. Furthermore, "perpendicular" refers to a state in which two straight lines are arranged at an angle of 80 degrees or more and 100 degrees or less. Therefore, it also includes cases where the angle is 85 degrees or more and 95 degrees or less. Furthermore, "substantially perpendicular" refers to a state in which two straight lines are arranged at an angle of 70 degrees or more and 110 degrees or less.

[0037] In this specification, "connection" includes, as an example, "electrical connection." Note that the term "electrical connection" is sometimes used to define the connection relationship between circuit elements as an object. Furthermore, "electrical connection" includes "direct connection" and "indirect connection." "A and B are directly connected" means that A and B are connected without a circuit element (e.g., a transistor, a switch, etc.; wiring is not a circuit element). On the other hand, "A and B are indirectly connected" means that A and B are connected via one or more circuit elements. Note that A, B, and C, which will be described later, represent objects such as elements, circuits, wiring, electrodes, terminals, semiconductor layers, and conductive layers.

[0038] For example, assuming that a circuit including A and B is operating, if there is a time during the operation of the circuit when an electrical signal is exchanged or an interaction of electrical potential occurs between A and B, then it can be defined that "A and B are indirectly connected" as objects. Note that even if there is a time during the operation of the circuit when no electrical signal is exchanged or an interaction of electrical potential occurs between A and B, it can still be defined that "A and B are indirectly connected" as long as there is a time during the operation of the circuit when an electrical signal is exchanged or an interaction of electrical potential occurs between A and B.

[0039] An example of a case where "A and B are indirectly connected" is when A and B are connected via the source and drain of one or more transistors. On the other hand, an example of a case where it cannot be said that "A and B are indirectly connected" is when an insulator is present in the path from A to B. Specifically, there are cases where a capacitive element is connected between A and B, and cases where a gate insulating film of a transistor is present between A and B. Therefore, it cannot be said that "the gate (A) of a transistor and the source or drain (B) of the transistor are indirectly connected."

[0040] Another example of a case where it cannot be said that "A and B are indirectly connected" is when multiple transistors are connected via their sources and drains to the path from A to B, and a constant potential V is supplied to a node between one transistor and another transistor from a power supply, GND, etc.

[0041] Unless otherwise specified, in this specification, the off-state current refers to a leakage current between the source and drain when a transistor is in an off state (also referred to as a non-conducting state or a cut-off state). Unless otherwise specified, the off-state refers to a state in which the gate-source voltage Vgs is lower than the threshold voltage Vth for an n-channel transistor (higher than Vth for a p-channel transistor).

[0042] In this specification and the like, a tapered shape refers to a shape in which at least a portion of the side surface of a structure is inclined with respect to the substrate surface or the surface to be formed. For example, it is preferable to have a region in which the angle (also called the taper angle) between the inclined side surface and the substrate surface or the surface to be formed is greater than 0 degrees and less than 90 degrees. Note that the side surface of the structure, the substrate surface, and the surface to be formed do not necessarily need to be completely flat, and may be approximately planar with a slight curvature or approximately planar with a slight unevenness.

[0043] In this specification, when it is stated that A is located on B, at least a portion of A is located on B. Therefore, for example, it can be rephrased as "A has a region located on B." Similarly, when it is stated that A contacts B or A overlaps B, at least a portion of A contacts B or overlaps B. Therefore, it can be rephrased as "A has a region contacting B" or "A has a region overlapping B," respectively. Similarly, in this specification, when it is stated that A covers B, at least a portion of A covers B. Therefore, for example, it can be rephrased as "A has a region covering B."

[0044] In this specification, the term "island-like" refers to a state in which two or more layers formed using the same material in the same process are physically separated. For example, an island-like light-emitting layer refers to a state in which the light-emitting layer is physically separated from an adjacent light-emitting layer.

[0045] In the drawings and the like relating to this specification, arrows indicating the X direction, Y direction, and Z direction may be used. In this specification and the like, the "X direction" refers to the direction along the X axis, and there may be no distinction between the forward direction and the reverse direction unless explicitly stated. The same applies to the "Y direction" and the "Z direction." The X direction, Y direction, and Z direction are directions that intersect with each other. For example, the X direction, Y direction, and Z direction are directions that are perpendicular to each other.

[0046] Embodiment 1 In this embodiment, a semiconductor device of one embodiment of the present invention will be described.

[0047] One embodiment of the present invention relates to a transistor including an indium oxide film as a semiconductor layer and a semiconductor device including the transistor. The indium oxide film is a metal oxide film that is likely to have crystallinity. For example, the indium oxide film can be a single-crystal film or a polycrystalline film. This allows, for example, a structure in which no grain boundaries are observed in the channel formation region of the transistor. Therefore, carrier scattering at the grain boundaries can be suppressed, and a transistor with high field-effect mobility can be realized. Furthermore, a highly reliable transistor can be realized.

[0048] In this specification and the like, indium oxide having at least a crystalline portion or a crystalline region in a film is referred to as crystalline indium oxide (crystal IO) or crystalline indium oxide (crystalline IO). Examples of crystalline IO or crystalline IO include single-crystalline indium oxide, polycrystalline indium oxide, and microcrystalline indium oxide.

[0049] Furthermore, indium oxide films tend to allow one or both of hydrogen and oxygen to move more easily than, for example, indium gallium zinc oxide (In—Ga—Zn oxide, also referred to as IGZO) films. Therefore, it can be said that indium oxide films are films into which one or both of hydrogen and oxygen are more easily supplied and from which one or both of hydrogen and oxygen are more easily discharged than, for example, an IGZO film.

[0050] It is preferable that oxygen vacancies and impurities are reduced as much as possible in the channel formation region of the metal oxide film. On the other hand, if an excessive amount of oxygen is supplied to the metal oxide film, the reliability of the transistor decreases. From the above, in the semiconductor device of one embodiment of the present invention, it is preferable that the hydrogen concentration in the metal oxide film is low. Furthermore, it is preferable that an appropriate amount of oxygen is supplied to the metal oxide film to reduce the excessive amount of oxygen.

[0051] By using an indium oxide film, through which one or both of hydrogen and oxygen can easily move, as the metal oxide film, the hydrogen concentration in the metal oxide film can be reduced. Also, the amount of excess oxygen in the metal oxide film can be reduced. As described above, by using an indium oxide film as the semiconductor layer, a highly reliable semiconductor device can be provided.

[0052] The semiconductor layer includes a channel formation region of the transistor as well as a source region and a drain region. The channel formation region is located between the source region and the drain region. The source region and the drain region are regions with reduced resistance, e.g., regions with lower electrical resistivity than the channel formation region.

[0053] A semiconductor device according to one embodiment of the present invention includes an interlayer film over a semiconductor layer. The interlayer film has an opening having a region overlapping with the semiconductor layer. A gate insulating layer and a gate electrode of a transistor are provided in the opening. The gate insulating layer has a region in contact with a source region and a region in contact with a drain region. Specifically, the gate insulating layer has a region in contact with a side surface of the source region and a region in contact with a side surface of the drain region. Note that the gate electrode is provided over the gate insulating layer.

[0054] The source region and the drain region can be formed by forming an impurity layer on the semiconductor layer and then performing heat treatment. For example, a first impurity layer is formed on the semiconductor layer, and an interlayer film is formed on the first impurity layer. Subsequently, the interlayer film and the first impurity layer are processed. As a result, an opening having a region overlapping with the semiconductor layer is formed in the interlayer film. In addition, a second impurity layer and a third impurity layer are formed. Then, by performing heat treatment, the elements contained in the second impurity layer and the elements contained in the third impurity layer can be added as impurity elements to the semiconductor layer. As a result, a source region overlapping with the second impurity layer and a drain region overlapping with the third impurity layer can be formed in the semiconductor layer. The source region and the drain region each have a higher concentration of the impurity element than the channel formation region. Here, the heat treatment can be performed, for example, after forming a gate insulating layer and a gate electrode of the transistor.

[0055] By performing the heat treatment, a mixed layer of the component contained in the semiconductor layer and the component contained in the second impurity layer may be formed, i.e., alloyed. Similarly, the component contained in the semiconductor layer may be alloyed with the component contained in the third impurity layer. For example, when the second impurity layer and the third impurity layer contain an element that is the main component of the semiconductor layer and other elements, the above-mentioned alloying may occur. As a result, particularly when the film thickness of the second impurity layer is sufficiently thin compared to the film thickness of the semiconductor layer, the interface between the semiconductor layer and the second impurity layer may not be observed, and they may be observed as being integrated. Similarly, when the film thickness of the third impurity layer is sufficiently thin compared to the film thickness of the semiconductor layer, the interface between the semiconductor layer and the third impurity layer may not be observed, and they may be observed as being integrated.

[0056] Here, the side surface of the opening in the interlayer film preferably has a region that protrudes beyond the side surface of the second impurity layer and a region that protrudes beyond the side surface of the third impurity layer. This allows the distance between the source region and the channel formation region of the transistor and the distance between the drain region and the channel formation region of the transistor to be increased. Therefore, for example, during the above-mentioned heat treatment, impurity elements can be prevented from being mixed into the channel formation region. Therefore, a highly reliable semiconductor device can be provided. In the above case, the interlayer film has a region located on the gate insulating layer of the transistor. Specifically, the interlayer film is provided on the region of the gate insulating layer that contacts the source region and the region that contacts the drain region.

[0057] The impurity element contained in the semiconductor layer can be a metal element, such as titanium, tin, or antimony. The source and drain regions of the transistor according to one embodiment of the present invention each contain at least one of these metal elements.

[0058] <Structural Example of Semiconductor Device> A structural example of a semiconductor device of one embodiment of the present invention will be described below.

[0059] 1A is a plan view of a semiconductor device including a transistor 200A. Note that some elements are omitted from the plan view of FIG. 1A for clarity. Some elements may also be omitted from the subsequent plan views.

[0060] Fig. 1B is a cross-sectional view taken along dashed dotted line A1-A2 in Fig. 1A and is also a cross-sectional view in the channel length direction of transistor 200A. Fig. 1C is a cross-sectional view taken along dashed dotted line A3-A4 in Fig. 1A and is also a cross-sectional view in the channel width direction of transistor 200A. Fig. 1D is a cross-sectional view taken along dashed dotted line A5-A6 in Fig. 1A. Fig. 2A is an example of an enlarged view of Fig. 1B.

[0061] 1A to 2A, the X direction, Y direction, and Z direction are indicated by arrows. Note that although the same X, Y, and Z symbols are used in FIGS. 1A to 2A, the directions do not necessarily have to match. In subsequent drawings, the X direction, Y direction, and Z direction may also be indicated by arrows, but the directions do not necessarily have to match.

[0062] 1A to 2A includes an insulating layer 212 over a substrate (not shown), an insulating layer 214 over the insulating layer 212, a transistor 200A and an insulating layer 216 over the insulating layer 214, an insulating layer 275 over the insulating layer 216, an insulating layer 280 over the insulating layer 275, an insulating layer 282 over the transistor 200A and the insulating layer 280, an insulating layer 283 over the insulating layer 282, and an insulating layer 285 over the insulating layer 283. The insulating layer 212, the insulating layer 214, the insulating layer 216, the insulating layer 280, the insulating layer 282, the insulating layer 283, and the insulating layer 285 function as interlayer films.

[0063] [Transistor] The transistor 200A includes a conductive layer 205, an insulating layer 221 on the conductive layer 205, an insulating layer 222 on the insulating layer 221, an insulating layer 224 on the insulating layer 222, a semiconductor layer 230 on the insulating layer 224, an insulating layer 250, a conductive layer 243a, and a conductive layer 243b on the semiconductor layer 230, and a conductive layer 260 on the insulating layer 250.

[0064] The semiconductor layer 230 includes a metal oxide (also referred to as an oxide semiconductor) that functions as a semiconductor. Here, a transistor including an oxide semiconductor is referred to as an OS transistor. Note that in this specification and the like, a semiconductor layer including an oxide semiconductor can be alternatively referred to as an oxide semiconductor layer. Furthermore, since the semiconductor layer 230 includes a metal oxide, the semiconductor layer 230 can be alternatively referred to as a metal oxide layer. In the semiconductor device of one embodiment of the present invention, indium oxide can be used as the semiconductor layer 230, for example.

[0065] The semiconductor layer 230 has a low-resistance region 230na, a low-resistance region 230nb, and a channel formation region 230i located between the low-resistance region 230na and the low-resistance region 230nb. The low-resistance region 230na and the low-resistance region 230nb each have a higher carrier concentration than the channel formation region 230i. One of the low-resistance region 230na and the low-resistance region 230nb functions as a source region. The other of the low-resistance region 230na and the low-resistance region 230nb functions as a drain region.

[0066] The conductive layer 260 functions as a first gate electrode (also referred to as an upper gate electrode or a top gate electrode) of the transistor 200A. The insulating layer 250 functions as a first gate insulating layer of the transistor 200A. At least a part of a region of the semiconductor layer 230 that overlaps with the conductive layer 260 functions as a channel formation region 230i.

[0067] 2A shows the channel length L of the transistor 200A. The channel length L is, for example, preferably 1 nm or more and 300 nm or less, and more preferably 3 nm or more and 100 nm or less. This increases the on-state current of the transistor 200A, thereby improving the frequency characteristics.

[0068] The conductive layer 205 functions as a second gate electrode (also referred to as a lower gate electrode or a bottom gate electrode) of the transistor 200A. The insulating layers 224, 222, and 221 each function as a second gate insulating layer of the transistor 200A. The conductive layer 243a functions as one of a source electrode and a drain electrode of the transistor 200A. The conductive layer 243b functions as the other of the source electrode and the drain electrode of the transistor 200A.

[0069] The insulating layer 275 is located on the semiconductor layer 230 and the insulating layer 222. The insulating layer 275 is provided to cover the semiconductor layer 230 and the insulating layer 224. As described above, the insulating layer 280 is located on the insulating layer 275.

[0070] The insulating layer 280 and the insulating layer 275 have openings 289 that have regions overlapping with the insulating layer 222 and the semiconductor layer 230. Note that the openings 289 may be grooves.

[0071] In this specification and the like, a groove can be rephrased as a slit or a trench. Also, a groove portion can be rephrased as a slit portion or a trench portion. Note that a groove portion may also be rephrased as a slit or a trench.

[0072] The opening 289 has a region located between the low resistance region 230na and the low resistance region 230nb in a plan view. The insulating layer 250 and the conductive layer 260 are disposed within the opening 289. The upper surface of the insulating layer 280, the upper end of the insulating layer 250, and the upper surface of the conductive layer 260 are aligned or substantially aligned.

[0073] Insulating layer 282 is located on insulating layer 280, insulating layer 250, and conductive layer 260. Also, insulating layer 283 is located on insulating layer 282, and insulating layer 285 is located on insulating layer 283, as described above.

[0074] An opening 244a overlapping the low-resistance region 230na and an opening 244b overlapping the low-resistance region 230nb are provided in the insulating layer 285, the insulating layer 283, the insulating layer 282, the insulating layer 280, and the insulating layer 275. A conductive layer 243a and an insulating layer 241a are provided in the opening 244a, and a conductive layer 243b and an insulating layer 241b are provided in the opening 244b.

[0075] The conductive layer 243a has a region in contact with the low-resistance region 230na, and can be in contact with the upper surface of the low-resistance region 230na within the opening 244a, for example. Similarly, the conductive layer 243b has a region in contact with the low-resistance region 230nb, and can be in contact with the upper surface of the low-resistance region 230nb within the opening 244b, for example. The insulating layer 241a is provided in contact with the sidewall of the opening 244a. Similarly, the insulating layer 241b is provided in contact with the sidewall of the opening 244b. Furthermore, the conductive layer 243a is located inside the insulating layer 241a, and the conductive layer 243b is located inside the insulating layer 241b.

[0076] In this specification and the like, the sidewall of an opening refers to the side surface within the opening of the layer in which the opening is formed.

[0077] The low-resistance region 230na and the low-resistance region 230nb are regions with reduced resistance, e.g., regions with lower electrical resistivity than the channel formation region 230i. When impurity elements are added to the semiconductor layer 230, carriers are generated. The regions where carriers are generated become the low-resistance region 230na and the low-resistance region 230nb. Valence electron control can be achieved by adding impurity elements to the semiconductor layer 230. Examples of impurity elements include metal elements. Examples of impurity elements include titanium, tin, and antimony. The low-resistance region 230na and the low-resistance region 230nb each contain at least one of these metal elements. Specifically, the concentrations of these metal elements in the low-resistance region 230na and the low-resistance region 230nb are higher than the concentrations in the channel formation region 230i. The impurity elements are not limited to titanium, tin, and antimony. For example, germanium may be used as the impurity element. Furthermore, a trivalent element can be used as the impurity element, such as aluminum.

[0078] Adding titanium, tin, or antimony as an impurity element to the semiconductor layer 230 makes it easier to form a shallow donor level. That is, the donor level is easily formed so that the difference between the energy of the conduction band minimum (CBM) and the donor level is small. For example, adding titanium as an impurity element to the semiconductor layer 230 makes it possible to set the energy gap between the CBM and the donor level to 0.3 eV or less. Here, the band gap of indium oxide is 3 eV. Therefore, when indium oxide is used as the semiconductor layer 230, adding titanium as an impurity element makes it possible to set the energy gap between the CBM and the donor level to 1 / 10 of the band gap. This makes it possible to realize a transistor with high field-effect mobility.

[0079] Aluminum has a stronger bond with oxygen than indium. Therefore, when indium oxide is used as the semiconductor layer 230, adding aluminum as an impurity element to the semiconductor layer 230 may easily form oxygen vacancies (Vo). Here, when a metal oxide is used as the semiconductor layer 230, the oxygen vacancies in the semiconductor layer 230 become a source of carrier generation. Specifically, defects in which hydrogen enters an oxygen vacancy (hereinafter referred to as V Ｏ H) is formed, electrons that serve as carriers are generated. As described above, by adding aluminum as an impurity element to the semiconductor layer 230, the low-resistance regions 230na and 230nb can be formed in some cases.

[0080] The concentration of the impurity element in the low resistance region 230na and the low resistance region 230nb is 1×10 １７ atoms / cm ３ 8 x 10 or more ２１ atoms / cm ３ Preferably, 1×10 １７ atoms / cm ３ 5x10 or more ２０ atoms / cm ３ More preferably, 1×10 or less １８ atoms / cm ３ 5x10 or more２０ atoms / cm ３ The concentration of the impurity element in the low-resistance region 230na and the low-resistance region 230nb is preferably 0.5 atomic % or more and 30 atomic % or less, and more preferably 1 atomic % or more and 10 atomic % or less. The concentration of the impurity element in the channel formation region 230i is 1×10 １７ atoms / cm ３ Preferably less than 1 x 10 １５ atoms / cm ３ Less than 5 x 10 is more preferable. １４ atoms / cm ３ Alternatively, the concentration of the impurity element in the channel formation region 230i is preferably less than 0.5 atomic %, more preferably 0.01 atomic % or less, and further preferably 0.0002 atomic % or less.

[0081] In this specification and the like, when the impurity concentration contained in a semiconductor layer is expressed in atomic %, the impurity concentration is a value obtained by dividing the number of atoms of the impurity element by the number of atoms of the main element of the semiconductor layer. For example, when the impurity concentration in an indium oxide film is expressed in atomic %, the impurity concentration is a value obtained by dividing the number of atoms of the impurity element by the sum of the number of indium atoms and the number of oxygen atoms. Note that the impurity concentration in the indium oxide film may also be a value obtained by dividing the number of atoms of the impurity element by the number of indium atoms.

[0082] The low-resistance region 230na and the low-resistance region 230nb may not contain impurity elements. In this case, the low-resistance region 230na and the low-resistance region 230nb may be regions containing an element that is a main component of the semiconductor layer 230 at a higher concentration than the channel formation region 230i. For example, when indium oxide is used as the semiconductor layer 230, the low-resistance region 230na and the low-resistance region 230nb may be regions having a higher indium concentration than the channel formation region 230i.

[0083] When the semiconductor layer 230 is an n-type semiconductor, an impurity element imparting p-type conductivity may be added to the channel formation region 230i. For example, at least one of magnesium, cadmium, and zinc may be added to the channel formation region 230i. This may make it easier to make the channel formation region 230i i-type or substantially i-type. In this case, the concentration of the added element in the channel formation region 230i is 5×10 １４ atoms / cm ３ 5x10 or more １８ atoms / cm ３ Preferably less than 5 x 10 １４ atoms / cm ３ 1x10 or more １８ atoms / cm ３ More preferably, 1×10 or less １５ atoms / cm ３ 5x10 or more １７ atoms / cm ３ Alternatively, the concentration of the additional element in the channel formation region 230i is preferably 0.0002 atomic % or more and 0.5 atomic % or less, and more preferably 0.001 atomic % or more and 0.1 atomic % or less.

[0084] The concentration of the metal element contained in at least one of the low resistance region 230na, the low resistance region 230nb, and the channel formation region 230i can be measured by, for example, inductively coupled plasma mass spectrometry (ICP-MS), XPS, SIMS, time-of-flight secondary ion mass spectrometry (ToF-SIMS), Auger electron spectroscopy (AES), energy dispersive X-ray spectroscopy (EDX), or the like. The evaluation can be performed using, for example, plasma atomic emission spectroscopy (ICP-AES), inductively coupled plasma atomic emission spectroscopy (ICP-AES), or the like.

[0085] The insulating layer 250 has a region in contact with the channel formation region 230i, a region in contact with the low-resistance region 230na, and a region in contact with the low-resistance region 230nb. Specifically, the insulating layer 250 has a region in contact with the top surface of the channel formation region 230i, a region in contact with the side surface of the low-resistance region 230na on the opening 289 side, and a region in contact with the side surface of the low-resistance region 230nb on the opening 289 side.

[0086] Furthermore, the insulating layer 275 has a region located above the insulating layer 250. In other words, the insulating layer 250 has a region located below the insulating layer 275. Specifically, the insulating layer 250 has a region located between the semiconductor layer 230 and the insulating layer 275. For example, the insulating layer 250 can have a region in contact with the lower surface of the insulating layer 275.

[0087] The side surfaces of the insulating layer 275 at the opening 289 and the side surfaces of the insulating layer 280 at the opening 289 have regions that protrude toward the channel formation region 230i relative to the side surfaces of the low resistance region 230na, and regions that protrude toward the channel formation region 230i relative to the side surfaces of the low resistance region 230nb.

[0088] As a result, the distance between the low-resistance region 230na and the channel formation region 230i, and the distance between the low-resistance region 230nb and the channel formation region 230i can be made larger than when, for example, the side surface of the low-resistance region 230na on the opening 289 side and the side surface of the low-resistance region 230nb on the opening 289 side are aligned with the side surface of the insulating layer 275 at the opening 289. This makes it possible to prevent impurity elements contained in the low-resistance region 230na and the low-resistance region 230nb from being mixed into the channel formation region 230i. This makes it possible to provide a highly reliable semiconductor device.

[0089] 2A , the distance in the Y direction between the side surface of the low-resistance region 230na on the opening 289 side and the bottom end of the insulating layer 275 at the opening 289 is referred to as distance D. The distance D is, for example, preferably 0.1 nm or more and 20 nm or less, more preferably 0.1 nm or more and 10 nm or less, more preferably 0.1 nm or more and 7 nm or less, even more preferably 0.1 nm or more and 4 nm or less, and even more preferably 0.2 nm or more and 2 nm or less. As a result, it is possible to prevent impurity elements contained in the low-resistance region 230na from being mixed into the channel formation region 230i, while also preventing, for example, the conductive layer 260 from penetrating between the semiconductor layer 230 and the insulating layer 275. The same applies to the low-resistance region 230nb.

[0090] The low-resistance regions 230na and 230nb can be formed by forming an impurity layer on the semiconductor layer 230 and then performing heat treatment, as will be described in detail later. Specifically, by performing the heat treatment, elements contained in the impurity layer can be added as impurity elements to the semiconductor layer 230. This allows the low-resistance regions 230na and 230nb to be formed. Here, when indium oxide is used for the semiconductor layer 230, at least one of titanium, tin, antimony, germanium, and aluminum can be used as the impurity element.

[0091] By performing the heat treatment, the components contained in the semiconductor layer 230 and the components contained in the impurity layer may be alloyed. For example, when the impurity layer contains an element that is the main component of the semiconductor layer 230 and other elements, the above-mentioned alloying may occur. Therefore, particularly when the film thickness of the impurity layer is sufficiently thinner than the film thickness of the semiconductor layer 230, the interface between the semiconductor layer 230 and the impurity layer may not be observed, and they may be observed as being integrated.

[0092] FIG. 2A shows the thickness Tins of the semiconductor layer 230 in the region overlapping with the conductive layer 260, and the thickness Tn of the semiconductor layer 230 in the region including the low-resistance region 230na and the region including the low-resistance region 230nb. As described above, when the components contained in the semiconductor layer 230 and the components contained in the impurity layer are alloyed, the semiconductor layer 230 and the impurity layer may be observed as integrated. In this case, the impurity layer may not be observed, and the thickness Tn of the semiconductor layer 230 may be observed to be thicker than the thickness Tins. The difference between the thickness Tn and the thickness Tins may be equal to or approximately equal to the thickness of the impurity layer. In this case, the thickness Tins may be the film thickness of the semiconductor layer 230 before the impurity layer is formed, i.e., the film thickness of the semiconductor layer 230 as formed. Note that when the components contained in the semiconductor layer 230 and the components contained in the impurity layer are not alloyed, the interface between the semiconductor layer 230 and the impurity layer may be observed.

[0093] In the following description, it is assumed that the semiconductor layer 230 and the impurity layer are integrated and observed as one semiconductor layer 230 .

[0094] The thickness Tins is preferably 2 nm to 500 nm, more preferably 2.5 nm to 300 nm, more preferably 2.5 nm to 200 nm, more preferably 5 nm to 100 nm, more preferably 7 nm to 70 nm, and even more preferably 10 nm to 50 nm. The difference between the thickness Tn and the thickness Tins is set smaller than the thickness Tins. The difference between the thickness Tn and the thickness Tins is preferably, for example, 0.1 nm to 10 nm, more preferably 0.1 nm to 5 nm, more preferably 0.1 nm to 3 nm, more preferably 0.1 nm to 2 nm, and even more preferably 0.1 nm to 1 nm. By keeping the difference between the thickness Tn and the thickness Tins within the above range, for example, it is possible to prevent the step generated in the semiconductor layer 230 from becoming too large. Therefore, for example, it is possible to prevent the conductive layer 260 from penetrating into the region between the semiconductor layer 230 and the insulating layer 275.

[0095] The thickness of the alloyed region may be calculated by performing a line analysis of the composition of the alloyed region and its surroundings using SIMS or EDX.

[0096] The impurity elements contained in the low-resistance region 230na and the low-resistance region 230nb may also be contained in regions of the semiconductor layer 230 that overlap with both the insulating layer 250 and the insulating layer 275. These regions can function as LDD (Lightly Doped Drain) regions. The concentration of the impurity elements in the LDD regions is lower than the concentration of the impurity elements in the low-resistance region 230na and the low-resistance region 230nb and higher than the concentration of the impurity elements in the channel formation region 230i. The LDD regions can function as buffer regions for alleviating an electric field. Note that since the LDD regions do not overlap with the conductive layer 260, almost no channel is formed even when a gate voltage is applied to the conductive layer 260.

[0097] 2A shows an example in which the height from the reference plane of the lower surface of the insulating layer 250 in contact with the semiconductor layer 230 is higher than the height from the reference plane of the lower surfaces of the low-resistance regions 230na and 230nb, but this is not a limitation of one aspect of the present invention. FIG. 2B shows an example in which the height from the reference plane of the lower surface of the insulating layer 250 in contact with the semiconductor layer 230 is lower than the height from the reference plane of the lower surfaces of the low-resistance regions 230na and 230nb. As will be described in detail later, a portion of the semiconductor layer 230 may be removed due to the impurity layer formation process. As a result, as shown in FIG. 2B, the height from the reference plane of the lower surface of the insulating layer 250 in contact with the semiconductor layer 230 may be lower than the height from the reference plane of the lower surfaces of the low-resistance regions 230na and 230nb.

[0098] In this specification and the like, the reference plane may be, for example, the substrate surface or the upper surface of an interlayer film. For example, in terms of the height from the reference plane of an element located on the insulating layer 224, the upper surface of the insulating layer 224 may be the reference plane.

[0099] 3A is a plan view illustrating a configuration example of a semiconductor device including a transistor 200B. In the following description of the transistor 200B, differences in configuration from the transistor 200A will be mainly described, and descriptions of similar configurations will be omitted as appropriate.

[0100] In the transistor 200B, the semiconductor layer 230 has a recess 287 at a position overlapping the opening 289. The channel formation region 230i of the transistor 200B is located below the recess 287. In the transistor 200B, the insulating layer 250 has a region in contact with the side surface of the low-resistance region 230na and a region in contact with the side surface of the low-resistance region 230nb, as well as a region in contact with the top surface of the semiconductor layer 230 in the region between the low-resistance region 230na and the recess 287, a region in contact with the top surface of the semiconductor layer 230 in the region between the low-resistance region 230nb and the recess 287, a region in contact with the side surface of the semiconductor layer 230 in the recess 287, and a region in contact with the top surface of the semiconductor layer 230 in the recess 287. Here, the side surface of the semiconductor layer 230 in the recess 287 is also referred to as the sidewall of the recess 287. The top surface of the semiconductor layer 230 in the recess 287 is also referred to as the bottom of the recess 287.

[0101] In transistor 200B, the height (e.g., thickness T2) of the lower surface of insulating layer 250 from the reference plane in the region overlapping with insulating layer 275 is higher than the height (e.g., thickness T1) of the lower surface of insulating layer 250 from the reference plane within recess 287. In this case, regions 230nc and 230nd may be formed in the regions of semiconductor layer 230 overlapping with insulating layer 250 and insulating layer 275. Figure 3B is an enlarged view of region 230nd and the region nearby.

[0102] The region 230nc is located between the low-resistance region 230na and the channel formation region 230i in a planar view. The region 230nd is located between the low-resistance region 230nb and the channel formation region 230i in a planar view. The region 230nc has a region in contact with the side surface of the low-resistance region 230na on the opening 289 side, and a region in contact with the bottom surface of the insulating layer 250. The region 230nd has a region in contact with the side surface of the low-resistance region 230nb on the opening 289 side, and a region in contact with the bottom surface of the insulating layer 250.

[0103] The concentration of the impurity element in the region 230nc is lower than the concentration of the impurity element in the low-resistance region 230na and higher than the concentration of the impurity element in the channel formation region 230i. Similarly, the concentration of the impurity element in the region 230nd is lower than the concentration of the impurity element in the low-resistance region 230nb and higher than the concentration of the impurity element in the channel formation region 230i. The regions 230nc and 230nd can function as LDD regions. As described above, the LDD regions can function as buffer regions for alleviating electric fields. Therefore, by including the regions 230nc and 230nd, the transistor 200B can be a transistor with a high drain breakdown voltage.

[0104] Furthermore, since the semiconductor layer 230 has the recess 287, the region 230nc and the channel formation region 230i can be separated from each other. Furthermore, the region 230nd and the channel formation region 230i can be separated from each other. This prevents impurity elements contained in the region 230nc and the region 230nd from being mixed into the channel formation region 230i. As a result, a semiconductor device including the transistor 200B can be a highly reliable semiconductor device. Note that the region 230nc and the region 230nd may not be formed.

[0105] FIG. 3A shows the thickness T1 of the semiconductor layer 230 in the region where the recess 287 is formed. FIG. 3A also shows the thickness T2 of the semiconductor layer 230 in the region located outside the recess 287 and overlapping with the insulating layer 250. Similar to FIG. 2A , FIG. 3A also shows the thickness Tn of the semiconductor layer 230 in the region including the low-resistance region 230na and the region including the low-resistance region 230nb. As shown in FIG. 3A , the channel formation region 230i of the transistor 200B is formed in a region where the semiconductor layer 230 has a thickness T1. Furthermore, the regions 230nc and 230nd are formed in a region where the semiconductor layer 230 has a thickness T2. Note that a portion of the region 230nc and a portion of the region 230nd may be formed in the region where the semiconductor layer 230 has a thickness T1.

[0106] The difference between the thickness T2 and the thickness T1 can be set to the depth of the recess 287. The difference between the thickness T2 and the thickness T1 is preferably, for example, 0.1 nm to 50 nm, more preferably 0.2 nm to 30 nm, more preferably 0.3 nm to 10 nm, and even more preferably 0.5 nm to 5 nm. By setting the difference between the thickness T2 and the thickness T1 within the above range, the distance between the region 230nc and the channel formation region 230i and the region 230nd can be set to a distance that can prevent impurity elements from entering the channel formation region 230i while suppressing a decrease in the on-current of the transistor 200B due to an offset region (a region in the semiconductor layer 230 to which a gate electric field is not applied).

[0107] Fig. 4A is a plan view showing a configuration example of a semiconductor device including a transistor 200C. Fig. 4B is a cross-sectional view taken along dashed dotted line A1-A2 in Fig. 4A. Fig. 4C is a cross-sectional view taken along dashed dotted line A5-A6 in Fig. 4A. Note that Fig. 1C can be referred to for a cross-sectional view taken along dashed dotted line A3-A4 in Fig. 4A.

[0108] In the following description of the transistor 200C, differences from the transistor 200A will be mainly described, and descriptions of similar components will be omitted as appropriate. Note that in this specification and the like, the transistors 200A, 200B, and 200C are collectively referred to as transistors 200.

[0109] The transistor 200C includes a conductive layer 242a and a conductive layer 242b. The conductive layer 242a is provided on the low-resistance region 230na and has a region in contact with, for example, the upper surface of the low-resistance region 230na. The conductive layer 242b is provided on the low-resistance region 230nb and has a region in contact with, for example, the upper surface of the low-resistance region 230nb. Here, the upper end of the conductive layer 242a on the opening 289 side and the upper end of the conductive layer 242b on the opening 289 side can be aligned or approximately aligned with the lower end of the insulating layer 275 at the opening 289.

[0110] The conductive layer 242a has a region that protrudes from the side surface of the low-resistance region 230na toward the channel formation region 230i. Similarly, the conductive layer 242b has a region that protrudes from the side surface of the low-resistance region 230nb toward the channel formation region 230i.

[0111] The conductive layer 242a functions as one of a source electrode and a drain electrode of the transistor 200C. The conductive layer 242b functions as the other of the source electrode and the drain electrode of the transistor 200C.

[0112] In the semiconductor device including the transistor 200C, the opening 244a is provided to overlap with the conductive layer 242a. Similarly, the opening 244b is provided to overlap with the conductive layer 242b. Here, in the semiconductor device including the transistor 200C, the opening 244a does not have to overlap with the low-resistance region 230na. Similarly, the opening 244b does not have to overlap with the low-resistance region 230nb.

[0113] In a semiconductor device including the transistor 200C, the conductive layer 243a provided in the opening 244a has a region in contact with the conductive layer 242a, and can be in contact with, for example, the top surface of the conductive layer 242a. Similarly, the conductive layer 243b provided in the opening 244b has a region in contact with the conductive layer 242b, and can be in contact with, for example, the top surface of the conductive layer 242b. Note that the conductive layer 243a may or may not be included in one of the source electrode and the drain electrode of the transistor 200C. Similarly, the conductive layer 243b may or may not be included in the other of the source electrode and the drain electrode of the transistor 200C.

[0114] The transistor 200C can have a larger contact area between the low-resistance region 230na and one of the source and drain electrodes, and a larger contact area between the low-resistance region 230nb and the other of the source and drain electrodes, than, for example, the transistor 200A. For example, the entire top surface of the low-resistance region 230na can be in contact with one of the source and drain electrodes. Furthermore, the entire top surface of the low-resistance region 230nb can be in contact with the other of the source and drain electrodes. As a result, the contact resistance between the low-resistance region 230na and one of the source and drain electrodes, and the contact resistance between the low-resistance region 230nb and the other of the source and drain electrodes can be smaller than, for example, the transistor 200A. Therefore, the transistor 200C can have a larger on-state current than the transistor 200A. Meanwhile, the transistor 200A can be manufactured using fewer processes than the transistor 200C. Furthermore, in the transistor 200A, no parasitic capacitance occurs between the conductive layer 242a and the conductive layer 260, and no parasitic capacitance occurs between the conductive layer 242b and the conductive layer 260. Therefore, the transistor 200A can have smaller parasitic capacitance between the source electrode and the gate electrode and smaller parasitic capacitance between the drain electrode and the gate electrode than the transistor 200C.

[0115] The conductive layers 242a and 242b can be formed using the conductive materials described in the section "Conductive Layer" below. In particular, it is preferable to use a conductive material that is resistant to oxidation or a conductive material that has a function of suppressing oxygen diffusion for the conductive layers 242a and 242b. Examples of such a conductive material include a conductive material containing nitrogen and a conductive material containing oxygen. This can suppress a decrease in the conductivity of the conductive layers 242a and 242b.

[0116] For the conductive layers 242a and 242b, it is preferable to use a metal nitride, such as a nitride containing tantalum, a nitride containing titanium, a nitride containing molybdenum, a nitride containing tungsten, a nitride containing tantalum and aluminum, or a nitride containing titanium and aluminum. For example, tantalum nitride can be used for the conductive layers 242a and 242b. Alternatively, for example, ruthenium, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, an oxide containing lanthanum and nickel, indium tin oxide (In—Sn oxide, also referred to as ITO), indium tin oxide containing silicon oxide (also referred to as ITSO), In—Zn oxide, or the like may be used. These materials are preferable because they are conductive materials that are difficult to oxidize or that maintain their conductivity even when they absorb oxygen.

[0117] Alternatively, each of the conductive layers 242a and 242b may have a stacked structure. In this case, it is preferable to use the above-mentioned conductive material for the lower layer (layer having a large contact area with the semiconductor layer 230) of the conductive layer 242a and the conductive layer 242b, and to use a conductive material with higher conductivity for the upper layer of the conductive layer 242a and the conductive layer 242b. For example, tantalum nitride can be used for the lower layer, and tungsten can be used for the upper layer. Alternatively, ITO or ITSO can be used for the lower layer, and tungsten can be used for the upper layer.

[0118] A semiconductor layer, an insulating layer, and a conductive layer provided in a semiconductor device including the transistor 200 will be described below.

[0119] As described above, indium oxide is preferably used for the semiconductor layer 230. In this case, the semiconductor layer 230 contains indium and oxygen. For example, the semiconductor layer 230 preferably includes an indium oxide film. The higher the ratio of the number of indium atoms to the sum of the numbers of atoms of all metal elements contained in the metal oxide, the higher the field-effect mobility of the transistor. Therefore, by using indium oxide for the semiconductor layer 230, the transistor can have a large on-state current and high frequency characteristics.

[0120] Next, an indium oxide film applied to a transistor will be described. The indium oxide film preferably has crystallinity (i.e., has crystal grains). Examples of films having crystal grains include single-crystal films, polycrystalline films, and amorphous films containing crystal grains (also called microcrystalline films). In particular, the indium oxide film is preferably a polycrystalline film, and more preferably a single-crystal film. A single-crystal film does not have grain boundaries. Impurities (typically, insulating impurities, insulating oxides, etc.) that hinder carrier flow tend to segregate at grain boundaries. The use of a single-crystal film can suppress carrier scattering at grain boundaries, thereby realizing a transistor exhibiting high field-effect mobility. Furthermore, the use of a single-crystal film has the excellent effect of suppressing variations in transistor characteristics due to the grain boundaries.

[0121] Furthermore, polycrystalline films are preferable because they can reduce carrier scattering and exhibit high field-effect mobility compared to microcrystalline or amorphous films. When using a polycrystalline film, it is preferable to use a film with as large a crystal grain size as possible and with few crystal grain boundaries. Note that in a transistor using an indium oxide polycrystalline film, if there is no crystal grain boundary in the channel formation region or no crystal grain boundary is observed, the channel formation region is located within a single crystal region included in the polycrystalline film, and therefore the transistor can be considered to be using single-crystal indium oxide.

[0122] The crystallinity of indium oxide can be analyzed by, for example, X-ray diffraction (XRD), transmission electron microscopy (TEM), or electron diffraction (ED). Alternatively, a combination of these methods may be used for analysis.

[0123] In this specification and the like, a semiconductor layer in which no crystal grain boundary is observed in the channel formation region, a semiconductor layer in which the channel formation region is included in one crystal grain, or a semiconductor layer in which the crystal axis direction is the same in at least two regions in the channel formation region can be called a single crystal film. Also, a semiconductor layer in which, in the channel formation region, within one crystal grain, the direction of another crystal axis continuously changes around a certain crystal axis or a certain crystal orientation as the axis of rotation can be called a single crystal film.

[0124] The channel formation region refers to a region of the semiconductor layer that overlaps (or faces) the gate electrode via the gate insulating layer, and is located between the region in contact with the source electrode and the region in contact with the drain electrode. The current path in the channel formation region is the shortest distance between the source electrode and the drain electrode. Therefore, the crystal grains, crystal grain boundaries, crystal axes, crystal orientation, etc. in the channel formation region can be confirmed by observing a cross section including the semiconductor layer, the source electrode, and the drain electrode.

[0125] The indium oxide film is preferably a single-crystal film. A single-crystal film does not have grain boundaries, so that carrier scattering at the grain boundaries can be suppressed, resulting in a transistor with high field-effect mobility and high reliability.

[0126] The indium oxide film may be a polycrystalline film or an amorphous film containing crystal grains. In this case, it is preferable that no crystal grain boundaries are observed in the channel formation region or that the grain boundary components are small. For example, by locating one crystal grain in the channel formation region, a structure in which no crystal grain boundaries are observed in the channel formation region can be achieved. Even in such a structure, the same effects as in a structure in which the indium oxide film is a single crystal film can be achieved.

[0127] Two or more crystal grains may also be located in the channel formation region. For example, when first and second crystal grains are located in the channel formation region, it is preferable that the crystal orientation of the first crystal grain and the crystal orientation of the second crystal grain coincide or substantially coincide. When the crystal orientation of the first crystal grain and the crystal orientation of the second crystal grain coincide or substantially coincide, a crystal grain boundary may not be observed at the boundary between the first crystal grain and the second crystal grain. When the crystal orientation of the first crystal grain and the crystal orientation of the second crystal grain coincide or substantially coincide, the formation of a crystal grain boundary between the first crystal grain and the second crystal grain can be suppressed. Therefore, even in this configuration, the same effect as in the configuration in which the indium oxide film is a single crystal film can be achieved. Note that the coincidence or substantially coincidence of the crystal orientation of the first crystal grain and the crystal orientation of the second crystal grain may be confirmed, for example, by a high-resolution TEM image. Specifically, in a high-resolution TEM image, it can be confirmed that the lattice fringes of the first crystal grains and the lattice fringes of the second crystal grains are continuously connected at the boundary between the first crystal grains and the second crystal grains.

[0128] In this specification, the term "grain boundary" refers to, for example, a boundary between adjacent crystal grains with different crystal orientations. Therefore, in this specification, the term "grain boundary" does not include a boundary between adjacent crystal grains with the same crystal orientation. For example, even if a boundary between two crystal grains is observed in a high-resolution TEM image, if the crystal orientations of the two crystal grains are the same or nearly the same, the boundary may not be called a grain boundary.

[0129] The degree of polycrystallinity of an indium oxide film can be evaluated by the grain size of the crystal grains. The grain size can be calculated, for example, by calculating the area of ​​the crystal grain and assuming a perfect circle corresponding to the calculated area as the diameter of the circle. The diameter in this case is sometimes called the area-equivalent diameter or the like.

[0130] The degree of polycrystallinity of an indium oxide film can also be evaluated by the extension length of the grain boundaries. The extension length of the grain boundaries can be calculated, for example, by extracting a field of view of a specific area from a TEM image of the film acquired at a total magnification at which the grain boundaries can be observed, and calculating the total length of the grain boundaries observed in that field of view. An indium oxide film with a grain boundary extension length of 0 nm can be considered a single-crystal film. Furthermore, the longer the extension length of the grain boundaries, the more grain boundary components there are.

[0131] The extension length of the grain boundary in the indium oxide film is preferably 0 nm to 1500 nm, more preferably 0 nm to 1000 nm, and even more preferably 0 nm to 800 nm. When the semiconductor layer 230 has an indium oxide film with an extension length of the grain boundary in the above range, a configuration in which no crystal grain boundary is observed or only a small amount of grain boundary components can be realized in the channel formation region. Note that, unless otherwise specified in this specification, the area of ​​the field of view used to calculate the extension length of the grain boundary is 90 nm square.

[0132] The thickness of the semiconductor layer 230 is preferably 2 nm to 50 nm, more preferably 2.5 nm to 30 nm, even more preferably 2.5 nm to 20 nm, even more preferably 5 nm to 20 nm, and even more preferably 5 nm to 10 nm. It is preferable that at least a portion of the semiconductor layer 230 has a region with the above-described thickness. For example, it is preferable that the channel formation region of the semiconductor layer 230 has a region with the above-described thickness. By setting the thickness of the semiconductor layer 230 within the above range, the crystallinity of the semiconductor layer 230 can be improved. By improving the crystallinity of the semiconductor layer 230, the semiconductor layer 230 can have crystal grains.

[0133] When a metal oxide contains indium and zinc, the metal oxide may have a c-axis aligned crystalline (CAAC) structure. The CAAC structure has fewer grain boundaries in the a-b plane than a polycrystalline structure. Examples of metal oxides containing indium and zinc include indium zinc oxide (In-Zn oxide, also referred to as IZO (registered trademark)) and indium gallium zinc oxide (In-Ga-Zn oxide, also referred to as IGZO).

[0134] In a crystalline oxide semiconductor layer, an indium oxide film is a film through which one or both of hydrogen and oxygen move more easily than, for example, an IGZO film. Therefore, it can be said that an indium oxide film is a film through which one or both of hydrogen and oxygen are more easily supplied and from which one or both of hydrogen and oxygen are more easily discharged than, for example, an IGZO film. It can be said that an indium oxide film is a film that is more permeable to one or both of hydrogen and oxygen than, for example, an IGZO film. In other words, it can be said that an indium oxide film is a film that has a lower barrier property against one or both of hydrogen and oxygen than, for example, an IGZO film.

[0135] The indium oxide film is formed by heat treatment at a heating temperature of 400° C. for 8 hours, and the oxygen concentration is 1×10 ２０ atoms / cm ３ 2 x 10 or more ２１ atoms / cm ３ Below 2 × 10, preferably ２０ atoms / cm ３ 1x10 or more ２１ atoms / cm ３ Furthermore, the indium oxide film can transmit, for example, 1×10 ２０ atoms / cm ３ 2 x 10 or more ２１ atoms / cm ３ Below 2 × 10, preferably ２０ atoms / cm ３ 1x10 or more ２１ atoms / cm ３It is preferable that the following oxygen has the property of diffusing within the crystal grains.

[0136] Oxygen in the indium oxide film diffuses through the crystal grains and grain boundaries, and V present in the crystal grains or grain boundaries is removed. Ｏ Therefore, the electrical characteristics and reliability of the transistor can be improved.

[0137] The permeability of the membrane to oxygen and hydrogen can be evaluated by calculation using a method called Nudged Elastic Band (NEB). Specifically, the permeability can be evaluated by calculating the migration barrier of oxygen atoms and hydrogen atoms using the NEB method. The smaller the migration barrier value, the easier it is for the atoms to move (permeate).

[0138] An example of the calculation results is shown in Table 1. ２ O ３ is a crystal model of indium oxide, and IGZO shown in Table 1 is a crystal model of In—Ga—Zn oxide. Note that the excess oxygen shown in Table 1 refers to oxygen that is not located at the oxygen site of the crystal lattice or oxygen that is located between the lattices.

[0139]

[0140] From Table 1, it can be seen that the barriers to the movement of oxygen, hydrogen, and excess oxygen are large in the In-Ga-Zn oxide crystal model and small in the indium oxide crystal model. This suggests that oxygen and hydrogen move more easily (permeate more easily) in indium oxide than in In-Ga-Zn oxide. It also suggests that the indium oxide film has higher permeability to oxygen atoms and hydrogen atoms than the In-Ga-Zn oxide film. Therefore, it is presumed that the indium oxide film is a film into which hydrogen and oxygen are easily supplied and from which hydrogen and oxygen are easily discharged. In addition, the V generated in the +GBT test Ｏ It is expected that this will have the effect of filling the gap with oxygen, thereby enabling the realization of highly reliable transistors.

[0141] From the above, as shown in FIG. 5A, an indium oxide film (InO Ｘ Oxygen (O) diffusing into the indium oxide film passes through the indium oxide film and becomes oxygen molecules (O２ ) and are released as water molecules (H ２ In some cases, oxygen atoms are released as oxygen atoms (O). If oxygen vacancies exist in the film, the diffusing oxygen atoms compensate for the oxygen vacancies. Since oxygen easily diffuses in an indium oxide film, it can be said that oxygen vacancies are more easily compensated for in comparison with an IGZO film.

[0142] As described above, an indium oxide film can more easily reduce oxygen vacancies in the film than an IGZO film. Therefore, by using such an indium oxide film in a transistor, a transistor with extremely high reliability can be realized.

[0143] Furthermore, as shown in FIG. 5A, the indium oxide film diffuses hydrogen. Hydrogen that diffuses into the indium oxide film from the outside passes through the indium oxide film and becomes hydrogen molecules (H ２ ) or, as described above, reacts with oxygen contained in the film and is released as water molecules.

[0144] The lower the impurity concentration of the indium oxide film, the more preferable. Impurities in indium oxide can be a scattering source of carriers, which can cause a decrease in field-effect mobility. Furthermore, these impurities can also cause an inhibition of crystal growth of the indium oxide film. Examples of impurities in the indium oxide film include gallium, zinc, boron, aluminum, and silicon. The concentrations of these impurities in the indium oxide film are preferably 1 atomic % or less, more preferably 0.1 atomic % or less, and even more preferably 0.01 atomic % (100 ppm) or less. Carbon, hydrogen, and the like are elements that can be contained in the film-forming gas or precursor during film formation, and may remain in the indium oxide film in greater amounts than the above-mentioned impurities.

[0145] Furthermore, by using a precursor that has been distilled one or more times, it is possible to set the concentration of the first element in the semiconductor layer 230 to 0.01 atomic % (100 ppm) or less, 0.0001% (1 ppm) or less, 0.00001% (0.1 ppm or 100 ppb) or less, or 0.0000001% (0.001 ppm or 1 ppb) or less. That is, the content (purity) of indium excluding oxygen in the semiconductor layer 230 can be set to 99.99 atomic % or more (4N), 99.9999 atomic % or more (6N), 99.99999 atomic % or more (7N), or 99.9999999 atomic % or more (9N), and it is possible to form a semiconductor layer 230 having a purity comparable to the purity (10N) of silicon used in the semiconductor layer.

[0146] By reducing the concentrations of boron, carbon, aluminum, and silicon in the semiconductor layer 230, the crystallinity of the semiconductor layer 230 can be improved.

[0147] When the semiconductor layer 230 contains gallium atoms, the gallium atoms bond with excess oxygen atoms to form a Ga—O structure. The Ga—O structure functions as an acceptor that traps electrons. Therefore, a transistor having a semiconductor layer 230 containing gallium atoms and excess oxygen atoms exhibits a large variation in threshold voltage in a PBTS (Positive Bias Temperature Stress) test. Therefore, by lowering the gallium concentration in the semiconductor layer 230, the variation in threshold voltage in the PBTS test can be reduced. This results in a transistor with high reliability against positive bias application. Note that the same phenomenon as when the semiconductor layer 230 contains zinc atoms may occur.

[0148] Furthermore, aluminum atoms, gallium atoms, and zinc atoms have stronger bonding strength with oxygen atoms than indium atoms, so that by reducing the concentrations of aluminum, gallium, and zinc in the indium oxide film, it is possible to prevent the oxygen permeability from decreasing.

[0149] Furthermore, impurities such as the first element contained in the indium oxide film can become crystal nuclei. Reducing the impurities in the indium oxide film as much as possible reduces the number of crystal nuclei, which can promote the growth of large crystal grains, as described below.

[0150] Furthermore, when the indium oxide film is a polycrystalline film, the first element segregates at the grain boundaries to form an oxide containing the first element. Since the oxide has insulating properties, the on-state current or field-effect mobility of the transistor may be reduced. By reducing the first element in the indium oxide film as much as possible, the on-state current or field-effect mobility of the transistor can be increased.

[0151] By reducing the impurities in the indium oxide film, impurity scattering can be suppressed. Therefore, a transistor with high field-effect mobility can be realized. For example, by setting the concentration of the first element in the semiconductor layer 230 in the above preferred range, the field-effect mobility of the transistor can be increased to 50 cm ２ / (V・s) or more, 100cm ２ / (V·s) or more, preferably 150 cm ２ / (V·s) or more, more preferably 200 cm ２ / (V·s) or more, more preferably 250 cm ２ / (V·s) or more.

[0152] The carrier concentration dependence of the Hall mobility of indium oxide, silicon, and IGZO will be explained. FIG. 5A shows the carrier concentration dependence of the Hall mobility of silicon (Si) and indium oxide (InO Ｘ ) and FIG. 5B is a schematic diagram showing the carrier concentration dependence of the hole mobility for IGZO.

[0153] First, IGZO tends to exhibit higher hole mobility as the carrier concentration increases, as shown by the arrows in Figure 5B. On the other hand, indium oxide tends to exhibit higher hole mobility as the carrier concentration decreases, as shown by the arrows in Figure 5A (see Non-Patent Document 2). This trend is similar to that of silicon; the lower the dopant (impurity) concentration in the material, the less impurity scattering there is and the higher the hole mobility. In other words, the higher the purity and intrinsic indium oxide, the higher the hole mobility. From these results, it can be said that indium oxide, unlike IGZO, is a material with physical properties similar to those of silicon. Note that the characteristics of indium oxide shown in Figure 5A are assumed to be single crystal. Therefore, when indium oxide is non-single crystal (e.g., polycrystalline), the characteristics may differ from those shown in Figure 5A.

[0154] 5A, the range R1 of low carrier concentration has extremely high hole mobility, and therefore can be said to be a range of carrier concentration suitable for, for example, a channel formation region of a transistor. For example, in the case of indium oxide, the range R1 is a range where the carrier concentration value is 1×10 １５ cm −３ The range includes, for example, 1×10 １４ cm −３ That's it, 1 x 10 １８ cm −３ By sufficiently reducing the carrier concentration, the Hall mobility can be reduced to 270 cm ２ It is expected that the resistance can be increased to about / (V·s).

[0155] In addition, in indium oxide, the region where the carrier concentration is in the range R1 may contain an element that lowers the carrier concentration. Examples of elements that lower the carrier concentration include magnesium, calcium, zinc, cadmium, and copper. By substituting these elements for indium, the carrier concentration can be lowered. Examples of elements that lower the carrier concentration include nitrogen, phosphorus, arsenic, and antimony. For example, by substituting nitrogen, phosphorus, arsenic, or antimony for oxygen, the carrier concentration can be lowered.

[0156] On the other hand, the range R2 with a high carrier concentration has a low electrical resistance, and can be said to be a range of carrier concentrations suitable for, for example, the source and drain regions of a transistor, a resistor, or a transparent conductive film. ２０ cm −３ The range includes, for example, 1×10 １９ cm −３ That's it, 1 x 10 ２２ cm −３ By increasing the carrier concentration sufficiently, the resistivity can be reduced to 1×10 −４ It is expected that the resistance can be reduced to Ω·cm or less.

[0157] In addition, in indium oxide, the region where the carrier concentration is in the range R2 may contain an element that increases the carrier concentration. For example, it is preferable that the indium oxide contains an element that is common to the source electrode and drain electrode of the transistor. Examples of elements that increase the carrier concentration include titanium, zirconium, hafnium, tantalum, tungsten, molybdenum, tin, silicon, and boron. In particular, it is more preferable to use an element whose oxide has conductive or semiconducting properties. Note that, as a method for supplying an element that increases the carrier concentration, a method of forming a film containing the element and diffusing it, ion implantation, ion doping, plasma immersion ion implantation, or plasma treatment can be used. Note that, unless otherwise specified in this specification, the presence or absence of mass separation is not limited. For example, in this specification, a method of supplying ions after mass separation is referred to as an ion implantation method, and a method of supplying ions without mass separation is referred to as an ion doping method.

[0158] In this way, indium oxide uses a region with a low carrier concentration as the channel formation region of a transistor, and a region with a high carrier concentration as the source and drain regions of the transistor. In other words, indium oxide can be said to be an oxide capable of valence electron control. Note that IGZO may experience strain in the source and drain regions due to stress from electrodes in contact with the IGZO, resulting in the formation of n-type regions. On the other hand, unlike IGZO, indium oxide is capable of valence electron control, and therefore does not require strain to be formed in the film as with IGZO. Less strain in the film is expected to improve reliability. For example, by separately creating a region with a carrier concentration in the range R1 shown in FIG. 5A and a region with a carrier concentration in the range R2 in the indium oxide film, a so-called n-i-n junction (a junction between an n-type region, an i-type region, and an n-type region) can be created. Note that valence electron control in transistors using silicon is generally known. On the other hand, valence electron control in transistors using indium oxide is a novel technical concept that would not normally be conceived.

[0159] By using the above technical concept, the transistor having indium oxide in this specification and the like has two or more, preferably three or more, more preferably four or more, and most preferably five of the following characteristics (1) to (5): (1) high on-current (in other words, high mobility); (2) low off-current; (3) normally-off operation; (4) high reliability; and (5) high cutoff frequency (fT). For example, the transistor having indium oxide in this specification and the like has high mobility, low off-current, and is normally-off operation. The transistor has high mobility and is different from a normally-on transistor.

[0160] In addition, a semiconductor being i-type can be rephrased as having the same Fermi level (Ef) and intrinsic Fermi level (Ei) (Ef = Ei). As shown in FIG. 5B, in IGZO, the lower the carrier concentration, the smaller the hole mobility. Therefore, when Ef = Ei is finally achieved, the carriers disappear (in other words, the physical properties become similar to those of an insulator), and the semiconductor may no longer function as a transistor. On the other hand, in indium oxide, as shown in FIG. 5A, the lower the carrier concentration, the larger the hole mobility. When Ef = Ei is finally achieved, the hole mobility is maximized. In other words, a transistor containing indium oxide can achieve high field-effect mobility by setting Ef = Ei. Note that a transistor containing indium oxide is likely to be normally-off due to its low carrier concentration. Therefore, a transistor containing indium oxide can be normally-off and achieve high field-effect mobility.

[0161] Note that normally-off refers to a state in which no current flows through a transistor when no potential is applied to the gate or when the gate-source voltage is 0 V. Furthermore, normally-off can be evaluated by the threshold voltage (Vth) or shift value (Vsh) of the transistor. Unless otherwise specified, Vth is calculated by a constant current method. More specifically, Vth refers to a state in which the value of drain current (Id) × channel length (L) ÷ channel width (W) in the Id-Vg characteristics of a transistor is 1 nA (1 × 10 −９ A). Vsh is the gate voltage (Vg) when the drain current (Id) in the Id-Vg characteristic of the transistor is expressed logarithmically and the tangent of the maximum slope is Id = 1 pA (1 × 10 −１２ The gate voltage (Vg) is the intersection point between the line of Id = 1 pA and the line extrapolated from two points where the slope of Id is maximum when Id is expressed logarithmically in the Id-Vg characteristics of the transistor. For example, if either or both of Vth and Vsh are zero or a positive value, the transistor can be considered to be normally-off.

[0162] One of the features of an indium oxide film is that it has higher oxygen permeability (diffusibility) than an IGZO film. As shown in FIG. 5C, an indium oxide film (InO Ｘ Oxygen (O) diffusing into the indium oxide film passes through the indium oxide film and becomes oxygen molecules (O ２ ) and is released as water molecules (H ２ O) may be released in the film. Ｏ In the case where an indium oxide film is present, oxygen atoms diffuse to compensate for the oxygen vacancies. Since oxygen diffuses easily in the indium oxide film, it can be said that oxygen vacancies are more easily compensated for in the indium oxide film than in the IGZO film.

[0163] As described above, an indium oxide film can more easily reduce oxygen vacancies in the film than an IGZO film. Therefore, by using such an indium oxide film in a transistor, a transistor with extremely high reliability can be realized.

[0164] Furthermore, as shown in FIG. 5C, the indium oxide film diffuses hydrogen. Hydrogen that diffuses into the indium oxide film from the outside passes through the indium oxide film and becomes hydrogen molecules (H ２ ) or reacts with oxygen contained in the membrane and is released as water molecules.

[0165] The concentration of the first element can be evaluated using, for example, ICP-MS, XPS, SIMS, ToF-SIMS, AES, EDX, or ICP-AES.

[0166] Hydrogen contained in the oxide semiconductor reacts with oxygen bonded to metal atoms to form water, which may cause oxygen vacancies. This may result in fluctuations in electrical characteristics and reduced reliability. On the other hand, hydrogen present at the grain boundaries may terminate dangling bonds present at the grain boundaries, improving the electrical characteristics and reliability of the transistor. Therefore, it is preferable that the hydrogen concentration in the indium oxide film be reduced, but it may be higher than the concentration of the first element in some cases.

[0167] The band gap of indium oxide is greater than or equal to 2.5 eV and less than or equal to 3.7 eV. By using indium oxide with a wide band gap for the semiconductor layer 230, the off-state current of the transistor can be reduced, and the power consumption of the semiconductor device can be sufficiently reduced.

[0168] A transistor using an indium oxide film is an accumulation-type transistor that uses electrons as majority carriers. Assuming that the carrier relaxation time is constant, the smaller the effective mass of the electrons (carriers), the higher the electron mobility. In other words, by using indium oxide, which has a small effective mass of electrons, for a transistor, the on-state current or field-effect mobility of the transistor can be increased.

[0169] Table 2 shows the results of single crystal indium oxide (here, In ２ O ３ ) and single-crystal silicon (Si). As shown in Table 2, indium oxide is characterized by a small effective mass of electrons and a large effective mass of holes. Indium oxide also has the characteristic that the effective mass of electrons is almost independent of the crystal orientation. Therefore, by using crystalline indium oxide in a transistor, a transistor with high field-effect mobility and high frequency characteristics (also called f characteristics) can be realized. Furthermore, since the effective mass of holes is large, a transistor with extremely small off-current can be realized. For example, by applying an indium oxide film to a vertical transistor, the off-current per 1 μm of channel width can be reduced to 1 fA (1×10) in an environment of 125° C. −１５ A) or less, or 1aA (1 x 10 −１８ A) or less, and under room temperature (25°C) conditions, −１８ A) or less, or 1zA (1 x 10 −２１ Furthermore, as shown in Table 2, indium oxide has a smaller effective mass of electrons and a larger effective mass of holes than silicon, and therefore may be able to realize a transistor with higher field-effect mobility and lower off-state current than a Si transistor.

[0170]

[0171] Furthermore, miniaturization of an OS transistor can improve the high-frequency characteristics of the transistor. For example, the cutoff frequency of the transistor can be increased. Specifically, the cutoff frequency of the transistor can be set to 50 GHz or higher, preferably 100 GHz or higher, and more preferably 150 GHz or higher at room temperature.

[0172] An insulating layer containing excess oxygen is provided near the semiconductor layer 230, and heat treatment is performed to supply oxygen from the insulating layer to the semiconductor layer 230, thereby eliminating oxygen vacancies and V Ｏ H can be reduced. However, if an excessive amount of oxygen is supplied to the low-resistance region 230na or the low-resistance region 230nb, this may cause a decrease in the on-state current or a decrease in field-effect mobility of the transistor 200. Furthermore, variations in the amount of oxygen supplied to the low-resistance region 230na or the low-resistance region 230nb within the substrate surface may cause variations in the characteristics of a semiconductor device including the transistor 200. Furthermore, if the amount of oxygen supplied from the insulating layer to the semiconductor layer 230 becomes excessively large, this may adversely affect the electrical characteristics and reliability of the transistor 200. Furthermore, oxygen may diffuse into the conductive layer 260, the conductive layer 243a, the conductive layer 243b, etc., causing these conductive layers to oxidize and lose their conductivity.

[0173] First, at least one of an insulating layer having a barrier property against hydrogen and an insulating layer having a function of capturing or fixing hydrogen is formed near the semiconductor layer 230, and V in the channel formation region 230i of the semiconductor layer 230 and its vicinity is formed. Ｏ It is preferable to reduce H.

[0174] At least one of the insulating layer 212, the insulating layer 214, the insulating layer 221, the insulating layer 222, the insulating layer 275, the insulating layer 282, and the insulating layer 283 preferably functions as a barrier insulating layer against hydrogen. At least one of the insulating layer 212, the insulating layer 214, the insulating layer 221, the insulating layer 222, the insulating layer 275, the insulating layer 282, and the insulating layer 283 preferably functions as a barrier insulating layer against impurities. At least one of the insulating layer 212, the insulating layer 214, the insulating layer 221, the insulating layer 222, the insulating layer 275, the insulating layer 282, and the insulating layer 283 preferably functions as a barrier insulating layer against oxygen. Note that all of the insulating layer 212, the insulating layer 214, the insulating layer 221, the insulating layer 222, the insulating layer 275, the insulating layer 282, and the insulating layer 283 do not necessarily need to be provided. As long as the insulating layer has sufficient barrier properties against hydrogen, impurities, oxygen, and the like, the insulating layer can be formed by appropriately selecting from the insulating layer 212, the insulating layer 214, the insulating layer 221, the insulating layer 222, the insulating layer 275, the insulating layer 282, and the insulating layer 283. For example, a structure can be used in which the insulating layer 216 and the conductive layer 205 are formed in contact with the upper surface of the insulating layer 212 without providing the insulating layer 214.

[0175] In this specification and the like, a barrier insulating layer refers to an insulating layer having barrier properties. The barrier properties are defined as a property that makes it difficult for a corresponding substance to diffuse (also referred to as a property that makes it difficult for a corresponding substance to permeate, a property that the permeability of a corresponding substance is low, or a function that suppresses the diffusion of a corresponding substance). Note that hydrogen when described as a corresponding substance includes, for example, a hydrogen atom, a hydrogen molecule, a water molecule, and OH. − Furthermore, unless otherwise specified, impurities when described as corresponding substances refer to impurities in the channel formation region or semiconductor layer, and include, for example, hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, and nitrogen oxide molecules (N ２ O, NO, and NO ２ The term "oxygen" when used in reference to a corresponding substance refers to at least one of an oxygen atom, an oxygen molecule, and the like.

[0176] It is preferable that the insulating layer 212, the insulating layer 221, the insulating layer 275, and the insulating layer 283 have a function of suppressing diffusion of hydrogen. For example, it is preferable that the insulating layer 212, the insulating layer 221, the insulating layer 275, and the insulating layer 283 be made of silicon nitride, which has a higher hydrogen barrier property.

[0177] The insulating layer 214, the insulating layer 222, and the insulating layer 282 preferably have a function of capturing or fixing hydrogen. For example, aluminum oxide is preferably used for the insulating layer 214 and the insulating layer 282. Furthermore, for example, hafnium oxide, which is a high-k material, is preferably used for the insulating layer 222 that functions as the second gate insulating layer.

[0178] By providing the insulating layer 212 having a function of suppressing hydrogen diffusion under the transistor 200, it is possible to suppress diffusion of hydrogen from layers below the transistor 200. Furthermore, by providing the insulating layer 214 having a function of capturing or fixing hydrogen, hydrogen contained in the insulating layer 216 or the like can be captured or fixed in the insulating layer 214. This makes it possible to reduce the hydrogen concentration in the semiconductor layer 230 and its vicinity.

[0179] Furthermore, by providing the insulating layer 221 having a function of suppressing hydrogen diffusion under the semiconductor layer 230, it is possible to suppress diffusion of hydrogen from below the semiconductor layer 230. Furthermore, by providing the insulating layer 222 having a function of capturing or fixing hydrogen, hydrogen contained in the insulating layer 224 or the like can be captured or fixed in the insulating layer 222. This makes it possible to reduce the hydrogen concentration in the semiconductor layer 230 and its vicinity.

[0180] Furthermore, by providing the insulating layer 275 having a function of suppressing diffusion of hydrogen so as to cover the semiconductor layer 230 , diffusion of hydrogen from the insulating layer 280 to the semiconductor layer 230 can be suppressed.

[0181] Furthermore, by providing the insulating layer 283 having a function of suppressing hydrogen diffusion over the transistor 200, it is possible to suppress diffusion of hydrogen from above the transistor 200. Furthermore, by providing the insulating layer 282 having a function of capturing or fixing hydrogen, hydrogen contained in the insulating layer 280 or the like can be captured or fixed to the insulating layer 282. This makes it possible to reduce the hydrogen concentration in the semiconductor layer 230 and its vicinity.

[0182] In this way, by using a structure in which the transistor 200 is surrounded by barrier insulating layers against hydrogen from above and below, the diffusion of hydrogen into the semiconductor layer 230 is reduced, and the V Ｏ H can be reduced. As a result, the electrical characteristics and reliability of the transistor 200 can be improved.

[0183] Furthermore, excess oxygen is preferably contained in one or both of the insulating layer 224 and the insulating layer 280. By performing heat treatment on the insulating layer 224 containing excess oxygen, a suitable amount of oxygen can be supplied to the semiconductor layer 230. Furthermore, by performing heat treatment on the insulating layer 280 containing excess oxygen, a suitable amount of oxygen can be supplied to the semiconductor layer 230 through the insulating layer 250. As described above, oxygen vacancies in the channel formation region 230i can be reduced.

[0184] In the above-described heat treatment, it is preferable that at least one of the insulating layer 222, the insulating layer 221, the insulating layer 214, and the insulating layer 212 under the insulating layer 224 has a barrier property against oxygen, because the oxygen contained in the insulating layer 224 can be prevented from excessively diffusing from the insulating layer 280. Furthermore, in the above-described heat treatment, it is preferable that one or both of the insulating layer 282 and the insulating layer 283 over the insulating layer 280 have a barrier property against oxygen, because the oxygen contained in the insulating layer 280 can be prevented from excessively diffusing from the insulating layer 280. Furthermore, it is preferable that the insulating layer 275 has a barrier property against oxygen, because the oxygen contained in the insulating layer 224 can be prevented from excessively diffusing from the insulating layer 224 and the oxygen contained in the insulating layer 280 can be prevented from excessively diffusing from the insulating layer 280. By performing the heat treatment with openings formed in parts of the insulating layer 280, the insulating layer 282, and the insulating layer 283, it is possible to diffuse some of the oxygen contained in the insulating layer 280 outward, thereby adjusting the amount of oxygen supplied from the insulating layer 280 to the semiconductor layer 230.

[0185] The insulating layer 250 preferably has a structure that allows oxygen to diffuse from the insulating layer 280 to the semiconductor layer 230 and prevents the conductive layer 260 from being oxidized.

[0186] The insulating layer 250 is formed in the opening 289 in contact with the top surface of the insulating layer 222 , the side surface of the insulating layer 224 , the side surface and top surface of the semiconductor layer 230 , the side surface of the insulating layer 275 , and the side surface of the insulating layer 280 .

[0187] 6A illustrates an example in which the insulating layer 250, the conductive layer 205, the conductive layer 260, the conductive layer 243a, and the conductive layer 243b included in the transistor 200A illustrated in FIG. 2A have a stacked structure of two or more layers. The stacked structure example illustrated in FIG. 6A can also be applied to the transistor 200B and the transistor 200C.

[0188] As shown in FIG. 6A, the insulating layer 250 preferably has a stacked structure of an insulating layer 250_1 in contact with the semiconductor layer 230, an insulating layer 250_2 over the insulating layer 250_1, and an insulating layer 250_3 over the insulating layer 250_2.

[0189] 6B is a cross-sectional view showing a configuration example of the insulating layer 224, the semiconductor layer 230, the insulating layer 275, the insulating layer 280, the insulating layer 250, the conductive layer 260, the insulating layer 282, and the insulating layer 283. Also, FIG. 6B shows an example in which the insulating layer 250 has a stacked structure of an insulating layer 250_1, an insulating layer 250_2 on the insulating layer 250_1, an insulating layer 250_4 on the insulating layer 250_2, and an insulating layer 250_3 on the insulating layer 250_4. In this case, the insulating layer 250_1 is formed in the opening 289 in contact with the top surface of the insulating layer 222, the side surface of the insulating layer 224, the side surface and top surface of the semiconductor layer 230, the side surface of the insulating layer 275, and the side surface of the insulating layer 280.

[0190] The insulating layer 250_1 can be formed using any of the materials that can be used for the insulating layer 250. The insulating layer 250_1 can have a function of capturing or fixing oxygen. By providing the insulating layer 250_1 between the insulating layer 280 and the insulating layer 250_2 and between the insulating layer 250_2 and the semiconductor layer 230, excessive supply of oxygen from the insulating layer 280 to the semiconductor layer 230 can be suppressed, and an appropriate amount of oxygen can be supplied to the semiconductor layer 230. Therefore, the amount of oxygen in and around the channel formation region 230i can be appropriately controlled, thereby preventing an excessive positive shift of the transistor 200 and improving reliability. Furthermore, excessive oxidation of the low-resistance region 230na and the low-resistance region 230nb can be suppressed, which can reduce the on-state current or the field-effect mobility of the transistor 200.

[0191] By adopting the above-described structure, the channel formation region 230i can be made i-type or substantially i-type, and the low-resistance region 230na and the low-resistance region 230nb can be made, for example, n-type, thereby providing a semiconductor device with excellent electrical characteristics. Furthermore, by adopting the above-described structure, the semiconductor device can have excellent electrical characteristics even when miniaturized or highly integrated. Furthermore, miniaturizing the transistor 200 can improve high-frequency characteristics. Specifically, the cutoff frequency can be improved.

[0192] It is also preferable to use a high-k material with a high relative dielectric constant for the insulating layer 250_1. An example of a high-k material is an oxide containing one or both of aluminum and hafnium. Using a high-k material for the insulating layer 250_1 makes it possible to reduce the gate potential applied during transistor operation while maintaining the physical thickness of the gate insulating layer. Furthermore, it is possible to reduce the equivalent oxide thickness (EOT) of the insulating layer that functions as the gate insulating layer.

[0193] From the above, it is preferable to use an oxide containing at least one of aluminum, magnesium, and hafnium for the insulating layer 250_1, and it is more preferable to use an oxide having an amorphous structure and containing at least one of aluminum, magnesium, and hafnium. For example, aluminum oxide, magnesium oxide, or hafnium oxide is preferably used for the insulating layer 250_1. Aluminum oxide having an amorphous structure is more preferably used because an amorphous film of aluminum oxide can be formed relatively easily by using an ALD method. In this embodiment, aluminum oxide is used for the insulating layer 250_1. Aluminum oxide has a function of capturing or fixing oxygen and hydrogen, and therefore can be suitably used for the insulating layer 250_1.

[0194] Furthermore, even when magnesium is supplied to the semiconductor layer 230 as an impurity element, no levels are formed in the band gap. Therefore, by using magnesium oxide as the insulating layer 250_1, trap levels at the interface between the semiconductor layer 230 and the insulating layer 250 and in the vicinity thereof can be reduced. This makes it possible to realize a buried-channel transistor 200 in which the channel is spaced away from the insulating layer interface, thereby increasing the field-effect mobility. Furthermore, the influence of interface states that may be formed on the back channel side can be reduced, which can suppress photodegradation (e.g., photodegradation due to negative bias current) of the transistor 200 and improve the reliability of the transistor 200.

[0195] For example, the insulating layer 250_2 preferably includes a material with a low dielectric constant, such as a silicon oxide film or a silicon oxynitride film.

[0196] Silicon oxide or silicon nitride is an insulating material with high dielectric strength. This can reduce the leakage current of a transistor. Furthermore, a silicon oxide film or a silicon oxynitride film is also a film with high hydrogen permeability. Therefore, the insulating layer 250 may have a three-layer structure including an insulating layer 250_2, an insulating layer 250_1 on the insulating layer 250_2, and an insulating layer 250_3 on the insulating layer 250_1. With this structure, hydrogen in the semiconductor layer 230 can diffuse into the insulating layer 250_1 through the insulating layer 250_2 and be captured or fixed. Therefore, the hydrogen concentration in the semiconductor layer 230 can be reduced.

[0197] The insulating layer 250_3 preferably has a barrier property against hydrogen. With such a structure, diffusion of hydrogen into the semiconductor layer 230 can be suppressed. Furthermore, the insulating layer 250_3 preferably has a barrier property against oxygen. The insulating layer 250_3 is provided between the channel formation region 230i and the conductive layer 260. With such a structure, oxygen contained in the channel formation region 230i can be prevented from diffusing into the conductive layer 260 and forming oxygen vacancies in the channel formation region 230i. Furthermore, oxygen contained in the semiconductor layer 230 can be prevented from diffusing into the conductive layer 260 and oxidizing the conductive layer 260. The insulating layer 250_3 is preferably at least less permeable to oxygen than the insulating layer 250_2. Furthermore, the insulating layer 250_3 preferably has a function of suppressing diffusion of hydrogen. This can prevent impurities such as hydrogen contained in the conductive layer 260 from diffusing into the semiconductor layer 230. For example, silicon nitride is preferably used as the insulating layer 250_3.

[0198] The insulating layer 250_4 can be formed using an insulating material that can be used for the insulating layer 250_1. For example, the insulating layer 250_4 preferably has a function of capturing or fixing hydrogen. By providing the insulating layer 250_4 between the insulating layer 250_3 and the insulating layer 250_2, hydrogen contained in the insulating layer 250_2 and the like can be more effectively captured or fixed.

[0199] Specifically, the insulating layer 250 preferably has a four-layer structure in which an aluminum oxide film, a silicon oxide film, a hafnium oxide film, and a silicon nitride film are stacked in this order from the semiconductor layer 230 side. With such a structure, hydrogen in the semiconductor layer 230 can be diffused to the insulating layer 250_1 or the insulating layer 250_4 and captured or fixed. Therefore, the hydrogen concentration in the semiconductor layer 230 can be reduced.

[0200] The insulating layer 250 is preferably a thin film. For example, the subthreshold swing value (also referred to as S value) can be reduced by setting the thickness of the insulating layer 250 to 1 nm or more and 20 nm or less, preferably 3 nm or more and 10 nm or less. Note that the S value refers to the amount of change in gate voltage when the drain current is changed by one order of magnitude with the drain voltage held constant in the subthreshold region.

[0201] Furthermore, in order to miniaturize the transistor 200, the insulating layers 250_1 to 250_4 preferably have thin film thicknesses. The insulating layers 250_1 to 250_4 each have a film thickness of preferably 0.1 nm to 20 nm, more preferably 0.1 nm to 10 nm, more preferably 0.5 nm to 5.0 nm, more preferably 1.0 nm to less than 5.0 nm, and still more preferably 1.0 nm to 3.0 nm. Note that each of the insulating layers 250_1 to 250_4 preferably has a region with the above film thickness in at least a portion thereof.

[0202] Note that the insulating layer 250 may have a four-layer structure without the insulating layer 250_3. For example, an insulating layer having a function of capturing or fixing oxygen can be used as the insulating layer 250_1, an insulating layer containing a material with a low dielectric constant can be used as the insulating layer 250_2, and an insulating layer having a function of capturing or fixing hydrogen can be used as the insulating layer 250_4. Specifically, the insulating layer 250 can have a three-layer structure in which an aluminum oxide film, a silicon oxide film, and a hafnium oxide film are stacked in this order from the semiconductor layer 230 side.

[0203] In order to thin the insulating layers 250_1 to 250_4 as described above, the insulating layers 250_1 to 250_4 are preferably deposited by an ALD method. In addition, in order to form the insulating layers 250_1 to 250_4 in the opening 289 with good coverage, the insulating layers 250_1 to 250_4 are preferably deposited by an ALD method.

[0204] It is preferable to use the ALD process two or more times in forming the insulating layer 250 having a stacked structure of multiple insulating films. For example, it is preferable that two or more of the multiple insulating films included in the insulating layer 250 are formed using the ALD process. By forming at least two or more types of insulating films using the ALD process, it is possible to improve the coverage and film thickness uniformity of the insulating layer 250. Furthermore, for example, it is possible to increase productivity by successively forming two or more types of insulating films using the ALD process.

[0205] Note that although the above description has been given of a structure in which the insulating layer 250 has a three-layer structure of insulating layers 250_1 to 250_3 or a four-layer structure of insulating layers 250_1 to 250_4, the present invention is not limited to this. The insulating layer 250 may have a single-layer structure, a two-layer structure, or a stacked structure of five or more layers. The insulating layer 250 can have a structure including at least one of the insulating layers 250_1 to 250_4. The insulating layer 250 can have, for example, a two-layer structure of the insulating layer 250_2 and the insulating layer 250_3 or 250_4 over the insulating layer 250_2. In this case, the insulating layer 250 can have, for example, a two-layer structure of a silicon oxide film and a silicon nitride film or a hafnium oxide film over the silicon oxide film.

[0206] When the insulating layer 250 is formed using one, two, or three of the insulating layers 250_1 to 250_4, the manufacturing process of the semiconductor device can be simplified and productivity can be improved.

[0207] The conductive layer 205 is disposed so as to have a region overlapping with the semiconductor layer 230 and the conductive layer 260. The conductive layer 205 can be formed using a conductive material described in the section [Conductive Layer] below. Here, the conductive layer 205 is provided so as to be embedded in an opening formed in the insulating layer 216. The conductive layer 205 is preferably provided so as to extend in the channel width direction, as shown in FIG. 1A , for example. With this structure, the conductive layer 205 functions as a wiring when a plurality of transistors 200 are provided.

[0208] 6A , the conductive layer 205 preferably includes a conductive layer 205_1 and a conductive layer 205_2. The conductive layer 205_1 is provided in contact with the bottom surface and sidewall of the opening. The conductive layer 205_2 is provided so as to fill a recess in the conductive layer 205_1 formed along the opening. Here, the height of the top surface of the conductive layer 205 is the same as or approximately the same as the height of the top surface of the insulating layer 216.

[0209] Here, the conductive layer 205_1 contains hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, and nitrogen oxide molecules (N ２ O, NO, NO ２It is preferable to have a conductive material that has a function of suppressing the diffusion of impurities such as copper atoms, etc., or a conductive material that has a function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms, oxygen molecules, etc.).

[0210] By using a conductive material that can reduce hydrogen diffusion for the conductive layer 205_1, impurities such as hydrogen contained in the conductive layer 205_2 can be prevented from diffusing into the semiconductor layer 230 through the insulating layer 216 or the like. Furthermore, by using a conductive material that can suppress oxygen diffusion for the conductive layer 205_1, oxidation of the conductive layer 205_2 and a decrease in conductivity can be suppressed. Examples of conductive materials that can suppress oxygen diffusion include titanium, titanium nitride, tantalum, tantalum nitride, ruthenium, and ruthenium oxide. The conductive layer 205_1 can have a single-layer structure or a stacked-layer structure of the above conductive materials. For example, the conductive layer 205_1 preferably contains titanium nitride.

[0211] The conductive layer 205_2 is preferably formed using a conductor with high conductivity. For example, the conductive layer 205_2 is preferably formed using a conductive material containing tungsten, copper, or aluminum as a main component. For example, the conductive layer 205_2 preferably contains tungsten.

[0212] The conductive layer 205 can function as a second gate electrode. In this case, the threshold voltage (Vth) of the transistor 200 can be controlled by changing the potential applied to the conductive layer 205 independently of the potential applied to the conductive layer 260. In particular, applying a negative potential to the conductive layer 205 can increase the Vth of the transistor 200 and reduce the off-state current. Therefore, applying a negative potential to the conductive layer 205 can reduce the drain current when the potential applied to the conductive layer 260 is 0 V, compared to when no negative potential is applied.

[0213] 6A shows a stacked structure of the conductive layer 205_1 and the conductive layer 205_2, the present invention is not limited thereto, and the conductive layer 205 may have a single-layer structure or a stacked structure of three or more layers. For example, the conductive layer 205_1 may have a two-layer structure of a tantalum nitride film and a titanium nitride film on the tantalum nitride film, and the conductive layer 205_2 having a tungsten film may be provided on the conductive layer 205_1. With such a structure, impurities such as hydrogen and metal impurities such as copper contained in the lower layer of the transistor 200 can be prevented from diffusing into the conductive layer 205.

[0214] The insulating layer 224 functions as a second gate insulating layer together with the insulating layers 221 and 222 .

[0215] The insulating layer 224 preferably includes, for example, a silicon oxide film or a silicon oxynitride film. This allows oxygen to be supplied from the insulating layer 224 to the semiconductor layer 230, thereby reducing oxygen vacancies. The insulating layer 224 may also include an aluminum oxide film. In this case, the insulating layer 224 can have a function of capturing or fixing oxygen and hydrogen. The insulating layer 224 may have a stacked structure of two or more layers. In this case, the insulating layer 224 is not limited to a stacked structure made of the same material, and may have a stacked structure made of different materials. The insulating layer 224 may have, for example, a two-layer stacked structure of a silicon oxide film and an aluminum oxide film on the silicon oxide film.

[0216] Furthermore, it is preferable to use a material for the insulating layer 224 that has a smaller thermal expansion coefficient than the metal oxide used for the semiconductor layer 230. For example, a material for the insulating layer 224 that has a smaller thermal expansion coefficient than indium oxide can be used. Specifically, the thermal expansion coefficient of the insulating layer 224 is 0.01×10 −６ K −１ 5.5 x 10 −６ K −１ Preferably, it is less than 0.01 × 10 −６ K −１ Above 5.0 x 10 −６ K −１ Preferably, it is less than 0.01 × 10 −６ K −１Above 3.0 x 10 −６ K −１ More preferably, 0.01 x 10 or less −６ K −１ Above 1.0 x 10 −６ K −１ The following is even more preferable. With this structure, the semiconductor layer 230 containing indium oxide is in contact with or located near the insulating layer 224 having a small thermal expansion coefficient, and thus tensile stress is applied to the indium oxide when the temperature is lowered, making the indium oxide energetically unstable. As a result, the indium oxide becomes a cubic crystal, which is more energetically stable. This promotes crystal growth, allowing the formation of cubic crystals with large grain sizes. Silicon oxide has a smaller thermal expansion coefficient than indium oxide, and is therefore suitable for use as the insulating layer 224.

[0217] The insulating layer 224 is preferably processed into an island shape, similar to the semiconductor layer 230. Thus, when a plurality of transistors 200 are provided, each transistor 200 has an insulating layer 224 of approximately the same size. As a result, the amount of oxygen supplied from the insulating layer 224 to the semiconductor layer 230 in each transistor 200 becomes approximately the same. Therefore, variation in the electrical characteristics of the transistors 200 within the substrate surface can be suppressed.

[0218] Furthermore, by providing the insulating layer 224 in an island shape, at least a part of the lower surface of the conductive layer 260 can be provided below the lower surface of the semiconductor layer 230 (see FIG. 1C ). This allows the conductive layer 260 to be provided facing the upper surface and side surface of the semiconductor layer 230, and therefore the electric field of the conductive layer 260 can be applied to the upper surface and side surface of the semiconductor layer 230. Therefore, in a cross-sectional view in the channel width direction, the channel formation region 230i can be formed not only on the upper surface but also along the side surface of the semiconductor layer 230.

[0219] However, the insulating layer 224 does not necessarily have to be processed into an island shape. For example, as shown in Figures 7A to 7C, the insulating layer 224 may not be formed into an island shape, but may have a shape in which an opening is formed in a part of it. Here, Figures 7A, 7B, and 7C correspond to Figures 1B, 1C, and 1D, respectively. Note that Figure 1A can be referred to for plan views of the semiconductor device shown in Figures 7A to 7C.

[0220] 7A to 7C , the thickness of the insulating layer 224 in a region that does not overlap with the semiconductor layer 230 is thinner than the thickness of the region that overlaps with the semiconductor layer 230. In addition, the insulating layer 224 has an opening in a region that does not overlap with the semiconductor layer 230 and overlaps with the insulating layer 250. When multiple transistors are provided over the same substrate, providing the insulating layer 224 in this manner allows the semiconductor layer 230 of each transistor to be provided over the same insulating layer 224. This can reduce variation in the amount of oxygen supplied from the insulating layer 224 to the semiconductor layer 230 of each transistor. Therefore, variation in the electrical characteristics of each transistor can be reduced.

[0221] For example, in the insulating layer 224 shown in FIG. 7B, an opening is formed in the region that does not overlap with the semiconductor layer 230 and overlaps with the insulating layer 250, but the opening may not be provided.

[0222] The conductive layer 260 can be made of the conductive material described in the section [Conductive Layer] below. In particular, it is preferable to use a conductive material that is resistant to oxidation or a conductive material that has the function of suppressing oxygen diffusion as the conductive layer 260. Examples of such conductive materials include a conductive material containing nitrogen and a conductive material containing oxygen. This can suppress a decrease in the conductivity of the conductive layer 260.

[0223] The conductive layer 260 is provided in the opening 289 so as to cover the top surface of the insulating layer 222 , the side surface of the insulating layer 224 , and the side and top surfaces of the semiconductor layer 230 with the insulating layer 250 interposed therebetween.

[0224] The sidewall of the opening 289 may be perpendicular or approximately perpendicular to the upper surface of the insulating layer 222, or may be tapered. By tapering the sidewall, the coverage of the insulating layer 250 provided in the opening 289 is improved, and defects such as voids can be reduced.

[0225] 1A, the conductive layer 260 is preferably provided to extend in the channel width direction. With this structure, when a plurality of transistors 200 are provided, the conductive layer 260 functions as a wiring.

[0226] The conductive layer 260 is preferably made of a highly conductive material such as titanium, aluminum, or tungsten. Furthermore, it is preferable to use a conductive material that is resistant to oxidation or a conductive material that has the function of suppressing oxygen diffusion as the conductive layer 260. Examples of such conductive materials include conductive materials containing nitrogen (e.g., titanium nitride or tantalum nitride) and conductive materials containing oxygen (e.g., ruthenium oxide). This can suppress a decrease in the conductivity of the conductive layer 260.

[0227] The conductive layer 260 is preferably made of a conductive material containing oxygen and the metal element contained in the semiconductor layer 230. That is, the conductive layer 260 is preferably made of a conductive material containing indium and oxygen. Alternatively, a conductive material containing nitrogen (e.g., titanium nitride, tantalum nitride, etc.) may be used. Alternatively, one or more selected from ITO, indium oxide containing tungsten, indium zinc oxide containing tungsten, indium oxide containing titanium, indium tin oxide containing titanium, In—Zn oxide, and ITSO may be used. Alternatively, indium gallium zinc oxide containing nitrogen may be used. Using such a material may enable hydrogen contained in the semiconductor layer 230 to be captured. Alternatively, hydrogen introduced from an outer insulating layer or the like may be captured.

[0228] 1C , in a cross-sectional view of the transistor 200 in the channel width direction, a curved surface may be formed between the side surface of the semiconductor layer 230 and the top surface of the semiconductor layer 230. In other words, the end of the side surface and the end of the top surface may be curved.

[0229] 6A, for example, the conductive layer 260 preferably has a two-layer structure. Here, the conductive layer 260 preferably includes a conductive layer 260_1 and a conductive layer 260_2 disposed over the conductive layer 260_1. For example, the conductive layer 260_1 is preferably disposed so as to surround the bottom and side surfaces of the conductive layer 260_2. In this case, it is preferable to use a conductive material that is resistant to oxidation or a conductive material that has a function of suppressing oxygen diffusion as the conductive layer 260_1.

[0230] The conductive layer 260_1 can be formed using a conductive material that can be used for the conductive layer 205_1. For example, titanium nitride can be used as the conductive layer 260_1. For example, the conductive layer 260_1 has a function of suppressing oxygen diffusion, which can suppress a decrease in conductivity due to oxidation of the conductive layer 260_2 caused by oxygen contained in the insulating layer 280 or the like.

[0231] The conductive layer 260_2 can be formed using a conductive material that can be used for the conductive layer 205_2. For example, tungsten can be used for the conductive layer 260_2. The conductive layer 260_2 may have a stacked-layer structure, for example, a stacked-layer structure of a titanium film or a titanium nitride film and a conductive material that can be used for the conductive layer 205_2.

[0232] The insulating layer 216, the insulating layer 280, and the insulating layer 285 preferably have a lower relative dielectric constant than the insulating layer 222. By using a material with a low relative dielectric constant as an interlayer film, parasitic capacitance generated between wirings can be reduced.

[0233] For example, the insulating layer 216, the insulating layer 280, and the insulating layer 285 can each be made of a material with a low dielectric constant, as described in the "Insulating Layer" section below. Silicon oxide and silicon oxynitride are particularly preferred because they are thermally stable. Materials such as silicon oxide, silicon oxynitride, and silicon oxide with vacancies are also preferred because they allow for the easy formation of a region containing excess oxygen.

[0234] Furthermore, the upper surfaces of the insulating layer 216 and the insulating layer 280 may each be flattened.

[0235] It is preferable that the concentration of impurities such as water and hydrogen is reduced in the insulating layer 280. For example, it is preferable that the insulating layer 280 has an oxide containing silicon, such as silicon oxide or silicon oxynitride.

[0236] The conductive layers 243a and 243b can be formed using a conductive material described in the section "Conductive Layer" below. The conductive layers 243a and 243b are preferably formed using a conductive material containing titanium, tungsten, copper, or aluminum as a main component, for example. The conductive layers 243a and 243b may have a stacked structure.

[0237] 6A, the conductive layer 243a and the conductive layer 243b may have a two-layer laminated structure. The conductive layer 243a includes a conductive layer 243a1 formed along the opening 244a and a conductive layer 243a2 formed inside the conductive layer 243a1. The conductive layer 243b includes a conductive layer 243b1 formed along the opening 244b and a conductive layer 243b2 formed inside the conductive layer 243b1.

[0238] The conductive layer 243a1 and the conductive layer 243b1 can be formed as a single layer or a stacked layer using a conductive material that can be used for the conductive layer 205_1. For example, titanium nitride can be used for the conductive layer 243a1 and the conductive layer 243b1. Providing the conductive layer 243a1 and the conductive layer 243b1 can prevent impurities such as water and hydrogen from entering the semiconductor layer 230 through the conductive layer 243a2 and the conductive layer 243b2.

[0239] The conductive layers 243a2 and 243b2 are preferably formed using a conductive material that can be used for the conductive layers 243a and 243b, for example, tungsten.

[0240] Furthermore, as shown in FIG. 1B, for example, the height of the upper surfaces of the conductive layers 243a and 243b is the same as or approximately the same as the height of the upper surface of the insulating layer 285.

[0241] The insulating layers 241a and 241b are preferably barrier insulating layers applicable to the insulating layer 275 and the like. For example, silicon nitride is preferably used for the insulating layers 241a and 241b. The insulating layers 241a and 241b are provided in contact with the insulating layers 285, 283, 282, and 275. This can prevent impurities such as water and hydrogen contained in the insulating layer 280 and the like from being mixed into the semiconductor layer 230 through the conductive layers 243a and 243b. Silicon nitride is particularly suitable because it has a high barrier property against hydrogen. Furthermore, oxygen contained in the insulating layer 280 can be prevented from being absorbed by the conductive layers 243a and 243b.

[0242] The insulating layer 241 a and the insulating layer 241 b may have a stacked structure. In this case, a first insulating layer in contact with a sidewall of an opening such as the insulating layer 280 and a second insulating layer on the inner side thereof preferably use a combination of a barrier insulating layer against oxygen and a barrier insulating layer against hydrogen.

[0243] <Constituent Materials of Semiconductor Device> Materials that can be used in the semiconductor device of this embodiment will be described below. Note that each layer that constitutes the semiconductor device of this embodiment may have a single-layer structure or a multilayer structure.

[0244] [Semiconductor Layer] For an oxide semiconductor layer that can be used as a semiconductor layer of a transistor according to one embodiment of the present invention, the description in <Structure of Semiconductor Device> can be referred to.

[0245] The carrier concentration in the channel formation region is 1×10 １９ cm −３ Less than 1 x 10 １８ cm −３ Less than 5 x 10 １７ cm −３ Less than 1 x 10 １７ cm −３ Less than 1 x 10 １６ cm −３ Less than 1 x 10 １５ cm −３ Less than 1 x 10 １４ cm −３ Less than 1 x 10 １３ cm −３Less than 1 x 10 １２ cm −３ Less than 1 x 10 １１ cm −３ Less than or 1 x 10 １０ cm −３ The lower limit of the carrier concentration in the channel formation region is not particularly limited, but is preferably less than 1×10 −７ cm −３ It can be said that:

[0246] As described above, when oxygen vacancies and impurities exist in the channel formation region of an oxide semiconductor in an OS transistor, the electrical characteristics of the OS transistor tend to fluctuate, which may result in poor reliability. Therefore, reducing the impurity concentration in the oxide semiconductor is effective for stabilizing the electrical characteristics of the OS transistor. Furthermore, in order to reduce the impurity concentration in the oxide semiconductor, it is preferable to also reduce the impurity concentration in a nearby film. Examples of impurities include hydrogen, carbon, and nitrogen.

[0247] When nitrogen is contained in an oxide semiconductor, electrons serving as carriers are generated, the carrier concentration increases, and the semiconductor is likely to become n-type. As a result, a transistor using an oxide semiconductor containing nitrogen as a semiconductor is likely to be normally on. Alternatively, when nitrogen is contained in an oxide semiconductor, trap states may be formed. As a result, the electrical characteristics of the transistor may become unstable. Therefore, the nitrogen concentration in the channel formation region of the oxide semiconductor obtained by SIMS is 1×10 ２０ atoms / cm ３ Below 5 × 10, preferably １９ atoms / cm ３ Less than 1×10, more preferably 1×10 １９ atoms / cm ３ Less than or equal to 5 × 10, more preferably １８ atoms / cm ３ Less than 1×10, more preferably 1×10 １８ atoms / cm ３ or less, more preferably 5 × 10 １７ atoms / cm ３ The following applies.

[0248] Furthermore, when an oxide semiconductor contains an alkali metal or an alkaline earth metal, defect levels are formed and carriers are generated in some cases. Therefore, a transistor using an oxide semiconductor containing an alkali metal or an alkaline earth metal is likely to be normally on. Therefore, when the concentration of the alkali metal or the alkaline earth metal in the channel formation region of the oxide semiconductor obtained by SIMS is set to 1×10 １８ atoms / cm ３ Below 2 × 10, preferably １６ atoms / cm ３ Do the following:

[0249] In this specification and the like, normally on refers to a state in which a channel exists and a current flows through a transistor even when no voltage is applied to the gate.

[0250] When an oxide semiconductor with sufficiently reduced impurities is used for a channel formation region of a transistor, stable electrical characteristics can be obtained.

[0251] [Insulating Layer] It is preferable to use an inorganic insulating film for each of the insulating layers (insulating layer 212, insulating layer 214, insulating layer 216, insulating layer 221, insulating layer 222, insulating layer 224, insulating layer 250, insulating layer 275, insulating layer 280, insulating layer 282, insulating layer 283, insulating layer 285, etc.) included in the semiconductor device. Examples of inorganic insulating films include an oxide insulating film, a nitride insulating film, an oxynitride insulating film, and a nitride oxide insulating film. Examples of oxide insulating films include a silicon oxide film, an aluminum oxide film, a magnesium oxide film, a gallium oxide film, a germanium oxide film, an yttrium oxide film, a zirconium oxide film, a lanthanum oxide film, a neodymium oxide film, a hafnium oxide film, a tantalum oxide film, a cerium oxide film, a gallium zinc oxide film, and a hafnium aluminate film. Examples of nitride insulating films include a silicon nitride film and an aluminum nitride film. Examples of the oxynitride insulating film include a silicon oxynitride film, an aluminum oxynitride film, a gallium oxynitride film, an yttrium oxynitride film, and a hafnium oxynitride film. Examples of the nitride oxide insulating film include a silicon nitride oxide film and an aluminum nitride oxide film. An insulating layer included in a semiconductor device may be an organic insulating film.

[0252] For example, as transistors become more miniaturized and highly integrated, problems such as leakage current may occur due to thinner gate insulating layers. Using a high-dielectric-constant (high-k) material for the gate insulating layer allows for lower voltage operation of the transistor while maintaining the physical film thickness. It also allows for thinner equivalent oxide thickness (EOT) of the gate insulating layer. Meanwhile, using a material with a low dielectric constant for the insulating layer that functions as an interlayer film can reduce the parasitic capacitance that occurs between wiring. Therefore, it is preferable to select materials according to the function of the insulating layer. Note that materials with a low dielectric constant also have high dielectric strength.

[0253] Examples of materials with a high relative dielectric constant include aluminum oxide, gallium oxide, hafnium oxide, tantalum oxide, zirconium oxide, hafnium zirconium oxide, oxides containing aluminum and hafnium, oxynitrides containing aluminum and hafnium, oxides containing silicon and hafnium, oxynitrides containing silicon and hafnium, and nitrides containing silicon and hafnium.

[0254] Examples of materials with a low dielectric constant include inorganic insulating materials such as silicon oxide, silicon oxynitride, and silicon nitride oxide, and resins such as polyester, polyolefin, polyamide (nylon, aramid, etc.), polyimide, polycarbonate, and acrylic resin. Other inorganic insulating materials with a low dielectric constant include silicon oxide containing fluorine, silicon oxide containing carbon, and silicon oxide containing carbon and nitrogen. Another example is silicon oxide having vacancies. These silicon oxides may contain nitrogen.

[0255] Furthermore, a material capable of exhibiting ferroelectricity may be used for the insulating layer of a semiconductor device. Examples of materials capable of exhibiting ferroelectricity include metal oxides such as hafnium oxide, zirconium oxide, and hafnium zirconium oxide. Examples of materials capable of exhibiting ferroelectricity include a material obtained by adding element J1 (here, element J1 is one or more selected from zirconium, silicon, aluminum, gadolinium, yttrium, lanthanum, strontium, etc.) to hafnium oxide. Here, the ratio of the number of hafnium atoms to the number of element J1 atoms can be appropriately set; for example, the ratio of the number of hafnium atoms to the number of element J1 atoms can be set to 1:1 or close to that. Examples of materials capable of exhibiting ferroelectricity include a material obtained by adding element J2 (here, element J2 is one or more selected from hafnium, silicon, aluminum, gadolinium, yttrium, lanthanum, strontium, etc.) to zirconium oxide. The ratio of the number of zirconium atoms to the number of atoms of element J2 can be set appropriately, for example, the ratio of the number of zirconium atoms to the number of atoms of element J2 can be set to 1:1 or close to that. Furthermore, as a material that can have ferroelectricity, lead titanate (PbTiO Ｘ Piezoelectric ceramics having a perovskite structure, such as barium strontium titanate (BST), strontium titanate, lead zirconate titanate (PZT), strontium bismuth tantalate (SBT), bismuth ferrite (BFO), or barium titanate, may also be used.

[0256] Furthermore, examples of materials that may exhibit ferroelectricity include metal nitrides containing element M1, element M2, and nitrogen. Here, element M1 is one or more elements selected from aluminum, gallium, indium, etc. Furthermore, element M2 is one or more elements selected from boron, scandium, yttrium, lanthanum, cerium, neodymium, europium, titanium, zirconium, hafnium, vanadium, niobium, tantalum, chromium, etc. The ratio of the number of atoms of element M1 to the number of atoms of element M2 can be appropriately set. Furthermore, metal oxides containing element M1 and nitrogen may exhibit ferroelectricity even without containing element M2. Furthermore, examples of materials that may exhibit ferroelectricity include materials in which element M3 is added to the above metal nitrides. Furthermore, element M3 is one or more elements selected from magnesium, calcium, strontium, zinc, cadmium, etc. Here, the ratio of the number of atoms of the element M1, the number of atoms of the element M2, and the number of atoms of the element M3 can be set appropriately.

[0257] Furthermore, materials that can have ferroelectricity include SrTaO ２ N and BaTaO ２ Perovskite-type oxynitrides such as N, GaFeO with κ-alumina structure ３ etc.

[0258] In the above description, metal oxides and metal nitrides are used as examples, but the present invention is not limited to these. For example, metal oxynitrides in which nitrogen is added to the aforementioned metal oxides, or metal oxynitrides in which oxygen is added to the aforementioned metal nitrides, may also be used.

[0259] Furthermore, as a material capable of exhibiting ferroelectricity, for example, a mixture or compound made of a plurality of materials selected from the materials listed above can be used. Alternatively, the insulating layer 454 described in Embodiment 2 can have a layered structure made of a plurality of materials selected from the materials listed above. Incidentally, the crystal structure (characteristics) of the materials listed above may change depending not only on the film formation conditions but also on various processes, etc., and therefore, in this specification and the like, a material that exhibits ferroelectricity is referred to not only as a ferroelectric but also as a material capable of exhibiting ferroelectricity.

[0260] In this specification, a layer of a material that can have ferroelectricity may be referred to as a ferroelectric layer, a metal oxide film, or a metal nitride film. Also, in this specification, a device having such a ferroelectric layer, a metal oxide film, or a metal nitride film may be referred to as a ferroelectric device.

[0261] Ferroelectricity is believed to be exhibited by the displacement of oxygen or nitrogen in crystals contained in the ferroelectric layer due to an external electric field. Furthermore, it is believed that the exhibiting of ferroelectricity depends on the crystal structure of the crystals contained in the ferroelectric layer. Therefore, for an insulating layer to exhibit ferroelectricity, the insulating layer must contain crystals. In particular, an insulating layer containing crystals having an orthorhombic crystal structure is preferred because it exhibits ferroelectricity. The crystal structure of the crystals contained in the insulating layer may be one or more selected from the group consisting of tetragonal, orthorhombic, monoclinic, and hexagonal. The insulating layer may also have an amorphous structure. In this case, the insulating layer may have a composite structure having an amorphous structure and a crystalline structure.

[0262] A metal oxide containing either or both of hafnium and zirconium is also an insulating material capable of capturing or fixing hydrogen. Therefore, by using a metal oxide containing either or both of hafnium and zirconium for at least a part of a gate insulating layer, hydrogen contained in the oxide semiconductor layer can be captured or fixed, thereby reducing the hydrogen concentration in the oxide semiconductor layer. Furthermore, a transistor having the gate insulating layer can function as a ferroelectric field effect transistor (FeFET).

[0263] Furthermore, adding a Group 3 element in the periodic table to an oxide containing one or both of hafnium and zirconium increases the oxygen vacancy concentration in the oxide, making it easier to form crystals with an orthorhombic crystal structure. This is preferable because it increases the proportion of crystals with an orthorhombic crystal structure and increases the remanent polarization. On the other hand, if the amount of the Group 3 element added is too large, the crystallinity of the oxide may decrease, making it difficult to exhibit ferroelectricity. Therefore, the content of the Group 3 element in the oxide containing one or both of hafnium and zirconium is preferably 0.1 atomic% to 10 atomic%, more preferably 0.1 atomic% to 5 atomic%, and even more preferably 0.1 atomic% to 3 atomic%. Here, the content of the Group 3 element refers to the ratio of the number of atoms of the Group 3 element to the sum of the number of atoms of all metal elements contained in the layer. The Group 3 element is preferably one or more selected from scandium, lanthanum, and yttrium, and more preferably one or both of lanthanum and yttrium.

[0264] Furthermore, a transistor using a metal oxide can have stable electrical characteristics by being surrounded by an insulating layer that has a function of suppressing the permeation of impurities and oxygen. The insulating layer that has a function of suppressing the permeation of impurities and oxygen can be, for example, a single-layer or stacked insulating layer containing one or more elements selected from boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, and tantalum. Specifically, the insulating layer that has a function of suppressing the permeation of impurities and oxygen can be made of a metal oxide such as aluminum oxide, magnesium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, or tantalum oxide; a nitride such as aluminum nitride or silicon nitride; or a nitride oxide such as silicon nitride oxide.

[0265] Specifically, examples of materials for the insulating layer that have the function of suppressing the permeation of impurities such as water and hydrogen, and oxygen, include metal oxides such as aluminum oxide, magnesium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, tantalum oxide, and oxides containing aluminum and hafnium (hafnium aluminate). Examples of nitrides include aluminum nitride, aluminum titanium nitride, and silicon nitride. Examples of nitride oxides include silicon nitride oxide. Examples of materials for the insulating layer that have the function of suppressing the permeation of oxygen include gallium oxide.

[0266] An insulating layer, such as a gate insulating layer, that is in contact with an oxide semiconductor layer or that is provided near the oxide semiconductor layer is preferably an insulating layer having a region containing excess oxygen. For example, when an insulating layer having a region containing excess oxygen is in contact with an oxide semiconductor layer or is located near the oxide semiconductor layer, oxygen vacancies in the oxide semiconductor layer can be reduced. Examples of insulating materials that easily form a region containing excess oxygen include silicon oxide, silicon oxynitride, and silicon oxide having vacancies. Examples of insulating layers that easily form a region containing excess oxygen include a silicon oxide film, a silicon oxynitride film, and a silicon oxide film having vacancies.

[0267] An insulating layer provided in contact with or near an oxide semiconductor layer is preferably a barrier insulating layer against hydrogen. When the insulating layer has a barrier property against hydrogen, diffusion of hydrogen into the oxide semiconductor layer can be suppressed. The barrier insulating layer against hydrogen can also be said to have a function of suppressing diffusion of hydrogen.

[0268] Examples of insulating materials having the function of capturing or fixing hydrogen include metal oxides such as oxides containing hafnium, oxides containing magnesium, oxides containing aluminum, oxides containing aluminum and hafnium (hafnium aluminate), hafnium silicate, etc. These metal oxides may further contain zirconium, and examples thereof include oxides containing hafnium and zirconium.

[0269] An insulating layer having the function of capturing or fixing hydrogen preferably has an amorphous structure. In a metal oxide having an amorphous structure, some oxygen atoms have dangling bonds, which enhances the ability to capture or fix hydrogen. Therefore, when the insulating layer has an amorphous structure, the function of capturing or fixing hydrogen can be enhanced.

[0270] By making the insulating layer an amorphous structure, it is possible to suppress the formation of crystal grain boundaries. By suppressing the formation of crystal grain boundaries, it is possible to improve the flatness of the insulating layer. This makes it possible to uniformize the film thickness distribution of the insulating layer and reduce areas with extremely thin film thickness, thereby improving the breakdown voltage of the insulating layer. It is also possible to uniformize the film thickness distribution of a film provided on the insulating layer. Furthermore, by suppressing the formation of crystal grain boundaries in the insulating layer, it is possible to reduce leakage current caused by defect levels at the crystal grain boundaries. Therefore, the insulating layer can function as an insulating film with low leakage current.

[0271] The insulating layer may have a crystalline region and / or a grain boundary in a part thereof.

[0272] The ability to capture or fix a corresponding substance can also be said to have the property of making it difficult for the corresponding substance to diffuse. Therefore, the ability to capture or fix a corresponding substance can be rephrased as barrier properties.

[0273] Examples of materials for the barrier insulating layer against hydrogen include aluminum oxide, magnesium oxide, hafnium oxide, zirconium oxide, oxides containing aluminum and hafnium (hafnium aluminate), oxides containing hafnium and zirconium (hafnium zirconium oxide), silicon nitride, and silicon nitride oxide.

[0274] The inorganic insulating layers cited as insulating layers having the function of capturing or fixing hydrogen and insulating layers having the function of suppressing hydrogen diffusion also have barrier properties against oxygen. Examples of materials for the oxygen barrier insulating layer include oxides containing one or both of aluminum and hafnium, magnesium oxide, gallium zinc oxide, silicon nitride, and silicon nitride oxide. Examples of oxides containing one or both of aluminum and hafnium include aluminum oxide, hafnium oxide, oxides containing aluminum and hafnium (hafnium aluminate), and hafnium silicate.

[0275] [Conductive Layer] The conductive layers (conductive layer 205, conductive layer 242a, conductive layer 242b, conductive layer 243a, conductive layer 243b, conductive layer 260, etc.) included in the semiconductor device preferably contain a metal element selected from aluminum, chromium, copper, silver, gold, platinum, zinc, tantalum, nickel, titanium, iron, cobalt, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, lanthanum, etc., or an alloy containing the above metal element or an alloy combining the above metal elements. As the alloy containing the above metal element, a nitride of the alloy or an oxide of the alloy may be used. For example, tantalum nitride, titanium nitride, nitride containing titanium and aluminum, nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxide containing strontium and ruthenium, oxide containing lanthanum and nickel, etc. are preferably used. Furthermore, semiconductors with high electrical conductivity, such as polycrystalline silicon containing impurity elements such as phosphorus, and silicides such as nickel silicide may also be used.

[0276] Nitrogen-containing conductive materials, such as nitrides containing tantalum, nitrides containing titanium, nitrides containing molybdenum, nitrides containing tungsten, nitrides containing ruthenium, nitrides containing tantalum and aluminum, or nitrides containing titanium and aluminum; oxygen-containing conductive materials, such as ruthenium oxide, oxides containing strontium and ruthenium, or oxides containing lanthanum and nickel; and materials containing metal elements, such as titanium, tantalum, or ruthenium, are preferred because they are conductive materials that are resistant to oxidation, have a function of suppressing oxygen diffusion, or maintain conductivity even after absorbing oxygen. Examples of oxygen-containing conductive materials include indium oxide containing tungsten, indium oxide containing titanium, ITO, indium tin oxide containing titanium, ITSO, In—Zn oxide, and indium zinc oxide containing tungsten. In this specification and the like, a conductive film formed using a conductive material containing oxygen may be referred to as an oxide conductive film.

[0277] Conductive materials containing tungsten, copper, or aluminum as a main component are preferred because they have high conductivity.

[0278] A plurality of conductive layers formed from the above materials may be stacked. For example, a stacked structure may be formed by combining the above-mentioned material containing a metal element and a conductive material containing oxygen. A stacked structure may be formed by combining the above-mentioned material containing a metal element and a conductive material containing nitrogen. A stacked structure may be formed by combining the above-mentioned material containing a metal element, a conductive material containing oxygen, and a conductive material containing nitrogen.

[0279] When a metal oxide is used for the channel formation region of a transistor, the conductive layer that functions as a gate electrode preferably has a stacked structure that combines a material containing the metal element and a conductive material containing oxygen. In this case, the conductive material containing oxygen is preferably provided on the channel formation region side. By providing the conductive material containing oxygen on the channel formation region side, oxygen desorbed from the conductive material is easily supplied to the channel formation region.

[0280] [Substrate] Substrates on which transistors are formed can include, for example, insulating substrates, semiconductor substrates, or conductive substrates. Examples of insulating substrates include glass substrates, quartz substrates, sapphire substrates, stabilized zirconia substrates (e.g., yttria-stabilized zirconia substrates), and resin substrates. Examples of semiconductor substrates include semiconductor substrates made of silicon or germanium, or compound semiconductor substrates made of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, or gallium oxide. Examples of semiconductor substrates include those having an insulating region within the semiconductor substrate, such as an SOI (Silicon-On-Insulator) substrate. Examples of conductive substrates include graphite substrates, metal substrates, alloy substrates, and conductive resin substrates. Examples of substrates include substrates having a metal nitride or a metal oxide. Examples of substrates include substrates having a conductor or semiconductor provided on an insulating substrate, substrates having a conductor or insulator provided on a semiconductor substrate, and substrates having a semiconductor or insulator provided on a conductive substrate. Alternatively, a substrate provided with elements may be used, such as a capacitor element, a resistor element, a switch element, a light-emitting element, or a memory element.

[0281] The above is the description of the materials that can be used for the semiconductor device of this embodiment mode.

[0282] <Example 1 of Manufacturing Method of Semiconductor Device> An example of a manufacturing method of a semiconductor device of one embodiment of the present invention will be described below with reference to the drawings. In FIGS. 8A to 14D illustrating an example of a manufacturing process of a semiconductor device, A in each drawing is a plan view. B in each drawing is a cross-sectional view taken along dashed-dotted line A1-A2 in A in each drawing. C in each drawing is a cross-sectional view taken along dashed-dotted line A3-A4 in A in each drawing. D in each drawing is a cross-sectional view taken along dashed-dotted line A5-A6 in A in each drawing.

[0283] Thin films (insulating films, semiconductor films, conductive films, etc.) that constitute semiconductor devices can be formed using a sputtering method, a chemical vapor deposition (CVD) method, a vacuum deposition method, a molecular beam epitaxy (MBE) method, a pulsed laser deposition (PLD) method, an atomic layer deposition (ALD) method, or the like.

[0284] Sputtering methods include RF sputtering, which uses a high-frequency power supply as the sputtering power source, DC sputtering, which uses a direct current power supply, and pulsed DC sputtering, which changes the voltage applied to the electrode in a pulsed manner. RF sputtering is mainly used to form insulating films, while DC sputtering is mainly used to form metal conductive films. Pulsed DC sputtering is mainly used to form films of compounds such as oxides, nitrides, and carbides using reactive sputtering.

[0285] CVD methods can be further classified into plasma-enhanced CVD (PECVD) methods that utilize plasma, thermal CVD (TCVD) methods that utilize heat, and photo-CVD (photo-CVD) methods that utilize light. CVD methods can also be further classified into metal CVD (MCVD) methods and metal organic CVD (MOCVD) methods depending on the source gas used.

[0286] The plasma CVD method can produce high-quality films at relatively low temperatures. Furthermore, the thermal CVD method is a film formation method that can minimize plasma damage to the workpiece because it does not use plasma. For example, wiring, electrodes, elements (transistors, capacitors, etc.) included in a semiconductor device may become charged up by receiving electric charge from the plasma. In this case, the accumulated electric charge may destroy the wiring, electrodes, elements, etc. included in the semiconductor device. On the other hand, the thermal CVD method, which does not use plasma, does not cause such plasma damage, and therefore can increase the yield of semiconductor devices. Furthermore, the thermal CVD method does not cause plasma damage during film formation, so films with fewer defects can be obtained.

[0287] As the ALD method, a thermal ALD method in which a precursor and a reactant are reacted using only thermal energy, a plasma ALD (PEALD: Plasma Enhanced ALD) method in which a plasma-excited reactant is used, or the like can be used.

[0288] Note that some precursors used in the ALD method contain elements such as carbon or chlorine. Therefore, films formed by the ALD method may contain more elements such as carbon or chlorine than films formed by other film formation methods. The amounts of these elements can be quantified using XPS or SIMS. Note that the metal oxide film formation method of one embodiment of the present invention uses the ALD method, but employs one or both of a high substrate temperature during film formation and an impurity removal treatment. Therefore, the amount of carbon and chlorine contained in the film may be smaller than when the ALD method is used without these.

[0289] Unlike film formation methods in which particles emitted from a target or the like are deposited, the ALD method is a film formation method in which a film is formed by a reaction on the surface of a workpiece. Therefore, it is a film formation method that is less affected by the shape of the workpiece and has good step coverage. In particular, the ALD method has excellent step coverage and excellent thickness uniformity, making it suitable for coating the surface of an opening with a high aspect ratio.

[0290] The CVD and ALD methods differ from sputtering methods in which particles emitted from a target or the like are deposited. Therefore, they are film formation methods that are less affected by the shape of the workpiece and have good step coverage. In particular, the ALD method has excellent step coverage and excellent thickness uniformity, making it suitable for coating the surface of an opening with a high aspect ratio. However, because the ALD method has a relatively slow film formation rate, it may be preferable to use it in combination with other film formation methods, such as the CVD method, which have a faster film formation rate.

[0291] Furthermore, the CVD method allows deposition of a film of any composition by adjusting the flow rate ratio of the source gases. For example, the CVD method allows deposition of a film with a continuously changing composition by changing the flow rate ratio of the source gases during deposition. When deposition is performed while changing the flow rate ratio of the source gases, the time required for deposition can be shortened compared to deposition using multiple deposition chambers because no time is required for transport or pressure adjustment. Therefore, the productivity of semiconductor devices can be improved in some cases.

[0292] In addition, in the ALD method, a film of any composition can be formed by simultaneously introducing multiple different precursors, or by controlling the number of cycles of each precursor when multiple different precursors are introduced.

[0293] Furthermore, thin films (insulating films, semiconductor films, conductive films, etc.) constituting the semiconductor device can be formed by a wet film formation method such as spin coating, dip coating, spray coating, inkjet printing, dispensing, screen printing, offset printing, doctor knife method, slit coating, roll coating, curtain coating, or knife coating.

[0294] Furthermore, when processing a thin film that constitutes a semiconductor device, a photolithography method or the like can be used. Alternatively, the thin film may be processed by a nanoimprint method, a sandblasting method, a lift-off method, or the like. Furthermore, an island-shaped thin film may be directly formed by a film formation method using a shielding mask such as a metal mask.

[0295] There are two typical photolithography methods: one is to form a resist mask on the thin film to be processed, and then remove part of the thin film by etching or the like, and then remove the resist mask; the other is to form a photosensitive thin film, and then expose and develop it to process the thin film into the desired shape.

[0296] In photolithography, the light used for exposure can be, for example, i-line (wavelength 365 nm), g-line (wavelength 436 nm), h-line (wavelength 405 nm), or a mixture of these. Other light sources that can be used include ultraviolet light, KrF laser light, ArF laser light, etc. Exposure can also be performed by immersion exposure technology. Extreme ultraviolet (EUV) light or X-rays can also be used as the light used for exposure. An electron beam can also be used instead of the light used for exposure. Extreme ultraviolet light, X-rays, or an electron beam are preferred because they enable extremely fine processing. When exposure is performed by scanning a beam such as an electron beam, a photomask is not required.

[0297] For etching the thin film, dry etching, wet etching, sandblasting, or the like can be used.

[0298] An example of a method for manufacturing a semiconductor device including the transistor 200A will be described below.

[0299] First, as shown in FIGS. 8A to 8D , a substrate (not shown) is prepared, and insulating layers 212, 214, 216, a conductive layer 205, an insulating layer 221, an insulating layer 222, an insulating layer 224f, a semiconductor film 230f, and a film 231f are sequentially formed on the substrate. The insulating film 224f is a film that will become the insulating layer 224 in a later step. The semiconductor film 230f is a film that will become the semiconductor layer 230 in a later step. As described above, the semiconductor layer 230 can be an oxide semiconductor layer or a metal oxide layer. In this case, the semiconductor film 230f is also referred to as an oxide semiconductor film or a metal oxide film, respectively. The film 231f contains an impurity element that will be added to the semiconductor layer 230 to form the low-resistance regions 230na and 230nb in a later step. Therefore, the film 231f is also referred to as an impurity film.

[0300] For example, an indium oxide film can be formed as the semiconductor film 230f. The film 231f can be formed to contain a metal element. Specifically, the film 231f can contain an element that is a main component of the semiconductor film 230f and the above-mentioned impurity element. For example, when the semiconductor film 230f is an indium oxide film, the film 231f can contain indium. Furthermore, the film 231f can contain at least one of titanium, tin, antimony, germanium, and aluminum as the above-mentioned impurity element. The film 231f may be formed to contain these metal elements as simple substances or as oxides. The film 231f may be formed to contain, for example, indium oxide, titanium oxide, or tin oxide.

[0301] Note that the film 231f does not necessarily contain an impurity element. For example, when an indium oxide film is formed as the semiconductor film 230f, an indium film or an indium oxide film may be formed as the film 231f. In this case, the film 231f can be a film containing an element that is a main component of the semiconductor film 230f at a higher concentration than the semiconductor film 230f. For example, when the semiconductor film 230f is an indium oxide film, the film 231f can be a film containing an indium concentration higher than the semiconductor film 230f.

[0302] For example, the thickness Tins shown in FIG. 2A can be the thickness of the semiconductor film 230f. Furthermore, the thickness Tn can be the sum of the thickness of the semiconductor film 230f and the thickness of the film 231f. The thickness of the film 231f is set to be thinner than the thickness of the semiconductor film 230f. The thickness of the semiconductor film 230f is preferably 2 nm to 500 nm, more preferably 2.5 nm to 300 nm, more preferably 2.5 nm to 200 nm, more preferably 5 nm to 100 nm, more preferably 7 nm to 70 nm, and even more preferably 10 nm to 50 nm. The thickness of the film 231f is preferably 0.1 nm to 10 nm, more preferably 0.1 nm to 5 nm, more preferably 0.1 nm to 3 nm, more preferably 0.1 nm to 2 nm, and even more preferably 0.1 nm to 1 nm.

[0303] The semiconductor film 230f can be formed by a sputtering method. The semiconductor film 230f can be formed, for example, in an atmosphere containing oxygen. Furthermore, by using a sputtering method that does not require the use of hydrogen-containing molecules in the deposition gas, the hydrogen concentration in the semiconductor film 230f can be reduced. For example, oxygen or a mixed gas of oxygen and a noble gas can be used as the sputtering gas. The semiconductor film 230f may also be formed by an ALD method.

[0304] After the semiconductor film 230f is formed, a process for supplying oxygen to the semiconductor film 230f may be performed. This allows oxygen to be supplied to the semiconductor film 230f by heat or the like applied after the process. Examples of the process for supplying oxygen include heat treatment in an atmosphere containing oxygen, plasma treatment (including microwave plasma treatment) in an atmosphere containing oxygen, and the like.

[0305] It is preferable to perform heat treatment after the formation of the semiconductor film 230f and before the formation of the film 231f. By performing the heat treatment, impurities such as hydrogen or water contained in the semiconductor film 230f can be reduced. The temperature of the heat treatment is preferably 100°C to 650°C, more preferably 250°C to 600°C, further preferably 300°C to 500°C or 350°C to 550°C, and typically 400°C.

[0306] The heat treatment is performed in a nitrogen gas or inert gas atmosphere, or an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas. For example, when the heat treatment is performed in a mixed atmosphere of nitrogen gas and oxygen gas, the oxygen gas content is preferably about 20%. The heat treatment may also be performed under reduced pressure. Alternatively, after the heat treatment in the nitrogen gas or inert gas atmosphere, the heat treatment may be performed in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas to compensate for the desorbed oxygen.

[0307] The gas used in the heat treatment is preferably highly purified. For example, the amount of moisture contained in the gas used in the heat treatment is preferably 1 ppb or less, more preferably 0.1 ppb or less, and even more preferably 0.05 ppb or less. By performing the heat treatment using a highly purified gas, it is possible to prevent moisture and the like from being taken into the semiconductor film 230f as much as possible.

[0308] The heat treatment reduces impurities such as carbon, hydrogen, and water in the semiconductor film 230f. Reducing the impurities in the film in this manner improves the crystallinity of the semiconductor film 230f, resulting in a denser, more compact structure. This increases the crystalline regions in the semiconductor film 230f, reducing in-plane variations in the crystalline regions in the semiconductor film 230f. This reduces in-plane variations in the electrical characteristics of the transistor.

[0309] When the insulating film 224f contains oxygen, oxygen can be supplied from the insulating film 224f to the semiconductor film 230f by the heat treatment. Ｏ H can be reduced.

[0310] Note that microwave plasma treatment may be performed after the semiconductor film 230f is formed. By performing the microwave plasma treatment, the concentration of impurities such as hydrogen or water contained in the semiconductor film 230f can be reduced. Furthermore, a crystalline region of the semiconductor film 230f may grow.

[0311] In this specification, microwaves refer to electromagnetic waves having a frequency of 300 MHz to 300 GHz. Microwave plasma treatment refers to treatment using a device with a power source that generates high-density plasma using microwaves. Microwave plasma treatment can also be called microwave-excited high-density plasma treatment.

[0312] By performing microwave plasma treatment in an atmosphere containing oxygen, the impurity concentration in the semiconductor film 230f can be reduced. Examples of impurities include hydrogen and carbon. While the above example illustrates a configuration in which microwave plasma treatment is performed on the semiconductor film 230f in an atmosphere containing oxygen, the present invention is not limited to this. For example, microwave plasma treatment may be performed on an insulating film, more specifically, a silicon oxide film, provided near the semiconductor film 230f in an atmosphere containing oxygen. Furthermore, the heat generated by the microwave plasma treatment may increase the crystallinity of the semiconductor film 230f.

[0313] The microwave plasma treatment is preferably carried out under reduced pressure, and the pressure is preferably from 10 to 1000 Pa, more preferably from 50 to 700 Pa, and even more preferably from 100 to 400 Pa. The treatment temperature is preferably from room temperature (25°C) to 750°C, more preferably from 300 to 500°C, and can be from 400 to 450°C.

[0314] When microwave plasma treatment is performed, the substrate may be heated. The substrate is preferably heated to a temperature above room temperature (e.g., 25°C), above 100°C, above 200°C, above 300°C, or above 400°C, and below 500°C, or below 450°C. For example, the substrate is preferably heated to a temperature above room temperature and below 500°C, more preferably above 100°C and below 450°C, more preferably above 200°C and below 450°C, even more preferably above 300°C and below 450°C, and even more preferably above 400°C and below 450°C.

[0315] The microwave plasma treatment can be performed using, for example, oxygen gas and argon gas. In the microwave plasma treatment using oxygen gas and argon gas, the main oxygen radical is triplet oxygen (O( ３ P ｊ )), singlet oxygen (O( １ D ２ )), and oxygen ions (O ２ ＋ ) can take three states. Note that oxygen ions act effectively in reducing the hydrogen concentration in the oxide film by microwave plasma processing. The amount of oxygen radicals in each state varies depending on the oxygen flow rate ratio or pressure in microwave plasma processing. For example, under conditions where the oxygen flow rate ratio is low and the pressure is low, the amount of oxygen ions tends to increase. On the other hand, if the oxygen flow rate ratio or pressure is excessively low, there is a concern that the control of the oxygen flow rate becomes unstable, making it difficult to stabilize the discharge, and that the oxide film may be etched. Therefore, for example, when the oxygen flow rate ratio (O ２ / (O ２ +Ar)) is preferably greater than 0% and not greater than 10%, more preferably 0.5% to 5%, more preferably 0.5% to 3%, and typically more preferably 1%.

[0316] The shorter the processing time of the microwave plasma treatment, the higher the productivity. Therefore, for example, the processing time of the microwave plasma treatment is preferably from 1 minute to 60 minutes, more preferably from 1 minute to 30 minutes, and even more preferably from 1 minute to 10 minutes.

[0317] By performing microwave plasma treatment in an atmosphere containing oxygen, oxygen gas is converted into plasma using microwaves or high frequency waves such as RF, and oxygen radicals generated by converting the oxygen gas into plasma can act on the oxide semiconductor layer. By the action of plasma, microwaves, oxygen radicals, or the like, defects in which hydrogen has entered oxygen vacancies in the oxide semiconductor layer (V Ｏ In this way, the V contained in the oxide semiconductor layer can be separated into oxygen vacancies and hydrogen, and the hydrogen as an impurity can be removed from the oxide semiconductor layer. Ｏ H can be reduced. At this time, carbon bonded to oxygen, hydrogen, or the like can also be removed in some cases. In this way, impurities such as carbon or hydrogen can be reduced by performing microwave plasma treatment. Furthermore, by supplying the oxygen radicals to oxygen vacancies formed in the oxide semiconductor layer, the oxygen vacancies in the oxide semiconductor layer can be further reduced.

[0318] Furthermore, a reaction occurs between part of oxygen present in the oxide semiconductor before the microwave plasma treatment and hydrogen in the oxide semiconductor. In other words, the reaction proceeds as follows: 2H + O → H ２ O↑” reaction occurs, converting the hydrogen to H ２ O (also called dehydration or dehydrogenation). ２ Since O is one of the factors that hinder improvement of crystallinity, it is preferable to remove O from the oxide semiconductor. ２ The hydrogen concentration in the oxide semiconductor can be reduced by removing the hydrogen as O, which can also promote improvement in crystallinity. Note that the hydrogen concentration in the oxide semiconductor can be further reduced by increasing the temperature during the microwave plasma treatment.

[0319] After the microwave plasma treatment, a heat treatment may be performed without exposing the substrate to the outside air. The temperature of the heat treatment is, for example, preferably 100° C. or higher and 750° C. or lower, more preferably 300° C. or higher and 500° C. or lower, and even more preferably 400° C. or higher and 450° C. or lower.

[0320] It should be noted that the crystallinity can be improved by plasma treatment containing oxygen gas instead of microwave plasma treatment.

[0321] Oxygen supplied to the oxide semiconductor layer can be in various forms such as oxygen atoms, oxygen molecules, oxygen ions (charged oxygen atoms or oxygen molecules), and oxygen radicals (oxygen atoms, oxygen molecules, or oxygen ions having an unpaired electron). Note that the oxygen injected into the oxide semiconductor layer is preferably in one or more of the above forms, and is particularly preferably in the form of oxygen radicals.

[0322] In this manner, impurities in the semiconductor film 230f can be reduced, and the crystallinity of the semiconductor film 230f can be improved.

[0323] The film 231f is preferably formed using a sputtering method. When the sputtering target has multiple crystal grains, and the crystal grains have a layered structure and have interfaces that are prone to cleavage, bombarding the sputtering target with ions can cleave the crystal grains, resulting in plate-shaped or pellet-shaped sputtering particles. This can sometimes improve the crystallinity of the film 231f. In this case, the electrical resistivity of the low-resistance region 230na and the low-resistance region 230nb, which will be formed in a later process, can sometimes be reduced. The film 231f may also be formed using an ALD method. In this case, the film 231f can be easily formed to a thin thickness.

[0324] 9A to 9D, the insulating film 224f, the semiconductor film 230f, and the film 231f are processed into, for example, an island shape, thereby forming the insulating layer 224, the semiconductor layer 230, and the layer 231. The layer 231 is formed by processing the film 231f, which can be called an impurity film, and therefore the layer 231 is also called an impurity layer.

[0325] The above processing can be performed using a dry etching method or a wet etching method. The dry etching method is suitable for fine processing. The insulating film 224f, the semiconductor film 230f, and the film 231f may be processed under different conditions.

[0326] Here, the insulating film 224f, the semiconductor film 230f, and the film 231f are preferably processed collectively into an island shape. In this case, the upper end of the insulating layer 224 preferably coincides with or substantially coincides with the lower end of the semiconductor layer 230. Furthermore, the upper end of the semiconductor layer 230 preferably coincides with or substantially coincides with the lower end of the layer 231. With such a structure, the number of steps for manufacturing a semiconductor device according to one embodiment of the present invention can be reduced. Therefore, a method for manufacturing a semiconductor device with high productivity can be provided.

[0327] The insulating layer 224, the semiconductor layer 230, and the layer 231 are formed so that at least a portion of each of them overlaps with the conductive layer 205. For example, the insulating layer 222 is exposed in a region where the insulating layer 224 does not overlap with the layer 231. However, this is not limiting, and for example, the insulating layer 224 may remain on the insulating layer 222 in a region where the insulating layer 224 does not overlap with the layer 230, as shown in FIGS.

[0328] 9B to 9D , the side surfaces of the insulating layer 224, the semiconductor layer 230, and the layer 231 can be tapered. The taper angle of the side surfaces of the insulating layer 224, the semiconductor layer 230, and the layer 231 may be, for example, 60° or more and less than 90°. By tapering the side surfaces in this manner, the coverage of the insulating layer 275 and the like can be improved in subsequent steps, and defects such as voids can be reduced.

[0329] The side surfaces of the insulating layer 224, the semiconductor layer 230, and the layer 231 may be perpendicular or approximately perpendicular to the top surface of the insulating layer 222. With such a structure, a reduction in area and high density can be achieved when forming a plurality of transistors.

[0330] Furthermore, by processing the insulating layer 224 into an island shape, an insulating layer 275 can be provided in contact with the side surface of the insulating layer 224 and the top surface of the insulating layer 222 in a step described later. That is, the insulating layer 224 can be separated from the insulating layer 280 by the insulating layer 275. With this structure, it is possible to prevent impurities such as excessive oxygen and hydrogen from the insulating layer 280, which will be formed in a later step, from being mixed into the semiconductor layer 230 through the insulating layer 224.

[0331] 10A to 10D , an insulating layer 275 is formed to cover the insulating layer 224, the semiconductor layer 230, and the layer 231, and an insulating layer 280 is formed on the insulating layer 275. The insulating layer 275 and the insulating layer 280 can be formed by, for example, a sputtering method, a CVD method, an MBE method, a PLD method, or an ALD method. Here, after the insulating layer 275 is formed, an insulating film that will become the insulating layer 280 is preferably formed and then subjected to CMP treatment to form the insulating layer 280 with a flat upper surface.

[0332] As a result, the semiconductor layer 230 can be covered with the insulating layer 275 having a function of suppressing oxygen diffusion. This can suppress oxygen from diffusing directly into the semiconductor layer 230 from the insulating layer 280 or the like in a later step.

[0333] 11A to 11D , the insulating layer 280, the insulating layer 275, and the layer 231 are processed by lithography. By processing the insulating layer 280 and the insulating layer 275, an opening 289 having a region overlapping with the semiconductor layer 230 is formed in the insulating layer 280 and the insulating layer 275. In addition, the layer 231 is divided to form layers 231a and 231b. Because the layers 231a and 231b are formed by processing the layer 231, which can be called an impurity layer, the layers 231a and 231b are also called impurity layers. The opening 289 is formed to have a region overlapping with the conductive layer 205.

[0334] 11A to 11D , the insulating layer 280, the insulating layer 275, and the layer 231 can be processed using, for example, an etching method. Dry etching is particularly suitable for microfabrication and is therefore preferable. At least one of the processing conditions for the insulating layer 280, the insulating layer 275, and the layer 231 may be different from the other two. For example, it is preferable to process the insulating layer 275 under conditions that provide a high etching selectivity with respect to the layer 231, and to process the layer 231 under conditions that are different from the processing conditions for the insulating layer 275. Processing the layer 231 may result in the removal of a portion of the semiconductor layer 230. This may result in the formation of a recess in the semiconductor layer 230. The recess has a region that overlaps with the opening 289. When a recess is formed in the semiconductor layer 230, a semiconductor device including the transistor 200A shown in FIG. 2B may be manufactured.

[0335] Here, the layer 231 is preferably processed under isotropic conditions. The layer 231 is preferably processed under conditions with higher isotropy than the processing conditions for the insulating layer 275, for example. Alternatively, the layer 231 is processed under first conditions to form layers 231a and 231b, and then the layers 231a and 231b are preferably processed under second conditions with higher isotropy than the first conditions. Here, by reducing the bias power, ions generated from the plasma are less likely to be attracted in a direction perpendicular to the substrate, thereby enhancing isotropy. Furthermore, by increasing the pressure of the etching gas, the mean free path of molecules in the atmosphere is shortened. Therefore, collisions between molecules are more likely to occur, thereby enhancing isotropy. Furthermore, wet etching may be used to process the layer 231 under the second conditions.

[0336] As a result, the layers 231a and 231b can be formed so that the side surfaces of the insulating layer 275 at the opening 289 and the side surfaces of the insulating layer 280 at the opening 289 have regions that protrude relative to the layer 231a and regions that protrude relative to the layer 231b, respectively.

[0337] After the layers 231a and 231b are formed, an impurity element may be added to a region of the semiconductor layer 230 that overlaps with the opening 289. For example, when the semiconductor layer 230 is an n-type semiconductor, an impurity element that imparts p-type conductivity can be added. For example, one or both of cadmium and zinc can be added. This may make it easier to make the channel formation region 230i i-type or substantially i-type.

[0338] 12A to 12D , an insulating layer 250 and a conductive layer 260 are formed so as to have regions located within the opening 289. For example, an insulating film to become the insulating layer 250 is formed so as to have, within the opening 289, a region in contact with the top surface of the insulating layer 222, a region in contact with the side surface of the insulating layer 224, a region in contact with the side surface of the semiconductor layer 230, a region in contact with the top surface of the semiconductor layer 230, a region in contact with the side surface of the layer 231a, a region in contact with the side surface of the layer 231b, a region in contact with the side surface of the insulating layer 275, a region in contact with the bottom surface of the insulating layer 275, a region in contact with the side surface of the insulating layer 280, and a region in contact with the top surface of the insulating layer 280. Next, a conductive film to become the conductive layer 260 is formed on the insulating film so as to fill the opening 289. Thereafter, the regions of the insulating film to become the insulating layer 250 and the conductive film to become the conductive layer 260 exposed from the opening 289 are removed by CMP treatment. In this manner, the insulating layer 250 and the conductive layer 260 over the insulating layer 250 are formed in the opening 289. As described above, at least a part of the region of the semiconductor layer 230 that overlaps with the conductive layer 260 becomes the channel formation region 230i.

[0339] The insulating film to be the insulating layer 250 is preferably formed by a film formation method with good coverage, since this makes it easy to form the insulating layer 250 so as to be in contact with the side surfaces of the layer 231a and the layer 231b. The conductive film to be the conductive layer 260 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, a plating method, or an ALD method. For example, a titanium nitride film and a tungsten film can be stacked and formed by a CVD method.

[0340] 13A to 13D , an insulating layer 282 is formed on the insulating layer 250, the conductive layer 260, and the insulating layer 280. After that, an insulating layer 283 is formed on the insulating layer 282, and an insulating layer 285 is formed on the insulating layer 283. The insulating layer 282, the insulating layer 283, and the insulating layer 285 can each be formed by, for example, a sputtering method, a CVD method, an MBE method, a PLD method, or an ALD method.

[0341] The insulating layers 282, 283, and 285 are preferably formed by a sputtering method, which does not require the use of hydrogen-containing molecules in a deposition gas, so that the hydrogen concentrations in the insulating layers 282, 283, and 285 can be reduced.

[0342] Here, the insulating layers 282, 283, and 285 are preferably formed successively by, for example, a sputtering method without exposure to the air environment. By forming the insulating layers 282, 283, and 285 without exposure to the air, impurities or moisture from the air environment can be prevented from adhering to the insulating layers 282, 283, and 285. This allows the vicinity of the interface between the insulating layers 282 and 283 and the vicinity of the interface between the insulating layers 283 and 285 to be kept clean.

[0343] Subsequently, heat treatment is performed. As a result, the elements contained in the layer 231a and the elements contained in the layer 231b can be added to the semiconductor layer 230. Therefore, for example, an impurity element can be supplied to the semiconductor layer 230. As a result, a low-resistance region 230na and a low-resistance region 230nb can be formed in the semiconductor layer 230. Specifically, the low-resistance region 230na can be formed in a region overlapping with the layer 231a, and the low-resistance region 230nb can be formed in a region overlapping with the layer 231b. The low-resistance region 230na contains the elements contained in the layer 231a. The low-resistance region 230nb contains the elements contained in the layer 231b.

[0344] Heat treatment may cause the components contained in the semiconductor layer 230 to be alloyed with the components contained in the layer 231a. Similarly, the components contained in the semiconductor layer 230 may be alloyed with the components contained in the layer 231b. For example, when layers 231a and 231b contain elements that are the main components of the semiconductor layer 230 and other elements, the above-mentioned alloying may occur. The alloyed regions become low-resistance regions 230na and 230nb. As a result, particularly when the film thickness of layer 231a is sufficiently thinner than the film thickness of the semiconductor layer 230, the interface between the semiconductor layer 230 and the layer 231a may not be observed, and they may be observed as being integrated. Similarly, when the film thickness of layer 231b is sufficiently thinner than the film thickness of the semiconductor layer 230, the interface between the semiconductor layer 230 and the layer 231b may not be observed, and they may be observed as being integrated. In addition, if the components contained in the semiconductor layer 230 and the components contained in the impurity layer are not alloyed, the interface between the semiconductor layer 230 and the layer 231a and the interface between the semiconductor layer 230 and the layer 231b may be observed.

[0345] The heat treatment is preferably performed at 200°C or higher and 600°C or lower, more preferably 300°C or higher and 500°C or lower. Here, for example, in the process shown in FIG. 11B, if the layer 231a is formed so that the side surface of the insulating layer 275 at the opening 289 has a region that protrudes relative to the layer 231a, the distance between the low-resistance region 230na and the channel formation region 230i can be increased. Similarly, if the layer 231b is formed so that the side surface of the insulating layer 275 at the opening 289 has a region that protrudes relative to the layer 231b, the distance between the low-resistance region 230nb and the channel formation region 230i can be increased. Therefore, for example, in the above-mentioned heat treatment, impurity elements can be prevented from being mixed into the channel formation region 230i. Therefore, the manufacturing yield of the semiconductor device can be improved. Here, the distance in the Y direction between the side surface of the layer 231a on the opening 289 side and the bottom end of the insulating layer 275 at the opening 289 can be set to distance D shown in FIG. 2A.

[0346] Although this embodiment shows an example in which heat treatment for forming the low-resistance regions 230na and 230nb is performed after the formation of the insulating layer 285, one embodiment of the present invention is not limited thereto. Heat treatment may be performed after the formation of the layers 231a and 231b and before the formation of the insulating layer 250, after the formation of the insulating layer 250 and before the formation of the conductive layer 260, after the formation of the conductive layer 260 and before the formation of the insulating layer 282, or after the formation of the conductive layer 243a and the conductive layer 243b in a later step.

[0347] 14A to 14D , an opening 244a reaching the low-resistance region 230na and an opening 244b reaching the low-resistance region 230nb are formed in the insulating layer 285, the insulating layer 283, the insulating layer 282, the insulating layer 280, and the insulating layer 275. The openings 244a and 244b can be formed using, for example, lithography. The openings 244a and 244b are preferably formed by processing the workpiece using dry etching. Because dry etching allows for anisotropic etching, it is suitable for forming openings 244a and 244b with a high aspect ratio.

[0348] Next, insulating films that will become insulating layers 241a and 241b in a later process are formed along the sidewalls of the openings 244a and 244b. The insulating films can be formed by sputtering, CVD, MBE, PLD, ALD, or the like. The insulating films that will become insulating layers 241a and 241b are preferably formed by ALD because they are formed in the openings 244a and 244b, which have a large aspect ratio. Furthermore, insulating films that have the function of suppressing oxygen permeation are preferably used as the insulating films that will become insulating layers 241a and 241b. For example, silicon nitride is preferably formed by PEALD. Silicon nitride is preferred because it has a high barrier property against hydrogen.

[0349] Next, as shown in FIGS. 14A to 14D , the insulating film is anisotropically etched to form insulating layers 241a and 241b. Here, the insulating layer 241a is formed so as to cover the sidewall of the opening 244a. Similarly, the insulating layer 241b is formed so as to cover the sidewall of the opening 244b. Dry etching or the like can be used as anisotropic etching of the insulating film that will become the insulating layers 241a and 241b. For example, reactive ion etching is preferably performed. By forming the insulating layer 241a so as to cover the sidewall of the opening 244a and the insulating layer 241b so as to cover the sidewall of the opening 244b, oxygen permeation from the outside can be suppressed, and oxidation of the conductive layers 243a and 243b, which will be formed in the next process, can be prevented. Furthermore, impurities such as water and hydrogen contained in the insulating layer 280 can be prevented from diffusing into the conductive layers 243a and 243b. Note that the anisotropic etching may form recesses in parts of the top surfaces of the conductive layers 242a and 242b.

[0350] Next, conductive films to be the conductive layers 243a and 243b are formed. The conductive films preferably have a stacked structure including a conductor that has a function of suppressing permeation of impurities such as water and hydrogen. For example, the conductive films can be stacked layers of tantalum nitride, titanium nitride, or the like, and tungsten, molybdenum, copper, or the like. The conductive films to be the conductive layers 243a and 243b can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

[0351] 14A to 14D, CMP processing is performed to remove portions of the conductive film that will become the conductive layers 243a and 243b, exposing the upper surface of the insulating layer 285. As a result, the conductive film remains only in the openings 244a and 244b, thereby forming the conductive layers 243a and 243b with flat upper surfaces. Note that the CMP processing may remove a portion of the upper surface of the insulating layer 285. As a result, the conductive layer 243a can be formed in the opening 244a so as to have a region in contact with the low-resistance region 230na. Furthermore, the conductive layer 243b can be formed in the opening 244b so as to have a region in contact with the low-resistance region 230nb.

[0352] After the conductive layers 243a and 243b are formed, heat treatment may be further performed. The heat treatment may be performed under the same conditions as those of the above-described heat treatment. By performing the heat treatment, the amount of oxygen supplied to the semiconductor layer 230 can be adjusted. This can improve the electrical characteristics and reliability of the transistor 200A.

[0353] Through the above steps, a semiconductor device including the transistor 200A can be manufactured.

[0354] <Second Example of Manufacturing Method of Semiconductor Device> An example of a method for manufacturing a semiconductor device including the transistor 200B shown in Fig. 3A will be described below with reference to Fig. 15A to Fig. 16B. Fig. 15A to Fig. 16B are cross-sectional views corresponding to Fig. 3A.

[0355] 8A to 10D are performed. Then, as shown in FIG. 15A , the insulating layer 280, the insulating layer 275, and the layer 231 are processed by lithography. By processing the insulating layer 280 and the insulating layer 275, an opening 289 having a region overlapping with the semiconductor layer 230 is formed in the insulating layer 280 and the insulating layer 275. In addition, the layer 231 is divided to form layers 231a and 231b. The opening 289 is formed to have a region overlapping with the conductive layer 205.

[0356] 15A , the insulating layer 280, the insulating layer 275, and the layer 231 can be processed using, for example, an etching method. Dry etching is particularly suitable for fine processing and is therefore preferable. At least one of the processing conditions for the insulating layer 280, the processing conditions for the insulating layer 275, and the processing conditions for the layer 231 may be different from the other two. For example, it is preferable to process the insulating layer 275 under conditions that provide a high etching selectivity with respect to the layer 231, and to process the layer 231 under conditions that are different from the processing conditions for the insulating layer 275.

[0357] 15A , a recess 287 is formed in the semiconductor layer 230. The recess 287 is formed at a position overlapping with the opening 289. For example, if the layer 231 is processed under conditions that provide a low etching selectivity with respect to the semiconductor layer 230, the recess 287 can be formed under the same conditions as those for processing the layer 231.

[0358] 15B , layers 231a and 231b are processed in a direction parallel to the reference plane. For example, layers 231a and 231b are processed in a direction perpendicular to the Z direction, i.e., in the X direction, Y direction, or the like. In other words, the side surface of layer 231a facing opening 289 and the side surface of layer 231b facing opening 289 are recessed. As a result, layers 231a and 231b are formed so that the side surface of insulating layer 275 at opening 289 and the side surface of insulating layer 280 at opening 289 have regions that protrude relative to layer 231a and regions that protrude relative to layer 231b.

[0359] 15B, the layers 231a and 231b can be processed using, for example, dry etching or wet etching. When the layers 231a and 231b are processed using dry etching, the layers 231a and 231b are processed under conditions that are more isotropic than the conditions for processing the layer 231 in the step shown in FIG. 15A. For example, the layers 231a and 231b can be processed under conditions similar to the second conditions in the steps shown in FIGS. 11A to 11D.

[0360] 12A to 13B are then performed. As described above, by performing the heat treatment, the components contained in the semiconductor layer 230 and the components contained in the layer 231a may be alloyed. Similarly, the components contained in the semiconductor layer 230 and the components contained in the layer 231b may be alloyed. For example, the alloyed regions may be the low-resistance region 230na and the low-resistance region 230nb.

[0361] The above-described heat treatment may result in the formation of a region 230nc and a region 230nd, as shown in FIG. 16A . The region 230nc is formed so as to be located between the low-resistance region 230na and the channel formation region 230i in a planar view. The region 230nd is formed so as to be located between the low-resistance region 230nb and the channel formation region 230i in a planar view. The region 230nc is formed so as to have a region in contact with the side surface of the low-resistance region 230na on the opening 289 side and a region in contact with the bottom surface of the insulating layer 250. The region 230nd is formed so as to have a region in contact with the side surface of the low-resistance region 230nb on the opening 289 side and a region in contact with the bottom surface of the insulating layer 250. The region 230nc is formed, for example, by the diffusion of an impurity element contained in the low-resistance region 230na. Similarly, the region 230nd is formed, for example, by the diffusion of an impurity element contained in the low-resistance region 230nb.

[0362] The regions 230nc and 230nd can function as LDD regions as described above, so that a semiconductor device including a transistor with a high drain breakdown voltage can be manufactured.

[0363] 15A, by forming a recess 287 in the semiconductor layer 230, the region 230nc and the channel formation region 230i can be separated. The region 230nd and the channel formation region 230i can also be separated. This prevents impurity elements contained in the region 230nc and the region 230nd from being mixed into the channel formation region 230i by, for example, the above-described heat treatment. As a result, the manufacturing yield of the semiconductor device can be improved. Note that, as described above, the region 230nc and the region 230nd may not be formed.

[0364] 14A to 14D are then performed. As a result, openings 244a and 244b are formed as shown in FIG. 16B. An insulating layer 241a and a conductive layer 243a are formed in the opening 244a, and an insulating layer 241b and a conductive layer 243b are formed in the opening 244b. In this manner, a semiconductor device including the transistor 200B can be manufactured.

[0365] <Example 3 of Manufacturing Method of Semiconductor Device> An example of a method for manufacturing a semiconductor device including the transistor 200C shown in Figures 4A to 4C will be described below with reference to Figures 17A to 18B. Figures 17A to 18B are cross-sectional views corresponding to Figure 4B.

[0366] 8A to 8D are performed. Then, as shown in Fig. 17A, a conductive film 242f is formed over the film 231f. The conductive film 242f can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, or an ALD method.

[0367] 17B, ​​the insulating film 224f, the semiconductor film 230f, the film 231f, and the conductive film 242f are processed into, for example, an island shape. This forms the insulating layer 224, the semiconductor layer 230, the layer 231, and the conductive layer 242. A dry etching method or a wet etching method can be used for the above processing. Processing by the dry etching method is suitable for microfabrication. Furthermore, the insulating film 224f, the semiconductor film 230f, the film 231f, and the conductive film 242f may be processed under different conditions.

[0368] Here, the insulating film 224f, the semiconductor film 230f, the film 231f, and the conductive film 242f are preferably processed collectively into an island shape. At this time, the upper end of the insulating layer 224 preferably coincides or substantially coincides with the lower end of the semiconductor layer 230. Furthermore, the upper end of the semiconductor layer 230 preferably coincides or substantially coincides with the lower end of the layer 231. Furthermore, the upper end of the layer 231 preferably coincides or substantially coincides with the lower end of the conductive layer 242.

[0369] 10A to 10D are then performed. That is, an insulating layer 275 is formed on the conductive layer 242 and the insulating layer 222, and an insulating layer 280 is formed on the insulating layer 275.

[0370] 11A to 11D, openings 289 are formed in the insulating layer 280 and the insulating layer 275, as shown in FIG. 17C. Thereafter, the conductive layer 242 and the layer 231 are processed. By processing the conductive layer 242, the conductive layer 242 is divided, and conductive layers 242a and 242b are formed. Furthermore, by processing the layer 231, the layer 231 is divided, and layers 231a and 231b are formed.

[0371] 17C , the insulating layer 280, the insulating layer 275, the conductive layer 242, and the layer 231 can be processed using, for example, an etching method. Dry etching is particularly suitable for fine processing and is therefore preferable. Note that at least one of the processing conditions for the insulating layer 280, the processing conditions for the insulating layer 275, the processing conditions for the conductive layer 242, and the processing conditions for the layer 231 may be different from the other two. For example, it is preferable to process the insulating layer 275 under conditions that provide a high etching selectivity with respect to the layer 231, and to process the layer 231 under conditions that are different from the processing conditions for the insulating layer 275.

[0372] 13A to 13D are then performed. As a result, as shown in Fig. 18A, an insulating layer 250, a conductive layer 260, an insulating layer 282, an insulating layer 283, and an insulating layer 285 are formed. Furthermore, a heat treatment is performed to alloy the semiconductor layer 230 with the layer 231a and the layer 231b, thereby forming low-resistance regions 230na and 230nb, respectively.

[0373] 18B, an opening 244a reaching the conductive layer 242a and an opening 244b reaching the conductive layer 242b are formed in the insulating layer 285, the insulating layer 283, the insulating layer 282, the insulating layer 280, and the insulating layer 275. For the formation of the opening 244a and the opening 244b, refer to the descriptions of FIGS. 14A to 14D.

[0374] Subsequently, an insulating layer 241a, an insulating layer 241b, a conductive layer 243a, and a conductive layer 243b are formed. For the formation of the insulating layer 241a, the insulating layer 241b, the conductive layer 243a, and the conductive layer 243b, refer to the descriptions of FIGS. 14A to 14D.

[0375] Through the above steps, a semiconductor device including the transistor 200C can be manufactured.

[0376] This embodiment mode can be combined with other embodiment modes as appropriate. In addition, in this specification, when a plurality of configuration examples are shown in one embodiment mode, the configuration examples can be combined as appropriate.

[0377] Embodiment 2 In this embodiment, a semiconductor device 900 according to one embodiment of the present invention will be described. The semiconductor device 900 can function as a memory device.

[0378] Fig. 19 is a block diagram showing a configuration example of a semiconductor device 900. The semiconductor device 900 shown in Fig. 19 has a driver circuit 910 and a memory array 920. The memory array 920 has one or more memory cells 950. Fig. 19 shows an example in which the memory array 920 has a plurality of memory cells 950 arranged in a matrix.

[0379] The semiconductor device described in Embodiment 1, for example, a semiconductor device including the transistor 200, can be applied to the memory cell 950. By using the transistor described in Embodiment 1, the operation speed of the memory device can be improved. Furthermore, miniaturization and high integration of the memory device can be achieved. Furthermore, the capacitance per area of ​​the memory device can be increased.

[0380] The drive circuit 910 includes a PSW 931 (power switch), a PSW 932, and a peripheral circuit 915. The peripheral circuit 915 includes a peripheral circuit 911, a control circuit 912, and a voltage generation circuit 928.

[0381] In the semiconductor device 900, each circuit, signal, and voltage can be appropriately selected or omitted as needed. Alternatively, other circuits or signals may be added. The signals BW, CE, GW, CLK, WAKE, ADDR, WDA, PON1, and PON2 are input signals from the outside, and the signal RDA is an output signal to the outside. The signal CLK is a clock signal.

[0382] Furthermore, signals BW, CE, and GW are control signals. Signal CE is a chip enable signal, signal GW is a global write enable signal, and signal BW is a byte write enable signal. Signal ADDR is an address signal. Signal WDA is a write data signal, and signal RDA is a read data signal. Signals PON1 and PON2 are power gating control signals. Note that signals PON1 and PON2 may be generated by the control circuit 912.

[0383] The control circuit 912 is a logic circuit having a function of controlling the overall operation of the semiconductor device 900. For example, the control circuit 912 performs a logical operation on the signals CE, GW, and BW to determine the operation mode (e.g., write operation, read operation) of the semiconductor device 900. Alternatively, the control circuit 912 generates a control signal for the peripheral circuit 911 so that this operation mode is executed.

[0384] The voltage generating circuit 928 has a function of generating a negative voltage. The signal WAKE has a function of controlling the input of the signal CLK to the voltage generating circuit 928. For example, when an H-level signal is given as the signal WAKE, the signal CLK is input to the voltage generating circuit 928, and the voltage generating circuit 928 generates a negative voltage.

[0385] The peripheral circuit 911 is a circuit for writing and reading data to and from the memory cells 950. The peripheral circuit 911 includes a row decoder 941, a column decoder 942, a row driver 923, a column driver 924, an input circuit 925, an output circuit 926, and a sense amplifier 927.

[0386] The row decoder 941 and the column decoder 942 have the function of decoding the signal ADDR. The row decoder 941 is a circuit for specifying a row to be accessed, and the column decoder 942 is a circuit for specifying a column to be accessed. The row driver 923 has the function of selecting the row specified by the row decoder 941. The column driver 924 has the function of writing data to the memory cells 950, reading data from the memory cells 950, and retaining the read data.

[0387] The input circuit 925 has a function of holding a signal WDA. The data held by the input circuit 925 is output to the column driver 924. The output data of the input circuit 925 is data (Din) to be written to the memory cell 950. The data (Dout) read from the memory cell 950 by the column driver 924 is output to the output circuit 926. The output circuit 926 has a function of holding Dout. In addition, the output circuit 926 has a function of outputting Dout to the outside of the semiconductor device 900. The data output from the output circuit 926 is a signal RDA.

[0388] The PSW 931 is a V ＤＤ The PSW 932 has the function of controlling the supply of V to the row driver 923. ＨＭ Here, the high power supply potential of the semiconductor device 900 is V ＤＤ and the low power supply potential is GND (ground potential). ＨＭ is the high power supply potential used to drive the word line high, and V ＤＤ 19, in the peripheral circuit 915, V ＤＤ Although the number of power domains to which power is supplied is set to one, it may be set to a plurality of power domains. In this case, a power switch can be provided for each power domain.

[0389] 20A to 20G, examples of memory cell configurations that can be applied to the memory cell 950 will be described.

[0390] 20A shows an example of a circuit configuration of a memory cell of a dynamic random access memory (DRAM). In this specification and the like, a DRAM using an OS transistor is referred to as a dynamic oxide semiconductor random access memory (DOSRAM). The memory cell 951 includes a transistor M1 and a capacitor CA.

[0391] The transistor M1 may have a front gate (sometimes simply referred to as a gate) and a back gate. In this case, the back gate may be connected to a wiring to which a constant potential or a signal is applied, or the front gate and the back gate may be connected to each other.

[0392] A first terminal of the transistor M1 is connected to a first terminal of the capacitance element CA, a second terminal of the transistor M1 is connected to the wiring BIL, and a gate of the transistor M1 is connected to the wiring WOL. The second terminal of the capacitance element CA is connected to the wiring CAL.

[0393] The wiring BIL functions as a bit line, and the wiring WOL functions as a word line. The wiring CAL functions as a wiring for applying a predetermined potential to the second terminal of the capacitance element CA. When writing and reading data, it is preferable to apply a low-level potential (sometimes referred to as a reference potential) to the wiring CAL.

[0394] Data is written and read by applying a high-level potential to the wiring WOL, turning on the transistor M1, and bringing the wiring BIL and the first terminal of the capacitor CA into a conductive state (a state in which current can flow).

[0395] Furthermore, the memory cell that can be used as the memory cell 950 is not limited to the memory cell 951, and the circuit configuration can be changed. For example, the memory cell 952 shown in FIG. 20B may be used. The memory cell 952 is an example in which the memory cell 952 does not include a capacitor CA and a wiring CAL. The first terminal of the transistor M1 is in an electrically floating state.

[0396] In the memory cell 952, the potential written through the transistor M1 is held in a capacitance (also referred to as a parasitic capacitance) between the first terminal and the gate, which is indicated by a dashed line. With this configuration, the configuration of the memory cell can be significantly simplified.

[0397] Note that an OS transistor is preferably used as the transistor M1. Use of an OS transistor can improve the operation speed of the memory device. Furthermore, an OS transistor has a characteristic of having an extremely low off-state current. By using an OS transistor as the transistor M1, the leakage current of the transistor M1 can be made extremely small. That is, written data can be held by the transistor M1 for a long time, which reduces the frequency of refreshing the memory cell. Alternatively, the refresh operation of the memory cell can be made unnecessary. Furthermore, since the leakage current is extremely small, multilevel data or analog data can be held in the memory cell 951 and the memory cell 952.

[0398] An example of the structure of a DOSRAM will now be described with reference to Fig. 21. In Fig. 21, the X direction is parallel to the channel width direction of the transistor, the Y direction is perpendicular to the X direction, and the Z direction is perpendicular to the X and Y directions.

[0399] As shown in FIG. 21 , the memory cell 951 includes a transistor M1 and a capacitor CA. An insulating layer 284 is provided over the transistor M1. The insulating layer 284 can be formed using an insulator that can be used for the insulating layer 216. The transistor M1 has a similar structure to the transistor 200 described in Embodiment 1, and the same components are denoted by the same reference numerals. For details of the transistor 200, refer to Embodiment 1. A conductive layer 243b (conductive layer 243b1 and conductive layer 243b2) is provided in contact with the low-resistance region 230nb. The conductive layer 243b extends in the Z direction and functions as a wiring BIL. The conductive layer 260 of the transistor M1 extends in the X direction and functions as a wiring WOL.

[0400] The capacitance element CA has a conductive layer 453 on the low-resistance region 230na, an insulating layer 454 on the conductive layer 453, and a conductive layer 460 (conductive layer 460a and conductive layer 460b) on the insulating layer 454. The conductive layer 453 has a region in contact with the low-resistance region 230na, for example, a region in contact with the upper surface of the low-resistance region 230na.

[0401] At least a portion of the conductive layer 453, the insulating layer 454, and the conductive layer 460 is disposed in an opening 461 provided in the insulating layer 275, the insulating layer 280, the insulating layer 282, the insulating layer 283, and the insulating layer 285, respectively. Ends of the conductive layer 453, the insulating layer 454, and the conductive layer 460 are located at least on the insulating layer 283, and preferably on the insulating layer 285. The insulating layer 454 is provided so as to cover an end of the conductive layer 453. This allows the conductive layer 453 and the conductive layer 460 to be electrically insulated from each other.

[0402] The deeper the opening 461, i.e., the thicker the thickness of one or more of the insulating layers 275, 280, 282, 283, and 285, the larger the capacitance of the capacitor CA. Increasing the capacitance per unit area of ​​the capacitor CA allows for miniaturization or high integration of a memory device. For example, the capacitance of the capacitor CA can be set by adjusting the thickness of the insulating layer 285. Specifically, the thickness of the insulating layer 285 can be set to a range of 50 nm to 250 nm, and the depth of the opening 461 can be set to approximately 150 nm to 350 nm. Forming the capacitor CA within such a range allows the capacitor CA to have sufficient capacitance, and prevents the height of one layer from becoming excessively high in a semiconductor device in which multiple memory cell layers are stacked. Note that the capacitance of the capacitors provided in each memory cell may be different in each of the multiple memory cell layers. In this configuration, for example, the thickness of the insulating layer 285 provided in each memory cell layer can be made different.

[0403] In the capacitor CA, the conductive layer 453 has a region that functions as one electrode (lower electrode), the insulating layer 454 has a region that functions as a dielectric, and the conductive layer 460 has a region that functions as the other electrode (upper electrode). The upper portion of the conductive layer 460 can be extended to function as a wiring CAL. The capacitor CA forms a metal-insulator-metal (MIM) capacitor. At least a portion of the conductive layer 453 functions as one of the source electrode and drain electrode of the transistor M1.

[0404] The conductive layer 453 and the conductive layer 460 can be formed using a material that can be used for the conductive layer 205 or the conductive layer 260. The conductive layer 453 and the conductive layer 460 are preferably formed by a film formation method with good coverage, such as an ALD method or a CVD method. For example, the conductive layer 453 can be formed using titanium nitride or tantalum nitride formed by an ALD method or a CVD method.

[0405] Alternatively, the conductive layer 460a may be formed using titanium nitride by an ALD method or a CVD method, and the conductive layer 460b may be formed using tungsten by a CVD method. Note that if the adhesion of tungsten to the insulating layer 454 is sufficiently high, the conductive layer 460 may have a single-layer structure of tungsten formed by a CVD method.

[0406] The insulating layer 454 of the capacitor CA is preferably formed using a high-dielectric-constant (high-k) material as described in the previous embodiment. By using such a high-k material, the insulating layer 454 can be thick enough to suppress leakage current and ensure sufficient capacitance of the capacitor CA. The insulating layer 454 is preferably formed using a film formation method with good coverage, such as an ALD method or a CVD method.

[0407] Furthermore, it is preferable to use a laminated insulating layer made of the above materials, and it is preferable to use a laminated structure of a material with a high dielectric constant (high-k) and a material with a higher dielectric strength than the high dielectric constant (high-k) material. For example, an insulating film formed by laminating zirconium oxide, aluminum oxide, and zirconium oxide in this order can be used as the insulating layer 454. Alternatively, it is possible to use an insulating film formed by laminating zirconium oxide, aluminum oxide, zirconium oxide, and aluminum oxide in this order. Alternatively, it is possible to use an insulating film formed by laminating hafnium zirconium oxide, aluminum oxide, hafnium zirconium oxide, and aluminum oxide in this order. By using a laminated insulator with a relatively high dielectric strength, such as aluminum oxide, the dielectric strength is improved, and electrostatic breakdown of the capacitance element CA can be suppressed.

[0408] Further, the insulating layer 454 may be formed using the material that can have ferroelectricity described in the [Insulating Layer] section of Embodiment Mode 1.

[0409] A ferroelectric material is an insulator that generates polarization internally when an external electric field is applied, and the polarization remains even when the electric field is removed. Therefore, a nonvolatile memory element can be formed using a capacitance element (hereinafter sometimes referred to as a ferroelectric capacitor) that uses this material as a dielectric. A nonvolatile memory element using a ferroelectric capacitor is sometimes called a Ferroelectric Random Access Memory (FeRAM), a ferroelectric memory, or the like. For example, a ferroelectric memory includes a transistor and a ferroelectric capacitor, and one of the source and drain of the transistor is electrically connected to one terminal of the ferroelectric capacitor. Therefore, when a ferroelectric capacitor is used as the capacitance element CA, the memory device described in this embodiment functions as a ferroelectric memory.

[0410] Note that the sidewall of the opening 461 may be perpendicular or approximately perpendicular to the top surface of the insulating layer 222, or may have a tapered shape. By tapering the sidewall of the opening 461, coverage of the conductive layer 453 or the like provided in the opening 461 can be improved, and defects such as voids can be reduced.

[0411] By having the conductive layer 243b directly contact at least one of the upper surface and side edge of the low-resistance region 230nb, there is no need to provide a separate connection electrode, thereby reducing the area occupied by the memory array. Furthermore, the integration density of memory cells is improved, allowing for an increase in the storage capacity of the storage device. It is preferable that the conductive layer 243b contact a portion of the upper surface and side edge of the low-resistance region 230nb. By having the conductive layer 243b contact multiple surfaces of the low-resistance region 230nb, the contact resistance between the conductive layer 243b and the low-resistance region 230nb can be reduced.

[0412] The conductive layer 243b is provided in an opening 463 formed in the insulating layer 216, the insulating layer 221, the insulating layer 222, the insulating layer 275, the insulating layer 280, the insulating layer 282, the insulating layer 283, the insulating layer 285, and the insulating layer 284.

[0413] 21 , an insulating layer 241b is preferably provided in contact with the side surface of the conductive layer 243b. Specifically, the insulating layer 241b is provided in contact with the side wall of the opening 463. The insulating layer 241b is also formed on the side surface of the semiconductor layer 230, which is formed to protrude into the opening 463. Here, at least a portion of the low-resistance region 230nb is exposed from the insulating layer 241b and is in contact with the conductive layer 243b. In other words, the conductive layer 243b is provided so as to fill the opening 463 via the insulating layer 241b.

[0414] 21 , the uppermost portion of the insulating layer 241b formed below the low-resistance region 230nb is preferably located below the upper surface of the low-resistance region 230nb. This configuration allows the conductive layer 243b to contact at least a portion of the side edge of the low-resistance region 230nb. The insulating layer 241b formed below the low-resistance region 230nb preferably has a region that contacts the side surface of the semiconductor layer 230. This configuration can prevent impurities such as water and hydrogen contained in the insulating layer 280 from entering the semiconductor layer 230 through the conductive layer 243b.

[0415] The sidewall of the opening 463 may be perpendicular or approximately perpendicular to the top surface of the insulating layer 222, or may be tapered. The tapered sidewall improves coverage of the opening 463 with the insulating layer 241b or the like.

[0416] 20C shows an example circuit configuration of a gain cell type memory cell having two transistors and one capacitor. The memory cell 953 includes a transistor M2, a transistor M3, and a capacitor CB. In this specification and the like, a memory device having a gain cell type memory cell in which the transistor M2 is an OS transistor is referred to as a nonvolatile oxide semiconductor RAM (NOSRAM).

[0417] The first terminal of transistor M2 is connected to the first terminal of capacitance element CB, the second terminal of transistor M2 is connected to wiring WBL, and the gate of transistor M2 is connected to wiring WOL. The second terminal of capacitance element CB is connected to wiring CAL. The first terminal of transistor M3 is connected to wiring RBL, the second terminal of transistor M3 is connected to wiring SL, and the gate of transistor M3 is connected to the first terminal of capacitance element CB.

[0418] The wiring WBL functions as a write bit line, the wiring RBL functions as a read bit line, and the wiring WOL functions as a word line. The wiring CAL functions as a wiring for applying a predetermined potential to the second terminal of the capacitance element CB. When writing data, while retaining data, and when reading data, it is preferable to apply a low-level potential (sometimes referred to as a reference potential) to the wiring CAL.

[0419] Data is written by applying a high-level potential to the wiring WOL, turning on the transistor M2, and establishing electrical continuity between the wiring WBL and the first terminal of the capacitor CB. Specifically, when the transistor M2 is on, a potential corresponding to the information to be recorded is applied to the wiring WBL, and the potential is written to the first terminal of the capacitor CB and the gate of the transistor M3. Then, a low-level potential is applied to the wiring WOL, turning off the transistor M2, thereby maintaining the potential of the first terminal of the capacitor CB and the potential of the gate of the transistor M3.

[0420] Data is read by applying a predetermined potential to the wiring SL. The current flowing between the source and drain of the transistor M3 and the potential of the first terminal of the transistor M3 are determined by the potential of the gate of the transistor M3 and the potential of the second terminal of the transistor M3. Therefore, the potential held in the first terminal of the capacitor CB (or the gate of the transistor M3) can be read by reading the potential of the wiring RBL connected to the first terminal of the transistor M3. In other words, information written in this memory cell can be read from the potential held in the first terminal of the capacitor CB (or the gate of the transistor M3).

[0421] Alternatively, for example, the wiring WBL and the wiring RBL may be combined into a single wiring BIL. An example circuit configuration of such a memory cell is shown in FIG. 20D . The memory cell 954 is configured such that the wiring WBL and the wiring RBL of the memory cell 953 are combined into a single wiring BIL, and the second terminal of the transistor M2 and the first terminal of the transistor M3 are connected to the wiring BIL. In other words, the memory cell 954 is configured such that the write bit line and the read bit line operate as a single wiring BIL.

[0422] 20E is an example in which the capacitor element CB and the wiring CAL are omitted from the memory cell 953. Also, the memory cell 956 shown in Fig. 20F is an example in which the capacitor element CB and the wiring CAL are omitted from the memory cell 954. With such a configuration, the integration degree of the memory cells can be increased.

[0423] Note that it is preferable to use an OS transistor for at least the transistor M2. In particular, it is preferable to use OS transistors for the transistors M2 and M3. By using an OS transistor as the transistor M2, written data can be held by the transistor M2 for a long time, which reduces the frequency of refreshing the memory cell. Alternatively, the refresh operation of the memory cell can be eliminated. Furthermore, since the leakage current is extremely small, multilevel data or analog data can be held in the memory cells 953 to 956.

[0424] The memory cells 953 to 956 in which an OS transistor is used as the transistor M2 are one embodiment of NOSRAM.

[0425] Note that a Si transistor may be used as the transistor M3. The Si transistor can increase the field effect mobility and can also be used as a p-channel transistor, thereby increasing the degree of freedom in circuit design.

[0426] 20G shows a three-transistor, one-capacitor gain cell type memory cell 957. The memory cell 957 has transistors M4 to M6 and a capacitor CC.

[0427] The first terminal of transistor M4 is connected to the first terminal of capacitor CC, the second terminal of transistor M4 is connected to wiring BIL, and the gate of transistor M4 is connected to wiring WOL. The second terminal of capacitor CC is connected to the first terminal of transistor M5 and wiring GNDL. The second terminal of transistor M5 is connected to the first terminal of transistor M6, and the gate of transistor M5 is connected to the first terminal of capacitor CC. The second terminal of transistor M6 is connected to wiring BIL, and the gate of transistor M6 is connected to wiring RWL.

[0428] The wiring BIL functions as a bit line, the wiring WOL functions as a write word line, and the wiring RWL functions as a read word line. The wiring GNDL is a wiring that applies a low-level potential.

[0429] Data is written by applying a high-level potential to the wiring WOL, turning on the transistor M4, and establishing electrical continuity between the wiring BIL and the first terminal of the capacitor CC. Specifically, when the transistor M4 is on, a potential corresponding to the information to be recorded is applied to the wiring BIL, and the potential is written to the first terminal of the capacitor CC and the gate of the transistor M5. Then, a low-level potential is applied to the wiring WOL, turning off the transistor M4, thereby maintaining the potential of the first terminal of the capacitor CC and the potential of the gate of the transistor M5.

[0430] Data is read by precharging the wiring BIL to a predetermined potential, then electrically floating the wiring BIL, and applying a high-level potential to the wiring RWL. Because the wiring RWL is at a high-level potential, the transistor M6 is turned on, and the wiring BIL and the second terminal of the transistor M5 are electrically connected. At this time, the potential of the wiring BIL is applied to the second terminal of the transistor M5. The potential of the second terminal of the transistor M5 and the potential of the wiring BIL change depending on the potential held in the first terminal of the capacitor CC (or the gate of the transistor M5). By reading the potential of the wiring BIL, the potential held in the first terminal of the capacitor CC (or the gate of the transistor M5) can be read. In other words, information written in this memory cell can be read from the potential held in the first terminal of the capacitor CC (or the gate of the transistor M5).

[0431] Note that at least the transistor M4 is preferably an OS transistor.

[0432] Note that Si transistors may be used as the transistors M5 and M6. As described above, Si transistors may have higher field-effect mobility than OS transistors depending on the crystalline state of silicon used in the semiconductor layer.

[0433] The driver circuit 910 and memory array 920 of the semiconductor device 900 may be provided on the same plane. Alternatively, as shown in FIG. 22A, the driver circuit 910 and memory array 920 may be provided overlapping each other. By providing the driver circuit 910 and memory array 920 overlapping each other, the signal propagation distance can be shortened. Alternatively, as shown in FIG. 22B, the memory array 920 may be provided in multiple layers on the driver circuit 910.

[0434] Here, an example of the configuration of a semiconductor device 900 in which memory arrays 920 are stacked in multiple layers will be described with reference to FIG.

[0435] 23 includes a driver circuit 910 including a transistor 310 and memory arrays 920[1] to 920[m] on the driver circuit 910. Here, the memory array 920 provided in the first layer (bottom) is referred to as memory array 920[1], the memory array 920 provided in the second layer is referred to as memory array 920[2], and the memory array 920 provided in the m-th layer (top) is referred to as memory array 920[m] in FIG. 23. That is, the memory device of one embodiment of the present invention may have a structure in which a plurality of layers including memory cells are stacked.

[0436] 23 illustrates a transistor 310 included in a driver circuit 910. The transistor 310 is provided over a substrate 311 and includes a conductive layer 316 functioning as a gate, an insulating layer 315 functioning as a gate insulating layer, a semiconductor region 313 including part of the substrate 311, and low-resistance regions 314a and 314b functioning as source and drain regions. An element isolation layer 318 is preferably provided between adjacent transistors 310. The transistor 310 may be either a p-channel transistor or an n-channel transistor. The substrate 311 may be, for example, a single crystal silicon substrate.

[0437] Here, in the transistor 310, a semiconductor region 313 (a part of the substrate 311) in which a channel is formed has a convex shape. A conductive layer 316 is provided to cover the side and top surfaces of the semiconductor region 313 with an insulating layer 315 interposed therebetween. Note that the conductive layer 316 may be made of a material that adjusts the work function. Such a transistor 310 is also called a FIN-type transistor because it utilizes the convex portions of the semiconductor substrate. Note that an insulating layer that is in contact with the top of the convex portions and functions as a mask for forming the convex portions may be provided. Here, the case where the convex portions are formed by processing a part of the semiconductor substrate is shown, but a semiconductor film having a convex shape may also be formed by processing an SOI substrate.

[0438] Note that the transistor 310 illustrated in FIG. 23 is just an example, and the structure is not limited thereto. An appropriate transistor can be used depending on the circuit configuration or driving method.

[0439] Between each structure, a wiring layer provided with an interlayer film, wiring, plugs, etc. may be provided. Furthermore, multiple wiring layers may be provided depending on the design. Here, for a conductive layer that functions as a plug or wiring, the same reference numeral may be used to refer to multiple structures. Furthermore, in this specification and the like, the wiring and the plug electrically connected to the wiring may be integrated. That is, there are cases where a part of the conductive layer functions as the wiring, and cases where a part of the conductive layer functions as the plug.

[0440] For example, an insulating layer 320, an insulating layer 322, an insulating layer 324, and an insulating layer 326 are stacked in this order as an interlayer film over the transistor 310. A conductive layer 328 and the like are embedded in the insulating layer 320 and the insulating layer 322. A conductive layer 330 and the like are embedded in the insulating layer 324 and the insulating layer 326. The conductive layer 328 and the conductive layer 330 function as contact plugs or wirings.

[0441] The insulating layer 322 may also function as a planarizing film that covers the underlying unevenness. For example, the top surface of the insulating layer 322 may be planarized by CMP treatment to improve the planarity.

[0442] Insulators that can be used as the interlayer film include oxides, nitrides, oxynitrides, nitride oxides, metal oxides, metal oxynitrides, and metal nitride oxides, which have insulating properties.

[0443] For example, by using a material with a low dielectric constant for the insulating layer that functions as an interlayer film, the parasitic capacitance that occurs between wirings can be reduced. Therefore, it is preferable to select a material depending on the function of the insulating layer.

[0444] An insulating layer 208 is provided on the driver circuit 910, and a conductive layer 207 is provided in an opening formed in the insulating layer 208. Furthermore, an insulating layer 210 is provided on the insulating layer 208, and a conductive layer 209 is provided in an opening formed in the insulating layer 210. Furthermore, an insulating layer 212 is provided on the insulating layer 210, and an insulating layer 214 is provided on the insulating layer 212. Part of a conductive layer 243b provided in the memory array 920[1] is buried in the openings formed in the insulating layer 212 and the insulating layer 214. Here, the insulating layer 208 and the insulating layer 210 can use an insulator applicable to the insulating layer 216.

[0445] The conductive layer 207 functions as a wiring electrically connected to the driver circuit 910. The top surface of the conductive layer 207 is in contact with the bottom surface of the conductive layer 209. The top surface of the conductive layer 209 is in contact with the bottom surface of the conductive layer 243b provided in the memory array 920[1]. With this structure, the conductive layer 243b corresponding to the wiring BIL can be electrically connected to the driver circuit 910.

[0446] Each of the memory arrays 920[1] to 920[m] includes a plurality of memory cells 951. The conductive layer 243b of each memory cell 951 is electrically connected to the conductive layer 243b in the upper layer and the conductive layer 243b in the lower layer.

[0447] 23, the conductive layer 243b is shared by adjacent memory cells 951. In addition, in the adjacent memory cells 951, the configuration on the right side and the configuration on the left side are arranged symmetrically with respect to the conductive layer 243b.

[0448] In the above-described memory array 920, a plurality of memory arrays 920[1] to 920[m] can be stacked. The memory arrays 920[1] to 920[m] included in the memory array 920 can be arranged in the vertical direction of the substrate surface on which the driver circuit 910 is provided, thereby improving the memory density of the memory cells 951. Furthermore, the memory array 920 can be manufactured by repeatedly using the same manufacturing process in the vertical direction. The semiconductor device 900 can reduce the manufacturing cost of the memory array 920.

[0449] Next, an example of a processing unit that can include a semiconductor device such as the memory device will be described.

[0450] 24 shows a block diagram of the arithmetic device 960. The arithmetic device 960 shown in FIG. 24 can be applied to, for example, a CPU. The arithmetic device 960 can also be applied to processors such as a GPU (Graphics Processing Unit), a TPU (Tensor Processing Unit), and an NPU (Neural Processing Unit) that have a larger number (several tens to several hundreds) of processor cores capable of parallel processing than a CPU.

[0451] The arithmetic device 960 shown in FIG. 24 has an ALU 962 (ALU: Arithmetic logic unit, arithmetic circuit), an ALU controller 962c, an instruction decoder 963, an interrupt controller 964, a timing controller 965, a register 966, a register controller 967, a bus interface 968, a cache 969, and a cache interface 969i on a substrate 961. The substrate 961 may be a semiconductor substrate, an SOI substrate, a glass substrate, or the like. It may also have a rewritable ROM and a ROM interface. The cache 969 and the cache interface 969i may also be provided on separate chips.

[0452] The cache 969 is connected to a main memory provided on a separate chip via a cache interface 969i. The cache interface 969i has a function of supplying part of the data held in the main memory to the cache 969. The cache interface 969i also has a function of outputting part of the data held in the cache 969 to the ALU 962, register 966, etc. via the bus interface 968.

[0453] As will be described later, a memory array 920 can be provided stacked on the arithmetic unit 960. The memory array 920 can be used as a cache. In this case, the cache interface 969i may have a function of supplying data held in the memory array 920 to the cache 969. In this case, it is preferable that a drive circuit 910 be provided as part of the cache interface 969i.

[0454] It is also possible to use only the memory array 920 as a cache without providing the cache 969 .

[0455] The arithmetic device 960 shown in FIG. 24 is merely an example of a simplified configuration, and actual arithmetic devices 960 have a wide variety of configurations depending on their applications. For example, it is preferable to use a configuration including the arithmetic device 960 shown in FIG. 24 as one core, and to include multiple such cores, each of which operates in parallel, in a so-called multi-core configuration. The greater the number of cores, the higher the computational performance. The greater the number of cores, for example, two, preferably four, more preferably eight, even more preferably twelve, and even more preferably sixteen or more. Furthermore, when extremely high computational performance is required, such as for server applications, a multi-core configuration having 16 or more, preferably 32 or more, and even more preferably 64 or more cores is preferable. Furthermore, the number of bits that the arithmetic device 960 can handle in its internal computation circuit, data bus, etc. can be, for example, 8 bits, 16 bits, 32 bits, 64 bits, etc.

[0456] An instruction input to the arithmetic unit 960 via the bus interface 968 is input to the instruction decoder 963, decoded, and then input to the ALU controller 962c, the interrupt controller 964, the register controller 967, and the timing controller 965.

[0457] The ALU controller 962c, interrupt controller 964, register controller 967, and timing controller 965 perform various controls based on the decoded instructions. Specifically, the ALU controller 962c generates signals for controlling the operation of the ALU 962. Furthermore, the interrupt controller 964 determines and processes interrupt requests from external input / output devices, peripheral circuits, etc. based on their priority, mask status, etc. while the arithmetic unit 960 is executing a program. The register controller 967 generates an address for the register 966 and reads and writes data from and to the register 966 depending on the state of the arithmetic unit 960.

[0458] Furthermore, the timing controller 965 generates signals that control the timing of the operations of the ALU 962, the ALU controller 962c, the instruction decoder 963, the interrupt controller 964, and the register controller 967. For example, the timing controller 965 includes an internal clock generation unit that generates an internal clock signal based on a reference clock signal, and supplies the internal clock signal to the various circuits described above.

[0459] 24, the register controller 967 selects the holding operation in the register 966 in accordance with an instruction from the ALU 962. That is, it selects whether the memory cells in the register 966 will hold data using flip-flops or using capacitors. If holding data using flip-flops is selected, a power supply potential is supplied to the memory cells in the register 966. If holding data using capacitors is selected, the data is rewritten to the capacitors, and the supply of power supply potential to the memory cells in the register 966 can be stopped.

[0460] The memory array 920 and the arithmetic unit 960 can be provided overlapping each other. Perspective views of a semiconductor device 970A are shown in Figures 25A and 25B. The semiconductor device 970A has a layer 930 on which memory arrays are provided above the arithmetic unit 960. The layer 930 is provided with memory arrays 920L1, 920L2, and 920L3. The arithmetic unit 960 and each memory array have overlapping regions. To make the configuration of the semiconductor device 970A easier to understand, the arithmetic unit 960 and the layer 930 are shown separately in Figure 25B.

[0461] By stacking the layer 930 having the memory array and the arithmetic unit 960, the connection distance between them can be shortened, thereby increasing the communication speed between them. In addition, the short connection distance reduces power consumption.

[0462] As a method for stacking the layer 930 having a memory array and the arithmetic device 960, a method (also referred to as monolithic stacking) in which the layer 930 having a memory array is stacked directly on the arithmetic device 960 may be used, or a method in which the arithmetic device 960 and the layer 930 are formed on different substrates, and the two substrates are bonded together and connected using a through-via or conductive film bonding technology (Cu-Cu bonding, etc.) may be used. The former method does not require consideration of misalignment during bonding, and therefore can not only reduce the chip size but also reduce manufacturing costs.

[0463] Here, the arithmetic unit 960 does not have a cache 969, and the memory arrays 920L1, 920L2, and 920L3 provided in the layer 930 can each be used as a cache. In this case, for example, the memory array 920L1 can be used as an L1 cache (also referred to as a level 1 cache), the memory array 920L2 can be used as an L2 cache (also referred to as a level 2 cache), and the memory array 920L3 can be used as an L3 cache (also referred to as a level 3 cache). Of the three memory arrays, the memory array 920L3 has the largest capacity and the lowest access frequency. Furthermore, the memory array 920L1 has the smallest capacity and the highest access frequency.

[0464] When the cache 969 provided in the arithmetic unit 960 is used as an L1 cache, each memory array provided in the layer 930 can be used as a lower-level cache or a main memory. The main memory has a larger capacity than the cache and is accessed less frequently.

[0465] 25B, a driving circuit 910L1, a driving circuit 910L2, and a driving circuit 910L3 are provided. The driving circuit 910L1 is connected to the memory array 920L1 via a connection electrode 940L1. Similarly, the driving circuit 910L2 is connected to the memory array 920L2 via a connection electrode 940L2, and the driving circuit 910L3 is connected to the memory array 920L3 via a connection electrode 940L3.

[0466] Although the number of memory arrays functioning as caches is three in this example, the number may be one or two, or four or more.

[0467] When the memory array 920L1 is used as a cache, the driver 910L1 may function as part of the cache interface 969i, or may be configured to be connected to the cache interface 969i. Similarly, the driver circuits 910L2 and 910L3 may also function as part of the cache interface 969i, or may be configured to be connected thereto.

[0468] Whether the memory array 920 is made to function as a cache or as a main memory is determined by a control circuit 912 included in each drive circuit 910. The control circuit 912 can cause some of the memory cells 950 included in the semiconductor device 900 to function as RAM based on a signal supplied from the arithmetic device 960.

[0469] The semiconductor device 900 can cause some of the memory cells 950 to function as a cache and the other memory cells to function as a main memory. That is, the semiconductor device 900 can function as both a cache and a main memory. The semiconductor device 900 according to one embodiment of the present invention can function as, for example, a universal memory.

[0470] Furthermore, a layer 930 having one memory array 920 may be provided over the arithmetic device 960. Figure 26A shows a perspective view of a semiconductor device 970B.

[0471] In the semiconductor device 970B, one memory array 920 can be divided into multiple areas, each of which can be used for a different function. Fig. 26A shows an example in which area L1 is used as an L1 cache, area L2 is used as an L2 cache, and area L3 is used as an L3 cache.

[0472] Furthermore, in the semiconductor device 970B, the capacity of each of the areas L1 to L3 can be changed depending on the situation. For example, if it is desired to increase the capacity of the L1 cache, this can be achieved by increasing the area of ​​the area L1. This configuration can improve the efficiency of calculation processing and increase the processing speed.

[0473] Also, multiple memory arrays may be stacked. Figure 26B shows a perspective view of a semiconductor device 970C.

[0474] The semiconductor device 970C includes a layer 930L1 having a memory array 920L1, a layer 930L2 having a memory array 920L2 on top of that, and a layer 930L3 having a memory array 920L3 on top of that. The memory array 920L1, which is physically closest to the arithmetic unit 960, can be used as a higher-level cache, and the memory array 920L3, which is farthest, can be used as a lower-level cache or main memory. This configuration allows the capacity of each memory array to be increased, thereby further improving processing power.

[0475] This embodiment mode can be combined with other embodiment modes as appropriate. In addition, in this specification, when a plurality of configuration examples are shown in one embodiment mode, the configuration examples can be combined as appropriate.

[0476] 27 , a memory device according to one embodiment of the present invention includes a transistor including an oxide as a semiconductor (hereinafter also referred to as an OS transistor) and a capacitor. Since the off-state current of an OS transistor is extremely small, the memory device including the OS transistor has excellent storage characteristics and can function as a nonvolatile memory.

[0477] In semiconductor devices such as computers, various memory devices are used depending on the application. Figure 27 shows a conceptual diagram explaining the hierarchy of memory devices used in semiconductor devices. In Figure 27, the conceptual diagram explaining the hierarchy of memory devices is shown as a triangle, with memory devices located higher in the triangle being required to have a faster operating speed, and memory devices located lower in the triangle being required to have a larger memory capacity and a higher recording density.

[0478] In FIG. 27 , from the top layer of the triangle, memories integrated as registers in the CPU, GPU, and NPU arithmetic processing units, cache memories (sometimes simply referred to as caches, and typically L1, L2, and L3 caches), main memories such as DRAM, and storage memories such as 3D NAND and hard disks (also called HDDs: hard disk drives) are shown.

[0479] The memory embedded as a register in a processing unit such as a CPU, GPU, or NPU is used for temporary storage of calculation results, and is therefore frequently accessed by the processing unit. Therefore, a high operating speed is required rather than a large storage capacity. Registers also have the function of storing setting information for the processing unit.

[0480] Cache memory has the function of duplicating and storing a portion of the data stored in DRAM. By duplicating frequently used data and storing it in cache memory, the speed of accessing the data can be increased. The storage capacity required for cache memory is smaller than that of DRAM, but it is required to have a faster operating speed than DRAM. In addition, data rewritten in cache memory is duplicated and supplied to DRAM.

[0481] The memory device of one embodiment of the present invention can be used as a DRAM.

[0482] 27 illustrates only up to the L3 cache, but the cache memory is not limited to this. For example, the storage device of one embodiment of the present invention can be used as a last level cache (LLC) or a final level cache (FLC), which are located at the lowest level of the cache.

[0483] The DRAM has a function of holding programs, data, etc. read from the 3D NAND.

[0484] 3D NAND has the function of storing data that requires long-term storage, various programs used in computing devices (e.g., artificial neural network models), etc. Therefore, 3D NAND requires large storage capacity and high recording density rather than fast operating speed.

[0485] Hard disks have large capacity and are non-volatile. Instead of hard disks, solid state drives (SSDs) and the like can be used.

[0486] The memory device of one embodiment of the present invention can be monolithically structured with peripheral circuits by using OS transistors. Furthermore, the use of OS transistors allows monolithic stacking with peripheral circuits. Therefore, this has advantages in terms of data access with peripheral circuits. Furthermore, the degree of integration can be increased by stacking with peripheral circuits. Furthermore, the use of OS transistors enables the memory device of one embodiment of the present invention to retain data for a long period of time. Therefore, when used as a DRAM, the frequency of refresh can be reduced.

[0487] Furthermore, the storage device of one embodiment of the present invention can reduce leakage current by using an OS transistor. Therefore, for example, data can be sufficiently stored even if the capacitance value of a capacitor is small. Therefore, for example, by using the storage device of one embodiment of the present invention as a DRAM, the operation speed of the DRAM, for example, the speed of rewriting, can be increased in some cases.

[0488] Furthermore, since the memory device of one embodiment of the present invention includes a capacitor including a ferroelectric material, data can be retained for a long time. Therefore, when the memory device is used as a DRAM, the frequency of refresh can be reduced. Furthermore, the reliability of the memory device can be improved.

[0489] The storage device of one embodiment of the present invention can be used for the Target2 region and the Target1 region shown in Figure 27. In particular, the storage device can be suitably used for the Target1 region.

[0490] 27, Target1 includes a boundary area (Target1_1) between the DRAM and 3D NAND, and a boundary area (Target1_2) between the DRAM and cache (L1, L2, L3). Examples of Target1_2 include the LLC and FLC described above.

[0491] By replacing the storage device of one embodiment of the present invention with a DRAM, power consumption can be reduced. With this configuration, power consumption can be reduced to half or less, preferably one-tenth or less, more preferably one-hundredth or less, and further preferably one-thousandth or less, compared to a configuration using a DRAM. Therefore, the storage device of one embodiment of the present invention can be suitably used for Target 1.

[0492] Furthermore, the storage device of one embodiment of the present invention can retain data for a long time and has advantages in terms of data access. Therefore, the storage device of one embodiment of the present invention can be suitably used for Target1_1, which is a region of Target1 that is rewritten relatively infrequently. By applying the storage device of one embodiment of the present invention to Target1_1, the reliability of the storage device can be improved. Furthermore, the integration degree of the storage device can be increased. Furthermore, the power consumption of the storage device can be reduced.

[0493] Furthermore, the storage device of one embodiment of the present invention has high operating speed and is advantageous in terms of data access, and therefore can be suitably used for Target1_2, which is rewritten more frequently than Target1. By applying the storage device of one embodiment of the present invention to Target1_2, the calculation efficiency of the storage device can be improved and power consumption can be reduced.

[0494] Another means for reducing power consumption is a configuration in which a storage device such as a DRAM or an FeRAM (including the semiconductor device of one embodiment of the present invention) is stacked on an arithmetic processing device such as a CPU, a GPU, or an NPU. A configuration in which an arithmetic processing device and a storage device are stacked is called a monolithic stack. By configuring the arithmetic processing device and the storage device as a monolithic stack, for example, the power consumption required for data access between the arithmetic processing device and the storage device can be significantly reduced. Therefore, by deploying information processing devices including supercomputers (also called high performance computers (HPCs)), computers, servers, etc. to which such a configuration is applied throughout the world, global warming can be suppressed.

[0495] As described above, the memory device including an oxide semiconductor according to one embodiment of the present invention can be applied to a wide range of memories, from memories integrated as registers in arithmetic processing units such as CPUs, GPUs, and NPUs to memories located in the boundary region between DRAMs and 3D NANDs.

[0496] This embodiment mode can be combined with other embodiment modes as appropriate. In addition, in this specification, when a plurality of configuration examples are shown in one embodiment mode, the configuration examples can be combined as appropriate.

[0497] Embodiment 4 In this embodiment, application examples of a semiconductor device of one embodiment of the present invention will be described with reference to FIGS. 28A to 30F.

[0498] The semiconductor device of one embodiment of the present invention can be used in, for example, electronic components, mainframes, space equipment, data centers (also referred to as DCs), and various electronic devices. By using the semiconductor device of one embodiment of the present invention, low power consumption and high performance can be achieved for the electronic components, mainframes, space equipment, data centers, and various electronic devices.

[0499] Examples of electronic devices include electronic devices with relatively large screens such as television sets, desktop or notebook computers, computer monitors, digital signage, large game machines such as pachinko machines, as well as digital cameras, digital video cameras, digital photo frames, mobile phones, portable game machines, personal digital assistants, and sound playback devices.

[0500] The electronic device of this embodiment may have a sensor (including the function of detecting, detecting, or measuring force, displacement, position, velocity, acceleration, angular velocity, rotation speed, distance, light, liquid, magnetism, temperature, chemical substance, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, gradient, vibration, odor, or infrared rays).

[0501] The electronic device of the present embodiment can have various functions, such as a function to display various information (still images, videos, text images, etc.) on a display unit, a touch panel function, a function to display a calendar, date, time, etc., a function to execute various software (programs), a wireless communication function, and a function to read out programs or data recorded on a recording medium.

[0502] [Electronic Component] FIG. 28A shows a perspective view of a substrate (mounting substrate 989) on which an electronic component 980 is mounted. The electronic component 980 shown in FIG. 28A has a semiconductor device 981 inside a mold 984. FIG. 28A omits some details in order to show the interior of the electronic component 980. The electronic component 980 has lands 985 on the outside of the mold 984. The lands 985 are electrically connected to electrode pads 986, and the electrode pads 986 are electrically connected to the semiconductor device 981 via wires 987. The electronic component 980 is mounted on, for example, a printed circuit board 988. A plurality of such electronic components are combined and electrically connected on the printed circuit board 988 to complete the mounting substrate 989.

[0503] The semiconductor device 981 also includes a drive circuit layer 982 and a memory layer 983. The memory layer 983 has a configuration in which multiple memory cell arrays are stacked. The stacked configuration of the drive circuit layer 982 and the memory layer 983 can be a monolithic stacked configuration. In a monolithic stacked configuration, the layers can be connected without using through-electrode technology such as TSV (Through Silicon Via) or bonding technology such as Cu-Cu direct bonding. By monolithically stacking the drive circuit layer 982 and the memory layer 983, for example, a so-called on-chip memory configuration can be achieved in which the memory is formed directly on the processor. The on-chip memory configuration enables the operation of the interface between the processor and the memory to be faster.

[0504] Furthermore, by configuring an on-chip memory, the size of the connection wiring can be reduced compared to technologies that use through electrodes such as TSVs, and the number of connection pins can be increased. Increasing the number of connection pins enables parallel operation, which makes it possible to improve the memory bandwidth (also called memory bandwidth).

[0505] Furthermore, it is preferable that the memory cell arrays included in the memory layer 983 are formed using OS transistors and the memory cell arrays are monolithically stacked. By forming the memory cell arrays in a monolithic stacked configuration, it is possible to improve one or both of the memory bandwidth and the memory access latency. Note that the bandwidth is the amount of data transferred per unit time, and the access latency is the time from access to the start of data exchange. Note that when Si transistors are used for the memory layer 983, it is more difficult to form a monolithic stacked configuration than when OS transistors are used. Therefore, it can be said that OS transistors have a superior structure to Si transistors in a monolithic stacked configuration.

[0506] The semiconductor device 981 may also be referred to as a die. In this specification, a die refers to a chip piece obtained during the semiconductor chip manufacturing process by forming a circuit pattern on, for example, a disk-shaped substrate (also called a wafer) and dicing it into cubes. Semiconductor materials that can be used for the die include, for example, silicon (Si), silicon carbide (SiC), or gallium nitride (GaN). For example, a die obtained from a silicon substrate (also called a silicon wafer) may be called a silicon die.

[0507] 28B shows a perspective view of an electronic component 990. The electronic component 990 is an example of a SiP (System in Package) or an MCM (Multi-Chip Module). The electronic component 990 has an interposer 991 provided on a package substrate 992 (printed circuit board), and a semiconductor device 994 and a plurality of semiconductor devices 981 provided on the interposer 991.

[0508] The electronic component 990 shows an example in which the semiconductor device 981 is used as a high bandwidth memory (HBM). The semiconductor device 994 can be used in an integrated circuit such as a CPU, a GPU, or an FPGA (Field Programmable Gate Array).

[0509] For example, a ceramic substrate, a plastic substrate, or a glass epoxy substrate can be used as the package substrate 992. For example, a silicon interposer or a resin interposer can be used as the interposer 991.

[0510] The interposer 991 has multiple wirings and functions to connect multiple integrated circuits with different terminal pitches. The multiple wirings are provided in a single layer or multiple layers. The interposer 991 also functions to connect the integrated circuits provided on the interposer 991 to electrodes provided on the package substrate 992. For these reasons, the interposer is sometimes called a "rewiring substrate" or "intermediate substrate." In some cases, through electrodes are provided in the interposer 991, and the integrated circuits and the package substrate 992 are connected using the through electrodes. In addition, in a silicon interposer, TSVs can also be used as through electrodes.

[0511] In an HBM, many wirings must be connected to achieve a wide memory bandwidth. Therefore, the interposer on which the HBM is mounted must have fine and high-density wiring. Therefore, it is preferable to use a silicon interposer for the interposer on which the HBM is mounted.

[0512] Furthermore, in SiPs, MCMs, and the like that use silicon interposers, a decrease in reliability due to differences in the coefficient of expansion between the integrated circuit and the interposer is unlikely to occur. Furthermore, because the silicon interposer has a highly flat surface, poor connection between the integrated circuit mounted on the silicon interposer and the silicon interposer is unlikely to occur. In particular, it is preferable to use silicon interposers in 2.5D packages (2.5-dimensional packaging) in which multiple integrated circuits are arranged horizontally on an interposer.

[0513] On the other hand, when connecting multiple integrated circuits with different terminal pitches using a silicon interposer, TSVs, or the like, a space is required, such as the width of the terminal pitch. Therefore, when attempting to reduce the size of the electronic component 990, the width of the terminal pitch becomes an issue, and it may be difficult to provide the many wirings necessary to achieve a wide memory bandwidth. Therefore, as described above, a monolithic stacked structure using OS transistors is preferable. A composite structure may be formed by combining a memory cell array stacked using TSVs with a monolithic stacked memory cell array.

[0514] A heat sink (heat dissipation plate) may be provided over the electronic component 990. When a heat sink is provided, it is preferable to align the height of an integrated circuit provided on the interposer 991. For example, in the electronic component 990 shown in this embodiment, it is preferable to align the height of the semiconductor device 981 and the height of the semiconductor device 994.

[0515] Electrodes 993 may be provided on the bottom of the package substrate 992 in order to mount the electronic component 990 on another substrate. FIG. 28B shows an example in which the electrodes 993 are formed of solder balls. By providing solder balls in a matrix on the bottom of the package substrate 992, BGA (Ball Grid Array) mounting can be achieved. The electrodes 993 may also be formed of conductive pins. By providing conductive pins in a matrix on the bottom of the package substrate 992, PGA (Pin Grid Array) mounting can be achieved.

[0516] The electronic component 990 can be mounted on other substrates using various mounting methods, not limited to BGA and PGA, such as a staggered pin grid array (SPGA), a land grid array (LGA), a quad flat package (QFP), a quad flat J-leaded package (QFJ), and a quad flat non-leaded package (QFN).

[0517] 29A shows a perspective view of a mainframe computer 5600. The mainframe computer 5600 shown in Fig. 29A has a rack 5610 housing a plurality of rack-mounted computers 5620. The mainframe computer 5600 may also be called a supercomputer.

[0518] The computer 5620 can have the configuration shown in the perspective view of Fig. 29B, for example. In Fig. 29B, the computer 5620 has a motherboard 5630, which has a plurality of slots 5631 and a plurality of connection terminals. A PC card 5621 is inserted into the slot 5631. In addition, the PC card 5621 has connection terminals 5623, 5624, and 5625, which are each connected to the motherboard 5630.

[0519] PC card 5621 shown in Figure 29C is an example of a processing board equipped with a CPU, a GPU, a storage device, etc. PC card 5621 has board 5622. Board 5622 also has connection terminals 5623, 5624, 5625, semiconductor devices 5626, 5627, 5628, and 5629. Note that Figure 29C illustrates semiconductor devices other than semiconductor devices 5626, 5627, and 5628, but for these semiconductor devices, the following descriptions of semiconductor devices 5626, 5627, and 5628 can be referenced.

[0520] The connection terminal 5629 has a shape that allows it to be inserted into a slot 5631 of the motherboard 5630, and the connection terminal 5629 functions as an interface for connecting the PC card 5621 and the motherboard 5630. An example of the standard for the connection terminal 5629 is PCIe.

[0521] The connection terminals 5623, 5624, and 5625 can be, for example, interfaces for supplying power to the PC card 5621, inputting signals, etc. Furthermore, they can be, for example, interfaces for outputting signals calculated by the PC card 5621. Examples of the standards for the connection terminals 5623, 5624, and 5625 include USB (Universal Serial Bus), SATA (Serial ATA), and SCSI (Small Computer System Interface). Furthermore, when a video signal is output from the connection terminals 5623, 5624, and 5625, examples of the standards for each include HDMI (registered trademark).

[0522] The semiconductor device 5626 has a terminal (not shown) for inputting and outputting signals, and the semiconductor device 5626 can be connected to the board 5622 by inserting the terminal into a socket (not shown) provided on the board 5622.

[0523] The semiconductor device 5627 has a plurality of terminals, and the semiconductor device 5627 can be connected to the board 5622 by, for example, reflow soldering the terminals to wiring provided on the board 5622. Examples of the semiconductor device 5627 include an FPGA, a GPU, and a CPU. For example, the electronic component 990 can be used as the semiconductor device 5627.

[0524] The semiconductor device 5628 has a plurality of terminals, and the semiconductor device 5628 can be connected to the board 5622 by, for example, reflow soldering the terminals to wiring provided on the board 5622. Examples of the semiconductor device 5628 include a memory device. For example, the electronic component 990 can be used as the semiconductor device 5628.

[0525] The mainframe computer 5600 can also function as a parallel computer. By using the mainframe computer 5600 as a parallel computer, it is possible to perform large-scale calculations required for, for example, learning and inference in artificial intelligence.

[0526] [Space Equipment] The semiconductor device of one embodiment of the present invention can be suitably used in space equipment.

[0527] A semiconductor device according to one embodiment of the present invention includes an OS transistor. Compared to a Si transistor, an OS transistor exhibits smaller variations in electrical characteristics due to radiation exposure. That is, the OS transistor has high radiation resistance and is therefore highly reliable and suitable for use in environments where radiation may be incident. For example, an OS transistor can be suitably used in outer space. Specifically, an OS transistor can be used as a transistor for a semiconductor device provided in a space shuttle, an artificial satellite, or a space probe. Examples of radiation include X-rays and neutrons. Note that outer space refers to an altitude of 100 km or higher, and the outer space described in this specification can include one or more of the thermosphere, the mesosphere, and the stratosphere.

[0528] Fig. 29D shows an artificial satellite 6800 as an example of space equipment. The artificial satellite 6800 has a body 6801, a solar panel 6802, an antenna 6803, a secondary battery 6805, and a control device 6807. Note that Fig. 29D illustrates a planet 6804 in space.

[0529] 29D , a battery management system (also referred to as a BMS) or a battery control circuit may be provided for the secondary battery 6805. The use of an OS transistor in the battery management system or the battery control circuit is preferable because it has low power consumption and high reliability even in space.

[0530] Furthermore, outer space is an environment with radiation levels 100 times higher than on Earth. Examples of radiation include electromagnetic waves (electromagnetic radiation) such as X-rays and gamma rays, and particle radiation such as alpha rays, beta rays, neutron rays, proton rays, heavy ion rays, and meson rays.

[0531] When sunlight is irradiated onto the solar panel 6802, the power required for the operation of the satellite 6800 is generated. However, for example, in a situation where sunlight is not irradiated onto the solar panel or where the amount of sunlight irradiating the solar panel is small, the generated power is small. Therefore, there is a possibility that the power required for the operation of the satellite 6800 will not be generated. In order to operate the satellite 6800 even in a situation where the generated power is small, it is preferable to provide a secondary battery 6805 in the satellite 6800. Note that the solar panel may be called a solar cell module.

[0532] The satellite 6800 can generate a signal. The signal is transmitted via an antenna 6803, and can be received by, for example, a receiver installed on the ground or another satellite. By receiving the signal transmitted by the satellite 6800, the position of the receiver that received the signal can be determined. As described above, the satellite 6800 can constitute a satellite positioning system.

[0533] The control device 6807 has a function of controlling the artificial satellite 6800. The control device 6807 is configured using, for example, one or more selected from a CPU, a GPU, and a storage device. Note that the control device 6807 is preferably a semiconductor device including an OS transistor which is one embodiment of the present invention.

[0534] The artificial satellite 6800 can also be configured to include a sensor. For example, by including a visible light sensor, the artificial satellite 6800 can have the function of detecting sunlight reflected from an object on the ground. Or, by including a thermal infrared sensor, the artificial satellite 6800 can have the function of detecting thermal infrared rays emitted from the earth's surface. As described above, the artificial satellite 6800 can function as, for example, an earth observation satellite.

[0535] Although an artificial satellite is described as an example of space equipment in this embodiment, the present invention is not limited thereto. For example, the semiconductor device of one embodiment of the present invention can be suitably used in space equipment such as a spaceship, a space capsule, or a space probe.

[0536] As described above, OS transistors have excellent advantages over Si transistors, such as the ability to achieve a wide memory bandwidth and high radiation resistance.

[0537] [Data Center] The semiconductor device of one embodiment of the present invention can be suitably used in a storage system applied to, for example, a data center. The data center is required to perform long-term management of data, such as ensuring data immutability. Managing long-term data requires the construction of a large-scale building, such as installing storage and servers for storing a huge amount of data, ensuring a stable power supply for data retention, or ensuring cooling equipment required for data retention.

[0538] By using the semiconductor device of one embodiment of the present invention in a storage system applied to a data center, it is possible to reduce the power required to store data and the size of the semiconductor device that stores data. Therefore, it is possible to reduce the size of the storage system, the size of the power supply for storing data, the scale of cooling equipment, etc. Therefore, it is possible to reduce the space required for the data center.

[0539] Furthermore, the semiconductor device of one embodiment of the present invention has low power consumption, which allows heat generation from the circuit to be reduced. Therefore, adverse effects of the heat generation on the circuit itself, peripheral circuits, and modules can be reduced. Furthermore, by using the semiconductor device of one embodiment of the present invention, a data center that operates stably even in a high-temperature environment can be realized. Therefore, the reliability of the data center can be improved.

[0540] Fig. 29E shows a storage system applicable to a data center. The storage system 7010 shown in Fig. 29E has multiple servers 7001sb as hosts 7001 (illustrated as Host Computers). It also has multiple storage devices 7003md as storage 7003 (illustrated as Storage). The host 7001 and storage 7003 are shown connected via a storage area network 7004 (illustrated as SAN: Storage Area Network) and a storage control circuit 7002 (illustrated as Storage Controller).

[0541] The host 7001 corresponds to a computer that accesses data stored in the storage 7003. The hosts 7001 may be connected to each other via a network.

[0542] Although the storage 7003 uses flash memory to reduce the data access speed, i.e., the time required to store and output data, this time is significantly longer than the time required for DRAM, which can be used as cache memory within the storage. In order to solve the problem of the long access speed of the storage 7003, a storage system typically provides cache memory within the storage to reduce the time required to store and output data.

[0543] The cache memory described above is used in the storage control circuit 7002 and the storage 7003. Data exchanged between the host 7001 and the storage 7003 is stored in the cache memory in the storage control circuit 7002 and the storage 7003, and then output to the host 7001 or the storage 7003.

[0544] By using OS transistors as transistors for storing data in the cache memory and holding a potential corresponding to the data, the frequency of refresh operations can be reduced, and power consumption can be reduced.

[0545] 30A to 30F , examples of wearable devices that can be worn on the head will be described. These wearable devices have at least one of the following functions: a function to display AR content, a function to display VR content, a function to display Substitutional Reality (SR) content, and a function to display MR content. By having an electronic device with the function to display at least one of AR, VR, SR, and MR content, it is possible to enhance the user's sense of immersion.

[0546] The electronic device 800 shown in Figure 30A has a pair of display panels 810, a pair of housings 811, a communication unit (not shown), a pair of mounting units 813, a control unit 814, an imaging unit (not shown), a pair of optical members 816, a frame 817, and a pair of nose pads 818.

[0547] The semiconductor device of one embodiment of the present invention can be applied to the control unit 814. This makes it possible to reduce power consumption of the electronic device.

[0548] The electronic device 800 can project an image displayed on the display panel 810 onto a display area 819 of the optical member 816. Because the optical member 816 is translucent, the user can see the image displayed in the display area superimposed on a transmitted image visually recognized through the optical member 816. Therefore, the electronic device 800 is an electronic device capable of AR display.

[0549] The electronic device 800 may be provided with a camera capable of capturing an image in front of it as an imaging unit. The electronic device 800 may also be provided with an acceleration sensor such as a gyro sensor, thereby detecting the orientation of the user's head and displaying an image corresponding to that orientation in the display area 819.

[0550] The communication unit has a wireless communication device, and can supply a video signal, etc. Instead of or in addition to the wireless communication device, a connector to which a cable through which a video signal and a power supply potential are supplied may be provided.

[0551] The electronic device 800 is also provided with a battery, which can be charged wirelessly and / or wired.

[0552] The housing 811 may be provided with a touch sensor module. The touch sensor module has a function of detecting a touch on the outer surface of the housing 811. The touch sensor module can detect a tap operation, a slide operation, or the like by the user and perform various processes. For example, a tap operation can perform a process such as pausing or resuming a video, and a slide operation can perform a process such as fast-forwarding or fast-rewinding. Furthermore, providing a touch sensor module on each of the two housings 811 can widen the range of operations.

[0553] The electronic device 830A shown in Figure 30B and the electronic device 830B shown in Figure 30C each have a pair of display units 840, a housing 841, a communication unit 842, a pair of mounting units 843, a control unit 844, a pair of imaging units 845, and a pair of lenses 846.

[0554] The semiconductor device of one embodiment of the present invention can be applied to the control unit 844. This makes it possible to reduce power consumption of the electronic device.

[0555] The display unit 840 is provided inside the housing 841 at a position that can be viewed through a lens 846. In addition, by displaying different images on the pair of display units 840, it is possible to perform three-dimensional display using parallax.

[0556] The electronic device 830A and the electronic device 830B can be said to be electronic devices for VR. A user wearing the electronic device 830A or the electronic device 830B can view an image displayed on the display unit 840 through the lens 846.

[0557] It is preferable that the electronic device 830A and the electronic device 830B each have a mechanism for adjusting the left-right positions of the lens 846 and the display unit 840 so that the lens 846 and the display unit 840 are optimally positioned according to the position of the user's eyes. It is also preferable that the electronic device 830A and the electronic device 830B each have a mechanism for adjusting the focus by changing the distance between the lens 846 and the display unit 840.

[0558] The mounting unit 843 allows the user to mount the electronic device 830A or the electronic device 830B on the head. Note that, in Fig. 30B and other figures, the mounting unit 843 is shaped like the temples of glasses, but is not limited to this. The mounting unit 843 may be shaped like a helmet or a band, for example, as long as it can be worn by the user.

[0559] The imaging unit 845 has a function of acquiring external information. Data acquired by the imaging unit 845 can be output to the display unit 840. An image sensor can be used for the imaging unit 845. Furthermore, multiple cameras may be provided to support multiple angles of view, such as telephoto and wide angle.

[0560] Note that, although an example in which the imaging unit 845 is provided is shown here, the imaging unit 845 does not have to be provided if a distance measuring sensor (hereinafter also referred to as a detection unit) capable of measuring the distance to an object is provided. That is, the imaging unit 845 is one aspect of the detection unit. As the detection unit, for example, an image sensor or a range image sensor such as a LIDAR (Light Detection and Ranging) can be used. By using an image obtained by the camera and an image obtained by the range image sensor, more information can be obtained, enabling more accurate gesture operations.

[0561] The electronic device 830A may have a vibration mechanism that functions as a bone conduction earphone. For example, a configuration having such a vibration mechanism can be applied to one or more of the display unit 840, the housing 841, and the wearing unit 843. This allows a user to enjoy video and audio simply by wearing the electronic device 830A, without the need for separate audio equipment such as headphones, earphones, or speakers.

[0562] The electronic device 830A and the electronic device 830B may each have an input terminal to which a cable can be connected for supplying a video signal from a video output device or the like and power for charging a battery provided in the electronic device.

[0563] The electronic device of one embodiment of the present invention may have a function of wireless communication with an earphone 820. The ea...

Claims

a transistor and a first insulating layer; the transistor includes an oxide semiconductor layer, a second insulating layer, a first conductive layer, a second conductive layer, and a third conductive layer; the oxide semiconductor layer has a source region, a drain region, and a channel formation region located between the source region and the drain region; the first insulating layer is located on the oxide semiconductor layer; the first insulating layer has a first opening overlapping the channel formation region, a second opening overlapping the source region, and a third opening overlapping the drain region; the second insulating layer is located within the first opening; the second insulating layer is in contact with the source region, the drain region, and a lower surface of the first insulating layer; the first conductive layer is located on the second insulating layer within the first opening; the second conductive layer is located in the second opening; the second conductive layer contacts the source region; the third conductive layer is located in the third opening; the third conductive layer is in contact with the drain region; The semiconductor device has a higher concentration of the impurity element in the source region and the drain region than in the channel formation region. 　 a transistor and a first insulating layer; the transistor includes an oxide semiconductor layer, a second insulating layer, a first conductive layer, a second conductive layer, and a third conductive layer; the oxide semiconductor layer has a source region, a drain region, and a recessed portion located between the source region and the drain region; the oxide semiconductor layer has a channel formation region below the recess; the first insulating layer is located on the oxide semiconductor layer; the first insulating layer has a first opening having a region overlapping with the channel formation region, a second opening having a region overlapping with the source region, and a third opening having a region overlapping with the drain region; the second insulating layer is located within the first opening and within the recess; the second insulating layer is in contact with the source region, the drain region, and a lower surface of the first insulating layer; the first conductive layer is located on the second insulating layer within the first opening; the second conductive layer is located in the second opening; the second conductive layer contacts the source region; the third conductive layer is located in the third opening; the third conductive layer is in contact with the drain region; a height from a reference plane of a lower surface of the second insulating layer in a region overlapping with the first insulating layer is higher than a height from the reference plane of a lower surface of the second insulating layer in the recess; The semiconductor device has a higher concentration of the impurity element in the source region and the drain region than in the channel formation region. 　 In claim 2, the oxide semiconductor layer has a first region and a second region, the first region contacts a side surface of the source region and a lower surface of the second insulating layer; the second region contacts a side surface of the drain region and a lower surface of the second insulating layer; the first region and the second region overlap the first insulating layer; a concentration of the impurity element in the first region is lower than a concentration of the impurity element in the source region and higher than a concentration of the impurity element in the channel formation region; The semiconductor device has a concentration of the impurity element in the second region that is lower than a concentration of the impurity element in the drain region and higher than a concentration of the impurity element in the channel formation region. 　 In any one of claims 1 to 3, The impurity element is a metal element. 　 In any one of claims 1 to 3, the oxide semiconductor layer contains indium, The impurity element is at least one of titanium, tin, and antimony. 　 a first step of forming an oxide semiconductor layer and a first impurity layer located on the oxide semiconductor layer and having a thickness smaller than that of the oxide semiconductor layer; a second step of forming a first insulating layer on the first impurity layer; a third step of processing the first insulating layer and the first impurity layer to form a first opening in the first insulating layer, the first opening having a region overlapping with the oxide semiconductor layer, and forming a second impurity layer and a third impurity layer; a fourth step of forming a second insulating layer so as to have a region located within the first opening, a region in contact with a side surface of the second impurity layer, and a region in contact with a side surface of the third impurity layer; a fifth step of forming a first conductive layer on the second insulating layer to have a region located within the first opening; a sixth step of forming a first region containing an element contained in the second impurity layer in a region of the oxide semiconductor layer overlapping with the second impurity layer and forming a second region containing an element contained in the third impurity layer in a region of the oxide semiconductor layer overlapping with the third impurity layer by performing heat treatment; a seventh step of forming a second opening in the first insulating layer, the second opening reaching the first region, and a third opening reaching the second region; and an eighth step of forming a second conductive layer in the second opening so as to be in contact with the first region, and forming a third conductive layer in the third opening so as to be in contact with the second region. 　 In claim 6, In the third step, the second impurity layer and the third impurity layer are formed so that a side surface of the first insulating layer at the first opening has a region that protrudes relative to the second impurity layer and a region that protrudes relative to the third impurity layer. 　 In claim 6 or claim 7, The method for manufacturing a semiconductor device, wherein the element is a metal element. 　 In claim 6 or claim 7, in the first step, the oxide semiconductor layer and the first impurity layer are formed so as to each contain indium; The element is at least one of titanium, tin, and antimony.

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