Semiconductor device

Abstract

The present invention provides a semiconductor device in which a higher level of integration can be achieved. This semiconductor device includes first to third conductive layers, a semiconductor layer, first to third insulating layers, and a capacitive element. The first insulating layer is located above the first conductive layer. The semiconductor layer has a first portion in contact with the side surface of the first insulating layer, and a second portion in contact with the upper surface thereof. The second conductive layer is located above the first insulating layer and is in contact with the first portion. The second insulating layer, the third conductive layer, and the third insulating layer cover the first portion and the second portion. The capacitive element is located below the second portion and has a part of the first conductive layer, a fourth conductive layer, and a fourth insulating layer therebetween. The first conductive layer has a first conductive film, and a second conductive film on the first conductive film. The semiconductor layer contains indium oxide and is in contact with the second conductive film. The second conductive film contains a metal oxide, and the first conductive film contains a metal.

Description

Semiconductor Devices

[0001] 1. Field of the Invention One embodiment of the present invention relates to a semiconductor device, a transistor, or a memory device.

[0002] Note that one embodiment of the present invention is not limited to the above technical field. Examples of the technical field of one embodiment of the present invention disclosed in this specification and the like include semiconductor devices, display devices, light-emitting devices, power storage devices, memory devices, electronic devices, lighting devices, input devices, input / output devices, driving methods thereof, and manufacturing methods thereof. A semiconductor device refers to any device that can function by utilizing semiconductor characteristics.

[0003] In recent years, the development of semiconductor devices has progressed, and CPUs, memories, and other large-scale integrated circuits (LSIs) are mainly used in semiconductor devices. A CPU is an assembly of semiconductor elements that have semiconductor integrated circuits (at least transistors and memories) formed into chips by processing a semiconductor wafer and on which electrodes serving as connection terminals are formed.

[0004] 2. Description of the Related Art A CPU, a memory, or other LSI semiconductor circuit (IC chip) is mounted on a circuit board, such as a printed wiring board, and is used as one of the components of various electronic devices.

[0005] Furthermore, a technique for constructing a transistor using a semiconductor thin film formed on a substrate having an insulating surface has attracted attention. Such transistors are widely applied to electronic devices such as integrated circuits and image display devices (also simply referred to as display devices). While silicon-based semiconductor materials are widely known as semiconductor thin films applicable to transistors, oxide semiconductors have also attracted attention as other materials.

[0006] Furthermore, it is known that a transistor including an oxide semiconductor has an extremely small leakage current in a non-conducting state. For example, Patent Document 1 discloses a low-power consumption CPU that utilizes the property of a small leakage current. Furthermore, Patent Document 2 discloses a memory device that can retain stored data for a long period of time.

[0007] In recent years, along with the trend toward smaller and lighter electronic devices, there has been an increasing demand for higher density integrated circuits. There is also a demand for improved productivity of semiconductor devices including integrated circuits. For example, Patent Document 3 discloses a technique for increasing the density of integrated circuits by stacking a first transistor using an oxide semiconductor film and a second transistor using an oxide semiconductor film to provide multiple memory cells in a superimposed manner. Patent Document 4 also discloses a vertical transistor in which a side surface of an oxide semiconductor is covered with a gate electrode via a gate insulator.

[0008] Also, Patent Document 5 discloses a semiconductor memory device having a channel pattern having a vertical channel portion on a bit line, and a word line provided on the channel pattern so as to cross the bit line.

[0009] JP 2012-257187 A JP 2011-151383 A WO 2021 / 053473 JP 2013-211537 A U.S. Patent Application Publication No. 2023 / 0055499

[0010] Takashi Koida, "High Mobility Transparent Conductive Film," National Institute of Advanced Industrial Science and Technology, AIST Photovoltaic Power Generation Research Results Report 2019, Internet <URL: https: / / unit.aist.go.jp / rpd-envene / PV / ja / results / 2019 / oral / T13.pdf>

[0011] An object of one embodiment of the present invention is to provide a semiconductor device that can be easily miniaturized. Another object is to provide a semiconductor device that enables high integration. Another object is to provide a semiconductor device in which a wiring load is reduced. Another object is to provide a highly reliable semiconductor device. Another object is to provide a semiconductor device that exhibits favorable electrical characteristics. Another object is to provide a semiconductor device with high operating speed.

[0012] An object of one embodiment of the present invention is to provide a semiconductor device, a memory device, or an electronic device having a novel structure. An object of one embodiment of the present invention is to alleviate at least one of the problems of the prior art.

[0013] Note that the description of these problems does not preclude the existence of other problems. Note that one embodiment of the present invention does not necessarily solve all of these problems. Note that problems other than these can be extracted from the description of the specification, drawings, claims, etc.

[0014] One embodiment of the present invention is a semiconductor device including a first conductive layer, a second conductive layer, a third conductive layer, a fourth conductive layer, a semiconductor layer, a first insulating layer, a second insulating layer, a third insulating layer, and a fourth insulating layer. The first insulating layer is provided above the first conductive layer and has a side surface. The semiconductor layer has a first portion in contact with the side surface of the first insulating layer and a second portion in contact with an upper surface of the first conductive layer. The second conductive layer has a portion located above the first insulating layer and in contact with the first portion. The second insulating layer covers the first portion and the second portion. The third conductive layer covers the first portion and the second portion via the second insulating layer. The third insulating layer covers the first portion and the second portion via the second insulating layer and the third conductive layer. The fourth conductive layer is located below the first conductive layer. The fourth insulating layer has a portion located between the first conductive layer and the fourth conductive layer. The first conductive layer includes a first conductive film and a second conductive film over the first conductive film. The semiconductor layer includes indium oxide and is in contact with the second conductive film. The second conductive film includes a metal oxide, and the first conductive film includes a metal.

[0015] Another embodiment of the present invention is a semiconductor device including a pair of first conductive layers, a second conductive layer, a pair of third conductive layers, a pair of fourth conductive layers, a pair of semiconductor layers, a first insulating layer, a pair of second insulating layers, a pair of third insulating layers, and a fourth insulating layer. The pair of third conductive layers, the pair of semiconductor layers, the pair of second insulating layers, and the pair of third insulating layers are provided symmetrically with the first insulating layer interposed therebetween. The first insulating layer is provided above the first conductive layer and has a pair of side surfaces. Each of the pair of semiconductor layers has a first portion in contact with the side surface of the first insulating layer and a second portion in contact with a top surface of the first conductive layer. The second conductive layer has a portion located above the first insulating layer and in contact with each of the first portions of the pair of semiconductor layers. The pair of second insulating layers each cover the first portion and the second portion. The pair of third conductive layers respectively cover the first portion and the second portion via the second insulating layer. The pair of third insulating layers respectively cover the first portion and the second portion via the second insulating layer and the third insulating layer. The pair of fourth conductive layers are each located below the first conductive layer. The fourth insulating layer has a portion located between the first conductive layer and the fourth conductive layer. The pair of first conductive layers each have a first conductive film and a second conductive film on the first conductive film. The pair of semiconductor layers each contain indium oxide and are in contact with the second conductive film. The second conductive film contains a metal oxide, and the first conductive film contains a metal.

[0016] In any of the above, the fourth conductive layer preferably has a recess. In this case, the fourth insulating layer preferably has a portion provided along the recess. Furthermore, the first conductive layer preferably has a portion located within the recess via the fourth insulating layer and contacts the side and upper surfaces of the fourth insulating layer within the recess.

[0017] In any of the above, each of the pair of semiconductor layers preferably has a single crystal structure or a polycrystalline structure.

[0018] In any of the above, the metal oxide preferably contains indium.

[0019] In any of the above, the second conductive film preferably has a recess, and in this case, the semiconductor layer preferably contacts the side and upper surfaces of the recess in the second conductive film.

[0020] In any of the above, it is preferable that the semiconductor device further includes a fifth insulating layer, and in this case, the fifth insulating layer preferably has a portion in contact with the upper surface of the third conductive layer and the upper surface of the third insulating layer and located between the second conductive layer and the third conductive layer.

[0021] In any of the above, it is preferable that a sixth insulating layer be further included. In this case, it is preferable that the fourth conductive layer be located on the sixth insulating layer. Furthermore, it is preferable that the sixth insulating layer contains silicon nitride or silicon oxynitride.

[0022] In any of the above, it is preferable that the semiconductor device further includes a seventh insulating layer. In this case, the seventh insulating layer is preferably located above the second conductive layer. Furthermore, it is preferable that the seventh insulating layer contains silicon nitride or silicon nitride oxide.

[0023] In any of the above, the third insulating layer preferably contains hafnium oxide, aluminum oxide, or an oxide containing hafnium and silicon.

[0024] In the above, the fifth insulating layer preferably contains hafnium oxide, aluminum oxide, or an oxide containing hafnium and silicon.

[0025] In any of the above, it is preferable that a transistor be provided below the fourth conductive layer. In this case, it is preferable that the transistor contains silicon in a semiconductor in which a channel is formed, and that one of a source and a drain of the transistor be connected to the second conductive layer.

[0026] Alternatively, in any of the above, it is preferable that a transistor be provided above the second conductive layer. In this case, it is preferable that the transistor contains silicon in a semiconductor in which a channel is formed, and that one of a source and a drain of the transistor be connected to the second conductive layer.

[0027] According to one embodiment of the present invention, a semiconductor device that can be easily miniaturized, a semiconductor device that enables high integration, a semiconductor device in which the load on wiring is reduced, a highly reliable semiconductor device, a semiconductor device that exhibits favorable electrical characteristics, or a semiconductor device that operates at a high speed can be provided.

[0028] According to one aspect of the present invention, it is possible to provide a semiconductor device, a memory device, or an electronic device having a novel configuration. According to one aspect of the present invention, it is possible to at least alleviate at least one of the problems of the prior art.

[0029] Note that the description of these effects does not preclude the existence of other effects. Note that one embodiment of the present invention does not necessarily have all of these effects. Note that effects other than these can be extracted from the description in the specification, drawings, claims, etc.

[0030] FIGS. 1A and 1B are structural examples of a semiconductor device. FIGS. 2A and 2B are structural examples of a semiconductor device. FIGS. 3A and 3B are structural examples of a semiconductor device. FIG. 4 is a structural example of a semiconductor device. FIG. 5 is a structural example of a semiconductor device. FIGS. 6A and 6B are structural examples of a semiconductor device. FIG. 7 is a structural example of a semiconductor device. FIG. 8 is a structural example of a semiconductor device. FIGS. 9A, 9B, 9C, and 9D are structural examples of a semiconductor device. FIGS. 10A, 10B, 10C, and 10D are structural examples of a semiconductor device. FIGS. 11A, 11B, 11C, and 11D are diagrams illustrating an example of a method for manufacturing a semiconductor device. FIGS. 12A, 12B, and 12C are diagrams illustrating an example of a method for manufacturing a semiconductor device. FIGS. 13A, 13B, and 13C are diagrams illustrating an example of a method for manufacturing a semiconductor device. FIGS. 14A, 14B, and 14C are diagrams illustrating an example of a method for manufacturing a semiconductor device. FIGS. 15A, 15B, and 15C are diagrams illustrating an example of a method for manufacturing a semiconductor device. FIGS. 16A and 16B are diagrams illustrating an example of a method for manufacturing a semiconductor device. FIGS. 17A and 17B are diagrams illustrating an example of a method for manufacturing a semiconductor device. FIGS. 18A and 18B are diagrams illustrating carrier concentration dependence of Hall mobility. FIG. 18C is a cross-sectional view illustrating an indium oxide film. FIG. 19 is a block diagram illustrating a configuration example of a semiconductor device. FIGS. 20A, 20B, 20C, 20D, 20E, 20F, 20G, and 20H are diagrams illustrating an example of a circuit configuration of a memory cell. FIGS. 21A and 21B are perspective views illustrating an example of a configuration of a semiconductor device. FIG. 22 is a block diagram illustrating a CPU. FIGS. 23A and 23B are perspective views of a semiconductor device. FIGS. 24A and 24B are perspective views of a semiconductor device. FIGS. 25A and 25B are configuration examples of electronic components. 26A, 26B, and 26C are configuration examples of a mainframe computer, Fig. 27A is a configuration example of space equipment, and Fig. 27B is a configuration example of a storage system.

[0031] Hereinafter, embodiments will be described with reference to the drawings. However, it will be readily understood by those skilled in the art that the embodiments can be implemented in many different ways and that various changes in form and details can be made without departing from the spirit and scope of the present invention. Therefore, the present invention should not be interpreted as being limited to the following description of the embodiments.

[0032] In the configuration of the invention described below, the same parts or parts having similar functions are denoted by the same reference numerals in different drawings, and repeated explanations thereof will be omitted. Furthermore, when referring to similar functions, the same hatching pattern may be used and no particular reference numeral may be assigned.

[0033] In the drawings described in this specification, the size of each component, the thickness of a layer, or an area may be exaggerated for clarity, and therefore, the drawings are not necessarily limited to the scale.

[0034] In this specification, ordinal numbers such as "first" and "second" are used to avoid confusion of components and do not limit the number.

[0035] A transistor is a type of semiconductor element that can perform functions such as amplifying current or voltage and performing switching operations to control conduction or non-conduction. The term "transistor" as used herein includes an insulated gate field effect transistor (IGFET) and a thin film transistor (TFT).

[0036] Furthermore, the functions of "source" and "drain" may be interchangeable when transistors of different polarities are used, or when the direction of current flow changes during circuit operation, etc. For this reason, the terms "source" and "drain" may be used interchangeably in this specification.

[0037] Furthermore, in this specification, "electrically connected" includes connection via "something that has some kind of electrical action." Here, "something that has some kind of electrical action" is not particularly limited as long as it allows electrical signals to be transmitted and received between the connected objects. For example, "something that has some kind of electrical action" includes electrodes or wiring, as well as switching elements such as transistors, resistive elements, coils, and other elements with various functions.

[0038] In this specification, when two nodes are connected via an insulator such as a dielectric of a capacitive element, a gate insulating film of a transistor, or an interlayer insulating film, this is not considered to be an "electrical connection."

[0039] In this specification, the phrase "top surface shapes generally match" refers to the overlap of at least a portion of the contours between stacked layers. For example, this includes cases where the upper and lower layers are processed using the same mask pattern or a portion of the same mask pattern. However, strictly speaking, the contours may not overlap, and the upper layer may be located inside the lower layer, or outside the lower layer. In these cases, the phrase "top surface shapes generally match" may also be used.

[0040] In this specification, the top surface shape of a certain component refers to the contour shape of the component in a plan view. The plan view refers to a view from the normal direction of the surface on which the component is formed or the surface of a support (e.g., a substrate) on which the component is formed.

[0041] In the following description, expressions indicating directions such as "upper" and "lower" are basically used in accordance with the directions in the drawings. However, for ease of explanation, the directions indicated by "upper" or "lower" in the specification may not match those in the drawings. For example, when explaining the stacking order (or formation order) of a laminate, etc., even if the surface on which the laminate is provided (such as a forming surface, a supporting surface, an adhesive surface, or a flat surface) is located above the laminate in the drawings, the forming surface side may be expressed as "lower" and the laminate side as "upper."

[0042] In this specification, the channel length direction of a transistor refers to one of the directions parallel to the line connecting the source region and the drain region at the shortest distance. In other words, the channel length direction corresponds to one of the directions of current flowing through the semiconductor layer when the transistor is in an on-state. The channel width direction refers to a direction perpendicular to the channel length direction. Depending on the structure or shape of the transistor, the channel length direction and the channel width direction may not be defined as a single direction.

[0043] In addition, in this specification and the like, the terms "film" and "layer" are interchangeable. For example, the term "insulating layer" may be interchangeable with the term "insulating film."

[0044] Unless otherwise specified, in this specification and the like, the off-state current refers to the drain current when a transistor is in an off state (also referred to as a non-conducting state or a cut-off state). Unless otherwise specified, the off-state refers to a state in which the gate-source voltage Vgs is lower than the threshold voltage Vth for an n-channel transistor (higher than Vth for a p-channel transistor).

[0045] Embodiment 1 In this embodiment, a structural example of a semiconductor device according to one embodiment of the present invention will be described. The semiconductor device exemplified below can be applied to a memory device.

[0046] A semiconductor device according to one embodiment of the present invention includes a plurality of memory cells. Each memory cell includes one transistor and one memory element. Various elements capable of retaining stored data, such as a capacitor, a variable resistance element, a ferroelectric element, a charge trap element, or a floating gate element, can be used as the memory element. An example in which a capacitor is used as the memory element will be described below.

[0047] In a transistor included in a memory cell, a source electrode and a drain electrode are located at different heights, and a current flows in a semiconductor layer in a height direction. In other words, it can be said that the channel length direction has a component in the height direction (vertical direction). Therefore, one embodiment of the present invention can be called a VFET (Vertical Field Effect Transistor), a vertical transistor, a vertical channel transistor, a vertical channel transistor, or the like.

[0048] More specifically, a first insulating layer functioning as a spacer is provided above a lower electrode (first conductive layer) that is one of the source electrode and the drain electrode, and an upper electrode (second conductive layer) that is the other of the source electrode and the drain electrode is provided so as to have a portion located above the first insulating layer. The first insulating layer has a side surface that is approximately perpendicular to the upper surface of the lower electrode. The semiconductor layer has a vertical portion (also referred to as a vertical portion) along the side surface, a portion in contact with the upper electrode, and a portion in contact with the lower electrode. The portion of the semiconductor layer in contact with the lower electrode may have a portion (also referred to as a horizontal portion or lateral portion) that is parallel to the upper surface of the lower electrode. Furthermore, a gate insulating layer (second insulating layer) is provided to cover the vertical and horizontal portions of the semiconductor layer, and a gate electrode (third conductive layer) is provided to cover the vertical and horizontal portions via the gate insulating layer. Furthermore, a third insulating layer is provided to cover the vertical and horizontal portions via the gate insulating layer and the gate electrode.

[0049] The two transistors in two adjacent memory cells are preferably arranged symmetrically across the first insulating layer. That is, a configuration can be adopted in which a pair of semiconductor layers, a pair of gate insulating layers, a pair of gate electrodes, a pair of third insulating layers, etc. are arranged along a pair of side surfaces of the first insulating layer. This allows for even higher density arrangement of transistors. In this case, one or both of the upper electrode and the lower electrode may be common between two adjacent memory cells. For example, of the upper electrode and the lower electrode, an electrode connected to a bit line or functioning as a bit line itself can be common between adjacent memory cells. In this case, the other electrode can be connected to a capacitor.

[0050] Here, the capacitor of the memory cell can be provided below the transistor. By stacking the transistor and the capacitor, the memory cells can be arranged with high density. The capacitor can be a so-called MIM (Metal-Insulator-Metal) capacitor having a pair of electrodes. In this case, it is preferable that the lower electrode of the transistor also serves as the upper electrode of the capacitor. In this case, it is preferable that the upper electrode of the transistor functions as a bit line.

[0051] The semiconductor layer is preferably made of a metal oxide (oxide semiconductor) that exhibits semiconductor properties. For example, silicon, a typical semiconductor material, needs to be doped with impurities that function as donors or acceptors to form source and drain regions. However, in the vertical transistor of one embodiment of the present invention, it may be difficult to dope impurities into the semiconductor layer with high precision because the source and drain regions are different in height and the channel formation region is located vertically relative to the substrate surface. On the other hand, an oxide semiconductor can be well connected to source and drain electrodes without doping with such impurities. Therefore, a transistor having a three-dimensional structure as in one embodiment of the present invention can be manufactured with high yield.

[0052] In particular, it is preferable to use indium oxide for the semiconductor layer. Furthermore, it is preferable to use single-crystal or polycrystalline indium oxide. This makes it possible to realize a transistor having both high field-effect mobility and high reliability.

[0053] Here, the lower electrode preferably has a stacked structure in which a first conductive film and a second conductive film are stacked thereon. In this case, the second conductive film is in contact with the semiconductor layer. Furthermore, the second conductive film preferably contains a conductive metal oxide (oxide conductor). Using a metal oxide for the conductive film in contact with the metal oxide-containing semiconductor layer is preferable because it can reduce the contact resistance between them and the wiring load. In particular, it is preferable that the second conductive film contains the same metal element as the metal element contained in the semiconductor layer, because this can further reduce the contact resistance. For example, when indium oxide is used for the semiconductor layer, it is preferable to use a metal oxide containing indium for the second conductive film. Furthermore, a low-resistance metal material can be used for the first conductive film. This makes it possible to reduce both the contact resistance and the wiring resistance, thereby further reducing the wiring load.

[0054] Furthermore, it is preferable to use an insulating material capable of capturing or fixing hydrogen for the third insulating layer located near the semiconductor layer. This allows hydrogen, which may diffuse into the semiconductor layer due to heat or the like applied during the manufacturing process of the semiconductor device, to be captured or fixed by the third insulating layer, thereby reducing the concentration of hydrogen in the semiconductor layer. Oxygen vacancies in an oxide semiconductor are bonded with hydrogen to generate carriers, which may affect, for example, the threshold voltage of a transistor. Therefore, by providing such a third insulating layer near the semiconductor layer, a highly reliable transistor with favorable electrical characteristics can be realized. For example, hafnium oxide, aluminum oxide, or an oxide containing hafnium and silicon (also referred to as hafnium silicate) is preferably used for the third insulating layer.

[0055] A more specific example will be described below with reference to the drawings.

[0056] [Configuration Example] Fig. 1A shows a schematic top view of a semiconductor device 10. Figs. 2A, 2B, 3A, and 3B show schematic cross-sectional views taken along the cutting lines A1-A2, B1-B2, C1-C2, and D1-D2 shown in Fig. 1A, respectively. Each figure also shows arrows indicating the X, Y, and Z directions. Fig. 4 shows a perspective view of 4 x 2 memory cells. Some components (such as insulating layers) are omitted from Fig. 4.

[0057] The semiconductor device 10 has a configuration in which a plurality of memory cells 15 are arranged in the X and Y directions. In the semiconductor device 10, a conductive layer 25 functioning as a bit line extends in the X direction, and a conductive layer 23 functioning as a word line extends in the Y direction. As shown in FIG. 2A , the memory cell 15 has a transistor 20 and a capacitance element 30 thereunder.

[0058] 1B shows a circuit diagram corresponding to the semiconductor device 10. In FIG. 1B, a plurality of bit lines BL, a plurality of word lines WL orthogonal to each bit line, and wiring CL are shown. While FIG. 1B shows an example in which the wiring CL is parallel to the bit lines BL, the wiring CL may also be parallel to the word lines WL or may be arranged in a grid pattern. Alternatively, the wiring CL may be a flat conductive film.

[0059] The memory cell 15 includes one transistor 20 and one capacitor 30. The transistor 20 has a gate connected to a word line WL, one of a source and a drain connected to a bit line BL, and the other connected to one electrode of the capacitor 30. The other electrode of the capacitor 30 is connected to a wiring CL.

[0060] 1A, 1B, etc., the memory cells 15 arranged along the X direction are arranged so that the orientations of the transistors 20 are staggered. In other words, two transistors 20 adjacent along the X direction are arranged symmetrically with respect to the Y-Z plane.

[0061] The bit line BL functions as a wiring for writing and reading data. The word line WL functions as a wiring for controlling the on / off (conducting state or non-conducting state) of the transistor 20 functioning as a switch. The wiring CL functions as a constant potential line connected to the capacitor 30.

[0062] 1A, a conductive layer 29 is provided parallel to the conductive layer 25 functioning as a bit line. The conductive layer 29 is disposed between the pair of conductive layers 25 and is given a constant potential. The conductive layer 29 functions as a shielding layer for shielding signal transmission between two adjacent bit lines.

[0063] 5 shows a schematic top view of a case where the conductive layer 29 is not provided. With this configuration, it is possible to arrange the memory cells 15 at a higher density in the Y direction compared to a case where the conductive layer 29 is provided.

[0064] 2A and other drawings, the transistor 20 and the capacitor 30 are provided on an insulating layer 11 provided on a substrate (not shown). The insulating layer 11 functions as a base insulating layer.

[0065] 7 shows an enlarged view of the transistor 20 and the capacitor 30 in FIG. 2A and their vicinity. The transistor 20 includes a semiconductor layer 21, an insulating layer 22 functioning as a gate insulating layer, a conductive layer 23 functioning as a gate electrode, a conductive layer 24 functioning as one of a source electrode and a drain electrode, and a conductive layer 25 functioning as the other. Here, an example is shown in which the conductive layer 24 includes a conductive film 24a and a conductive film 24b located thereon.

[0066] The capacitor 30 is provided on a conductive layer 55 that functions as a wiring CL. The capacitor 30 includes a conductive layer 51 that functions as a lower electrode, a conductive layer 24 that functions as an upper electrode, and an insulating layer 52 that is disposed between the conductive layer 51 and the conductive layer 24 and functions as a dielectric. In this manner, the conductive layer 24 preferably serves as both the lower electrode of the transistor 20 and the upper electrode of the capacitor 30. This simplifies the manufacturing process and reduces manufacturing costs. As shown in FIG. 2A and other figures, when the conductive layer 24 has a stacked structure of conductive films 24a and 24b, the lower conductive film 24a can function as the upper electrode of the capacitor 30. In this case, the upper conductive film 24b can also function as a connection electrode for connecting the conductive film 24a and the semiconductor layer 21.

[0067] An insulating layer 41 is provided on an insulating layer 11, and a conductive layer 55 is provided on the insulating layer 41. Here, an example is shown in which the conductive layer 55 has a two-dimensional flat plate shape, but it may also be a wiring extending in the X direction, the Y direction, or another direction. Alternatively, it may have a lattice shape that combines two or more portions extending in different directions.

[0068] The insulating layer 41 functions as a protective insulating layer and has the function of preventing impurities such as hydrogen from diffusing from the insulating layer 11 side into the semiconductor layer 21. For example, a film through which hydrogen is less likely to diffuse than a silicon oxide film (having barrier properties against hydrogen), such as a silicon nitride film, a silicon nitride oxide film, an aluminum oxide film, a magnesium oxide film, a hafnium oxide film, or a gallium oxide film, can be used. In particular, it is preferable to use a silicon nitride film or a silicon nitride oxide film. Note that the insulating layer 41 does not have to be provided if it is not necessary.

[0069] In this specification and elsewhere, an oxynitride refers to a material having a higher content of oxygen atoms than nitrogen atoms, and a nitride oxide refers to a material having a higher content of nitrogen atoms than oxygen atoms. For example, silicon oxynitride refers to a material having a higher content of oxygen atoms than nitrogen atoms, and silicon nitride oxide refers to a material having a higher content of nitrogen atoms than oxygen atoms.

[0070] An insulating layer 46 is provided on the conductive layer 55. The insulating layer 46 functions as an interlayer insulating layer. The insulating layer 46 has a plurality of openings reaching the conductive layer 55, and one capacitor element 30 is provided for each opening. The conductive layer 51 has a portion provided along the side surface of the opening of the insulating layer 46 and a portion in contact with the top surface of the conductive layer 55. In other words, the conductive layer 51 has a cylindrical (also called cup-shaped) shape with a bottom and a recess. The insulating layer 52 has a portion provided along the recess of the conductive layer 51, a portion in contact with the top surface of the conductive layer 51, and a portion in contact with the top surface of the insulating layer 46. The conductive layer 24 is provided so as to fill the recess of the conductive layer 51 with the insulating layer 52 interposed therebetween. The conductive layer 24 also has a portion provided on the insulating layer 46 with the insulating layer 52 interposed therebetween. The portion is provided so as to be embedded in the insulating layer 44. The conductive layer 51 is provided individually for each memory cell and connected by the conductive layer 55. On the other hand, the conductive layer 24 is provided individually for each memory cell.

[0071] FIG. 4 shows an example in which the outline of the conductive layer 51 in a plan view is circular, but this is not limiting. The horizontal cross-sectional shape of the conductive layer 51 is not limited to a circular ring shape and may be an annular shape. For example, the outline shape of the conductive layer 51 in a plan view is not limited to a circle but may be an ellipse, a rectangle with rounded corners, or the like. It may also be a regular polygon such as an equilateral triangle, square, or regular pentagon, or a polygon other than a regular polygon. Furthermore, a concave polygon, such as a star-shaped polygon, in which at least one interior angle exceeds 180 degrees, can increase capacitance. Other shapes include a polygon with rounded corners and a closed curve combining straight lines and curves.

[0072] 2A and the like is a so-called cylinder-type or trench-type capacitor element. The configuration of the capacitor element 30 is not limited to this, and for example, a pillar-type capacitor element may also be used.

[0073] FIG. 7 shows an example in which the bottom of the conductive layer 51 is rounded. Furthermore, the bottoms of the insulating layer 52 provided along the conductive layer 51 and the conductive layer 24 provided on the insulating layer 52 are also rounded. The upper end of the conductive layer 51 is located below the upper surface of the insulating layer 46, and the upper ends of the conductive layer 51 and the insulating layer 46 are both rounded. By providing the conductive layer 51 and the insulating layer 46, which form the surface on which the insulating layer 52 is formed, with no corners, the insulating layer 52 can be prevented from becoming locally thin. Furthermore, by providing no corners in the conductive layer 51, localized electric field concentration can be prevented. This suppresses leakage current in the capacitor element 30, thereby improving reliability.

[0074] Furthermore, a rounded recess is formed on the upper surface of the conductive layer 55, and the bottom of the conductive layer 51 is fitted into the recess. This configuration increases the contact area between the conductive layer 55 and the conductive layer 51, thereby reducing the contact resistance between them. The recess in the conductive layer 55 can be formed by etching a portion of the upper portion of the conductive layer 55 when forming an opening in the insulating layer 46. As shown in FIG. 8 , the conductive layer 55 may have a layered structure of conductive films 55a and 55b, with the recess provided in the conductive film 55b. In this case, it is preferable to use a low-resistance conductive material such as a metal or alloy for the conductive film 55a. Furthermore, a material suitable for processing to form the recess can be selected for the conductive film 55b. Various conductive materials, such as not only metals but also nitride conductors and oxide conductors, can be used.

[0075] The conductive layer 24 is provided so as to be embedded in the insulating layer 44, and it is preferable that the heights of the upper surfaces of the conductive layer 24 (heights from the upper surface of the insulating layer 11) are approximately the same. Note that, in the conductive layer 24, the conductive film 24a may be embedded in the insulating layer 44, and the conductive film 24b may have a portion located above the insulating layer 44.

[0076] The conductive layer 24 includes a conductive film 24a and a conductive film 24b located thereon. The conductive film 24a is preferably made of a conductive material having a lower resistance than the conductive film 24b. In particular, it is preferable for the conductive film 24a to contain a metal material. The conductive film 24b is preferably made of a conductive metal oxide (oxide conductor).

[0077] Using a conductive metal oxide for the conductive film 24b in contact with the semiconductor layer 21 containing a metal oxide is preferable because the contact resistance between them can be reduced and the load on the wiring can be reduced. In particular, a configuration in which the conductive film 24b contains the same metal element as the metal element contained in the semiconductor layer 21 is preferable because the contact resistance can be further reduced. For example, when indium oxide is used for the semiconductor layer 21, it is preferable to use a metal oxide containing indium for the conductive film 24b. It is preferable to use a material for the conductive film 24b that contains one or more elements selected from tin, zinc, antimony, and titanium in addition to indium. Furthermore, using a metal material with lower resistance than the conductive film 24b for the conductive film 24a can reduce both the contact resistance and the wiring resistance, thereby further reducing the load on the wiring.

[0078] An insulating layer 43 is provided above the conductive layer 24 and the insulating layer 44. The insulating layer 43 is provided at least in a portion that overlaps with the insulating layer 44. The insulating layer 43 has a strip-shaped upper surface extending in the Y direction. The insulating layer 43 has a pair of side surfaces that are orthogonal to the X direction. A configuration is possible in which a portion of the side surfaces overlap with the conductive layer 24. It is preferable that the side surfaces of the insulating layer 43 are approximately perpendicular to the surface on which they are formed (the upper surface of the conductive layer 24 or the insulating layer 44). It is preferable that the height of the insulating layer 43 is greater than its width in the X direction.

[0079] In this specification, "two surfaces are perpendicular" refers to a state in which the interior angle between them is 80 degrees or more and 100 degrees or less. "Two surfaces are approximately perpendicular" refers to a state in which the interior angle between them is 60 degrees or more and 120 degrees or less. "Two surfaces are parallel" refers to a state in which the interior angle between them is -10 degrees or more and 10 degrees or less (including parallel). "Two surfaces are approximately parallel" refers to a state in which the interior angle between them is -30 degrees or more and 30 degrees or less (including parallel).

[0080] The semiconductor layer 21 is preferably made of a metal oxide (oxide semiconductor) that exhibits semiconductor properties. In particular, it is preferable to use indium oxide. Furthermore, it is preferable to use single-crystal or polycrystalline indium oxide. This makes it possible to realize a transistor 20 that has both high field-effect mobility and high reliability. Furthermore, since the field-effect mobility of the transistor 20 can be increased, it is possible to realize a memory cell 15 that can perform high-speed read and write operations.

[0081] The semiconductor layer 21 has a vertical portion in contact with the side surface of the insulating layer 43 and a horizontal portion in contact with the upper surface of the conductive layer 24. Note that the vertical portion is not necessarily vertical in the strict sense; if the side surface of the insulating layer 43 is inclined with respect to the Z direction, the vertical portion of the semiconductor layer 21 is also inclined along the side surface. Similarly, if the upper surface of the conductive layer 24 is inclined with respect to the X-Y plane (e.g., the substrate surface), the horizontal portion of the semiconductor layer 21 is also inclined along the upper surface. A part of the vertical portion of the semiconductor layer 21 functions as a channel formation region. Furthermore, the upper end of the vertical portion of the semiconductor layer 21 is in contact with the conductive layer 25.

[0082] More specifically, the vertical portion of the semiconductor layer 21 refers to a portion that is provided along the side surface of the insulating layer 43 and whose surface (either or both of the surface of the semiconductor layer 21 on the insulating layer 43 side or the surface of the insulating layer 22 side) is perpendicular or approximately perpendicular to the upper surface of the conductive layer 24 or the insulating layer 44. Furthermore, the horizontal portion of the semiconductor layer 21 refers to a portion that is provided along the upper surface of the conductive layer 24 or the insulating layer 44 and whose surface (the surface of the semiconductor layer 21 on the conductive layer 24 side or the surface of the insulating layer 22 side) is parallel or approximately parallel to the upper surface of the conductive layer 24 or the insulating layer 44.

[0083] The semiconductor layer 21 is divided between the two transistors 20 provided between the two insulating layers 43. In other words, it can be said that a pair of semiconductor layers 21 is provided symmetrically between the two insulating layers 43.

[0084] In the transistor 20, the source electrode and the drain electrode are located at different heights, and therefore, a current flows in the height direction through the semiconductor. That is, it can be said that the channel length direction has a component in the height direction (vertical direction). Therefore, the transistor of one embodiment of the present invention can also be called a VFET, a vertical transistor, a vertical channel transistor, or the like. Since the transistor 20 can have two or more of the source electrode, the semiconductor, and the drain electrode stacked, the occupied area can be significantly reduced compared to a so-called planar transistor (which can also be called a lateral transistor, LFET (Lateral FET), or the like) in which the semiconductor is arranged on a plane.

[0085] Furthermore, the channel length of the transistor 20 can be precisely controlled by the thickness of the insulating layer 43, which functions as a spacer. This significantly reduces the variation in channel length compared to planar transistors. Furthermore, by thinning the insulating layer 43, transistors with extremely short channel lengths can be fabricated. For example, transistors with channel lengths of 2 μm or less, 1 μm or less, 500 nm or less, 300 nm or less, 200 nm or less, 100 nm or less, 50 nm or less, 30 nm or less, or 20 nm or less, and 5 nm or more, 7 nm or more, or 10 nm or more, can be fabricated. Therefore, transistors with extremely short channel lengths that could not be achieved using mass-production exposure equipment can be realized. Furthermore, transistors with channel lengths of less than 10 nm can be fabricated without using the extremely expensive exposure equipment used in cutting-edge LSI technology.

[0086] 7 shows an example in which the semiconductor layer 21 has no bend between the vertical and horizontal portions and has a rounded, curved shape. The bottom of the insulating layer 43 also has a flared bottom. As shown in FIG. 7 , this configuration allows the insulating layer 22 covering the semiconductor layer 21 and the conductive layer 23 covering the insulating layer 22 to have a rounded shape, thereby realizing a configuration in which an electric field is less likely to concentrate, similar to the conductive layer 51 of the capacitance element 30. This allows for a highly reliable transistor with a small leakage current.

[0087] The insulating layer 22 is provided to cover the vertical and horizontal portions of the semiconductor layer 21. The conductive layer 23 is located on the insulating layer 22 and is provided to cover the vertical and horizontal portions of the semiconductor layer 21 via the insulating layer 22. An insulating layer 31 is provided on the conductive layer 23. The insulating layer 31 is provided to cover the vertical and horizontal portions of the semiconductor layer 21 via the insulating layer 22 and the conductive layer 23.

[0088] It is preferable to use an insulating film having a function of capturing or fixing hydrogen for the insulating layer 31. This allows hydrogen that may diffuse into the semiconductor layer 21 due to heat or the like applied during the manufacturing process of the transistor 20 or the memory cell 15 to be captured or fixed by the insulating layer 31, thereby reducing the concentration of hydrogen contained in the semiconductor layer 21. This makes it possible to realize a transistor 20 or a semiconductor device 10 with good electrical characteristics and high reliability. As an insulating film that can be used for the insulating layer 31 and that can capture or fix hydrogen, a hafnium oxide film, a hafnium silicate film, an aluminum oxide film, or the like is preferably used.

[0089] Slits are provided in insulating layer 31, conductive layer 23, insulating layer 22, and semiconductor layer 21, reaching insulating layer 44, and the layers are divided at the slits. Inside the slits, insulating layer 32 is provided along and in contact with the side surfaces of insulating layer 31, conductive layer 23, insulating layer 22, and semiconductor layer 21. Furthermore, insulating layer 33 is provided on insulating layer 32 so as to fill the slits.

[0090] As with the insulating layer 41, it is preferable to use an insulating film having a barrier property against hydrogen for the insulating layer 32. This can prevent hydrogen contained in the insulating layer 33 and the like from diffusing toward the semiconductor layer 21. It is preferable to use a silicon nitride film, a silicon nitride oxide film, an aluminum oxide film, a magnesium oxide film, a hafnium oxide film, a gallium oxide film, or the like for the insulating layer 32. It is particularly preferable to use a silicon nitride film or a silicon nitride oxide film.

[0091] It is preferable to use an insulating material with a low dielectric constant for the insulating layer 33. This can reduce the parasitic capacitance between the pair of conductive layers 23 sandwiching the insulating layer 33. For the insulating layer 33, an inorganic insulating material such as silicon oxide or silicon oxynitride can be used.

[0092] An insulating layer 34 is provided in contact with the upper surfaces of the conductive layer 23, the insulating layer 31, the insulating layer 32, and the insulating layer 33. The insulating layer 34 can also be provided in contact with the side surface of the insulating layer 22 (the side surface on the insulating layer 33 side).

[0093] As the insulating layer 34, it is preferable to use an insulating film having a barrier property against hydrogen, similar to the insulating layer 32 and the insulating layer 41. This makes it possible to prevent hydrogen from diffusing from above the insulating layer 34 toward the semiconductor layer 21. It is preferable to use a silicon nitride film, a silicon nitride oxide film, an aluminum oxide film, a magnesium oxide film, a hafnium oxide film, a gallium oxide film, or the like for the insulating layer 34. It is particularly preferable to use a silicon nitride film or a silicon nitride oxide film.

[0094] Furthermore, it is preferable to use an insulating film having a function of capturing or fixing hydrogen, similar to the insulating layer 31, for the insulating layer 34. This allows hydrogen that may diffuse into the semiconductor layer 21 due to heat or the like applied during the manufacturing process of the transistor 20 or the memory cell 15 to be captured or fixed by the insulating layer 34, thereby reducing the concentration of hydrogen contained in the semiconductor layer 21. This makes it possible to realize a highly reliable transistor 20 or semiconductor device 10 with good electrical characteristics. As an insulating film that can capture or fix hydrogen and that can be used for the insulating layer 34, it is preferable to use a hafnium oxide film, a hafnium silicate film, an aluminum oxide film, or the like.

[0095] An insulating layer 47 is provided to cover the insulating layer 43, the insulating layer 22, and the insulating layer 34. The insulating layer 47 functions as an interlayer insulating film. The insulating layer 47 can be made of an inorganic insulating material such as silicon oxide or silicon oxynitride.

[0096] Furthermore, a conductive layer 25 and a conductive layer 29 are provided on the insulating layer 34, the insulating layer 22, and the semiconductor layer 21. The conductive layer 25 and the conductive layer 29 are provided so as to be embedded in the insulating layer 47.

[0097] Here, the upper surface of the vertical portion of the semiconductor layer 21 may be located below the upper surface of the insulating layer 22, and a portion of the conductive layer 25 may be provided in the gap surrounded by the insulating layer 43, the insulating layer 22, and the semiconductor layer 21. In this case, the upper surface of the semiconductor layer 21 is preferably located below the upper surface of the conductive layer 23. If the upper surface of the semiconductor layer 21 is located above the upper surface of the conductive layer 23, a so-called offset region may be formed, to which a gate electric field is not applied. Therefore, by processing the upper surface of the semiconductor layer 21 so that it is located below the upper surface of the conductive layer 23, the formation of an offset region in the semiconductor layer 21 can be prevented, and the current that the transistor 20 can pass can be increased. As a result, a semiconductor device 10 with high operating speed can be realized.

[0098] The conductive layer 25 and the conductive layer 29 each extend in the X direction. The conductive layer 25 functions as a bit line, and is provided in common among the plurality of transistors 20 arranged in the X direction, as shown in Figures 1A, 2A, etc. In other words, the conductive layer 25 is provided in contact with each semiconductor layer 21 of the plurality of transistors 20 arranged in the X direction.

[0099] Here, an example is shown in which the conductive layer 29 is formed on the same surface as the conductive layer 25 by processing the same conductive film. This structure is preferable because the conductive layer 29 can be formed without adding an additional process. Note that the conductive layer 29 can also be formed in a different process from that of the conductive layer 25. In this case, the conductive layer 29 can have a stacked structure different from that of the conductive layer 25, or a single layer structure.

[0100] Here, two transistors 20 are provided symmetrically on either side of the insulating layer 43. More specifically, a pair of semiconductor layers 21, a pair of conductive layers 23, a pair of conductive layers 24, a pair of insulating layers 22, a pair of insulating layers 31, etc. are provided symmetrically on either side of the insulating layer 43. In this way, by providing the transistors 20 not only on one side surface of the insulating layer 43 but also along each of the two side surfaces positioned back to back, the integration degree of the transistors 20 can be increased, which is preferable.

[0101] An insulating layer 48 is provided to cover the conductive layer 25, the conductive layer 29, and the insulating layer 47. As the insulating layer 48, an insulating film having a barrier property against hydrogen is preferably used, similar to the insulating layers 34, 32, and 41. This makes it possible to prevent hydrogen from diffusing from above the insulating layer 48 toward the semiconductor layer 21. As the insulating layer 48, a silicon nitride film, a silicon nitride oxide film, an aluminum oxide film, a magnesium oxide film, a hafnium oxide film, a gallium oxide film, or the like is preferably used. In particular, a silicon nitride film or a silicon nitride oxide film is preferably used.

[0102] Here, it is preferable that the semiconductor device 10 has a layer in which the memory cells 15 are provided stacked on a layer in which the functional circuits are provided. The functional circuits may include, for example, a driver circuit for driving the memory cells 15, an arithmetic circuit, a power supply circuit, etc. The driver circuit may include, for example, one or more of a row decoder, a column decoder, a row driver, a column driver, an input circuit, an output circuit, a sense amplifier, etc. This not only reduces the footprint of the semiconductor chip including the semiconductor device 10, but also shortens the wiring length compared to when the functional circuits and the memory cells 15 are arranged side by side, thereby achieving high-speed operation and low power consumption.

[0103] 6A shows an example in which a transistor 90 that constitutes a functional circuit is arranged below the insulating layer 11. In this example, one of a source electrode and a drain electrode of the transistor 90 is connected to a conductive layer 25 that functions as a bit line.

[0104] The transistor 90 is a transistor in which a channel is formed in a part of a substrate 91, which is a single-crystal semiconductor substrate. The substrate 91 can typically be made of single-crystal silicon. The substrate 91 can be made of a semiconductor made of a single element such as germanium, or a compound semiconductor made of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, gallium oxide, or gallium nitride. Alternatively, the substrate 91 can be a semiconductor substrate having an insulator region therein, such as an SOI (Silicon On Insulator) substrate.

[0105] The transistor 90 is provided on a substrate 91 and includes a conductive layer 94 functioning as a gate, an insulating layer 93 functioning as a gate insulating layer, a semiconductor region 92 formed of part of the substrate 91, and low-resistance regions 95a and 95b functioning as source and drain regions. The transistor 90 may be either a p-channel type or an n-channel type. An element isolation layer 98 is provided on the substrate 91 between two adjacent transistors 90.

[0106] The transistor 90 has a semiconductor region 92 in which a channel is formed that has a convex shape (fin shape). Although not shown in Fig. 6A, a conductive layer 94 is provided to cover the side and top surfaces of the semiconductor region 92 in the X direction via an insulating layer 93. Such a transistor 90 is also called a FIN-type transistor.

[0107] An insulating layer 85 is provided covering the transistor 90, an insulating layer 86 is provided on the insulating layer 85, and an insulating layer 87 is provided on the insulating layer 86. A conductive layer 81 is provided so as to be embedded in the insulating layer 87. An insulating layer 11 is provided covering the conductive layer 81 and the insulating layer 87. A plug 82 is provided inside an opening provided in the insulating layer 85 and the insulating layer 86, and the plug 82 connects the low-resistance region 95a or the low-resistance region 95b to the conductive layer 81. A conductive layer 56 is provided on the insulating layer 41, and a conductive layer 57 is provided on the insulating layer 52. The conductive layer 56 can be formed by processing the same conductive film as the conductive layer 55, and the conductive layer 57 can be formed by processing the same conductive film as the conductive layer 24. A plug 83 is provided inside an opening provided in the insulating layer 41 and the insulating layer 11, and the plug 83 connects the conductive layer 56 to the conductive layer 81. Furthermore, the conductive layer 56 and the conductive layer 57 are connected by a plug 88 that penetrates the insulating layer 46 and the insulating layer 52, and the conductive layer 25 and the conductive layer 57 are connected by a plug 89 that penetrates the insulating layer 34, the insulating layer 33, the insulating layer 32, and the insulating layer 44. As a result, one of the source and the drain of the transistor 90 is connected to the conductive layer 25.

[0108] Note that although an example of providing a conductive layer 81 as a wiring layer has been shown here, a structure in which interlayer insulating layers and wiring layers are alternately stacked (also called a multilayer wiring layer) can be used between the layer in which the transistor 90 is provided and the layer in which the memory cell 15 is provided.

[0109] 6B shows a configuration in which the transistor 90 and the conductive layer 25 are connected by bonding a substrate 91 on which the transistor 90 is provided and a substrate on which the memory cell 15 is provided. The bonding surface between the two substrates is shown as surface 70. On the substrate 91 side, the surfaces of the conductive layer 71 and the insulating layer 75 are located on surface 70. The conductive layer 71 is connected to one of the source and drain of the transistor 90 via a plug 83, a conductive layer 81, a plug 82, etc. On the other hand, on the substrate side on which the memory cell 15 is provided, the surfaces of the conductive layer 72 and the insulating layer 76 are located on surface 70. The insulating layer 49 and the insulating layer 48 are provided on the insulating layer 47, and the conductive layer 72 and the insulating layer 76 are provided on the insulating layer 48. The conductive layer 72 is connected to the conductive layer 25 via a plug 78.

[0110] 6B shows an example of a case where direct bonding (hybrid bonding) using a direct bonding technique, such as Cu-Cu bonding, is used. Note that the bonding technique for the two layers is not limited to this. For example, a method of connecting electrodes provided on each layer by forming through electrodes after bonding two or more layers together with insulating films may also be used. In particular, using a method using direct bonding or through electrodes allows the pitch of the connection electrodes to be extremely narrow, making it possible to arrange a large number of connection electrodes at high density, which is preferable because it increases the amount of data transmitted between layers.

[0111] When bonding two layers, any of CoC (chip-on-chip) bonding, CoW (chip-on-wafer) bonding, and WoW (wafer-on-wafer) bonding may be used. WoW bonding is superior in productivity because wafers are bonded together, but since all chips, including both good and bad, are bonded together, the yield may be reduced. On the other hand, CoW bonding, which bonds a chip to a wafer, and CoC bonding, which bonds chips together, are inferior to WoW bonding in terms of productivity, but the yield is significantly improved because good chips can be bonded together. Furthermore, CoC bonding is inferior in productivity to the other two, but is highly versatile because it can bond two layers even when the sizes of the two layers are significantly different.

[0112] A wiring layer such as an interposer may be provided between the two layers, which eliminates the need to align the positions of bonding electrodes between two adjacent layers, increasing the degree of freedom in designing each layer and enabling the realization of a semiconductor device with higher performance.

[0113] The above is a description of an example of the configuration of the semiconductor device.

[0114] [Regarding Components] <Substrate> The substrate on which a transistor is formed may be, for example, an insulating substrate, a semiconductor substrate, or a conductive substrate. Examples of insulating substrates include glass substrates, quartz substrates, sapphire substrates, stabilized zirconia substrates (e.g., yttria-stabilized zirconia substrates), and resin substrates. Examples of semiconductor substrates include semiconductor substrates made of silicon or germanium, or compound semiconductor substrates made of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, gallium oxide, and gallium nitride. Examples of semiconductor substrates include those having an insulating region within the aforementioned semiconductor substrate, such as an SOI (Silicon-On-Insulator) substrate. Examples of conductive substrates include graphite substrates, metal substrates, alloy substrates, and conductive resin substrates. Alternatively, substrates containing metal nitrides or metal oxides may also be used. Further, there are substrates in which a conductive layer or a semiconductor layer is provided on an insulating substrate, substrates in which a conductive layer or an insulating layer is provided on a semiconductor substrate, and substrates in which a semiconductor layer or an insulating layer is provided on a conductive substrate. Alternatively, any of these substrates may be provided with elements. The elements provided on the substrate include capacitor elements, resistor elements, switch elements (including transistors), light-emitting elements, memory elements, and the like.

[0115] <Semiconductor Layer> The semiconductor layer 21 preferably contains a metal oxide (oxide semiconductor).

[0116] The semiconductor layer 21 is preferably made of indium oxide.

[0117] Metal oxides can be formed by sputtering or atomic layer deposition (ALD). ALD has excellent coating properties and is therefore suitable for uneven surfaces. On the other hand, sputtering can increase the film formation rate compared to ALD, thereby improving productivity.

[0118] By using a metal oxide that does not contain an element that easily bonds with oxygen, such as Ga, for the semiconductor layer 21, a transistor with high reliability against positive bias application can be obtained. In other words, a transistor with small fluctuation in threshold voltage in a PBTS (Positive Bias Temperature Stress) test can be obtained.

[0119] The semiconductor layer 21 may have a stacked structure including two or more metal oxide layers. When the semiconductor layer 21 has a stacked structure, it is preferable that at least one layer of the semiconductor layer 21 be made of indium oxide. Furthermore, oxides containing indium, gallium, zinc, or tin can be used for the other layers. More specific examples of metal oxides that can be used include Ga oxide, Zn oxide, Sn oxide, In—Zn oxide, In—Ga oxide, In—Sn oxide, In—Ti oxide, Ga—Zn oxide, In—Ga—Al oxide, In—Ga—Sn oxide, In—Ga—Zn oxide, In—Sn—Zn oxide, In—Al—Zn oxide, In—Ti—Zn oxide, In—Ga—Sn—Zn oxide, and In—Ga—Al—Zn oxide. Furthermore, these metal oxides may contain C, N, P, S, Se, F, Cl, Br, H, Y, Zr, Ag, Cd, Sn, Sb, Ba, Pb, Bi, La, Ce, Pr, Nd, Pm, Sm, Eu, etc. By containing such elements, the field-effect mobility may be increased in some cases.

[0120] When the semiconductor layer 21 has a two-layer structure, it is preferable to use a material with higher mobility (higher conductivity) in the second layer, i.e., the side closer to the gate electrode, than in the first layer. This allows for a transistor that is normally off and has a large on-current. This makes it possible to achieve both low power consumption and high performance. Alternatively, a material with higher mobility than in the second layer may be used in the first layer, i.e., the side in contact with the source electrode and drain electrode. This reduces the contact resistance between the semiconductor layer 21 and the source electrode or drain electrode, thereby reducing parasitic resistance and enabling a transistor with a large on-current.

[0121] Furthermore, when the semiconductor layer 21 has a three-layer structure, it is preferable to use a material for the second layer that has a higher mobility than the first and third layers, thereby realizing a transistor with a high on-current and high reliability.

[0122] The semiconductor layer 21 is preferably made of a crystalline metal oxide. In particular, it is preferable to use a metal oxide having a single crystal structure. Also, for example, a metal oxide layer having a c-axis aligned crystal (CAAC) structure, a polycrystalline structure, a nanocrystalline (nc) structure, or the like can be used. By using a crystalline metal oxide layer for the semiconductor layer 21, the defect level density in the semiconductor layer 21 can be reduced, and a highly reliable semiconductor device can be realized.

[0123] In particular, by using a single crystal or polycrystalline indium oxide film, a transistor exhibiting extremely high field-effect mobility comparable to that of polycrystalline silicon can be realized.

[0124] Here, when a single-crystal indium oxide film is used, it is preferable that the defects (including oxygen vacancies, lattice defects, etc.) in the crystal in the channel formation region be as few as possible, and that the amount of impurity elements (elements other than oxygen and indium) in the channel formation region be as few as possible. This allows for a high-purity, high-quality single crystal, reduces the carrier concentration, and increases the mobility (Hall mobility and field-effect mobility).

[0125] Furthermore, when a polycrystalline indium oxide film is used, the crystal grains in the channel formation region are preferably high-purity, high-quality crystals, similar to single crystals, and, similarly to the above, it is preferable that defects and impurities are reduced as much as possible. Furthermore, at the crystal grain boundaries, a large number of dangling bonds may cause a decrease in mobility. Therefore, it is preferable that the dangling bonds at the crystal grain boundaries are terminated with an element such as hydrogen so that the dangling bonds at the crystal grain boundaries are reduced as much as possible.

[0126] Furthermore, when a polycrystalline indium oxide film is used, it is preferable that no crystal grain boundaries exist at least in the channel formation region. Alternatively, it is preferable that the crystal orientation of the crystalline regions within at least the channel formation region is aligned. This allows at least the channel formation region to be considered a single-crystalline indium oxide film. Alternatively, it is also preferable that no crystal grain boundaries cross the current path (i.e., between the source and drain). For example, not only are the above-mentioned dangling bonds present at the crystal grain boundaries, but impurities may also segregate, which may cause a decrease in mobility (Hall mobility and field-effect mobility). The channel formation region here refers to a region of the semiconductor layer that overlaps (or faces) the gate electrode via the gate insulating layer, and is located between the region in contact with the source electrode and the region in contact with the drain electrode.

[0127] Thus, when a single-crystal or polycrystalline indium oxide film is used, it is preferable to supply oxygen to the indium oxide film during the process in order to reduce oxygen vacancies in the crystals (including crystal grains) in the channel formation region. It is also preferable that hydrogen in the crystals in the channel formation region is reduced. On the other hand, when a polycrystalline indium oxide film is used, it may be preferable to supply hydrogen during the process in order to terminate dangling bonds at the crystal grain boundaries.

[0128] A transistor using an oxide semiconductor (hereinafter referred to as an OS transistor) has significantly higher field-effect mobility than a transistor using amorphous silicon. Furthermore, an OS transistor has significantly lower source-drain leakage current in an off state (hereinafter also referred to as an off-state current) and can hold charge accumulated in a capacitor connected in series with the transistor for a long period of time. Furthermore, the use of an OS transistor can reduce the power consumption of a semiconductor device.

[0129] The semiconductor device according to one embodiment of the present invention can be applied to, for example, a processor, a memory device, or various ICs. The transistor according to one embodiment of the present invention is capable of passing a large current and has an extremely low off-state current, and therefore, high-speed operation of a circuit and low power consumption can be achieved at the same time.

[0130] A semiconductor device according to one embodiment of the present invention can also be applied to a display device, for example. To increase the emission luminance of a light-emitting device included in a pixel circuit of a display device, it is necessary to increase the amount of current flowing through the light-emitting device. To achieve this, it is necessary to increase the source-drain voltage of a driving transistor included in the pixel circuit. Since an OS transistor has a higher withstand voltage between the source and drain than a transistor using silicon (hereinafter referred to as a Si transistor), a high voltage can be applied between the source and drain of the OS transistor. Therefore, by using an OS transistor as the driving transistor included in the pixel circuit, it is possible to increase the amount of current flowing through the light-emitting device and increase the emission luminance of the light-emitting device.

[0131] When a transistor operates in the saturation region, an OS transistor can reduce the change in source-drain current with respect to a change in gate-source voltage compared to a Si transistor. Therefore, by using an OS transistor as a driving transistor included in a pixel circuit, the amount of current flowing through the light-emitting device can be precisely controlled. This allows for a larger number of gray levels in the pixel circuit. Furthermore, even if the electrical characteristics (e.g., resistance) of the light-emitting device fluctuate or vary, a stable current can flow.

[0132] As described above, by using an OS transistor for a driving transistor included in a pixel circuit, it is possible to achieve "suppression of black floating," "increase in light emission luminance," "multiple gradations," "suppression of the influence of manufacturing variations in light-emitting devices," and the like.

[0133] OS transistors exhibit little change in electrical characteristics due to radiation exposure, i.e., have high radiation resistance, and therefore can be suitably used in environments where radiation may be incident. It can also be said that OS transistors have high reliability against radiation. For example, OS transistors can be suitably used in pixel circuits of X-ray flat panel detectors. Furthermore, OS transistors can be suitably used in semiconductor devices used in outer space. Examples of radiation include electromagnetic radiation (e.g., X-rays and gamma rays) and particle radiation (e.g., alpha rays, beta rays, proton rays, and neutron rays).

[0134] <Gate Insulating Layer> The insulating layer 22 functions as a gate insulating layer of a transistor. When an oxide semiconductor is used for the semiconductor layer 21, it is preferable to use an oxide insulating film for at least the film of the insulating layer 22 that is in contact with the semiconductor layer 21. For example, one or more of silicon oxide, silicon oxynitride, aluminum oxide, aluminum oxynitride, hafnium oxide, hafnium oxynitride, gallium oxide, gallium oxynitride, yttrium oxide, yttrium oxynitride, and Ga—Zn oxide can be used. Alternatively, a nitride insulating film such as silicon nitride, silicon nitride oxide, aluminum nitride, or aluminum nitride oxide can also be used for the insulating layer 22. Furthermore, the insulating layer 22 may have a stacked structure, for example, a stacked structure including one or more oxide insulating films and one or more nitride insulating films.

[0135] Furthermore, the insulating layer 22 is preferably formed by laminating insulating materials made of high-k materials, and preferably by using a laminate structure of a high-dielectric-constant (high-k) material and a material with a higher dielectric strength than the high-k material. For example, the insulating layer 22 can be formed by laminating an insulating film (also referred to as ZAZ) in which zirconium oxide, aluminum oxide, and zirconium oxide are stacked in this order. Alternatively, the insulating film (also referred to as ZAZA) can be formed by laminating zirconium oxide, aluminum oxide, zirconium oxide, and aluminum oxide in this order. Alternatively, the insulating film can be formed by laminating hafnium zirconium oxide, aluminum oxide, hafnium zirconium oxide, and aluminum oxide in this order. By using a laminate of insulators with a relatively high dielectric strength, such as aluminum oxide, the dielectric strength is improved, and electrostatic breakdown of the capacitor element can be suppressed.

[0136] Furthermore, a material exhibiting ferroelectricity may be used for the insulating layer 22. Examples of the material exhibiting ferroelectricity include hafnium oxide, zirconium oxide, and HfZrO. Ｘ (X is a real number greater than 0). Ｘ (X is a real number greater than 0) may also be used as a metal oxide with Y (yttrium) added. Ｘ(X is a real number greater than 0) and adding Y (yttrium) to the compound can enhance the ferroelectricity.

[0137] When the insulating layer 22 has a two-layer structure, it is preferable to use an insulating film having a function of capturing or fixing hydrogen as the film in contact with the semiconductor layer 21, and to use an insulating film having a barrier property against hydrogen as the film located on the conductive layer 23 side that functions as the gate electrode. This makes it possible to suppress diffusion of hydrogen from the conductive layer 23 side to the semiconductor layer 21, thereby realizing a highly reliable transistor.

[0138] As an insulating film that captures or fixes hydrogen, it is preferable to use a hafnium oxide film, a hafnium silicate film, an aluminum oxide film, etc. Furthermore, as an insulating film having a barrier property against hydrogen, it is preferable to use a silicon nitride film, a silicon nitride oxide film, an aluminum oxide film, a magnesium oxide film, a hafnium oxide film, a gallium oxide film, etc.

[0139] Alternatively, an insulating film that releases oxygen when heated may be used as a film in contact with the semiconductor layer 21, and an insulating film having a barrier property against hydrogen may be used as a film located on the conductive layer 23 side. Alternatively, an insulating film that releases oxygen when heated may be used as a film in contact with the semiconductor layer 21, and an insulating film that has a function of capturing or fixing hydrogen may be used as a film located on the conductive layer 23 side.

[0140] When the insulating layer 22 has a three-layer structure, it is preferable to use an insulating film made of a material through which oxygen easily diffuses as the film in contact with the semiconductor layer 21, an insulating film having barrier properties against hydrogen and oxygen as the film located on the conductive layer 23 side, and an insulating film having the function of capturing or fixing hydrogen as the film located between them. Silicon oxide or silicon oxynitride can be used as the material through which oxygen easily diffuses. With this structure, oxygen can be supplied to the semiconductor layer 21 from the film in contact with the semiconductor layer 21. Furthermore, the film located on the conductive layer 23 side prevents oxygen from diffusing toward the conductive layer 23, thereby suppressing oxidation of the conductive layer 23.

[0141] As the insulating film having a barrier property against oxygen, it is preferable to use an aluminum oxide film, a silicon nitride film, a hafnium oxide film, a hafnium silicate film, etc. As the insulating film having a barrier property against oxygen and hydrogen, it is preferable to use an aluminum oxide film, a silicon nitride film, a hafnium oxide film, etc.

[0142] When the insulating layer 22 has a four-layer structure, it is preferable to use an insulating film having a barrier property against oxygen as the film in contact with the semiconductor layer 21, followed by an insulating film made of a material through which oxygen easily diffuses, an insulating film having a function of capturing or fixing hydrogen, and an insulating film having a barrier property against hydrogen and oxygen, from the side closer to the semiconductor layer 21. That is, in addition to the above-mentioned three-layer structure, a configuration can be obtained in which a film in contact with the semiconductor layer 21 is added. By using an insulating film having a barrier property against oxygen as the film in contact with the semiconductor layer 21, oxygen can be prevented from being desorbed from the semiconductor layer 21. In this case, it is preferable to use an aluminum oxide film as the film in contact with the semiconductor layer 21. Aluminum oxide not only has a barrier property against oxygen but also has a function of capturing or fixing hydrogen, and therefore has the effect of preventing hydrogen from diffusing into the semiconductor layer 21.

[0143] When the insulating layer 22 has a stacked structure, each insulating film is preferably a thin film. For example, the thickness of the insulating layer 22 is 1 nm to 20 nm, preferably 3 nm to 10 nm, to reduce the subthreshold swing (also referred to as the S value) of the transistor. The thickness of each insulating film is preferably 0.1 nm to 10 nm, more preferably 0.1 nm to 5 nm, more preferably 0.5 nm to 5 nm, still more preferably 1 nm to less than 5 nm, and even more preferably 1 nm to 3 nm.

[0144] As a specific example, it is preferable to use a four-layer structure in which an aluminum oxide film, a silicon oxide film, a hafnium oxide film, and a silicon nitride film are stacked in this order from the semiconductor layer 21 side, and to set the thicknesses of these films to 1 nm, 2 nm, 2 nm, and 1 nm from the semiconductor layer 21 side.

[0145] In this specification and the like, the barrier property refers to a property that makes it difficult for a corresponding substance to diffuse (also referred to as a property that makes it difficult for a corresponding substance to permeate, a property that the permeability of a corresponding substance is low, or a function that suppresses the diffusion of a corresponding substance). Note that when hydrogen is described as a corresponding substance, it can refer to, for example, a hydrogen atom, a hydrogen molecule, a water molecule, and OH. − Furthermore, unless otherwise specified, impurities when described as corresponding substances refer to impurities in the channel formation region or semiconductor layer, and include, for example, hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, and nitrogen oxide molecules (N ２ O, NO, NO ２ The term "oxygen" refers to at least one of an oxygen atom, an oxygen molecule, etc., when described as a corresponding substance.

[0146] Here, a transistor using a metal oxide film can have stable electrical characteristics by being surrounded by an insulating film that has a function of suppressing the permeation of impurities and oxygen. Examples of insulating films that have a function of suppressing the permeation of impurities and oxygen include insulating films containing one or more elements selected from boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, and tantalum, and the insulating films can be used in a single layer or a stacked layer. Specifically, examples of materials that can be used for the insulating film that has a function of suppressing the permeation of impurities and oxygen include metal oxides such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide, and nitrides such as aluminum nitride, silicon nitride oxide, and silicon nitride.

[0147] Specifically, examples of insulating film materials that have the function of suppressing the permeation of impurities such as water and hydrogen and oxygen include metal oxides such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide. Examples of insulating film materials that have the function of suppressing the permeation of impurities such as water and hydrogen and oxygen include oxides containing aluminum and hafnium (hafnium aluminate). Examples of insulating film materials that have the function of suppressing the permeation of impurities such as water and hydrogen and oxygen include nitrides such as aluminum nitride, aluminum titanium nitride, silicon nitride oxide, and silicon nitride.

[0148] Examples of insulating film materials capable of capturing or adhering hydrogen include metal oxides such as oxides containing hafnium, oxides containing magnesium, oxides containing aluminum, and oxides containing aluminum and hafnium (hafnium aluminate). These metal oxides may further contain zirconium, such as oxides containing hafnium and zirconium. Metal oxides with an amorphous structure have dangling bonds in some oxygen atoms, which enhance their ability to capture or adhering hydrogen. Therefore, these metal oxides preferably have an amorphous structure. For example, an amorphous structure may be achieved by including silicon in these oxides. For example, it is preferable to use an oxide containing hafnium and silicon (hafnium silicate). Metal oxides may have crystalline regions and / or grain boundaries in some regions.

[0149] <Conductive Layer> The conductive layer 24 and the conductive layer 25 are in contact with the semiconductor layer 21. When an oxide semiconductor is used as the semiconductor layer 21, if an easily oxidized metal such as aluminum is used in the portion of the conductive layer 24 or the conductive layer 25 in contact with the semiconductor layer 21, an insulating oxide (e.g., aluminum oxide) may be formed between the conductive layer 24 or the conductive layer 25 and the semiconductor layer 21, preventing electrical conduction therebetween. Therefore, it is preferable to use a conductive material that is resistant to oxidation, a conductive material that maintains low electrical resistance even when oxidized, or a conductive oxide material for at least the portion of the conductive layer 24 and the conductive layer 25 in contact with the semiconductor layer 21.

[0150] For example, titanium, tantalum nitride, titanium nitride, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, oxides containing lanthanum and nickel, etc. are preferably used for the conductive film 24b and conductive layer 25 in contact with the semiconductor layer 21. These are conductive materials that are difficult to oxidize, or materials that maintain conductivity even when oxidized, and are therefore preferred.

[0151] Alternatively, conductive oxides such as indium oxide, zinc oxide, In—Sn oxide, In—Zn oxide, In—W oxide, In—W—Zn oxide, In—Ti oxide, In—Ti—Sn oxide, In—Sn—Si oxide, and Ga—Zn oxide can be used. Conductive oxides containing indium are particularly preferred because of their high conductivity. Alternatively, oxide materials such as In—Ga—Zn oxide that can be used for the semiconductor layer 21 can also be used as a conductive layer by increasing the carrier concentration.

[0152] For example, the conductive layer 24 and the conductive layer 25 can each be a single-layer structure of the above-mentioned conductive oxide film, a three-layer structure in which a titanium nitride film, a tungsten film, and a titanium nitride film are stacked in this order, a two-layer structure in which a ruthenium film or a ruthenium oxide film is stacked on tungsten, a two-layer structure in which a ruthenium film or a ruthenium oxide film is stacked on the above-mentioned conductive oxide film, or a two-layer structure in which the above-mentioned conductive oxide film is stacked on a ruthenium film or a ruthenium oxide film.

[0153] The conductive layer 23 functions as a gate electrode and can be made of various conductive materials. For example, a metal element selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, lanthanum, etc., or an alloy containing such a metal element, may be used as the conductive layer 23. Alternatively, nitrides of the above metals or alloys, or oxides of the above metals or alloys, may be used. For example, tantalum nitride, titanium nitride, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, oxides containing lanthanum and nickel, etc. may be used. Alternatively, semiconductors with high electrical conductivity, such as polycrystalline silicon containing impurity elements such as phosphorus, or silicides such as nickel silicide may be used.

[0154] The conductive layer 23 may be made of the nitride or oxide that can be used for the conductive layers 24 and 25 .

[0155] Since the conductive layer 23, the conductive film 24a, and the conductive layer 25 also function as wiring, it is preferable to use a laminate of low-resistance conductive materials. For example, the low-resistance conductive material that can be used for the conductive layer 23 described above can also be used for the upper layer of the conductive film 24a and the conductive layer 25.

[0156] <Insulating Layer> The insulating layer 43 can be used as an interlayer insulating film. For example, it is preferably formed by a film formation method such as a sputtering method or a plasma CVD method. In particular, when a sputtering method is used, hydrogen gas is not required as a film formation gas, and therefore a film with an extremely low hydrogen content can be obtained. Therefore, the supply of hydrogen to the semiconductor layer 21 can be suppressed, and the electrical characteristics of the transistor 20 can be stabilized.

[0157] The insulating layer 43 is preferably an oxide insulating film because it is in contact with the channel formation region of the semiconductor layer 21. In particular, it is preferably an oxide insulating film that releases oxygen when heated. The insulating layer 43 can be an oxide insulating film that can be used for the gate insulating layer.

[0158] Furthermore, since the insulating layer 43 functions as an interlayer insulating layer, it is preferable to use a film formation method that allows film formation at a high film formation rate compared to other insulating layers. For example, the insulating layer 43 may be formed using TEOS (Tetra-Ethyl-Ortho-Silicate, chemical formula: Si(OC ２ H ５ ) ４ Alternatively, a silicon oxide film formed by plasma CVD using a silicon dioxide film containing SiO 2 may be used. This can improve productivity.

[0159] The insulating layer 11, the insulating layer 44, the insulating layer 46, and the insulating layer 47 each function as an interlayer insulating layer. The insulating layer 11, the insulating layer 44, the insulating layer 46, and the insulating layer 47 can be made of the same insulating material as can be used for the insulating layer 43.

[0160] The insulating layer 52 functions as a dielectric for the capacitance element 30. The insulating layer 52 can be made of the same insulating material as the insulating layer 22. Furthermore, by using the above-mentioned ferroelectric material for the insulating layer 52, the capacitance element 30 can be made into a ferroelectric capacitor, thereby realizing a nonvolatile memory device. Note that the capacitance element 30 can also be a resistance change type memory element that utilizes the electric field induced giant resistance change (CER: Colossal Electro-Resistance) effect.

[0161] This concludes the description of the components.

[0162] [Modification] The following describes an example in which the configuration is partially different from the above-described configuration example. Note that the same reference numerals are used to designate the same parts as those described above, and descriptions thereof will be omitted.

[0163] [Modification 1] The configuration shown in FIG. 8 differs from the above-described configuration examples mainly in that the shape of the conductive layer 24 is different.

[0164] A recess is formed in the conductive film 24b of the conductive layer 24. More specifically, the thickness of the region of the conductive film 24b overlapping with the semiconductor layer 21 is processed to be thinner than the region of the conductive film 24b overlapping with the insulating layer 43. The semiconductor layer 21 contacts not only the top surface of the recess of the conductive film 24b but also the side surfaces. With this configuration, the contact area between the semiconductor layer 21 and the conductive film 24b can be increased, thereby further reducing the contact resistance therebetween.

[0165] Furthermore, the recess provided in the conductive film 24b is processed so that the region between the side surface and the bottom surface has a curved shape. As a result, the lower ends of the semiconductor layer 21, the insulating layer 22, and the conductive layer 23 covering the conductive film 24b are curved and no corners are formed, realizing a configuration in which electric field concentration is unlikely to occur. This allows for the realization of a highly reliable transistor 20.

[0166] 9A is different from the above-described exemplary configuration mainly in that it does not include insulating layer 31. Note that in FIG. 9A and other figures, the region between insulating layer 44 and insulating layer 41 is omitted.

[0167] 9A , the insulating layer 32 is provided in contact with the surface of the conductive layer 23 on the insulating layer 33 side. A part of the insulating layer 32 covers the horizontal portion of the semiconductor layer 21 via the conductive layer 23 and the insulating layer 22. The insulating layer 33 also covers the horizontal portion of the semiconductor layer 21 via the insulating layer 32, the conductive layer 23, and the insulating layer 22. Not providing the insulating layer 31 is preferable because the step of forming the insulating layer 31 can be omitted and the manufacturing process can be simplified.

[0168] FIG. 9B shows an example in which the conductive film 24b having the recesses illustrated in the first modification is applied to this configuration.

[0169] 9A and 9B, an insulating film having a function of capturing or fixing hydrogen is preferably used for insulating layer 32 or insulating layer 33 instead of insulating layer 31. As an insulating film that can be used for insulating layer 32 or insulating layer 33 and that can capture or fix hydrogen, a hafnium oxide film, a hafnium silicate film, an aluminum oxide film, or the like is preferably used.

[0170] [Modification 3] The configuration shown in FIG. 9C differs from Modification 2 above mainly in that it does not have the insulating layer 33 and that the shape of the insulating layer 32 is different.

[0171] The insulating layer 32 is provided to fill a region surrounded by the conductive layer 23, the insulating layer 22, the semiconductor layer 21, and the insulating layer 34. With this structure, the steps of forming the insulating layers 31 and 33 can be omitted, thereby simplifying the manufacturing process.

[0172] FIG. 9D shows an example in which the conductive film 24b having the recesses illustrated in the first modification is applied to this configuration.

[0173] 9C and 9D, it is preferable to use an insulating film having a function of capturing or fixing hydrogen as insulating layer 32 instead of insulating layer 31. As an insulating film that can be used for insulating layer 32 and that can capture or fix hydrogen, it is preferable to use a hafnium oxide film, a hafnium silicate film, an aluminum oxide film, or the like.

[0174] [Modification 4] The configuration shown in FIG. 10A differs from the above-described configuration example 1 mainly in that the insulating layer 22 is not divided between a pair of insulating layers 43 .

[0175] The insulating layer 22 is provided to cover the side surfaces of the horizontal portions of the semiconductor layer 21. With this configuration, the surface of the semiconductor layer 21 is not exposed during the manufacturing process of the insulating layer 32 and is covered with the insulating layer 22, so that damage to the semiconductor layer 21 can be suppressed and reliability can be improved.

[0176] 10B shows an example in which the conductive film 24b having the recesses illustrated in the above-described Modification 1 is applied to this configuration. Also, Figures 10C and 10D show an example in which the insulating layer 31 is not provided, as in the above-described Modification 2. Although not shown here, a configuration in which the insulating layer 31 and the insulating layer 33 are not provided may also be used, as in the above-described Modification 3.

[0177] The above is a description of the modified example.

[0178] [Manufacturing Method Example] An example of a manufacturing method of a semiconductor device according to one embodiment of the present invention will be described below, taking the semiconductor device 10 including the memory cell 15 exemplified in the above structure example as an example.

[0179] Thin films (insulating films, semiconductor films, conductive films, etc.) constituting the semiconductor device can be formed by a sputtering method, a chemical vapor deposition (CVD) method, a vacuum evaporation method, a pulsed laser deposition (PLD) method, an atomic layer deposition (ALD) method, or the like.

[0180] Furthermore, thin films (insulating films, semiconductor films, conductive films, etc.) constituting the semiconductor device can be formed by methods such as spin coating, dipping, spray coating, inkjet, dispensing, screen printing, offset printing, doctor knife, slit coating, roll coating, curtain coating, and knife coating.

[0181] Sputtering methods include RF sputtering, which uses a high-frequency power supply as the sputtering power source, DC sputtering, which uses a direct current power supply, and pulsed DC sputtering, which changes the voltage applied to the electrode in a pulsed manner. RF sputtering is mainly used to deposit insulating films, while DC sputtering is mainly used to deposit metal conductive films. Pulsed DC sputtering is mainly used to deposit films of compounds such as oxides, nitrides, and carbides using reactive sputtering.

[0182] CVD methods can be classified into plasma-enhanced chemical vapor deposition (PECVD), which uses plasma, thermal CVD (TCVD), which uses heat, and photo-CVD (photo-CVD), which uses light. CVD methods can also be further classified into metal CVD (MCVD) and metal organic CVD (MOCVD), depending on the source gas used.

[0183] The plasma CVD method can produce high-quality films at relatively low temperatures. Furthermore, since the thermal CVD method does not use plasma, it is possible to minimize plasma damage to the workpiece. Furthermore, since the thermal CVD method does not cause plasma damage during film formation, it can produce films with fewer defects.

[0184] As the ALD method, a thermal ALD method in which a precursor and a reactant are reacted using only thermal energy, a PEALD method in which a plasma-excited reactant is used, or the like can be used.

[0185] Unlike sputtering, CVD and ALD are film formation methods that are less affected by the shape of the workpiece and have good step coverage. In particular, ALD has excellent step coverage and excellent thickness uniformity, making it suitable for coating the surface of an opening with a high aspect ratio. However, because ALD has a relatively slow film formation rate, it may be preferable to use it in combination with other film formation methods, such as CVD, which have a faster film formation rate.

[0186] In the CVD method, a film of any composition can be formed by adjusting the flow rate ratio of the source gases. For example, in the CVD method, a film with a continuously changing composition can be formed by changing the flow rate ratio of the source gases while forming the film. When forming a film while changing the flow rate ratio of the source gases, the time required for film formation can be shortened compared to when forming a film using multiple film formation chambers because no time is required for transportation or pressure adjustment. Therefore, the productivity of semiconductor devices can be increased in some cases.

[0187] In the ALD method, a film of any composition can be formed by simultaneously introducing multiple different precursors. Alternatively, when multiple different precursors are introduced, a film of any composition can be formed by controlling the number of cycles of each precursor. Furthermore, as with the CVD method, a film with a continuously changing composition can be formed.

[0188] The thin film constituting the semiconductor device can be processed using a photolithography method or the like. Alternatively, the thin film may be processed using a nanoimprint method, a sandblasting method, a lift-off method or the like. Alternatively, the island-shaped thin film may be directly formed by a film formation method using a shielding mask such as a metal mask.

[0189] There are two typical photolithography methods: one is to form a resist mask on the thin film to be processed, process the thin film by etching or the like, and then remove the resist mask; the other is to form a photosensitive thin film, and then process the thin film into the desired shape by exposure and development.

[0190] In photolithography, the light used for exposure can be, for example, i-line (wavelength 365 nm), g-line (wavelength 436 nm), h-line (wavelength 405 nm), or a mixture of these. Other light sources that can be used include ultraviolet light, KrF laser light, ArF laser light, etc. Exposure can also be performed by immersion exposure technology. Extreme ultraviolet (EUV) light or X-rays can also be used as the light used for exposure. An electron beam can also be used instead of light used for exposure. Extreme ultraviolet light, X-rays, or an electron beam are preferred because they enable extremely fine processing. When exposure is performed by scanning a beam such as an electron beam, a photomask is not required.

[0191] For etching the thin film, dry etching, wet etching, sandblasting, or the like can be used.

[0192] 11A to 16B are schematic cross-sectional views corresponding to the steps in the example of the fabrication method described below, and each view corresponds to a cross section taken along the line O-P-Q shown in FIG.

[0193] First, a substrate (not shown) is prepared, and an insulating layer 11 is formed on the substrate.

[0194] The substrate may be a substrate having heat resistance sufficient to withstand at least the subsequent heat treatment.

[0195] An inorganic insulating film such as a silicon oxide film or a silicon oxynitride film can be used as the insulating layer 11. The insulating layer 11 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. If the surface on which the insulating layer 11 is to be formed is not flat, a planarization process may be performed after the insulating layer 11 is formed so that the upper surface of the insulating layer 11 becomes flat.

[0196] Subsequently, an insulating layer 41 is formed on the insulating layer 11. The insulating layer 41 can be formed by a film formation method such as a sputtering method, an ALD method, or a CVD method.

[0197] Next, a conductive film that will become the conductive layer 55 is formed on the insulating layer 41. The conductive film can be formed by a film formation method such as a sputtering method, an ALD method, or a CVD method. Next, a resist mask is formed on the conductive film, and unnecessary portions of the conductive film are removed by etching to form the conductive layer 55. The conductive layer 55 can have a plate-like, line-like, or lattice-like shape.

[0198] Next, an insulating film is formed to cover the conductive layer 55, and then planarization treatment is performed until the top surface of the conductive layer 55 is exposed. This allows the conductive layer 55 to be embedded in an insulating layer (not shown). Note that although an example in which an insulating layer (not shown) is formed after the conductive layer 55 is shown here, the conductive layer 55 and the insulating layer may be formed by forming an insulating film, forming an opening (or a recess) in the insulating film for embedding the conductive layer 55, forming a conductive film to be the conductive layer 55, and performing planarization treatment until the surface of the insulating film is exposed. For the planarization treatment, for example, CMP (Chemical Mechanical Polishing), dry etching, or the like may be used.

[0199] The cross section at this stage corresponds to FIG. 11A.

[0200] Subsequently, the insulating layer 46 is formed on the conductive layer 55. The insulating layer 46 can be formed by a film formation method such as a sputtering method, an ALD method, or a CVD method.

[0201] Next, an opening is formed in the insulating layer 46 down to the conductive layer 55 (FIG. 11B). At this time, a part of the upper surface of the conductive layer 55 may be etched. By etching the conductive layer 55 so that a curved surface is formed on the upper part, the structure shown in FIGS. 7 and 8 can be obtained.

[0202] Subsequently, a conductive film to be the conductive layer 51 is formed to cover the upper surface of the insulating layer 46, the side surfaces of the insulating layer 46 in the opening, and the upper surface of the conductive layer 55. The conductive film can be formed by a method such as CVD, ALD, or sputtering. From the viewpoint of coverage, it is particularly preferable to form the conductive film by a CVD method.

[0203] Next, a sacrificial layer is formed on the conductive film so as to cover the recess of the opening, and a planarization process is performed until the top surface of the insulating layer 46 is exposed. The sacrificial layer is then removed, thereby forming a conductive layer 51 that is located only inside the opening (Figure 11C).

[0204] Here, during the planarization process or removal of the sacrificial layer, the height of the upper surface of the conductive layer 51 may become lower than the upper surface of the insulating layer 46. Also, the corners of the upper end of the conductive layer 51 and the upper end of the opening in the insulating layer 46 may be scraped and rounded. As a result, the configuration shown in FIGS. 7 and 8 can be obtained.

[0205] Next, an insulating layer 52 is formed along the surfaces of the insulating layer 46 and the conductive layer 51. The insulating layer 52 can be formed by a film formation method such as sputtering, ALD, or CVD, but ALD is preferable from the viewpoint of coverage. Next, a conductive film 24af that will become the conductive film 24a is formed on the insulating layer 52 so as to fill the recesses in the openings of the insulating layer 46. Thereafter, the upper surface of the conductive film 24af may be planarized as necessary. Next, a conductive film 24bf that will become the conductive film 24b is formed on the conductive film 24af (FIG. 11D).

[0206] The conductive films 24af and 24bf can be formed by a film formation method such as a sputtering method, an ALD method, a CVD method, etc. Subsequently, a resist mask is formed on the conductive film 24bf, and unnecessary portions of each conductive film are removed by etching, thereby forming the conductive layer 24 including the conductive film 24a and the conductive film 24b.

[0207] Next, an insulating film that will become the insulating layer 44 is formed to cover the conductive layer 24, and then planarization is performed until the upper surface of the conductive film 24b is exposed, thereby forming the insulating layer 44 (FIG. 12A). The insulating film that will become the insulating layer 44 can be formed by a film formation method such as a sputtering method, an ALD method, or a CVD method.

[0208] Next, the insulating layer 43 is formed on the conductive layer 24 and the insulating layer 44 ( FIG. 12B ). First, an insulating film that will become the insulating layer 43 is formed, and then the insulating film is etched by photolithography to form the insulating layer 43. After the insulating layer 43 is formed, the upper surfaces of the conductive film 24b and the insulating layer 44 are exposed.

[0209] It should be noted that there is a risk that the insulating layer 44 may be etched and thinned during processing of the insulating layer 43. In such a case, an insulating layer that functions as an etching stop film may be provided under the insulating film that will become the insulating layer 43, and after the insulating layer 43 is formed by etching, the etching stop film may be subsequently etched, thereby exposing the top surfaces of the insulating layer 44 and the like.

[0210] Here, since the thickness of the insulating layer 43 affects the channel length of the transistor, it is important to prevent the insulating layer 43 from varying in thickness.

[0211] When processing the insulating layer 43, it is preferable to process it by anisotropic dry etching so that the side surfaces are approximately vertical. Depending on the processing conditions, the side surfaces of the insulating layer 43 may be inclined with respect to the direction perpendicular to the surface on which they are formed, resulting in a tapered shape.

[0212] Furthermore, when processing the insulating layer 43, a portion of the upper part of the conductive film 24b can be etched to reduce the thickness of the region that does not overlap with the insulating layer 43. At this time, it is preferable to process the insulating layer 43 so that the side surface of the insulating layer 43 is positioned on the conductive film 24b. This makes it possible to form the conductive film 24b having the recessed portion shown in FIG. 7 and the like. At this time, it is preferable to determine the etching conditions so that the conductive film 24b does not disappear, or to form the conductive film 24b thick in advance.

[0213] The insulating film to be the insulating layer 43 is preferably an oxide film that contains a large amount of oxygen to such an extent that oxygen is released by heating and that contains a small amount of hydrogen. The insulating film to be the insulating layer 43 can be formed by a film formation method such as a PECVD method, a sputtering method, or an ALD method, but is particularly preferably formed by a sputtering method. In particular, by forming the insulating film using a gas containing oxygen and not a gas containing hydrogen as a film formation gas, an insulating film with an extremely small amount of hydrogen and an excess amount of oxygen can be formed. By forming the insulating film to be the insulating layer 43 in this manner, oxygen can be supplied from the insulating layer 43 to the channel formation region of the semiconductor layer 21, thereby reducing oxygen vacancies.

[0214] Subsequently, heat treatment may be performed. The heat treatment may be performed at a temperature of 250° C. or higher and 650° C. or lower, preferably 300° C. or higher and 500° C. or lower, more preferably 320° C. or higher and 450° C. or lower. Note that the heat treatment is performed in a nitrogen gas or inert gas atmosphere, or an atmosphere containing an oxidizing gas at 10 ppm or higher, 1% or higher, or 10% or higher. For example, when the heat treatment is performed in a mixed atmosphere of nitrogen gas and oxygen gas, the oxygen gas concentration is preferably about 20%. The heat treatment may be performed under reduced pressure. Alternatively, the heat treatment may be performed in an atmosphere containing an oxidizing gas at 10 ppm or higher, 1% or higher, or 10% or higher to compensate for desorbed oxygen after the heat treatment in the nitrogen gas or inert gas atmosphere. By performing the above heat treatment, impurities such as water and hydrogen contained in the insulating layer 43 or the like can be reduced before the formation of an oxide semiconductor film to be a semiconductor layer.

[0215] The gas used in the heat treatment is preferably highly purified. For example, the amount of moisture contained in the gas used in the heat treatment is set to 1 ppb (0.001 ppm) or less, preferably 0.1 ppb or less, and more preferably 0.05 ppb or less. By performing the heat treatment using a highly purified gas, it is possible to prevent moisture and the like from being introduced into the insulating layer 43 and the like as much as possible.

[0216] A process of supplying oxygen may be performed after the insulating film that becomes the insulating layer 43 is formed or after processing into the insulating layer 43. This allows oxygen to be supplied from the insulating layer 43 to the semiconductor film 21f by heat or the like applied after the semiconductor film 21f is formed.

[0217] Examples of the treatment for supplying oxygen include heat treatment in an oxygen-containing atmosphere and plasma treatment (including microwave plasma) in an oxygen-containing atmosphere. Alternatively, oxygen may be supplied to the insulating layer by forming an oxide film (preferably a metal oxide film) in an oxygen-containing atmosphere by sputtering. The formed oxide film may be removed immediately or may be left as it is. Note that the oxygen-containing atmosphere may be oxygen gas (O ２ ) as well as ozone (O ３ ), nitrous oxide (N ２ The atmosphere may include a gas containing an oxygen-containing compound such as oxygen (O).

[0218] Subsequently, a semiconductor film 21f, which will later become the semiconductor layer 21, is formed to cover the insulating layer 43, the conductive film 24b, and the insulating layer 44 (FIG. 12C).

[0219] The semiconductor film 21f can be a metal oxide (oxide semiconductor) film having semiconductor properties. The metal oxide film can be formed by a suitable method such as sputtering, CVD, MBE, PLD, or ALD. The sputtering or ALD method is particularly preferred. The metal oxide film is preferably formed in contact with the substantially vertical side surfaces of the insulating layer 43. Therefore, the metal oxide film is preferably formed by a method with good coverage, and more preferably by ALD.

[0220] The metal oxide film preferably has crystallinity. In particular, the metal oxide film of one embodiment of the present invention preferably has a metal oxide having a single crystal structure or a polycrystalline structure.

[0221] It is preferable to perform a treatment to enhance the crystallinity of the metal oxide film during or after the formation of the metal oxide film. Examples of treatments to enhance the crystallinity of the metal oxide film include heat treatment, plasma treatment, microwave (typically 2.45 GHz) treatment, microwave plasma treatment, and light (e.g., ultraviolet light) irradiation treatment. A plurality of these treatments may be performed simultaneously or sequentially. For example, heat treatment and microwave plasma treatment may be performed simultaneously. Alternatively, microwave plasma treatment may be performed after heat treatment.

[0222] Furthermore, it is more preferable to perform the treatment for increasing the crystallinity of the metal oxide film multiple times during the formation of the metal oxide film. For example, when forming a metal oxide film by the ALD method, it is preferable to perform a microwave plasma treatment every time an atomic layer is formed. Alternatively, it is preferable to perform a treatment for increasing the crystallinity every time a metal oxide film having a thickness within a predetermined range is formed, which can improve productivity. Specifically, it is preferable to form a first metal oxide film having a thickness of 1 nm to 10 nm, perform the first microwave plasma treatment, and then form a second metal oxide film having a thickness of 1 nm to 10 nm, and perform the second microwave plasma treatment.

[0223] The deposition method for the first metal oxide film and the second metal oxide film is not particularly limited, and ALD or sputtering may be used for each. In particular, depositing the first metal oxide film by ALD is preferable because it can prevent elements from the layer constituting the surface to be formed from being mixed into the first metal oxide film and the second metal oxide film (also known as mixing). This is particularly suitable when the elements contained in the layer constituting the surface to be formed inhibit the crystallization of the metal oxide (e.g., when the layer contains silicon, carbon, or the like). The first metal oxide film and the second metal oxide film may have different compositions. Although a stacked structure of the first metal oxide film and the second metal oxide film is illustrated here, the present invention is not limited thereto. Similar processes can be applied to a single-layer or a stacked structure of three or more layers of metal oxide films.

[0224] Furthermore, a treatment for increasing the crystallinity of a metal oxide film may be performed after the metal oxide film is formed. Specifically, the treatment may be performed directly on the formed metal oxide film, or may be performed through another film, such as an insulating film, formed on the metal oxide film. For example, a microwave plasma treatment may be performed after the metal oxide film is formed, or an insulating film (e.g., a silicon nitride film, a silicon oxide film, an aluminum oxide film, etc.) may be formed after the metal oxide film is formed, and then a heat treatment or a microwave plasma treatment may be performed on the metal oxide film through the insulating film.

[0225] The above-described treatment for increasing the crystallinity of a metal oxide film can also serve as a treatment for removing impurities contained in the metal oxide film. For example, carbon, hydrogen, nitrogen, and the like contained in the metal oxide film can be preferably removed. Alternatively, by performing the treatment for increasing the crystallinity of a metal oxide film in an oxygen gas atmosphere, oxygen vacancies in the metal oxide film can be reduced.

[0226] When performing a treatment to increase the crystallinity of a metal oxide film, it is preferable to set the temperature of the heat treatment (or the temperature of the substrate) to room temperature (e.g., 25°C) or higher, 100°C or higher and 700°C or lower, 100°C or higher and 600°C or lower, or 300°C or higher and 450°C or lower.

[0227] By increasing the crystallinity of the metal oxide film, a highly reliable transistor can be realized.

[0228] The metal oxide film can be formed by, for example, a sputtering method using a metal oxide target.

[0229] The metal oxide film is preferably a dense film with as few defects as possible. Furthermore, the metal oxide film is preferably a high-purity film with as few impurities as possible, such as hydrogen and water, as reduced as possible. In particular, it is preferable to use a crystalline metal oxide film as the metal oxide film.

[0230] Furthermore, when forming a metal oxide film, oxygen gas may be mixed with an inert gas (e.g., helium gas, argon gas, xenon gas, etc.). Note that the higher the ratio of oxygen gas to the total deposition gas when forming the metal oxide film (hereinafter also referred to as the oxygen flow ratio), the higher the crystallinity of the metal oxide film can be, and a highly reliable transistor can be realized. On the other hand, the lower the oxygen flow ratio, the lower the crystallinity of the metal oxide film can be, and a transistor with a higher on-state current can be obtained.

[0231] When forming a metal oxide film, the higher the substrate temperature, the higher the crystallinity and density of the metal oxide film, whereas the lower the substrate temperature, the lower the crystallinity and electrical conductivity of the metal oxide film.

[0232] The conditions for forming the metal oxide film include a substrate temperature of room temperature or higher and 250° C. or lower, preferably room temperature or higher and 200° C. or lower, and more preferably room temperature or higher and 140° C. or lower. For example, a substrate temperature of room temperature or higher and lower than 140° C. is preferred because it increases productivity. Furthermore, by forming the metal oxide film at room temperature or without intentional heating, the crystallinity can be reduced.

[0233] When the ALD method is used, it is preferable to use a film formation method such as thermal ALD (Atomic Layer Deposition) or PEALD (Plasma Enhanced ALD). The thermal ALD method is preferable because it exhibits extremely high step coverage. The PEALD method is also preferable because it exhibits high step coverage and allows low-temperature film formation.

[0234] For example, when a metal oxide is used for the semiconductor layer 21, the semiconductor layer 21 can be formed by the ALD method using a precursor containing the constituent metal element and an oxidizing agent.

[0235] For example, when forming an indium oxide film, a precursor containing indium and an oxidizing agent can be used.

[0236] Furthermore, when forming an In—Ga—Zn oxide film, three precursors, namely, a precursor containing indium, a precursor containing gallium, and a precursor containing zinc, can be used, or two precursors, namely, a precursor containing indium and a precursor containing gallium and zinc, can be used.

[0237] Examples of precursors that can be used that contain indium include trimethylindium, triethylindium, tris(2,2,6,6-tetramethyl-3,5-heptanedionate)indium, cyclopentadienylindium, indium(III) chloride, and (3-(dimethylamino)propyl)dimethylindium.

[0238] Furthermore, examples of precursors that can be used that contain gallium include trimethylgallium, triethylgallium, tris(dimethylamido)gallium(III), gallium(III) acetylacetonate, tris(2,2,6,6-tetramethyl-3,5-heptanedionate)gallium, dimethylchlorogallium, diethylchlorogallium, and gallium(III) chloride.

[0239] Furthermore, as a precursor containing zinc, dimethyl zinc, diethyl zinc, zinc bis(2,2,6,6-tetramethyl-3,5-heptanedionate), zinc chloride, etc. can be used.

[0240] Examples of oxidizing agents include ozone (O ３ ), oxygen (O ２ ), water (H ２ O), hydrogen peroxide (H ２ O ２ ) etc. can be used.

[0241] Methods for controlling the composition of the resulting film include adjusting the flow rate ratio of the source gases, the time for which the source gases are flowed, the order in which the source gases are flowed, etc. By adjusting these, it is also possible to form a film whose composition changes continuously. It is also possible to form two or more films with different compositions continuously.

[0242] Here, when a single-crystal or polycrystalline indium oxide film is formed as the semiconductor film 21f, the polycrystalline or single-crystal indium oxide film can be formed directly on the insulating layer 43, the conductive film 24b, and the insulating layer 44, but by using a seed crystal that serves as a crystal nucleus, an indium oxide film with good crystallinity can also be formed.

[0243] For example, as shown in FIG. 17A , in a region X outside the region where the semiconductor device 10 is to be fabricated, a layer 21s serving as a seed crystal is first formed on the insulating layer 44. Then, as shown in FIG. 17B , an indium oxide film is formed as a semiconductor film 21f covering the layer 21s. This allows crystal growth to proceed using the seed crystal as a nucleus, resulting in the formation of a single-crystal or polycrystalline indium oxide film having an orientation corresponding to the crystal orientation of the seed crystal. Furthermore, by forming an indium oxide film in this manner, even if the indium oxide film has a polycrystalline crystal structure, each crystal grain can be uniaxially oriented (including being oriented in a specific direction other than the crystal axis). Therefore, a transistor with superior electrical characteristics and reliability can be realized compared to a polycrystalline film having a disordered crystal orientation.

[0244] The seed crystal layer 21s may be, for example, a metal oxide film having a CAAC structure or an indium oxide film. Alternatively, an insulating film such as a YSZ (yttria-stabilized zirconia) film may be used. The layer 21s may be made of a material having a crystalline structure with a small lattice mismatch with indium oxide. This facilitates homoepitaxial or heteroepitaxial growth using the seed crystal as a crystal nucleus, resulting in the formation of a highly crystalline indium oxide film. The layer 21s may be formed, for example, by forming a crystalline thin film using a method such as ALD, sputtering, or CVD, and then removing unnecessary portions by etching. The layer 21s may be provided singly within the substrate surface, or multiple layers may be provided at approximately equal intervals within the substrate surface. The layer 21s may be removed in the same manner as the metal oxide film in a subsequent etching process of the metal oxide film. Alternatively, the layer 21s may be positioned on a scribe line used when dividing the substrate into individual semiconductor chips, thereby removing the seed crystal during the scribing process.

[0245] After the metal oxide film is formed, it is preferable to perform heat treatment. By performing heat treatment, hydrogen, excess oxygen, or other impurities in the metal oxide film can be eliminated, and high purity can be achieved. Furthermore, the heat treatment can also improve crystallinity. The heat treatment can be performed at a temperature of 120° C. or higher and 300° C. or lower, preferably 120° C. or higher and 250° C. or lower, more preferably 120° C. or higher and 200° C. or lower. The heat treatment can be performed, for example, by using hydrogen (H ２ ) and nitrogen (N ２ ), and hydrogen (H ２ ) and nitrogen (N ２ In this case, the hydrogen flow rate is preferably 3% or more and 15% or less, and more preferably 5% or more and 10% or less.

[0246] The gas used in the heat treatment is preferably highly purified. For example, the amount of moisture contained in the gas used in the heat treatment is set to 1 ppb or less, preferably 0.1 ppb or less, and more preferably 0.05 ppb or less. By performing the heat treatment using a highly purified gas, it is possible to prevent moisture and the like from being incorporated into the metal oxide film as much as possible.

[0247] Although the semiconductor film 21f is shown as a single layer in the drawings, it may have a laminated structure. For example, it may have a two-layer structure formed by the ALD method, a three-layer structure formed by the ALD method, a two-layer structure in which the first layer is formed by the ALD method and the second layer is formed by the sputtering method, or a three-layer structure in which the first layer is formed by the ALD method, the second layer is formed by the sputtering method, and the third layer is formed by the ALD method or the sputtering method. Forming the first layer by the ALD method is preferable because it can suppress mixing, but it can also be formed by the sputtering method. Note that the semiconductor film 21f may have a laminated structure of four or more layers.

[0248] Next, a sacrificial layer 61 and a resist mask 65 are formed ( FIG. 13A ). The sacrificial layer 61 functions as a planarizing film and is provided to suppress variations in the thickness of the resist mask 65. The sacrificial layer 61 may be omitted if unnecessary. The sacrificial layer 61 may be made of an organic or inorganic material formed by a coating method. More specifically, a coating-type insulating film such as an SOC (spin-on-carbon) film or an SOG (spin-on-glass) film may be used. Alternatively, the sacrificial layer 61 may be formed by a film formation method such as a sputtering method or a CVD method. It is preferable that the material used for the sacrificial layer 61 satisfy the following conditions: it can be formed thick, it can be formed or processed vertically, and it is easy to remove (leaving no residue and causing minimal damage to the surface on which it is formed).

[0249] Subsequently, the sacrificial layer 61 and the portion of the semiconductor film 21f that is not covered by the resist mask 65 are removed by etching (FIG. 13B).

[0250] Next, the resist mask 65 and the sacrificial layer 61 are removed. The sacrificial layer 61 can be removed by wet etching or dry etching. After the dry etching, dry cleaning using plasma or wet cleaning using a chemical solution (including acid or alkali) or water (including carbonated water) may be performed.

[0251] Next, a new sacrificial layer 62 is formed (FIG. 13C). The sacrificial layer 62 can be formed by the same method as the sacrificial layer 61.

[0252] Next, a planarization process is performed until the top surface of the insulating layer 43 is exposed ( FIG. 14A ). As a result, the portion of the semiconductor film 21f located above the insulating layer 43 is removed, and the semiconductor film 21f is divided into two at the insulating layer 43. In this manner, the semiconductor layer 21 can be formed. The planarization process can be performed by, for example, CMP or dry etching. Thereafter, the sacrificial layer 62 is removed.

[0253] Subsequently, an insulating film 22f, which will later become the insulating layer 22, is formed to cover the semiconductor layer 21, the insulating layer 43, the insulating layer 44, the conductive layer 24, and the like.

[0254] The insulating film 22f can be formed by a film formation method such as sputtering, ALD, or CVD. It is preferable that the insulating film 22f be provided on the surface of the vertical portion of the semiconductor layer 21 with as uniform a thickness as possible. Therefore, it is particularly preferable to form the insulating film 22f by the ALD method, which is a film formation method with extremely excellent coverage. Note that when the sidewalls of the insulating layer 43 have a tapered shape, the insulating film 22f can be formed by a film formation method such as sputtering or CVD.

[0255] Subsequently, a conductive film 23f is formed to cover the insulating film 22f, and the conductive film 23f will later become the conductive layer 23. The conductive film 23f can be formed by a method such as CVD, ALD, or sputtering. From the viewpoint of coverage, the CVD method is particularly preferable.

[0256] Subsequently, an insulating film 31f is formed to cover the conductive film 23f (FIG. 14B), which will later become the insulating layer 31. The insulating film 31f can be formed by a film formation method such as a sputtering method, an ALD method, or a CVD method.

[0257] Next, insulating film 31f is anisotropically etched to form a pair of insulating layers 31 that are provided along the vertical portions of conductive film 23f and are symmetrically positioned with insulating layer 43 in between. Next, conductive film 23f is anisotropically etched using insulating layer 31 as a mask to form a pair of conductive layers 23 that are symmetrically positioned with insulating layer 43 in between. Next, insulating film 22f is anisotropically etched to form insulating layers 22 that are symmetrically positioned with insulating layer 43 in between. Furthermore, semiconductor layer 21 is etched to divide semiconductor layer 21 ( FIG. 14C ).

[0258] The insulating film 31f, the conductive film 23f, the insulating film 22f, and the semiconductor layer 21 may be etched in order using different etching methods, or two or more films may be etched simultaneously in one etching step. For example, in the etching step of the conductive film 23f, the insulating film 22f may be etched successively under the same conditions after the conductive film 23f.

[0259] Next, an insulating film that will become insulating layer 32 is formed. Next, an insulating film that will become insulating layer 33 is formed so as to fill the recesses in the insulating film. These insulating films can be formed independently by a film formation method such as a sputtering method, an ALD method, or a CVD method. For example, the insulating film that will become insulating layer 32 can be formed by an ALD method, and the insulating film that will become insulating layer 33 can be formed by a CVD method. Next, the insulating film that will become insulating layer 33 and the insulating film that will become insulating layer 32 are anisotropically etched in order to expose the upper surfaces of semiconductor layer 21, insulating layer 22, conductive layer 23, and insulating layer 31.

[0260] Next, an insulating film that will become the insulating layer 34 is formed, and planarization is performed until the top surface of the insulating layer 43 is exposed, thereby forming the insulating layer 34 that contacts the top surfaces of the conductive layer 23, the insulating layer 31, the insulating layer 32, and the insulating layer 33 ( FIG. 15A ). The insulating film that will become the insulating layer 34 can be formed by a film formation method such as a sputtering method, an ALD method, or a CVD method.

[0261] Next, the semiconductor layer 21 is etched so that the upper surface of the semiconductor layer 21 is lower than the upper surface of the conductive layer 23 ( FIG. 15B ). At this time, a recess is formed that is surrounded by the side surfaces of the insulating layer 43, the side surfaces of the insulating layer 22, and the upper surface of the semiconductor layer 21.

[0262] Subsequently, a conductive film 25f that will become the conductive layer 25 and the conductive layer 29 is formed so as to fill the recesses (FIG. 15C). The conductive film 25f can be formed by a film formation method such as a sputtering method, an ALD method, or a CVD method.

[0263] Subsequently, unnecessary portions of the conductive film 25f are removed by etching using photolithography, thereby forming the conductive layer 25 and the conductive layer 29 (FIG. 16A).

[0264] At this point, the capacitor 30 and the transistor 20 can be formed.

[0265] Next, an insulating film that will become the insulating layer 47 is formed and planarized until the upper surfaces of the conductive layers 25 and 29 are exposed, thereby forming the insulating layer 47 ( FIG. 16A ). The insulating film that will become the insulating layer 47 can be formed by a film formation method such as a sputtering method, an ALD method, or a CVD method.

[0266] Subsequently, an insulating layer 48 is formed to cover the conductive layer 25, the conductive layer 29, and the insulating layer 47 (FIG. 16B). The insulating layer 48 can be formed by a film formation method such as a sputtering method, an ALD method, or a CVD method.

[0267] Through the above steps, a semiconductor device including the transistor 20 and the capacitor 30 can be manufactured.

[0268] The above is a description of an example of the manufacturing method.

[0269] This embodiment mode can be implemented by appropriately combining at least a part thereof with other embodiment modes described in this specification.

[0270] Embodiment 2 In this embodiment, an indium oxide film that can be used for a semiconductor layer of a transistor included in a semiconductor device of one embodiment of the present invention will be described.

[0271] In this specification and the like, indium oxide having at least a crystalline portion or a crystalline region in a film is referred to as crystalline indium oxide (crystal IO) or crystalline indium oxide (crystalline IO). Examples of crystalline IO or crystalline IO include single-crystalline indium oxide, polycrystalline indium oxide, and microcrystalline indium oxide.

[0272] Indium oxide is a semiconductor material having physical properties that are completely different from those of oxide semiconductors such as In—Ga—Zn oxide (hereinafter also referred to as IGZO) and zinc oxide.

[0273] The carrier concentration dependence of the Hall mobility of indium oxide, silicon, and IGZO will be explained. FIG. 18A shows the carrier concentration dependence of the Hall mobility of silicon (Si) and indium oxide (InO Ｘ ) and FIG. 18B is a schematic diagram showing the carrier concentration dependence of the hole mobility for IGZO.

[0274] First, IGZO tends to exhibit higher hole mobility as the carrier concentration increases, as shown by the arrows in Figure 18B. On the other hand, indium oxide tends to exhibit higher hole mobility as the carrier concentration decreases, as shown by the arrows in Figure 18A (see Non-Patent Document 1). This trend is similar to that of silicon; the lower the dopant (impurity) concentration in the material, the less impurity scattering there is and the higher the hole mobility. In other words, the higher the purity and intrinsic indium oxide, the higher the hole mobility. From these results, it can be said that indium oxide, unlike IGZO, is a material with physical properties similar to those of silicon. Note that the characteristics of indium oxide shown in Figure 18A are assumed to be single crystal. Therefore, when indium oxide is non-single crystal (e.g., polycrystalline), the characteristics may differ from those shown in Figure 18A.

[0275] 18A, the range R1 of low carrier concentration has extremely high hole mobility, and therefore can be said to be a range of carrier concentration suitable for, for example, a channel formation region of a transistor. For example, in the case of indium oxide, the range R1 is a range where the carrier concentration value is 1×10 １５ cm −３ The range includes, for example, 1×10１４ cm −３ That's it, 1 x 10 １８ cm −３ By sufficiently reducing the carrier concentration, the Hall mobility value can be increased to 270 cm ２ It is expected that the resistance can be increased to about / (V·s).

[0276] In addition, in indium oxide, the region where the carrier concentration is in the range R1 may contain an element that lowers the carrier concentration. Examples of elements that lower the carrier concentration include magnesium, calcium, zinc, cadmium, and copper. By substituting these elements for indium, the carrier concentration can be lowered. Examples of elements that lower the carrier concentration include nitrogen, phosphorus, arsenic, and antimony. For example, by substituting nitrogen, phosphorus, arsenic, or antimony for oxygen, the carrier concentration can be lowered.

[0277] On the other hand, the range R2 with a high carrier concentration has a low electrical resistance, and can be said to be a range of carrier concentrations suitable for, for example, the source and drain regions of a transistor, a resistor, or a transparent conductive film. ２０ cm −３ The range includes, for example, 1×10 １９ cm −３ That's it, 1 x 10 ２２ cm −３ By increasing the carrier concentration sufficiently, the resistivity can be reduced to 1×10 −４ It is expected that the resistivity can be reduced to Ω·cm or less.

[0278] In addition, in indium oxide, the region where the carrier concentration is in the range R2 may contain an element that increases the carrier concentration. For example, it is preferable that the indium oxide contains an element that is common to the source electrode and drain electrode of the transistor. Examples of elements that increase the carrier concentration include titanium, zirconium, hafnium, tantalum, tungsten, molybdenum, tin, silicon, and boron. In particular, it is more preferable to use an element whose oxide has conductive or semiconducting properties. Note that, as a method for supplying an element that increases the carrier concentration, a method of forming a film containing the element and diffusing it, ion implantation, ion doping, plasma immersion ion implantation, or plasma treatment can be used. Note that, unless otherwise specified in this specification, the presence or absence of mass separation is not limited. For example, in this specification, a method of supplying ions after mass separation is referred to as an ion implantation method, and a method of supplying ions without mass separation is referred to as an ion doping method.

[0279] In this way, indium oxide uses a region with a low carrier concentration as the channel formation region of a transistor, and a region with a high carrier concentration as the source and drain regions of the transistor. In other words, indium oxide can be said to be an oxide capable of valence electron control. Note that IGZO may experience strain in the source and drain regions due to stress from electrodes in contact with the IGZO, resulting in the formation of n-type regions. On the other hand, unlike IGZO, indium oxide is capable of valence electron control, and therefore does not require strain to be formed in the film as with IGZO. Less strain in the film is expected to improve reliability. For example, by separately creating a region with a carrier concentration in the range R1 shown in FIG. 18A and a region with a carrier concentration in the range R2 in the indium oxide film, a so-called n-i-n junction (a junction between an n-type region, an i-type region, and an n-type region) can be created. Note that valence electron control in transistors using silicon is generally known. On the other hand, valence electron control in transistors using indium oxide is a novel technical concept that would not normally be conceived.

[0280] By using the above technical concept, the transistor having indium oxide in this specification and the like has two or more, preferably three or more, more preferably four or more, and most preferably five of the following characteristics (1) to (5): (1) high on-current (in other words, high mobility); (2) low off-current; (3) normally-off operation; (4) high reliability; and (5) high cutoff frequency (fT). For example, the transistor having indium oxide in this specification and the like has high mobility, low off-current, and is normally-off operation. The transistor has high mobility and is different from a normally-on transistor.

[0281] In addition, a semiconductor being i-type can be rephrased as having the same Fermi level (Ef) and intrinsic Fermi level (Ei) (Ef = Ei). As shown in FIG. 18B, in IGZO, the lower the carrier concentration, the smaller the hole mobility. Therefore, when Ef = Ei finally occurs, the carriers disappear (in other words, the physical properties become similar to those of an insulator), and there is a possibility that the transistor will no longer function. On the other hand, in indium oxide, as shown in FIG. 18A, the lower the carrier concentration, the higher the hole mobility. When Ef = Ei finally occurs, the hole mobility is maximized. In other words, a transistor containing indium oxide can achieve high field-effect mobility by setting Ef = Ei. Note that a transistor containing indium oxide is likely to be normally-off due to its low carrier concentration. Therefore, a transistor containing indium oxide can be normally-off and achieve high field-effect mobility.

[0282] Note that normally-off refers to a state in which no current flows through a transistor when no potential is applied to the gate or when the gate-source voltage is 0 V. Furthermore, normally-off can be evaluated by the threshold voltage (Vth) or shift value (Vsh) of the transistor. Unless otherwise specified, Vth is calculated by a constant current method. More specifically, Vth refers to a state in which the value of drain current (Id) × channel length (L) ÷ channel width (W) in the Id-Vg characteristics of a transistor is 1 nA (1 × 10 −９ A). Vsh is the gate voltage (Vg) when the drain current (Id) in the Id-Vg characteristic of the transistor is expressed logarithmically and the tangent of the maximum slope is Id = 1 pA (1 × 10 −１２ The gate voltage (Vg) is the intersection point between the line of Id = 1 pA and the line extrapolated from two points where the slope of Id is maximum when Id is expressed logarithmically in the Id-Vg characteristics of the transistor. For example, if either or both of Vth and Vsh are zero or a positive value, the transistor can be considered to be normally-off.

[0283] In addition, in a transistor containing indium oxide, in order to make the semiconductor i-type, that is, to achieve Ef = Ei, the film structure in contact with the indium oxide film is important. For example, in a transistor containing indium oxide, a film structure in which a silicon oxide film in contact with the indium oxide film, a hafnium oxide film, and a silicon nitride film are stacked is exemplified. By using this film structure, a semiconductor device with high reliability and Ef = Ei can be obtained.

[0284] In the above film configuration, a film containing oxygen, such as a silicon oxynitride film, a silicon nitride oxide film, an aluminum oxide film, or a gallium oxide film, can be used instead of the silicon oxide film. Also, in the above film configuration, a silicon nitride oxide film, a silicon oxynitride film, or the like can be used instead of the silicon nitride film. The hafnium oxide film, which is located closer to the indium oxide film than the silicon nitride film, functions as a gettering site for hydrogen.

[0285] The above film configuration can also be considered as a stacked structure of a film (e.g., a silicon oxide film) capable of supplying oxygen to the indium oxide film from the indium oxide film side, a film (e.g., a hafnium oxide film) capable of gettering hydrogen, and a film (e.g., a silicon nitride film) that suppresses the penetration of oxygen and hydrogen. With this configuration, oxygen vacancies in the indium oxide film are filled with oxygen in the silicon oxide film. Hydrogen in the indium oxide film is captured by the hafnium oxide film by heat treatment or the like. Furthermore, the provision of the silicon nitride film results in a film configuration that reduces the penetration of oxygen and hydrogen from the outside. That is, with the above film configuration, the indium oxide film can be made closer to i-type. Therefore, a transistor having the above-described indium oxide film has high field-effect mobility and high reliability.

[0286] Next, an indium oxide film applied to a transistor will be described. The indium oxide film preferably has crystallinity (i.e., has crystal grains). Examples of films having crystal grains include single-crystal films, polycrystalline films, and amorphous films containing crystal grains (also called microcrystalline films). In particular, the indium oxide film is preferably a polycrystalline film, and more preferably a single-crystal film. A single-crystal film does not have grain boundaries. Impurities (typically, insulating impurities, insulating oxides, etc.) that hinder carrier flow tend to segregate at grain boundaries. The use of a single-crystal film can suppress carrier scattering at grain boundaries, thereby realizing a transistor exhibiting high field-effect mobility. Furthermore, the use of a single-crystal film has the excellent effect of suppressing variations in transistor characteristics due to the grain boundaries.

[0287] Furthermore, polycrystalline films are preferable because they can reduce carrier scattering and exhibit high field-effect mobility compared to microcrystalline or amorphous films. When using a polycrystalline film, it is preferable to use a film with as large a crystal grain size as possible and with few crystal grain boundaries. Note that in a transistor using an indium oxide polycrystalline film, if there is no crystal grain boundary in the channel formation region or no crystal grain boundary is observed, the channel formation region is located within a single crystal region included in the polycrystalline film, and therefore the transistor can be considered to be using single-crystal indium oxide.

[0288] The crystallinity of indium oxide can be analyzed by, for example, X-ray diffraction (XRD), transmission electron microscopy (TEM), or electron diffraction (ED). Alternatively, the analysis may be performed by combining a plurality of these techniques.

[0289] In this specification and the like, a semiconductor layer in which no crystal grain boundary is observed in the channel formation region, a semiconductor layer in which the channel formation region is included in one crystal grain, or a semiconductor layer in which the crystal axis direction is the same in at least two regions in the channel formation region can be called a single crystal film. Also, a semiconductor layer in which, in the channel formation region, within one crystal grain, the direction of another crystal axis continuously changes around a certain crystal axis or a certain crystal orientation as the axis of rotation can be called a single crystal film.

[0290] The channel formation region refers to a region of the semiconductor layer that overlaps (or faces) the gate electrode via the gate insulating layer, and is located between the region in contact with the source electrode and the region in contact with the drain electrode. The current path in the channel formation region is the shortest distance between the source electrode and the drain electrode. Therefore, the crystal grains, crystal grain boundaries, crystal axes, crystal orientation, etc. in the channel formation region can be confirmed by observing a cross section including the semiconductor layer, the source electrode, and the drain electrode.

[0291] The indium oxide film in the channel formation region preferably has a lower impurity concentration. Impurities in the indium oxide film in the channel formation region can be a scattering source of carriers, which can lead to a decrease in field-effect mobility. These impurities can also hinder the crystal growth of the indium oxide film. Examples of impurities in the indium oxide film include boron and silicon. The indium oxide film preferably contains these impurities at concentrations of 0.1% or less, and more preferably 0.01% (100 ppm) or less. Carbon, hydrogen, and other elements may be contained in the film-forming gas or precursor during film formation, and may remain in the indium oxide film in greater amounts than the above-mentioned impurities.

[0292] The indium oxide film in the channel formation region may contain an element that can become the same trivalent cation as indium, as long as the crystal maintains a cubic crystal structure (bixbyite type). Examples of such an element include Group 13 elements of the periodic table, such as gallium and aluminum, and Group 3 elements of the periodic table. These elements exist mainly as trivalent cations in oxides, and therefore the carrier concentration of indium oxide can be maintained low.

[0293] By using such an indium oxide film in a transistor, the field effect mobility of the transistor can be increased to 50 cm ２ / (V·s) or more, preferably 100 cm ２ / (V·s) or more, more preferably 150 cm ２ / (V·s) or more, more preferably 200 cm ２ / (V·s) or more, more preferably 250 cm ２ / (V·s) or more.

[0294] One of the features of an indium oxide film is that it has higher oxygen permeability (diffusibility) than an IGZO film. As shown in FIG. 18C, an indium oxide film (InO Ｘ Oxygen (O) diffusing into the indium oxide film passes through the indium oxide film and becomes oxygen molecules (O ２ ) and is released as water molecules (H ２O) in the film. Ｏ In the case where an indium oxide film is present, oxygen atoms diffuse to compensate for the oxygen vacancies. Since oxygen diffuses easily in the indium oxide film, it can be said that oxygen vacancies are more easily compensated for in the indium oxide film than in the IGZO film.

[0295] As described above, an indium oxide film can more easily reduce oxygen vacancies in the film than an IGZO film. Therefore, by using such an indium oxide film in a transistor, a transistor with extremely high reliability can be realized.

[0296] Furthermore, as shown in FIG. 18C, the indium oxide film diffuses hydrogen. Hydrogen that diffuses into the indium oxide film from the outside passes through the indium oxide film and becomes hydrogen molecules (H ２ ) or reacts with oxygen contained in the membrane and is released as water molecules.

[0297] A transistor using an indium oxide film is an accumulation-type transistor that uses electrons as majority carriers. Assuming that the carrier relaxation time is constant, the smaller the effective mass of the electrons (carriers), the higher the electron mobility. In other words, by using indium oxide, which has a small effective mass of electrons, for a transistor, the on-state current or field-effect mobility of the transistor can be increased.

[0298] Table 1 shows the results of single crystal indium oxide (here, In ２ O ３ ) and single-crystal silicon (Si). As shown in Table 1, indium oxide is characterized by a small effective mass of electrons and a large effective mass of holes. Indium oxide also has the characteristic that the effective mass of electrons is almost independent of the crystal orientation. Therefore, by using crystalline indium oxide in a transistor, a transistor with high field-effect mobility and high frequency characteristics (also called f characteristics) can be realized. Furthermore, since the effective mass of holes is large, a transistor with extremely small off-current can be realized. For example, by applying an indium oxide film to a vertical transistor, the off-current per 1 μm of channel width can be reduced to 1 fA (1×10) in an environment of 125° C.−１５ A) or less, or 1aA (1 x 10 −１８ A) or less, and under room temperature (25°C) conditions, −１８ A) or less, or 1zA (1 x 10 −２１ Furthermore, as shown in Table 1, indium oxide has a smaller effective mass of electrons and a larger effective mass of holes than silicon, and therefore may be able to realize a transistor with higher field-effect mobility and lower off-state current than a Si transistor.

[0299]

[0300] It is preferable to provide a seed layer so as to be in contact with at least a portion of the crystalline indium oxide film. The seed layer is preferably made of a material containing crystals with a small difference in lattice constant (also called lattice mismatch) with indium oxide. This can improve the crystallinity of the indium oxide film. Note that a substrate (e.g., a single-crystal substrate) may be used as one of the layers in contact with at least a portion of the crystalline indium oxide film.

[0301] One method for evaluating the degree of lattice mismatch is to use the value of the lattice mismatch shown below. The lattice mismatch Δa [%] of the crystals of the formed film (here, the indium oxide film) with respect to the crystals of the seed layer is expressed as Δa = ((L １ -L ２ ) / L ２ ) × 100, where L １ is the length or lattice constant of the unit lattice vector of the crystal of the formed film, and L ２ is the length of the unit cell vector or the lattice constant of the crystal of the seed layer.

[0302] The smaller the absolute value of the lattice mismatch Δa between the seed layer and the indium oxide film, the more preferable, and it is most preferably 0. For example, Δa can be set to −5% or more and 5% or less, preferably −4% or more and 4% or less, more preferably −3% or more and 3% or less, and even more preferably −2% or more and 2% or less.

[0303] Here, the indium oxide crystal has a cubic crystal structure (bixbyite type). For example, the crystal of yttria-stabilized zirconia (YSZ) can have a cubic crystal structure (fluorite type). The lattice mismatch of the indium oxide crystal with the cubic YSZ crystal is in the range of −2% to 2%, and a single crystal film of indium oxide can be epitaxially grown on the YSZ substrate.

[0304] It should be noted that the crystal structure of the seed layer and the crystal structure of the indium oxide film may not necessarily have the same crystal system or crystal orientation. For example, a film having crystals of a hexagonal or trigonal structure may be used under an indium oxide film having crystals of a cubic structure. For example, by setting the crystal orientation of the surface of the seed layer to

[001] and the crystal orientation of the underside of the indium oxide film to

[111] , the requirements related to the crystal orientation necessary for epitaxial growth can be satisfied. Examples of hexagonal or trigonal crystals include wurtzite structure, YbFe ２ O ４ Type structure, Yb ２ Fe ３ O ７ YbFeFe alloys have the following structures: ２ O ４ Type structure or Yb ２ Fe ３ O ７ An example of a crystal having a crystalline structure is IGZO. It should be noted that a single crystal film of indium oxide can be formed not only on a YSZ substrate but also on an insulating film. On the other hand, it is difficult to form a single crystal film of silicon on an insulating film. Silicon crystals have a diamond structure. As such, indium oxide and silicon have similar properties in terms of single crystal. However, when comparing indium oxide and silicon in terms of whether they can be formed as single crystals on an insulating film, they have different properties.

[0305] This embodiment mode can be implemented by appropriately combining at least a part thereof with other embodiment modes described in this specification.

[0306] Embodiment 3 In this embodiment, a semiconductor device 900 according to one embodiment of the present invention, which is different from the above embodiment, will be described. The semiconductor device 900 can function as a memory device.

[0307] Fig. 19 is a block diagram showing a configuration example of a semiconductor device 900. The semiconductor device 900 shown in Fig. 19 has a driver circuit 910 and a memory array 920. The memory array 920 has one or more memory cells 950. Fig. 19 shows an example in which the memory array 920 has a plurality of memory cells 950 arranged in a matrix.

[0308] The memory cell 15 exemplified in the above embodiment can be applied to the memory cell 950 .

[0309] The drive circuit 910 includes a PSW 931 (power switch), a PSW 932, and a peripheral circuit 915. The peripheral circuit 915 includes a peripheral circuit 911, a control circuit 912, and a voltage generation circuit 928.

[0310] In the semiconductor device 900, each circuit, signal, and voltage can be appropriately selected or omitted as needed. Alternatively, other circuits or signals may be added. The signals BW, CE, GW, CLK, WAKE, ADDR, WDA, PON1, and PON2 are input signals from the outside, and the signal RDA is an output signal to the outside. The signal CLK is a clock signal.

[0311] Furthermore, signals BW, CE, and GW are control signals. Signal CE is a chip enable signal, signal GW is a global write enable signal, and signal BW is a byte write enable signal. Signal ADDR is an address signal. Signal WDA is a write data signal, and signal RDA is a read data signal. Signals PON1 and PON2 are power gating control signals. Note that signals PON1 and PON2 may be generated by the control circuit 912.

[0312] The control circuit 912 is a logic circuit having a function of controlling the overall operation of the semiconductor device 900. For example, the control circuit 912 performs a logical operation on the signals CE, GW, and BW to determine the operation mode (e.g., write operation, read operation) of the semiconductor device 900. Alternatively, the control circuit 912 generates a control signal for the peripheral circuit 911 so that this operation mode is executed.

[0313] The voltage generating circuit 928 has a function of generating a negative voltage. The signal WAKE has a function of controlling the input of the signal CLK to the voltage generating circuit 928. For example, when an H-level signal is given as the signal WAKE, the signal CLK is input to the voltage generating circuit 928, and the voltage generating circuit 928 generates a negative voltage.

[0314] The peripheral circuit 911 is a circuit for writing and reading data to and from the memory cells 950. The peripheral circuit 911 includes a row decoder 941, a column decoder 942, a row driver 923, a column driver 924, an input circuit 925, an output circuit 926, and a sense amplifier 927.

[0315] The row decoder 941 and the column decoder 942 have the function of decoding the signal ADDR. The row decoder 941 is a circuit for specifying a row to be accessed, and the column decoder 942 is a circuit for specifying a column to be accessed. The row driver 923 has the function of selecting the row specified by the row decoder 941. The column driver 924 has the function of writing data to the memory cells 950, reading data from the memory cells 950, and retaining the read data.

[0316] The input circuit 925 has a function of holding a signal WDA. The data held by the input circuit 925 is output to the column driver 924. The output data of the input circuit 925 is data (Din) to be written to the memory cell 950. The data (Dout) read from the memory cell 950 by the column driver 924 is output to the output circuit 926. The output circuit 926 has a function of holding Dout. In addition, the output circuit 926 has a function of outputting Dout to the outside of the semiconductor device 900. The data output from the output circuit 926 is a signal RDA.

[0317] The PSW 931 has a function of controlling the supply of VDD to the peripheral circuit 915. The PSW 932 has a function of controlling the supply of VHM to the row driver 923. In this example, the high power supply voltage of the semiconductor device 900 is VDD, and the low power supply voltage is GND (ground potential). VHM is a high power supply voltage used to set the word line to a high level and is higher than VDD. The on / off of the PSW 931 is controlled by a signal PON1, and the on / off of the PSW 932 is controlled by a signal PON2. In FIG. 19 , the number of power domains to which VDD is supplied in the peripheral circuit 915 is one, but multiple domains may also be used. In this case, a power switch may be provided for each power domain.

[0318] 20A to 20H, other examples of memory cell configurations that can be applied to the memory cell 950 will be described.

[0319] In the following, when two components are described as being connected, this includes being electrically connected via a circuit element (such as a transistor, a switch, a diode, or a resistor). Electrical connection means that a current can flow between the two components. Note that when two components are connected via a switch or a transistor, this is also included in the term "electrical connection," because a current can flow when these are in the on state.

[0320] 20A shows an example of a circuit configuration of a DRAM memory cell. In this specification and the like, a DRAM using an OS transistor is referred to as a DOSRAM (Dynamic Oxide Semiconductor Random Access Memory). The memory cell 951 includes a transistor M1 and a capacitor CA.

[0321] The transistor M1 may have a front gate (sometimes simply referred to as a gate) and a back gate. In this case, the back gate may be connected to a wiring that supplies a constant potential or a signal, or the front gate and the back gate may be connected to each other.

[0322] A first terminal of the transistor M1 is connected to a first terminal of the capacitance element CA, a second terminal of the transistor M1 is connected to the wiring BIL, and a gate of the transistor M1 is connected to the wiring WOL. The second terminal of the capacitance element CA is connected to the wiring CAL.

[0323] The wiring BIL functions as a bit line, and the wiring WOL functions as a word line. The wiring CAL functions as a wiring for applying a predetermined potential to the second terminal of the capacitance element CA. When writing and reading data, it is preferable to apply a low-level potential (sometimes referred to as a reference potential) to the wiring CAL.

[0324] Data is written and read by applying a high-level potential to the wiring WOL, turning on the transistor M1, and bringing the wiring BIL and the first terminal of the capacitor CA into a conductive state (a state in which current can flow).

[0325] Furthermore, the memory cell that can be used as the memory cell 950 is not limited to the memory cell 951, and the circuit configuration can be changed. For example, the memory cell 950 can have the configuration of a memory cell 952 as shown in FIG. 20B. The memory cell 952 is an example in which the memory cell 952 does not include a capacitor CA and a wiring CAL. The first terminal of the transistor M1 is in an electrically floating state.

[0326] In the memory cell 952, the potential written through the transistor M1 is held in a capacitance (also referred to as a parasitic capacitance) between the first terminal and the gate, which is indicated by a dashed line. With this configuration, the configuration of the memory cell can be significantly simplified.

[0327] Note that an OS transistor is preferably used as the transistor M1. An OS transistor has a characteristic of extremely low off-state current. By using an OS transistor as the transistor M1, the leakage current of the transistor M1 can be significantly reduced. That is, written data can be held by the transistor M1 for a long time, so that the frequency of refreshing the memory cell can be reduced. Alternatively, the refresh operation of the memory cell can be eliminated. Furthermore, because the leakage current is extremely low, multilevel data or analog data can be held in the memory cell 951 and the memory cell 952.

[0328] 20C shows an example circuit configuration of a gain cell type memory cell having two transistors and one capacitor. The memory cell 953 includes a transistor M2, a transistor M3, and a capacitor CB. In this specification and the like, a storage device having a gain cell type memory cell in which the transistor M2 is an OS transistor is referred to as a nonvolatile oxide semiconductor RAM (NOSRAM).

[0329] The first terminal of transistor M2 is connected to the first terminal of capacitance element CB, the second terminal of transistor M2 is connected to wiring WBL, and the gate of transistor M2 is connected to wiring WOL. The second terminal of capacitance element CB is connected to wiring CAL. The first terminal of transistor M3 is connected to wiring RBL, the second terminal of transistor M3 is connected to wiring SL, and the gate of transistor M3 is connected to the first terminal of capacitance element CB.

[0330] The wiring WBL functions as a write bit line, the wiring RBL functions as a read bit line, and the wiring WOL functions as a word line. The wiring CAL functions as a wiring for applying a predetermined potential to the second terminal of the capacitance element CB. When writing data, while retaining data, and when reading data, it is preferable to apply a low-level potential (sometimes referred to as a reference potential) to the wiring CAL.

[0331] Data is written by applying a high-level potential to the wiring WOL, turning on the transistor M2, and establishing electrical continuity between the wiring WBL and the first terminal of the capacitor CB. Specifically, when the transistor M2 is on, a potential corresponding to the information to be recorded is applied to the wiring WBL, and the potential is written to the first terminal of the capacitor CB and the gate of the transistor M3. Then, a low-level potential is applied to the wiring WOL, turning off the transistor M2, thereby maintaining the potential of the first terminal of the capacitor CB and the potential of the gate of the transistor M3.

[0332] Data is read by applying a predetermined potential to the wiring SL. The current flowing between the source and drain of the transistor M3 and the potential of the first terminal of the transistor M3 are determined by the potential of the gate of the transistor M3 and the potential of the second terminal of the transistor M3. Therefore, the potential held in the first terminal of the capacitor CB (or the gate of the transistor M3) can be read by reading the potential of the wiring RBL connected to the first terminal of the transistor M3. In other words, information written in this memory cell can be read from the potential held in the first terminal of the capacitor CB (or the gate of the transistor M3).

[0333] Alternatively, for example, the wiring WBL and the wiring RBL may be combined into a single wiring BIL. An example circuit configuration of such a memory cell is shown in FIG. 20D . The memory cell 954 is configured such that the wiring WBL and the wiring RBL of the memory cell 953 are combined into a single wiring BIL, and the second terminal of the transistor M2 and the first terminal of the transistor M3 are connected to the wiring BIL. In other words, the memory cell 954 is configured to operate as a write bit line and a read bit line using a single wiring BIL.

[0334] 20E is an example in which the capacitor element CB and the wiring CAL are omitted from the memory cell 953. Also, the memory cell 956 shown in Fig. 20F is an example in which the capacitor element CB and the wiring CAL are omitted from the memory cell 954. With such a configuration, the integration degree of the memory cells can be increased.

[0335] Note that at least the transistor M2 is preferably an OS transistor, and in particular, the transistors M2 and M3 are preferably OS transistors.

[0336] Since the OS transistor has an extremely low off-state current, written data can be held by the transistor M2 for a long time, which reduces the frequency of refreshing the memory cell. Alternatively, the refresh operation of the memory cell can be eliminated. Furthermore, since the leakage current is extremely low, multilevel data or analog data can be held in the memory cell 953, the memory cell 954, the memory cell 955, and the memory cell 956.

[0337] The memory cell 953, the memory cell 954, the memory cell 955, and the memory cell 956, in which an OS transistor is used as the transistor M2, are one embodiment of an NOSRAM.

[0338] Note that a Si transistor may be used as the transistor M3. The Si transistor can increase the field effect mobility and can also be used as a p-channel transistor, thereby increasing the degree of freedom in circuit design.

[0339] When an OS transistor is used as the transistor M3, the memory cell can be configured using only n-channel transistors.

[0340] 20G shows a three-transistor, one-capacitor gain cell type memory cell 957. The memory cell 957 has transistors M4 to M6 and a capacitor CC.

[0341] The first terminal of transistor M4 is connected to the first terminal of capacitor CC, the second terminal of transistor M4 is connected to wiring BIL, and the gate of transistor M4 is connected to wiring WOL. The second terminal of capacitor CC is connected to the first terminal of transistor M5 and wiring GNDL. The second terminal of transistor M5 is connected to the first terminal of transistor M6, and the gate of transistor M5 is connected to the first terminal of capacitor CC. The second terminal of transistor M6 is connected to wiring BIL, and the gate of transistor M6 is connected to wiring RWL.

[0342] The wiring BIL functions as a bit line, the wiring WOL functions as a write word line, and the wiring RWL functions as a read word line. The wiring GNDL is a wiring that applies a low-level potential.

[0343] Data is written by applying a high-level potential to the wiring WOL, turning on the transistor M4, and establishing electrical continuity between the wiring BIL and the first terminal of the capacitor CC. Specifically, when the transistor M4 is on, a potential corresponding to the information to be recorded is applied to the wiring BIL, and the potential is written to the first terminal of the capacitor CC and the gate of the transistor M5. Then, a low-level potential is applied to the wiring WOL, turning off the transistor M4, thereby maintaining the potential of the first terminal of the capacitor CC and the potential of the gate of the transistor M5.

[0344] Data is read by precharging the wiring BIL to a predetermined potential, then electrically floating the wiring BIL, and applying a high-level potential to the wiring RWL. Because the wiring RWL is at a high-level potential, the transistor M6 is turned on, and the wiring BIL and the second terminal of the transistor M5 are electrically connected. At this time, the potential of the wiring BIL is applied to the second terminal of the transistor M5. The potential of the second terminal of the transistor M5 and the potential of the wiring BIL change depending on the potential held in the first terminal of the capacitor CC (or the gate of the transistor M5). By reading the potential of the wiring BIL, the potential held in the first terminal of the capacitor CC (or the gate of the transistor M5) can be read. In other words, information written in this memory cell can be read from the potential held in the first terminal of the capacitor CC (or the gate of the transistor M5).

[0345] Note that at least the transistor M4 is preferably an OS transistor.

[0346] Note that Si transistors may be used as the transistors M5 and M6. As described above, Si transistors may have higher field-effect mobility than OS transistors depending on the crystalline state of silicon used in the semiconductor layer.

[0347] When OS transistors are used as the transistors M5 and M6, the memory cell can be configured using only n-channel transistors.

[0348] [OS-SRAM] Figure 20H shows an example of an SRAM (Static Random Access Memory) using an OS transistor. In this specification and the like, an SRAM using an OS transistor is referred to as an OS-SRAM (Oxide Semiconductor-SRAM). Note that a memory cell 958 shown in Figure 20H is a memory cell of an SRAM that can be backed up.

[0349] The memory cell 958 includes transistors M7 to M10, transistors MS1 to MS4, and capacitors CD1 and CD2. Note that the transistors MS1 and MS2 are p-channel transistors, and the transistors MS3 and MS4 are n-channel transistors.

[0350] A first terminal of transistor M7 is connected to wiring BIL, and a second terminal of transistor M7 is connected to a first terminal of transistor MS1, a first terminal of transistor MS3, the gate of transistor MS2, the gate of transistor MS4, and a first terminal of transistor M10. The gate of transistor M7 is connected to wiring WOL. A first terminal of transistor M8 is connected to wiring BILB, and a second terminal of transistor M8 is connected to a first terminal of transistor MS2, the first terminal of transistor MS4, the gate of transistor MS1, the gate of transistor MS3, and a first terminal of transistor M9. The gate of transistor M8 is connected to wiring WOL.

[0351] A second terminal of the transistor MS1 is connected to the wiring VDL. A second terminal of the transistor MS2 is connected to the wiring VDL. A second terminal of the transistor MS3 is connected to the wiring GNDL. A second terminal of the transistor MS4 is connected to the wiring GNDL.

[0352] A second terminal of the transistor M9 is connected to a first terminal of the capacitor CD1, and a gate of the transistor M9 is connected to the wiring BRL. A second terminal of the transistor M10 is connected to a first terminal of the capacitor CD2, and a gate of the transistor M10 is connected to the wiring BRL.

[0353] A second terminal of the capacitance element CD1 is connected to the wiring GNDL, and a second terminal of the capacitance element CD2 is connected to the wiring GNDL.

[0354] The wirings BIL and BILB function as bit lines, the wiring WOL functions as a word line, and the wiring BRL is a wiring that controls the on / off states of the transistors M9 and M10.

[0355] The wiring VDL is a wiring that applies a high-level potential, and the wiring GNDL is a wiring that applies a low-level potential.

[0356] Data is written by applying a high-level potential to the wiring WOL and a high-level potential to the wiring BRL. Specifically, when the transistor M10 is on, a potential corresponding to information to be written is applied to the wiring BIL, and the potential is written to the second terminal of the transistor M10.

[0357] Since the memory cell 958 includes an inverter loop formed by the transistors MS1 and MS2, an inverted signal of the data signal corresponding to the potential is input to the second terminal of the transistor M8. Because the transistor M8 is on, the potential applied to the wiring BIL, i.e., the inverted signal of the signal input to the wiring BIL, is output to the wiring BILB. Because the transistors M9 and M10 are on, the potentials of the second terminals of the transistors M7 and M8 are held in the first terminals of the capacitors CD2 and CD1, respectively. Then, a low-level potential is applied to the wiring WOL and a low-level potential is applied to the wiring BRL to turn off the transistors M7 to M10, thereby holding the potentials of the first terminals of the capacitors CD1 and CD2.

[0358] The data read will be described below. First, the wirings BIL and BILB are precharged to a predetermined potential. Next, a high-level potential is applied to the wiring WOL, and a high-level potential is applied to the wiring BRL. At this time, the potential of the first terminal of the capacitor CD1 is refreshed by the inverter loop of the memory cell 958 and output to the wiring BILB. The potential of the first terminal of the capacitor CD2 is also refreshed by the inverter loop of the memory cell 958 and output to the wiring BIL. Since the potentials of the wirings BIL and BILB change from the precharged potentials to the potentials of the first terminals of the capacitor CD2 and the first terminals of the capacitor CD1, respectively, the potential held in the memory cell can be read from the potential of the wiring BIL or the wiring BILB.

[0359] Note that OS transistors are preferably used as the transistors M7 to M10. This allows written data to be held by the transistors M7 to M10 for a long time, which reduces the frequency of refreshing the memory cells. Alternatively, refreshing the memory cells can be eliminated.

[0360] Note that Si transistors may be used as the transistors MS1 to MS4.

[0361] The driver circuit 910 and memory array 920 of the semiconductor device 900 may be provided on the same plane. Alternatively, as shown in FIG. 21A, the driver circuit 910 and memory array 920 may be provided overlapping each other. By providing the driver circuit 910 and memory array 920 overlapping each other, the signal propagation distance can be shortened. Alternatively, as shown in FIG. 21B, the memory array 920 may be provided in multiple layers on the driver circuit 910.

[0362] Next, an example of a processing unit that can include a semiconductor device such as the memory device will be described.

[0363] 22 shows a block diagram of the arithmetic device 960. The arithmetic device 960 shown in FIG. 22 can be applied to, for example, a CPU (Central Processing Unit). The arithmetic device 960 can also be applied to processors such as a GPU (Graphics Processing Unit), a TPU (Tensor Processing Unit), or an NPU (Neural Processing Unit) that have a larger number (several tens to several hundreds) of processor cores capable of parallel processing than a CPU.

[0364] The arithmetic device 960 shown in FIG. 22 has an ALU 991 (ALU: Arithmetic logic unit, arithmetic circuit), an ALU controller 992, an instruction decoder 993, an interrupt controller 994, a timing controller 995, a register 996, a register controller 997, a bus interface 998, a cache 999, and a cache interface 989 on a substrate 990. The substrate 990 may be a semiconductor substrate, an SOI substrate, a glass substrate, or the like. It may also have a rewritable ROM and a ROM interface. The cache 999 and the cache interface 989 may also be provided on separate chips.

[0365] The cache 999 is connected to a main memory provided on a separate chip via a cache interface 989. The cache interface 989 has a function of supplying part of the data held in the main memory to the cache 999. The cache interface 989 also has a function of outputting part of the data held in the cache 999 to the ALU 991, register 996, etc. via the bus interface 998.

[0366] As will be described later, a memory array 920 can be provided by stacking it on the arithmetic unit 960. The memory array 920 can be used as a cache. In this case, the cache interface 989 may have a function of supplying data held in the memory array 920 to the cache 999. In this case, it is preferable that a drive circuit 910 be included as part of the cache interface 989.

[0367] It is also possible to use only the memory array 920 as a cache without providing the cache 999 .

[0368] The arithmetic device 960 shown in FIG. 22 is merely an example of a simplified configuration, and actual arithmetic devices 960 have a wide variety of configurations depending on their applications. For example, it is preferable to use a configuration including the arithmetic device 960 shown in FIG. 22 as one core, and to include multiple such cores, each of which operates in parallel, in a so-called multi-core configuration. The greater the number of cores, the higher the computational performance. The greater the number of cores, for example, two, preferably four, more preferably eight, even more preferably twelve, and even more preferably sixteen or more. Furthermore, when extremely high computational performance is required, such as for server applications, a multi-core configuration with 16 or more, preferably 32 or more, and even more preferably 64 or more cores is preferable. Furthermore, the number of bits that the arithmetic device 960 can handle via its internal computation circuit, data bus, etc. can be, for example, 8 bits, 16 bits, 32 bits, or 64 bits.

[0369] An instruction input to the arithmetic unit 960 via the bus interface 998 is input to the instruction decoder 993, decoded, and then input to the ALU controller 992, interrupt controller 994, register controller 997, and timing controller 995.

[0370] The ALU controller 992, interrupt controller 994, register controller 997, and timing controller 995 perform various controls based on the decoded instructions. Specifically, the ALU controller 992 generates signals for controlling the operation of the ALU 991. Furthermore, the interrupt controller 994 determines and processes interrupt requests from external input / output devices, peripheral circuits, etc. based on their priority, mask status, etc. while the arithmetic unit 960 is executing a program. The register controller 997 generates addresses for registers 996 and performs read and write operations on the registers 996 depending on the state of the arithmetic unit 960.

[0371] Furthermore, the timing controller 995 generates signals that control the timing of the operations of the ALU 991, the ALU controller 992, the instruction decoder 993, the interrupt controller 994, and the register controller 997. For example, the timing controller 995 includes an internal clock generation unit that generates an internal clock signal based on a reference clock signal, and supplies the internal clock signal to the various circuits described above.

[0372] 22, the register controller 997 selects the holding operation of the register 996 in accordance with an instruction from the ALU 991. That is, it selects whether the memory cells of the register 996 will hold data using flip-flops or using capacitive elements. If holding data using flip-flops is selected, a power supply voltage is supplied to the memory cells in the register 996. If holding data using capacitive elements is selected, the data is rewritten to the capacitive elements, and the supply of power supply voltage to the memory cells in the register 996 can be stopped.

[0373] The memory array 920 and the arithmetic unit 960 can be provided overlapping each other. Figures 23A and 23B show perspective views of a semiconductor device 970A. The semiconductor device 970A has a layer 930 on which memory arrays are provided above the arithmetic unit 960. The layer 930 is provided with memory arrays 920L1, 920L2, and 920L3. The arithmetic unit 960 and each memory array have overlapping regions. To make the configuration of the semiconductor device 970A easier to understand, the arithmetic unit 960 and the layer 930 are shown separately in Figure 23B.

[0374] By stacking the layer 930 having the memory array and the arithmetic unit 960, the connection distance between them can be shortened, thereby increasing the communication speed between them. In addition, the short connection distance reduces power consumption.

[0375] As a method for stacking the layer 930 having a memory array and the arithmetic device 960, a method (also called monolithic stacking) in which the layer 930 having a memory array is stacked directly on the arithmetic device 960 may be used, or a method in which the arithmetic device 960 and the layer 930 are formed on different substrates, and the two substrates are bonded together and connected using a through-via or conductive film bonding technology (such as Cu-Cu bonding) may be used. The former method does not require consideration of misalignment during bonding, and therefore can not only reduce the chip size but also reduce manufacturing costs.

[0376] Here, the arithmetic unit 960 does not have a cache 999, and the memory arrays 920L1, 920L2, and 920L3 provided in the layer 930 can each be used as a cache. In this case, for example, the memory array 920L1 can be used as an L1 cache (also referred to as a level 1 cache), the memory array 920L2 can be used as an L2 cache (also referred to as a level 2 cache), and the memory array 920L3 can be used as an L3 cache (also referred to as a level 3 cache). Of the three memory arrays, the memory array 920L3 has the largest capacity and the lowest access frequency. Furthermore, the memory array 920L1 has the smallest capacity and the highest access frequency.

[0377] When the cache 999 provided in the arithmetic unit 960 is used as an L1 cache, each memory array provided in the layer 930 can be used as a lower-level cache or a main memory. The main memory has a larger capacity than the cache and is accessed less frequently.

[0378] 23B, a driving circuit 910L1, a driving circuit 910L2, and a driving circuit 910L3 are provided. The driving circuit 910L1 is connected to the memory array 920L1 via a connection electrode 940L1. Similarly, the driving circuit 910L2 is connected to the memory array 920L2 via a connection electrode 940L2, and the driving circuit 910L3 is connected to the memory array 920L3 via a connection electrode 940L3.

[0379] Although the number of memory arrays functioning as caches is three in this example, the number may be one or two, or four or more.

[0380] When the memory array 920L1 is used as a cache, the driver circuit 910L1 may function as part of the cache interface 989, or may be configured to be connected to the cache interface 989. Similarly, the driver circuits 910L2 and 910L3 may also function as part of the cache interface 989, or may be configured to be connected thereto.

[0381] Whether the memory array 920 is made to function as a cache or as a main memory is determined by a control circuit 912 included in each drive circuit 910. The control circuit 912 can cause some of the memory cells 950 included in the semiconductor device 900 to function as RAM based on a signal supplied from the arithmetic device 960.

[0382] The semiconductor device 900 can cause some of the memory cells 950 to function as a cache and the other memory cells to function as a main memory. That is, the semiconductor device 900 can function as both a cache and a main memory. The semiconductor device 900 according to one embodiment of the present invention can function as, for example, a universal memory.

[0383] Furthermore, a layer 930 having one memory array 920 may be provided over the arithmetic device 960. Figure 24A shows a perspective view of a semiconductor device 970B.

[0384] In the semiconductor device 970B, one memory array 920 can be divided into multiple areas, each of which can be used for a different function. Figure 24A shows an example in which area L1 is used as an L1 cache, area L2 is used as an L2 cache, and area L3 is used as an L3 cache.

[0385] Furthermore, in the semiconductor device 970B, the capacity of each of the areas L1 to L3 can be changed depending on the situation. For example, if it is desired to increase the capacity of the L1 cache, this can be achieved by increasing the area of ​​the area L1. This configuration can improve the efficiency of calculation processing and increase the processing speed.

[0386] Also, multiple memory arrays may be stacked. Figure 24B shows a perspective view of a semiconductor device 970C.

[0387] The semiconductor device 970C includes a layer 930L1 having a memory array 920L1, a layer 930L2 having a memory array 920L2 on top of that, and a layer 930L3 having a memory array 920L3 on top of that. The memory array 920L1, which is physically closest to the arithmetic unit 960, can be used as a higher-level cache, and the memory array 920L3, which is farthest, can be used as a lower-level cache or main memory. This configuration allows the capacity of each memory array to be increased, thereby further improving processing power.

[0388] This embodiment mode can be implemented by appropriately combining at least a part thereof with other embodiment modes described in this specification.

[0389] Embodiment 4 In this embodiment, an application example of a semiconductor device of one embodiment of the present invention will be described. The semiconductor device of one embodiment of the present invention can be used for, for example, electronic components, electronic devices, mainframes, space equipment, and data centers (also referred to as data centers (DCs)). Electronic components, electronic devices, mainframes, space equipment, and data centers using the semiconductor device of one embodiment of the present invention are effective in achieving high performance, such as low power consumption.

[0390] [Electronic Component] FIG. 25A shows a perspective view of a substrate (mounting substrate 704) on which electronic component 700 is mounted. Electronic component 700 shown in FIG. 25A has semiconductor device 710 inside mold 711. FIG. 25A omits some parts to show the interior of electronic component 700. Electronic component 700 has lands 712 on the outside of mold 711. Lands 712 are electrically connected to electrode pads 713, and electrode pads 713 are electrically connected to semiconductor device 710 via wires 714. Electronic component 700 is mounted on, for example, a printed circuit board 702. A plurality of such electronic components are combined and electrically connected on printed circuit board 702 to complete mounting substrate 704.

[0391] The semiconductor device 710 also includes a drive circuit layer 715 and a memory layer 716. The memory layer 716 has a configuration in which multiple memory cell arrays are stacked. The stacked configuration of the drive circuit layer 715 and the memory layer 716 can be a monolithic stacked configuration. In a monolithic stacked configuration, the layers can be connected without using through-electrode technology such as a TSV (Through Silicon Via) or a bonding technology such as Cu-Cu direct bonding. By configuring the drive circuit layer 715 and the memory layer 716 as a monolithic stacked configuration, for example, a so-called on-chip memory configuration can be achieved in which the memory is formed directly on the processor. The on-chip memory configuration enables the operation of the interface between the processor and the memory to be faster.

[0392] Furthermore, by configuring an on-chip memory, the size of the connection wiring can be reduced compared to technologies that use through electrodes such as TSVs, and the number of connection pins can be increased. Increasing the number of connection pins enables parallel operation, which makes it possible to improve the memory bandwidth (also called memory bandwidth).

[0393] It is also preferable that the memory cell arrays included in the memory layer 716 are formed using OS transistors and the memory cell arrays are monolithically stacked. By forming the memory cell arrays in a monolithic stacked structure, one or both of the memory bandwidth and the memory access latency can be improved. Note that the bandwidth is the amount of data transferred per unit time, and the access latency is the time from access to the start of data exchange. Note that when Si transistors are used for the memory layer 716, it is more difficult to form a monolithic stacked structure than when OS transistors are used. Therefore, it can be said that OS transistors have a superior structure to Si transistors in a monolithic stacked structure.

[0394] The semiconductor device 710 may also be referred to as a die. In this specification, a die refers to a chip piece obtained by forming a circuit pattern on, for example, a disk-shaped substrate (also called a wafer) and dicing it into cubes during the semiconductor chip manufacturing process. Examples of semiconductor materials that can be used for the die include silicon (Si), silicon carbide (SiC), and gallium nitride (GaN). For example, a die obtained from a silicon substrate (also called a silicon wafer) may be called a silicon die.

[0395] 25B shows a perspective view of an electronic component 730. The electronic component 730 is an example of a SiP (System in Package) or an MCM (Multi-Chip Module). The electronic component 730 has an interposer 731 provided on a package substrate 732 (printed circuit board), and a semiconductor device 735 and a plurality of semiconductor devices 710 provided on the interposer 731.

[0396] The electronic component 730 shows an example in which the semiconductor device 710 is used as a high bandwidth memory (HBM). The semiconductor device 735 can be used in an integrated circuit such as a central processing unit (CPU), a graphics processing unit (GPU), a neural processing unit (NPU), or a field programmable gate array (FPGA).

[0397] For example, a ceramic substrate, a plastic substrate, or a glass epoxy substrate can be used as the package substrate 732. For example, a silicon interposer or a resin interposer can be used as the interposer 731.

[0398] The interposer 731 has multiple wirings and functions to electrically connect multiple integrated circuits with different terminal pitches. The multiple wirings are provided in a single layer or multiple layers. The interposer 731 also functions to electrically connect the integrated circuits provided on the interposer 731 to electrodes provided on the package substrate 732. For these reasons, the interposer is sometimes called a "rewiring substrate" or "intermediate substrate." In addition, through electrodes may be provided in the interposer 731, and the integrated circuits and the package substrate 732 may be electrically connected using the through electrodes. In addition, with a silicon interposer, a TSV may also be used as the through electrode.

[0399] In an HBM, many wirings must be connected to achieve a wide memory bandwidth. Therefore, the interposer on which the HBM is mounted must have fine and high-density wiring. Therefore, it is preferable to use a silicon interposer for the interposer on which the HBM is mounted.

[0400] Furthermore, in SiPs, MCMs, and the like that use silicon interposers, a decrease in reliability due to differences in the coefficient of expansion between the integrated circuit and the interposer is unlikely to occur. Furthermore, because the silicon interposer has a highly flat surface, poor connection between the integrated circuit mounted on the silicon interposer and the silicon interposer is unlikely to occur. In particular, it is preferable to use silicon interposers in 2.5D packages (2.5-dimensional packaging) in which multiple integrated circuits are arranged horizontally on an interposer.

[0401] On the other hand, when electrically connecting multiple integrated circuits with different terminal pitches using a silicon interposer, a TSV, or the like, a space is required, such as the width of the terminal pitch. Therefore, when attempting to reduce the size of the electronic component 730, the width of the terminal pitch becomes an issue, and it may be difficult to provide the many wirings necessary to achieve a wide memory bandwidth. Therefore, as described above, a monolithic stacked structure using OS transistors is preferable. A composite structure may be formed by combining a memory cell array stacked using TSVs and a monolithically stacked memory cell array.

[0402] A heat sink (heat dissipation plate) may be provided overlapping the electronic component 730. When a heat sink is provided, it is preferable to align the height of an integrated circuit provided on the interposer 731. For example, in the electronic component 730 shown in this embodiment, it is preferable to align the height of the semiconductor device 710 and the height of the semiconductor device 735.

[0403] Electrodes 733 may be provided on the bottom of package substrate 732 in order to mount electronic component 730 on another substrate. FIG. 25B shows an example in which electrodes 733 are formed with solder balls. By providing solder balls in a matrix on the bottom of package substrate 732, BGA (Ball Grid Array) mounting can be achieved. Electrodes 733 may also be formed with conductive pins. By providing conductive pins in a matrix on the bottom of package substrate 732, PGA (Pin Grid Array) mounting can be achieved.

[0404] The electronic component 730 can be mounted on other substrates using various mounting methods, including, but not limited to, BGA and PGA, such as a staggered pin grid array (SPGA), a land grid array (LGA), a quad flat package (QFP), a quad flat J-leaded package (QFJ), and a quad flat non-leaded package (QFN).

[0405] 26A shows a perspective view of a mainframe computer 5600. The mainframe computer 5600 has a rack 5610 housing a plurality of rack-mounted computers 5620. The mainframe computer 5600 may also be called a supercomputer.

[0406] 26B shows a perspective view of an example of a computer 5620. The computer 5620 has a motherboard 5630. The motherboard 5630 is provided with a plurality of slots 5631 and a plurality of connection terminals. A PC card 5621 is inserted into the slot 5631. In addition, the PC card 5621 has connection terminals 5623, 5624, and 5625, which are each connected to the motherboard 5630.

[0407] Fig. 26C shows an example of a PC card 5621. The PC card 5621 is a processing board equipped with, for example, a CPU, a GPU, a storage device, etc. The PC card 5621 has a board 5622 and connection terminals 5623, 5624, 5625, electronic components 5626, 5627, 5628, and 5629 mounted on the board 5622. Note that Fig. 26C illustrates components other than electronic components 5626, 5627, and 5628.

[0408] The connection terminal 5629 has a shape that allows it to be inserted into a slot 5631 of the motherboard 5630, and the connection terminal 5629 functions as an interface for connecting the PC card 5621 and the motherboard 5630. An example of the standard for the connection terminal 5629 is PCIe.

[0409] The connection terminals 5623, 5624, and 5625 can be, for example, interfaces for supplying power to the PC card 5621, inputting signals, etc. Furthermore, they can be, for example, interfaces for outputting signals calculated by the PC card 5621. Examples of standards for the connection terminals 5623, 5624, and 5625 include USB (Universal Serial Bus), SATA (Serial ATA), and SCSI (Small Computer System Interface). Furthermore, when a video signal is output from the connection terminals 5623, 5624, and 5625, examples of the respective standards include HDMI (registered trademark).

[0410] The electronic component 5626 has a terminal (not shown) for inputting and outputting signals, and the electronic component 5626 and the board 5622 can be electrically connected by inserting the terminal into a socket (not shown) provided on the board 5622.

[0411] The electronic components 5627 and 5628 have multiple terminals, and can be mounted on wiring provided on the board 5622 by, for example, reflow soldering the terminals. Examples of the electronic component 5627 include an FPGA, a GPU, and a CPU. For example, the electronic component 730 can be used as the electronic component 5627. For example, the electronic component 5628 includes a storage device. For example, the electronic component 700 can be used as the electronic component 5628.

[0412] The mainframe computer 5600 can also function as a parallel computer. By using the mainframe computer 5600 as a parallel computer, it is possible to perform large-scale calculations required for, for example, learning and inference in artificial intelligence.

[0413] [Space Equipment] The semiconductor device of one embodiment of the present invention can be suitably used in space equipment.

[0414] A semiconductor device according to one embodiment of the present invention includes an OS transistor. The OS transistor exhibits small changes in electrical characteristics due to radiation exposure. That is, the OS transistor has high radiation resistance and can be suitably used in an environment where radiation may be incident. For example, the OS transistor can be suitably used in outer space. Specifically, the OS transistor can be used as a transistor for a semiconductor device provided in a space shuttle, an artificial satellite, or a space probe. Examples of radiation include X-rays and neutrons. Note that outer space refers to an altitude of 100 km or higher, but the outer space described in this specification may include one or more of the thermosphere, the mesosphere, and the stratosphere.

[0415] Fig. 27A shows an artificial satellite 6800 as an example of space equipment. The artificial satellite 6800 has a body 6801, a solar panel 6802, an antenna 6803, a secondary battery 6805, and a control device 6807. Note that Fig. 27A shows a planet 6804 in space as an example.

[0416] 27A , a battery management system (also referred to as a BMS) or a battery control circuit may be provided for the secondary battery 6805. The use of an OS transistor in the battery management system or the battery control circuit is preferable because it consumes low power and has high reliability even in space.

[0417] Furthermore, outer space is an environment with radiation levels 100 times higher than on Earth. Examples of radiation include electromagnetic waves (electromagnetic radiation) such as X-rays and gamma rays, and particle radiation such as alpha rays, beta rays, neutron rays, proton rays, heavy ion rays, and meson rays.

[0418] When sunlight is irradiated onto the solar panel 6802, the power required for the operation of the satellite 6800 is generated. However, for example, in a situation where sunlight is not irradiated onto the solar panel or where the amount of sunlight irradiating the solar panel is small, the generated power is small. Therefore, there is a possibility that the power required for the operation of the satellite 6800 will not be generated. In order to operate the satellite 6800 even in a situation where the generated power is small, it is preferable to provide a secondary battery 6805 on the satellite 6800. Note that the solar panel may be called a solar cell module.

[0419] The satellite 6800 can generate a signal. The signal is transmitted via an antenna 6803, and can be received by, for example, a receiver installed on the ground or another satellite. By receiving the signal transmitted by the satellite 6800, the position of the receiver that received the signal can be determined. As described above, the satellite 6800 can constitute a satellite positioning system.

[0420] The control device 6807 has a function of controlling the satellite 6800. The control device 6807 is configured using, for example, one or more selected from a CPU, a GPU, and a storage device. Note that a semiconductor device including an OS transistor, which is one embodiment of the present invention, is preferably used for the control device 6807. The OS transistor has smaller fluctuations in electrical characteristics due to radiation exposure than a Si transistor. That is, the OS transistor has high reliability even in an environment where radiation may be incident, and can be preferably used.

[0421] The artificial satellite 6800 can also be configured to include a sensor. For example, by including a visible light sensor, the artificial satellite 6800 can have the function of detecting sunlight reflected from an object on the ground. Alternatively, by including a thermal infrared sensor, the artificial satellite 6800 can have the function of detecting thermal infrared rays emitted from the earth's surface. As described above, the artificial satellite 6800 can function as, for example, an earth observation satellite.

[0422] Although an artificial satellite is described as an example of space equipment in this embodiment, the present invention is not limited thereto. For example, the semiconductor device of one embodiment of the present invention can be suitably used in space equipment such as a spaceship, a space capsule, or a space probe.

[0423] As described above, OS transistors have excellent advantages over Si transistors, such as the ability to achieve a wide memory bandwidth and high radiation resistance.

[0424] [Data Center] The semiconductor device of one embodiment of the present invention can be suitably used in a storage system applied to, for example, a data center. The data center is required to perform long-term management of data, such as ensuring data immutability. Managing long-term data requires a large-scale building, such as installing storage and servers for storing a huge amount of data, ensuring a stable power supply for maintaining the data, or ensuring cooling equipment required for maintaining the data.

[0425] By using the semiconductor device of one embodiment of the present invention in a storage system applied to a data center, it is possible to reduce the power required to store data and the size of the semiconductor device that stores data. Therefore, it is possible to reduce the size of the storage system, the size of the power supply for storing data, the scale of the cooling equipment, and the like. Therefore, it is possible to reduce the space required for the data center.

[0426] Furthermore, the semiconductor device of one embodiment of the present invention has low power consumption, which allows heat generation from the circuit to be reduced. Therefore, adverse effects of the heat generation on the circuit itself, peripheral circuits, and modules can be reduced. Furthermore, by using the semiconductor device of one embodiment of the present invention, a data center that operates stably even in a high-temperature environment can be realized. Therefore, the reliability of the data center can be improved.

[0427] Fig. 27B shows a storage system applicable to a data center. The storage system 6000 shown in Fig. 27B has a plurality of servers 6001sb as hosts 6001 (illustrated as Host Computers). It also has a plurality of storage devices 6003md as storage 6003 (illustrated as Storage). The host 6001 and storage 6003 are shown connected via a storage area network 6004 (illustrated as SAN: Storage Area Network) and a storage control circuit 6002 (illustrated as Storage Controller).

[0428] The host 6001 corresponds to a computer that accesses data stored in the storage 6003. The hosts 6001 may be connected to each other via a network.

[0429] Although the storage 6003 uses flash memory to reduce the data access speed, i.e., the time required to store and output data, this time is significantly longer than the time required for DRAM, which can be used as cache memory within the storage. In order to solve the problem of the long access speed of the storage 6003, a storage system typically provides cache memory within the storage to reduce the time required to store and output data.

[0430] The cache memory described above is used in the storage control circuit 6002 and the storage 6003. Data exchanged between the host 6001 and the storage 6003 is stored in the cache memory in the storage control circuit 6002 and the storage 6003, and then output to the host 6001 or the storage 6003.

[0431] By using OS transistors as transistors for storing data in the cache memory and holding a potential corresponding to the data, the frequency of refresh operations can be reduced, and power consumption can be reduced.

[0432] Note that the application of the semiconductor device of one embodiment of the present invention to any one or more selected from electronic components, electronic devices, mainframe computers, space equipment, and data centers is expected to have an effect of reducing power consumption. Therefore, while energy demand is expected to increase with the improvement in performance or high integration of semiconductor devices, the use of the semiconductor device of one embodiment of the present invention can contribute to the reduction of carbon dioxide (CO ２ Furthermore, the semiconductor device of one embodiment of the present invention is effective as a countermeasure against global warming because it consumes low power.

[0433] This embodiment mode can be implemented by appropriately combining at least a part thereof with other embodiment modes described in this specification.

[0434] 10: semiconductor device, 11: insulating layer, 15: memory cell, 20: transistor, 21: semiconductor layer, 21f: semiconductor film, 21s: layer, 22: insulating layer, 22f: insulating film, 23: conductive layer, 23f: conductive film, 24: conductive layer, 24a: conductive film, 24af: conductive film, 24b: conductive film, 24bf: conductive film, 25: conductive layer, 25f: conductive film, 29: conductive layer, 30: capacitor, 31: insulating layer, 31f: insulating film, 32: insulating layer, 33: insulating layer, 34: insulating layer, 41: insulating layer, 43: insulating layer, 44: insulating layer, 46: insulating layer, 47: insulating layer, 48: insulating layer, 49: insulating layer, 51 : conductive layer, 52: insulating layer, 55: conductive layer, 55a: conductive film, 55b: conductive film, 56: conductive layer, 57: conductive layer, 61: sacrificial layer, 62: sacrificial layer, 65: resist mask, 70: surface, 71: conductive layer, 72: conductive layer, 75: insulating layer, 76: insulating layer, 78: plug, 81: conductive layer, 82: plug, 83: plug, 85: insulating layer, 86: insulating layer, 87: insulating layer, 88: plug, 89: plug, 90: transistor, 91: substrate, 92: semiconductor region, 93: insulating layer, 94: conductive layer, 95a: low resistance region, 95b: low resistance region, 98: element isolation layer, 700: electronic component, 702: printed circuit board, 704: mounting substrate, 710: semiconductor device, 711: mold, 712: land, 713: electrode pad, 714: wire, 715: drive circuit layer, 716: memory layer, 730: electronic component, 731: interposer, 732: package substrate, 733: electrode, 735: semiconductor device, 900: semiconductor device, 910: drive circuit, 911: peripheral circuit, 912: control circuit, 915: peripheral circuit, 920: memory array, 923: row driver, 924: column driver, 925: input circuit, 926: output circuit, 927: sense amplifier, 928 : voltage generation circuit, 930: layer, 931: PSW, 932: PSW, 941: row decoder, 942: column decoder, 950: memory cell, 951: memory cell, 952: memory cell, 953: memory cell, 954: memory cell, 955: memory cell, 956: memory cell, 957: memory cell, 958: memory cell, 960: arithmetic unit, 970A: semiconductor device, 970B: semiconductor device, 970C: semiconductor device, 989: cache interface, 990: substrate, 991: ALU, 992: ALU controller, 993: instruction decoder,994: Interrupt controller, 995: Timing controller, 996: Register, 997: Register controller, 998: Bus interface, 999: Cache, 5600: Mainframe computer, 5610: Rack, 5620: Computer, 5621: PC card, 5622: Board, 5623: Connection terminal, 5624: Connection terminal, 5625: Connection terminal, 5626: Electronic component, 5627: Electronic component, 5 628: Electronic component, 5629: Connection terminal, 5630: Motherboard, 5631: Slot, 6000: Storage system, 6001: Host, 6001sb: Server, 6002: Storage control circuit, 6003: Storage, 6003md: Storage device, 6800: Artificial satellite, 6801: Airframe, 6802: Solar panel, 6803: Antenna, 6804: Planet, 6805: Secondary battery, 6807: Control device,

Claims

a first conductive layer, a second conductive layer, a third conductive layer, a fourth conductive layer, a semiconductor layer, a first insulating layer, a second insulating layer, a third insulating layer, and a fourth insulating layer; the first insulating layer is provided above the first conductive layer and has a side surface; the semiconductor layer has a first portion in contact with the side surface of the first insulating layer and a second portion in contact with the top surface of the first conductive layer; the second conductive layer has a portion located above the first insulating layer and in contact with the first portion; the second insulating layer covers the first portion and the second portion; the third conductive layer covers the first portion and the second portion via the second insulating layer; the third insulating layer covers the first portion and the second portion via the second insulating layer and the third conductive layer; the fourth conductive layer is located below the first conductive layer, the fourth insulating layer has a portion located between the first conductive layer and the fourth conductive layer; the first conductive layer includes a first conductive film and a second conductive film on the first conductive film; the semiconductor layer contains indium oxide and is in contact with the second conductive film; the second conductive film contains a metal oxide; the first conductive film contains a metal; Semiconductor device. 　 a pair of first conductive layers, a second conductive layer, a pair of third conductive layers, a pair of fourth conductive layers, a pair of semiconductor layers, a first insulating layer, a pair of second insulating layers, a pair of third insulating layers, and a fourth insulating layer; the pair of third conductive layers, the pair of semiconductor layers, the pair of second insulating layers, and the pair of third insulating layers are provided symmetrically with the first insulating layer interposed therebetween, the first insulating layer is provided above the first conductive layer and has a pair of side surfaces; each of the pair of semiconductor layers has a first portion in contact with the side surface of the first insulating layer and a second portion in contact with the top surface of the first conductive layer; the second conductive layer has a portion located above the first insulating layer and is in contact with the first portions of the pair of semiconductor layers; the pair of second insulating layers respectively cover the first portion and the second portion; the pair of third conductive layers respectively cover the first portion and the second portion via the second insulating layer; the pair of third insulating layers respectively cover the first portion and the second portion via the second insulating layer and the third insulating layer; the pair of fourth conductive layers are respectively located below the first conductive layer, the fourth insulating layer has a portion located between the first conductive layer and the fourth conductive layer; each of the pair of first conductive layers includes a first conductive film and a second conductive film on the first conductive film; the pair of semiconductor layers each contain indium oxide and are in contact with the second conductive film; the second conductive film contains a metal oxide; the first conductive film contains a metal; Semiconductor device. 　 In claim 1 or claim 2, The metal oxide includes indium. Semiconductor device. 　 In claim 1 or claim 2, Each of the pair of semiconductor layers has a single crystal structure or a polycrystalline structure. Semiconductor device. 　 In claim 1 or claim 2, the fourth conductive layer has a recess; the fourth insulating layer has a portion provided along the recess, the first conductive layer has a portion located within the recess with the fourth insulating layer interposed therebetween, and is in contact with a side surface and an upper surface of the fourth insulating layer within the recess; Semiconductor device. 　 In claim 1 or claim 2, the second conductive film has a recess; the semiconductor layer is in contact with a side surface and an upper surface of the recess of the second conductive film; Semiconductor device. 　 In claim 1 or claim 2, a fifth insulating layer; the fifth insulating layer has a portion in contact with an upper surface of the third conductive layer and an upper surface of the third insulating layer and located between the second conductive layer and the third conductive layer; Semiconductor device. 　 In claim 1 or claim 2, a sixth insulating layer; the fourth conductive layer is located on the sixth insulating layer; the sixth insulating layer includes silicon nitride or silicon oxynitride; Semiconductor device. 　 In claim 1 or claim 2, a seventh insulating layer; the seventh insulating layer is located above the second conductive layer; the seventh insulating layer includes silicon nitride or silicon oxynitride; Semiconductor device. 　 In claim 1 or claim 2, the third insulating layer comprises hafnium oxide, aluminum oxide, or an oxide containing hafnium and silicon; Semiconductor device. 　 In claim 7, the fifth insulating layer includes hafnium oxide, aluminum oxide, or an oxide containing hafnium and silicon; Semiconductor device. 　 In claim 1 or claim 2, a transistor below the fourth conductive layer; The transistor includes silicon as a semiconductor in which a channel is formed, one of the source and the drain of the transistor is connected to the second conductive layer; Semiconductor device. 　 In claim 1 or claim 2, a transistor above the second conductive layer; The transistor includes silicon as a semiconductor in which a channel is formed, one of the source and the drain of the transistor is connected to the second conductive layer; Semiconductor device.

Images