Memory cells using negative differential resistance ferroelectric field effect transistors

Abstract

Static memory cells utilizing negative differential resistance (NDR) ferroelectric field-effect transistor (NDR FeFET) devices are disclosed. By exploiting the NDR characteristic of the FeFETs, a binary data latch can be formed with only two transistors, providing for compact storage. A single transfer FET operating in a non-NDR mode can be used for both writing to and reading from the storage node of the latch. Alternatively a second transfer FET operating in a non-NDR mode may be used for writing to the latch. Variations of these bits-cells are also described.

Description

MEMORY CELLS USING NEGATIVE DIFFERENTIAL RESISTANCE FERROELECTRIC FIELD EFFECT TRANSISTORSCROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application claims priority to, and the benefit of, U.S. provisional patent application serial number 63 / 651 ,321 filed on May 23, 2024, incorporated herein by reference in its entirety.STATEMENT REGARDING FEDERALLY SPONSORED RESEARCH OR DEVELOPMENT

[0002] Not ApplicableNOTICE OF MATERIAL SUBJECT TO COPYRIGHT PROTECTION

[0003] A portion of the material in this patent document may be subject to copyright protection under the copyright laws of the United States and of other countries. The owner of the copyright rights has no objection to the facsimile reproduction by anyone of the patent document or the patent disclosure, as it appears in the United States Patent and Trademark Office publicly available file or records, but otherwise reserves all copyright rights whatsoever. The copyright owner does not hereby waive any of its rights to have this patent document maintained in secrecy, including without limitation its rights pursuant to 37 C. F. R. § 1 .14.BACKGROUND

[0004] 1. Technical Field

[0005] The technology of this disclosure pertains generally to semiconductor memory devices, and more particularly to Static Random-Access Memory (SRAM) devices utilizing Negative Differential Resistance (NDR) FETs.

[0006] 2. Background Discussion

[0007] There is a need to miniaturize Static Random-Access Memory (SRAM) cells to increase storage density and reduce cost per bit of stored information. However, existing approaches to scaling down the size of SRAM cells below that of a standard cell comprising six transistors, have largely beenimpractical.

[0008] Accordingly, a need exists for a more compact SRAM technology which can overcome these existing issues. The present disclosure fulfills that need and provides additional benefits over existing SRAM cell designs.BRIEF SUMMARY

[0009] This disclosure describes SRAM cell designs that utilize FeFETs operating in Negative Differential Resistance (NDR) mode (i.e., NDR-FeFETs) to achieve improved scalability as compared with a conventional six-transistor SRAM cell design. The NDR-FeFET elements are preferably of the type described in Section 3 of the present disclosure, which presents a field-effect transistor that includes a ferroelectric (“Fe”) material layer in the gateinsulating material stack and that can exhibit negative differential resistance in its output characteristic of drain current as a function of drain voltage.

[0010] Further aspects of the technology described herein will be brought out in the following portions of the specification, wherein the detailed description is for the purpose of fully disclosing preferred embodiments of the technology without placing limitations thereon.BRIEF DESCRIPTION OF THE DRAWINGS

[0011] The technology described herein will be more fully understood by reference to the following drawings which are for illustrative purposes only:

[0012] FIG. 1 is a circuit diagram of a Static Random-Access Memory (SRAM) cell having a bistable latch comprising NDR-FeFETs, according to at least one embodiment of the present disclosure.

[0013] FIG. 2A through FIG. 2C are current-versus-voltage (l-V) plots of NDR- FeFETs operating in the SRAM cell of FIG. 1 , showing hysteretic NDR behavior, when sweeping the storage-node voltage VSN in the positive and negative directions, according to at least one embodiment of the present disclosure.

[0014] FIG. 3A through FIG. 3C are plots of voltage waveforms for various write and read operations as well as power supply changes for the SRAM cell of FIG. 1 , according to at least one embodiment of the present disclosure.

[0015] FIG. 4 is a circuit diagram of a Static Random-Access Memory (SRAM) cell according to the present disclosure, having a bistable latch with a controllable bias voltage, according to at least one embodiment of the present disclosure.

[0016] FIG. 5 is a circuit diagram of an embodiment of a bistable static random-access memory (SRAM) cell using a nonvolatile-mode n-channel “pull-down” NDR-FeFET, according to at least one embodiment of the present disclosure.

[0017] FIG. 6 is a plot of voltage waveforms for a write operation followed by a shutdown operation for the circuit of FIG. 5, according to at least one embodiment of the present disclosure.

[0018] FIG. 7 is a circuit diagram of a two-port bistable inverter Static Random-Access Memory (SRAM) cell, according to at least one embodiment of the present disclosure.

[0019] FIG. 8 is a plot of a voltage-transfer-characteristic for the bistable latch design illustrated in FIG. 7, according to at least one embodiment of the present disclosure.

[0020] FIG. 9 is a plot of voltage waveforms for various operations of the Static Random-Access Memory (SRAM) cell design of FIG. 7, according to at least one embodiment of the present disclosure.

[0021] FIG. 10A through FIG. 10C are schematic cross-sections along the direction of current flow, of NDR ferroelectric field-effect-transistor embodiments as a metal-ferroelectric-semiconductor field-effect transistor (MFSFET) (FIG. 10A), as a metal-ferroelectric-insulator-semiconductor fieldeffect transistor (MFISFET) (FIG. 10B), and as a metal-ferroelectric-metal- insulator-semiconductor field-effect transistor (MFMISFET) (FIG. 10C) according to at least one embodiment of the present disclosure.

[0022] FIG. 11 A through FIG. 11 D is a series of schematic cross-sections along the direction of current flow, showing polarization switching, propagating from the drain end to the source end of the channel region, in the ferroelectric (FE) layer of the gate stack of the (MFSFET) NDR-FeFET according to at least one embodiment of the present disclosure.

[0023] FIG. 12 is a graph illustrating drain current versus drain voltage characteristic of the NDR-FeFET, including a NDR region of operation with hysteretic behavior, according to at least one embodiment of the present disclosure.

[0024] FIG. 13 is a graph of drain current versus drain voltage characteristics of the NDR-FeFET for different values of applied gate voltage showing electrically tunable negative-differential-resistance onset voltage, according to at least one embodiment of the present disclosure.

[0025] FIG. 14 is a graph of drain current (on a logarithmic scale) versus gate voltage characteristics of the NDR-FeFET showing that for a fixed gate voltage the current at high drain voltage can be orders of magnitude less than at a low drain voltage, according to at least one embodiment of the present disclosure.

[0026] FIG. 15 is a graph of drain current (on a logarithmic scale) versus gate voltage characteristics of the NDR-FeFET, showing how the FE material layer polarization state can be maintained through a shutdown procedure to retain the FE material layer polarization state and thereby achieve nonvolatile operation, according to at least one embodiment of the present disclosure.

[0027] FIG. 16 is a graphical chart illustrating the drain current (on a logarithmic scale) versus gate voltage characteristics of the NDR-FeFET having nonvolatile operation in which the state of the NDR-FeFET can be restored by first raising the drain voltage and then raising the gate voltage, according to at least one embodiment of the present disclosure.

[0028] FIG. 17 is a sequenced list of fabrication process steps for fabricating the NDR-FeFET in a manner compatible with a conventional CMOS IC manufacturing process, according to at least one embodiment of the present disclosure.

[0029] FIG. 18A through FIG. 18C are schematic cross-sections of NDR FeFETs according to the present disclosure, as a metal-ferroelectric- semiconductor field-effect transistor (MFSFET) (FIG. 18A), metal-ferroelectric- insulator-semiconductor field-effect transistor (MFISFET) (FIG. 9B) and metal- ferroelectric-metal-insulator-semiconductor field-effect transistor (MFMISFET) (FIG. 18C), according to embodiments of the present disclosure.

[0030] FIG. 19A through FIG. 19C are schematic cross-sections orthogonal to the direction of current flow, for fin-shaped NDR ferroelectric field-effect- transistors (FeFETs) as a metal-ferroelectric-sem iconductor field-effect transistor (MFSFET) (FIG. 19A), metal-ferroelectric-insulator-semiconductor field-effect transistor (MFISFET) (FIG. 19B), and metal-ferroelectric-metal- insulator-semiconductor field-effect transistor (MFMISFET) (FIG. 19C), according to embodiments of the present disclosure.

[0031] FIG. 20A through FIG. 20C are schematic cross-sections orthogonal to the direction of current flow, of nanosheet or “gate-all-around” NDR ferroelectric field-effect-transistors (FeFETs), as metal-ferroelectric- semiconductor field-effect transistor (MFSFET) (FIG. 20A), metal-ferroelectric- insulator-semiconductor field-effect transistor (MFISFET) (FIG. 20B), and metal-ferroelectric-metal-insulator-sem iconductor field-effect transistor (MFMISFET) (FIG. 20C), according to embodiments of the present disclosure.

[0032] FIG. 21 A and FIG. 21 B are schematic cross-sections along the direction of current flow, of NDR ferroelectric field-effect-transistors (FeFETs), as metal-ferroelectric-sem iconductor field-effect transistor (MFSFET) (FIG. 21 A), and metal-ferroelectric-insulator-sem iconductor field-effect transistor (MFISFET) (FIG. 21 B), according to embodiments of the present disclosure.DETAILED DESCRIPTION

[0033] 1. Introduction

[0034] The rapid growth of the semiconductor industry over the past six decades has largely been enabled by continual advancements in integrated circuit (IC) “chip” manufacturing technology which have allowed the size of Metal-Oxide-Semiconductor Field-Effect Transistors (MOSFETs), which are the basic building blocks used to fabricate Very-Large-Scale Integrated (VLSI) circuits, to be steadily reduced with each new generation of technology. In general, as the transistor size is scaled down, the chip area required for a given circuit is reduced, so that more chips can be manufactured on a single silicon wafer substrate, resulting in lower manufacturing cost per chip; circuit operation speed also improves, because of reduced capacitance and higher transistor current density. State-of-the-art fabrication facilities presentlymanufacture ICs with minimum transistor feature size smaller than 10 nm, so that microprocessor products with transistor counts over 100 billion on a single chip can be manufactured cost-effectively. Arrays of Static Random Access Memory (SRAM) cells, which typically comprise six or more MOSFETs, are used to temporarily store data within a microprocessor chip. Increased SRAM storage capacity is necessary to achieve significant improvements in computational performance; therefore, SRAM arrays may comprise over half of the area of a high-performance microprocessor chip.

[0035] The pace of SRAM cell area scaling with each new generation of IC manufacturing technology has slowed dramatically in recent years, due to increasing sensitivity of transistor performance to process-induced variations with miniaturization. This presents an obstruction in the path of continued improvements in computing performance, energy efficiency, and cost. Innovative solutions that are compatible with modern IC fabrication processes are needed to overcome this SRAM scaling challenge.

[0036] Negative Differential Resistance (NDR) devices previously have been proposed for more compact implementations of SRAM cells. For example, E. Goto (IRE Trans. Electronic Computers, March 1960, p. 25) disclosed a SRAM cell consisting of two tunneling diodes (TDs) and a pass transistor. For a variety of NDR devices, including TDs, the current first increases with increasing applied voltage, reaching a peak value, then decreases with increasing applied voltage, exhibiting negative differential resistance and reaching a minimum (“valley”) value. For TDs, the current again increases with increasing applied voltage beyond the valley voltage; therefore, a TD’s current-versus-voltage characteristic is shaped like the letter “N.” For other NDR devices, the current does not significantly increase again with increasing applied voltage beyond the peak voltage; thus their current-vs. -voltage characteristic is shaped like the symbol “A” and the valley current is simply the current corresponding to the maximum device operating voltage, typically the power supply voltage.

[0037] A key figure of merit for NDR devices is the ratio of the Peak Current to the Valley Current (PVCR). The higher the value of the PVCR, the more useful the NDR device is for variety of circuit applications. The PVCR of TDsis generally not sufficiently large to make them practical for low-power compact SRAM cell application, because in order for the TDs in a Goto cell to have sufficient on-state “drive” current, the valley current would be large, resulting in large static power dissipation. Even if TDs could achieve PVCR sufficiently large to implement low-power SRAMs, they would require specialized fabrication process sequences to integrate them monolithically with CMOS transistors used for other circuit blocks of a microprocessor; the increased complexity of an integrated TD-CMOS manufacturing process would result in higher cost, offsetting the area reduction benefit of TD-based SRAM cells. U.S. Pat. No. 6,479,862 discloses a device in which dynamic charge-carrier trapping and detrapping was proposed to dynamically modulate the transistor threshold voltage (VT), eliciting an NDR effect in the device output characteristic. Furthermore, U.S. Pat. No. 6,512,274, discloses a 3- transistor SRAM cell based on the device described in the aforementioned patent. However, this device was demonstrated in U.S. Pat. No. 7,557,009 to have peak-to-valley-current ratios less than 100 and required undesirably high supply voltages, making it unsuitable for low-power, compact SRAM application. Accordingly, there exists a significant need for NDR devices with very high PVCR (greater than ten thousand) which can be easily integrated into a conventional CMOS fabrication process, and practical SRAM designs to use them to implement practical, compact, low-power SRAM devices at relatively low cost.

[0038] 2. Embodiments of the Disclosure

[0039] The following presents one or more embodiments of Static Random- Access Memory (SRAM) cells that can improve area and / or energy efficiency over that of conventional six-transistor SRAM cells, without requiring a significant increase in manufacturing cost. In some embodiments, this compact SRAM cell can be used for nonvolatile information storage.

[0040] The specific NDR transistors utilized in the disclosed SRAM embodiments are described in Section 3, and were the subject of another patent application by the Applicants.

[0041] The memory cells are described by way of example and not limitation, as variations of the embodiments disclosed will be obvious to those ofordinary skill in the art in view of the following descriptions.

[0042] FIG. 1 illustrates a Static Random-Access Memory (SRAM) cell 10. As shown, the data storage node (SN) 28 is coupled to a bitline 20 through enhancement-mode (VT > 0 V) access FET element 18, gated by wordline 22, and two series-connected depletion-mode (VTO < 0 V) n-channel NDR-FeFET elements 24, 26 form the bistable latch 12. In this embodiment the gate terminal is directly connected to the source terminal of each FET 24 and 26. Power supply connections are depicted as VDD 16 and Vss 14.

[0043] Access FET 18 is configured as a transfer gate, allowing a bit address line (“bitline”) to be connected to the storage node (SN) 28 under the control of a word address line (“wordline”) 22. One of the source / drain terminals of access FET 18 is connected to the storage node 28, and the other source / drain terminal of access FET 18 is connected to bitline 20. The gate terminal of access FET 18 is connected to the wordline 22.

[0044] The bistable latch 12 comprises two series-connected NDR-FeFETs configured as follows. The drain terminal of a first “pull-down” NDR-FeFET 26 is connected to the source terminal of a second “pull-up” NDR-FeFET 24 to form the data storage node, with the source terminal of the pull-down NDR- FeFET 26 connected to a grounded or negatively biased voltage terminal (Vss) and the drain terminal of the pull-up NDR-FeFET 24 connected to a power-supply voltage terminal (VDD); the gate terminal of the pull-down NDR- FeFET 26 is connected to its source terminal, biased at Vss, and the gate terminal of the pull-up NDR-FeFET 24 is connected to its source terminal and the storage node.

[0045] FIG. 2A through FIG. 2C are simulated current-versus-voltage (l-V) curves for the NDR-FeFETs that comprise the bistable latch 12, plotting their currents as a function of the storage node voltage (VSN) to explain the operation of the bistable latch 12. The NDR-FeFET elements of this embodiment are preferably of the type described in Section 3.

[0046] In FIG. 2A is shown a plot 50 of current flows for the upper (pull-up) NDR-FeFET 24 and the lower (pull-down) NDR-FeFET 26 of the bistable latch 12.

[0047] On the left side of the plot 50 is shown current IPD flowing in the pulldown NDR-FeFET 26, which is dependent on the potential difference between its drain and source terminals, which correlates with VSN. This current initially increases 52 as VSN increases above Vss (assumed to be 0 Volts), reaching a peak value when VSN is equal to a critical value VPEAK, PD 58a, and rapidly decreasing towards zero amperes as VSN increases beyond VPEAK, PD. Due to hysteretic polarization switching behavior of the ferroelectric layer in an NDR- FeFET, when VSN is decreased back down to 0 Volts, the voltage VPEAK, PD, REV 56a at which IPD reaches a peak is smaller than VPEAK, PD.

[0048] The IPU current flow in the pull-up NDR-FeFET 24, as seen at the right side of the plot 50, is likewise dependent on the potential difference between its drain and source terminals, VDD-VSN, It initially increases as VDD-VSN increases above 0 Volts, reaching a peak value when VDD-VSN is equal to a critical value VPEAK, PU 56b, and rapidly decreases toward zero Amperes as VDD-VSN increases beyond the critical value VPEAK, PU. Due to hysteretic NDR behavior, when VDD-VSN is decreased back down to 0 Volts, the voltage VPEAK, PU, REV 58b at which Ipu reaches a peak is smaller than VPEAK, PU.

[0049] Thus, FIG. 2A plots both IPD and Ipu as a function of VSN ranging from Vss (which is assumed to be 0 Volts) to VDD (which is assumed to be 1 Volt). Since the pull-up NDR-FeFET 24 and pull-down NDR-FeFET 26 are connected in series, IPD must be equal to IPU when the access FET 18 is in the off state, such as when the wordline voltage is lower than the threshold voltage of the access FET. Therefore, the values of VSN for which IPD = IPU, for example where the current-versus-voltage (l-V) curves for the pull-up NDR-FeFET 24 and for the pull-down NDR-FeFET 26 intersect and have the same gradient signs (i.e. , with both increasing with increasing VSN, or both decreasing with increasing VSN) correspond to the stable operating points of latch 12 during a storage operation. It will be noted that the crossing point near one-half VDD, where IPU and IPD have different gradient signs, is not a stable operating point, thus making 12 a true bistable latch.

[0050] Thus it is understood that latch 12 is stable when the electric potential VSN at the storage node is one of two values, near Vss (corresponding to a “0” state) or near VDD (corresponding to a “1” state), as shown in FIG. 2A.Accordingly, it can be used to store one binary digit (“bit”) of information.

[0051] In FIG. 2B is depicted 70 relevant IPU 74 and IPD 72 l-V curves if the latch is in the “0” state and the value of VSN is disturbed away from 0 Volts, for example taking place during a read operation. The current IPD flowing in the pull-down NDR-FeFET 26 becomes significantly larger than the current IPU flowing in the pull-up NDR-FeFET 24, causing the value of VSN to be decreased back toward the stable operating point near 0 Volts. The IPU current 74 is shown increasing with SN voltage decreasing from VDD to VDD -VPEAK,PU,REV 78 and abruptly dropping toward zero Amperes with further decrease in SN voltage.

[0052] In FIG. 2C is illustrated 90 the relevant Ipu 94 and IPD 92 curves if the latch is in the “1” state and the value of VSN is disturbed away from VDD: the current IPU 94 flowing in the pull-up NDR-FET 24 becomes much greater than the current IPD 92 flowing in the pull-down NDR-FeFET 26, causing the value of VSN to be increased back toward the stable operating point near VDD. The IPD current 92 is shown increasing with SN voltage increasing from 0 Volts up to VPEAK,PD,REV 96 and abruptly dropping toward zero Amperes with further increase in SN voltage.

[0053] The access FET 18 is used to transfer data from the data line to the storage node (write operation) and also to transfer data from the storage node to the data line (read operation) under the control of the voltage applied to the wordline, as follows. When the wordline voltage (electric potential) is pulsed high, typically to VDD, access FET 18 is in the on state, allowing current to flow between the bitline and the storage node for data transfer, for example reading data from the storage node or writing data to the storage node. When the wordline voltage is low, such as below VT for the access FET, then access FET 18 is in the off state, so that the storage node is electrically disconnected from the bitline.

[0054] For a write operation, the bitline voltage is first driven to either VDD or Vss (which is typically 0 Volts) while the wordline voltage is low, and then the wordline voltage is pulsed high (e.g., to VDD) to turn on access FET 18 and thereby allow the storage node to be either charged to VDD minus the threshold voltage of the access FET 18 (“Write 1” operation) or discharged toVss (“Write 0” operation), respectively.

[0055] FIG. 3A through FIG. 3C show voltage waveforms 110 during write operations of the SRAM cell 10.

[0056] In FIG. 3A is illustrated wordline voltage (VWL) as a function of time 116, bitline voltage (VBL) as a function of time 118, and storage node voltage (VSN) as a function of time 120 for “Write 1” 112 and “Write 0” 114 operations in succession, assuming the polarization switching speed of a FeFET does not limit the write speed. Ideally VPEAK, PU, REV should be greater than VT for the access FET, for the storage node voltage to be quickly latched to the “1” state. It should be noted that the drive current of the access FET 18 should be greater than each of the peak currents of the NDR FeFETs that form the bistable latch 12 of FIG. 1 , so as to ensure that the write operation can successfully switch the state, from the “1” state to the “0” state or from the “0” state to the “1” state, of bistable latch 12.

[0057] For a read operation, the bitline voltage is first “precharged” to VDD and then electrically floated, while the wordline voltage is maintained at a low level no greater than the threshold voltage of access FET 18, then the wordline is pulsed high (e.g., to VDD) to turn on access FET 18 and thereby allow the bitline to be discharged toward Vss (assumed to be 0 Volts in FIGS. 2A, 2B, 2C, 3A, 3B and 3C) through the pull-down NDR-FeFET 26 if the latch is in the “0” state; otherwise if the latch is in the “1” state then the bitline voltage remains at VDD.

[0058] In FIG. 3B is illustrated 130 more detail of voltage waveforms for a “Read 0” operation for the write line voltage (VWL) as a function of time 116, bitline voltage (VBL) as a function of time 118 and storage node (VSN) as a function of time 120. It should be noted that a voltage drop of 50 mV is sufficient for the “0” state to be detected by a sense amplifier circuit located at the periphery of a SRAM cell array. It should be noted that the storage node voltage rises as the access FET 18 is turned on due to a voltage-divider effect, but that the pull-down NDR-FeFET 26 prevents the latch from changing states due to the large read static noise margin (approximately equal to VPEAK, PD).

[0059] The hysteretic current-voltage (l-V) characteristics of NDR-FeFET devices allow the bistable latch 12 to have much larger supply voltage noise margin than that of a typical six-transistor (6T) CMOS SRAM cell or a TD- based latch. When a high voltage (“1” state) is latched at the storage node, the voltage drop between the drain and source (VDS) for the pull-down NDR- FeFET is close to VDD while VDS for the pull-up NDR-FeFET is close to 0 Volts. If the supply voltage VDD is reduced, such as due to electrical “noise,” VSN will track the supply voltage and hence also be reduced. The cell will remain latched in the “1” state until the pull-down current exceeds the pull-up current, for example until VDD is reduced to VPEAK, PD, REV.

[0060] Therefore the supply voltage for SRAM cell 10 can be reduced almost to VPEAK, PD, REV, approximately 0.1 Volts in FIG. 2C, to reduce static power dissipation. This result is in contrast to a typical minimum operating voltage of approximately 0.5 Volts for state-of-the-art 6T CMOS SRAM cells.

[0061] In FIG. 3C is illustrated 150 voltage waveforms for the power supply voltage (VDD) 158, for the wordline voltage (VWL) 160, for the bitline voltage (VBL) 162, and for the storage node voltage (VSN) 164 for SRAM cell 10 of FIG. 1 as it is powered on (VDD going high) 152 and then when a “1” is written 154 to the storage node, after which the supply voltage (VDD) is momentarily reduced 156 to approximately VPEAK, PD, REV, 0.1 Volts, and the “1” state is retained when the supply voltage is restored to 1 Volt.

[0062] This plot demonstrates that hysteretic NDR behavior is beneficial for SRAM application. It is expected that this hysteretic behavior is also beneficial for other applications beyond the scope of this disclosure, such as digital logic and computing.

[0063] The valley currents of the NDR-FeFETs that form the bistable latch 12 of FIG. 1 are preferably minimized to achieve low static power dissipation, while the peak current of the pull-down NDR-FeFET 26 is preferably maximized to achieve fast read access time.

[0064] It will be appreciated that the memory cell depicted in FIG. 1 using the novel NDR FETs can be varied without departing from the teachings of the present disclosure

[0065] FIG. 4 illustrates a read / write performance enhanced SRAM cell 210, as a variation of FIG. 1 , in that the bistable latch 212 is configured with a controllable bias voltage (VBIAS). In this example the bias voltage is shown as being applied to the gate terminal of the pull-down NDR-FeFET, although it may be implemented on either or both of the NDR-FeFETs.

[0066] The exemplified memory cell is shown with a bitline 220 coupled to a storage node 230 via an access FET 218 gated by a wordline 222.

[0067] The pull-up NDR FET 224 is connected between the power supply VDD 216 and the storage node 230, with its gate terminal exemplified as also being tied to the storage node. The pull-down NDR FET 226 is connected between the storage node and power supply Vss 214, with its gate terminal being configured to receive a controllable bias voltage (VBIAS) 228, rather than connecting the gate terminal of the pull-down NDR-FeFET 226 to its source terminal, thus providing a means for dynamically modulating its peak current and valley current, such as by lowering VBIAS to lower the valley current during standby (storage) operation and / or to lower the peak current during a write operation, and / or by raising VBIAS to increase the peak current during a read operation.

[0068] Furthermore, it should be appreciated that other variations can be utilized, such as allowing a controllable bias voltage to be applied to the gate terminal of the pull-up NDR-FeFET device 224, rather than it being connected to the storage node, thereby providing a means for dynamically modulating its peak current and valley current to improve SRAM cell performance.

[0069] FIG. 5 illustrates another variation 250 of the NDR-FeFET SRAM memory cell which is non-volatile. In this example latch 252 is connected between VDD 256 and Vss 254 as in prior examples, with a pull-up transistor 264 and a pull-down transistor 266. The bitline 260 is connected through FET 258, gated by wordline 262, to storage node 269 as shown.

[0070] However in this example the pull-down NDR FeFET is a non-volatile (NV) mode NDR-FeFET 266 rather than a depletion-mode NDR-FeFET. In addition, this NV mode NDR-FeFET is configured with a controllable bias voltage (VBIAS) 268 applied to the gate terminal.

[0071] The ferroelectric polarization-versus-gate voltage hysteresis loop of the nonvolatile-mode NDR-FeFET 266 is approximately centered at VGS = 0 Volts, and this transistor has a threshold voltage slightly greater than 0 Volts so that it has two stable polarization states for VGS = 0 Volts and VDS = 0 Volts.

[0072] For VBIAS greater than 0 Volts, when the electric polarization of the ferroelectric layer is in the downward direction, for instance with the positive end of the electric dipole pointing to the semiconductor substrate, the nonvolatile NDR-FeFET 266 has a larger current than the pull-up NDR FeFET 264. Yet when the electric polarization of the ferroelectric layer is in the upward direction, for instance with the negative end of the electric dipole pointing to the semiconductor substrate, it has a smaller current than the pull- up NDR FeFET 264. Therefore when SRAM cell 252 is powered on, it can latch into the state it was in just prior to being powered off as is shown in FIG. 6.

[0073] FIG. 6 illustrates timing waveforms for VDD 280, VWL 282, VBL 284, VBIAS 286, VSN(1 ) 288 and VSN(0) 290 during Power On 272, Write 274, Power Off 276 and another Power On 278 for the SRAM cell 250 of FIG. 5. This nonvolatility is achieved by powering off (“shutting down”) the cell by first reducing VBIAS to 0 Volts before reducing the power-supply voltage, applied to the drain terminal of the pull-up NDR-FeFET 264 to 0 Volts, and subsequently powering on (“waking up”) the cell by ramping up the power-supply voltage before ramping up VBIAS. The access FET 258 is again used to transfer a value (voltage) to and from the storage node. This “non-volatile” operation of the cell can effectively provide for zero standby power consumption.

[0074] Thus, FIG. 6 shows these voltage versus time waveforms for SRAM cell 252 as it is initially powered on and then either a “0” or a “1” is written to the storage node, and subsequently as the cell is powered off and on as described above. It can be seen from the figure that the previously stored state has been recovered.

[0075] FIG. 7 illustrates an embodiment 310 of a bistable inverter circuit implemented with a complementary pair of NDR-FeFETs. Specifically the figure depicts an inverting latch 312 with a p-channel enhancement-mode NDR-FeFET 324 connected in series with an n-channel enhancement-modeNDR-FeFET 326. The gate terminals of the two NDR-FeFETs are connected together to form an input node 327, while the drain terminals of the two NDR- FeFETs are connected together to form a storage node 329.

[0076] One of the source / drain terminals of a read access FET 318 is connected to the storage node 329, while the other source / drain terminal of the read access FET 318 is connected to a bitline 320 and the gate terminal is connected to a read wordline 322.

[0077] The source terminal of the n-channel NDR-FeFET 326 is connected to a grounded or negatively biased terminal (Vss) 314 and the drain terminal of the p-channel NDR-FeFET 324 is connected to a power-supply terminal (VDD) 316.

[0078] A write access FET 328 is shown with one source / drain terminal connected to the input node 327 of the inverting latch 312, and its other source / drain terminal is connected to a write bitline 330, while the gate terminal of this FET is connected to a write wordline 332. The two-port SRAM cell design 310 can have a more compact layout than a typical 6T CMOS SRAM cell, with the functionality of an eight-transistor two-port CMOS SRAM cell.

[0079] FIG. 8 illustrates a hysteretic voltage transfer curve of the inverting latch 312 of FIG. 7, such that for a range of input node voltages from VLH to VHL, the storage node voltage (VSN) has two stable values that correspond to a “0” state (VSN = Vss) and a “1” state (VSN = VDD). TO write a “0” to SRAM cell 310, the input node voltage should be increased above VHL such that VSN is discharged to Vss (assumed to be 0 Volts in FIG. 8) through n-channel NDR- FeFET 326, which is achieved by increasing the write bitline voltage 330 to a high level, typically VDD and at least equal to VHL, then pulsing the write wordline voltage 332 to a high level, typically VDD and at least VHL plus the threshold voltage of write access FET 328, to turn on write access FET 328. To write a “1” to SRAM cell 310, the input node voltage should be decreased below VLH such that VSN is charged to VDD through p-channel NDR-FeFET 324, which is achieved by decreasing the write bitline 330 voltage to a low level, typically 0 Volts and at most equal to VLH, then pulsing the write wordline voltage 332 to a high level, typically VDD and at least VLH plus thethreshold voltage of write access FET 328, to turn on its write access. When the write wordline voltage 332 is low (below VT for write access FET 328), the write access FET is in the off state, so that the input node 327 is electrically disconnected from the write bitline 330.

[0080] A read operation of SRAM cell 310 is performed similarly to that of SRAM cell 10 in FIG. 1 , as the read bitline 320 voltage is first “precharged” to VDD and then electrically floated, while the read wordline voltage is low, then the read wordline is pulsed high (e.g., to VDD) to turn on read access FET 318 and thereby allows the bitline to be discharged toward Vss through the n- channel NDR-FeFET 326 if the bistable inverter is in the “0” state; otherwise if the bistable inverter is in the “1” state then the read bitline voltage remains at VDD. When the read wordline 322 voltage is low (below VT for read access FET 318), then read access FET 318 is in the off state, so that the storage node is electrically disconnected from the read bitline.

[0081] FIG. 9 illustrates voltage waveforms 370 for a sequence of operations of the SRAM cell of FIG. 7, and indicates a hold voltage level (VHOLD) 388. The waveforms are shown for a write wordline voltage (VWWL) 384, a write bitline voltage (VWBL) 386, an input node voltage (VIN) 390, a storage node voltage (VSN) 392, a read wordline voltage (VRWL) 394, and a read bitline voltage (VRBL) 396. The operations depicted in the waveforms are for “Write 1” 372, “Standby” 374, “Read 1” 376, “Write 0” 378, “Standby” 380 and “Read 0” 382.

[0082] Since the input node is electrically floating when write access FET 328 is in the off state, capacitive coupling via the gate-to-source / drain capacitances of the write access FET and the NDR-FeFETs causes the voltage of the input node to be affected somewhat by write-wordline voltage transitions; so long as VIN remains less than VHL when the cell is in the “1” state or VIN remains greater than VLH when the cell is in the “0” state, the state of the cell is retained. It should be noted that the SRAM cell design 310 can provide for significantly faster write speeds than that of the SRAM cell design 10 of FIG. 1.

[0083] For each embodiment, high PVCR for each of the NDR-FeFETs is desirable for fast write and read operations and for low standby powerconsumption of the SRAM cell. Also, the access transistor(s) in each embodiment may be either standard enhancement-mode metal-oxide- semiconductor FET(s) or enhancement-mode NDR FeFET(s) that do not exhibit NDR behavior for a large applied gate voltage (close to or equal to VDD).

[0084] While the technology of this disclosure has been described with reference to illustrative embodiments, this description is not intended to be construed in a limiting sense. As an example, the previously described exclusively n-channel NDR-FeFET SRAM cell designs 10 of FIG. 1 , 210 of FIG. 4, and 250 of FIG. 5 each could be implemented with exclusively p- channel NDR-FeFETs or with a complementary pair of n-channel and p- channel NDR-FeFETs to implement the core bistable circuit.

[0085] 3. Embodiments of NDR FETs

[0086] 3.1. Introduction

[0087] This section describes in detail specific embodiments of NDR FeFETs, such as utilized in the preceding sections of the application. It will be noted that the reference numbering below overlaps that of the preceding sections.

[0088] In contrast to prior approaches the following describes an electronically tunable, Negative Differential Resistance (NDR), devices that enhance the drain-to-source-voltage induced depolarization phenomenon to achieve substantial levels of NDR. The devices exhibit a Peak-to-Valley-Current Ratio (PVCR) of greater than ten thousand at room temperature, and enable the implementation of compact and energy-efficient Integrated Circuits (ICs) using a Complementary Metal Oxide Semiconductor (CMOS)-compatible manufacturing process. These devices also exhibits nonvolatile operation, are compatibility with CMOS IC manufacturing technology, and should be scalability to smaller feature sizes as IC manufacturing technology progresses.

[0089] By way of example, and not of limitation, one embodiment of the device comprises a Field-Effect Transistor (FET) that includes a ferroelectric (FE) material layer in the gate-insulating material stack, wherein the FET exhibits a negative differential resistance in its output characteristic (drain current as a function of drain voltage). For a fixed applied gate voltage and small drain-to-source voltage, the FE layer has positive electric polarization (i.e. , the polarization vector points from the gate terminal towards the semiconductor channel region) such that the FET is in a low threshold voltage state. As the drain-to-source voltage increases above zero volts, the FET channel current first increases as the positive polarization of the FE layer is retained. Once the drain-to-source voltage exceeds a pre-determined level, the current subsequently decreases with increasing drain-to-source voltage as the polarization of the FE is reduced, and then rapidly decreases as the net FE polarization switches from positive to negative (i.e., the polarization vector points from the semiconductor channel region towards the gate terminal) causing the threshold voltage of the FET to suddenly increase. In this region of operation, the device exhibits negative differential resistance, as the drain current decreases with increasing drain voltage.

[0090] The device may exhibit a hysteretic negative-differential-resistance region of operation in which the voltage at which the current reaches a peak is lower when the drain-to-source voltage is reduced from a high value to zero. The drain-to-source voltage corresponding to the onset of negative differential resistance is tunable by modifying the device structure during its manufacture or by electronically adjusting the applied gate voltage. The resulting device can be incorporated into an integrated circuit for a number of useful applications, including as part of a volatile memory device, nonvolatile memory device, a logic device, and other applications without limitation.

[0091] By way of example, and not of limitation, the following description presents one or more embodiments of an electronically tunable, negative differential resistance (NDR), FeFET design that can be readily fabricated using conventional CMOS IC fabrication techniques. Other embodiments of the technology and variations of those disclosed will be obvious to those of ordinary skill in the art in view of the following description.

[0092] In the description that follows, a preferred device embodiment is described first. Next, device operation and the mechanism responsible for the negative differential resistance (NDR) mode is described, followed by descriptions of additional preferred embodiments for enhancing the performance of an NDR FeFET device. Finally, an exemplary fabricationprocess flow is described. The functionality of the NDR FeFET is demonstrated using the technology of computer aided design (TCAD) software simulations, with exemplary results provided in FIG. 11 through FIG. 16.

[0093] 3.2. Embodiments

[0094] FIG. 10A through FIG. 10C illustrate different cross-section embodiments of FeFET NDR device structures along the direction of current flow. The figures of these and the other embodiments are shown for illustrative purposes, wherein the drawings are not to scale.

[0095] The differences between these figures is in regard to the gate stack structure above the channel region. The following describes the common portions of each of these embodiments, implemented on a Silicon-On- Insulator (SOI) substrate. A SOI wafer contains a bulk semiconductor region 12 which has a Buried Oxide (BOX) layer 16 beneath the silicon channel region 18.

[0096] Shallow Trench Isolation (STI) dielectric regions 14 are formed to electrically insulate the device horizontally from adjacent devices. Above BOX layer 16 is the SOI channel region 18, on either side of which are heavily n-type doped (n+) source region 20 and drain region 24 to which voltages Vs 22 and VD 26 are applied, respectively. Outside of the BOX layer 16 and STI regions there is a heavily p-type doped (p+) body contact region 28 to which voltage VB 30 is applied.

[0097] In FIG. 10A is illustrated 10 a NDR ferroelectric field-effect-transistor (FeFET) which is configured in the form of a metal-ferroelectric-semiconductor field-effect transistor (MFSFET), as the SFET has a gate terminal 36 to which a voltage can be applied to a metal gate terminal 34 over a ferroelectric layer 32, which is directly over channel region 18. On either side of the metal gate terminal are dielectric spacers 33.

[0098] In FIG. 10B is illustrated 50 a NDR ferroelectric field-effect-transistor (FeFET) which is configured in the form of a metal-ferroelectric-insulator- semiconductor field-effect transistor (MFISFET), as the SFET has an ‘MFI’ gate stack structure with a gate terminal 36 to which a voltage can be applied to a metal gate terminal 56 over a ferroelectric layer 54, over an interfacialdielectric insulator layer 52 which is directly over channel region 18.

[0099] In FIG. 10C is illustrated 70 a NDR ferroelectric field-effect-transistor (FeFET) which is configured in the form of a metal-ferroelectric-metal- insulator-semiconductor field-effect transistor (MFMISFET), as the SFET has an ‘MFMI’ gate stack structure with a gate terminal 36 to which a voltage can be applied to a metal gate terminal 78 over a ferroelectric layer 76, over a floating metal gate layer 74, over an interfacial dielectric insulator layer 72 which is directly over channel region 18.

[0100] The above embodiments can be fabricated with a minimum of modifications to a conventional silicon-on-insulator (SOI) CMOS IC manufacturing process. Each of these NDR FeFET devices allows a gate voltage to be applied via a terminal 36 to a gate stack structure which includes at least a ferroelectric (FE) layer (e.g., 32, 54, 76).

[0101] The source 20 and drain 24 regions are each doped with an n-type dopant concentration exceeding approximately 1 E20 per cubic centimeter. These regions are located on each side of the channel region 18 and approximately aligned to the edges of the gate terminal.

[0102] The FE material layer can be separated from the channel region 18 by an interfacial dielectric insulator layer 52 as illustrated in FIG. 10B, or by both an electrically floating metal layer “floating gate” 74 and dielectric insulating layer 72 as illustrated in FIG. 10C.

[0103] Gate-sidewall dielectric spacers 33 are located on either side of the gate stack, partially over the source region 20 and drain region 24. The bulk semiconductor “well” region 13 below the BOX layer 16 is typically doped p- type and can be used to adjust the electric potential in the channel region by applying a bias voltage VB to a body terminal 30. It should be noted that, in standard practice, a heavily doped p-type region 28 is formed at the metalsemiconductor contact to provide for low contact resistance. It should be apparent that a p-channel NDR FeFET device can be constructed with the same key components as described herein, with standard modifications that are familiar to persons of ordinary skill in the art, to utilize holes instead of electrons for electric current conduction. An n-channel device is described herein for the sake of convenience.

[0104] Although these NDR FeFET devices are similar in appearance to a conventional SOI n-channel FeFET transistor, the present disclosure incorporates critical modifications in order that the device manifests the desired NDR output characteristics.

[0105] A first modification of these FeFET devices is that the FE material layer should comprise a minimum number of polarization domains, ideally one domain. This may be achieved in a number of ways, including by reducing the gate area of the device (by minimizing the gate length, i.e., the distance between the source and regions, and the channel width), by reducing the area of the FE material layer (e.g., 32, 54, 76) using a selective recess-etch process, by optimizing the FE material layer formation process, and by straining the FE material layer.

[0106] In addition, a gate-to-source voltage (VGS) is applied to the NDR FeFET device which is greater than the FE material layer positive polarization switching voltage (i.e., the gate-to-source voltage at which the FE material layer switches from a negative polarization state to a positive polarization state). This voltage level is necessary to cause a conductive “inversion-layer” of mobile charge carriers (electrons, for an n-channel device) to form in the semiconductor channel region and thereby allow current to flow between the source and drain regions under the influence of the drain-to-source voltage (VDS). The positive polarization switching voltage (VPPS) is determined by a combination of transistor design parameters, including the effective work function of the metal gate terminal, and it can be engineered to be negative, such that the device is in the on state for VGS = 0 Volts.

[0107] When the NDR FeFET device is in the on state and VDS is non-zero, the electric potential profile along the channel region is non-uniform. As VDS is increased, the channel electric potential will rise, more so on the drain side, and eventually (at a certain value of VDS) the FE material layer can no longer maintain a uniformly positive polarization state. Ideally, polarization switching within the FE material layer to the negative state (i.e., with the polarization vector pointing from the semiconductor channel region towards the gate terminal) begins proximal (near to) the drain region and propagates toward the source region resulting in an increase in transistor threshold voltage andhence a decrease in transistor current with increasing VDS, i.e. , NDR.

[0108] FIG. 11A through FIG. 11 D illustrates 110, 120, 130, 140, progression in the state of polarization within the FE material layer corresponding to various different values of VDS. FIG. 11 A is seen at VDS = 0 Volts, in which the FE material layer is positively polarized 112 (down arrows shown) along the entire channel region due to the positive electric field between the gate terminal and semiconductor, uniformly along the direction of current flow.

[0109] As VDS increases, the strength of polarization near the drain is reduced, such as seen in FIG. 11 B, represented as lighter line shading 122 at the right side portion of the FE material, due to the reduced electric field there.

[0110] At a certain value of VDS (defined as VPEAK, 158 in FIG. 12) the polarization near the drain switches to negative (arrows shown reversed) 132 in a portion of the drain region (134 showing the dividing line of the reversal).

[0111] A further increase in VDS causes polarization switching 142 to propagate all the way to the source end so that the FE material layer becomes negatively polarized (up arrows 142), uniformly along the direction of current flow as seen in FIG. 11 D. If the FE material layer comprises multiple polarization domains, then this propagation may occur via sequential domain switching or domain wall migration.

[0112] Relatively large values of remanent polarization and saturation polarization of the FE material layer are desirable for achieving a large Peak- to-Valley-Current Ratio (PVCR) since a larger charge density within the gate insulator will result in a larger change in transistor threshold voltage. If the polarization state of the FE material layer at the source end does not switch, then the change in threshold voltage is not maximized and hence PVCR is not maximized.

[0113] In some embodiments a floating gate may be inserted between the FE material layer and an interfacial dielectric insulator layer, which can relax the requirement for a minimum number of domains in the FE material layer because the floating gate equalizes the electric potential at the bottom interface of the FE material layer along the entire length of the channel, forcing a uniform electric field throughout the FE material layer. In this case, special care should be taken to optimize the thickness of the interfacialdielectric insulator material layer to prevent electronic charges from accumulating on the floating gate while maintaining small interfacial layer equivalent oxide thickness.

[0114] An additional modification to a conventional n-channel FeFET is that the FE material layer should have a low coercive electric field and hence a low polarization switching voltage, which is equal to the coercive electric field multiplied by the FE material layer thickness. Ideally, the coercive electric field should be relatively small while maintaining a sharp polarization-versus- voltage switching characteristic. This is desirable because the hysteresis of the polarization-versus-voltage switching characteristic can limit the extent to which the supply voltage (VDD) of a NDR FeFET-based IC can be scaled down for reduced power consumption. This is additionally desirable because a low coercive electric field facilitates fast FE material polarization switching. The capacitances of the FE material layer and the dielectric-semiconductor layers should be matched to minimize the hysteresis voltage.

[0115] With the source voltage (Vs) applied to terminal 22 and body voltage (VB) applied to terminal 30 (as per FIG. 10A - 10C) both held at ground potential and the gate voltage (VG) applied to terminal 36 such that the gate- to-source voltage VGS is greater than VPPS (so that an inversion-layer channel exists for small drain-to-source voltage VDS), the output characteristic (drain current as a function of drain-to-source voltage VDS) of the device will exhibit negative differential resistance over a range of VDS values.

[0116] FIG. 12 illustrates 150 a graph of drain current as a function of the applied drain voltage for this aspect of device operation demonstrating a hysteretic NDR behavior. It can be seen that for a fixed gate-to-source voltage (VGS) (198 in FIG. 14) the drain current firstly increases in a first VDS range 152, similarly as for a conventional n-channel MOSFET. However, beyond a certain VDS value the drain current decreases with increasing VDS, i.e. , the device operates in a NDR mode in a second VDS range 154. The VDS value at which the drain current peaks and begins to decrease (i.e., VPEAK 158) can be tuned by adjusting the transistor channel length, native threshold voltage, and / or other parameters during the manufacturing process, or by adjusting the applied body voltage. Within the voltage range 154, at a certainvalue of drain-to-source voltage 160, the current abruptly decreases with increasing VDS. It is at this voltage that the electric polarization of the FE material layer switches completely from positive to negative. The concomitant shift in charge within the FE material layer results in an abrupt increase in transistor threshold voltage. This complete FE-layer polarization switching enables higher PVCR than reported for other FeFET-based NDR devices.

[0117] As VDS is reduced back from VDD towards zero Volts (moving to the left on the graph 150), NDR behavior (increase in drain current with decreasing VDS) occurs at lower voltages due to the hysteretic switching characteristic of the FE material layer. In the resultant larger “valley” 162 of voltage range 156 the device essentially remains in the “off state.” Once the drain-to-source voltage is reduced sufficiently to a second certain voltage value 164 such that the positive coercive field is reached, the FE material layer will switch back to the positive polarization state and the device will operate with positive differential resistance as VDS is reduced to zero Volts. This hysteretic NDR behavior can be advantageous, for example to provide an increased noise margin in NDR FeFET-based digital ICs.

[0118] FIG. 13 illustrates 170 another unique aspect of the device of this disclosure, that is gate modulation of NDR behavior, as the drain current is plotted as a function of VDS for five different values of gate overdrive voltage (-0.1 to 0.4V), which are defined as the difference between the gate-to-source voltage VGS and the positive polarization switching voltage VPPS, to show how the drain current increases and the drain-to-source voltage range for NDR behavior shifts with increasing gate overdrive voltage.

[0119] For large gate overdrive voltage, the peak voltage and current levels are increased, and the NDR behavior can even be eliminated for the operating voltage range (zero to VDD Volts) so that the device functions as a conventional n-channel MOSFET (curve 172). This tunable behavior makes possible reconfigurable CMOS-NDR ICs with dynamically adaptive functionality.

[0120] FIG. 14 illustrates a plot 190 of drain current (on a logarithmic scale) as a function of gate voltage, for low drain-to-source voltage VDS = 0.05 V as curves 191 , and for high drain-to-source voltage VDS = 1 V, as curves 195. Itcan be seen that for both sets of curves there is a region of operation in which the drain current rapidly increases 202, 206 with increasing VGS and rapidly decreases 200, 204 with decreasing VGS, corresponding to the FE material layer switching to a positive polarization state and to a negative polarization state, respectively.

[0121] Additionally, it can be seen that a region of operation 196 exists for which the drain current is lower for VDS = 1 V than for VDS = 0.05 V, corresponding to NDR behavior. In this region the FE material layer is in the positive polarization state for VDS = 0.05 V and in the negative polarization state for VDS = 1 V. If the gate voltage is biased, such as at the value indicated 198, to be only slightly higher than the gate voltage value at which the FE material layer switches to a positive polarization 202 when VDS = 0.05 V, then the value of VDS corresponding to the onset of NDR behavior is small.

[0122] Another highly desirable feature of the device of the present disclosure is its capacity for nonvolatile operation, in which the device may be operated so that the FE material layer retains its state of polarization without the need of voltages being applied, for example “memorizing” whether it was last in the NDR valley voltage range of operation 156 in FIG. 12 or not.

[0123] FIG. 15 illustrates 210 this aspect of the present disclosure, which is achieved by designing the NDR FeFET to have a positive polarization switching voltage slightly greater than 0 Volts, and shutting it down by first reducing VGS from its typical NDR operation value 216 to 0 Volts, as illustrated with the arrows labeled 212, and subsequently reducing VDS to 0 Volts, illustrated with the arrows labeled 214a, 214b.

[0124] FIG. 16 illustrates 230 the process of subsequently “waking up” the NDR FeFET with a reverse sequence of applying voltages by first increasing VDS, illustrated with the arrows labeled 234, 235, and then increasing VGS illustrated with the arrows labeled 232 toward its typical NDR operation value 236. In this way, the polarization state of the FE material layer can be retained when the IC is powered down, which can prove useful for embedded nonvolatile memory and logic applications.

[0125] The technology of the present disclosure leverages a phenomenon that has hitherto not been exploited to achieve significantly high levels of NDRbehavior. In the prior art, band-to-band quantum-mechanical tunneling of charged particles (e.g., electrons and / or holes) from one side of a diode to the other side is the primary mechanism for achieving NDR in tunneling diodes. FeFET devices have been extensively investigated for nonvolatile memory applications, and they typically require relatively long programming time (resulting in low memory access speed) and large programming voltages (greater than 2 V), so practical dynamic operation of a FeFET device for digital logic and static memory applications is not obvious. Additionally, it is usually undesirable for an applied drain voltage to disturb the polarization state of the FE material layer, so this is typically avoided in designing FeFETs. It was recently proposed to use an applied drain voltage to assist the erase operation of a nonvolatile FeFET, but the mechanism utilizes generation of holes (forward biasing the body-source junction, increasing the vertical electric field) rather than a purely electrostatic effect to switch the polarization state of the FE material layer. Ferroelectric polarization switching recently has been shown to occur in less than 1 nanosecond, and careful interface and ferroelectric dopant engineering has enabled low coercive electric fields, below 1 MV / cm, for a range of materials taught herein; furthermore, manufacturing process advancements have enabled single-grain FEs for dimensions relevant to nanometer scale devices. These recent advances enable fast and low-voltage NDR FeFET operation.

[0126] The value of PVCR for a NDR FeFET can be estimated by calculating the change in threshold voltage (VT) effected by switching the polarization state of the entire FE material layer: AVT «AQfe / CFE where AQfe=2xPr; Pr is the remanent polarization, and CFE is the FE capacitance per unit area. As an example, for very mild remanent polarization of 3 microCoulombs per square centimeter (uC / cm2), and for a 2 nm-thick HZO ferroelectric layer with relative permittivity sr=30, AVT=400 mV so that PVCR is close to 10,000, assuming that the applied gate voltage is close to the threshold voltage and that the transistor sub-threshold swing is 100 mV per decade. A slight increase of Pr through material engineering to 4 uC / cm2can increase the PVCR to 200,000 due to larger VT. The PVCR also can be enhanced by dynamically changingthe gate bias voltage to either enhance the peak current and / or to lower the valley current.

[0127] An additional and notable feature of the technology of the present disclosure is that the performance of the NDR-FeFET can improve at scaled transistor dimensions. In other words, as the transistor channel length is reduced, the ability of a single stable domain to form and switch in response to an applied drain voltage is enhanced, due to limitations of the maximum domain size set by ferroelectric material fabrication process and material properties. This aspect of the technology ensures that the structures and methods taught herein have future utility in more advanced devices and products that are made with smaller feature sizes, operated with lower voltage, etc. than those currently available.

[0128] FIG. 17 illustrates an example embodiment 310, specifically a sequenced list of fabrication process steps for fabricating the NDR-FeFET, such as seen in FIG. 10A. In at least one embodiment a standard semiconductor substrate 312 is utilized, which for example could be a silicon- on-insulator wafer or a bulk-silicon wafer (as seen in FIG. 10A), and is first processed through standard device-isolation-structure formation steps 314.

[0129] Subsequently a series of process steps are used to implant dopant atoms selectively, followed by thermal annealing, to form 316, 318 doped regions (“wells”) in the semiconductor substrate underneath the transistor regions.

[0130] Next, the dummy gate stack is formed 320 by deposition of silicon dioxide or thermal oxidation, followed by deposition of polycrystalline or amorphous silicon or silicon alloy material, and patterned using lithography and etch process steps to form dummy gate structures. Subsequently a series of process steps 322, 324 are used to implant dopant atoms selectively, followed by thermal annealing, to form doped source regions and doped drain regions and doped well contact regions in the surface region of the semiconductor.

[0131] Prior to dopant implantation, dielectric spacers (e.g., shown as 33 in FIG. 10A) may be formed along the sidewall(s) of the dummy gate structures, by conformal deposition and anisotropic etching of one or more layers ofdielectric material such as silicon oxide and silicon nitride, to adjust the lateral offset between the gate edges and the source and / or drain regions to optimize transistor performance characteristics. Thermal annealing is performed to heal implant-induced crystalline damage and activate the implanted dopant atoms. Afterwards, an insulating dielectric layer is conformally deposited and then planarized by chemical mechanical polishing, exposing the surfaces of the dummy gate structures.

[0132] Next, the dummy gate stack is selectively removed 326 by a masked etch process and replaced 328, 330 with the permanent gate stack, for the n- channel FeFETs, p-channel MOSFETs, and n-channel MOSFETs as separate process modules. The formation of the permanent gate stack may include steps to thoroughly clean the semiconductor surface, grow a thin (less than 1 nanometer thick) interfacial oxide layer, conformally deposit one or more insulator materials, and deposit one or more metal layers. For the FeFETs, the insulator would include a FE material layer (e.g., roughly 2 nanometer thick hafnium-zirconium oxide); a sacrificial layer of tungsten may be deposited, followed by rapid thermal annealing to crystallize the FE material layer; then the sacrificial tungsten would be selectively removed with an etch process, and layers of metal (e.g., titanium and platinum) may be deposited in succession and patterned to form gate terminal. The replacement gate process for the p-channel MOSFETs, and then the n-channel MOSFETs, is similar but does not include a crystallization anneal, and may feature different materials for the gate insulator and gate metal layers.

[0133] After gate stack formation a forming gas anneal is performed to improve semiconductor-dielectric interface properties. IC fabrication is completed with a “middle-of-line” process sequence 332 to form contacts to the semiconductor regions and local interconnections, followed by a “back- end-of-line process” sequence 334 to form all of the remaining metallic interconnects and dielectric insulating layers in-between. Since the NDR FeFET is fully compatible with a standard CMOS IC manufacturing process, memory and logic circuits can be formed at the same time as the NDR FeFET, and thus integrated monolithically to form conventional CMOS circuits with added NDR capability.

[0134] It will be appreciated by those of ordinary skill in the art that various types of starting semiconductor substrates can be used, for example a SOI substrate as illustrated in FIGS. 10A, 10B, and 10C or a bulk-semiconductor substrate as illustrated in FIGS. 18A, 18B, and 18C. The main modification needed for a bulk-semiconductor FeFET is a retrograde doping profile for the well region, to suppress sub-surface leakage current. Suitable and / or optimal processing conditions for achieving the NDR mode in any particular CMOS technology will be easily designed and determined by those of ordinary skill in the art through conventional modeling and experimentation techniques.

[0135] FIG. 18A through FIG. 18C illustrate example embodiments 410, 450, 470 of an n-channel FeFET NDR device structure. These examples differ from each other in regard to their gate structures. Each of these depict a bulk semiconductor region 412, having Shallow Trench Isolation (STI) dielectric regions 414 to horizontally isolate the device region. Outside of the STI is a p+ doped area 428 for a VB connection 430. Doped (n+) source and drain regions 420, 424 are located on either side of the channel region 427 with terminal connections 422, 426 respectively. The device illustrated can be fabricated with a minimum of modifications to a conventional bulk CMOS IC manufacturing process. The NDR FeFET devices are n-channel metal-oxide- sem iconductor (nMOS) field-effect transistors in which the gate stack includes a metal gate terminal and gate-insulating layer(s) comprising a ferroelectric (FE) material layer.

[0136] In FIG. 18A the gate stack is formed with a ferroelectric layer 432, over which is a metal gate terminal 434 with a terminal 436 to which a gate voltage can be applied. On either side of the gate terminal are spacers comprising dielectric insulating material 433.

[0137] Gate terminal 436 is used to apply a voltage to control a current flowing in response to a voltage applied between the drain terminal 426 and the source terminal 422. Heavily doped n-type semiconductor surface regions 420, 424, with n-type dopant concentrations exceeding approximately 1 E20 per cubic centimeter, are located on each side of the channel region and approximately aligned to the edges of the gate terminal, forming the source and drain regions of the transistor, respectively.

[0138] In FIG. 18B it is illustrated that the FE material layer 454, beneath the metal gate terminal 456 (with a terminal 436), can be separated from the channel region by an interfacial dielectric insulator layer 452.

[0139] In FIG. 18C is illustrated an additional layer of an electrically floating metal layer “floating gate” 474. Thus the gate stack has an interfacial dielectric layer 472, over which is the floating metal gate 474, then the ferroelectric layer 476, and over which is the metal gate terminal 478 to which a gate terminal 436 is connected.

[0140] Gate-sidewall dielectric spacers 433 are located on either side of the gate stack, partially overlapping the source 420 and drain 424 regions, respectively. The Shallow trench isolation (STI) dielectric regions 414 electrically isolate the source, drain, and channel regions from adjacent semiconductor regions. The bulk semiconductor region 412 is typically doped p-type and can be used to dynamically adjust the native threshold voltage by applying a bias voltage to the heavily doped contact region 428 through its contact terminal 430.

[0141] It will also be appreciated by those of ordinary skill in the art that a NDR FeFET may comprise any desired non-planar transistor structure.

[0142] FIG. 19A through FIG. 19C illustrate example embodiments 510, 530, 550 of a non-planar NDR FeFET, which by way of example and not limitation is fin-shaped. The device illustrated can be fabricated with minimum modification to a conventional fin-shaped FeFET CMOS IC manufacturing process. These NDR FeFET devices are depicted as metal-oxide- sem iconductor (MOS) field-effect transistors in which a fin-shaped channel region 520 is formed on top of a bulk semiconductor region 512, isolated from adjacent semiconductor regions by shallow trench isolation (STI) dielectric regions 514, and straddled by a gate stack comprising gate-insulating layer(s) including a ferroelectric (FE) material layer 516 and a gate terminal 518 having gate terminal 522 used for applying a voltage to control current flow in the fin-shaped channel region 520.

[0143] In FIG. 19A the FeFET 510 is shown with the channel region 520 surrounded by an FE layer 516 over which is the metal gate terminal 518.

[0144] In FIG. 19B the FeFET 530 is shown with the channel region 520surrounded by an interfacial dielectric layer 532, a FE layer 516 over which is the metal gate terminal 518.

[0145] In FIG. 19C the FeFET 550 is shown with the channel region 520 surrounded by an interfacial dielectric layer 532, followed by a floating gate metal layer 552, then an FE layer 516 over which is the metal gate terminal 518.

[0146] These FeFET devices may also be fabricated in the form of “Nanosheet,” “nanoribbon” or “gate-all-around” NDR FeFET structures.

[0147] FIGS. 20A through FIG. 20C illustrate these NDR FeFET devices 610, 630, 650. The devices illustrated can be fabricated with minimum modification to a conventional nanosheet FeFET CMOS IC manufacturing process. These NDR FeFET devices are metal-oxide-sem iconductor (MOS) transistors comprising multiple nanosheet-shaped channel regions 624 each wrapped by a gate stack comprising gate-insulating layer(s) including a ferroelectric (FE) material layer and a gate layer, and enveloped by a metal gate terminal 618. The device structure is formed on top of a bulk semiconductor region 612, electrically isolated from adjacent semiconductor regions by shallow trench isolation (STI) dielectric regions 614, and a substrate isolation layer 616. A gate terminal 626 is used to apply a voltage to control current flowing in the channel regions 624.

[0148] In FIG. 20A is illustrated 610 an NDR FeFET in which each channel region 624 is surrounded by a gate stack structure with a FE material layer.

[0149] In FIG. 20B is illustrated 630 an NDR FeFET in which each channel region 624 is surrounded by an interfacial dielectric layer 636 which is surrounded by a FE material layer 622.

[0150] In FIG. 20C is illustrated 650 an NDR FeFET in which each channel region 624 is surrounded by an interfacial dielectric layer 636 which is surrounded by a floating metal gate layer 656, which is surrounded by a FE material layer 622.

[0151] Modifications to the standard non-planar CMOS transistor fabrication process flows are similar to those described above for the planar transistor structures, to fabricate the NDR FeFETs.

[0152] Those of ordinary skill in the art will recognize that the transistorstructures illustrated in FIGS. 10A-10C, 18A-18C, and 19A-19C correspond to a so-called "gate-first" fabrication process in which the permanent gate stack (comprising the gate insulator layer(s) and metal gate layer(s)) are formed prior to the source and drain regions. The exemplary process flow depicted in FIG. 17 is known to those of ordinary skill in the art as a "gate-last" process because the permanent gate stack layers are formed after the source and drain regions are formed.

[0153] It should also be appreciated that these NDR FeFET devices can be fabricated using a “gate-last” fabrication process.

[0154] FIG. 21 A and FIG. 21 B illustrate example embodiments 710, 750 of a gate-last n-channel FeFET NDR device structure, shown by way of example and not limitation. The device illustrated can be fabricated with minimum modification to a conventional silicon-on-insulator (SOI) CMOS IC manufacturing process. The differences between these two examples is primarily found in the gate stack structure.

[0155] The substrate is shown with a bulk semiconductor region 712 (e.g., p- well) which is electrically insulated from the channel region 718 by a buried oxide (BOX) layer 716 and shallow trench isolation (STI) 714 dielectric regions. Outside of the region between the STI regions is a p+ doped contact region 728 for a VB connection 730. Heavily doped n-type semiconductor surface regions 720, 724, with an n-type dopant concentration exceeding approximately 1 E20 per cubic centimeter, are located at each end of the channel region 718 and approximately aligned to the edges of the gate terminal, to form source and drain regions of the transistor.

[0156] In FIG. 21A is illustrated the NDR FeFET with a gate terminal 736 connected to a metal gate terminal 734 over gate-insulating layer(s) 732 comprising a ferroelectric (FE) material layer formed over the SOI channel region 718. At the sidewalls of the gate stack are dielectric spacers 733. It will be noted that the ferroelectric area 732 is in a shape that substantially surrounds metal gate 734, such as having a recess into which the metal gate is contained (e.g., ‘U’-shaped cross-section).

[0157] In FIG. 21 B is illustrated the NDR FeFET 750 with a gate terminal 736 connected to a metal gate terminal 756 over gate-insulating layer(s) 754comprising a ferroelectric (FE) material layer, over an interfacial dielectric layer 752 formed over the SOI channel region 718. At the sidewalls of the gate stack are dielectric spacers 733. It will be noted that the ferroelectric area 732 is in a shape that substantially surrounds metal gate 734. By way of example and not limitation, this example shows dielectric layer 752 extending down slightly into the channel region 718 and drain region 724.

[0158] In the above example the FE material layer 754 is separated from the channel region 718 by the interfacial dielectric layer 752 assuming that the interfacial dielectric layer 752 is formed at least in part by a semiconductor oxidation or nitridation process. Gate-sidewall dielectric spacers 733 are located on either side of the gate stack, over source 720 and drain 724 regions, respectively. The bulk semiconductor “p well” region 712 below the BOX layer 716 is typically doped p-type and can be used to dynamically adjust the electric potential in the channel region 718 by applying a bias voltage to the p-well contact terminal 730. It should be noted that, in standard practice, a heavily doped p-type region 728 is formed at the metalsemiconductor contact to provide for low contact resistance. Typically the ferroelectric layer is formed by a conformal deposition process, so in a gatelast process it would be deposited along the inner sidewalls of the dielectric spacers 733 as well as the surface of the semiconductor channel region, as illustrated in FIG. 21 A and FIG. 21 B.

[0159] It will be understood by those of ordinary skill in the art how the structures of the bulk-semiconductor transistor of FIG. 18A through FIG. 18C, non-planar fin-shaped transistor of FIG. 19A through FIG. 19C, and gate-all- around transistor of FIG. 20A through FIG. 20C can be similarly modified by using a gate-last process.

[0160] Furthermore it will be appreciated by those of ordinary skill in the art that the illustrative process flow of FIG. 17 allows an NDR device design to be optimized independently of the CMOS devices, which is advantageous for scaling with future generations of CMOS IC process technology.

[0161] It will be apparent to those skilled in the art that the NDR FeFET can be advantageously employed in both memory and digital logic applications, and in the types of circuits as described in the prior art, such as memory devices,use in logic circuits, self-latching logic devices, oscillators, power management devices, and a wide range of environments where these useful characteristics can be exploited.

[0162] 3.3. Summary Characteristics of NDR FeFET Devices

[0163] Based on the foregoing, it will be appreciated that this disclosure describes various devices and features, including, but not limited to, the following:

[0164] (a) A new type of semiconductor device with a strong NDR characteristic that can be utilized to improve the density, performance, and / or functionality of integrated circuits.

[0165] (b) A new NDR device in which the dynamic switching of the electric polarization of a ferroelectric material layer can be used for achieving an NDR characteristic.

[0166] (c) A new NDR device with hysteretic behavior, wherein the onset of negative differential resistance with increasing applied voltage occurs at a larger value of applied voltage than that for the onset of negative differential resistance with decreasing applied voltage.

[0167] (d) A new NDR device in which the negative differential resistance region of operation includes a region with sharply decreasing current in response to increasing applied voltage due to the abrupt dynamic switching of the electric polarization of a ferroelectric material layer.

[0168] (e) A new NDR device which features full field-effect transistor features, wherein the conductivity between two terminals is influenced by a voltage applied to a third terminal.

[0169] (f) A new NDR device which can be fabricated with a process that is fully compatible with conventional CMOS IC manufacturing process.

[0170] (g) A new NDR device for which the voltage and current level corresponding to the onset of negative differential resistance is electronically tunable.

[0171] (h) A new NDR device that can be useful for electronic information processing and storage devices.

[0172] (i) A semiconductor field-effect transistor (FET) device that achieves aNegative Differential Resistance (NDR) mode by using a dynamically variablethreshold voltage. Specifically, the transistor threshold voltage can be dynamically adjusted using the drain-to-source voltage. Unlike prior art devices, the NDR device of the present disclosure utilizes a change in the electric polarization state of a ferroelectric material layer embedded in the gate insulator, rather than a band-to-band tunneling mechanism or chargetrapping mechanism, to vary the transistor threshold voltage.

[0173] (j) A semiconductor field-effect transistor device which comprises three terminals and is operable with a NDR mode by applying a voltage across two of the terminals to induce current flow through the semiconductor between the two terminals, and applying a control signal to a third terminal for influencing the conductivity of the current path by controlling an initial electric polarization of the ferroelectric material layer and the density of mobile charge carriers in the current path.

[0174] (k) A ferroelectric (FE) material layer embedded in the gate insulator of the field-effect transistor structure comprising one or more of the following materials, but not limited to: hafnium oxide, hafnium-zirconium oxide, hafniumaluminum oxide, hafnium-silicon oxide, hafnium-lanthanum oxide, hafniumyttrium oxide, hafnium-gadolinium oxide, zirconium oxide, lead-zirconium- titanate oxide. The ferroelectric material layer may be in direct contact with the semiconductor, or it may be separated from the semiconductor by a dielectric insulator layer or by a metal layer and dielectric insulator layer stack.

[0175] A NDR mode of transistor operation is induced by lowering the magnitude of, and furthermore reversing the polarization state, of the FE material layer with increasing applied drain-to-source voltage, and hence decreasing gate-to-drain voltage for a fixed applied gate voltage. In the preferred embodiment, the FE material layer contains one or close-to-one domain, to achieve an abrupt reduction of transistor current when the electric polarization of the FE material layer switches from (substantially) positive to (substantially) negative, in order to achieve a high Peak-to-Valley-Current Ratio (PVCR). It is desirable for the FE material to have a low coercive voltage and high remanent polarization to ensure a low peak-current voltage and high peak-to-valley current ratio, respectively. Furthermore, the thicknesses of the FE material layer and the dielectric insulator layer can beadjusted to maximize PVCR.

[0176] (I) A FE material layer formed as an integral part of the gate (insulatormetal) stack for the FET, which may optionally include a dielectric insulator material layer at the semiconductor interface; this interfacial layer may comprise one or more of the following insulating materials: silicon-dioxide, silicon-oxynitride, aluminum-oxynitride, and / or a high-permittivity dielectric material with a relative permittivity greater than approximately nine. The interfacial dielectric insulator material layer may be formed by a chemical oxidation, thermal oxidation, or atomic layer deposition process and the FE material layer may be formed by atomic layer deposition or sputtering.

[0177] Furthermore, the interfacial dielectric insulator material layer has both thickness and material properties optimized to maintain high effective carrier mobility in the channel while allowing for a large change in threshold voltage due to polarization switching in the FE material layer. In general, a smaller effective oxide (SiC ) thickness of the interfacial dielectric insulator material layer will enable a larger PVCR in an NDR FeFET device due to FE material layer polarization switching. The gate stack may optionally include an electrically floating metal layer “floating gate” between the interfacial dielectric insulator material layer and the FE material layer, which serves to equalize the electric potential across the bottom interface of the FE material layer to provide a consistent electric field throughout the FE layer.

[0178] (m) The effective work function of the gate terminal (control terminal) of the field-effect transistor achieve an NDR mode of operation. In order to switch the electric polarization of the FE material layer with increasing drain- to-source voltage, the gate work function and the coercive electric field of the FE material should be chosen such that the polarization of the FE material layer can be switched without the need for negative drain-to-source voltage or negative gate-to-source voltage. This is in contrast to a ferroelectric memory transistor which requires the application of a negative voltage to switch the electric polarization. A metallic material or combination of materials, such as Ti, TiN, W can be used as the material for the gate terminal. Metal work function tuning techniques, such as chemical treatment, geometrical optimization, or other means may be employed to lower the effective workfunction of the metal gate, which may lower the gate voltage required to operate the NDR device. Other possible embodiments may utilize alternative gate materials, such as doped polycrystalline silicon, doped polycrystalline silicon-germanium, or any number of other materials conventionally used in CMOS IC manufacturing.

[0179] (n) The hysteretic switching behavior of the FE material layer results in hysteresis in the NDR operating region of the FET device and thereby can constrain the operating ranges of drain-to-source voltage and gate voltage for the FET to operate with NDR. The capacitance of the FE material layer can be engineered to “match” the combined dielectric and semiconductor capacitance in order to reduce the hysteresis voltage of the NDR-FeFET below the hysteresis voltage (equal to two times the coercive voltage) of the FE material layer alone. When the FE material layer switches polarization, the voltage dropped across it will decrease (“snapback”) by an amount that is dependent on the relative capacitances of the FE material layer and the dielectric-semiconductor layers as well as the remanent polarization. These should be co-optimized to reduce the hysteresis voltage and maximize the change in transistor threshold voltage upon polarization switching within the FE material layer.

[0180] (o) FET design can be optimized to maximize the relative influence of the drain voltage (relative to the source voltage) on the FE material layer polarization state, so that a change in the drain voltage can cause the FE material layer polarization to switch. Specifically, the geometry and dielectric constant of the gate-sidewall dielectric spacers may be engineered to enhance capacitive coupling between the drain and the FE material layer and / or to decrease capacitive coupling between the source and the FE material layer. Other more detailed features of this aspect of the device of the present disclosure include source and drain dopant concentration profiles tailored to enhance the influence of the drain voltage on the FE material polarization state..

[0181] (p) A gate-sidewall dielectric spacer between the source and gate terminal can be incorporated which has a relatively low dielectric constant of approximately one to decrease capacitive coupling between the source andthe FE material layer. This feature can enhance polarization switching, such as making the FE material layer polarization completely switch with changes in the drain voltage.

[0182] (q) A transistor structure that includes the use of a thin semiconductor body to suppress sub-surface leakage current in the NDR region of operation. This “thin-body” structure can be achieved with a fully-depleted (FD) Silicon- On-Insulator (SOI) FET, FinFET, nanosheet or gate-all-around transistor with silicon thickness smaller than the channel length.

[0183] (r) Methods of operating the NDR FeFET devices are described above.

[0184] (s) Methods of making the structures and devices are described above. These include manufacturing processes that are compatible with conventional CMOS transistor fabrication techniques used in commercial IC manufacturing facilities, thus providing a substantial advantage over the prior art. An additional benefit lies in the fact that the onset voltage for the NDR mode can be adjusted during the manufacturing process.

[0185] 4. General Scope of Embodiments

[0186] From the description herein, it will be appreciated that the present disclosure encompasses multiple implementations of the technology which include, but are not limited to, the following:

[0187] A memory cell comprising: (a) a first negative differential resistance ferroelectric field effect transistor (NDR-FeFET) having each of a gate terminal and a source terminal configured to be connected to a storage node, and a drain terminal configured to be connected to a first voltage potential at a first node; (b) a second NDR-FeFET having each of a gate terminal and a source terminal configured to be connected to a second voltage potential at a second node, and a drain terminal configured to be connected to said storage node; and (c) a field-effect transistor (FET) configured to operate in an enhancement / non-NDR mode to transfer a voltage data value from a data line to the storage node or to transfer a voltage data value from the storage node to the data line in response to a write or read voltage signal respectively provided to the memory cell.

[0188] A memory cell comprising: (a) a first negative differential resistanceferroelectric field effect transistor (NDR-FeFET) having each of a gate terminal and a source terminal configured to be connected to a storage node, and a drain terminal configured to be connected to a first voltage potential at a first node; (b) a second NDR-FeFET having a source terminal configured to be connected to a second voltage potential at a second node, a gate terminal configured to receive a bias voltage signal, and a drain terminal configured to be connected to said storage node; and (c) a field-effect transistor (FET) configured to operate in an enhancement / non-NDR mode to transfer a voltage data value from a data line to the storage node or to transfer a voltage data value from the storage node to the data line in response to a write or read voltage signal respectively provided to the memory cell.

[0189] A memory cell comprising: (a) a first negative differential resistance ferroelectric field effect transistor (NDR-FeFET) having a source terminal configured to be connected to a storage node, a gate terminal configured to receive a first bias voltage signal, and a drain terminal configured to be connected to a first voltage potential at a first node; (b) a second NDR-FeFET having a source terminal configured to be connected to a second voltage potential at a second node, a gate terminal configured to receive a second bias voltage signal, and a drain terminal configured to be connected to said storage node; and (c) a field-effect transistor (FET) configured to operate in an enhancement / non-NDR mode to transfer a voltage data value from a data line to the storage node or to transfer a voltage data value from the storage node to the data line in response to a write or read voltage signal respectively provided to the memory cell.

[0190] A memory cell comprising: (a) a first negative differential resistance ferroelectric field effect transistor (NDR-FeFET) having each of a gate terminal and a source terminal configured to be connected to a storage node, and a drain terminal configured to be connected to a first voltage potential at a first node; (b) a second NDR-FeFET capable of nonvolatile operation, having a source terminal configured to be connected to a second voltage potential at a second node, a gate terminal configured to receive a bias voltage signal, and a drain terminal configured to be connected to said storage node; and (c) a field-effect transistor (FET) configured to operate in an enhancement / non-NDR mode to transfer a voltage data value from a data line to the storage node or to transfer a voltage data value from the storage node to the data line in response to a write or read voltage signal respectively provided to the memory cell.

[0191] A memory cell comprising: (a) a p-channel negative differential resistance ferroelectric field effect transistor (NDR-FeFET) having a drain terminal configured to be connected to a storage node, a gate terminal configured to be connected to an input node, and a source terminal configured to be connected to a first voltage potential at a first node; (b) an n- channel NDR-FeFET having a drain terminal configured to be connected to said storage node, a gate terminal configured to be connected to said input node, and a source terminal configured to be connected to a second voltage potential at a second node; (c) a first field-effect transistor configured to operate in an enhancement / non-NDR mode to transfer a voltage data value from a write data line to said input node in response to a write voltage signal provided to the memory cell; and (d) a second field-effect transistor configured to operate in an enhancement / non-NDR mode to transfer a voltage data value from said storage node to a read data line in response to a read voltage signal provided to the memory cell.

[0192] A method of operating a memory cell having a storage node comprising the steps of: (a) receiving or transferring a data value from or to a data line by gating a transfer field effect transistor (FET) in response to a write or read voltage signal, respectively, such that said transfer FET operates without a negative differential resistance (NDR) characteristic; (b) coupling a first negative differential resistance ferroelectric field effect transistor (NDR- FeFET) and a second NDR-FeFET in a latch configuration with said transfer FET so that said data value can be written to or read from said storage node via said transfer FET in the on state; and (c) operating said first NDR-FeFET and said second NDR-FeFET so that said data value is maintained at said storage node when said transfer FET is in the off state.

[0193] A method of operating a memory cell having a storage node comprising the steps of: (a) receiving or transferring a data value from or to a data line by gating a transfer field effect transistor (FET) in response to a writeor read voltage signal, respectively, such that said transfer FET operates without a negative differential resistance (NDR) characteristic; (b) coupling a negative differential resistance ferroelectric field effect transistor (NDR- FeFET) and a NDR-FeFET capable of nonvolatile operation in a latch configuration with said transfer FET so that said data value can be read from or written to the storage node via said transfer FET in the on state; (c) operating said NDR-FeFET and said NDR-FeFET capable of nonvolatile operation so that said data value is maintained at said storage node when said transfer FET is in the off state; and (d) powering down and up said memory cell in a manner that restores a previously stored data value at said storage node.

[0194] A method of operating a memory cell having an input node and a storage node comprising the steps of: (a) receiving an input data value from a write data line by gating a write transfer field effect transistor (FET) in response to a write voltage signal, such that said write transfer FET operates without a negative differential resistance (NDR) characteristic; (b) transferring a stored data value to a read data line by gating a read transfer FET in response to a read voltage signal, such that said read transfer FET operates without a NDR characteristic; (c) coupling a first a first negative differential resistance ferroelectric field effect transistor (NDR-FeFET) and a second NDR-FeFET in a bistable inverter configuration with said input node and with said write transfer FET so that said input data value can be transferred to the input node via said write transfer FET in the on state; (d) coupling said first NDR-FeFET and said second NDR-FeFET with said storage node and read transfer FET so that said stored data value can be written to said read data line via said read transfer FET in the on state; and (e) operating said first NDR-FeFET and said second NDR-FeFET so that said stored data value is maintained at said storage node when both said write transfer FET and said read transfer FET are in the off state.

[0195] The apparatus or method of any preceding implementation, wherein the memory cell uses a hysteretic negative differential resistance characteristic of said first NDR-FeFET and said second NDR-FeFET to maintain the state of said voltage data value at said storage node withenhanced stability.

[0196] The apparatus or method of any preceding implementation, wherein said storage node includes a source / drain region shared by said transfer FET and at least one of said first NDR-FeFET and said second NDR-FeFET.

[0197] The apparatus or method of any preceding implementation, wherein the memory cell uses a hysteretic negative differential resistance characteristic of said first NDR-FeFET and said second NDR-FeFET to maintain the state of said voltage data value at said storage node with enhanced stability.

[0198] The apparatus or method of any preceding implementation, wherein said storage node includes a source / drain region shared by said transfer FET and at least one of said first NDR-FeFET and said second NDR-FeFET.

[0199] The apparatus or method of any preceding implementation, wherein the memory cell uses a hysteretic negative differential resistance characteristic of said first NDR-FeFET and said second NDR-FeFET to maintain the state of said voltage data value at said storage node with enhanced stability.

[0200] The apparatus or method of any preceding implementation, wherein said storage node includes a source / drain region shared by said transfer FET and at least one of said NDR-FeFET and said FeFET.

[0201] The apparatus or method of any preceding implementation, wherein the memory cell uses a hysteretic negative differential resistance characteristic of said NDR-FeFET to maintain the state of said voltage data value at said storage node with enhanced stability and in a nonvolatile manner.

[0202] The apparatus or method of any preceding implementation, wherein said storage node includes a source / drain region shared by said transfer FET and at least one of said NDR-FeFET and said FeFET.

[0203] The apparatus or method of any preceding implementation, wherein the memory cell uses a hysteretic negative differential resistance characteristic of said p-channel and n-channel NDR-FeFETs to maintain the state of said voltage data value at said storage node with enhanced stability.

[0204] An integrated circuit comprising only three n-channel FETs, eachincluding a gate terminal, a source terminal, and a drain terminal, with one of the source or drain (source / drain) terminals of an “access” FET connected to a bitline and the other of the source / drain terminals of the access FET connected to a storage node of a bistable latch comprising two series- connected NDR-FeFETs. Specifically, the drain terminal of a first “pull-down” NDR-FeFET is connected to the source terminal of a second “pull-up” NDR- FeFET to form the data storage node, with the source terminal of the pulldown NDR-FeFET connected to a grounded or negatively biased voltage terminal (Vss) and the drain terminal of the pull-up NDR-FeFET connected to a power-supply voltage terminal (VDD). For each of the two NDR-FeFETs, the gate terminal is biased or connected within the integrated circuit such that the NDR-FeFET is in a conductive (“on”) state for small values of drain-to-source voltage (e.g., less than 100 mV in magnitude), and in a NDR state for large drain-to-source voltage (above approximately VDD / 2 in magnitude). Thus, the latch has two stable operating points near VDD and Vss, corresponding to points of intersection between the current-vs. -voltage (l-V) characteristic of the pull-up NDR-FeFET and the l-V characteristic of the pull-down NDR- FeFET. Therefore, this integrated circuit can function as a memory cell, with access to the data storage node provided via the access FET. In certain embodiments, one or both of the gate terminals of the NDR-FeFETs are connected to independent bias lines. In other embodiments, the pull-down NDR-FeFET has a high-current state when its gate-to-source voltage (VGS) is non-zero and a low-current state when its VGS = 0 Volts, and the gate terminal of the pull-down NDR-FeFET is connected to an independent bias line allowing the state of the cell to be restored after a power supply shutdown.

[0205] An integrated circuit comprising two n-channel FETs and one p- channel FET, each including a gate terminal, a source terminal, and a drain terminal, with one of the source or drain (source / drain) terminals of an n- channel “access” FET connected to a bitline and the other of the source / drain terminals of the access FET connected to a storage node of a bistable latch comprising series-connected p-channel and n-channel NDR-FeFETs. Specifically, the drain terminal of the n-channel NDR-FeFET is connected to the drain terminal of the p-channel NDR-FeFET to form the data storagenode, with the source terminal of the n-channel NDR-FeFET connected to a grounded or negatively biased voltage terminal (Vss) and the source terminal of the p-channel NDR-FeFET connected to a power-supply voltage terminal (VDD). For each of the two NDR-FeFETs, the gate terminal is biased such that the NDR-FeFET is in a conductive (“on”) state for small values of drain-to- source voltage (e.g., less than 100 mV), and in a NDR state for large drain-to- source voltage (above approximately VDD / 2). Thus, the latch has two stable operating points near VDD and Vss, corresponding to points of intersection between the current-vs. -voltage (l-V) characteristic of the p-channel NDR- FeFET and the l-V characteristic of the n-channel NDR-FeFET. Therefore, this integrated circuit can function as a memory cell, with access to the data storage node provided via the access FET.

[0206] An integrated circuit comprising four FETs, each including a gate terminal, a source terminal, and a drain terminal, with one of the source or drain (source / drain) terminals of a “read access” FET connected to a read bitline and the other of the source / drain terminals of the access FET connected to a storage node of a bistable latch comprising series-connected p-channel and n-channel NDR-FeFETs with their gate terminals connected together to form an input node, and with one of the source / drain terminals of a “write access” FET connected to a write bitline and the other of the source / drain terminals of the access FET connected to the input node of the bistable latch. Specifically, the drain terminal of the n-channel NDR-FeFET is connected to the drain terminal of the p-channel NDR-FeFET to form the data storage node, with the source terminal of the n-channel NDR-FeFET connected to a grounded or negatively biased voltage terminal (Vss) and the source terminal of the p-channel NDR-FeFET connected to a power-supply voltage terminal (VDD).

[0207] A memory cell comprising: a first negative differential resistance ferroelectric field effect transistor (NDR-FeFET) having each of a gate terminal and a source terminal configured to be connected to a storage node, and a drain terminal configured to be connected to a first voltage potential at a first node; a second NDR-FeFET having each of a gate terminal and a source terminal configured to be connected to a second voltage potential at a secondnode, and a drain terminal configured to be connected to said storage node; and a field-effect transistor (FET) configured to operate in an enhancement / non-NDR mode to transfer a voltage data value from a data line to the storage node or to transfer a voltage data value from the storage node to the data line in response to a write or read voltage signal respectively provided to the memory cell.

[0208] The memory cell of any preceding or following implementation, wherein the memory cell uses a hysteretic negative differential resistance characteristic of said first NDR-FeFET and said second NDR-FeFET to maintain the state of said voltage data value at said storage node with enhanced stability.

[0209] The memory cell of any preceding or following implementation, wherein said storage node includes a source / drain region shared by said transfer FET and at least one of said first NDR-FeFET and said second NDR-FeFET.

[0210] A memory cell comprising: a first negative differential resistance ferroelectric field effect transistor (NDR-FeFET) having each of a gate terminal and a source terminal configured to be connected to a storage node, and a drain terminal configured to be connected to a first voltage potential at a first node; a second NDR-FeFET having a source terminal configured to be connected to a second voltage potential at a second node, a gate terminal configured to receive a bias voltage signal, and a drain terminal configured to be connected to said storage node; and a field-effect transistor (FET) configured to operate in an enhancement / non-NDR mode to transfer a voltage data value from a data line to the storage node or to transfer a voltage data value from the storage node to the data line in response to a write or read voltage signal respectively provided to the memory cell.

[0211] The memory cell of any preceding or following implementation, wherein the memory cell uses a hysteretic negative differential resistance characteristic of said first NDR-FeFET and said second NDR-FeFET to maintain the state of said voltage data value at said storage node with enhanced stability.

[0212] The memory cell of any preceding or following implementation, wherein said storage node includes a source / drain region shared by said transfer FETand at least one of said first NDR-FeFET and said second NDR-FeFET.

[0213] A memory cell comprising: a first negative differential resistance ferroelectric field effect transistor (NDR-FeFET) having a source terminal configured to be connected to a storage node, a gate terminal configured to receive a first bias voltage signal, and a drain terminal configured to be connected to a first voltage potential at a first node; a second NDR-FeFET having a source terminal configured to be connected to a second voltage potential at a second node, a gate terminal configured to receive a second bias voltage signal, and a drain terminal configured to be connected to said storage node; and a field-effect transistor (FET) configured to operate in an enhancement / non-NDR mode to transfer a voltage data value from a data line to the storage node or to transfer a voltage data value from the storage node to the data line in response to a write or read voltage signal respectively provided to the memory cell.

[0214] The memory cell of any preceding or following implementation, wherein the memory cell uses a hysteretic negative differential resistance characteristic of said first NDR-FeFET and said second NDR-FeFET to maintain the state of said voltage data value at said storage node with enhanced stability.

[0215] The memory cell of any preceding or following implementation, wherein said storage node includes a source / drain region shared by said transfer FET and at least one of said NDR-FeFET and said FeFET.

[0216] A memory cell comprising: a first negative differential resistance ferroelectric field effect transistor (NDR-FeFET) having each of a gate terminal and a source terminal configured to be connected to a storage node, and a drain terminal configured to be connected to a first voltage potential at a first node; a second NDR-FeFET capable of nonvolatile operation, having a source terminal configured to be connected to a second voltage potential at a second node, a gate terminal configured to receive a bias voltage signal, and a drain terminal configured to be connected to said storage node; and a fieldeffect transistor (FET) configured to operate in an enhancement / non-NDR mode to transfer a voltage data value from a data line to the storage node or to transfer a voltage data value from the storage node to the data line inresponse to a write or read voltage signal respectively provided to the memory cell.

[0217] The memory cell of any preceding or following implementation, wherein the memory cell uses a hysteretic negative differential resistance characteristic of said NDR-FeFET to maintain the state of said voltage data value at said storage node with enhanced stability and in a nonvolatile manner.

[0218] The memory cell of any preceding or following implementation, wherein said storage node includes a source / drain region shared by said transfer FET and at least one of said NDR-FeFET and said FeFET.

[0219] A memory cell comprising: a p-channel negative differential resistance ferroelectric field effect transistor (NDR-FeFET) having a drain terminal configured to be connected to a storage node, a gate terminal configured to be connected to an input node, and a source terminal configured to be connected to a first voltage potential at a first node; an n-channel NDR-FeFET having a drain terminal configured to be connected to said storage node, a gate terminal configured to be connected to said input node, and a source terminal configured to be connected to a second voltage potential at a second node; a first field-effect transistor configured to operate in an enhancement / non-NDR mode to transfer a voltage data value from a write data line to said input node in response to a write voltage signal provided to the memory cell; and a second field-effect transistor configured to operate in an enhancement / non-NDR mode to transfer a voltage data value from said storage node to a read data line in response to a read voltage signal provided to the memory cell.

[0220] The memory cell of any preceding or following implementation, wherein the memory cell uses a hysteretic negative differential resistance characteristic of said p-channel and n-channel NDR-FeFETs to maintain the state of said voltage data value at said storage node with enhanced stability.

[0221] A method of operating a memory cell having a storage node comprising the steps of: receiving or transferring a data value from or to a data line by gating a transfer field effect transistor (FET) in response to a write or read voltage signal, respectively, such that said transfer FET operateswithout a negative differential resistance (NDR) characteristic; coupling a first negative differential resistance ferroelectric field effect transistor (NDR- FeFET) and a second NDR-FeFET in a latch configuration with said transfer FET so that said data value can be written to or read from said storage node via said transfer FET in the on state; and operating said first NDR-FeFET and said second NDR-FeFET so that said data value is maintained at said storage node when said transfer FET is in the off state.

[0222] A method of operating a memory cell having a storage node comprising the steps of: receiving or transferring a data value from or to a data line by gating a transfer field effect transistor (FET) in response to a write or read voltage signal, respectively, such that said transfer FET operates without a negative differential resistance (NDR) characteristic; coupling a negative differential resistance ferroelectric field effect transistor (NDR- FeFET) and a NDR-FeFET capable of nonvolatile operation in a latch configuration with said transfer FET so that said data value can be read from or written to the storage node via said transfer FET in the on state; operating said NDR-FeFET and said NDR-FeFET capable of nonvolatile operation so that said data value is maintained at said storage node when said transfer FET is in the off state; and powering down and up said memory cell in a manner that restores a previously stored data value at said storage node.

[0223] A method of operating a memory cell having an input node and a storage node comprising the steps of: receiving an input data value from a write data line by gating a write transfer field effect transistor (FET) in response to a write voltage signal, such that said write transfer FET operates without a negative differential resistance (NDR) characteristic; transferring a stored data value to a read data line by gating a read transfer FET in response to a read voltage signal, such that said read transfer FET operates without a NDR characteristic; coupling a first a first negative differential resistance ferroelectric field effect transistor (NDR-FeFET) and a second NDR-FeFET in a bistable inverter configuration with said input node and with said write transfer FET so that said input data value can be transferred to the input node via said write transfer FET in the on state; coupling said first NDR- FeFET and said second NDR-FeFET with said storage node and readtransfer FET so that said stored data value can be written to said read data line via said read transfer FET in the on state; and operating said first NDR- FeFET and said second NDR-FeFET so that said stored data value is maintained at said storage node when both said write transfer FET and said read transfer FET are in the off state.

[0224] As used herein, the term "implementation" is intended to include, without limitation, embodiments, examples, or other forms of practicing the technology described herein.

[0225] As used herein, the singular terms "a," "an," and "the" may include plural referents unless the context clearly dictates otherwise. Reference to an object in the singular is not intended to mean "one and only one" unless explicitly so stated, but rather "one or more."

[0226] Phrasing constructs, such as “A, B and / or C”, within the present disclosure describe where either A, B, or C can be present, or any combination of items A, B and C. Phrasing constructs indicating, such as “at least one of” followed by listing a group of elements, indicates that at least one of these groups of elements is present, which includes any possible combination of the listed elements as applicable.

[0227] References in this disclosure referring to “an embodiment”, “at least one embodiment” or similar embodiment wording indicates that a particular feature, structure, or characteristic described in connection with a described embodiment is included in at least one embodiment of the present disclosure. Thus, these various embodiment phrases are not necessarily all referring to the same embodiment, or to a specific embodiment which differs from all the other embodiments being described. The embodiment phrasing should be construed to mean that the particular features, structures, or characteristics of a given embodiment may be combined in any suitable manner in one or more embodiments of the disclosed apparatus, system, or method.

[0228] As used herein, the term "set" refers to a collection of one or more objects. Thus, for example, a set of objects can include a single object or multiple objects.

[0229] Relational terms such as first and second, top and bottom, upper and lower, left and right, and the like, may be used solely to distinguish one entityor action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions.

[0230] The terms "comprises," "comprising," "has", "having," "includes", "including," "contains", "containing" or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, apparatus, or system, that comprises, has, includes, or contains a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, apparatus, or system. An element proceeded by "comprises . . . a", "has . . . a", "includes . . . a", "contains . . . a" does not, without more constraints, preclude the existence of additional identical elements in the process, method, article, apparatus, or system, that comprises, has, includes, contains the element.

[0231] As used herein, the terms "approximately", "approximate", "substantially", "substantial", "essentially", and "about", or any other version thereof, are used to describe and account for small variations. When used in conjunction with an event or circumstance, the terms can refer to instances in which the event or circumstance occurs precisely as well as instances in which the event or circumstance occurs to a close approximation. When used in conjunction with a numerical value, the terms can refer to a range of variation of less than or equal to ± 10% of that numerical value, such as less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1 %, less than or equal to ±0.5%, less than or equal to ±0.1 %, or less than or equal to ±0.05%. For example, "substantially" aligned can refer to a range of angular variation of less than or equal to ±10°, such as less than or equal to ±5°, less than or equal to ±4°, less than or equal to ±3°, less than or equal to ±2°, less than or equal to ±1 °, less than or equal to ±0.5°, less than or equal to ±0.1 °, or less than or equal to ±0.05°.

[0232] Additionally, amounts, ratios, and other numerical values may sometimes be presented herein in a range format. It is to be understood that such range format is used for convenience and brevity and should be understood flexibly to include numerical values explicitly specified as limits ofa range, but also to include all individual numerical values or sub-ranges encompassed within that range as if each numerical value and sub-range is explicitly specified. For example, a ratio in the range of about 1 to about 200 should be understood to include the explicitly recited limits of about 1 and about 200, but also to include individual ratios such as about 2, about 3, and about 4, and sub-ranges such as about 10 to about 50, about 20 to about 100, and so forth.

[0233] The term "coupled" as used herein is defined as connected, although not necessarily directly and not necessarily mechanically. A device or structure that is "configured" in a certain way is configured in at least that way, but may also be configured in ways that are not listed.

[0234] Benefits, advantages, solutions to problems, and any element(s) that may cause any benefit, advantage, or solution to occur or become more pronounced are not to be construed as a critical, required, or essential feature or element of the technology described herein or any or all the claims.

[0235] In addition, in the foregoing disclosure various features may be grouped together in various embodiments for the purpose of streamlining the disclosure. This method of disclosure is not to be interpreted as reflecting an intention that the claimed embodiments require more features than are expressly recited in each claim. Inventive subject matter can lie in less than all features of a single disclosed embodiment.

[0236] The abstract of the disclosure is provided to allow the reader to quickly ascertain the nature of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.

[0237] It will be appreciated that the practice of some jurisdictions may require deletion of one or more portions of the disclosure after the application is filed. Accordingly, the reader should consult the application as filed for the original content of the disclosure. Any deletion of content of the disclosure should not be construed as a disclaimer, forfeiture, or dedication to the public of any subject matter of the application as originally filed.

[0238] All text in a drawing figure is hereby incorporated into the disclosure and is to be treated as part of the written description of the drawing figure.

[0239] The following claims are hereby incorporated into the disclosure, with each claim standing on its own as a separately claimed subject matter.

[0240] Although the description herein contains many details, these should not be construed as limiting the scope of the disclosure, but as merely providing illustrations of some of the presently preferred embodiments. Therefore, it will be appreciated that the scope of the disclosure fully encompasses other embodiments which may become obvious to those skilled in the art.

[0241] All structural and functional equivalents to the elements of the disclosed embodiments that are known to those of ordinary skill in the art are expressly incorporated herein by reference and are intended to be encompassed by the present claims. Furthermore, no element, component, or method step in the present disclosure is intended to be dedicated to the public regardless of whether the element, component, or method step is explicitly recited in the claims. No claim element herein is to be construed as a "means plus function" element unless the element is expressly recited using the phrase "means for". No claim element herein is to be construed as a "step plus function" element unless the element is expressly recited using the phrase "step for".

Claims

CLAIMSWhat is claimed is:1 . A memory cell comprising: a first negative differential resistance ferroelectric field effect transistor (NDR- FeFET) having each of a gate terminal and a source terminal configured to be connected to a storage node, and a drain terminal configured to be connected to a first voltage potential at a first node; a second NDR-FeFET having each of a gate terminal and a source terminal configured to be connected to a second voltage potential at a second node, and a drain terminal configured to be connected to said storage node; and a field-effect transistor (FET) configured to operate in an enhancement / non- NDR mode to transfer a voltage data value from a data line to the storage node or to transfer a voltage data value from the storage node to the data line in response to a write or read voltage signal respectively provided to the memory cell.

2. The memory cell of claim 1 , wherein the memory cell uses a hysteretic negative differential resistance characteristic of said first NDR-FeFET and said second NDR-FeFET to maintain the state of said voltage data value at said storage node with enhanced stability.

3. The memory cell of claim 1 , wherein said storage node includes a source / drain region shared by said transfer FET and at least one of said first NDR- FeFET and said second NDR-FeFET.

4. A memory cell comprising: a first negative differential resistance ferroelectric field effect transistor (NDR- FeFET) having each of a gate terminal and a source terminal configured to be connected to a storage node, and a drain terminal configured to be connected to a first voltage potential at a first node; a second NDR-FeFET having a source terminal configured to be connected to a second voltage potential at a second node, a gate terminal configured to receive abias voltage signal, and a drain terminal configured to be connected to said storage node; and a field-effect transistor (FET) configured to operate in an enhancement / non- NDR mode to transfer a voltage data value from a data line to the storage node or to transfer a voltage data value from the storage node to the data line in response to a write or read voltage signal respectively provided to the memory cell.

5. The memory cell of claim 4, wherein the memory cell uses a hysteretic negative differential resistance characteristic of said first NDR-FeFET and said second NDR-FeFET to maintain the state of said voltage data value at said storage node with enhanced stability.

6. The memory cell of claim 4, wherein said storage node includes a source / drain region shared by said transfer FET and at least one of said first NDR- FeFET and said second NDR-FeFET.

7. A memory cell comprising: a first negative differential resistance ferroelectric field effect transistor (NDR- FeFET) having a source terminal configured to be connected to a storage node, a gate terminal configured to receive a first bias voltage signal, and a drain terminal configured to be connected to a first voltage potential at a first node; a second NDR-FeFET having a source terminal configured to be connected to a second voltage potential at a second node, a gate terminal configured to receive a second bias voltage signal, and a drain terminal configured to be connected to said storage node; and a field-effect transistor (FET) configured to operate in an enhancement / non- NDR mode to transfer a voltage data value from a data line to the storage node or to transfer a voltage data value from the storage node to the data line in response to a write or read voltage signal respectively provided to the memory cell.

8. The memory cell of claim 7, wherein the memory cell uses a hysteretic negative differential resistance characteristic of said first NDR-FeFET and said second NDR-FeFET to maintain the state of said voltage data value at said storagenode with enhanced stability.

9. The memory cell of claim 7, wherein said storage node includes a source / drain region shared by said transfer FET and at least one of said NDR- FeFET and said FeFET.

10. A memory cell comprising: a first negative differential resistance ferroelectric field effect transistor (NDR- FeFET) having each of a gate terminal and a source terminal configured to be connected to a storage node, and a drain terminal configured to be connected to a first voltage potential at a first node; a second NDR-FeFET capable of nonvolatile operation, having a source terminal configured to be connected to a second voltage potential at a second node, a gate terminal configured to receive a bias voltage signal, and a drain terminal configured to be connected to said storage node; and a field-effect transistor (FET) configured to operate in an enhancement / non- NDR mode to transfer a voltage data value from a data line to the storage node or to transfer a voltage data value from the storage node to the data line in response to a write or read voltage signal respectively provided to the memory cell.11 . The memory cell of claim 10, wherein the memory cell uses a hysteretic negative differential resistance characteristic of said NDR-FeFET to maintain the state of said voltage data value at said storage node with enhanced stability and in a nonvolatile manner.

12. The memory cell of claim 10, wherein said storage node includes a source / drain region shared by said transfer FET and at least one of said NDR- FeFET and said FeFET.

13. A memory cell comprising: a p-channel negative differential resistance ferroelectric field effect transistor (NDR-FeFET) having a drain terminal configured to be connected to a storage node, a gate terminal configured to be connected to an input node, and a source terminalconfigured to be connected to a first voltage potential at a first node; an n-channel NDR-FeFET having a drain terminal configured to be connected to said storage node, a gate terminal configured to be connected to said input node, and a source terminal configured to be connected to a second voltage potential at a second node; a first field-effect transistor configured to operate in an enhancement / non- NDR mode to transfer a voltage data value from a write data line to said input node in response to a write voltage signal provided to the memory cell; and a second field-effect transistor configured to operate in an enhancement / non- NDR mode to transfer a voltage data value from said storage node to a read data line in response to a read voltage signal provided to the memory cell.

14. The memory cell of claim 13, wherein the memory cell uses a hysteretic negative differential resistance characteristic of said p-channel and n- channel NDR-FeFETs to maintain the state of said voltage data value at said storage node with enhanced stability.

15. A method of operating a memory cell having a storage node comprising the steps of: receiving or transferring a data value from or to a data line by gating a transfer field effect transistor (FET) in response to a write or read voltage signal, respectively, such that said transfer FET operates without a negative differential resistance (NDR) characteristic; coupling a first negative differential resistance ferroelectric field effect transistor (NDR-FeFET) and a second NDR-FeFET in a latch configuration with said transfer FET so that said data value can be written to or read from said storage node via said transfer FET in the on state; and operating said first NDR-FeFET and said second NDR-FeFET so that said data value is maintained at said storage node when said transfer FET is in the off state.

16. A method of operating a memory cell having a storage node comprising the steps of:receiving or transferring a data value from or to a data line by gating a transfer field effect transistor (FET) in response to a write or read voltage signal, respectively, such that said transfer FET operates without a negative differential resistance (NDR) characteristic; coupling a negative differential resistance ferroelectric field effect transistor (NDR-FeFET) and a NDR-FeFET capable of nonvolatile operation in a latch configuration with said transfer FET so that said data value can be read from or written to the storage node via said transfer FET in the on state; operating said NDR-FeFET and said NDR-FeFET capable of nonvolatile operation so that said data value is maintained at said storage node when said transfer FET is in the off state; and powering down and up said memory cell in a manner that restores a previously stored data value at said storage node.

17. A method of operating a memory cell having an input node and a storage node comprising the steps of: receiving an input data value from a write data line by gating a write transfer field effect transistor (FET) in response to a write voltage signal, such that said write transfer FET operates without a negative differential resistance (NDR) characteristic; transferring a stored data value to a read data line by gating a read transfer FET in response to a read voltage signal, such that said read transfer FET operates without a NDR characteristic; coupling a first a first negative differential resistance ferroelectric field effect transistor (NDR-FeFET) and a second NDR-FeFET in a bistable inverter configuration with said input node and with said write transfer FET so that said input data value can be transferred to the input node via said write transfer FET in the on state; coupling said first NDR-FeFET and said second NDR-FeFET with said storage node and read transfer FET so that said stored data value can be written to said read data line via said read transfer FET in the on state; and operating said first NDR-FeFET and said second NDR-FeFET so that said stored data value is maintained at said storage node when both said write transfer FET and said read transfer FET are in the off state.

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