Array substrate and display apparatus

Abstract

Provided in the present disclosure are an array substrate and a display apparatus. The array substrate comprises a plurality of first signal lines and a plurality of second signal lines, wherein a first gate driving module is electrically connected to the plurality of first signal lines; a second gate driving module is electrically connected to the plurality of second signal lines; the plurality of first signal lines comprise at least one first-part first signal line and at least one second-part first signal line; the plurality of second signal lines comprise at least one first-part second signal line and at least one second-part second signal line; the first-part first signal line is electrically connected to a pin by means of a first trace; the first-part second signal line is electrically connected to a pin by means of a second trace; the second-part first signal line is electrically connected to the corresponding first-part second signal line by means of a connecting line disposed in a fourth frame area; and the second-part second signal line is electrically connected to the corresponding first-part first signal line by means of a connecting line disposed in the fourth frame area. The present disclosure saves space occupied by PLG traces.

Description

Array substrate and display device Technical Field

[0001] This disclosure relates to the field of display technology, and more particularly to an array substrate and a display device. Background Technology

[0002] In related technologies, as panel resolution and panel size continue to increase, in order to ensure pixel charging rate and the driving capability of GOA (Gate On Array, gate drive circuit set on array substrate) circuit, the number of clock signal lines is also increasing, from the initial two clock signal lines to the currently commonly used 10 clock signal lines, 12 clock signal lines, and even 16 clock signal lines. The increased number of clock signal lines has three main impacts: First, it places higher demands on the level shifters (level converters) in the driver integrated circuits, requiring more signal channels and increasing the cost of level shifters. Second, it increases the number of pins on the bonding leads of the panel, requiring a reduction in the width of individual pins or the spacing between pins, which increases the probability of pin misses. Third, the GOA (Glass Outer Array) circuits of a typical panel are located on the left and right bezels. The signal lines electrically connected to the GOA circuits need to be routed from the bonding area to the left and right bezels of the panel, and the traces in between are PLG (Pattern Line On Glass) traces. The clock signal is a square wave signal, and its frequency is related to the panel's resolution and refresh rate. One clock signal line typically connects multiple GOA circuits. The TFTs (Thin Film Transistors) in the GOA circuits have parasitic capacitance, so the clock signal line generates charging and discharging current during normal operation. The magnitude of the current is usually related to the clock signal frequency, the total resistance of the clock signal line, and the size of the parasitic capacitance on the clock signal line. The current on the clock signal lines ultimately converges at the PLG trace, where the current is at its maximum. When there are many clock signal lines, the layout space for the PLG traces is limited, and the PLG traces corresponding to each clock signal line need to be narrowed. After the PLG traces are narrowed, the resistance per unit length at the PLG traces increases. When the current remains constant, the increased resistance will cause more heat to be generated at that location, and the temperature at that location will rise. Therefore, in high-resolution, high-refresh-rate display products, the temperature of the PLG traces is a challenging issue.

[0003] Summary of the Invention

[0004] In one aspect, embodiments of this disclosure provide an array substrate, including a first gate driving module disposed in a first border region, a second gate driving module disposed in a second border region, and a bonding region disposed in a third border region; the array substrate further includes a plurality of first signal lines and a plurality of second signal lines, at least a portion of the first signal lines being disposed in the first border region, and at least a portion of the second signal lines being disposed in the second border region; the first border region and the second border region are disposed on opposite sides of a display region;

[0005] The first gate driving module is electrically connected to the plurality of first signal lines and is used to receive electrical signals provided by the first signal lines; the second gate driving module is electrically connected to the plurality of second signal lines and is used to receive electrical signals provided by the second signal lines.

[0006] The plurality of first signal lines include at least one first portion first signal line and at least one second portion first signal line; the plurality of second signal lines include at least one first portion second signal line and at least one second portion second signal line;

[0007] The first signal line of the first portion is electrically connected to the pin disposed in the bonding area through the first trace; at least a portion of the first trace is disposed in the first wiring space, and the first wiring space is disposed between the first border area and the bonding area;

[0008] The first portion of the second signal line is electrically connected to a pin disposed in the bonding area via a second trace; at least a portion of the second trace is disposed in a second wiring space; the second wiring space is disposed between the second border area and the bonding area;

[0009] The second part of the first signal line is electrically connected to the corresponding first part of the second signal line through the connecting line disposed in the fourth frame area; the second part of the second signal line is electrically connected to the corresponding first part of the first signal line through the connecting line disposed in the fourth frame area.

[0010] The third border area and the fourth border area are located on opposite sides of the display area.

[0011] Optionally, the width of the first trace is greater than the width of the first signal line, and the width of the second trace is greater than the width of the second signal line.

[0012] Optionally, the width of the connecting line is greater than the width of the first signal line, and the width of the connecting line is greater than the width of the second signal line.

[0013] Optionally, the first signal line is electrically connected to the second signal line via a connecting line disposed in the fourth frame region.

[0014] Optionally, the plurality of first signal lines include a plurality of first-side clock signal lines, and the plurality of second signal lines include a plurality of second-side clock signal lines;

[0015] The plurality of first-side clock signal lines include at least one first-part first-side clock signal line and at least one second-part first-side clock signal line; the plurality of second signal lines include at least one first-part second-side clock signal line and at least one second-part second-side clock signal line.

[0016] A portion of the plurality of first-side clock signal lines are electrically connected to pins located in the bonding area via the first trace.

[0017] A portion of the multiple second-side clock signal lines are electrically connected to pins located in the bonding area via the second trace.

[0018] Optionally, the second part first-side clock signal line is electrically connected to the corresponding first part second-side clock signal line via the connecting line, and the second part second-side clock signal line is electrically connected to the corresponding first part first-side clock signal line via the connecting line.

[0019] 7. The array substrate as claimed in claim 6, wherein the plurality of first signal lines include 2N first-side clock signal lines, and the plurality of second signal lines include 2N second-side clock signal lines; N is a positive integer;

[0020] The 2n-1th first-side clock signal line is electrically connected to the pin located in the bonding area through the first trace;

[0021] The 2nth second-side clock signal line is electrically connected to the pin located in the bonding area via the second trace;

[0022] n is a positive integer less than or equal to N.

[0023] Optionally, the 2nth first-side clock signal line and the 2nth second-side clock signal line are electrically connected through the connecting line;

[0024] The 2n-1th second-side clock signal line is electrically connected to the 2n-1th first-side clock signal line via the connecting line.

[0025] Optionally, the plurality of first signal lines include a first-side start signal line and a first-side power supply voltage line, and the plurality of second signal lines include a second-side start signal line and a second-side power supply voltage line;

[0026] The first-side start signal line is electrically connected to the pin located in the bonding area via a corresponding first trace;

[0027] The second-side power supply voltage line is electrically connected to the pin located in the bonding area via a corresponding second trace;

[0028] The first-side start signal line is electrically connected to the first-stage gate drive circuit included in the first gate drive module, and the second-side start signal line is electrically connected to the first-stage gate drive circuit included in the second gate drive module.

[0029] Optionally, the first-side start signal line is electrically connected to the second-side start signal line via the connecting line; the second-side power supply voltage line is electrically connected to the first-side power supply voltage line via the connecting line.

[0030] Optionally, the plurality of first signal lines include a first first-side start signal line and a second first-side start signal line, and the plurality of second signal lines include a first second-side start signal line and a second second-side start signal line;

[0031] The first first-side start signal line is electrically connected to a corresponding pin located in the bonding area via the first trace;

[0032] The second second-side start signal line is electrically connected to the corresponding pin located in the bonding area via the second trace.

[0033] Optionally, the first first-side start signal line is electrically connected to the first second-side start signal line via the connecting line, and the second second-side start signal line is electrically connected to the second first-side start signal line via the connecting line.

[0034] Optionally, the first first-side start signal line is electrically connected to the first-stage gate drive circuit of the first gate drive module, and the second first-side start signal line is electrically connected to the second-stage gate drive circuit of the first gate drive module; the first second-side start signal line is electrically connected to the first-stage gate drive circuit of the second gate drive module, and the second second-side start signal line is electrically connected to the second-stage gate drive circuit of the second gate drive module; or;

[0035] The first first-side start signal line is electrically connected to the first-stage gate drive circuit of the second gate drive module, and the first second-side start signal line is electrically connected to the first-stage gate drive circuit of the first gate drive module.

[0036] Optionally, the plurality of first signal lines include a first first-side power supply voltage line and a second first-side power supply voltage line, and the plurality of second signal lines include a first second-side power supply voltage line and a second second-side power supply voltage line;

[0037] The first power supply voltage line on the first side is electrically connected to the corresponding pin located in the bonding area through the first trace;

[0038] The second power supply voltage line on the second side is electrically connected to the corresponding pin located in the bonding area via the second trace.

[0039] Optionally, the first power supply voltage line on the first side is electrically connected to the first power supply voltage line on the second side through the connecting line, and the second power supply voltage line on the second side is electrically connected to the second power supply voltage line on the first side through the connecting line;

[0040] The first power supply voltage line on the first side and the first power supply voltage line on the second side are respectively connected to different levels of gate drive circuits of different gate drive modules, or the first power supply voltage line on the first side and the first power supply voltage line on the second side are connected to the same level of gate drive circuit of the same gate drive module.

[0041] Optionally, the plurality of first signal lines include a first-side high-voltage line and a first-side low-voltage line, and the plurality of second signal lines include a second-side high-voltage line and a second-side low-voltage line;

[0042] The first high-voltage line is electrically connected to a corresponding pin located in the bonding area via the first trace.

[0043] The second low-voltage line is electrically connected to the corresponding pin located in the bonding area via the second trace.

[0044] Optionally, the first low-voltage line is electrically connected to the second low-voltage line via the connecting line;

[0045] The second high-voltage line is electrically connected to the first high-voltage line via the connecting line.

[0046] Optionally, the plurality of first signal lines further includes M first-side clock signal lines, and the plurality of second signal lines further includes M second-side clock signal lines; M is a positive integer;

[0047] The first-side clock signal line is electrically connected to a corresponding pin in the bonding area via a first trace disposed in the first wiring space.

[0048] The second-side clock signal line is electrically connected to a corresponding pin in the bonding area via a second trace provided in the second wiring space.

[0049] The m-th first-side clock signal line is electrically connected to the m-th second-side clock signal line via a connecting line located in the fourth border area; m is a positive integer less than or equal to M.

[0050] In a second aspect, embodiments of this disclosure provide a display device including the array substrate described above. Attached Figure Description

[0051] Figure 1A is a structural diagram of an array substrate according to at least one embodiment of the present disclosure;

[0052] Figure 1B is a structural diagram of an array substrate according to at least one embodiment of the present disclosure;

[0053] Figure 1C is a structural diagram of an array substrate according to at least one embodiment of the present disclosure;

[0054] Figure 2A is a structural diagram of an array substrate according to at least one embodiment of the present disclosure;

[0055] Figure 2B is a structural diagram of an array substrate according to at least one embodiment of the present disclosure;

[0056] Figure 3A is a structural diagram of an array substrate according to at least one embodiment of the present disclosure;

[0057] Figure 3B is a structural diagram of an array substrate according to at least one embodiment of the present disclosure;

[0058] Figure 4A is a structural diagram of an array substrate according to at least one embodiment of the present disclosure;

[0059] Figure 4B is a structural diagram of an array substrate according to at least one embodiment of the present disclosure;

[0060] Figure 5 is a structural diagram of the array substrate according to at least one embodiment of the present disclosure;

[0061] Figure 6A is a structural diagram of an array substrate according to at least one embodiment of the present disclosure;

[0062] Figure 6B is a structural diagram of an array substrate according to at least one embodiment of the present disclosure;

[0063] Figure 7A is a structural diagram of an array substrate according to at least one embodiment of the present disclosure;

[0064] Figure 7B is a structural diagram of an array substrate according to at least one embodiment of the present disclosure;

[0065] Figure 8A is a structural diagram of an array substrate according to at least one embodiment of the present disclosure;

[0066] Figure 8B is a structural diagram of an array substrate according to at least one embodiment of the present disclosure;

[0067] Figure 9A is a structural diagram of an array substrate according to at least one embodiment of the present disclosure;

[0068] Figure 9B is a structural diagram of an array substrate according to at least one embodiment of the present disclosure;

[0069] Figure 10 is a structural diagram of an array substrate according to at least one embodiment of the present disclosure;

[0070] Figure 11 is a structural diagram of an array substrate according to at least one embodiment of the present disclosure. Detailed Implementation

[0071] The technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. Based on the embodiments of this disclosure, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this disclosure.

[0072] In all embodiments of this disclosure, the transistors used can be thin-film transistors, field-effect transistors, or other devices with similar characteristics. In the embodiments of this disclosure, to distinguish the two terminals of the transistor other than the gate, one terminal is referred to as the first terminal and the other as the second terminal.

[0073] In actual operation, when the transistor is a thin-film transistor or a field-effect transistor, the first electrode can be the drain and the second electrode can be the source; or, the first electrode can be the source and the second electrode can be the drain.

[0074] The array substrate described in this embodiment includes a first gate driving module disposed in the first frame region, a second gate driving module disposed in the second frame region, and a bonding region disposed in the third frame region; the array substrate also includes a plurality of first signal lines and a plurality of second signal lines, at least a portion of the first signal lines being disposed in the first frame region, and the second signal lines being disposed in the second frame region; the first frame region and the second frame region are disposed on opposite sides of the display area;

[0075] The first gate driving module is electrically connected to the plurality of first signal lines and is used to receive electrical signals provided by the first signal lines; the second gate driving module is electrically connected to the plurality of second signal lines and is used to receive electrical signals provided by the second signal lines.

[0076] The plurality of first signal lines include at least one first portion first signal line and at least one second portion first signal line; the plurality of second signal lines include at least one first portion second signal line and at least one second portion second signal line;

[0077] The first signal line in the first portion is electrically connected to a pin disposed in the bonding area via a first trace; at least a portion of the first trace is disposed in a first wiring space; the first wiring space is disposed between the first border area and the bonding area;

[0078] The first portion of the second signal line is electrically connected to a pin disposed in the bonding area via a second trace; at least a portion of the second trace is disposed in a second wiring space; the second wiring space is disposed between the second border area and the bonding area;

[0079] The second part of the first signal line is electrically connected to the corresponding first part of the second signal line through the connecting line disposed in the fourth frame area; the second part of the second signal line is electrically connected to the corresponding first part of the first signal line through the connecting line disposed in the fourth frame area.

[0080] The third border area and the fourth border area are located on opposite sides of the display area.

[0081] In at least one embodiment of this disclosure, a driver integrated circuit may be disposed in the bonding area; the driver integrated circuit provides corresponding electrical signals to each signal line; or,

[0082] A flexible circuit board can be bonded to the bonding area, and a driver integrated circuit can be disposed on the flexible circuit board to provide corresponding electrical signals to each signal line.

[0083] In at least one embodiment of this disclosure, a first portion of the first signal lines among a plurality of first signal lines disposed in the first frame region is configured to be electrically connected to a corresponding pin disposed in the bonding region via a first trace, and a first portion of the second signal lines among a plurality of second signal lines disposed in the second frame region is configured to be electrically connected to a corresponding pin disposed in the bonding region via a second trace. The first trace and the second trace are PLG traces, which are disposed in the PLG wiring space. This reduces the number of PLG traces, increases the linewidth of the PLG traces, prevents the temperature at the PLG traces from rising, and effectively improves the problems of a large number of signal channels, insufficient PLG wiring space, and too many bonding pins in the driver integrated circuits of high-resolution and high-refresh-rate display panels.

[0084] In at least one embodiment of this disclosure, the second portion of the first signal line is electrically connected to the corresponding first portion of the second signal line via a connecting line disposed in the fourth border area, and receives the electrical signal provided by the first portion of the second signal line;

[0085] The second part of the second signal line is electrically connected to the corresponding first part of the first signal line through a connecting line disposed in the fourth border area, and receives the electrical signal provided by the first part of the first signal line.

[0086] Optionally, the first border area can be located on the left side of the display area, the second border area can be located on the right side of the display area, the third border area can be located on the lower side of the display area, and the fourth border area can be located on the upper side of the display area.

[0087] In at least one embodiment of this disclosure, in the display panel, a first gate driving module is disposed on the left side of the display area, and a second gate driving module is disposed on the right side of the display area. For a scan line, there is a GOA circuit at each end to drive the scan line. This is necessary in large-size display products or high-resolution display products to ensure that the pixel resolution is high enough. The left and right bezels of the display panel are relatively tight in space due to the layout of the gate driving module and signal lines. However, the top bezel of the display panel does not have special routing requirements. Generally, a ground line is needed for electrostatic discharge protection and a common electrode line is needed for the uniformity of the common electrode in the plane. The wiring space of the top bezel of the display panel is sufficient, so the space of the top bezel can be used to save space for PLG routing.

[0088] In at least one embodiment of this disclosure, the line width of the first trace is greater than the line width of the first signal line, and the line width of the second trace is greater than the line width of the second signal line.

[0089] In practical implementation, the line width of the first trace can be set to be greater than the line width of the first signal line, and the line width of the second trace can be set to be greater than the line width of the second signal line, so that the resistance per unit length of the first trace and the resistance per unit length of the second trace can be set to be smaller, thereby reducing the heat generation of the first trace and the heat generation of the second trace.

[0090] In at least one embodiment of this disclosure, the line width of the connecting line is greater than the width of the first signal line, and the line width of the connecting line is greater than the line width of the second signal line.

[0091] In practical implementation, the line width of the connecting line set in the fourth border area can be set to be greater than the line width of the first signal line, and the line width of the connecting line can be set to be greater than the line width of the second signal line, so as to improve the signal delay problem.

[0092] Optionally, the first signal line is electrically connected to the second signal line via a connecting line disposed in the fourth frame region.

[0093] In a specific implementation, the first signal line located in the first frame area can be electrically connected to the corresponding second signal line located in the second frame area through the connecting line located in the fourth frame area, thereby enhancing the signal driving capability.

[0094] In at least one embodiment of this disclosure, the plurality of first signal lines include a plurality of first-side clock signal lines, and the plurality of second signal lines include a plurality of second-side clock signal lines;

[0095] The plurality of first-side clock signal lines include at least one first-part first-side clock signal line and at least one second-part first-side clock signal line; the plurality of second signal lines include at least one first-part second-side clock signal line and at least one second-part second-side clock signal line.

[0096] A portion of the plurality of first-side clock signal lines are electrically connected to pins located in the bonding area via the first trace.

[0097] A portion of the multiple second-side clock signal lines are electrically connected to pins located in the bonding area via the second trace.

[0098] Optionally, the second part first-side clock signal line is electrically connected to the corresponding first part second-side clock signal line via the connecting line, and the second part second-side clock signal line is electrically connected to the corresponding first part first-side clock signal line via the connecting line.

[0099] In at least one embodiment of this disclosure, the plurality of first signal lines includes 2N first-side clock signal lines, and the plurality of second signal lines includes 2N second-side clock signal lines; N is a positive integer;

[0100] The 2n-1th first-side clock signal line is electrically connected to the pin located in the bonding area through the first trace;

[0101] The 2nth second-side clock signal line is electrically connected to the pin located in the bonding area via the second trace;

[0102] n is a positive integer less than or equal to N.

[0103] In a specific implementation, 2N first-side clock signal lines can be set in the first frame area, and 2N second-side clock signal lines can be set in the second frame area. In the first frame area, the odd-numbered first-side clock signal lines are electrically connected to the pins set in the bonding area through the first trace, and in the second frame area, the even-numbered second-side clock signal lines are electrically connected to the pins set in the bonding area through the second trace.

[0104] Optionally, the 2nth first-side clock signal line and the 2nth second-side clock signal line are electrically connected through the connecting line;

[0105] The 2n-1th second-side clock signal line is electrically connected to the 2n-1th first-side clock signal line via the connecting line.

[0106] In specific implementation, the even-numbered first-side clock signal lines are electrically connected to the even-numbered second-side clock signal lines via connecting lines located in the fourth border area, and the odd-numbered first-side clock signal lines are electrically connected to the odd-numbered second-side clock signal lines via connecting lines located in the fourth border area.

[0107] As shown in Figures 1A and 1B, in this disclosure, multiple first signal lines include multiple first-side clock signal lines, multiple second signal lines include multiple second-side clock signal lines, the first signal lines include a first portion of first signal lines (the first portion of first signal lines may include CLK11 and CLK31) and a second portion of first signal lines (the second portion of first signal lines may include CLK21 and CLK41), the second signal lines include a first portion of second signal lines (the first portion of second signal lines may include CLK22 and CLK42) and a second portion of second signal lines (the second portion of second signal lines may include CLK12 and CLK32), in the array substrate described in at least one embodiment of this disclosure, the first first-side clock signal line CLK11, the second first-side clock signal line CLK21, the third first-side clock signal line CLK31 and the fourth first-side clock signal line CLK41 are disposed in the first border area B1;

[0108] The first second-side clock signal line CLK12, the second second-side clock signal line CLK22, the third second clock signal line CLK32, and the fourth second clock signal line CLK42 are disposed in the second border area B2;

[0109] The first scan line GL1, the second scan line GL2, the third scan line GL3, the fourth scan line GL4, the fifth scan line GL5, the sixth scan line GL6, the seventh scan line GL7, the (N-1)th scan line GLN-1, and the Nth scan line GLN are set in the display area A0;

[0110] The first gate driving module is disposed in the first frame region B1, and the second gate driving module is disposed in the second frame region B2.

[0111] In Figures 1A and 1B, G11 represents the first-stage gate drive circuit of the first gate drive module, G12 represents the second-stage gate drive circuit of the first gate drive module, G13 represents the third-stage gate drive circuit of the first gate drive module, G14 represents the fourth-stage gate drive circuit of the first gate drive module, G15 represents the fifth-stage gate drive circuit of the first gate drive module, G16 represents the sixth-stage gate drive circuit of the first gate drive module, G17 represents the seventh-stage gate drive circuit of the first gate drive module, G1N-1 represents the (N-1)th-stage gate drive circuit of the first gate drive module, and G1N represents the Nth-stage gate drive circuit of the first gate drive module.

[0112] The circuit labeled G21 is the first-stage gate drive circuit included in the second gate drive module; the circuit labeled G22 is the second-stage gate drive circuit included in the second gate drive module; the circuit labeled G23 is the third-stage gate drive circuit included in the second gate drive module; the circuit labeled G24 is the fourth-stage gate drive circuit included in the second gate drive module; the circuit labeled G25 is the fifth-stage gate drive circuit included in the second gate drive module; the circuit labeled G26 is the sixth-stage gate drive circuit included in the second gate drive module; the circuit labeled G27 is the seventh-stage gate drive circuit included in the second gate drive module; the circuit labeled G2N-1 is the (N-1)th-stage gate drive circuit included in the second gate drive module; and the circuit labeled G2N is the Nth-stage gate drive circuit included in the second gate drive module.

[0113] N is an integer greater than 8;

[0114] CLK11 is electrically connected to G11, CLK21 is electrically connected to G12, CLK31 is electrically connected to G13, CLK41 is electrically connected to G14; CLK11 is electrically connected to G15, CLK21 is electrically connected to G16, CLK31 is electrically connected to G17, CLK31 is electrically connected to G1N-1, and CLK41 is electrically connected to G1N.

[0115] CLK12 is electrically connected to G21, CLK22 is electrically connected to G22, CLK32 is electrically connected to G23, CLK42 is electrically connected to G24; CLK12 is electrically connected to G25, CLK22 is electrically connected to G26, CLK32 is electrically connected to G27, CLK32 is electrically connected to G2N-1, and CLK42 is electrically connected to G2N.

[0116] CLK11 is electrically connected to the first pin P1 located in the bonding area D1 via the first trace L11;

[0117] CLK31 is electrically connected to the second pin P2 located in the bonding area D1 via the second first trace L21;

[0118] CLK42 is electrically connected to the third pin P3 located in the bonding area D1 via the first second trace L12;

[0119] CLK22 is electrically connected to the fourth pin P4 located in the bonding area D1 via the second trace L22;

[0120] CLK11 is electrically connected to CLK12 via the first connecting line LX1, and CLK31 is electrically connected to CLK32 via the second connecting line LX2;

[0121] CLK22 is electrically connected to CLK21 via the third connecting line LX3, and CLK42 is electrically connected to CLK41 via the fourth connecting line LX4;

[0122] LX1, LX2, LX3 and LX4 are all located in the fourth border area B4;

[0123] The binding area D1 is contained within the third border area B3;

[0124] The first wiring space BX1 is disposed between the first border area B1 and the binding area D1; the second wiring space BX2 is disposed between the second border area B2 and the binding area D1;

[0125] L11 and L21 are located in the first wiring space BX1, and L12 and L22 are located in the second wiring space BX2.

[0126] In at least one embodiment of the array substrate shown in Figures 1A and 1B, the number of signal channels of the driving integrated circuit can be reduced by half. With the unlimited space of the PLG trace area remaining unchanged, the number of PLG traces becomes half of the original solution.

[0127] As shown in Figure 1C, when the first signal line and the second signal line are clock signal lines...

[0128] The line labeled X11-1 is the first signal line of the first part, and the line labeled X11-2 is the second signal line of the first part.

[0129] The line labeled X21-1 is the first signal line of the second part, and the line labeled X21-2 is the first signal line of the second part.

[0130] The line labeled X12-1 is the first part of the second signal line, and the line labeled X12-2 is the second part of the second signal line.

[0131] The line labeled X22-1 is the second signal line of the first second part, and the line labeled X22-2 is the second signal line of the second second part.

[0132] As shown in Figures 1A-1C, the first signal line X11-1 of the first part is CLK11, and the second signal line X11-2 of the first part is CLK31.

[0133] The first signal line X21-1 of the second part is CLK21, and the first signal line X21-2 of the second part is CLK41;

[0134] The first signal line X12-1 of the first part is CLK22, and the second signal line X12-2 of the first part is CLK42;

[0135] The first signal line X22-1 of the second part is CLK12, and the second signal line X22-2 of the second part is CLK32.

[0136] The differences between at least one embodiment of the array substrate shown in Figure 2A and at least one embodiment of the array substrate shown in Figure 1A are as follows:

[0137] The line width of L11 is greater than the line width of each clock signal line, and the line width of L21 is greater than the line width of each clock signal line.

[0138] The line width of L12 is greater than the line width of each clock signal line, and the line width of L22 is greater than the line width of each clock signal line.

[0139] In at least one embodiment of the array substrate shown in Figures 1A, 1B, and 2A, the linewidth of LX1 is greater than the linewidth of each clock signal line, the linewidth of LX2 is greater than the linewidth of each clock signal line, the linewidth of LX3 is greater than the linewidth of each clock signal line, and the linewidth of LX4 is greater than the linewidth of each clock signal line. When the fourth frame area is not provided with bonding pads or other structures for bonding with the circuit board, the non-display area of ​​the fourth frame area may include common electrode lines, electrostatic discharge circuits, etc. Therefore, the connection lines in the fourth frame area can be widened to reduce the impedance of the signal lines.

[0140] In at least one embodiment shown in Figure 2A, the number of signal channels of the driving integrated circuit can be reduced by half. With the unlimited space in the PLG trace area remaining unchanged, the number of PLG traces becomes half of the original scheme; the linewidth of the PLG trace can be doubled, the resistance of the PLG trace becomes half of the original, and the heat of the PLG trace becomes half of the original. Referring to Figure 2A, since CLK21 and CLK41 do not need to be electrically connected to pins through the first trace in the first frame area, the saved space can be used to increase the linewidth of L11 and L21. Optionally, as shown in Figure 2B, when CLK21 extends along its extension direction, CLK21 at least partially overlaps with L11; when CLK41 extends along its extension direction, CLK41 at least partially overlaps with L21; when CLK42 extends along its extension direction, CLK42 at least partially overlaps with L12; and when CLK22 extends along its extension direction, CLK22 at least partially overlaps with L22.

[0141] In Figure 2B, the area labeled A1 is the first overlapping region, the area labeled A2 is the second overlapping region, the area labeled A3 is the third overlapping region, and the area labeled A4 is the fourth overlapping region.

[0142] The first overlapping region A1 is the overlapping region between the extension of CLK21 and L11, the second overlapping region A2 is the overlapping region between the extension of CLK41 and L21, the third overlapping region A3 is the overlapping region between the extension of CLK42 and L12, and the third overlapping region A4 is the overlapping region between the extension of CLK22 and L22.

[0143] In at least one embodiment of this disclosure, the plurality of first signal lines include a first-side start signal line and a first-side power supply voltage line, and the plurality of second signal lines include a second-side start signal line and a second-side power supply voltage line;

[0144] The first-side start signal line is electrically connected to the pin located in the bonding area via a corresponding first trace;

[0145] The second-side power supply voltage line is electrically connected to the pin located in the bonding area via a corresponding second trace;

[0146] The first-side start signal line is electrically connected to the first-stage gate drive circuit included in the first gate drive module, and the second-side start signal line is electrically connected to the first-stage gate drive circuit included in the second gate drive module.

[0147] In a specific implementation, a first-side start signal line and a first-side power supply voltage line may also be provided in the first frame area, and a second-side start signal line and a second-side power supply voltage line may also be provided in the second frame area. The first-side start signal line is electrically connected to the pin in the bonding area through a first trace in the first wiring space to receive the start signal provided by the driver integrated circuit. The second-side power supply voltage line is electrically connected to the pin in the bonding area through a second trace in the second wiring space to receive the power supply voltage signal provided by the driver integrated circuit.

[0148] Optionally, the first-side start signal line is electrically connected to the second-side start signal line via the connecting line; the second-side power supply voltage line is electrically connected to the first-side power supply voltage line via the connecting line.

[0149] In a specific implementation, the first-side start signal line can be electrically connected to the second-side start signal line through a connecting line set in the fourth frame area. The second-side start signal line receives the start signal through the first-side start signal line. The second-side power supply voltage line can be electrically connected to the first-side power supply voltage line through a connecting line set in the fourth frame area. The first-side power supply voltage line receives the power supply voltage signal through the second-side power supply voltage line.

[0150] As shown in Figures 3A and 3B, based on at least one embodiment of the array substrate shown in Figure 1B, and in at least one embodiment of this disclosure,

[0151] The plurality of first signal lines include a first-side start signal line STV1 and a first-side power supply voltage line VDD1, and the plurality of second signal lines include a second-side start signal line STV2 and a second-side power supply voltage line VDD2.

[0152] STV1 is set in the first border area B1, and STV2 is set in the second border area B2;

[0153] The first-side start signal line STV1 is electrically connected to the fifth pin P5 located in the binding area D1 through the third first trace L31 to receive the start signal;

[0154] The second-side power supply voltage line VDD2 is electrically connected to the sixth pin P6 located in the bonding area D1 through the third second trace L32 to receive the power supply voltage signal;

[0155] The first-side start signal line STV1 is electrically connected to the first-stage gate drive circuit G11 included in the first gate drive module, providing a start signal for G11.

[0156] The second-side start signal line STV2 is electrically connected to the first-stage gate drive circuit G21 included in the second gate drive module, providing a start signal to G21.

[0157] The first-side start signal line STV1 is electrically connected to the second-side start signal line STV2 via the fifth connecting line LX5 located in the fourth frame area B4; STV2 receives the start signal through STV1.

[0158] The second-side power supply voltage line VDD2 is electrically connected to the first-side power supply voltage line VDD1 via the sixth connecting line LX6 located in the fourth frame area B4; VDD1 receives the power supply voltage signal through VDD2.

[0159] In at least one embodiment of this disclosure, the plurality of first signal lines further includes M first-side clock signal lines, and the plurality of second signal lines further includes M second-side clock signal lines; M is a positive integer;

[0160] The first-side clock signal line is electrically connected to a corresponding pin in the bonding area via a first trace disposed in the first wiring space.

[0161] The second-side clock signal line is electrically connected to a corresponding pin in the bonding area via a second trace provided in the second wiring space.

[0162] The m-th first-side clock signal line is electrically connected to the m-th second-side clock signal line via a connecting line located in the fourth border area; m is a positive integer less than or equal to M.

[0163] In a specific implementation, M first-side clock signal lines can be provided in the first frame area, and M second-side clock signal lines can be provided in the second frame area. The M first-side clock signal lines are electrically connected to the corresponding pins provided in the bonding area through corresponding first traces, and the M second-side clock signal lines are electrically connected to the corresponding pins provided in the bonding area through corresponding second traces.

[0164] As shown in Figures 4A and 4B, in the array substrate described in at least one embodiment of this disclosure, a first first-side clock signal line CLK11, a second first-side clock signal line CLK21, a third first-side clock signal line CLK31, and a fourth first-side clock signal line CLK41 are disposed in the first border area B1.

[0165] The first second-side clock signal line CLK12, the second second-side clock signal line CLK22, the third second clock signal line CLK32, and the fourth second clock signal line CLK42 are disposed in the second border area B2;

[0166] The first scan line GL1, the second scan line GL2, the third scan line GL3, the fourth scan line GL4, the fifth scan line GL5, the sixth scan line GL6, the seventh scan line GL7, the (N-1)th scan line GLN-1, and the Nth scan line GLN are set in the display area A0;

[0167] The first gate driving module is disposed in the first frame region B1, and the second gate driving module is disposed in the second frame region B2.

[0168] In Figures 4A and 4B, G11 represents the first-stage gate drive circuit of the first gate drive module, G12 represents the second-stage gate drive circuit of the first gate drive module, G13 represents the third-stage gate drive circuit of the first gate drive module, and so on. G1N-1 represents the (N-1)th-stage gate drive circuit of the first gate drive module, and G1N represents the Nth-stage gate drive circuit of the first gate drive module.

[0169] The circuit labeled G21 is the first-stage gate drive circuit included in the second gate drive module, the circuit labeled G22 is the second-stage gate drive circuit included in the second gate drive module, the circuit labeled G23 is the third-stage gate drive circuit included in the second gate drive module, and so on. The circuit labeled G2N-1 is the (N-1)th-stage gate drive circuit included in the second gate drive module, and the circuit labeled G2N is the Nth-stage gate drive circuit included in the second gate drive module.

[0170] N is an integer greater than 8;

[0171] CLK11 is electrically connected to G11, CLK21 is electrically connected to G12, CLK31 is electrically connected to G13, CLK41 is electrically connected to G14; CLK11 is electrically connected to G15, CLK21 is electrically connected to G16, CLK31 is electrically connected to G17, CLK31 is electrically connected to G1N-1, and CLK41 is electrically connected to G1N.

[0172] CLK12 is electrically connected to G21, CLK22 is electrically connected to G22, CLK32 is electrically connected to G23, CLK42 is electrically connected to G24; CLK12 is electrically connected to G25, CLK22 is electrically connected to G26, CLK32 is electrically connected to G27, CLK32 is electrically connected to G2N-1, and CLK42 is electrically connected to G2N.

[0173] CLK11 is electrically connected to the first pin P1 located in the bonding area D1 via the first trace L11;

[0174] CLK21 is electrically connected to the second pin P2 located in the bonding area D1 via the second first trace L21;

[0175] CLK31 is electrically connected to the third pin P3 located in the bonding area D1 via the third first trace L31;

[0176] CLK41 is electrically connected to the fourth pin P4 located in the bonding area D1 via the fourth first trace L41;

[0177] CLK42 is electrically connected to the fifth pin P5 located in the bonding area D1 via the first second trace L12;

[0178] The CLK32 is electrically connected to the sixth pin P6 located in the bonding area D1 via the second trace L22;

[0179] CLK22 is electrically connected to pin P7, which is located in the bonding area D1, via the third second trace L32;

[0180] CLK12 is electrically connected to the eighth pin P8 located in the bonding area D1 via the fourth second trace L42;

[0181] The binding area D1 is contained within the third border area B3;

[0182] The first wiring space BX1 is disposed between the first border area B1 and the binding area D1; the second wiring space BX2 is disposed between the second border area B2 and the binding area D1;

[0183] L11, L21, L31 and L41 are located in the first wiring space BX1, and L12, L22, L32 and L42 are located in the second wiring space BX2.

[0184] The plurality of first signal lines include a first-side start signal line STV1 and a first-side power supply voltage line VDD1, and the plurality of second signal lines include a second-side start signal line STV2 and a second-side power supply voltage line VDD2.

[0185] STV1 is set in the first border area B1, and STV2 is set in the second border area B2;

[0186] The first-side start signal line STV1 is electrically connected to the ninth pin P9 located in the bonding area D1 through the fifth first trace L51, and receives the start signal provided by the driver integrated circuit;

[0187] The second-side power supply voltage line VDD2 is electrically connected to the tenth pin P10 located in the bonding area D1 through the fifth second trace L52, and receives the power supply voltage signal provided by the driver integrated circuit.

[0188] The first-side start signal line STV1 is electrically connected to the first-stage gate drive circuit G11 included in the first gate drive module, providing a start signal for G11.

[0189] The second-side start signal line STV2 is electrically connected to the first-stage gate drive circuit G21 included in the second gate drive module, providing a start signal to G21.

[0190] The first-side start signal line STV1 is electrically connected to the second-side start signal line STV2 via the first connecting line LX1 located in the fourth frame area B4; STV2 receives the start signal through STV1.

[0191] The second-side power supply voltage line VDD2 is electrically connected to the first-side power supply voltage line VDD1 through the second connecting line LX2 located in the fourth frame area B4; VDD1 receives the power supply voltage signal through VDD2.

[0192] The differences between at least one embodiment of the array substrate shown in Figure 5 and at least one embodiment of the array substrate shown in Figure 4A are as follows:

[0193] CLK11 and CLK12 are electrically connected via the third connection line LX3 located in the fourth border area B4; CLK21 and CLK22 are electrically connected via the fourth connection line LX4 located in the fourth border area B4; CLK31 and CLK32 are electrically connected via the fifth connection line LX5 located in the fourth border area B4; and CLK41 and CLK42 are electrically connected via the sixth connection line LX6 located in the fourth border area B4, in order to enhance the driving capability of each clock signal line.

[0194] In at least one embodiment of this disclosure, the plurality of first signal lines include a first first-side start signal line and a second first-side start signal line, and the plurality of second signal lines include a first second-side start signal line and a second second-side start signal line;

[0195] The first first-side start signal line is electrically connected to a corresponding pin located in the bonding area via the first trace;

[0196] The second second-side start signal line is electrically connected to the corresponding pin located in the bonding area via the second trace.

[0197] In a specific implementation, two start signal lines can be provided in the first frame area and two start signal lines can be provided in the second frame area. In the first frame area, the first start signal line is electrically connected to the pin provided in the bonding area and receives the first start signal provided by the driver integrated circuit. In the second frame area, the second start signal line is electrically connected to the pin provided in the bonding area and receives the second start signal provided by the driver integrated circuit.

[0198] Optionally, the first first-side start signal line is electrically connected to the first second-side start signal line via the connecting line, and the second second-side start signal line is electrically connected to the second first-side start signal line via the connecting line.

[0199] In a specific implementation, the first first-side start signal line is electrically connected to the first second-side start signal line through a connecting line disposed in the fourth frame area. The first second-side start signal line receives the first start signal through the first first-side start signal line. The second second-side start signal line is electrically connected to the second first-side start signal line through a connecting line disposed in the fourth frame area. The second first-side start signal line receives the second start signal through the second second-side start signal line.

[0200] In at least one embodiment of this disclosure, the first first-side start signal line is electrically connected to the first-stage gate drive circuit of the first gate drive module, and the second first-side start signal line is electrically connected to the second-stage gate drive circuit of the first gate drive module; the first second-side start signal line is electrically connected to the first-stage gate drive circuit of the second gate drive module, and the second second-side start signal line is electrically connected to the second-stage gate drive circuit of the second gate drive module; or;

[0201] The first first-side start signal line is electrically connected to the first-stage gate drive circuit of the second gate drive module, and the first second-side start signal line is electrically connected to the first-stage gate drive circuit of the first gate drive module.

[0202] In specific implementation, the first first-side start signal line and the second first-side start signal line can be electrically connected to the first-stage gate drive circuit and the second-stage gate drive circuit in the first gate drive module, respectively; and the first second-side start signal line and the second second-side start signal line can be electrically connected to the first-stage gate drive circuit and the second-stage gate drive circuit in the second gate drive module, respectively; or,

[0203] The first start signal line on the first side is electrically connected to the first-stage gate drive circuit of the second gate drive module on the opposite side, and the second start signal line on the second side is electrically connected to the first-stage gate drive circuit of the first gate drive module on the opposite side.

[0204] As shown in Figures 6A and 6B, in the array substrate described in at least one embodiment of this disclosure, a first first-side clock signal line CLK11, a second first-side clock signal line CLK21, a third first-side clock signal line CLK31, and a fourth first-side clock signal line CLK41 are disposed in the first border area B1.

[0205] The first second-side clock signal line CLK12, the second second-side clock signal line CLK22, the third second clock signal line CLK32, and the fourth second clock signal line CLK42 are disposed in the second border area B2;

[0206] The first scan line GL1, the second scan line GL2, the third scan line GL3, the fourth scan line GL4, the fifth scan line GL5, the sixth scan line GL6, the seventh scan line GL7, the (N-1)th scan line GLN-1, and the Nth scan line GLN are set in the display area A0;

[0207] The first gate driving module is disposed in the first frame region B1, and the second gate driving module is disposed in the second frame region B2.

[0208] In Figures 6A and 6B, G11 represents the first-stage gate drive circuit of the first gate drive module, G12 represents the second-stage gate drive circuit of the first gate drive module, G13 represents the third-stage gate drive circuit of the first gate drive module, and so on. G1N-1 represents the (N-1)th-stage gate drive circuit of the first gate drive module, and G1N represents the Nth-stage gate drive circuit of the first gate drive module.

[0209] The circuit labeled G21 is the first-stage gate drive circuit included in the second gate drive module, the circuit labeled G22 is the second-stage gate drive circuit included in the second gate drive module, the circuit labeled G23 is the third-stage gate drive circuit included in the second gate drive module, and so on. The circuit labeled G2N-1 is the (N-1)th-stage gate drive circuit included in the second gate drive module, and the circuit labeled G2N is the Nth-stage gate drive circuit included in the second gate drive module.

[0210] N is an integer greater than 8;

[0211] CLK11 is electrically connected to G11, CLK21 is electrically connected to G12, CLK31 is electrically connected to G13, CLK41 is electrically connected to G14; CLK11 is electrically connected to G15, CLK21 is electrically connected to G16, CLK31 is electrically connected to G17, CLK31 is electrically connected to G1N-1, and CLK41 is electrically connected to G1N.

[0212] CLK12 is electrically connected to G21, CLK22 is electrically connected to G22, CLK32 is electrically connected to G23, CLK42 is electrically connected to G24; CLK12 is electrically connected to G25, CLK22 is electrically connected to G26, CLK32 is electrically connected to G27, CLK32 is electrically connected to G2N-1, and CLK42 is electrically connected to G2N.

[0213] CLK11 is electrically connected to the first pin P1 located in the bonding area D1 via the first trace L11;

[0214] CLK21 is electrically connected to the second pin P2 located in the bonding area D1 via the second first trace L21;

[0215] CLK31 is electrically connected to the third pin P3 located in the bonding area D1 via the third first trace L31;

[0216] CLK41 is electrically connected to the fourth pin P4 located in the bonding area D1 via the fourth first trace L41;

[0217] CLK42 is electrically connected to the fifth pin P5 located in the bonding area D1 via the first second trace L12;

[0218] The CLK32 is electrically connected to the sixth pin P6 located in the bonding area D1 via the second trace L22;

[0219] CLK22 is electrically connected to pin P7, which is located in the bonding area D1, via the third second trace L32;

[0220] CLK12 is electrically connected to the eighth pin P8 located in the bonding area D1 via the fourth second trace L42;

[0221] The binding area D1 is contained within the third border area B3;

[0222] The first wiring space BX1 is disposed between the first border area B1 and the binding area D1; the second wiring space BX2 is disposed between the second border area B2 and the binding area D1;

[0223] L11, L21, L31 and L41 are located in the first wiring space BX1, and L12, L22, L32 and L42 are located in the second wiring space BX2.

[0224] The plurality of first signal lines include a first first-side starting signal line STV11 and a second first-side starting signal line STV21, and the plurality of second signal lines include a first second-side starting signal line STV12 and a second second-side starting signal line STV22.

[0225] The first first-side start signal line STV11 is electrically connected to the ninth pin P9 located in the bonding area D1 via the fifth first trace L51;

[0226] The second second-side start signal line STV22 is electrically connected to the tenth pin P10 located in the bonding area D1 via the fifth second trace L52;

[0227] STV11 is electrically connected to G11 and provides a first start signal to G11; STV21 is electrically connected to G12 and provides a second start signal to G12.

[0228] STV12 is electrically connected to G21 and provides a first start signal to G21; STV22 is electrically connected to G22 and provides a second start signal to G22.

[0229] The first first-side start signal line STV11 is electrically connected to the first second-side start signal line STV12 via a first connecting line LX1 disposed in the fourth frame area B4, and the second second-side start signal line STV22 is electrically connected to the second first-side start signal line STV21 via a second connecting line LX2 disposed in the fourth frame area B4.

[0230] CLK11 and CLK12 are electrically connected via the third connection line LX3 located in the fourth border area B4; CLK21 and CLK22 are electrically connected via the fourth connection line LX4 located in the fourth border area B4; CLK31 and CLK32 are electrically connected via the fifth connection line LX5 located in the fourth border area B4; and CLK41 and CLK42 are electrically connected via the sixth connection line LX6 located in the fourth border area B4, in order to enhance the driving capability of each clock signal line.

[0231] In Figures 6A and 6B, the line labeled VDD1 is the first-side power supply voltage line, and the line labeled VDD2 is the second-side power supply voltage line.

[0232] VDD2 is electrically connected to the eleventh pin P11 located in the bonding area D1 via the sixth second trace L62;

[0233] VDD1 is electrically connected to VDD2 via the seventh connecting line LX7 located in the fourth border area B4.

[0234] As shown in Figures 7A and 7B, in the array substrate described in at least one embodiment of this disclosure, a first first-side clock signal line CLK11, a second first-side clock signal line CLK21, a third first-side clock signal line CLK31, and a fourth first-side clock signal line CLK41 are disposed in the first border area B1.

[0235] The first second-side clock signal line CLK12, the second second-side clock signal line CLK22, the third second clock signal line CLK32, and the fourth second clock signal line CLK42 are disposed in the second border area B2;

[0236] The first gate driving module is disposed in the first frame region B1, and the second gate driving module is disposed in the second frame region B2.

[0237] In Figures 7A and 7B, G11 represents the first-stage gate drive circuit of the first gate drive module, G12 represents the second-stage gate drive circuit of the first gate drive module, G13 represents the third-stage gate drive circuit of the first gate drive module, G14 represents the fourth-stage gate drive circuit of the first gate drive module, and so on. G1N-1 represents the (N-1)th-stage gate drive circuit of the first gate drive module, and G1N represents the Nth-stage gate drive circuit of the first gate drive module.

[0238] The circuit labeled G21 is the first-stage gate drive circuit included in the second gate drive module; the circuit labeled G22 is the second-stage gate drive circuit included in the second gate drive module; the circuit labeled G23 is the third-stage gate drive circuit included in the second gate drive module; the circuit labeled G24 is the fourth-stage gate drive circuit included in the second gate drive module; and so on. The circuit labeled G2N-1 is the (N-1)th-stage gate drive circuit included in the second gate drive module; and the circuit labeled G2N is the Nth-stage gate drive circuit included in the second gate drive module.

[0239] N is an integer greater than 8;

[0240] CLK11 is electrically connected to G11, CLK21 is electrically connected to G12, CLK31 is electrically connected to G13, CLK41 is electrically connected to G14; CLK11 is electrically connected to G15, CLK21 is electrically connected to G16, CLK31 is electrically connected to G17, CLK31 is electrically connected to G1N-1, and CLK41 is electrically connected to G1N.

[0241] CLK12 is electrically connected to G21, CLK22 is electrically connected to G22, CLK32 is electrically connected to G23, CLK42 is electrically connected to G24; CLK12 is electrically connected to G25, CLK22 is electrically connected to G26, CLK32 is electrically connected to G27, CLK32 is electrically connected to G2N-1, and CLK42 is electrically connected to G2N.

[0242] CLK11 is electrically connected to the first pin P1 located in the bonding area D1 via the first trace L11;

[0243] CLK21 is electrically connected to the second pin P2 located in the bonding area D1 via the second first trace L21;

[0244] CLK31 is electrically connected to the third pin P3 located in the bonding area D1 via the third first trace L31;

[0245] CLK41 is electrically connected to the fourth pin P4 located in the bonding area D1 via the fourth first trace L41;

[0246] CLK42 is electrically connected to the fifth pin P5 located in the bonding area D1 via the first second trace L12;

[0247] The CLK32 is electrically connected to the sixth pin P6 located in the bonding area D1 via the second trace L22;

[0248] CLK22 is electrically connected to pin P7, which is located in the bonding area D1, via the third second trace L32;

[0249] CLK12 is electrically connected to the eighth pin P8 located in the bonding area D1 via the fourth second trace L42;

[0250] The binding area D1 is contained within the third border area B3;

[0251] The first wiring space BX1 is disposed between the first border area B1 and the binding area D1; the second wiring space BX2 is disposed between the second border area B2 and the binding area D1;

[0252] L11, L21, L31 and L41 are located in the first wiring space BX1, and L12, L22, L32 and L42 are located in the second wiring space BX2.

[0253] The plurality of first signal lines include a first first-side starting signal line STV11 and a second first-side starting signal line STV21, and the plurality of second signal lines include a first second-side starting signal line STV12 and a second second-side starting signal line STV22.

[0254] The first first-side start signal line STV11 is electrically connected to the ninth pin P9 located in the bonding area D1 via the fifth first trace L51;

[0255] The second second-side start signal line STV22 is electrically connected to the tenth pin P10 located in the bonding area D1 via the fifth second trace L52;

[0256] STV11 is electrically connected to G11 and is used to provide a start signal to G11;

[0257] STV12 is electrically connected to G21 and is used to provide a start signal to G21;

[0258] STV21 is electrically connected to G12 and is used to provide a start signal to G12;

[0259] STV22 is electrically connected to G22 and is used to provide a start signal to G22;

[0260] STV11 and STV21 are both electrically connected to G11; STV11 provides a first start signal to G11, and STV21 provides a second start signal to G11;

[0261] STV12 and STV22 are both electrically connected to G21; STV12 provides a first start signal to G21, and STV22 provides a second start signal to G21;

[0262] The first first-side start signal line STV11 is electrically connected to the first second-side start signal line STV12 via a first connecting line LX1 disposed in the fourth frame area B4, and the second second-side start signal line STV22 is electrically connected to the second first-side start signal line STV21 via a second connecting line LX2 disposed in the fourth frame area B4.

[0263] CLK11 and CLK12 are electrically connected via the third connection line LX3 located in the fourth border area B4; CLK21 and CLK22 are electrically connected via the fourth connection line LX4 located in the fourth border area B4; CLK31 and CLK32 are electrically connected via the fifth connection line LX5 located in the fourth border area B4; and CLK41 and CLK42 are electrically connected via the sixth connection line LX6 located in the fourth border area B4, in order to enhance the driving capability of each clock signal line.

[0264] In Figures 7A and 7B, the line labeled VDD11 is the first power supply voltage line on the first side, and the line labeled VDD12 is the first power supply voltage line on the second side.

[0265] VDD12 is electrically connected to the eleventh pin P11 located in the bonding area D1 via the sixth second trace L62;

[0266] VDD11 is electrically connected to VDD12 via the seventh connecting line LX7 located in the fourth border area B4;

[0267] VDD11 is electrically connected to G11, G12, G13, G14, G15, G16, G17, G1N-1 and G1N respectively;

[0268] VDD12 is electrically connected to G21, G22, G23, G24, G25, G26, G27, G2N-1 and G2N respectively.

[0269] The differences between at least one embodiment of the array substrate shown in Figure 8A and at least one embodiment of the array substrate shown in Figure 7A are as follows:

[0270] Reduce the length of STV21, cut STV21, and cut off the signal line below the connection point between STV21 and G11.

[0271] Reduce the length of STV12, phase STV12, and cut off the signal line below the connection point between STV12 and G21.

[0272] This facilitates the achievement of narrow bezels.

[0273] The differences between at least one embodiment of the array substrate shown in Figure 8B and at least one embodiment of the array substrate shown in Figure 8A are as follows:

[0274] STV22 is electrically connected to G11 and is used to provide a start signal to G11;

[0275] STV11 is electrically connected to G21 and is used to provide a start signal to G21.

[0276] In at least one embodiment of this disclosure, the plurality of first signal lines include a first first-side power supply voltage line and a second first-side power supply voltage line, and the plurality of second signal lines include a first second-side power supply voltage line and a second second-side power supply voltage line.

[0277] The first power supply voltage line on the first side is electrically connected to the corresponding pin located in the bonding area through the first trace;

[0278] The second power supply voltage line on the second side is electrically connected to the corresponding pin located in the bonding area via the second trace.

[0279] In a specific implementation, a first first-side power supply voltage line and a second first-side power supply voltage line can be provided in the first frame area, and a first second-side power supply voltage line and a second second-side power supply voltage line can be provided in the second frame area. The first first-side power supply voltage line is electrically connected to the corresponding pin provided in the bonding area through a first trace, and the second second-side power supply voltage line is electrically connected to the corresponding pin provided in the bonding area through a second trace.

[0280] Optionally, the first power supply voltage line on the first side is electrically connected to the first power supply voltage line on the second side through the connecting line, and the second power supply voltage line on the second side is electrically connected to the second power supply voltage line on the first side through the connecting line;

[0281] The first power supply voltage line on the first side and the first power supply voltage line on the second side are respectively connected to different levels of gate drive circuits of different gate drive modules, or the first power supply voltage line on the first side and the first power supply voltage line on the second side are connected to the same level of gate drive circuit of the same gate drive module.

[0282] In specific implementation, the first power supply voltage line on the first side can be electrically connected to the first power supply voltage line on the second side through the connecting line set in the fourth frame area, and the second power supply voltage line on the second side can be electrically connected to the second power supply voltage line on the first side through the connecting line set in the fourth frame area.

[0283] Optionally, the first first-side power supply voltage line and the first second-side power supply voltage line can be respectively connected to different levels of gate drive circuits in different gate drive modules. That is, the first first-side power supply voltage line can be electrically connected to the odd-numbered level gate drive circuits included in the first gate drive module, the second first-side power supply voltage line can be electrically connected to the even-numbered level gate drive circuits included in the first gate drive module, the first second-side power supply voltage line can be electrically connected to the odd-numbered level gate drive circuits in the second gate drive module, and the second second-side power supply voltage line can be electrically connected to the even-numbered level gate drive circuits in the second gate drive module; or, the first first-side power supply voltage line is electrically connected to the first second-side power supply voltage line, and the second first-side power supply voltage line is electrically connected to the second second-side power supply voltage line; or...

[0284] The first first-side power supply voltage line and the first second-side power supply voltage line are connected to the same level of gate drive circuit in the same gate drive module; for example, the first first-side power supply voltage line and the second first-side power supply voltage line are both electrically connected to each level of gate drive circuit included in the first gate drive module, and the first second-side power supply voltage line and the second second-side power supply voltage line are both electrically connected to each level of gate drive circuit included in the second gate drive module; the first first-side power supply voltage line is electrically connected to the first second-side power supply voltage line, and the second first-side power supply voltage line is electrically connected to the second second-side power supply voltage line.

[0285] The differences between at least one embodiment of the array substrate shown in Figure 9A and at least one embodiment of the array substrate shown in Figure 7A are as follows:

[0286] It also includes a second first-side power supply voltage line VDD21 and a second second-side power supply voltage line VDD22;

[0287] VDD11 is electrically connected to G11, VDD21 is electrically connected to G12, VDD11 is electrically connected to G13, VDD21 is electrically connected to G14, VDD11 is electrically connected to G15, VDD21 is connected to G16, VDD11 is electrically connected to G17, VDD11 is electrically connected to G1N-1, and VDD21 is electrically connected to G1N.

[0288] VDD12 is electrically connected to G21, VDD22 is electrically connected to G22, VDD12 is electrically connected to G23, VDD22 is electrically connected to G24, VDD12 is electrically connected to G25, VDD22 is connected to G26, VDD12 is electrically connected to G27, VDD12 is electrically connected to G2N-1, and VDD22 is electrically connected to G2N.

[0289] As shown in Figures 9A and 9B, VDD21 is electrically connected to the twelfth pin P12 located in the bonding area D1 via the sixth first trace L61.

[0290] VDD21 is electrically connected to VDD22 via the eighth connecting line LX8 located in the fourth border area B4.

[0291] The differences between at least one embodiment of the array substrate shown in Figure 10 and at least one embodiment of the array substrate shown in Figure 9A are as follows:

[0292] VDD11 and VDD21 are both electrically connected to G11; VDD11 and VDD21 are both electrically connected to G12; VDD11 and VDD21 are both electrically connected to G13; VDD11 and VDD21 are both electrically connected to G14; VDD11 and VDD21 are both electrically connected to G15; VDD11 and VDD21 are both connected to G16; VDD11 and VDD21 are both electrically connected to G17; VDD11 and VDD21 are both electrically connected to G1N-1; VDD11 and VDD21 are both electrically connected to G1N.

[0293] VDD12 and VDD22 are both electrically connected to G21. VDD12 and VDD22 are both electrically connected to G22. VDD12 and VDD22 are both electrically connected to G23. VDD12 and VDD22 are both electrically connected to G24. VDD12 and VDD22 are both electrically connected to G25. VDD12 and VDD22 are both connected to G26. VDD12 and VDD22 are both electrically connected to G27. VDD12 and VDD22 are both electrically connected to G2N-1. VDD12 and VDD22 are both electrically connected to G2N.

[0294] In at least one embodiment of this disclosure, the plurality of first signal lines include a first-side high-voltage line and a first-side low-voltage line, and the plurality of second signal lines include a second-side high-voltage line and a second-side low-voltage line;

[0295] The first high-voltage line is electrically connected to a corresponding pin located in the bonding area via the first trace.

[0296] The second low-voltage line is electrically connected to the corresponding pin located in the bonding area via the second trace.

[0297] Optionally, the first low-voltage line is electrically connected to the second low-voltage line via the connecting line;

[0298] The second high-voltage line is electrically connected to the first high-voltage line via the connecting line.

[0299] The differences between at least one embodiment of the array substrate shown in Figure 11 and at least one embodiment of the array substrate shown in Figure 3A are as follows:

[0300] It also includes a first-side high-voltage line VGH1, a second-side high-voltage line VGH2, a first-side low-voltage line VGL1, and a second-side low-voltage line VGL2;

[0301] VGH1 is electrically connected to pin P7 of the seventh pin via the fourth first trace L41;

[0302] VGL2 is electrically connected to the eighth pin P8 via the fourth second trace L42;

[0303] VGH1 is electrically connected to VGH2 via the seventh connecting line LX7;

[0304] VGL1 is electrically connected to VGL2 via the eighth connection line LX8.

[0305] In this disclosure, the structures in the various embodiments can be used interchangeably, and the structure of the array substrate is not limited.

[0306] The display device described in this disclosure includes the array substrate described above.

[0307] The above description represents the preferred embodiments of this disclosure. It should be noted that those skilled in the art can make various improvements and modifications without departing from the principles described herein, and these improvements and modifications should also be considered within the scope of protection of this disclosure.

Claims

1. An array substrate, comprising a first gate driving module disposed in a first border region, a second gate driving module disposed in a second border region, and a bonding region disposed in a third border region; the array substrate further comprising a plurality of first signal lines and a plurality of second signal lines, wherein at least a portion of the first signal lines is disposed in the first border region, and at least a portion of the second signal lines is disposed in the second border region; the first border region and the second border region are disposed on opposite sides of a display region; The first gate driving module is electrically connected to the plurality of first signal lines and is used to receive electrical signals provided by the first signal lines; the second gate driving module is electrically connected to the plurality of second signal lines and is used to receive electrical signals provided by the second signal lines. The plurality of first signal lines include at least one first portion first signal line and at least one second portion first signal line; the plurality of second signal lines include at least one first portion second signal line and at least one second portion second signal line; The first signal line of the first portion is electrically connected to the pin disposed in the bonding area through the first trace; at least a portion of the first trace is disposed in the first wiring space, and the first wiring space is disposed between the first border area and the bonding area; The first portion of the second signal line is electrically connected to a pin disposed in the bonding area via a second trace; at least a portion of the second trace is disposed in a second wiring space; the second wiring space is disposed between the second border area and the bonding area; The second part of the first signal line is electrically connected to the corresponding first part of the second signal line through the connecting line disposed in the fourth frame area; the second part of the second signal line is electrically connected to the corresponding first part of the first signal line through the connecting line disposed in the fourth frame area. The third border area and the fourth border area are located on opposite sides of the display area.

2. The array substrate as claimed in claim 1, wherein, The width of the first trace is greater than the width of the first signal line, and the width of the second trace is greater than the width of the second signal line.

3. The array substrate as claimed in claim 1, wherein, The width of the connecting line is greater than the width of the first signal line, and the width of the connecting line is greater than the width of the second signal line.

4. The array substrate as claimed in claim 1, wherein, The first signal line is electrically connected to the second signal line via a connecting line disposed in the fourth border area.

5. The array substrate as claimed in claim 1, wherein, The plurality of first signal lines include a plurality of first-side clock signal lines, and the plurality of second signal lines include a plurality of second-side clock signal lines; The plurality of first-side clock signal lines include at least one first-part first-side clock signal line and at least one second-part first-side clock signal line; the plurality of second signal lines include at least one first-part second-side clock signal line and at least one second-part second-side clock signal line. A portion of the multiple first-side clock signal lines are connected to the first trace and disposed on... The pins of the bonding area are electrically connected; A portion of the multiple second-side clock signal lines are electrically connected to pins located in the bonding area via the second trace.

6. The array substrate as claimed in claim 5, wherein, The second part of the first-side clock signal line is electrically connected to the corresponding first part of the second-side clock signal line through the connecting line, and the second part of the second-side clock signal line is electrically connected to the corresponding first part of the first-side clock signal line through the connecting line.

7. The array substrate as claimed in claim 6, wherein, The plurality of first signal lines includes 2N first-side clock signal lines, and the plurality of second signal lines includes 2N second-side clock signal lines; N is a positive integer; The 2n-1th first-side clock signal line is electrically connected to the pin located in the bonding area through the first trace; The 2nth second-side clock signal line is electrically connected to the pin located in the bonding area via the second trace; n is a positive integer less than or equal to N.

8. The array substrate as claimed in claim 7, wherein, The 2nth first-side clock signal line and the 2nth second-side clock signal line are electrically connected through the connecting line; The 2n-1th second-side clock signal line is electrically connected to the 2n-1th first-side clock signal line via the connecting line.

9. The array substrate as claimed in claim 1, wherein, The plurality of first signal lines include a first-side start signal line and a first-side power supply voltage line, and the plurality of second signal lines include a second-side start signal line and a second-side power supply voltage line; The first-side start signal line is electrically connected to the pin located in the bonding area via a corresponding first trace; The second-side power supply voltage line is electrically connected to the pin located in the bonding area via a corresponding second trace; The first-side start signal line is electrically connected to the first-stage gate drive circuit included in the first gate drive module, and the second-side start signal line is electrically connected to the first-stage gate drive circuit included in the second gate drive module.

10. The array substrate as claimed in claim 9, wherein, The first-side start signal line is electrically connected to the second-side start signal line via the connecting line; the second-side power supply voltage line is electrically connected to the first-side power supply voltage line via the connecting line.

11. The array substrate as claimed in claim 1, wherein, The plurality of first signal lines include a first first-side start signal line and a second first-side start signal line, and the plurality of second signal lines include a first second-side start signal line and a second second-side start signal line; The first first-side start signal line is electrically connected to a corresponding pin located in the bonding area via the first trace; The second second-side start signal line is electrically connected to the corresponding pin located in the bonding area via the second trace.

12. The array substrate as claimed in claim 11, wherein, The first first-side start signal line is electrically connected to the first second-side start signal line through the connecting line, and the second second-side start signal line is electrically connected to the second first-side start signal line through the connecting line.

13. The array substrate as claimed in claim 12, wherein, The first first-side start signal line is electrically connected to the first-stage gate drive circuit of the first gate drive module, and the second first-side start signal line is electrically connected to the second-stage gate drive circuit of the first gate drive module; the first second-side start signal line is electrically connected to the first-stage gate drive circuit of the second gate drive module, and the second second-side start signal line is electrically connected to the second-stage gate drive circuit of the second gate drive module; or; The first first-side start signal line is electrically connected to the first-stage gate drive circuit of the second gate drive module, and the first second-side start signal line is electrically connected to the first-stage gate drive circuit of the first gate drive module.

14. The array substrate as claimed in claim 1, wherein, The plurality of first signal lines include a first first-side power supply voltage line and a second first-side power supply voltage line, and the plurality of second signal lines include a first second-side power supply voltage line and a second second-side power supply voltage line; The first power supply voltage line on the first side is electrically connected to the corresponding pin located in the bonding area through the first trace; The second power supply voltage line on the second side is electrically connected to the corresponding pin located in the bonding area via the second trace.

15. The array substrate as claimed in claim 14, wherein, The first power supply voltage line on the first side is electrically connected to the first power supply voltage line on the second side through the connecting line, and the second power supply voltage line on the second side is electrically connected to the second power supply voltage line on the first side through the connecting line; The first power supply voltage line on the first side and the first power supply voltage line on the second side are respectively connected to different levels of gate drive circuits of different gate drive modules, or the first power supply voltage line on the first side and the first power supply voltage line on the second side are connected to the same level of gate drive circuit of the same gate drive module.

16. The array substrate as claimed in claim 1, wherein, The plurality of first signal lines include a first-side high-voltage line and a first-side low-voltage line, and the plurality of second signal lines include a second-side high-voltage line and a second-side low-voltage line; The first high-voltage line is electrically connected to a corresponding pin located in the bonding area via the first trace. The second low-voltage line is electrically connected to the corresponding pin located in the bonding area via the second trace.

17. The array substrate as claimed in claim 16, wherein, The first low-voltage line is electrically connected to the second low-voltage line via the connecting line; The second high-voltage line is electrically connected to the first high-voltage line via the connecting line.

18. The array substrate according to any one of claims 9 to 17, wherein, The plurality of first signal lines further includes M first-side clock signal lines, and the plurality of second signal lines further includes M second-side clock signal lines; M is a positive integer; The first-side clock signal line is electrically connected to a corresponding pin in the bonding area via a first trace disposed in the first wiring space. The second-side clock signal line is electrically connected to a corresponding pin in the bonding area via a second trace provided in the second wiring space. The m-th first-side clock signal line is electrically connected to the m-th second-side clock signal line via a connecting line located in the fourth border area; m is a positive integer less than or equal to M.

19. A display device comprising an array substrate as claimed in any one of claims 1 to 18.

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