Signal generation circuit and driving method therefor, and display device

Abstract

A signal generation circuit and a driving method therefor, and a display device. The signal generation circuit comprises a first control sub-circuit (1), a second control sub-circuit (2), an output control node (G1), and target output ends (Gout, GNout1, GNout2, GNout3, GNout4, GNout5, GNout6, GPout1, GPout2, GPout3, GPout4, GPout5, GPout6). The output control node (G1) is coupled to the target output ends (Gout, GNout1, GNout2, GNout3, GNout4, GNout5, GNout6, GPout1, GPout2, GPout3, GPout4, GPout5, GPout6). The first control sub-circuit (1) is separately coupled to control signal input ends (HF, HF1, HF2), a first level signal input end (P1), and the output control node (G1), and is used for controlling, under the control of the control signal input ends (HF, HF1, HF2), electrical connection or disconnection between the first level signal input end (P1) and the output control node (G1). The second control sub-circuit (2) is separately coupled to adjustable data signal input ends (DG, DG1, DG2), analog signal input ends (SA, SA1, SA2), and the output control node (G1), and is used for controlling, under the joint control of the adjustable data signal input ends (DG, DG1, DG2) and the analog signal input ends (SA, SA1, SA2), electrical connection or disconnection between the analog signal input ends (SA, SA1, SA2) and the output control node (G1).

Description

Signal generation circuit and its driving method, display device Technical Field

[0001] This disclosure relates to the field of display technology, and in particular to a signal generation circuit and its driving method, and a display device. Background Technology

[0002] With the continuous development of display technology, display products are gradually moving towards high-end technologies such as high resolution and low power consumption, and the functions of the driving circuits in these products are also increasing accordingly. This driving circuit is coupled to the driving chip in the display product, and the channels in the driving chip provide corresponding signals to the driving circuit, which then performs its driving function based on these signals.

[0003] Summary of the Invention

[0004] The purpose of this disclosure is to provide a signal generation circuit and its driving method, as well as a display device.

[0005] To achieve the above objectives, this disclosure provides the following technical solution:

[0006] A first aspect of this disclosure provides a signal generation circuit, comprising: a first control sub-circuit, a second control sub-circuit, an output control node, and a target output terminal; wherein the output control node is coupled to the target output terminal;

[0007] The first control sub-circuit is coupled to the control signal input terminal, the first level signal input terminal, and the output control node, respectively; it is used to control the electrical connection between the first level signal input terminal and the output control node to be turned on or off under the control of the control signal input terminal.

[0008] The second control sub-circuit is coupled to the adjustable data signal input terminal, the analog signal input terminal, and the output control node, respectively; it is used to control the electrical connection between the analog signal input terminal and the output control node to be turned on or off under the joint control of the adjustable data signal input terminal and the analog signal input terminal.

[0009] Optionally, the signal generation circuit further includes:

[0010] An output control sub-circuit is provided, wherein the output control node is coupled to the target output terminal through the output control sub-circuit, and the output control sub-circuit is also coupled to the first level signal input terminal and the second level signal input terminal respectively. The output control sub-circuit is used to control the target output terminal to receive the first level signal output from the first level signal input terminal, or to control the target output terminal to receive the second level signal output from the second level signal input terminal, under the control of the output control node.

[0011] Optionally, the output control sub-circuit is used to control the electrical connection between the second level signal input terminal and the target output terminal to be turned on or off under the control of the output control node; it is also used to control the electrical connection between the first level signal input terminal and the target output terminal to be turned on under the control of the first level signal input terminal.

[0012] Optionally, the output control sub-circuit includes: a first control unit and a second control unit;

[0013] The first terminal of the first control unit is coupled to the output control node, the second terminal of the first control unit is coupled to the second level signal input terminal, and the third terminal of the first control unit is coupled to the target output terminal; the first control unit is used to control the electrical connection between the second level signal input terminal and the target output terminal to be turned on or off under the control of the output control node;

[0014] The first terminal of the second control unit is coupled to the first level signal input terminal, the second terminal of the second control unit is coupled to the first level signal input terminal, and the third terminal of the second control unit is coupled to the target output terminal; the second control unit is used to control the conduction of the electrical connection between the first level signal input terminal and the target output terminal under the control of the first level signal input terminal.

[0015] Optionally, the signal generation circuit further includes: a first output compensation sub-circuit, wherein the third terminal of the first control unit and the third terminal of the second control unit are coupled together, and the first output compensation sub-circuit is coupled to the target output terminal; the first output compensation sub-circuit is also coupled to the first level signal input terminal, the second level signal input terminal and the output control node respectively;

[0016] The first output compensation sub-circuit is used to: control the electrical connection between the second level signal input terminal and the target output terminal under the control of the output control node; and is also used to control the electrical connection between the first level signal input terminal and the target output terminal under the control of the third terminal of the first control unit.

[0017] Optionally, the first output compensation sub-circuit includes: a third control unit and a fourth control unit;

[0018] The third control unit is coupled to the output control node, the second level signal input terminal and the target output terminal respectively, and is used to control the electrical connection between the second level signal input terminal and the target output terminal to be turned on or off under the control of the output control node.

[0019] The fourth control unit is coupled to the third terminal of the first control unit, the first level signal input terminal, and the target output terminal, respectively, and is used to control the electrical connection between the first level signal input terminal and the target output terminal to be turned on or off under the control of the third terminal of the first control unit.

[0020] Optionally, the signal generation circuit further includes: a second output compensation sub-circuit, wherein the third terminal of the first control unit and the third terminal of the second control unit are coupled together, and the second output compensation sub-circuit is coupled to the target output terminal; the second output compensation sub-circuit is also coupled to the control signal input terminal, the first level signal input terminal and the second level signal input terminal respectively;

[0021] The second output compensation sub-circuit is used to: control the electrical connection between the second level signal input terminal and the target output terminal to be turned on or off under the control of the third terminal of the first control unit; and is also used to control the electrical connection between the first level signal input terminal and the target output terminal to be turned on or off under the control of the control signal input terminal.

[0022] Optionally, the second output compensation sub-circuit includes: a fifth control unit and a sixth control unit;

[0023] The fifth control unit is coupled to the third terminal of the first control unit, the second level signal input terminal, and the target output terminal, respectively; it is used to control the electrical connection between the second level signal input terminal and the target output terminal to be turned on or off under the control of the third terminal of the first control unit.

[0024] The sixth control unit is coupled to the control signal input terminal, the first level signal input terminal, and the target output terminal respectively; it is used to control the electrical connection between the first level signal input terminal and the target output terminal to be turned on or off under the control of the control signal input terminal.

[0025] Optionally, the output control sub-circuit is used, under the control of the output control node, to control the electrical connection between the second level signal input terminal and the target output terminal to be turned on or off; it is also used, under the control of the output control node, to control the electrical connection between the first level signal input terminal and the target output terminal to be turned on or off.

[0026] Optionally, the output control sub-circuit includes a seventh control unit and an eighth control unit;

[0027] The seventh control unit is coupled to the output control node, the second level signal input terminal and the target output terminal respectively, and is used to control the electrical connection between the second level signal input terminal and the target output terminal to be turned on or off under the control of the output control node.

[0028] The eighth control unit is coupled to the output control node, the first level signal input terminal and the target output terminal respectively, and is used to control the electrical connection between the first level signal input terminal and the target output terminal to be turned on or off under the control of the output control node.

[0029] Optionally, the signal generation circuit further includes:

[0030] The third output compensation sub-circuit is coupled to the target output terminal, the second level signal input terminal, and the output control node, respectively, and is used to control the electrical connection between the second level signal input terminal and the output control node to be turned on or off under the control of the target output terminal.

[0031] Optionally, the first control sub-circuit includes a first transistor, the gate of the first transistor being coupled to the control signal input terminal, the first electrode of the first transistor being coupled to the first level signal input terminal, and the second electrode of the first transistor being coupled to the output control node.

[0032] The second control sub-circuit includes a second transistor, the gate of which is coupled to the adjustable data signal input terminal, the first terminal of which is coupled to the analog signal input terminal, and the second terminal of which is coupled to the output control node.

[0033] The second control unit includes a third transistor, the gate of which and the second terminal of which are both coupled to the first level signal input terminal;

[0034] The first control unit includes a fourth transistor, the gate of which is coupled to the output control node, the first terminal of which is coupled to the first terminal of the third transistor, and the second terminal of which is coupled to the second level signal input terminal.

[0035] The fourth control unit includes a fifth transistor, the gate of which is coupled to the first terminal of the fourth transistor, the first terminal of which is coupled to the first level signal input terminal, and the second terminal of which is coupled to the target output terminal;

[0036] The third control unit includes a sixth transistor, the gate of which is coupled to the output control node, the first terminal of which is coupled to the second level signal input terminal, and the second terminal of which is coupled to the target output terminal.

[0037] Optionally, the first control sub-circuit includes a first transistor, the gate of the first transistor being coupled to the control signal input terminal, the first electrode of the first transistor being coupled to the first level signal input terminal, and the second electrode of the first transistor being coupled to the output control node.

[0038] The second control sub-circuit includes a second transistor, the gate of which is coupled to the adjustable data signal input terminal, the first terminal of which is coupled to the analog signal input terminal, and the second terminal of which is coupled to the output control node.

[0039] The second control unit includes a third transistor, the gate of which and the second terminal of which are both coupled to the first level signal input terminal;

[0040] The first control unit includes a fourth transistor, the gate of which is coupled to the output control node, the first terminal of which is coupled to the first terminal of the third transistor, and the second terminal of which is coupled to the second level signal input terminal.

[0041] The sixth control unit includes an eighth transistor and a second capacitor; the gate of the eighth transistor is coupled to the control signal input terminal, the first electrode of the eighth transistor is coupled to the first level signal input terminal, and the second electrode of the eighth transistor is coupled to the target output terminal; the first plate of the second capacitor is coupled to the first level signal input terminal, and the second plate of the second capacitor is coupled to the target output terminal.

[0042] The fifth control unit includes a ninth transistor, the gate of which is coupled to the first terminal of the fourth transistor, the first terminal of which is coupled to the second level signal input terminal, and the second terminal of which is coupled to the target output terminal.

[0043] Optionally, the first control sub-circuit includes a first transistor, the gate of the first transistor being coupled to the control signal input terminal, the first electrode of the first transistor being coupled to the first level signal input terminal, and the second electrode of the first transistor being coupled to the output control node.

[0044] The second control sub-circuit includes a second transistor, the gate of which is coupled to the adjustable data signal input terminal, the first terminal of which is coupled to the analog signal input terminal, and the second terminal of which is coupled to the output control node.

[0045] The seventh control unit includes a tenth transistor, the gate of which is coupled to the output control node, the first terminal of which is coupled to the second level signal input terminal, and the second terminal of which is coupled to the target output terminal.

[0046] The eighth control unit includes an eleventh transistor, the gate of which is coupled to the output control node, the first terminal of which is coupled to the first level signal input terminal, and the second terminal of which is coupled to the target output terminal; one of the eleventh transistor and the tenth transistor is a P-type transistor and the other is an N-type transistor.

[0047] Optionally, the third output compensation sub-circuit includes a twelfth transistor, the gate of which is coupled to the target output terminal, the first terminal of which is coupled to the second level signal input terminal, and the second terminal of which is coupled to the output control node.

[0048] Optionally, the first control sub-circuit includes a first transistor, the gate of the first transistor being coupled to the control signal input terminal, the first electrode of the first transistor being coupled to the first level signal input terminal, and the second electrode of the first transistor being coupled to the output control node.

[0049] The second control sub-circuit includes a second transistor, the gate of which is coupled to the adjustable data signal input terminal, the first terminal of which is coupled to the analog signal input terminal, and the second terminal of which is coupled to the output control node.

[0050] Optionally, the first control sub-circuit includes a first transistor, the gate of the first transistor being coupled to the control signal input terminal, the first electrode of the first transistor being coupled to the first level signal input terminal, and the second electrode of the first transistor being coupled to the output control node.

[0051] The second control sub-circuit includes a second transistor, the gate of which is coupled to the adjustable data signal input terminal, the first terminal of which is coupled to the analog signal input terminal, and the second terminal of which is coupled to the output control node.

[0052] The second control unit includes a third transistor, the gate of which and the second terminal of which are both coupled to the first level signal input terminal;

[0053] The first control unit includes a fourth transistor, the gate of which is coupled to the output control node, the first terminal of which is coupled to the first terminal of the third transistor, and the second terminal of which is coupled to the second level signal input terminal.

[0054] Optionally, the signal generation circuit further includes a capacitor structure, wherein a first end of the capacitor structure is coupled to the output control node, and a second end of the capacitor structure is coupled to the first level signal input terminal.

[0055] Optionally, the analog signal input terminal is used to input a periodic analog signal, the level value of which changes linearly within one cycle.

[0056] Based on the above-described signal generation circuit, a second aspect of this disclosure provides a display device including the above-described signal generation circuit.

[0057] Based on the above-described signal generation circuit technical solution, a third aspect of this disclosure provides a driving method for the signal generation circuit, used to drive the signal generation circuit; the driving method includes a periodic output stage, the output stage including a first level output stage and a second level output stage; an analog signal with periodicity is input at an analog signal input terminal; in one of the output stages, the level value of the analog signal changes linearly;

[0058] During the first level output phase, the second control sub-circuit, under the joint control of the adjustable data signal input terminal and the analog signal input terminal, controls the disconnection of the electrical connection between the analog signal input terminal and the output control node.

[0059] During the initial phase of the first level output stage, the first control sub-circuit, under the control of the control signal input terminal, controls the electrical connection between the first level signal input terminal and the output control node to be turned on; during the non-initial phase of the first level output stage, the first control sub-circuit, under the control of the control signal input terminal, controls the electrical connection between the first level signal input terminal and the output control node to be turned off.

[0060] During the second level output phase:

[0061] Under the control of the control signal input terminal, the first control sub-circuit controls the disconnection of the electrical connection between the first level signal input terminal and the output control node;

[0062] The second control sub-circuit, under the joint control of the adjustable data signal input terminal and the analog signal input terminal, controls the electrical connection between the analog signal input terminal and the output control node.

[0063] Optionally, the signal generation circuit further includes: an output control sub-circuit, wherein the output control node is coupled to the target output terminal through the output control sub-circuit, and the output control sub-circuit is also coupled to the first level signal input terminal and the second level signal input terminal respectively; the driving method further includes:

[0064] During the first level output phase, the output control sub-circuit, under the control of the output control node, controls the target output terminal to receive the second level signal output from the second level signal input terminal;

[0065] During the second level output phase, the output control sub-circuit, under the control of the output control node, controls the target output terminal to receive the first level signal output from the first level signal input terminal.

[0066] Optionally, during the first level output stage, the output control sub-circuit, under the control of the first level signal input terminal, controls the electrical connection between the first level signal input terminal and the target output terminal to be connected; the output control sub-circuit, under the control of the output control node, controls the electrical connection between the second level signal input terminal and the target output terminal to be connected.

[0067] During the second level output phase, the output control sub-circuit, under the control of the first level signal input terminal, controls the electrical connection between the first level signal input terminal and the target output terminal to be turned on; under the control of the output control node, the output control sub-circuit controls the electrical connection between the second level signal input terminal and the target output terminal to be turned off.

[0068] Optionally, the output control sub-circuit includes: a first control unit and a second control unit; a first terminal of the first control unit is coupled to the output control node, a second terminal of the first control unit is coupled to the second level signal input terminal, and a third terminal of the first control unit is coupled to the target output terminal; a first terminal of the second control unit is coupled to the first level signal input terminal, a second terminal of the second control unit is coupled to the first level signal input terminal, and a third terminal of the second control unit is coupled to the target output terminal.

[0069] During the first level output phase, the first control unit, under the control of the output control node, controls the electrical connection between the second level signal input terminal and the target output terminal to be turned on; the second control unit, under the control of the first level signal input terminal, controls the electrical connection between the first level signal input terminal and the third terminal of the second control unit to be turned on.

[0070] During the second level output phase, the first control unit, under the control of the output control node, controls to disconnect the electrical connection between the second level signal input terminal and the target output terminal; the second control unit, under the control of the first level signal input terminal, controls to connect the electrical connection between the first level signal input terminal and the target output terminal.

[0071] Optionally, the signal generation circuit further includes: a first output compensation sub-circuit, wherein the third terminal of the first control unit and the third terminal of the second control unit are coupled together, and are coupled to the target output terminal through the first output compensation sub-circuit; the first output compensation sub-circuit is also coupled to the first level signal input terminal, the second level signal input terminal and the output control node respectively; the driving method further includes:

[0072] During the first level output phase, the first output compensation sub-circuit, under the control of the output control node, controls the electrical connection between the second level signal input terminal and the target output terminal to be turned on; the first output compensation sub-circuit, under the control of the third terminal of the first control unit, also controls the electrical connection between the first level signal input terminal and the target output terminal to be turned off.

[0073] During the second level output phase, the first output compensation sub-circuit, under the control of the output control node, controls to disconnect the electrical connection between the second level signal input terminal and the target output terminal; the first output compensation sub-circuit, under the control of the third terminal of the first control unit, also controls to connect the electrical connection between the first level signal input terminal and the target output terminal.

[0074] Optionally, the signal generation circuit further includes: a second output compensation sub-circuit, wherein the third terminal of the first control unit and the third terminal of the second control unit are coupled together, and are coupled to the target output terminal through the second output compensation sub-circuit; the second output compensation sub-circuit is also coupled to the control signal input terminal, the first level signal input terminal, and the second level signal input terminal respectively; the driving method further includes:

[0075] During the first level output phase, the second output compensation sub-circuit, under the control of the third terminal of the first control unit, controls to disconnect the electrical connection between the second level signal input terminal and the target output terminal; the second output compensation sub-circuit, under the control of the control signal input terminal, also controls to connect the electrical connection between the first level signal input terminal and the target output terminal.

[0076] During the second level output phase, the second output compensation sub-circuit, under the control of the third terminal of the first control unit, controls the electrical connection between the second level signal input terminal and the target output terminal to be turned on; the second output compensation sub-circuit, under the control of the control signal input terminal, also controls the electrical connection between the first level signal input terminal and the target output terminal to be turned off.

[0077] Optionally, during the first level output stage, the output control sub-circuit is configured to, under the control of the output control node, control the electrical connection between the second level signal input terminal and the target output terminal to be turned on; and is also configured to, under the control of the output control node, control the electrical connection between the first level signal input terminal and the target output terminal to be turned off.

[0078] During the second level output phase, the output control sub-circuit is used, under the control of the output control node, to control the disconnection of the electrical connection between the second level signal input terminal and the target output terminal; and is also used, under the control of the output control node, to control the connection between the first level signal input terminal and the target output terminal.

[0079] Optionally, the signal generation circuit further includes: a third output compensation sub-circuit, coupled to the target output terminal, the second level signal input terminal, and the output control node respectively; the driving method further includes:

[0080] During the first level output stage, the third output compensation sub-circuit, under the control of the target output terminal, controls the disconnection of the electrical connection between the second level signal input terminal and the output control node.

[0081] During the second level output phase, the third output compensation sub-circuit, under the control of the target output terminal, controls the electrical connection between the second level signal input terminal and the output control node to be turned on. Attached Figure Description

[0082] The accompanying drawings, which are included to provide a further understanding of this disclosure and form part of this disclosure, illustrate exemplary embodiments of the present disclosure and are used to explain the disclosure, but do not constitute an undue limitation of the disclosure. In the drawings:

[0083] Figure 1 is a schematic diagram of the first module of the signal generation circuit provided in an embodiment of this disclosure;

[0084] Figure 2 is a schematic diagram of the second module of the signal generation circuit provided in an embodiment of this disclosure;

[0085] Figure 3 is a schematic diagram of the third module of the signal generation circuit provided in an embodiment of this disclosure;

[0086] Figure 4 is a schematic diagram of the fourth module of the signal generation circuit provided in the embodiment of this disclosure;

[0087] Figure 5 is a schematic diagram of the first circuit structure of the signal generation circuit provided in an embodiment of this disclosure;

[0088] Figure 6 is a schematic diagram of the second circuit structure of the signal generation circuit provided in an embodiment of this disclosure;

[0089] Figure 7 is a schematic diagram of the third circuit structure of the signal generation circuit provided in an embodiment of this disclosure;

[0090] Figure 8 is a schematic diagram of the fourth circuit structure of the signal generation circuit provided in an embodiment of this disclosure;

[0091] Figure 9 is a first operating timing diagram of the signal generation circuit provided in an embodiment of this disclosure;

[0092] Figure 10 is a schematic diagram of the fifth circuit structure of the signal generation circuit provided in the embodiment of this disclosure;

[0093] Figure 11 is a schematic diagram of the sixth circuit structure of the signal generation circuit provided in the embodiment of this disclosure;

[0094] Figure 12 is a schematic diagram of the seventh circuit structure of the signal generation circuit provided in the embodiment of this disclosure;

[0095] Figure 13 is a schematic diagram of the eighth circuit structure of the signal generation circuit provided in the embodiment of this disclosure;

[0096] Figure 14 is a second operating timing diagram of the signal generation circuit provided in an embodiment of this disclosure;

[0097] Figure 15 is a schematic diagram of the fifth module of the signal generation circuit provided in an embodiment of this disclosure;

[0098] Figure 16 is a schematic diagram of the sixth module of the signal generation circuit provided in an embodiment of this disclosure;

[0099] Figure 17 is a schematic diagram of the ninth circuit structure of the signal generation circuit provided in the embodiment of this disclosure;

[0100] Figure 18 is a schematic diagram of the tenth circuit structure of the signal generation circuit provided in an embodiment of this disclosure;

[0101] Figure 19 is a third operating timing diagram of the signal generation circuit provided in an embodiment of this disclosure;

[0102] Figure 20 is a schematic diagram of the eleventh circuit structure of the signal generation circuit provided in an embodiment of this disclosure;

[0103] Figure 21 is a schematic diagram of the twelfth circuit structure of the signal generation circuit provided in an embodiment of this disclosure;

[0104] Figure 22 is a fourth operating timing diagram of the signal generation circuit provided in an embodiment of this disclosure;

[0105] Figure 23 is a schematic diagram of the seventh module of the signal generation circuit provided in an embodiment of this disclosure. Detailed Implementation

[0106] To further illustrate the signal generation circuit, driving method, and display device provided in the embodiments of this disclosure, a detailed description is provided below with reference to the accompanying drawings.

[0107] With the continuous development of display technology, display products are gradually moving towards higher resolution and lower power consumption. Consequently, the functions of the driving circuits in these products are also increasing. To achieve these additional functions, timing signals are often required in the driving circuits. These timing signals have wide applications in display products, such as clock signals in gate drive circuits (e.g., GOA, EOA) and pulse width modulation (PWM) signals with different duty cycles for pixel driving.

[0108] In related technologies, the timing signals required for PWM, GOA, EOA, etc., are all provided by the driver chip. However, the period frequency and duty cycle of the timing signals provided by the driver chip are not adjustable. If multiple signals with different duty cycles are required, they need to be provided separately through multiple channels in the driver chip. However, the number of channels in the driver chip of high-resolution display products is limited, and backplane traces corresponding to each channel need to be added within the limited layout space. This makes it difficult to adjust the display brightness, frequency, etc. by adjusting the duty cycle of the timing signals.

[0109] Therefore, how to adjust the period frequency and duty cycle of timing signals without occupying too many driver chip channels has become an urgent technical problem to be solved.

[0110] Please refer to Figure 23. This embodiment of the present disclosure provides a signal generation circuit, including: a first control sub-circuit 1, a second control sub-circuit 2, an output control node G1, and a target output terminal Gout; the output control node G1 is coupled to the target output terminal Gout.

[0111] The first control sub-circuit 1 is coupled to the control signal input terminal HF, the first level signal input terminal P1 and the output control node G1 respectively; it is used to control the electrical connection between the first level signal input terminal P1 and the output control node G1 to be turned on or off under the control of the control signal input terminal HF.

[0112] The second control sub-circuit 2 is coupled to the adjustable data signal input terminal DG, the analog signal input terminal SA, and the output control node G1, respectively; it is used to control the electrical connection between the analog signal input terminal SA and the output control node G1 under the joint control of the adjustable data signal input terminal DG and the analog signal input terminal SA.

[0113] For example, the analog signal input terminal SA is used to input a periodic analog signal whose level value changes linearly within one cycle.

[0114] For example, when driving the signal generation circuit, the driving method includes a periodic output phase, which includes a first level output phase and a second level output phase. One of the first level output phase and the second level output phase is a valid level output phase, and the other is an invalid level output phase. The target signal output by the target output terminal Gout has a valid level in the valid level output phase and an invalid level in the invalid level output phase. The ratio of the duration of the target signal being at a valid level to the total duration of one period is the duty cycle of the target signal.

[0115] For example, the control signal input terminal HF is used to input a periodic timing control signal, the first level signal input terminal P1 is used to input a first level signal, and the first control sub-circuit 1 is used to control whether to transmit the first level signal to the output control node G1 under the control of the timing control signal.

[0116] For example, the adjustable data signal input terminal DG is used to input an adjustable data signal, the data voltage value of which can be adjusted as needed at any time during each output stage. The analog signal input terminal SA is used to input a periodic analog signal, the period of which corresponds to the period of the output stage. The level value of the analog signal changes linearly within one period, and the level change of the analog signal is the same in each output stage, but not limited to this.

[0117] For example, the second control sub-circuit 2 controls whether to transmit the analog signal to the output control node G1 under the joint control of the adjustable data signal and the analog signal.

[0118] Based on the specific structure of the signal generation circuit described above, the first control sub-circuit 1 can control whether to transmit the first level signal to the output control node G1 under the control of the control signal input terminal HF; the second control sub-circuit 2 can control whether to transmit the analog signal to the output control node G1 under the joint control of the adjustable data signal input terminal DG and the analog signal input terminal SA.

[0119] In one output stage of the signal generation circuit:

[0120] During the first level output stage, the second control sub-circuit 2, under the joint control of the adjustable data signal input terminal DG and the analog signal input terminal SA, controls the disconnection of the electrical connection between the analog signal input terminal SA and the output control node G1.

[0121] During the initial phase of the first level output phase, the first control sub-circuit 1 is used to control the electrical connection between the first level signal input terminal P1 and the output control node G1 under the control of the control signal input terminal HF; during the non-initial phase of the first level output phase, the first control sub-circuit 1 is used to control the electrical connection between the first level signal input terminal P1 and the output control node G1 under the control of the control signal input terminal HF.

[0122] Therefore, during the first level output phase, the output control node G1 has the same potential as the first level signal.

[0123] During the second-level output stage, the first control sub-circuit 1 is used to control the disconnection of the electrical connection between the first-level signal input terminal P1 and the output control node G1 under the control of the control signal input terminal HF; the second control sub-circuit 2 is used to control the connection of the electrical connection between the analog signal input terminal SA and the output control node G1 under the joint control of the adjustable data signal input terminal DG and the analog signal input terminal SA.

[0124] Therefore, during the second level output phase, the output control node G1 has the same potential as the analog signal.

[0125] Since the data voltage value of the adjustable data signal is adjustable at any time, and the level value of the analog signal changes linearly, in one output stage, with the data voltage value fixed, as the level value of the analog signal changes, when the level value of the analog signal is greater than (or less than) a certain threshold, the second control sub-circuit 2 controls the disconnection of the electrical connection between the analog signal input terminal SA and the output control node G1, so that the output control node G1 has a first potential the same as the first level signal; when the level value of the analog signal is less than (or greater than) a certain threshold, the second control sub-circuit 2 controls the connection between the analog signal input terminal SA and the output control node G1, so that the output control node G1 has a second potential the same as the analog signal. One of the first potential and the second potential controls the target signal to have a valid level in the valid level output stage, and the other of the first potential and the second potential controls the target signal to have an invalid level in the invalid level output stage. Further, in different output stages, by changing the data voltage value, the time when the output control node G1 is at the first potential and the time when it is at the second potential can be adjusted, thereby changing the time when the target signal is at the valid level and the time when it is at the invalid level. The target signal can be used as a clock signal in a gate drive circuit (such as GOA, EOA), or as a pulse width modulation signal (PWM) with different duty cycles for pixel driving, but is not limited to these.

[0126] In the signal generation circuit provided in this embodiment, by changing the data voltage value of the adjustable data signal input at the adjustable data signal input terminal DG, and setting the level value of the analog signal input at the analog signal input terminal SA to change linearly in each output stage, the output control node G1 can be controlled for the time it is at the first potential and the time it is at the second potential, thereby controlling the time the target signal output at the target output terminal Gout is at the effective level and the time it is at the ineffective level, thus realizing the adjustment of the duty cycle of the target signal.

[0127] Furthermore, in the signal generation circuit provided in this embodiment, the control signal input at the control signal input terminal HF can control whether the first control sub-circuit 1 is turned on, and the adjustable data signal input at the adjustable data signal input terminal DG and the analog signal input at the analog signal input terminal SA can control whether the second control sub-circuit 2 is turned on. Therefore, the frequency of the output target signal with periodicity is jointly determined by the control signal input terminal HF, the adjustable data signal input terminal DG, and the analog signal input terminal SA.

[0128] Therefore, in the signal generation circuit provided in this embodiment, the period, frequency, and duty cycle of the target signal output from the target output terminal Gout can be adjusted in real time simply by adjusting the control signal, the adjustable data signal, and the analog signal. Thus, the signal generation circuit provided in this embodiment can adjust the frequency and duty cycle of the target signal without occupying too many driver chip channels. This makes it more advantageous to apply the signal generation circuit provided in this embodiment to display products, enabling high-resolution layouts and real-time adjustments to display brightness and frequency.

[0129] As shown in Figures 2 and 15, in some embodiments, the signal generation circuit further includes:

[0130] The output control sub-circuit 3 is used to couple the output control node G1 to the target output terminal Gout. The output control sub-circuit 3 is also coupled to the first level signal input terminal P1 and the second level signal input terminal P2 respectively. The output control sub-circuit 3 is used to control the target output terminal Gout to receive the first level signal output from the first level signal input terminal P1, or to control the target output terminal Gout to receive the second level signal output from the second level signal input terminal P2, under the control of the output control node G1.

[0131] During the first level output phase, the output control sub-circuit 3, under the control of the output control node G1, controls the target output terminal Gout to receive the second level signal output from the second level signal input terminal; during the second level output phase, the output control sub-circuit 3, under the control of the output control node G1, controls the target output terminal Gout to receive the first level signal output from the first level signal input terminal.

[0132] The output control sub-circuit 3 is connected between the output control node G1 and the target output terminal Gout. The output control node G1 controls the output control sub-circuit 3 to transmit a first level signal or a second level signal to the target output terminal Gout, so that in the first level output stage, the output control node G1 has the same potential as the second level signal, and in the second level output stage, the output control node G1 has the same potential as the first level signal.

[0133] When the output control node G1 is directly coupled to the target output terminal Gout, since the analog signal is a linearly gradually changing signal, the second control sub-circuit 2 controls the electrical connection between the analog signal input terminal SA and the output control node G1 to be turned on slowly. This results in the analog signal being written to the target output terminal Gout slowly, causing the Tf (fall time) or Tr (rise time) of the target signal to be very large. At the same time, it causes the high voltage or low voltage part of the target signal to be a gradually changing analog signal instead of a stable DC signal, resulting in poor stability.

[0134] The aforementioned configuration connects the output control node G1 to the target output terminal Gout via the output control sub-circuit 3. This allows the output control sub-circuit 3, under the control of the output control node G1, to control the target output terminal Gout to receive either the first-level signal output from the first-level signal input terminal or the second-level signal output from the second-level signal input terminal. Therefore, when the potential of the output control node G1 reaches a certain threshold, the target signal output by the target output terminal Gout can be controlled to be either the first-level signal or the second-level signal, without being affected by the gradual change in the analog signal. This improves the problem of a large Tf (fall time) or Tr (rise time) in the target signal. Furthermore, by controlling the target signal output by the target output terminal Gout to be either the first-level signal or the second-level signal through the output control node G1, the high-voltage or low-voltage portion of the target signal is prevented from being a gradually changing analog signal, ensuring that the high-voltage or low-voltage portion of the target signal is a stable DC signal with good stability.

[0135] As shown in Figure 2, in some embodiments, the output control sub-circuit 3 is used to control the electrical connection between the second level signal input terminal P2 and the target output terminal Gout under the control of the output control node G1; it is also used to control the electrical connection between the first level signal input terminal P1 and the target output terminal Gout under the control of the first level signal input terminal P1.

[0136] During the first level output phase, the output control sub-circuit 3, under the control of the first level signal input terminal P1, controls the electrical connection between the first level signal input terminal P1 and the target output terminal Gout to be connected; under the control of the output control node G1, the output control sub-circuit 3 controls the electrical connection between the second level signal input terminal P2 and the target output terminal Gout to be connected; during the second level output phase, the output control sub-circuit 3, under the control of the first level signal input terminal P1, controls the electrical connection between the first level signal input terminal P1 and the target output terminal Gout to be connected; under the control of the output control node G1, the output control sub-circuit 3 controls the electrical connection between the second level signal input terminal P2 and the target output terminal Gout to be disconnected.

[0137] As shown in Figure 2, exemplarily, the output control sub-circuit 3 includes: a first control unit 31 and a second control unit 32; a first terminal of the first control unit 31 is coupled to the output control node G1, a second terminal of the first control unit 31 is coupled to the second level signal input terminal P2, and a third terminal of the first control unit 31 is coupled to the target output terminal Gout; the first control unit 31 is used to control the electrical connection between the second level signal input terminal P2 and the target output terminal Gout under the control of the output control node G1; a first terminal of the second control unit 32 is coupled to the first level signal input terminal P1, a second terminal of the second control unit 32 is coupled to the first level signal input terminal P1, and a third terminal of the second control unit 32 is coupled to the target output terminal Gout; the second control unit 32 is used to control the electrical connection between the first level signal input terminal P1 and the target output terminal Gout under the control of the first level signal input terminal P1.

[0138] During the first level output phase, the first control unit 31, under the control of the output control node G1, controls the electrical connection between the second level signal input terminal P2 and the target output terminal Gout; the second control unit 32, under the control of the first level signal input terminal P1, controls the electrical connection between the first level signal input terminal P1 and the third terminal of the second control unit 32.

[0139] During the second level output phase, the first control unit 31, under the control of the output control node G1, controls to disconnect the electrical connection between the second level signal input terminal P2 and the target output terminal Gout; the second control unit 32, under the control of the first level signal input terminal P1, controls to connect the electrical connection between the first level signal input terminal P1 and the target output terminal Gout.

[0140] The above configuration allows the output control sub-circuit 3 to control the target output terminal Gout to receive the second-level signal input from the second-level signal input terminal P2 under the control of the output control node G1, and to control the target output terminal Gout to receive the first-level signal input from the first-level signal input terminal P1 under the control of the first-level signal input terminal P1. Therefore, when the potential of the output control node G1 reaches a certain threshold, the target signal output by the target output terminal Gout can be controlled to be either a first-level signal or a second-level signal, without being affected by the gradual change of the analog signal, thereby improving the problem of a large Tf (fall time) or Tr (rise time) of the target signal. Moreover, by controlling the target signal output by the target output terminal Gout to be either a first-level signal or a second-level signal through the output control node G1, the high-voltage or low-voltage part of the target signal is avoided from being a gradually changing analog signal, making the high-voltage or low-voltage part of the target signal a stable DC signal with good stability.

[0141] As shown in Figure 3, in some embodiments, the signal generation circuit further includes: a first output compensation sub-circuit 4, wherein the third terminal of the first control unit 31 and the third terminal of the second control unit 32 are coupled to form a G2-1 node, and are coupled to the target output terminal Gout through the first output compensation sub-circuit 4; the first output compensation sub-circuit 4 is also coupled to the first level signal input terminal P1, the second level signal input terminal P2 and the output control node G1 respectively;

[0142] The first output compensation sub-circuit 4 is used to: control the electrical connection between the second level signal input terminal P2 and the target output terminal Gout under the control of the output control node G1; and is also used to control the electrical connection between the first level signal input terminal P1 and the target output terminal Gout under the control of the third terminal (i.e., node G2-1) of the first control unit 31.

[0143] During the first level output stage, the first output compensation sub-circuit 4, under the control of the output control node G1, controls the electrical connection between the second level signal input terminal P2 and the target output terminal Gout to be turned on; the first output compensation sub-circuit 4, under the control of the third terminal (i.e., node G2-1) of the first control unit 31, also controls the electrical connection between the first level signal input terminal P1 and the target output terminal Gout to be turned off.

[0144] During the second level output stage, the first output compensation sub-circuit 4, under the control of the output control node G1, controls to disconnect the electrical connection between the second level signal input terminal P2 and the target output terminal Gout; the first output compensation sub-circuit 4, under the control of the third terminal (i.e., node G2-1) of the first control unit 31, also controls to connect the electrical connection between the first level signal input terminal P1 and the target output terminal Gout.

[0145] As shown in Figure 3, for example, the first output compensation sub-circuit 4 includes: a third control unit 41 and a fourth control unit 42; the third control unit 41 is coupled to the output control node G1, the second level signal input terminal P2 and the target output terminal Gout respectively, and is used to control the electrical connection between the second level signal input terminal P2 and the target output terminal Gout under the control of the output control node G1; the fourth control unit 42 is coupled to the third terminal (i.e., node G2-1) of the first control unit 31, the first level signal input terminal P1 and the target output terminal Gout respectively, and is used to control the electrical connection between the first level signal input terminal P1 and the target output terminal Gout under the control of the third terminal (i.e., node G2-1) of the first control unit 31.

[0146] During the first level output phase, the third control unit 41, under the control of the output control node G1, controls the electrical connection between the second level signal input terminal P2 and the target output terminal Gout to be turned on; the fourth control unit 42, under the control of the third terminal (i.e., node G2-1) of the first control unit 31, controls the electrical connection between the first level signal input terminal P1 and the target output terminal Gout to be turned off.

[0147] During the second level output phase, the third control unit 41 is used to control the disconnection of the electrical connection between the second level signal input terminal P2 and the target output terminal Gout under the control of the output control node G1; the fourth control unit 42 is used to control the connection of the electrical connection between the first level signal input terminal P1 and the target output terminal Gout under the control of the third terminal (i.e., node G2-1) of the first control unit 31.

[0148] When the signal generation circuit includes the output control sub-circuit 3 but does not include the first output compensation sub-circuit 4, when both the first control unit 31 and the second control unit 32 are turned on, the potential of the target signal is actually the voltage division of the first control unit 31 and the second control unit 32, which makes it impossible for the potential of the target signal to fully reach the second level. Moreover, there is still room for improvement in the Tf (fall time) or Tr (rise time) of the target signal.

[0149] By configuring the signal generation circuit to include the output control sub-circuit 3 and the first output compensation sub-circuit 4, when the potential of the target signal is controlled to be at the second level, the third control unit 41 can conduct the electrical connection between the second level signal input terminal P2 and the target output terminal Gout, and the fourth control unit 42 can disconnect the electrical connection between the first level signal input terminal P1 and the target output terminal Gout. Therefore, the potential of the target signal is not a voltage divider between the first control unit 31 and the second control unit 32, and the potential of the target signal can fully reach the second level. Moreover, this configuration further improves the Tf (fall time) or Tr (rise time) of the target signal.

[0150] It should be noted that in the accompanying drawings of this disclosure, transistors marked M are N-type transistors, and those marked T are P-type transistors. All sub-circuits and control units in this disclosure can use either N-type or P-type transistors. When using N-type transistors, the signal generation circuit is connected to the following signal terminals: control signal input terminal HF1, adjustable data signal input terminal DG1, analog signal input terminal SA1, target output terminal GNout, first-level signal input terminal P1 (VDD signal input), and second-level signal input terminal P2 (VSS signal input). When using P-type transistors, the signal generation circuit is connected to the following signal terminals: control signal input terminal HF2, adjustable data signal input terminal DG2, analog signal input terminal SA2, target output terminal GPout, first-level signal input terminal P1 (VSS signal input), and second-level signal input terminal P2 (VDD signal input).

[0151] As shown in Figures 5 to 7 and Figures 10 to 12, in some embodiments, the first control sub-circuit 1 includes a first transistor (e.g., M1, T1), the gate of the first transistor is coupled to the control signal input terminal HF, the first terminal of the first transistor is coupled to the first level signal input terminal P1, and the second terminal of the first transistor is coupled to the output control node G1.

[0152] The second control sub-circuit 2 includes a second transistor (e.g., M2, T2), the gate of the second transistor is coupled to the adjustable data signal input terminal DG, the first terminal of the second transistor is coupled to the analog signal input terminal SA, and the second terminal of the second transistor is coupled to the output control node G1;

[0153] The second control unit 32 includes a third transistor (e.g., M3, T3), the gate of the third transistor and the second terminal of the third transistor are both coupled to the first level signal input terminal P1;

[0154] The first control unit 31 includes a fourth transistor (e.g., M4, T4), the gate of the fourth transistor is coupled to the output control node G1, the first terminal of the fourth transistor is coupled to the first terminal of the third transistor, and the second terminal of the fourth transistor is coupled to the second level signal input terminal P2.

[0155] The fourth control unit 42 includes a fifth transistor (e.g., M5, T5), the gate of the fifth transistor is coupled to the first terminal of the fourth transistor, the first terminal of the fifth transistor is coupled to the first level signal input terminal P1, and the second terminal of the fifth transistor is coupled to the target output terminal Gout.

[0156] The third control unit 41 includes a sixth transistor (e.g., M6, T6), the gate of the sixth transistor is coupled to the output control node G1, the first terminal of the sixth transistor is coupled to the second level signal input terminal P2, and the second terminal of the sixth transistor is coupled to the target output terminal Gout.

[0157] As shown in Figures 5 to 7, the signal generation circuit is implemented using N-type transistors. The timing diagrams for each signal are shown in Figure 9. In this case, the first level signal input terminal P1 receives the VDD signal, the second level signal input terminal P2 receives the VSS signal, and the analog signal input terminal SA1 receives an analog signal whose level changes from -10V to -20V within one cycle. The adjustable data signal's voltage value within each cycle can be adjusted to any value as needed. The specific operation of the signal generation circuit will be explained in detail below using data voltage signal values ​​of -21V, -17V, -14V, -12V, and -10.5V as examples.

[0158] For example, the control signal input at the control signal input terminal HF1 has the following parameters: frequency 2000Hz, one cycle 500µs, duty cycle (15V / -20V) = 1 / 499µs, 15V represents the voltage value when the control signal is at a high level, and -20V represents the voltage value when the brainwashing is at a low level. The analog signal input at the analog signal input terminal SA1 has the following parameters: frequency 2000Hz, voltage variation range within one cycle -10V to -20V. The VSS signal includes a -10V DC signal. The VDD signal includes a 10V DC signal.

[0159] As shown in Figures 5 and 9, the control signal input at the control signal input terminal HF1 turns on the first transistor M1 at the beginning of each cycle, resetting the target signal output at the target output terminal GNout1 to the VDD signal. The gate-source voltage Vgs of the second transistor M2 is equal to the difference between the data voltage value of the adjustable data signal input at the adjustable data signal input terminal DG1 and the voltage value of the analog signal input at the analog signal input terminal SA1. When Vgs < Vth, Vth is the threshold voltage of the second transistor M2, the second transistor M2 is turned off, and the target signal output at the target output terminal GNout1 remains at a high voltage. When Vgs > Vth, the second transistor M2 is turned on, the analog signal is transmitted to the target output terminal GNout1, and the potential of the target signal becomes low voltage. The case of Vgs < Vth corresponds to the first level output stage, and the case of Vgs > Vth corresponds to the second level output stage.

[0160] As shown in Figure 9, when the data voltage is -21V, Vgs = -11V to -1V < Vth, the second transistor M2 is always off, and the target signal output from the target output terminal GNout1 remains at a high voltage, with a duty cycle of 100%. When the data voltage is -17V, Vgs = -7V to 3V. In the -7V to Vth range, the second transistor M2 is off, and the target signal output from the target output terminal GNout1 is at a high potential. In the Vth to 3V range, the second transistor M2 is on, and the analog signal is transmitted to the target output terminal GNout1, changing the potential of the target signal to a low voltage. The duty cycle of the target signal is 82%. Similarly, when the data voltage is -14V, -12V, and -10.5V, the duty cycles of the target signal are 55%, 34%, and 20%, respectively. In summary, the period of the target signal is determined by the control signal input terminal HF1 and the analog signal input terminal SA1, while the duty cycle is determined by the adjustable data signal input terminal DG1.

[0161] Although the above embodiment achieves a target signal with adjustable duty cycle, the analog signal input to the analog signal input terminal SA1 is gradually changing. The Vgs of the second transistor M2 changes at the same rate as the analog signal. This causes the second transistor M2 to turn on slowly, and the analog signal is transmitted to the target output terminal GNout1 slowly, resulting in a large Tf of the target signal. At the same time, the low-voltage part of the target signal is a gradually changing analog signal, which is not a stable DC signal and has poor stability.

[0162] Furthermore, as shown in Figures 6 and 9, a third transistor M3 and a fourth transistor M4 are added. The third transistor M3 is normally open under the control of the VDD signal. The output signal of the output control node G1 is written to the gate of the fourth transistor M4. When the output signal of the output control node G1 is VDD, the fourth transistor M4 is turned on. According to the voltage divider principle of the series circuit, the target output terminal GNout2 outputs the VSS signal. When the output signal of the output control node G1 is an analog signal, the fourth transistor M4 is turned off, and the target output terminal GNout2 outputs the VDD signal. On the one hand, when the output signal of the output control node G1 drops to around -10V, the fourth transistor M4 is basically turned off, and the VDD signal is written to the target output terminal GNout2 through the third transistor M3. The target signal is a high-voltage signal, and it is not necessary to wait for the output signal of the output control node G1 to drop further. Therefore, the Tr of the target signal can be significantly reduced. On the other hand, after the output signal of the output control node G1 drops below -10V, the fourth transistor M4 remains off, and the target output terminal GNout2 stably outputs the high-voltage target signal, solving the problem of gradual change of the target signal.

[0163] However, in the above embodiments, on the one hand, when the target output terminal GNout2 outputs a low-voltage target signal, both the third transistor M3 and the fourth transistor M4 are turned on. Due to the voltage division between the third transistor M3 and the fourth transistor M4, the voltage of the output target signal cannot be completely reduced to the same -10V voltage as the VSS signal. On the other hand, the Tr of the target signal is still relatively large after improvement, and there is still room for further improvement.

[0164] More specifically, the current is the same throughout the series circuit, and current = voltage / resistance. Therefore, the ratio between the voltage across the third transistor M3 and the resistance of the third transistor M3 is equal to the ratio between the voltage across the fourth transistor M4 and the resistance of the fourth transistor M4. The voltage across the third transistor M3 is Vdd - VGout, where Vdd is the voltage value of the VDD signal and VGout is the voltage value of the target output terminal. The voltage across the fourth transistor M4 is VGout - Vss, where Vss is the voltage value of the VSS signal.

[0165] The following condition must be met: (Vdd-VGout) / (VGout-Vss)=R3 / R4, where R3 is the resistance of the third transistor M3 and R4 is the resistance of the fourth transistor M4.

[0166] The third transistor M3 is set to have a small width-to-length ratio, so that the resistance of the third transistor M3 is larger than that of the fourth transistor M4. As can be seen from the above formula, the larger the resistance of the third transistor M3 is relative to the resistance of the fourth transistor M4, the closer VGout is to Vss.

[0167] Assuming Vdd = 10V, Vss = -10V, and the resistance of the third transistor M3 is 100 times that of the fourth transistor M4, the voltage VGout can be calculated to be -9.8V; when the resistance of the third transistor M3 is 10 times that of the fourth transistor M4, the voltage VGout can be calculated to be -8.2V.

[0168] There are two ways to adjust the resistance of the third transistor M3: one is to adjust the transistor size (such as the width-to-length ratio W / L) in the layout design; the other is to adjust the gate voltage of the transistor. A low gate voltage results in insufficient transistor activation and a higher resistance. Therefore, in voltage design, the gate voltage of the third transistor M3 is minimized as much as possible without affecting circuit functionality.

[0169] The VDD signal connected to the third transistor M3 is used for output to the target output terminal Gout, i.e., for external use. Therefore, the specific voltage value of the signal can be determined according to actual external requirements. The VDD signal connected to the first transistor M1 is used for transmission to the gate of the fourth transistor M4, i.e., for internal use. Therefore, the voltage value of the VDD signal connected to the first transistor M1 can be set to be higher than the voltage value of the VDD signal connected to the third transistor M3. The higher voltage value can be between 1 and 10V, and can include the endpoint value.

[0170] For example: the voltage value of the VDD signal connected to the first transistor M1 is 15V, and the gate voltage of the fourth transistor M4 is 15V, so that the fourth transistor M4 is turned on more fully; the voltage value of the VDD signal connected to the third transistor M3 is 10V, so that the voltage value of the target signal output to the target output terminal Gout is 10V.

[0171] Further, as shown in Figures 7 and 9, a fifth transistor M5 and a sixth transistor M6 are added. The output signal of the output control node G1 is simultaneously written to the fourth transistor M4 and the sixth transistor M6. The output signal of the first terminal of the fourth transistor (corresponding to node G2-1) is written to the fifth transistor M5. When the output control node G1 outputs a high-voltage signal (i.e., the VDD signal), the fourth transistor M4 and the sixth transistor M6 are turned on. The G2-1 node outputs a low-voltage signal (i.e., the VSS signal), turning off the fifth transistor M5. The target output terminal GNout3 outputs the VSS signal. When the output control node G1 outputs an analog signal, the fourth transistor M4 and the sixth transistor M6 are turned off. The G2-1 node outputs a high-voltage signal, turning on the fifth transistor M5. The target output terminal GNout3 outputs the VDD signal. This method, through the secondary selection of the fifth transistor M5 and the sixth transistor M6, further lowers the low-voltage output of the target output terminal GNout3, improving the Tr of the target signal.

[0172] As shown in Figures 10 to 12, the signal generation circuit is implemented using P-type transistors. The timing diagrams for each signal are shown in Figure 14. In this case, the first level signal input terminal P1 receives the VSS signal, and the second level signal input terminal P2 receives the VDD signal. The analog signal level changes from 10V to 20V within one cycle. The adjustable data signal's data voltage value within each cycle can be adjusted to any value as needed. The specific operation of the signal generation circuit will be explained in detail below using data voltage signal values ​​of 21V, 17V, 14V, 12V, and 10.5V as examples.

[0173] For example, the control signal input at the control signal input terminal HF2 has the following parameters: frequency 2000Hz, one cycle 500µs, duty cycle (-15V / 20V) = 1 / 499µs, -15V represents the voltage value when the control signal is at a low level, and 20V represents the voltage value when the control signal is at a high level. The analog signal input at the analog signal input terminal SA2 has the following parameters: frequency 2000Hz, voltage variation range of 10V to 20V within one cycle. The VSS signal includes a -10V DC signal. The VDD signal includes a 10V DC signal.

[0174] As shown in Figures 10 and 14, the control signal input at the control signal input terminal HF2 turns on the first transistor T1 at the beginning of each cycle, resetting the target signal output at the target output terminal GPout1 to the VSS signal. The gate-source voltage Vgs of the second transistor T2 is equal to the difference between the data voltage value of the adjustable data signal input at the adjustable data signal input terminal DG2 and the voltage value of the analog signal input at the analog signal input terminal SA2. When Vgs > Vth, Vth is the threshold voltage of the second transistor T2, the second transistor T2 is turned off, and the target signal output at the target output terminal GPout1 remains at a low voltage. When Vgs < Vth, the second transistor T2 is turned on, the analog signal is transmitted to the target output terminal GPout1, and the potential of the target signal becomes high voltage. The case of Vgs > Vth corresponds to the first level output stage, and the case of Vgs < Vth corresponds to the second level output stage.

[0175] As shown in Figure 14, when the data voltage is 21V, Vgs = 11V to 1V > Vth, the second transistor T2 is always off, and the target signal output from the target output terminal GPout1 remains at a low voltage, with a duty cycle of 100%. When the data voltage is 17V, Vgs = 7V to -3V. In the 7V to Vth range, the second transistor T2 is off, and the target signal output from the target output terminal GPout1 is at a low potential. In the Vth to -3V range, the second transistor T2 is on, and the analog signal is transmitted to the target output terminal GPout1, changing the potential of the target signal to a high voltage, with a duty cycle of 82%. Similarly, when the data voltage is 14V, 12V, and 10.5V, the duty cycles of the target signal are 55%, 34%, and 20%, respectively. In summary, the period of the target signal is determined by the control signal input terminal HF2 and the analog signal input terminal SA2, while the duty cycle is determined by the adjustable data signal input terminal DG2.

[0176] Although the above embodiment achieves a target signal with adjustable duty cycle, the analog signal input at the analog signal input terminal SA2 is gradually changing. The Vgs of the second transistor T2 changes at the same rate as the analog signal. This causes the second transistor T2 to turn on slowly, and the analog signal is transmitted to the target output terminal GPout1 slowly, resulting in a large Tf of the target signal. At the same time, the high voltage part of the target signal is a gradually changing analog signal, which is not a stable DC signal and has poor stability.

[0177] Furthermore, as shown in Figures 11 and 14, a third transistor T3 and a fourth transistor T4 are introduced. The third transistor T3 is normally open, controlled by the VSS signal. The output signal of the output control node G1 is written to the gate of the fourth transistor T4. When the output signal of the output control node G1 is the VSS signal, the fourth transistor T4 is turned on. According to the voltage divider principle of the series circuit, the target output terminal GPout2 outputs the VDD signal. When the output signal of the output control node G1 is an analog signal, the fourth transistor T4 is turned off, and the target output terminal GPout2 outputs the VSS signal. On the one hand, when the second transistor T2 is turned on and the output signal of the output control node G1 rises to around 10V, the fourth transistor T4 is basically turned off. The VSS signal is written to the target output terminal GPout2 through the third transistor T3, and the target signal is a low-voltage signal. It is not necessary to wait for the output signal of the output control node G1 to rise further, so the Tf of the target signal can be significantly reduced. On the other hand, after the output signal of the output control node G1 rises above 10V, the fourth transistor T4 remains off, and GPout2 stably outputs the low-voltage target signal, solving the problem of target signal gradual change.

[0178] However, in the above embodiment, on the one hand, when the target output terminal GPout2 outputs a high-voltage target signal, both the third transistor T3 and the fourth transistor T4 are turned on. Due to the voltage division between the third transistor T3 and the fourth transistor T4, the voltage of the output target signal cannot be fully increased to the same 10V voltage as the VDD signal. On the other hand, the Tf of the target signal is still relatively large after improvement, and there is still room for further improvement.

[0179] In more detail, referring to the detailed principle analysis of the N-type transistor, it can be seen that: the VSS signal connected to the third transistor T3 is used for output to the target output terminal Gout, that is, for external use. Therefore, the specific voltage value of the signal can be determined according to the actual external requirements. The VSS signal connected to the first transistor T1 is used for transmission to the gate of the fourth transistor T4, that is, for internal use. Therefore, the voltage value of the VSS signal connected to the first transistor T1 can be set lower than the voltage value of the VSS signal connected to the third transistor T3.

[0180] For example: the voltage value of the VSS signal connected to the first transistor T1 is -15V, so the gate voltage of the fourth transistor T4 is -15V, making the fourth transistor T4 turn on more fully; the voltage value of the VSS signal connected to the third transistor T3 is -10V, so that the voltage value of the target signal output to the target output terminal Gout is -10V.

[0181] The principle of setting the signal voltage value when using a P-type transistor is essentially the same as that when using an N-type transistor. Therefore, when actually adjusting the resistance value and the signal voltage value, you can refer to the principle when using an N-type transistor, which will not be repeated here.

[0182] Further, as shown in Figures 12 and 14, a fifth transistor T5 and a sixth transistor T6 are added. The output signal of the output control node G1 is simultaneously written to the fourth transistor T4 and the sixth transistor T6. The output signal of the first terminal of the fourth transistor (corresponding to node G2-1) is written to the fifth transistor T5. When the output control node G1 outputs a low-voltage signal (i.e., the VSS signal), the fourth transistor T4 and the sixth transistor T6 are turned on, the G2-1 node outputs a high-voltage signal (i.e., the VDD signal), and the fifth transistor T5 is turned off. The target output terminal GPout3 outputs the VDD signal. When the output control node G1 outputs an analog signal, the fourth transistor T4 and the sixth transistor T6 are turned off, the G2-1 node outputs a low-voltage signal, and the fifth transistor T5 is turned on. The target output terminal GPout3 outputs a low-voltage VSS signal. This method, through the secondary selection of the fifth transistor M5 and the sixth transistor M6, further lowers the low-voltage output of the target output terminal GPout3, improving the Tf of the target signal.

[0183] As shown in Figure 4, in some embodiments, the signal generation circuit further includes: a second output compensation sub-circuit 5, wherein the third terminal of the first control unit 31 and the third terminal of the second control unit 32 are coupled to form a G2-2 node, and are coupled to the target output terminal Gout through the second output compensation sub-circuit 5; the second output compensation sub-circuit 5 is also coupled to the control signal input terminal HF, the first level signal input terminal P1, and the second level signal input terminal P2, respectively.

[0184] The second output compensation sub-circuit 5 is used to: control the electrical connection between the second level signal input terminal P2 and the target output terminal Gout under the control of the third terminal (i.e., node G2-2) of the first control unit 31; and is also used to control the electrical connection between the first level signal input terminal P1 and the target output terminal Gout under the control of the control signal input terminal HF.

[0185] During the first level output phase, the second output compensation sub-circuit 5, under the control of the third terminal (i.e., node G2-2) of the first control unit 31, controls to disconnect the electrical connection between the second level signal input terminal P2 and the target output terminal Gout; the second output compensation sub-circuit 5, under the control of the control signal input terminal HF, also controls to connect the electrical connection between the first level signal input terminal P1 and the target output terminal Gout.

[0186] During the second level output phase, the second output compensation sub-circuit 5, under the control of the third terminal (i.e., node G2-2) of the first control unit 31, controls the electrical connection between the second level signal input terminal P2 and the target output terminal Gout to be turned on; the second output compensation sub-circuit 5, under the control of the control signal input terminal HF, also controls the electrical connection between the first level signal input terminal P1 and the target output terminal Gout to be turned off.

[0187] As shown in Figure 4, exemplarily, the second output compensation sub-circuit 5 includes: a fifth control unit 51 and a sixth control unit 52; the fifth control unit 51 is coupled to the third terminal (i.e., node G2-2) of the first control unit 31, the second level signal input terminal P2, and the target output terminal Gout, respectively; it is used to control the electrical connection between the second level signal input terminal P2 and the target output terminal Gout to be turned on or off under the control of the third terminal (i.e., node G2-2) of the first control unit 31; the sixth control unit 52 is coupled to the control signal input terminal HF, the first level signal input terminal P1, and the target output terminal Gout, respectively; it is used to control the electrical connection between the first level signal input terminal P1 and the target output terminal Gout to be turned on or off under the control of the control signal input terminal HF.

[0188] During the first level output phase, the fifth control unit 51 is used to control the disconnection of the electrical connection between the second level signal input terminal P2 and the target output terminal Gout under the control of the third terminal (i.e., node G2-2) of the first control unit 31; the sixth control unit 52 is used to control the connection of the electrical connection between the first level signal input terminal P1 and the target output terminal Gout under the control of the control signal input terminal HF.

[0189] During the second level output phase, the fifth control unit 51 is used to control the electrical connection between the second level signal input terminal P2 and the target output terminal Gout under the control of the third terminal (i.e., node G2-2) of the first control unit 31; the sixth control unit 52 is used to control the electrical connection between the first level signal input terminal P1 and the target output terminal Gout under the control of the control signal input terminal HF.

[0190] By configuring the signal generation circuit to include the output control sub-circuit 3 and the second output compensation sub-circuit 5, when the potential of the target signal is controlled to be at the second level, the fifth control unit 51 can conduct the electrical connection between the second level signal input terminal P2 and the target output terminal Gout, and the sixth control unit 52 can disconnect the electrical connection between the first level signal input terminal P1 and the target output terminal Gout. Therefore, the potential of the target signal is not a voltage divider between the first control unit 31 and the second control unit 32, and the potential of the target signal can fully reach the second level. Moreover, this configuration further improves the Tf (fall time) or Tr (rise time) of the target signal.

[0191] As shown in Figures 8 and 13, in some embodiments, the first control sub-circuit 1 includes a first transistor (e.g., M1, T1), the gate of the first transistor is coupled to the control signal input terminal HF, the first terminal of the first transistor is coupled to the first level signal input terminal P1, and the second terminal of the first transistor is coupled to the output control node G1.

[0192] The second control sub-circuit 2 includes a second transistor (e.g., M2, T2), the gate of the second transistor is coupled to the adjustable data signal input terminal DG, the first terminal of the second transistor is coupled to the analog signal input terminal SA, and the second terminal of the second transistor is coupled to the output control node G1;

[0193] The second control unit 32 includes a third transistor (e.g., M3, T3), the gate of the third transistor and the second terminal of the third transistor are both coupled to the first level signal input terminal P1;

[0194] The first control unit 31 includes a fourth transistor (e.g., M4, T4), the gate of the fourth transistor is coupled to the output control node G1, the first terminal of the fourth transistor is coupled to the first terminal of the third transistor, and the second terminal of the fourth transistor is coupled to the second level signal input terminal P2.

[0195] The sixth control unit 52 includes an eighth transistor (e.g., M8, T8) and a second capacitor C2; the gate of the eighth transistor is coupled to the control signal input terminal HF, the first terminal of the eighth transistor is coupled to the first level signal input terminal P1, and the second terminal of the eighth transistor is coupled to the target output terminal Gout; the first plate of the second capacitor C2 is coupled to the first level signal input terminal P1, and the second plate of the second capacitor C2 is coupled to the target output terminal Gout; the second capacitor C2 has a storage function.

[0196] The fifth control unit 51 includes a ninth transistor (e.g., M9, T9), the gate of the ninth transistor is coupled to the first terminal of the fourth transistor, the first terminal of the ninth transistor is coupled to the second level signal input terminal P2, and the second terminal of the ninth transistor is coupled to the target output terminal Gout.

[0197] As shown in Figure 8, the signal generation circuit is implemented using an N-type transistor. The timing diagrams for each signal are shown in Figure 9. In this case, the first level signal input terminal P1 receives the VDD signal, and the second level signal input terminal P2 receives the VSS signal. The analog signal level changes from -10V to -20V within one cycle. The adjustable data signal's data voltage value within each cycle can be adjusted to any value as needed. The specific operation of the signal generation circuit will be explained in detail below using data voltage signal values ​​of -21V, -17V, -14V, -12V, and -10.5V as examples.

[0198] As shown in Figures 8 and 9, an eighth transistor M8 and a ninth transistor M9, along with a second capacitor C2, are added. At the start of the cycle, the control signal input terminal HF1 turns on the first transistor M1 and the eighth transistor M8. The VDD signal is written to the output control node G1 and the target output terminal GNout4. The target output terminal GNout4 outputs the VDD signal. The output control node G1 turns on the fourth transistor M4. The first terminal of the fourth transistor (corresponding to node G2-2) outputs a low-voltage signal to turn off the ninth transistor M9. The target signal output by the target output terminal GNout4 remains the VDD signal. When the output control node G1 outputs an analog signal, the fourth transistor M4 is turned off. The G2-2 node outputs a high-voltage signal to turn on the ninth transistor M9. The VSS signal is written to the target output terminal GNout4, and the target output terminal GNout4 outputs the VSS signal. This method completely solves the problem of insufficient low-voltage output at the target output terminal and further reduces Tf.

[0199] It is worth noting that in the embodiment shown in Figure 8, after the control signal is input to the control signal input terminal HF1, the output control node G1 is under high voltage and the fourth transistor M4 is turned on. The VDD signal and the VSS signal are turned on through the third transistor M3 and the fourth transistor M4. By adjusting parameters such as the width-to-length ratio of the transistors, the resistance of the third transistor M3 is made to be greater than that of the fourth transistor M4. According to the voltage division principle of series circuits, the voltage of node G2-2 is low. When the resistance of the third transistor M3 relative to the fourth transistor M4 is greater, or the VSS signal voltage connected to the fourth transistor M4 is lower, the voltage of node G2-2 is lower. Therefore, the potential of the VSS signal received by the fourth transistor M4 can be set to -14V to ensure that the voltage of node G2-2 is less than or equal to the -10V VSS signal connected to other transistors, thereby ensuring that the ninth transistor M9 is turned off and ensuring that the target output terminal GNout4 outputs a high voltage signal.

[0200] As shown in Figure 13, the signal generation circuit is implemented using a P-type transistor. The timing diagrams for each signal are shown in Figure 14. In this case, the first level signal input terminal P1 receives the VSS signal, and the second level signal input terminal P2 receives the VDD signal. The analog signal level changes from 10V to 20V within one cycle. The adjustable data signal's data voltage value within each cycle can be adjusted to any value as needed. The specific operation of the signal generation circuit will be explained in detail below using data voltage signal values ​​of 21V, 17V, 14V, 12V, and 10.5V as examples.

[0201] As shown in Figures 13 and 14, an eighth transistor T8 and a ninth transistor T9, along with a second capacitor C2, are added. At the start of the cycle, the control signal input terminal HF2 turns on the first transistor T1 and the eighth transistor T8. The VSS signal is written to the output control node G1 and the target output terminal GPout4. The target output terminal GPout4 outputs the VSS signal, and the output control node G1 turns on the fourth transistor T4. The first terminal of the fourth transistor T4 (corresponding to node G2-2) outputs a high-voltage signal to turn off the ninth transistor T9. The target signal output by the target output terminal GPout4 maintains the VSS signal. When the output control node G1 outputs an analog signal, the fourth transistor T4 is turned off, the G2-2 node outputs a high-voltage signal to turn on the ninth transistor T9, and VDD is written to the target output terminal GPout4. The target output terminal GPout4 outputs the VDD signal. This method completely solves the problem of insufficient high voltage output at the target output terminal and further reduces Tr.

[0202] It is worth noting that in the embodiment shown in Figure 13, after the control signal is input to the control signal input terminal HF2, the output control node G1 is in a low-voltage state and the fourth transistor T4 is turned on. The VDD signal and the VSS signal are turned on through the third transistor T3 and the fourth transistor T4. By adjusting parameters such as the width-to-length ratio of the transistors, the resistance of the third transistor T3 is made to be greater than that of the fourth transistor T4. According to the voltage division principle of series circuits, the voltage of node G2-2 is high. When the resistance of the third transistor T3 relative to the fourth transistor T4 is greater or the VDD signal voltage connected to the fourth transistor T4 is higher, the voltage of node G2-2 is higher. Therefore, the potential of the VDD signal received by the fourth transistor T4 can be set to 14V to ensure that the voltage of node G2-2 is greater than or equal to the 10V VDD signal connected to other transistors, thereby ensuring that the ninth transistor T9 is turned off and ensuring that the target output terminal GNout4 outputs a low-voltage signal.

[0203] As shown in Figure 15, in some embodiments, the output control sub-circuit 3 is used to control the electrical connection between the second level signal input terminal P2 and the target output terminal Gout under the control of the output control node G1; it is also used to control the electrical connection between the first level signal input terminal P1 and the target output terminal Gout under the control of the output control node G1.

[0204] During the first level output phase, the output control sub-circuit 3 is used, under the control of the output control node G1, to control the electrical connection between the second level signal input terminal P2 and the target output terminal Gout to be turned on; and is also used, under the control of the output control node G1, to control the electrical connection between the first level signal input terminal P1 and the target output terminal Gout to be turned off. During the second level output phase, the output control sub-circuit 3 is used, under the control of the output control node G1, to control the electrical connection between the second level signal input terminal P2 and the target output terminal Gout to be turned off; and is also used, under the control of the output control node G1, to control the electrical connection between the first level signal input terminal P1 and the target output terminal Gout to be turned on.

[0205] As shown in Figure 15, exemplarily, the output control sub-circuit 3 includes a seventh control unit 33 and an eighth control unit 34; the seventh control unit 33 is coupled to the output control node G1, the second level signal input terminal P2, and the target output terminal Gout, respectively, and is used to control the electrical connection between the second level signal input terminal P2 and the target output terminal Gout to be turned on or off under the control of the output control node G1; the eighth control unit 34 is coupled to the output control node G1, the first level signal input terminal P1, and the target output terminal Gout, respectively, and is used to control the electrical connection between the first level signal input terminal P1 and the target output terminal Gout to be turned on or off under the control of the output control node G1.

[0206] During the first level output phase, the seventh control unit 33 is used to control the electrical connection between the second level signal input terminal P2 and the target output terminal Gout under the control of the output control node G1; the eighth control unit 34 is used to control the electrical connection between the first level signal input terminal P1 and the target output terminal Gout under the control of the output control node G1.

[0207] During the second level output phase, the seventh control unit 33 is used to control the disconnection of the electrical connection between the second level signal input terminal P2 and the target output terminal Gout under the control of the output control node G1; the eighth control unit 34 is used to control the connection of the electrical connection between the first level signal input terminal P1 and the target output terminal Gout under the control of the output control node G1.

[0208] The above configuration allows the output control sub-circuit 3 to control the target output terminal Gout to receive the second-level signal output from the second-level signal input terminal P2 under the control of the output control node G1, or to control the target output terminal Gout to receive the second-level signal output from the second-level signal input terminal P2 under the control of the output control node G1. Therefore, when the potential of the output control node G1 reaches a certain threshold, the target signal output by the target output terminal Gout can be controlled to be a first-level signal or a second-level signal, without being affected by the gradual change of the analog signal, thereby improving the problem of a large Tf (fall time) or Tr (rise time) of the target signal. Moreover, by controlling the target signal output by the target output terminal Gout to be a first-level signal or a second-level signal through the output control node G1, the high-voltage or low-voltage part of the target signal is avoided from being a gradually changing analog signal, making the high-voltage or low-voltage part of the target signal a stable DC signal with good stability.

[0209] As shown in Figure 16, in some embodiments, the signal generation circuit further includes a third output compensation sub-circuit 6, which is coupled to the target output terminal Gout, the second level signal input terminal P2 and the output control node G1 respectively, and is used to control the electrical connection between the second level signal input terminal P2 and the output control node G1 to be turned on or off under the control of the target output terminal Gout.

[0210] During the first level output phase, the third output compensation sub-circuit 6, under the control of the target output terminal Gout, controls to disconnect the electrical connection between the second level signal input terminal P2 and the output control node G1; during the second level output phase, the third output compensation sub-circuit 6, under the control of the target output terminal Gout, controls to connect the electrical connection between the second level signal input terminal P2 and the output control node G1.

[0211] When the above signal generation circuit is working, in the first level output stage, the seventh control unit 33 is turned on and the eighth control unit 34 is turned off. The target signal output by the target output terminal Gout is the second level signal, which controls the third output compensation sub-circuit 6 to be turned off.

[0212] During the second level output stage, the second control sub-circuit 2 is turned on, writing the analog signal into the output control node G1, thereby controlling the seventh control unit 33 to gradually turn off and the eighth control unit 34 to gradually turn on, so that the target signal gradually becomes the first level signal. The first level signal controls the third output compensation sub-circuit 6 to turn on, quickly transmitting the second level signal to the output control node G1. Thus, under the control of the output control node G1, the output control sub-circuit 3 can quickly disconnect the electrical connection between the second level signal input terminal P2 and the target output terminal Gout, and quickly turn on the electrical connection between the first level signal input terminal P1 and the target output terminal Gout, so that the target signal output by the target output terminal Gout quickly reaches the first level signal. Because during the second-level output phase, the first-level signal continuously controls the third output compensation sub-circuit 6 to conduct in order to assist the output control node G1 in discharging (i.e., the node potential discharges to the second-level signal), the introduction of the third output compensation sub-circuit 6 can quickly change the potential of the output control node G1 to the second level. This solves the problem of excessively large Tf (fall time) or Tr (rise time) Tr of the output control node G1 signal due to the slow change of the analog signal. Furthermore, it better ensures the stability of the target signal.

[0213] As shown in Figures 17 to 22, in some embodiments, the first control sub-circuit 1 includes a first transistor (e.g., M1, T1), the gate of the first transistor is coupled to the control signal input terminal HF, the first terminal of the first transistor is coupled to the first level signal input terminal P1, and the second terminal of the first transistor is coupled to the output control node G1.

[0214] The second control sub-circuit 2 includes a second transistor (e.g., M2, T2), the gate of the second transistor is coupled to the adjustable data signal input terminal DG, the first terminal of the second transistor is coupled to the analog signal input terminal SA, and the second terminal of the second transistor is coupled to the output control node G1;

[0215] The seventh control unit 33 includes a tenth transistor (e.g., M10, T10), the gate of the tenth transistor is coupled to the output control node G1, the first terminal of the tenth transistor is coupled to the second level signal input terminal P2, and the second terminal of the tenth transistor is coupled to the target output terminal Gout.

[0216] The eighth control unit 34 includes an eleventh transistor (e.g., M11, T11), the gate of the eleventh transistor is coupled to the output control node G1, the first terminal of the eleventh transistor is coupled to the first level signal input terminal P1, and the second terminal of the eleventh transistor is coupled to the target output terminal Gout; one of the eleventh transistor and the tenth transistor is a P-type transistor and the other is an N-type transistor.

[0217] As shown in Figures 17 to 22, in some embodiments, the third output compensation sub-circuit 6 includes a twelfth transistor (e.g., M12, T12), the gate of the twelfth transistor is coupled to the target output terminal Gout, the first terminal of the twelfth transistor is coupled to the second level signal input terminal P2, and the second terminal of the twelfth transistor is coupled to the output control node G1.

[0218] As shown in Figures 17 and 18, the first transistor M1, the second transistor M2, the tenth transistor M10, and the twelfth transistor M12 are implemented using N-type transistors. The timing diagrams for the corresponding signals are shown in Figure 19. In this case, the first level signal input terminal P1 receives the VDD signal, and the second level signal input terminal P2 receives the VSS signal. The analog signal level changes from -10V to -20V within one cycle. The adjustable data signal's data voltage value within each cycle can be adjusted to any value as needed. The following detailed explanation of the signal generation circuit's operation is based on data voltage signal values ​​of -21V, -17V, -14V, -12V, and -10.5V.

[0219] As shown in Figures 5 and 19, the control signal input at the control signal input terminal HF1 turns on the first transistor M1 at the beginning of each cycle, resetting the target signal output at the target output terminal GNout1 to the VDD signal. The gate-source voltage Vgs of the second transistor M2 is equal to the difference between the data voltage value of the adjustable data signal input at the adjustable data signal input terminal DG1 and the voltage value of the analog signal input at the analog signal input terminal SA1. When Vgs < Vth, Vth is the threshold voltage of the second transistor M2, the second transistor M2 is turned off, and the target signal output at the target output terminal GNout1 remains at a high voltage. When Vgs > Vth, the second transistor M2 is turned on, the analog signal is transmitted to the target output terminal GNout1, and the potential of the target signal becomes low voltage. The case of Vgs < Vth corresponds to the first level output stage, and the case of Vgs > Vth corresponds to the second level output stage.

[0220] As shown in Figure 19, when the data voltage is -21V, Vgs = -11V to -1V < Vth, the second transistor M2 is always off, the target signal output by the target output terminal GNout1 is continuously at high voltage, and the duty cycle of the target signal is 100%. When the data voltage is -14V, Vgs = -4V to 6V, in the -4V to Vth stage, the second transistor M2 is off, the target signal output by the target output terminal GNout1 is at high voltage, in the Vth to 6V stage, the second transistor M2 is on, the analog signal is written, the target signal becomes low voltage, and the duty cycle of the target signal is 55%.

[0221] Since the analog signal input at the analog signal input terminal SA1 is gradually changing, the rising speed of Vgs of the second transistor M2 is consistent with the falling speed of the analog signal. This causes the second transistor M2 to turn on slowly, and the analog signal is transmitted to the target output terminal GNout1 slowly, resulting in a large Tf of the target signal. At the same time, the low voltage part of the target signal is a gradually changing analog signal, which is not a stable DC signal and has poor stability.

[0222] Further, as shown in Figures 17 and 19, a tenth N-type transistor M10 and an eleventh P-type transistor T11 are added. After the cycle begins, the VDD signal is written through the first transistor M1, the output control node G1 outputs high voltage, turns on the tenth transistor M10, and turns off the eleventh transistor T11. The VSS signal is written through the tenth transistor M10, and the target output terminal GNout5 outputs the VSS signal. When Vgs > Vth, the second transistor M2 turns on, the voltage of the output control node G1 slowly decreases to the voltage of the analog signal, the tenth transistor M10 gradually turns off, and the eleventh transistor T11 gradually turns on. When the voltage of the output control node G1 drops to approximately -10V (without waiting for the voltage of the output control node G1 to continue to decrease), the tenth transistor M10 can be completely turned off, the VDD signal is written through the eleventh transistor T11, and the target output terminal GNout5 outputs the VDD signal. Compared with the Tf of the signal of the output control node G1, the Tr of the target signal is significantly reduced. Simultaneously, the voltage drop of the output control node G1 is written to the gate of the eleventh transistor T11. The voltage drop of the output control node G1 will not affect the output of the target output terminal GNout5, thus solving the problem of unstable output target signal.

[0223] Furthermore, as shown in Figures 18 and 19, a twelfth N-type transistor M12 is added. After the cycle begins, the high voltage at the output control node G1 turns on the tenth transistor M10 and turns off the eleventh transistor T11. The target output terminal GNout6 outputs a low voltage, turning off the twelfth transistor M12. When the second transistor M2 is turned on and the analog signal is written to the output control node G1, the tenth transistor M10 gradually turns off, and the eleventh transistor T11 gradually turns on, causing the output voltage at the target output terminal GNout6 to gradually increase. Then, the twelfth transistor M12 gradually turns on. After the twelfth transistor M12 turns on, the VSS signal is written to the output control node G1, quickly reducing the voltage of the output control node G1 to the VSS signal level. This turns off the tenth transistor M10 and turns on the eleventh transistor T11, causing the VDD signal to be written to the target output terminal GNout6. The target output terminal GNout6 outputs a high voltage, and the twelfth transistor M12 remains on to assist the output control node G1 in discharging. The introduction of the twelfth transistor M12 quickly lowers the voltage of the output control node G1, resolving the issues of a large Tf value in the output control node G1 signal due to the slow decrease of the analog signal, and an excessively large Tr value in the target signal output at the target output terminal GNout6. Simultaneously, it ensures that both the high and low voltage values ​​of the target signal output at the target output terminal GNout6 are stable, and that the Tr and Tf values ​​of the signal are relatively small.

[0224] As shown in Figures 20 and 21, the first transistor T1, the second transistor T2, the eleventh transistor T11, and the twelfth transistor T12 are implemented using P-type transistors. The timing diagrams for the corresponding signals are shown in Figure 22. In this case, the first level signal input terminal P1 receives the VSS signal, and the second level signal input terminal P2 receives the VDD signal. The analog signal level changes from 10V to 20V within one cycle. The adjustable data signal's data voltage value within each cycle can be adjusted to any value as needed. The following detailed explanation of the signal generation circuit's operation is based on data voltage signal values ​​of 21V, 17V, 14V, 12V, and 10.5V.

[0225] As shown in Figures 10 and 22, the control signal input at the control signal input terminal HF2 turns on the first transistor T1 at the beginning of each cycle, resetting the target signal output at the target output terminal GPout1 to the VSS signal. The gate-source voltage Vgs of the second transistor T2 is equal to the difference between the data voltage value of the adjustable data signal input at the adjustable data signal input terminal DG2 and the voltage value of the analog signal input at the analog signal input terminal SA2. When Vgs > Vth, Vth is the threshold voltage of the second transistor T2, the second transistor T2 is turned off, and the target signal output at the target output terminal GPout1 remains at a low voltage. When Vgs < Vth, the second transistor T2 is turned on, the analog signal is transmitted to the target output terminal GPout1, and the potential of the target signal becomes high voltage. The case of Vgs > Vth corresponds to the first level output stage, and the case of Vgs < Vth corresponds to the second level output stage.

[0226] As shown in Figure 22, when the data voltage is 21V, Vgs = 11V ~ 1V > Vth, the second transistor T2 is turned off during the cycle, and the target signal output by the target output terminal GPout1 remains at a low voltage with a duty cycle of 100%. When the data voltage is 14V, Vgs = 4V ~ -6V. In the 4V ~ Vth stage, the second transistor T2 is turned off, and the target signal output by the target output terminal GPout1 is at a low potential. In the Vth ~ -6V stage, the second transistor T2 is turned on, and the analog signal is transmitted to the target output terminal GPout1. The potential of the target signal becomes high voltage, and the duty cycle of the target signal is 55%.

[0227] Although the above embodiment achieves a target signal with adjustable duty cycle, the analog signal input at the analog signal input terminal SA2 is gradually changing. The rate at which Vgs of the second transistor T2 decreases is consistent with the rate at which the analog signal rises. This causes the second transistor T2 to turn on slowly, and the analog signal is transmitted to the target output terminal GPout1 slowly, resulting in a large Tr of the target signal. At the same time, the high voltage part of the target signal is a gradually changing analog signal, which is not a stable DC signal and has poor stability.

[0228] Further, as shown in Figures 20 and 22, a tenth N-type transistor M10 and an eleventh P-type transistor T11 are added. After the cycle begins, the VSS signal is written through the first transistor T1, the output control node G1 outputs a low voltage, the tenth transistor M10 is turned off, and the eleventh transistor T11 is turned on. The VDD signal is written through the eleventh transistor T11, and the target signal output terminal GPout5 outputs the VDD signal. When Vgs < Vth, the second transistor T2 turns on, the output control node G1 slowly rises to an analog signal, the tenth transistor M10 gradually turns on, and the eleventh transistor T11 gradually turns off. When the output control node G1 rises to about 10V (without waiting for the voltage of the output control node G1 to continue to rise), the eleventh transistor T11 can be completely turned off, the VSS signal is written through the tenth transistor M10, and the target signal output terminal GPout5 outputs the VSS signal. Compared with the Tr of the signal at the output control node G1, the Tf of the target signal output at the target signal output terminal GPout5 is significantly reduced. Meanwhile, since the output control node G1 writes to the gate of the eleventh transistor T11, the voltage rise of the output control node G1 will not affect the output of the target signal output terminal GPout5, thus solving the problem of unstable output target signal.

[0229] Furthermore, as shown in Figures 21 and 22, a P-type twelfth transistor T12 is added. After the cycle starts, the output control node G1 outputs a low voltage to turn on the eleventh transistor T11 and turn off the tenth transistor M10. The standard signal output terminal GPout6 outputs a VDD signal to turn off the twelfth transistor T12. When the second transistor T2 is turned on and the analog signal is written to the output control node G1, the tenth transistor M10 gradually turns on, and the eleventh transistor T11 gradually turns off. The output voltage of the target signal output terminal GPout6 gradually decreases, and the twelfth transistor T12 gradually turns on. After the twelfth transistor T12 turns on, the VDD signal is written to the output control node G1, quickly raising the voltage of the output control node G1 to the same level as the VDD signal. The tenth transistor M10 turns on, and the eleventh transistor T11 turns off. The VSS signal is written to the target signal output terminal GPout6, and the target signal output terminal GPout6 outputs the VSS signal. The twelfth transistor T12 remains on to assist in charging the output control node G1. The introduction of the twelfth transistor T12 can quickly raise the voltage of the output control node G1, solving the problem of the signal Tr of the output control node G1 being too large due to the slow rise of the analog signal, and the problem of the Tf of the target signal output at the target signal output terminal GPout6 being too large. The high voltage and low voltage of the target signal output at the target signal output terminal GPout6 are stable, and the Tr and Tf of the target signal are both small.

[0230] The signal generation circuit provided in the above embodiments can generate low-voltage adjustable timing signals and high-voltage adjustable timing signals, and improves the high-voltage and low-voltage stability of the signals, as well as the Tr and Tf values ​​of the signals, to ensure that the output signal quality meets the requirements of the display field.

[0231] As shown in Figures 5 and 10, in some embodiments, the first control sub-circuit 1 includes a first transistor (e.g., M1, T1), the gate of the first transistor is coupled to the control signal input terminal HF, the first terminal of the first transistor is coupled to the first level signal input terminal P1, and the second terminal of the first transistor is coupled to the output control node G1.

[0232] The second control sub-circuit 2 includes a second transistor (e.g., M2, T2), the gate of the second transistor is coupled to the adjustable data signal input terminal DG, the first terminal of the second transistor is coupled to the analog signal input terminal SA, and the second terminal of the second transistor is coupled to the output control node G1;

[0233] As shown in Figures 6 and 11, in some embodiments, the gate of the first transistor is coupled to the control signal input terminal HF, the first terminal of the first transistor is coupled to the first level signal input terminal P1, and the second terminal of the first transistor is coupled to the output control node G1.

[0234] The second control sub-circuit 2 includes a second transistor (e.g., M2, T2), the gate of the second transistor is coupled to the adjustable data signal input terminal DG, the first terminal of the second transistor is coupled to the analog signal input terminal SA, and the second terminal of the second transistor is coupled to the output control node G1.

[0235] The second control unit 32 includes a third transistor (e.g., M3, T3), the gate of the third transistor and the second terminal of the third transistor are both coupled to the first level signal input terminal P1;

[0236] The first control unit 31 includes a fourth transistor (e.g., M4, T4), the gate of the fourth transistor is coupled to the output control node G1, the first terminal of the fourth transistor is coupled to the first terminal of the third transistor, and the second terminal of the fourth transistor is coupled to the second level signal input terminal P2.

[0237] As shown in Figure 1, in some embodiments, the signal generation circuit further includes a capacitor structure C1 with a storage function, the first end of the capacitor structure C1 being coupled to the output control node G1, and the second end of the capacitor structure C1 being coupled to the first level signal input terminal P1.

[0238] This disclosure also provides a display device, including the signal generation circuit provided in the above embodiments.

[0239] For example, the display device may include a liquid crystal display device, an organic light-emitting diode display device, a diode display device, etc. When the signal generation circuit is applied to these display devices, it can adjust the brightness and frequency of the display device, and can also be used to provide timing signals for the GOA and EOA of the display device.

[0240] It should be noted that the display device can be any product or component with display function, such as a television, monitor, digital photo frame, mobile phone, or tablet computer. The display device also includes flexible circuit boards, printed circuit boards, and backplanes.

[0241] In the signal generation circuit provided in the above embodiment, by changing the data voltage value of the adjustable data signal input at the adjustable data signal input terminal DG, and setting the level value of the analog signal input at the analog signal input terminal SA to change linearly in each output stage, the output control node G1 can be controlled for the time it is at the first potential and the time it is at the second potential, thereby controlling the time the target signal output at the target output terminal Gout is at the effective level and the time it is at the ineffective level, thus realizing the adjustment of the duty cycle of the target signal.

[0242] Furthermore, in the signal generation circuit provided in the above embodiments, the control signal input at the control signal input terminal HF can control whether the first control sub-circuit 1 is turned on, and the adjustable data signal input at the adjustable data signal input terminal DG and the analog signal input at the analog signal input terminal SA can control whether the second control sub-circuit 2 is turned on. Therefore, the frequency of the output target signal with periodicity is jointly determined by the control signal input terminal HF, the adjustable data signal input terminal DG, and the analog signal input terminal SA.

[0243] In the signal generation circuit provided in the above embodiments, the frequency and duty cycle of the target signal output from the target output terminal Gout can be adjusted in real time simply by adjusting the control signal, the adjustable data signal, and the analog signal. Therefore, the signal generation circuit provided in the above embodiments can adjust the frequency and duty cycle of the target signal without occupying too many driver chip channels. Thus, when the signal generation circuit provided in this disclosure is applied to display products, it is more conducive to achieving high-resolution layout of the display product and real-time adjustment of the display brightness and frequency.

[0244] Therefore, the display device provided in this disclosure, when including the signal generation circuit provided in the above embodiments, also has the above-mentioned beneficial effects, which will not be repeated here.

[0245] This disclosure also provides a driving method for a signal generation circuit, used to drive the signal generation circuit provided in the above embodiments; the driving method includes a periodic output stage, the output stage including a first level output stage and a second level output stage; an analog signal with periodicity is input at the analog signal input terminal SA; in one of the output stages, the level value of the analog signal changes linearly;

[0246] During the first level output stage, the second control sub-circuit 2, under the joint control of the adjustable data signal input terminal DG and the analog signal input terminal SA, controls the disconnection of the electrical connection between the analog signal input terminal SA and the output control node G1.

[0247] During the initial phase of the first level output stage, the first control sub-circuit 1, under the control of the control signal input terminal HF, controls the electrical connection between the first level signal input terminal P1 and the output control node G1 to be turned on; during the non-initial phase of the first level output stage, the first control sub-circuit 1, under the control of the control signal input terminal HF, controls the electrical connection between the first level signal input terminal P1 and the output control node G1 to be turned off.

[0248] During the second level output phase:

[0249] The first control sub-circuit 1, under the control of the control signal input terminal HF, controls the disconnection of the electrical connection between the first level signal input terminal P1 and the output control node G1;

[0250] The second control sub-circuit 2, under the joint control of the adjustable data signal input terminal DG and the analog signal input terminal SA, controls the electrical connection between the analog signal input terminal SA and the output control node G1.

[0251] When driving the signal generation circuit using the driving method provided in this embodiment, by changing the data voltage value of the adjustable data signal input at the adjustable data signal input terminal DG and setting the level value of the analog signal input at the analog signal input terminal SA to change linearly in each output stage, the time when the output control node G1 is at the first potential and the time when it is at the second potential can be controlled, thereby controlling the time when the target signal output at the target output terminal Gout is at the effective level and the time when it is at the ineffective level, thus realizing the adjustment of the duty cycle of the target signal.

[0252] Furthermore, when the driving method provided in this embodiment is used to drive the signal generation circuit, the control signal input at the control signal input terminal HF can control whether the first control sub-circuit 1 is turned on, and the adjustable data signal input at the adjustable data signal input terminal DG and the analog signal input at the analog signal input terminal SA can control whether the second control sub-circuit 2 is turned on. Therefore, the frequency of the output target signal with periodicity is jointly determined by the control signal input terminal HF, the adjustable data signal input terminal DG, and the analog signal input terminal SA.

[0253] Therefore, when driving the signal generation circuit using the driving method provided in this embodiment, the frequency and duty cycle of the target signal output from the target output terminal Gout can be adjusted in real time simply by adjusting the control signal, the adjustable data signal, and the analog signal. Thus, when driving the signal generation circuit using the driving method provided in this embodiment, the frequency and duty cycle of the target signal can be adjusted without occupying too many driver chip channels. This makes it more advantageous to apply the signal generation circuit provided in this embodiment to display products, enabling high-resolution layouts and real-time adjustments to display brightness and frequency.

[0254] In some embodiments, the signal generation circuit further includes: an output control sub-circuit 3, wherein the output control node G1 is coupled to the target output terminal Gout through the output control sub-circuit 3, and the output control sub-circuit 3 is also coupled to the first level signal input terminal P1 and the second level signal input terminal P2 respectively. The driving method further includes:

[0255] During the first level output stage, the output control sub-circuit 3, under the control of the output control node G1, controls the target output terminal Gout to receive the second level signal output from the second level signal input terminal;

[0256] During the second level output stage, the output control sub-circuit 3, under the control of the output control node G1, controls the target output terminal Gout to receive the first level signal output from the first level signal input terminal.

[0257] In some embodiments, during the first level output stage, the output control sub-circuit 3, under the control of the first level signal input terminal P1, controls the electrical connection between the first level signal input terminal P1 and the target output terminal Gout; the output control sub-circuit 3, under the control of the output control node G1, controls the electrical connection between the second level signal input terminal P2 and the target output terminal Gout.

[0258] During the second level output stage, under the control of the first level signal input terminal P1, the output control sub-circuit 3 controls the electrical connection between the first level signal input terminal P1 and the target output terminal Gout to be turned on; under the control of the output control node G1, the output control sub-circuit 3 controls the electrical connection between the second level signal input terminal P2 and the target output terminal Gout to be turned off.

[0259] In some embodiments, the output control sub-circuit 3 includes: a first control unit 31 and a second control unit 32; a first terminal of the first control unit 31 is coupled to the output control node G1, a second terminal of the first control unit 31 is coupled to the second level signal input terminal P2, and a third terminal of the first control unit 31 is coupled to the target output terminal; a first terminal of the second control unit 32 is coupled to the first level signal input terminal P1, a second terminal of the second control unit 32 is coupled to the first level signal input terminal P1, and a third terminal of the second control unit 32 is coupled to the target output terminal;

[0260] During the first level output phase, the first control unit 31, under the control of the output control node G1, controls the electrical connection between the second level signal input terminal and the target output terminal; the second control unit 32, under the control of the first level signal input terminal P1, controls the electrical connection between the first level signal input terminal P1 and the third terminal of the second control unit 32.

[0261] During the second level output phase, the first control unit 31, under the control of the output control node G1, controls to disconnect the electrical connection between the second level signal input terminal and the target output terminal; the second control unit 32, under the control of the first level signal input terminal P1, controls to connect the electrical connection between the first level signal input terminal P1 and the target output terminal Gout.

[0262] In some embodiments, the signal generation circuit further includes: a first output compensation sub-circuit 4, wherein the third terminal of the first control unit 31 and the third terminal of the second control unit 32 are coupled together, and are coupled to the target output terminal through the first output compensation sub-circuit 4; the first output compensation sub-circuit 4 is also coupled to the first level signal input terminal P1, the second level signal input terminal P2 and the output control node G1 respectively; the driving method further includes:

[0263] During the first level output stage, the first output compensation sub-circuit 4, under the control of the output control node G1, controls the electrical connection between the second level signal input terminal P2 and the target output terminal Gout to be turned on; the first output compensation sub-circuit 4, under the control of the third terminal of the first control unit 31, also controls the electrical connection between the first level signal input terminal P1 and the target output terminal Gout to be turned off.

[0264] During the second level output stage, the first output compensation sub-circuit 4, under the control of the output control node G1, controls to disconnect the electrical connection between the second level signal input terminal P2 and the target output terminal Gout; the first output compensation sub-circuit 4, under the control of the third terminal of the first control unit 31, also controls to connect the electrical connection between the first level signal input terminal P1 and the target output terminal Gout.

[0265] In some embodiments, the signal generation circuit further includes: a second output compensation sub-circuit 5, wherein the third terminal of the first control unit 31 and the third terminal of the second control unit 32 are coupled together, and are coupled to the target output terminal through the second output compensation sub-circuit 5; the second output compensation sub-circuit 5 is also coupled to the control signal input terminal HF, the first level signal input terminal P1, and the second level signal input terminal P2 respectively; the driving method further includes:

[0266] During the first level output stage, the second output compensation sub-circuit 5, under the control of the third terminal of the first control unit 31, controls to disconnect the electrical connection between the second level signal input terminal P2 and the target output terminal Gout; the second output compensation sub-circuit 5, under the control of the control signal input terminal HF, also controls to connect the electrical connection between the first level signal input terminal P1 and the target output terminal Gout.

[0267] During the second level output stage, the second output compensation sub-circuit 5, under the control of the third terminal of the first control unit 31, controls the electrical connection between the second level signal input terminal P2 and the target output terminal Gout to be turned on; the second output compensation sub-circuit 5, under the control of the control signal input terminal HF, also controls the electrical connection between the first level signal input terminal P1 and the target output terminal Gout to be turned off.

[0268] In some embodiments, during the first level output stage, the output control sub-circuit 3 is used to control the electrical connection between the second level signal input terminal P2 and the target output terminal Gout to be turned on under the control of the output control node G1; and is also used to control the electrical connection between the first level signal input terminal P1 and the target output terminal Gout to be turned off under the control of the output control node G1.

[0269] During the second level output stage, the output control sub-circuit 3 is used to control the disconnection of the electrical connection between the second level signal input terminal P2 and the target output terminal Gout under the control of the output control node G1; it is also used to control the connection of the electrical connection between the first level signal input terminal P1 and the target output terminal Gout under the control of the output control node G1.

[0270] In some embodiments, the signal generation circuit further includes: a third output compensation sub-circuit 6, coupled to the target output terminal Gout, the second level signal input terminal P2, and the output control node G1 respectively; the driving method further includes:

[0271] During the first level output stage, the third output compensation sub-circuit 6, under the control of the target output terminal Gout, controls the disconnection of the electrical connection between the second level signal input terminal P2 and the output control node G1.

[0272] During the second level output phase, the third output compensation sub-circuit 6, under the control of the target output terminal Gout, controls the electrical connection between the second level signal input terminal P2 and the output control node G1 to be turned on.

[0273] It is worth noting that the beneficial effects of the above-mentioned driving method can be found in the description of the corresponding structural part of the signal generation circuit, and will not be repeated here.

[0274] It should be noted that, in the embodiments of this disclosure, "same layer" can refer to film layers located on the same structural layer. Alternatively, for example, film layers located on the same layer can be layer structures formed by using the same film deposition process to form a specific pattern, and then patterning the film layer using the same photomask through a single patterning process. Depending on the specific pattern, the single patterning process may include multiple exposure, development, or etching processes, and the specific pattern in the formed layer structure can be continuous or discontinuous. These specific patterns may also be at different heights or have different thicknesses.

[0275] In the various method embodiments of this disclosure, the sequence numbers of each step are not intended to limit the order of the steps. For those skilled in the art, any changes in the order of the steps are within the scope of protection of this disclosure without any creative effort.

[0276] It should be noted that the various embodiments in this specification are described in a progressive manner, and the same or similar parts between the various embodiments can be referred to mutually. Each embodiment focuses on describing the differences from other embodiments. In particular, the method embodiments are basically similar to the product embodiments, so the description is relatively simple, and the relevant parts can be referred to the description of the product embodiments.

[0277] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as “comprising” or “including” mean that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. Terms such as “connection,” “coupled,” or “linked” are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. Terms such as “upper,” “lower,” “left,” and “right” are used only to indicate relative positional relationships, and these relative positional relationships may change accordingly when the absolute position of the described objects changes.

[0278] It is understandable that when a component such as a layer, film, region, or substrate is referred to as being "above" or "below" another component, the component may be "directly" located "above" or "below" the other component, or there may be intermediate components present.

[0279] In the description of the above embodiments, specific features, structures, materials, or characteristics may be combined in any suitable manner in one or more embodiments or examples.

[0280] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. A signal generation circuit, comprising: First control sub-circuit, second control sub-circuit, output control node and target output terminal; The output control node is coupled to the target output terminal; The first control sub-circuit is coupled to the control signal input terminal, the first level signal input terminal, and the output control node, respectively; it is used to control the electrical connection between the first level signal input terminal and the output control node to be turned on or off under the control of the control signal input terminal. The second control sub-circuit is coupled to the adjustable data signal input terminal, the analog signal input terminal, and the output control node, respectively; it is used to control the electrical connection between the analog signal input terminal and the output control node to be turned on or off under the joint control of the adjustable data signal input terminal and the analog signal input terminal.

2. The signal generation circuit of claim 1, wherein, The signal generation circuit further includes: An output control sub-circuit is provided, wherein the output control node is coupled to the target output terminal through the output control sub-circuit, and the output control sub-circuit is also coupled to the first level signal input terminal and the second level signal input terminal respectively. The output control sub-circuit is used to control the target output terminal to receive the first level signal output from the first level signal input terminal, or to control the target output terminal to receive the second level signal output from the second level signal input terminal, under the control of the output control node.

3. The signal generation circuit of claim 2, wherein, The output control sub-circuit is used to control the electrical connection between the second level signal input terminal and the target output terminal to be turned on or off under the control of the output control node. It is also used to control the electrical connection between the first level signal input terminal and the target output terminal under the control of the first level signal input terminal.

4. The signal generation circuit of claim 3, wherein, The output control sub-circuit includes: a first control unit and a second control unit; The first terminal of the first control unit is coupled to the output control node, the second terminal of the first control unit is coupled to the second level signal input terminal, and the third terminal of the first control unit is coupled to the target output terminal; the first control unit is used to control the electrical connection between the second level signal input terminal and the target output terminal to be turned on or off under the control of the output control node; The first terminal of the second control unit is coupled to the first level signal input terminal, the second terminal of the second control unit is coupled to the first level signal input terminal, and the third terminal of the second control unit is coupled to the target output terminal; the second control unit is used to control the conduction of the electrical connection between the first level signal input terminal and the target output terminal under the control of the first level signal input terminal.

5. The signal generation circuit of claim 4, wherein, The signal generation circuit further includes: a first output compensation sub-circuit, wherein the third terminal of the first control unit and the third terminal of the second control unit are coupled together, and are coupled to the target output terminal through the first output compensation sub-circuit; the first output compensation sub-circuit is also coupled to the first level signal input terminal, the second level signal input terminal and the output control node respectively; The first output compensation sub-circuit is used to: control the electrical connection between the second level signal input terminal and the target output terminal under the control of the output control node; and is also used to control the electrical connection between the first level signal input terminal and the target output terminal under the control of the third terminal of the first control unit.

6. The signal generation circuit of claim 5, wherein, The first output compensation sub-circuit includes: a third control unit and a fourth control unit; The third control unit is coupled to the output control node, the second level signal input terminal and the target output terminal respectively, and is used to control the electrical connection between the second level signal input terminal and the target output terminal to be turned on or off under the control of the output control node. The fourth control unit is coupled to the third terminal of the first control unit, the first level signal input terminal, and the target output terminal, respectively, and is used to control the electrical connection between the first level signal input terminal and the target output terminal to be turned on or off under the control of the third terminal of the first control unit.

7. The signal generation circuit of claim 4, wherein, The signal generation circuit further includes: a second output compensation sub-circuit, wherein the third terminal of the first control unit and the third terminal of the second control unit are coupled together, and are coupled to the target output terminal through the second output compensation sub-circuit; the second output compensation sub-circuit is also coupled to the control signal input terminal, the first level signal input terminal and the second level signal input terminal respectively; The second output compensation sub-circuit is used to: under the control of the third terminal of the first control unit, It controls the electrical connection between the second level signal input terminal and the target output terminal to be turned on or off; it is also used to control the electrical connection between the first level signal input terminal and the target output terminal to be turned on or off under the control of the control signal input terminal.

8. The signal generation circuit of claim 7, wherein, The second output compensation sub-circuit includes: a fifth control unit and a sixth control unit; The fifth control unit is coupled to the third terminal of the first control unit, the second level signal input terminal, and the target output terminal, respectively; it is used to control the electrical connection between the second level signal input terminal and the target output terminal to be turned on or off under the control of the third terminal of the first control unit. The sixth control unit is coupled to the control signal input terminal, the first level signal input terminal, and the target output terminal respectively; it is used to control the electrical connection between the first level signal input terminal and the target output terminal to be turned on or off under the control of the control signal input terminal.

9. The signal generation circuit according to claim 2, wherein, The output control sub-circuit is used to control the electrical connection between the second level signal input terminal and the target output terminal to be turned on or off under the control of the output control node. It is also used to control, under the control of the output control node, to control the electrical connection between the first level signal input terminal and the target output terminal to be turned on or off.

10. The signal generation circuit according to claim 9, wherein, The output control sub-circuit includes a seventh control unit and an eighth control unit; The seventh control unit is coupled to the output control node, the second level signal input terminal and the target output terminal respectively, and is used to control the electrical connection between the second level signal input terminal and the target output terminal to be turned on or off under the control of the output control node. The eighth control unit is coupled to the output control node, the first level signal input terminal and the target output terminal respectively, and is used to control the electrical connection between the first level signal input terminal and the target output terminal to be turned on or off under the control of the output control node.

11. The signal generation circuit according to claim 9 or 10, wherein, The signal generation circuit further includes: The third output compensation sub-circuit is coupled to the target output terminal, the second level signal input terminal, and the output control node, respectively, and is used to control the electrical connection between the second level signal input terminal and the output control node to be turned on or off under the control of the target output terminal.

12. The signal generation circuit according to claim 6, wherein, The first control sub-circuit includes a first transistor, the gate of the first transistor is coupled to the control signal input terminal, the first terminal of the first transistor is coupled to the first level signal input terminal, and the second terminal of the first transistor is coupled to the output control node; The second control sub-circuit includes a second transistor, the gate of which is coupled to the adjustable data signal input terminal, the first terminal of which is coupled to the analog signal input terminal, and the second terminal of which is coupled to the output control node. The second control unit includes a third transistor, the gate of which and the second terminal of which are both coupled to the first level signal input terminal; The first control unit includes a fourth transistor, the gate of which is coupled to the output control node, the first terminal of which is coupled to the first terminal of the third transistor, and the second terminal of which is coupled to the second level signal input terminal. The fourth control unit includes a fifth transistor, the gate of which is coupled to the first terminal of the fourth transistor, the first terminal of which is coupled to the first level signal input terminal, and the second terminal of which is coupled to the target output terminal; The third control unit includes a sixth transistor, the gate of which is coupled to the output control node, the first terminal of which is coupled to the second level signal input terminal, and the second terminal of which is coupled to the target output terminal.

13. The signal generation circuit according to claim 8, wherein, The first control sub-circuit includes a first transistor, the gate of the first transistor is coupled to the control signal input terminal, the first terminal of the first transistor is coupled to the first level signal input terminal, and the second terminal of the first transistor is coupled to the output control node; The second control sub-circuit includes a second transistor, the gate of which is coupled to the adjustable data signal input terminal, the first terminal of which is coupled to the analog signal input terminal, and the second terminal of which is coupled to the output control node. The second control unit includes a third transistor, the gate of which and the second terminal of which are both coupled to the first level signal input terminal; The first control unit includes a fourth transistor, the gate of which is coupled to the output control node, and the first terminal of which is coupled to the first terminal of the third transistor. The second terminal of the fourth transistor is coupled to the second level signal input terminal; The sixth control unit includes an eighth transistor and a second capacitor; the gate of the eighth transistor is coupled to the control signal input terminal, the first terminal of the eighth transistor is coupled to the first level signal input terminal, and the second terminal of the eighth transistor is coupled to the target output terminal. The first plate of the second capacitor is coupled to the first level signal input terminal, and the second plate of the second capacitor is coupled to the target output terminal; The fifth control unit includes a ninth transistor, the gate of which is coupled to the first terminal of the fourth transistor, the first terminal of which is coupled to the second level signal input terminal, and the second terminal of which is coupled to the target output terminal.

14. The signal generation circuit according to claim 11, wherein, The first control sub-circuit includes a first transistor, the gate of the first transistor is coupled to the control signal input terminal, the first terminal of the first transistor is coupled to the first level signal input terminal, and the second terminal of the first transistor is coupled to the output control node; The second control sub-circuit includes a second transistor, the gate of which is coupled to the adjustable data signal input terminal, the first terminal of which is coupled to the analog signal input terminal, and the second terminal of which is coupled to the output control node. The seventh control unit includes a tenth transistor, the gate of which is coupled to the output control node, the first terminal of which is coupled to the second level signal input terminal, and the second terminal of which is coupled to the target output terminal. The eighth control unit includes an eleventh transistor, the gate of which is coupled to the output control node, the first terminal of which is coupled to the first level signal input terminal, and the second terminal of which is coupled to the target output terminal; one of the eleventh transistor and the tenth transistor is a P-type transistor and the other is an N-type transistor.

15. The signal generation circuit according to claim 14, wherein, The third output compensation sub-circuit includes a twelfth transistor, the gate of which is coupled to the target output terminal, the first terminal of which is coupled to the second level signal input terminal, and the second terminal of which is coupled to the output control node.

16. The signal generation circuit according to claim 1, wherein, The first control sub-circuit includes a first transistor, the gate of the first transistor is coupled to the control signal input terminal, the first terminal of the first transistor is coupled to the first level signal input terminal, and the second terminal of the first transistor is coupled to the output control node; The second control sub-circuit includes a second transistor, the gate of which is coupled to the adjustable data signal input terminal, the first terminal of which is coupled to the analog signal input terminal, and the second terminal of which is coupled to the output control node.

17. The signal generation circuit according to claim 4, wherein, The first control sub-circuit includes a first transistor, the gate of the first transistor is coupled to the control signal input terminal, the first terminal of the first transistor is coupled to the first level signal input terminal, and the second terminal of the first transistor is coupled to the output control node; The second control sub-circuit includes a second transistor, the gate of which is coupled to the adjustable data signal input terminal, the first terminal of which is coupled to the analog signal input terminal, and the second terminal of which is coupled to the output control node. The second control unit includes a third transistor, the gate of which and the second terminal of which are both coupled to the first level signal input terminal; The first control unit includes a fourth transistor, the gate of which is coupled to the output control node, the first terminal of which is coupled to the first terminal of the third transistor, and the second terminal of which is coupled to the second level signal input terminal.

18. The signal generation circuit according to claim 1, wherein, The signal generation circuit further includes a capacitor structure, the first end of which is coupled to the output control node, and the second end of which is coupled to the first level signal input terminal.

19. The signal generation circuit according to claim 1, wherein, The analog signal input terminal is used to input a periodic analog signal, the level of which changes linearly within one cycle.

20. A display device comprising a signal generation circuit as claimed in any one of claims 1 to 19.

21. A driving method for a signal generation circuit, used to drive the signal generation circuit as described in any one of claims 1 to 19; the driving method includes a periodic output phase, the output phase including a first level output phase and a second level output phase; an analog signal with periodicity is input at an analog signal input terminal; in one of the output phases, the level value of the analog signal changes linearly; During the first level output phase, the second control sub-circuit outputs the adjustable data signal. Under the joint control of the input terminal and the analog signal input terminal, the electrical connection between the analog signal input terminal and the output control node is disconnected. In the initial stage of the first level output stage, the first control sub-circuit, under the control of the control signal input terminal, controls the electrical connection between the first level signal input terminal and the output control node to be turned on. During the non-starting phase of the first level output phase, the first control sub-circuit, under the control of the control signal input terminal, controls the disconnection of the electrical connection between the first level signal input terminal and the output control node; During the second level output phase: Under the control of the control signal input terminal, the first control sub-circuit controls the disconnection of the electrical connection between the first level signal input terminal and the output control node; The second control sub-circuit, under the joint control of the adjustable data signal input terminal and the analog signal input terminal, controls the electrical connection between the analog signal input terminal and the output control node.

22. The driving method for the signal generation circuit according to claim 21, wherein, The signal generation circuit further includes: an output control sub-circuit, wherein the output control node is coupled to the target output terminal through the output control sub-circuit, and the output control sub-circuit is also coupled to the first level signal input terminal and the second level signal input terminal respectively. The driving method further includes: During the first level output phase, the output control sub-circuit, under the control of the output control node, controls the target output terminal to receive the second level signal output from the second level signal input terminal; During the second level output phase, the output control sub-circuit, under the control of the output control node, controls the target output terminal to receive the first level signal output from the first level signal input terminal.

23. The driving method for the signal generation circuit according to claim 22, wherein, During the first level output phase, the output control sub-circuit, under the control of the first level signal input terminal, controls the electrical connection between the first level signal input terminal and the target output terminal to be turned on. Under the control of the output control node, the output control sub-circuit controls the electrical connection between the second level signal input terminal and the target output terminal to be turned on. During the second level output phase, the output control sub-circuit outputs the first level signal. Under the control of the input terminal, the electrical connection between the first level signal input terminal and the target output terminal is turned on. The output control sub-circuit, under the control of the output control node, controls the disconnection of the electrical connection between the second level signal input terminal and the target output terminal.

24. The driving method for the signal generation circuit according to claim 23, wherein, The output control sub-circuit includes: a first control unit and a second control unit; a first terminal of the first control unit is coupled to the output control node, a second terminal of the first control unit is coupled to the second level signal input terminal, and a third terminal of the first control unit is coupled to the target output terminal; a first terminal of the second control unit is coupled to the first level signal input terminal, a second terminal of the second control unit is coupled to the first level signal input terminal, and a third terminal of the second control unit is coupled to the target output terminal. During the first level output phase, the first control unit, under the control of the output control node, controls the electrical connection between the second level signal input terminal and the target output terminal to be turned on; the second control unit, under the control of the first level signal input terminal, controls the electrical connection between the first level signal input terminal and the third terminal of the second control unit to be turned on. During the second level output phase, the first control unit, under the control of the output control node, controls to disconnect the electrical connection between the second level signal input terminal and the target output terminal; the second control unit, under the control of the first level signal input terminal, controls to connect the electrical connection between the first level signal input terminal and the target output terminal.

25. The driving method for the signal generation circuit according to claim 24, wherein, The signal generation circuit further includes: a first output compensation sub-circuit, wherein the third terminal of the first control unit and the third terminal of the second control unit are coupled together, and are coupled to the target output terminal through the first output compensation sub-circuit; the first output compensation sub-circuit is also coupled to the first level signal input terminal, the second level signal input terminal and the output control node respectively; the driving method further includes: During the first level output phase, the first output compensation sub-circuit, under the control of the output control node, controls the electrical connection between the second level signal input terminal and the target output terminal to be turned on; the first output compensation sub-circuit, under the control of the third terminal of the first control unit, also controls the electrical connection between the first level signal input terminal and the target output terminal to be turned off. During the second-level output phase, the first output compensation sub-circuit, under the control of the output control node, controls the disconnection of the electrical connection between the second-level signal input terminal and the target output terminal. Connection; the first output compensation sub-circuit, under the control of the third terminal of the first control unit, controls the electrical connection between the first level signal input terminal and the target output terminal to be turned on.

26. The driving method for the signal generation circuit according to claim 24, wherein, The signal generation circuit further includes: a second output compensation sub-circuit, wherein the third terminal of the first control unit and the third terminal of the second control unit are coupled together, and are coupled to the target output terminal through the second output compensation sub-circuit; the second output compensation sub-circuit is also coupled to the control signal input terminal, the first level signal input terminal, and the second level signal input terminal respectively; the driving method further includes: During the first level output phase, the second output compensation sub-circuit, under the control of the third terminal of the first control unit, controls to disconnect the electrical connection between the second level signal input terminal and the target output terminal; the second output compensation sub-circuit, under the control of the control signal input terminal, also controls to connect the electrical connection between the first level signal input terminal and the target output terminal. During the second level output phase, the second output compensation sub-circuit, under the control of the third terminal of the first control unit, controls the electrical connection between the second level signal input terminal and the target output terminal to be turned on; the second output compensation sub-circuit, under the control of the control signal input terminal, also controls the electrical connection between the first level signal input terminal and the target output terminal to be turned off.

27. The driving method for the signal generation circuit according to claim 22, wherein, During the first level output phase, the output control sub-circuit is used to control the electrical connection between the second level signal input terminal and the target output terminal under the control of the output control node. It is also used to control the disconnection of the electrical connection between the first level signal input terminal and the target output terminal under the control of the output control node; During the second level output phase, the output control sub-circuit is used to control the disconnection of the electrical connection between the second level signal input terminal and the target output terminal under the control of the output control node; It is also used to control the electrical connection between the first level signal input terminal and the target output terminal under the control of the output control node.

28. The driving method for the signal generation circuit according to claim 27, wherein, The signal generation circuit further includes: a third output compensation sub-circuit, coupled to the target output terminal, the second level signal input terminal, and the output control node, respectively; the driving method further includes: During the first level output stage, the third output compensation sub-circuit, under the control of the target output terminal, controls the disconnection of the electrical connection between the second level signal input terminal and the output control node. During the second level output phase, the third output compensation sub-circuit, under the control of the target output terminal, controls the electrical connection between the second level signal input terminal and the output control node to be turned on.

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