Display panel and display apparatus

Abstract

The present disclosure relates to the technical field of display, and provides a display panel and a display apparatus. The display panel comprises: a base substrate, multiple pixel driving circuits, a first gate line, and a control circuit. Orthographic projections of the multiple pixel driving circuits onto the base substrate are distributed in an array in a first direction and a second direction, the first direction intersecting with the second direction, and multiple pixel driving circuits distributed in the first direction form pixel driving circuit rows. Each pixel driving circuit comprises a driving transistor and a second transistor, a first electrode of the second transistor being connected to a gate electrode of the driving transistor. An orthographic projection of the first gate line onto the base substrate extends along the first direction, and the first gate line is used for providing a gate driving signal to the multiple second transistors located in a same pixel driving circuit row. The control circuit is disposed corresponding to at least one pixel driving circuit. The control circuit is connected to the gate electrode of the second transistor and the first gate line in the pixel driving circuit corresponding to the control circuit, and the control circuit is used for responding to a control signal to place the gate electrode of the second transistor in communication with the first gate line, or is used for responding to the control signal so as to disconnect the gate electrode of the second transistor from the first gate line. The display panel can achieve adjustment of the refresh frequency of a local area of the display panel.

Description

Display panel and display device Technical Field

[0001] This disclosure relates to the field of display technology, and more particularly to a display panel and a display device. Background Technology

[0002] In related technologies, in order to improve the display effect of the display panel, the display panel has a high refresh rate. However, an excessively high refresh rate of the display panel will lead to excessive power consumption of the display panel.

[0003] It should be noted that the information disclosed in the background section above is only used to enhance the understanding of the background of this disclosure, and therefore may include information that does not constitute prior art known to those skilled in the art.

[0004] Summary of the Invention

[0005] According to one aspect of this disclosure, a display panel is provided, the display panel comprising:

[0006] Substrate;

[0007] Multiple pixel driving circuits are arranged in an array along a first direction and a second direction, with the orthographic projections of the multiple pixel driving circuits on the substrate intersecting each other. The multiple pixel driving circuits distributed in the first direction form a pixel driving circuit row.

[0008] The pixel driving circuit includes a driving transistor and a second transistor, wherein the first terminal of the second transistor is connected to the gate of the driving transistor.

[0009] A first gate line, whose orthogonal projection on the substrate extends along the first direction, is used to provide gate drive signals to a plurality of second transistors located in the same pixel drive circuit row;

[0010] A control circuit is provided, and at least one pixel driving circuit is correspondingly provided;

[0011] The control circuit is connected to the gate of the second transistor and the first gate line in the corresponding pixel driving circuit. The control circuit is used to respond to a control signal to connect the gate of the second transistor and the first gate line, or to respond to a control signal to disconnect the gate of the second transistor from the first gate line.

[0012] In one exemplary embodiment of this disclosure, the second terminal of the second transistor is connected to the second terminal of the driving transistor.

[0013] In one exemplary embodiment of this disclosure, the control circuit is further configured to respond to a control signal to transmit a turn-off signal to the gate of the second transistor.

[0014] In one exemplary embodiment of this disclosure, the control circuit and a portion of the pixel driving circuits in the same row of pixel driving circuits are correspondingly arranged.

[0015] In one exemplary embodiment of this disclosure, a plurality of pixel driving circuits distributed in the second direction form a pixel driving circuit column, and one or more adjacent pixel driving circuit columns form a pixel driving circuit group.

[0016] The display panel includes a plurality of pixel driving circuit groups, and the pixel driving circuit groups are correspondingly provided with a plurality of control circuits;

[0017] In the same pixel driving circuit group: the control circuit and the pixel driving circuit located in the same pixel driving circuit row are respectively set, and different control circuits correspond to pixel driving circuits in different pixel driving circuit rows.

[0018] In one exemplary embodiment of this disclosure, the display panel further includes:

[0019] The fifth gate line includes fifth gate line segments extending along the first direction and spaced apart along the first direction. The fifth gate line segments are correspondingly disposed with the pixel driving circuit group. A portion of the structure of the fifth gate line segment is used to form the gate of the second transistor located in the same pixel driving circuit row in the pixel driving circuit group corresponding to it.

[0020] The control circuit is connected to the gate of the second transistor in its corresponding pixel driving circuit via the fifth gate segment.

[0021] In one exemplary embodiment of this disclosure, the display panel further includes: a shutdown signal line and a fourth gate line, and the control circuit includes:

[0022] The ninth transistor has its first terminal connected to the first gate line, its second terminal connected to the gate of the second transistor, and its gate connected to the fourth gate line.

[0023] The tenth transistor has its first terminal connected to the turn-off signal line, its second terminal connected to the gate of the second transistor, and its gate connected to the fourth gate line.

[0024] The conduction signals of the ninth transistor and the tenth transistor have opposite polarities.

[0025] In one exemplary embodiment of this disclosure, the pixel driving circuit group includes two pixel driving circuit subgroups;

[0026] In the corresponding pixel driving circuit group and the control circuit, the orthographic projection of the control circuit on the substrate is located between the orthographic projections of the two pixel driving circuit subgroups on the substrate.

[0027] In one exemplary embodiment of this disclosure, the pixel driving circuit further includes a first transistor and a fourth transistor;

[0028] The first terminal of the first transistor is connected to the first initial signal line, the second terminal is connected to the second terminal of the driving transistor, and the gate is connected to the first reset signal line.

[0029] The first terminal of the fourth transistor is connected to the data line, the second terminal is connected to the first terminal of the driving transistor, and the gate is connected to the second gate line.

[0030] The display panel also includes:

[0031] A first active layer is located on one side of the substrate. The first active layer includes a ninth active portion, which is used to form the channel region of the ninth transistor.

[0032] In the same pixel driving circuit row, the orthographic projection of the ninth active part on the substrate is located between the orthographic projection of the second gate line on the substrate and the orthographic projection of the first reset signal line on the substrate.

[0033] In one exemplary embodiment of this disclosure, the pixel driving circuit further includes a fifth transistor;

[0034] The first terminal of the fifth transistor is connected to the first power supply line, the second terminal is connected to the first terminal of the driving transistor, and the gate is connected to the enable signal line.

[0035] The display panel also includes:

[0036] The second active layer is located on one side of the substrate. The second active layer includes a tenth active portion, which is used to form the channel region of the tenth transistor.

[0037] A third gate layer is located on the side of the second active layer away from the substrate. The third gate layer includes a fifth gate line, a portion of which is used to form the gate of the second transistor.

[0038] In the same pixel driving circuit row, the orthographic projection of the tenth active part on the substrate is located between the orthographic projection of the fifth gate line on the substrate and the orthographic projection of the enable signal line on the substrate.

[0039] In one exemplary embodiment of this disclosure, the display panel further includes: a fourth gate line, the fourth gate line extending along the second direction by its orthogonal projection on the substrate;

[0040] The fourth gate line is used to provide control signals to multiple control circuits corresponding to the same pixel driving circuit group.

[0041] In one exemplary embodiment of this disclosure, the pixel driving circuit group includes two pixel driving circuit subgroups;

[0042] The orthographic projection of the fourth gate line on the substrate lies between the orthographic projections of the two pixel driving circuit subgroups in the same pixel driving circuit group on the substrate.

[0043] In one exemplary embodiment of this disclosure, the display panel further includes a shutdown signal line, the shutdown signal line extending along the second direction by its orthogonal projection on the substrate, and the shutdown signal line being used to provide shutdown signals to a plurality of control circuits corresponding to the same pixel driving circuit group;

[0044] The orthographic projection of the shutdown signal line on the substrate is located between the orthographic projections of the two pixel driving circuit subgroups in the same pixel driving circuit group on the substrate, and the orthographic projection of the shutdown signal line on the substrate is located between the orthographic projection of the fourth gate line on the substrate and the orthographic projection of the pixel driving circuit subgroup on the substrate.

[0045] In one exemplary embodiment of this disclosure, the distance between the orthographic projections of two adjacent pixel driving circuit columns located in different pixel driving circuit groups on the substrate is less than the distance between the orthographic projections of two adjacent pixel driving circuit columns located in the same pixel driving circuit group but in different pixel driving circuit subgroups on the substrate.

[0046] In one exemplary embodiment of this disclosure, the display panel further includes:

[0047] A first source / drain layer is located on one side of the substrate. The first source / drain layer includes a first bridging portion, which is connected to the gate of the driving transistor and the first electrode of the second transistor through vias.

[0048] The second source / drain layer is located on the side of the first source / drain layer away from the substrate, and the second source / drain layer includes the fourth gate line and the turn-off signal line.

[0049] In one exemplary embodiment of this disclosure, the display panel further includes:

[0050] A first source / drain layer is located on one side of the substrate. The first source / drain layer includes a first bridging portion, which is connected to the gate of the driving transistor and the first electrode of the second transistor through vias.

[0051] The first source / drain layer includes the first gate line.

[0052] In one exemplary embodiment of this disclosure, the pixel driving circuit further includes a capacitor, the first electrode of which is connected to the gate of the driving transistor, and the second electrode of which is connected to a first power supply line.

[0053] The first gate line includes a first sub-gate line and a second sub-gate line, and the orthographic projection of the first sub-gate line on the substrate and the orthographic projection of the second sub-gate line on the substrate both extend along the first direction;

[0054] The display panel also includes:

[0055] A second gate layer is located on one side of the substrate. The second gate layer includes a third conductive portion and a first sub-gate line. The third conductive portion is used to form the second electrode of the capacitor.

[0056] The first source / drain layer is located on the side of the second gate layer away from the substrate. The first source / drain layer includes a first bridging portion, which is connected to the gate of the driving transistor and the first electrode of the second transistor through vias. The first source / drain layer also includes a second sub-gate line.

[0057] The first sub-gate line and the second sub-gate line are connected by vias.

[0058] In one exemplary embodiment of this disclosure, the control circuit includes:

[0059] The ninth transistor has its first terminal connected to the first gate line, its second terminal connected to the gate of the second transistor, and its gate connected to the fourth gate line.

[0060] The tenth transistor has its first terminal connected to the turn-off signal line, its second terminal connected to the gate of the second transistor, and its gate connected to the fourth gate line.

[0061] The display panel also includes:

[0062] A first active layer is located between the substrate and the second gate layer. The first active layer includes a ninth active portion, which is used to form the channel region of the ninth transistor.

[0063] The first source / drain layer further includes:

[0064] The second bridging portion is connected to the gate of the tenth transistor and the gate of the ninth transistor respectively through vias;

[0065] A protrusion is connected to the side of the second sub-gate line facing the second bridging portion, and the second sub-gate line is connected to the first sub-gate line through the through hole of the protrusion;

[0066] Wherein, the orthographic projection of the protrusion on the substrate and the orthographic projection of at least a portion of the second bridging portion on the substrate are located on both sides of the orthographic projection of the ninth active portion on the substrate in the first direction.

[0067] In one exemplary embodiment of this disclosure, the display panel further includes:

[0068] The second bridging portion is connected to the gate of the tenth transistor and the gate of the ninth transistor respectively through vias;

[0069] The second bridging portion and the shutdown signal line are located in different conductive layers, and the orthographic projection of the shutdown signal line on the substrate and the orthographic projection of the second bridging portion on the substrate at least partially overlap.

[0070] In one exemplary embodiment of this disclosure, the pixel driving circuit is connected to a first power line, and the first power line is used to provide a high-level signal to the pixel driving circuit.

[0071] The control circuit includes a tenth transistor, the first terminal of which is connected to the turn-off signal line, the second terminal of which is connected to the gate of the second transistor, and the gate is connected to the fourth gate line.

[0072] The display panel also includes:

[0073] The second active layer is located on one side of the substrate. The second active layer includes a tenth active portion, which is used to form the channel region of the tenth transistor.

[0074] The second source / drain layer is located on the side of the second active layer away from the substrate. The second source / drain layer includes a fifth conductive portion, which is connected to the first power line. In the same pixel driving circuit group, the orthogonal projections of the fifth conductive portions located in different pixel driving circuit subgroups and adjacent in the first direction X are spaced apart on the substrate.

[0075] The third source / drain layer is located on the side of the second source / drain layer away from the substrate. The third source / drain layer includes a sixteenth bridging portion. In the same pixel driving circuit group, the fifth conductive portions located in different pixel driving circuit subgroups and adjacent in the first direction X are bridged by the sixteenth bridging portion.

[0076] Wherein, the orthographic projection of the sixteenth bridging portion on the substrate and the orthographic projection of the tenth active portion on the substrate at least partially overlap.

[0077] In one exemplary embodiment of this disclosure, the third source / drain layer includes:

[0078] The first power line, whose orthogonal projection on the substrate extends along the second direction, is connected via a via to the fifth conductive portion intersecting with its orthogonal projection on the substrate.

[0079] In one exemplary embodiment of this disclosure, the pixel driving circuit subgroup includes two pixel driving circuit columns;

[0080] In the same subgroup of pixel driving circuits, two pixel driving circuits located in the same row of pixel driving circuits are arranged at least partially mirror-symmetrically.

[0081] In one exemplary embodiment of this disclosure, the display panel further includes a light-emitting unit, and the pixel driving circuit further includes a first transistor, a fifth transistor, a seventh transistor, and an eighth transistor;

[0082] The first terminal of the first transistor is connected to the first initial signal line, the second terminal is connected to the second terminal of the driving transistor, and the gate is connected to the first reset signal line.

[0083] The first terminal of the fifth transistor is connected to the first power supply line, the second terminal is connected to the first terminal of the driving transistor, and the gate is connected to the enable signal line.

[0084] The first electrode of the seventh transistor is connected to the second initial signal line, the second electrode is connected to the first electrode of the light-emitting unit, and the gate is connected to the second reset signal line.

[0085] The first terminal of the eighth transistor is connected to the third initial signal line, and the second terminal is connected to the first terminal of the driving transistor.

[0086] Wherein, the orthographic projection of the first initial signal line on the substrate and the orthographic projection of the second reset signal line in the adjacent previous row pixel driving circuit on the substrate at least partially overlap;

[0087] The orthographic projection of the second initial signal line on the substrate and the orthographic projection of the first reset signal line in the adjacent next row pixel driving circuit on the substrate at least partially overlap;

[0088] The orthographic projection of the third initial signal line on the substrate and the orthographic projection of the enable signal line in the current pixel driving circuit on the substrate at least partially overlap.

[0089] In one exemplary embodiment of this disclosure, the pixel driving circuit further includes:

[0090] The first transistor has a first terminal connected to a first initial signal line and a second terminal connected to the second terminal of the driving transistor.

[0091] The fourth transistor has its first terminal connected to the data line and its second terminal connected to the first terminal of the driving transistor.

[0092] The fifth transistor has its first terminal connected to the first power supply line and its second terminal connected to the first terminal of the driving transistor.

[0093] The sixth transistor has its first electrode connected to the second electrode of the driving transistor, and the second electrode connected to the first electrode of the light-emitting unit.

[0094] The seventh transistor has its first electrode connected to the second initial signal line and its second electrode connected to the first electrode of the light-emitting unit.

[0095] The eighth transistor has its first terminal connected to the third initial signal line and its second terminal connected to the first terminal of the driving transistor.

[0096] The capacitor has a first electrode connected to the gate of the driving transistor and a second electrode connected to the first power supply line.

[0097] The control circuit includes:

[0098] The ninth transistor has its first terminal connected to the first gate line and its second terminal connected to the gate of the second transistor.

[0099] The tenth transistor has its first terminal connected to the turn-off signal line and its second terminal connected to the gate of the second transistor.

[0100] Among them, the first transistor, the driving transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor, the eighth transistor, and the ninth transistor are P-type transistors, and the second transistor and the tenth transistor are N-type transistors.

[0101] In one exemplary embodiment of this disclosure, the display panel includes P-type transistors and N-type transistors, and the display panel further includes:

[0102] A first active layer is located on one side of the substrate, and a portion of the structure of the first active layer is used to form the channel region of the P-type transistor in the pixel driving circuit.

[0103] A first gate layer is located on the side of the first active layer away from the substrate, and a portion of the structure of the first gate layer is used to form the gate of the P-type transistor in the pixel driving circuit.

[0104] The second gate layer is located on the side of the first gate layer away from the substrate, and a portion of the structure of the second gate layer is used to form the bottom gate of the N-type transistor in the pixel driving circuit.

[0105] The second active layer is located on the side of the second gate layer away from the substrate, and a portion of the structure of the second active layer is used to form the channel region of the N-type transistor in the pixel driving circuit.

[0106] The third gate layer is located on the side of the second active layer away from the substrate, and a portion of the structure of the third gate layer is used to form the top gate of the N-type transistor in the pixel driving circuit.

[0107] The first source / drain layer is located on the side of the third gate layer opposite to the substrate, and a portion of the structure of the first source / drain layer is used to form a bridging portion connecting different transistors.

[0108] According to one aspect of this disclosure, a display panel is provided, wherein the display panel includes:

[0109] Substrate;

[0110] Multiple pixel driving circuits, wherein the orthographic projections of the multiple pixel driving circuits on the substrate are distributed in an array along a first direction and a second direction, the first direction and the second direction intersecting;

[0111] The pixel driving circuit includes a driving transistor and a second transistor, wherein the first terminal of the second transistor is connected to the gate of the driving transistor, and the second terminal of the second transistor is connected to the second terminal of the driving transistor.

[0112] A data line, whose orthogonal projection on the substrate extends along the second direction, is used to provide data signals to the pixel driving circuit.

[0113] A control circuit is provided, and at least one pixel driving circuit is correspondingly provided; the control circuit is used to control the switching on and off of the gate of the driving transistor and the second terminal of the driving transistor according to a control signal;

[0114] A fourth gate line, the fourth gate line extending along the second direction by its orthogonal projection on the substrate, the fourth gate line being used to provide the control signal to the control circuit.

[0115] According to one aspect of this disclosure, a display panel is provided, wherein the display panel includes:

[0116] Substrate;

[0117] Multiple pixel driving circuits, wherein the orthographic projections of the multiple pixel driving circuits on the substrate are distributed in an array along a first direction and a second direction, the first direction and the second direction intersecting;

[0118] The pixel driving circuit includes a driving transistor and a second transistor, wherein the first terminal of the second transistor is connected to the gate of the driving transistor, and the second terminal of the second transistor is connected to the second terminal of the driving transistor.

[0119] A data line, whose orthogonal projection on the substrate extends along the second direction, is used to provide data signals to the pixel driving circuit.

[0120] A control circuit is provided, and at least one pixel driving circuit is correspondingly provided; the control circuit is used to control the switching on and off of the gate of the driving transistor and the second terminal of the driving transistor according to a control signal;

[0121] The fourth gate line is used to provide the control signal to the control circuit. The conductive layer on which the fourth gate line is located is located on the side of the conductive layer away from the substrate of the data line, or the fourth gate line and the data line are located on the same conductive layer.

[0122] According to one aspect of this disclosure, a display device is provided, wherein the display device includes the display panel described above.

[0123] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Attached Figure Description

[0124] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure. It is obvious that the drawings described below are merely some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.

[0125] Figure 1 is a schematic diagram of an exemplary embodiment of the pixel driving circuit of this disclosure;

[0126] Figure 2 is a timing diagram of some nodes in an exemplary embodiment of the pixel driving circuit shown in Figure 1;

[0127] Figure 3 is a schematic diagram of an exemplary embodiment of a display panel in the related art;

[0128] Figure 4 is a schematic diagram of the structure of an exemplary embodiment of the display panel of this disclosure;

[0129] Figure 5 is a structural schematic diagram of another exemplary embodiment of the display panel of this disclosure;

[0130] Figure 6 is a structural layout diagram of an exemplary embodiment of the display panel of this disclosure;

[0131] Figure 7 is a structural layout of the shielding layer in Figure 6;

[0132] Figure 8 shows the structural layout of the first active layer in Figure 6;

[0133] Figure 9 is a structural layout of the first gate layer in Figure 6;

[0134] Figure 10 is a structural layout of the second gate layer in Figure 6;

[0135] Figure 11 shows the structural layout of the second active layer in Figure 6;

[0136] Figure 12 is a structural layout of the third gate layer in Figure 6;

[0137] Figure 13 is the structural layout of the first source / drain layer in Figure 6;

[0138] Figure 14 shows the structural layout of the second source / drain layer in Figure 6;

[0139] Figure 15 shows the structural layout of the third source / drain layer in Figure 6;

[0140] Figure 16 is a structural layout of the shielding layer and the first active layer in Figure 6;

[0141] Figure 17 is a structural layout of the shielding layer, the first active layer, and the first gate layer in Figure 6;

[0142] Figure 18 is a structural layout of the shielding layer, the first active layer, the first gate layer, and the second gate layer in Figure 6;

[0143] Figure 19 is a structural layout of the shielding layer, the first active layer, the first gate layer, the second gate layer, and the second active layer in Figure 6;

[0144] Figure 20 is a structural layout of the shielding layer, the first active layer, the first gate layer, the second gate layer, the second active layer, and the third gate layer in Figure 6.

[0145] Figure 21 is a structural layout of the shielding layer, the first active layer, the first gate layer, the second gate layer, the second active layer, the third gate layer, and the first source / drain layer in Figure 6.

[0146] Figure 22 is a structural layout of the shielding layer, the first active layer, the first gate layer, the second gate layer, the second active layer, the third gate layer, the first source / drain layer, and the second source / drain layer in Figure 6.

[0147] Figure 23 is a partial sectional view of the display panel shown in Figure 6, cut along the dashed line AA;

[0148] Figure 24 is a structural layout diagram of another exemplary embodiment of the display panel of this disclosure;

[0149] Figure 25 is a structural layout of the first active layer in the display panel shown in Figure 24;

[0150] Figure 26 is a structural layout of the second gate layer in the display panel shown in Figure 24;

[0151] Figure 27 is a structural layout of the first source / drain layer in the display panel shown in Figure 24;

[0152] Figure 28 is a schematic diagram of another exemplary embodiment of the display panel of this disclosure;

[0153] Figure 29 is a schematic diagram of another exemplary embodiment of the display panel of this disclosure;

[0154] Figure 30 is a schematic diagram of another exemplary embodiment of the display panel of this disclosure;

[0155] Figure 31 is a schematic diagram of another exemplary embodiment of the display panel of this disclosure;

[0156] Figure 32 is a structural layout of another exemplary embodiment of the display panel of this disclosure;

[0157] Figure 33 is a partial structural layout of the display panel shown in Figure 32;

[0158] Figure 34 is a schematic diagram of another exemplary embodiment of the display panel of this disclosure. Detailed Implementation

[0159] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the examples set forth herein; rather, they are provided so that this disclosure will be more comprehensive and complete, and will fully convey the concept of the exemplary embodiments to those skilled in the art. The same reference numerals in the drawings denote the same or similar structures, and therefore their detailed description will be omitted.

[0160] The terms “a,” “one,” and “the” are used to indicate the existence of one or more elements / components / etc.; the terms “including” and “having” are used to indicate an open-ended meaning of inclusion and that there may be other elements / components / etc. in addition to the listed elements / components / etc.

[0161] This exemplary embodiment first provides a pixel driving circuit, as shown in Figures 1 and 2. Figure 1 is a schematic diagram of the structure of an exemplary embodiment of the pixel driving circuit of this disclosure, and Figure 2 is a timing diagram of some nodes in an exemplary embodiment of the pixel driving circuit shown in Figure 1.

[0162] The pixel driving circuit may include: a driving transistor T3, a first transistor T1, a second transistor T2, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, an eighth transistor T8, and a capacitor C. Specifically, the first terminal of the fourth transistor T4 is connected to the data signal terminal Da, the second terminal of the fourth transistor T4 is connected to the first terminal of the driving transistor T3, and the gate of the fourth transistor T4 is connected to the second gate driving signal terminal G2. The first terminal of the fifth transistor T5 is connected to the first power supply terminal VDD, the second terminal of the fifth transistor T5 is connected to the first terminal of the driving transistor T3, and the gate of the fifth transistor T5 is connected to the enable signal terminal EM. The gate of the driving transistor T3 is connected to node N. The first terminal of the second transistor T2 is connected to node N, the second terminal of the second transistor T2 is connected to the second terminal of the driving transistor T3, and the gate of the second transistor T2 is connected to the first gate driving signal terminal G1. The first terminal of the sixth transistor T6 is connected to the second terminal of the driving transistor T3, and the second terminal of the sixth transistor T6 is connected to the seventh transistor T8. The second electrode of transistor T7 and the gate of the sixth transistor T6 are connected to the enable signal terminal EM. The first electrode of the seventh transistor T7 is connected to the second initial signal terminal Vinit2, and the gate of the seventh transistor T7 is connected to the second reset signal terminal Re2. The first electrode of the first transistor T1 is connected to the first initial signal terminal Vinit1, and the second electrode of the first transistor T1 is connected to the second electrode of the driving transistor T3. The gate of the first transistor T1 is connected to the first reset signal terminal Re1. The first electrode of the eighth transistor T8 is connected to the third initial signal terminal Vinit3, and the second electrode of the eighth transistor T8 is connected to the first electrode of the driving transistor T3. The gate of the eighth transistor T8 is connected to the second reset signal terminal Re2. The first electrode of capacitor C is connected to node N, and the second electrode of capacitor C is connected to the first power supply terminal VDD. This pixel driving circuit can be used to drive a light-emitting unit (OLED). The first electrode of the OLED can be connected to the second electrode of the sixth transistor T6, and the second electrode of the OLED can be connected to the second power supply terminal VSS. The first electrode of the OLED can be the anode of the OLED, and the second electrode can be the cathode of the OLED. In this design, the second transistor T2 can be an N-type transistor, such as an N-type metal-oxide-semiconductor transistor. N-type transistors have lower leakage current, which reduces the leakage current through the second transistor T2 at node N during the light-emitting stage. Meanwhile, the first transistor T1, driving transistor T3, fourth transistor T4, fifth transistor T5, sixth transistor T6, seventh transistor T7, and eighth transistor T8 can be P-type transistors, such as P-type low-temperature polysilicon transistors. P-type transistors have higher carrier mobility, which is beneficial for achieving display panels with high resolution, high response speed, high pixel density, and high aperture ratio.The first initial signal terminal, the second initial signal terminal, and the third initial signal terminal can output the same or different voltage signals according to the actual situation.

[0163] As shown in Figure 2, G1 represents the timing of the first gate drive signal terminal G1, G2 represents the timing of the second gate drive signal terminal G2, Re2 represents the timing of the second reset signal terminal Re2, Re1 represents the timing of the first reset signal terminal Re1, and EM represents the timing of the enable signal terminal EM. One driving cycle of this pixel driving circuit may include a first reset phase t1, a data writing phase t2, a second reset phase t3, and a light emission phase t4.

[0164] In the first reset phase t1: the first gate drive signal terminal G1 outputs a high level, the first reset signal terminal Re1 outputs a low level signal, the first transistor T1 and the second transistor T2 are turned on, and the first initial signal terminal Vinit1 inputs the first initial signal to node N through the first transistor T1 and the second transistor T2. In the data writing phase t2: the second gate drive signal terminal G2 outputs a low level signal, the first gate drive signal terminal G1 outputs a high level signal, the fourth transistor T4 and the second transistor T2 are turned on, and the data signal terminal Da writes the compensation voltage Vdata+Vth to node N through the fourth transistor T4 and the second transistor T2, where Vdata is the voltage of the data signal on the data signal terminal, and Vth is the threshold voltage of the driving transistor T3. In the second reset phase t3: the second reset signal terminal Re2 outputs a low level signal, the seventh transistor T7 and the eighth transistor T8 are turned on, the second initial signal terminal Vinit2 inputs the second initial signal to the first electrode of the light-emitting unit OLED, and the third initial signal terminal Vinit3 inputs the third initial signal to the first electrode of the driving transistor T3. During the light-emitting stage t4: the enable signal terminal EM outputs a low-level signal, turning on the sixth transistor T6 and the fifth transistor T5. This drives the light-emitting unit to emit light under the compensation voltage Vdata+Vth stored in capacitor C, caused by the driving transistor T3. The formula for the output current of the driving transistor is as follows:

[0165] I = (μWCox / 2L)(Vgs-Vth) 2

[0166] Where I is the output current of the driving transistor; μ is the carrier mobility; Cox is the gate capacitance per unit area; W is the width of the driving transistor channel; L is the length of the driving transistor channel; Vgs is the gate-source voltage difference of the driving transistor; and Vth is the threshold voltage of the driving transistor. In the pixel driving circuit described above, the output current of the driving transistor I = (μWCox / 2L)(Vdata + Vth - Vdd - Vth) 2 This pixel driving circuit can avoid the influence of the driving transistor threshold on its output current.

[0167] Figure 3 shows a schematic diagram of an exemplary embodiment of a display panel in the related art. The display panel may include a timing controller, a source driving circuit, a gate driving circuit, and a pixel array. The timing controller is connected to both the source driving circuit and the gate driving circuit. The source driving circuit is connected to multiple data lines (Da1 to Dan). The gate driving circuit includes a scan driving circuit and a light-emitting driving circuit. The scan driving circuit is connected to multiple scan signal lines (S1 to Sm), and the light-emitting driving circuit is connected to multiple light-emitting signal lines (E1 to Eo). The pixel array may include multiple sub-pixels Pxij, where i and j can be natural numbers. Each sub-pixel Pxij may include a pixel driving circuit and a light-emitting device connected to the pixel driving circuit. The pixel driving circuit may be connected to the scan signal lines, light-emitting signal lines, and data lines. The data lines can be used to provide the data signal terminals described above, and the light-emitting signal lines can be used to provide the enable signal terminals described above. This exemplary embodiment only shows one scan signal line connected to the pixel driving circuit. Each row of pixel driving circuits can be connected to multiple scan signal lines, which can be used to provide the first gate driving signal terminal, the second gate driving signal terminal, the first reset signal terminal, and the second reset signal terminal described above, respectively. In the exemplary embodiment, the timing controller can provide grayscale values ​​and control signals of specifications suitable for the source driving circuit to the source driving circuit, provide clock signals, scan start signals, etc. of specifications suitable for the scan driving circuit to the scan driving circuit, and provide clock signals, emission stop signals, etc. of specifications suitable for the light-emitting driving circuit to the light-emitting driving circuit. The source driving circuit can use the grayscale values ​​and control signals received from the timing controller to generate data signals to be provided to the data lines Da1, Da2, Da3, ... and Dan. For example, the source driver circuit can sample grayscale values ​​using a clock signal and apply data signals corresponding to the grayscale values ​​to data lines Da1 to Dan in pixel rows, where n can be a natural number. The scan driver circuit can generate scan signals to be provided to scan signal lines S1, S2, S3, ..., Sm by receiving clock signals, scan start signals, etc., from a timing controller. For example, the scan driver circuit can sequentially provide scan signals with on-level pulses to scan signal lines S1 to Sm. For example, the scan driver circuit can be configured as a shift register and can generate scan signals by sequentially transmitting scan start signals in the form of on-level pulses to the next stage circuit under the control of a clock signal, where m can be a natural number. The light-emitting driver circuit can generate transmit signals to be provided to light-emitting signal lines E1, E2, E3, ..., Eo by receiving clock signals, transmit stop signals, etc., from a timing controller. For example, the light-emitting driver circuit can sequentially provide transmit signals with off-level pulses to light-emitting signal lines E1 to Eo.For example, the light-emitting driving circuit can be constructed as a shift register, and can generate a transmission signal by sequentially transmitting a transmit stop signal provided in the form of a cutoff level pulse to the next stage circuit under the control of a clock signal, where 0 can be a natural number. Thus, the display panel can achieve line-by-line scanning and driving.

[0168] Figure 4 shows a schematic diagram of an exemplary embodiment of the display panel of this disclosure. The display panel may include a substrate, a plurality of pixel driving circuits Pi, a first gate line G1, and a control circuit K. The orthographic projections of the plurality of pixel driving circuits Pi on the substrate are distributed in an array along a first direction X and a second direction Y. The first direction X and the second direction Y intersect, for example, the first direction X and the second direction Y may be perpendicular. A plurality of pixel driving circuits distributed along the first direction X form a pixel driving circuit row Pih; wherein, the pixel driving circuit Pi includes a driving transistor T3 and a second transistor T2, the first terminal of the second transistor T2 is connected to the gate of the driving transistor T3, and the second terminal of the second transistor T2 is connected to the second terminal of the driving transistor T3; a first gate line G1 extends along the first direction X on the substrate, and the first gate line G1 is used to provide a gate driving signal to a plurality of second transistors T2 located in the same pixel driving circuit row; a control circuit K is correspondingly disposed with at least one pixel driving circuit; the control circuit K is connected to the gate of the second transistor T2 and the first gate line G1 in the corresponding pixel driving circuit, and the control circuit K is used to respond to a control signal to connect the gate of the second transistor T2 and the first gate line G1, or to respond to a control signal to transmit a turn-off signal to the gate of the second transistor T2.

[0169] This exemplary embodiment can control the driving state of the second transistor T2 in the pixel driving circuit connected to it via the control circuit K. When the control circuit K controls the gate of the second transistor T2 to connect to the first gate line G1, the second transistor T2 normally receives the gate driving signal on the first gate line G1, and the second transistor T2 can write a compensation voltage to the gate of the driving transistor T3 in each frame; when the control circuit K controls the gate of the second transistor T2 to receive a turn-off signal, the second transistor T2 is in the turn-off state, and the second transistor T2 cannot write a compensation voltage to the gate of the driving transistor T3. That is, this exemplary embodiment can adjust the refresh frequency of the pixel driving circuit connected to it via the control circuit K, and multiple control circuits K can adjust the refresh frequency of different areas of the display panel.

[0170] In this exemplary embodiment, the control circuit and a portion of the pixel driving circuits in the same row of pixel driving circuits are correspondingly configured. When the display panel is driven row by row, the control circuit can control the second transistor row by row. It should be understood that in other exemplary embodiments, the display panel can be driven in other ways, and correspondingly, the control circuit and pixel driving circuits can also have other corresponding configurations. For example, when the display panel is driven in two rows, the control circuit can be correspondingly configured with a portion of the pixel driving circuits in the two rows of pixel driving circuits.

[0171] In this exemplary embodiment, as shown in FIG4, a plurality of pixel driving circuits Pi distributed in the second direction form a pixel driving circuit column Piv, and one or more adjacent pixel driving circuit columns form a pixel driving circuit group Pivz; the display panel includes a plurality of pixel driving circuit groups Pivz, and a plurality of control circuits K are correspondingly arranged in the pixel driving circuit groups Pivz. In the same pixel driving circuit group Pivz: the control circuit K is correspondingly arranged with the pixel driving circuit located in the same pixel driving circuit row Pih, and different control circuits K correspond to pixel driving circuits in different pixel driving circuit rows Pih.

[0172] As shown in Figure 4, the display panel further includes a fourth gate line G4 and a shutdown signal line VGL. The orthogonal projection of the fourth gate line G4 onto the substrate extends along the second direction Y. The fourth gate line G4 can be used to provide control signals to multiple control circuits corresponding to the same pixel driving circuit group Pivz. The orthogonal projection of the shutdown signal line VGL onto the substrate extends along the second direction Y. The shutdown signal line VGL can be used to provide shutdown signals to multiple control circuits corresponding to the same pixel driving circuit group Pivz.

[0173] In this exemplary embodiment, as shown in FIG4, the control circuit may include a ninth transistor T9 and a tenth transistor T10. The first terminal of the ninth transistor T9 is connected to the first gate line G1, the second terminal is connected to the gate of the second transistor T2, and the gate is connected to the fourth gate line G4; the first terminal of the tenth transistor T10 is connected to the turn-off signal line VGL, the second terminal is connected to the gate of the second transistor T2, and the gate is connected to the fourth gate line G4; wherein, the turn-on polarities of the ninth transistor T9 and the tenth transistor T10 are opposite, for example, the ninth transistor T9 may be a P-type transistor, and the tenth transistor T10 may be an N-type transistor.

[0174] In this exemplary embodiment, as shown in FIG4, the display panel further includes a fifth gate line G5, the fifth gate line G5 including fifth gate line segments G51 extending along the first direction X and spaced apart along the first direction X, the fifth gate line segments G51 and the pixel driving circuit group Pivz are correspondingly disposed, and a portion of the structure of the fifth gate line segment G51 is used to form the gate of the second transistor located in the same pixel driving circuit row in the pixel driving circuit group corresponding to it; the control circuit can be connected to the gate of the corresponding second transistor T2 through the fifth gate line segment G51.

[0175] This exemplary embodiment can control the refresh frequency of its corresponding pixel driving circuit group Pivz via the fourth gate line G4. For example, as shown in FIG4, when the left fourth gate line G4 outputs a low-level signal, the ninth transistor T9 connected to the left fourth gate line G4 is turned on, and the first gate line G1 can normally provide the gate driving signal to the left pixel driving circuit group Pivz; when the left fourth gate line G4 outputs a low-high level signal, the tenth transistor T10 connected to the left fourth gate line G4 is turned on, and the turn-off signal line raises the turn-off signal to the gate of the second transistor T2 in the left pixel driving circuit group Pivz, so the left pixel driving circuit group Pivz no longer writes new data signals, thereby reducing the refresh frequency of the left pixel driving circuit group Pivz.

[0176] It should be noted that the shutdown signal is the signal that shuts down the target circuit. For example, the shutdown signal for a P-type transistor is a high-level signal, and the shutdown signal for an N-type transistor is a low-level signal. The turn-on signal is the signal that turns on the target circuit. For example, the turn-on signal for a P-type transistor is a low-level signal, and the turn-on signal for an N-type transistor is a high-level signal. Furthermore, the control signal responding to the connection between the gate of the second transistor T2 and the first gate line G1 by the control circuit K, and the control signal responding to the shutdown signal provided by the control circuit K to the gate of the second transistor T2, can be provided by the same signal line or by different signal lines. This exemplary embodiment only shows a portion of the pixel driving circuitry of the display panel; this disclosure does not limit the number of pixel driving circuits in the display panel.

[0177] It should be understood that in other exemplary embodiments, the pixel driving circuit Pi may also have other structures. For example, the pixel driving circuit Pi may be the structure shown in FIG1. ​​For another example, based on the pixel driving circuit shown in FIG1, the pixel driving circuit Pi may not include the eighth transistor T8. For yet another example, based on the pixel driving circuit shown in FIG1, the first transistor T1 may be connected to the gate of the driving transistor T3. Correspondingly, the first transistor T1 may also be an N-type transistor.

[0178] In this exemplary embodiment, as shown in FIG4, the fourth gate line G4 is connected to the control circuit K corresponding to the same pixel driving circuit group Pivz. The fourth gate line G4 is used to provide control signals to the multiple control circuits corresponding to the same pixel driving circuit group. It should be understood that in other exemplary embodiments, the fourth gate line may also be connected to the control circuit K corresponding to different pixel driving circuit groups Pivz.

[0179] In this exemplary embodiment, as shown in FIG4, the conduction signals of the ninth transistor T9 and the tenth transistor T10 have different polarities; that is, the conduction signals of the ninth transistor T9 and the tenth transistor T10 are one high level and the other low level. It should be understood that in other exemplary embodiments, the conduction signals of the ninth transistor T9 and the tenth transistor T10 may also have the same polarity, and correspondingly, the ninth transistor and the tenth transistor can be controlled by two gate lines respectively.

[0180] In this exemplary embodiment, as shown in FIG4, the number of pixel driving circuit columns Piv in each pixel driving circuit group Pivz is the same. It should be understood that in other exemplary embodiments, the number of pixel driving circuit columns Piv in at least some pixel driving circuit groups Pivz may be different.

[0181] In this exemplary embodiment, as shown in FIG4, the pixel driving circuit group Pivz includes two pixel driving circuit columns Piv. It should be understood that in other exemplary embodiments, the pixel driving circuit group Pivz may also include other numbers of pixel driving circuit columns Piv. For example, FIG5 shows a schematic diagram of the structure of another exemplary embodiment of the display panel of this disclosure. The pixel driving circuit group Pivz may include four pixel driving circuit columns Piv. Furthermore, in other exemplary embodiments, the pixel driving circuit group Pivz may also include one pixel driving circuit column Piv.

[0182] The shutdown signal line VGL is configured to correspond to one column of pixel driving circuits, or it can be configured to correspond to multiple columns of pixel driving circuits. The shutdown signal line VGL can share a signal line with other signal lines in the display panel. For example, the first initial signal line Vinit1, the second initial signal line Vinit2, and the low-level power line VSS in the display panel can be multiplexed as the shutdown signal line VGL. The low-level power line VSS is used to provide a second power supply terminal.

[0183] In this exemplary embodiment, the pixel driving circuit group Pivz may also include a pixel driving circuit column Piv, and correspondingly, a turn-off signal line and a column of pixel driving circuits are arranged. The voltages on each turn-off signal line may be the same or different; for example, the voltage of the turn-off signal line corresponding to the R pixel column (or B pixel column) may be less than the voltage of the turn-off signal line corresponding to the G pixel column. Based on the different turn-on speeds of the light-emitting units in different color pixel units, this arrangement can reduce the power consumption of the display panel while ensuring display quality.

[0184] In this exemplary embodiment, the second transistor T2 can also be a P-type transistor. Correspondingly, the shutdown signal line is a high-level power supply signal line, and the first power supply line VDD in the display panel can be multiplexed as the shutdown signal line. Similarly, the voltages on each shutdown signal line can be the same or different. For example, the voltage on the shutdown signal line corresponding to the R pixel column (or G pixel column) can be less than the voltage on the shutdown signal line corresponding to the B pixel column. This can further save power consumption.

[0185] This exemplary embodiment also provides a display panel, which may include a substrate, a shielding layer, a first active layer, a first gate layer, a second gate layer, a second active layer, a third gate layer, a first source / drain layer, a second source / drain layer, and a third source / drain layer stacked sequentially. An insulating layer may be disposed between adjacent layers. As shown in Figures 6-22, Figure 6 is a structural layout diagram of an exemplary embodiment of the display panel of this disclosure; Figure 7 is a structural layout diagram of the shielding layer in Figure 6; Figure 8 is a structural layout diagram of the first active layer in Figure 6; Figure 9 is a structural layout diagram of the first gate layer in Figure 6; Figure 10 is a structural layout diagram of the second gate layer in Figure 6; Figure 11 is a structural layout diagram of the second active layer in Figure 6; Figure 12 is a structural layout diagram of the third gate layer in Figure 6; Figure 13 is a structural layout diagram of the first source / drain layer in Figure 6; Figure 14 is a structural layout diagram of the second source / drain layer in Figure 6; Figure 15 is a structural layout diagram of the third source / drain layer in Figure 6; Figure 16 is a structural layout diagram of the shielding layer and the first active layer in Figure 6; and Figure 17 is a structural layout diagram of the shielding layer, the first active layer, and the first gate layer in Figure 6. The structural layouts are as follows: Figure 18 shows the structural layout of the shielding layer, first active layer, first gate layer, and second gate layer in Figure 6; Figure 19 shows the structural layout of the shielding layer, first active layer, first gate layer, second gate layer, and second active layer in Figure 6; Figure 20 shows the structural layout of the shielding layer, first active layer, first gate layer, second gate layer, second active layer, and third gate layer in Figure 6; Figure 21 shows the structural layout of the shielding layer, first active layer, first gate layer, second gate layer, second active layer, third gate layer, and first source / drain layer in Figure 6; and Figure 22 shows the structural layout of the shielding layer, first active layer, first gate layer, second gate layer, second active layer, third gate layer, first source / drain layer, and second source / drain layer in Figure 6.

[0186] The difference between this display panel and the display panel shown in Figure 5 is that the pixel driving circuit in this display panel is as shown in Figure 1.

[0187] As shown in Figure 6, in this exemplary embodiment, the pixel driving circuit group Pivz may include two pixel driving circuit subgroups Pivz1; in the corresponding pixel driving circuit group Pivz and the control circuit K, the orthographic projection of the control circuit K on the substrate is located between the orthographic projections of the two pixel driving circuit subgroups Pivz1 on the substrate. As shown in Figure 6, each pixel driving circuit subgroup Pivz1 includes two pixel driving circuit columns Piv. It should be understood that in other exemplary embodiments, the number of pixel driving circuit columns Piv in each pixel driving circuit subgroup Pivz1 may be the same or different.

[0188] As shown in Figures 6, 7, and 16, the shielding layer includes multiple shielding portions 81 distributed in an array along the first direction X and the second direction Y, and the shielding portions 81 are interconnected.

[0189] As shown in Figures 6, 8, 16, and 17, the first active layer may include: the first active section 71, the third active section 73, the fourth active section 74, the fifth active section 75, the sixth active section 76, the seventh active section 77, the eighth active section 78, the ninth active section 79, the twenty-second active section 722, the eleventh active section 711, the twelfth active section 712, the thirteenth active section 713, the fourteenth active section 714, the fifteenth active section 715, the sixteenth active section 716, the seventeenth active section 717, the eighteenth active section 718, the nineteenth active section 719, the twentieth active section 720, and the twenty-first active section 721. The first active portion 71 is used to form the channel region of the first transistor T1; the third active portion 73 can be used to form the channel region of the driving transistor T3; the fourth active portion 74 can be used to form the channel region of the fourth transistor T4; the fifth active portion 75 can be used to form the channel region of the fifth transistor T5; the sixth active portion 76 can be used to form the channel region of the sixth transistor T6; the seventh active portion 77 can be used to form the channel region of the seventh transistor T7; the eighth active portion 78 can be used to form the channel region of the eighth transistor T8; the ninth active portion 79 can be used to form the channel region of the ninth transistor T9; the twenty-second active portion 722 and the twelfth active portion 712 are connected to the two ends of the eighth active portion 78. In the same pixel driving circuit subgroup, adjacent pixel driving circuits in the first direction X can share the same twelfth active portion 712; the eleventh active portion 711 is connected between the fourth active portion 74 and the third active portion 73; the thirteenth active portion 713 is connected to... The fourth active part 74 is located on the side away from the third active part 73; the fourteenth active part 714 is connected to the seventh active part 77 on the side away from the sixth active part 76; the fifteenth active part 715 is connected to the fifth active part 75 on the side away from the third active part 73; the sixteenth active part 716 is connected between the seventh active part 77 and the sixth active part 76; the seventeenth active part 717 and the eighteenth active part 718 are connected to the two ends of the first active part 71, and the pixel driving circuits located in adjacent pixel driving circuit groups Pivz and adjacent in the first direction can share the same eighteenth active part 718. In the same pixel driving circuit group Pivz, the eighteenth active parts 718 adjacent in the first direction X in two adjacent pixel driving circuit subgroups Pivz1 can be arranged at intervals; the nineteenth active part 719 is connected between the third active part 73 and the sixth active part 76; the twentieth active part 720 and the twenty-first active part 721 are connected to the two ends of the ninth active part 79. The first active layer can be formed of polycrystalline silicon material. Correspondingly, the first transistor T1, the driving transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, the eighth transistor T8, and the ninth transistor T9 can be P-type low-temperature polycrystalline silicon thin-film transistors.

[0190] The orthographic projection of the shielding portion 81 on the substrate can at least partially overlap with the orthographic projection of the third active portion 73 on the substrate. The shielding portion 81 can block light from the third active portion 73 to improve the stability of the output characteristics of the driving transistor. The shielding layer can be a conductive structure, and the shielding layer can be connected to a stable voltage source. The shielding layer can also act as a signal shield for the pixel driving circuit.

[0191] As shown in Figures 6, 9, 16, and 17, the first gate layer may include: a first conductive portion 11, a second conductive portion 12, a second gate line G2, an enable signal line EM, a first reset signal line Re1, and a second reset signal line Re2. The second gate line G2 can be used to provide the second gate drive signal terminal in Figure 1; the enable signal line EM can be used to provide the enable signal terminal in Figure 1; the first reset signal line Re1 can be used to provide the first reset signal terminal in Figure 1; and the second reset signal line Re2 can be used to provide the second reset signal terminal in Figure 1. The orthographic projections of the second gate line G2, the enable signal line EM, the first reset signal line Re1, and the second reset signal line Re2 on the substrate can all extend along the first direction X. The orthographic projection of the second gate line G2 on the substrate covers the orthographic projection of the fourth active portion 74 on the substrate, and a portion of the structure of the second gate line G2 is used to form the gate of the fourth transistor. The orthographic projection of the enable signal line EM onto the substrate covers the orthographic projections of the fifth active portion 75 and the sixth active portion 76 onto the substrate. A portion of the structure of the enable signal line EM can be used to form the gates of the fifth transistor T5 and the sixth transistor T6, respectively. The orthographic projection of the first reset signal line Re1 onto the substrate covers the orthographic projection of the first active portion 71 onto the substrate. A portion of the structure of the first reset signal line Re1 is used to form the gate of the first transistor T1. The orthographic projection of the second reset signal line Re2 onto the substrate covers the orthographic projections of the seventh active portion 77 and the eighth active portion 78 onto the substrate. A portion of the structure of the first reset signal line Re1 can be used to form the gates of the seventh transistor T7 and the eighth transistor T8, respectively. The orthographic projection of the first conductive portion 11 onto the substrate covers the orthographic projection of the third active portion 73 onto the substrate. The first conductive portion 11 can be used to form the gate of the driving transistor T3 and the first electrode of the capacitor C. The orthographic projection of the second conductive portion 12 on the substrate covers the orthographic projection of the ninth active portion 79 on the substrate. The second conductive portion 12 can be used to form the gate of the ninth transistor T9. The display panel can use the first gate layer as a mask to perform a conductor treatment on the first active layer, that is, the area of ​​the first active layer covered by the first gate layer can form the channel region of the transistor, and the area of ​​the first active layer not covered by the first gate layer forms a conductor structure.

[0192] As shown in Figures 6, 10, and 18, the second gate layer may include: a third gate line G3, a third conductive portion 23, and a fourth conductive portion 24. The third gate line G3 includes third gate line segments G31 extending along the first direction X and spaced apart along the first direction X. The third gate line segments G31 are correspondingly disposed with the pixel driving circuit group Pivz. A portion of the structure of the third gate line segment G31 is used to form the bottom gate of the second transistor in the corresponding pixel driving circuit group. The control circuit can be connected to the gate of its corresponding second transistor through the third gate line segment G31. The orthographic projection of the third conductive portion 23 on the substrate may at least partially overlap with the orthographic projection of the first conductive portion 11 on the substrate. The third conductive portion 23 can be used to form the second electrode of the capacitor C.

[0193] As shown in Figures 6, 10, and 18, in the same pixel driving circuit subgroup Pivz1, adjacent third conductive parts 23 in the first direction X can be connected to each other through the first connecting part 21; adjacent third conductive parts 23 in the first direction X and located in different pixel driving circuit subgroups Pivz1 can be arranged at intervals.

[0194] As shown in Figures 6, 11, and 19, the second active layer may include a second active portion 92, a twenty-third active portion 923, a twenty-fourth active portion 924, a tenth active portion 910, a twenty-fifth active portion 925, and a twenty-sixth active portion 926. The twenty-third active portion 923 and the twenty-fourth active portion 924 are connected to the two ends of the second active portion 92; the twenty-fifth active portion 925 and the twenty-sixth active portion 926 are connected to the two ends of the tenth active portion 910. The second active portion 92 is used to form the channel region of the second transistor T2. The tenth active portion 910 is used to form the channel region of the tenth transistor T10. The second active layer may be formed of indium gallium zinc oxide (IGaZn), and correspondingly, the second transistor T2 and the tenth transistor T10 may be N-type metal-oxide thin-film transistors. The orthogonal projection of the third gate line G3 onto the substrate may cover the orthogonal projection of the second active portion 92 onto the substrate, and a portion of the structure of the third gate line G3 may be used to form the bottom gate of the second transistor T2. The orthographic projection of the fourth conductive portion 24 on the substrate covers the orthographic projection of the tenth active portion 910 on the substrate, and at least a portion of the fourth conductive portion 24 can be used to form the bottom gate of the tenth transistor T10.

[0195] As shown in Figures 6, 12, and 20, the third gate layer may include a fifth gate line G5, a first initial signal line Vinit1, a second initial signal line Vinit2, a third initial signal line Vinit3, and a sixth conductive portion 36. The fifth gate line G5 includes fifth gate line segments G51 extending along the first direction X and spaced apart along the first direction X. The fifth gate line segments G51 and the pixel driving circuit group Pivz are correspondingly disposed. The orthographic projection of the fifth gate line segments G51 on the substrate covers the orthographic projection of the second active portion 92 on the substrate. A portion of the structure of the fifth gate line segments G51 is used to form the gate of the second transistor located in the same pixel driving circuit row in the corresponding pixel driving circuit group. The control circuit K can be connected to the gate of its corresponding second transistor through the fifth gate line segments G51. The orthographic projections of the first initial signal line Vinit1, the second initial signal line Vinit2, and the third initial signal line Vinit3 on the substrate can all extend along the first direction X. The first initial signal line Vinit1 can be used to provide the first initial signal terminal in FIG1, the second initial signal line Vinit2 can be used to provide the second initial signal terminal in FIG1, and the third initial signal line Vinit3 can be used to provide the third initial signal terminal in FIG1. ​​The orthographic projection of the first initial signal line Vinit1 on the substrate can at least partially coincide with the orthographic projection of the second reset signal line Re2 in the adjacent previous row pixel driving circuit on the substrate. The orthographic projection of the second initial signal line Vinit2 on the substrate can at least partially coincide with the orthographic projection of the first reset signal line Re1 in the adjacent next row pixel driving circuit on the substrate. The orthographic projection of the third initial signal line Vinit3 on the substrate at least partially coincides with the orthographic projection of the enable signal line EM in the current row pixel driving circuit on the substrate. This arrangement can improve the light transmittance and integration of the display panel. The orthographic projection of the sixth conductive part 36 on the substrate covers the orthographic projection of the tenth active part 910 on the substrate. At least a portion of the structure of the sixth conductive part 36 is used to form the top gate of the tenth transistor T10.

[0196] Furthermore, the display panel can use the third gate layer as a mask to conduct the second active layer, that is, the area of ​​the second active layer covered by the third gate layer can form the channel region of the transistor, and the area of ​​the second active layer not covered by the third gate layer forms a conductor structure.

[0197] It should be noted that in other exemplary embodiments, the first initial signal line Vinit1, the second initial signal line Vinit2, and the third initial signal line Vinit3 may also be located in other conductive layers. For example, the first initial signal line Vinit1, the second initial signal line Vinit2, and the third initial signal line Vinit3 may also be located in the second gate layer, the first source / drain layer, etc.

[0198] As shown in Figures 6, 13, and 21, the first source / drain layer may include a first bridging portion 41, a second bridging portion 42, a third bridging portion 43, a fourth bridging portion 44, a fifth bridging portion 45, a sixth bridging portion 46, a seventh bridging portion 47, an eighth bridging portion 48, a ninth bridging portion 49, a tenth bridging portion 410, an eleventh bridging portion 411, a twelfth bridging portion 412, and a first gate line G1. The first bridging portion 41 can connect to the twenty-fourth active portion 924 and the first conductive portion 11 via vias, thereby connecting the gate of the driving transistor T3 and the first electrode of the second transistor T2. An opening 231 may be formed on the third conductive portion 23, and a via connecting the first bridging portion 41 and the first conductive portion 11 is disposed through the opening 231. The second bridging portion 42 connects to the second conductive portion 12, the fourth conductive portion 24, and the sixth conductive portion 36 via vias, thereby connecting the gate of the ninth transistor T9 and the gate of the tenth transistor T10. The third bridging section 43 can be connected to the first connecting section 21 and the fifteenth active section 715 via vias to connect the second electrode of capacitor C and the first electrode of fifth transistor T5. The fourth bridging section 44 can be connected to the eleventh active section 711 and the twenty-second active section 722 via vias to connect the second electrode of eighth transistor T8 and the first electrode of driving transistor T3. The fifth bridging section 45 can be connected to the third initial signal line Vinit3 and the twelfth active section 712 via vias to connect the first electrode of eighth transistor and the third initial signal line Vinit3. The sixth bridging section 46 can be connected to the thirteenth active section 713 via vias to connect the first electrode of fourth transistor T4. The seventh bridging section 47 can be connected to the nineteenth active section 719, the twenty-third active section 923, and the seventeenth active section 717 via vias to connect the second electrodes of first transistor T1, second transistor T2, and driving transistor T3. The eighth bridging section 48 can connect the eighteenth active section 718 and the first initial signal line Vinit1 via vias, respectively, to connect the first terminal and the first initial signal terminal of the first transistor T1. The ninth bridging section 49 can connect the fourteenth active section 714 and the second initial signal line Vinit2 via vias, respectively, to connect the first terminal and the second initial signal line of the seventh transistor T7. The tenth bridging section 410 can connect the sixteenth active section 716 via vias, respectively, to connect the second terminal of the seventh transistor T7 and the second terminal of the sixth transistor T6. The eleventh bridging section 411 can connect the twenty-sixth active section 926 via vias, respectively, to connect the first terminal of the tenth transistor T10. The twelfth bridging section 412 can connect the twentieth active section 720, the fifth gate segment G51, the third gate segment G31, and the twenty-fifth active section 925 via vias, respectively, to connect the second terminal of the ninth transistor T9, the second terminal of the tenth transistor T10, and the gate of the second transistor T2.The orthogonal projection of the first gate line G1 on the substrate can extend along the first direction X. The first gate line G1 can be used to provide the first gate drive signal terminal in FIG1. ​​The first gate line G1 can be connected to the twenty-first active part 721 through a via to connect the first electrode of the ninth transistor T9 and the first gate line G1.

[0199] As shown in Figures 6, 14, and 22, the second source / drain layer may include: a fifth conductive portion 55, a thirteenth bridging portion 513, a fourteenth bridging portion 514, a fourth gate line G4, and a turn-off signal line VGL. The fifth conductive portion 55 can be connected to the third bridging portion 43 via a via to connect to the first terminal of the fifth transistor T5. In the same pixel driving circuit group Pivz, the orthographic projections of the fifth conductive portions 55 located in different pixel driving circuit subgroups and adjacent in the first direction X are spaced apart on the substrate, and other adjacent fifth conductive portions 55 in the first direction X can be interconnected. The orthographic projection of the fifth conductive portion 55 on the substrate can at least partially overlap with the orthographic projection of the second active portion 92 on the substrate; for example, the orthographic projection of the fifth conductive portion 55 on the substrate can cover the orthographic projection of the second active portion 92 on the substrate. The fifth conductive portion 55 can block the second active portion 92 to reduce the influence of light on the characteristics of the second transistor T2. The orthographic projection of the fifth conductive portion 55 on the substrate can at least partially overlap with the orthographic projection of the first bridging portion 41 on the substrate. For example, the orthographic projection of the fifth conductive portion 55 on the substrate can cover the orthographic projection of the first bridging portion 41 on the substrate. The fifth conductive portion 55 can shield the interference of other signals to the first bridging portion 41, thereby improving the voltage stability of the driving transistor gate.

[0200] The thirteenth bridge section 513 can be connected to the tenth bridge section 410 via a via to connect to the second terminal of the sixth transistor T6. The fourteenth bridge section 514 can be connected to the sixth bridge section 46 via a via to connect to the first terminal of the fourth transistor T4.

[0201] The orthographic projection of the fourth gate line G4 onto the substrate and the orthographic projection of the turn-off signal line VGL onto the substrate can extend along the second direction Y. The fourth gate line G4 can be connected to the second bridging portion 42 via a via to connect to the gates of the ninth transistor T9 and the tenth transistor T10. The turn-off signal line VGL can be connected to the eleventh bridging portion 411 via a via to connect to the first terminal of the tenth transistor T10.

[0202] As shown in Figures 6 and 15, the third source / drain layer may include: a data line Da, a first power line VDD, a fifteenth bridging portion 615, and a sixteenth bridging portion 616. The orthographic projections of the data line Da and the first power line VDD on the substrate can extend along the second direction Y. The data line Da is used to provide the data signal terminal in Figure 1, and the first power line VDD is used to provide the first power terminal in Figure 1. The data line Da can be connected to the fourteenth bridging portion 514 through a via to connect the data signal terminal and the first terminal of the fourth transistor. There can be multiple first power lines VDD, and the orthographic projections of the multiple first power lines VDD on the substrate extend along the second direction Y and are spaced apart along the first direction X. One first power line VDD can be provided for each of two adjacent pixel driving circuit columns. The first power line VDD can be connected to the fifth conductive portion 55, which intersects with its orthographic projection on the substrate, through a via. In the same pixel driving circuit group Pivz, the first power line VDD may not be provided on two adjacent pixel driving circuit columns located in different pixel driving circuit subgroups. In the same pixel driving circuit group Pivz, the fifth conductive part 55 located in different pixel driving circuit subgroups and adjacent in the first direction X can be bridged by the sixteenth bridging part 616. The fifteenth bridging part 615 can be connected to the thirteenth bridging part 513 through a via.

[0203] As shown in Figures 6 and 15, the orthographic projection of the sixteenth bridging portion 616 on the substrate and the orthographic projection of the tenth active portion 910 on the substrate at least partially overlap. The sixteenth bridging portion 616 can shield the tenth active portion 910 from light to reduce the influence of light on the characteristics of the tenth transistor T10.

[0204] As shown in Figures 6 and 15, the first power line VDD can be connected via a via to the fifth conductive portion 55, which intersects with its orthographic projection on the substrate. The first power line VDD, the fifth conductive portion 55, and the third conductive portion 23 can form a grid structure. This arrangement can reduce the voltage difference of the first power line at different locations on the display panel, thereby improving the uniformity of the display panel.

[0205] In this exemplary embodiment, as shown in FIG6-22, in the same pixel driving circuit subgroup, two pixel driving circuits located in the same pixel driving circuit row are arranged at least partially mirror-symmetrically.

[0206] In this exemplary embodiment, as shown in FIG6-22, in the same pixel driving circuit row, the orthographic projection of the ninth active portion 79 on the substrate is located between the orthographic projection of the second gate line G2 on the substrate and the orthographic projection of the first reset signal line Re1 on the substrate. In the same pixel driving circuit row, the orthographic projection of the tenth active portion 910 on the substrate is located between the orthographic projection of the fifth gate line G5 on the substrate and the orthographic projection of the enable signal line EM on the substrate.

[0207] In this exemplary embodiment, as shown in FIG6-22, the orthographic projection of the fourth gate line G4 on the substrate is located between the orthographic projections of the two pixel driving circuit subgroups Pivz1 in the same pixel driving circuit group Pivz on the substrate. The orthographic projection of the turn-off signal line VGL on the substrate is located between the orthographic projections of the two pixel driving circuit subgroups Pivz1 in the same pixel driving circuit group Pivz on the substrate, and the orthographic projection of the turn-off signal line VGL on the substrate is located between the orthographic projection of the fourth gate line G4 on the substrate and the orthographic projection of the pixel driving circuit subgroup Pivz1 on the substrate. This exemplary embodiment can shield the coupling effect of the fourth gate line G4 on each node in the pixel driving circuit by using the turn-off signal line VGL.

[0208] In this exemplary embodiment, as shown in FIG6-22, the pixel driving circuit group can be compressed in the first direction X to free up space for setting the control circuit K. Accordingly, the distance between the orthographic projections of two adjacent pixel driving circuit columns Piv located in different pixel driving circuit groups Pivz on the substrate is less than the distance between the orthographic projections of two adjacent pixel driving circuit columns Piv located in different pixel driving circuit groups Pivz within the same pixel driving circuit group Pivz on the substrate. The distance between the orthographic projections of adjacent pixel driving circuit columns on the substrate can be understood as the distance between the orthographic projections of the channel regions of the two nearest transistors in adjacent pixel driving circuit columns on the substrate in the first direction.

[0209] In this exemplary embodiment, as shown in FIG6-22, the sheet resistance of any one of the first source / drain layer, the second source / drain layer, and the third source / drain layer is less than the sheet resistance of any one of the first gate layer, the second gate layer, and the third gate layer. This exemplary embodiment places the first gate line G1 in the first source / drain layer, thereby reducing the self-resistance of the first gate line G1, which in turn reduces the voltage drop across the first gate line G1 and improves the uniformity of the display panel.

[0210] In this exemplary embodiment, as shown in FIG6-22, the second bridging portion 42 and the turn-off signal line VGL are located on different conductive layers, and the orthographic projection of the turn-off signal line VGL on the substrate and the orthographic projection of the second bridging portion 42 on the substrate at least partially overlap. The turn-off signal line VGL can shield the second bridging portion 42. It should be understood that in other exemplary embodiments, the second bridging portion 42 may also be located at other positions.

[0211] It should be noted that, as shown in Figures 6, 21, and 22, the chamfered black squares drawn on the side of the first source / drain layer away from the substrate represent vias connecting the first source / drain layer to other layers facing the substrate; the black squares drawn on the side of the second source / drain layer away from the substrate represent vias connecting the second source / drain layer to other layers facing the substrate; and the black circles drawn on the side of the third source / drain layer away from the substrate represent vias connecting the third source / drain layer to other layers facing the substrate. Vias at different positions can penetrate different insulating layers.

[0212] Figure 23 shows a partial cross-sectional view of the display panel shown in Figure 6, cut along the dashed line AA. The display panel may further include a buffer layer 101, a second insulating layer 102, a third insulating layer 103, a fourth insulating layer 104, a fifth insulating layer 105, a first dielectric layer 106, a passivation layer 107, a first planarization layer 108, and a second planarization layer 109. The substrate 100, shielding layer, buffer layer 101, first active layer, second insulating layer 102, first gate layer, third insulating layer 103, second gate layer, fourth insulating layer 104, second active layer, fifth insulating layer 105, third gate layer, first dielectric layer 106, first source / drain layer, passivation layer 107, first planarization layer 108, second source / drain layer, second planarization layer 109, and third source / drain layer are sequentially stacked. The buffer layer 101, the second insulating layer 102, the third insulating layer 103, the fourth insulating layer 104, and the fifth insulating layer 105 can be single-layer or multi-layer structures, and the materials of the buffer layer 101, the second insulating layer 102, the third insulating layer 103, the fourth insulating layer 104, and the fifth insulating layer 105 can be at least one of silicon nitride, silicon oxide, and silicon oxynitride; the first dielectric layer 106 can be a silicon nitride layer; the materials of the first planarization layer 108 and the second planarization layer 109 can be organic materials, such as polyimide (PI), polyethylene terephthalate (PET), polyethylene naphthalate (PEN), silicon-glass bonded structure (SOG), etc. The passivation layer 107 can be a silicon oxide layer. The substrate 100 can include a glass substrate, a barrier layer, and a polyimide layer stacked sequentially, and the barrier layer can be an inorganic material. The materials of the first gate layer, second gate layer, and third gate layer can be molybdenum, aluminum, copper, titanium, niobium, or alloys thereof, or molybdenum / titanium alloys or stacked conductive layers. The materials of the first source / drain layer, second source / drain layer, and third source / drain layer can include metallic materials, for example, molybdenum, aluminum, copper, titanium, niobium, or alloys thereof, or molybdenum / titanium alloys or stacked layers, or titanium / aluminum / titanium stacked conductive layers. The sheet resistance of any one of the first source / drain layer, second source / drain layer, and third source / drain layer can be less than the sheet resistance of any one of the first gate layer, second gate layer, and third gate layer.

[0213] As shown in Figures 24-27, Figure 24 is a structural layout diagram of another exemplary embodiment of the display panel of the present disclosure, Figure 25 is a structural layout diagram of the first active layer in the display panel shown in Figure 24, Figure 26 is a structural layout diagram of the second gate layer in the display panel shown in Figure 24, and Figure 27 is a structural layout diagram of the first source / drain layer in the display panel shown in Figure 24.

[0214] The display panel shown in Figure 24 differs from the display panel shown in Figure 6 in the structure of the first active layer, the second gate layer, and the first source / drain layer. As shown in Figures 24-27, the twenty-first active portion 721 is located on one side of the ninth active portion 79 in the first direction X; the second gate layer may further include a first sub-gate line G11; the first gate line G1 in Figure 13 forms the second sub-gate line G12 in Figure 27, and the first source / drain layer also includes a protrusion 401, which is connected to the side of the second sub-gate line G12 facing the second bridging portion 42. The second sub-gate line G12 is connected to the first sub-gate line G11 through a via in the protrusion 401. In this exemplary embodiment, the first gate line G1 includes a first sub-gate line G11 and a second sub-gate line G12. The orthographic projection of the first sub-gate line G11 on the substrate and the orthographic projection of the second sub-gate line G12 on the substrate both extend along the first direction. The first gate line G1 in the multilayer structure has a smaller resistance, thereby improving the uniformity of the display panel.

[0215] As shown in Figures 24-27, the orthographic projection of the protrusion 401 on the substrate and the orthographic projection of at least a portion of the structure of the second bridging portion 42 on the substrate are located on either side of the orthographic projection of the ninth active portion 79 on the substrate in the first direction X. It should be understood that in other exemplary embodiments, the first sub-gate line G11 and the second sub-gate line G12 may also be connected via vias in the bezel area of ​​the display panel; correspondingly, the first source / drain layer may not have the protrusion 401.

[0216] In addition, the display panel shown in Figure 24 may also include a second source / drain layer and a third source / drain layer with the same structure as the display panel shown in Figure 6.

[0217] It should be understood that in other exemplary embodiments, the fourth gate line G4 and the turn-off signal line VGL may also be located in other positions. For example, as shown in Figures 32 and 33, Figure 32 is a structural layout diagram of another exemplary embodiment of the display panel of this disclosure, and Figure 33 is a partial structural layout diagram of the display panel shown in Figure 32. The fourth gate line G4 and the turn-off signal line VGL may also be located in the third source / drain layer. Correspondingly, the fifth conductive portions 55 spaced apart in the first direction may be connected in the same layer, and the sixteenth bridging portion 616 may not be provided in the third source / drain layer.

[0218] It should be noted that the scale of the accompanying drawings in this disclosure can be used as a reference in actual processes, but is not limited thereto. For example, the aspect ratio of the channels, the thickness and spacing of each film layer, and the width and spacing of each signal line can be adjusted according to actual needs. The number of pixels in the display panel and the number of sub-pixels in each pixel are not limited to the quantities shown in the figures. The accompanying drawings described in this disclosure are only schematic diagrams of the structure. In addition, the terms "first," "second," etc., are only used to define different structural names and do not have a specific order meaning. The same structural layer can be formed by the same patterning process. In this exemplary embodiment, the orthographic projection of a certain structure on the substrate extends along a certain direction, which can be understood as the orthographic projection of the structure on the substrate extending in a straight line or bending along that direction.

[0219] It should be understood that in other exemplary embodiments, the control circuit may also be used to respond to a control signal to connect the gate of the second transistor and the first gate line G1, or to respond to a control signal to disconnect the gate of the second transistor T2 from the first gate line G1. For example, as shown in FIG28, which is a schematic diagram of another exemplary embodiment of the display panel of this disclosure, the control circuit K may not have a tenth transistor T10, and correspondingly, the display panel may not have a turn-off signal line. Furthermore, the ninth transistor may be a P-type transistor or an N-type transistor.

[0220] As shown in Figure 28, the control circuit may further include a first capacitor C1. The first electrode of the first capacitor C1 is connected to the constant voltage power supply line VX, and the second electrode of the first capacitor C1 is connected to the second electrode of the ninth transistor T9. The first capacitor C1 can maintain a stable potential at the second electrode of the ninth transistor T9 during the period when the fourth gate line G4 is off, and can prevent large voltage fluctuations at the second electrode of the ninth transistor T9 due to leakage current. The constant voltage power supply line VX can be a DC signal. For example, the constant voltage power supply line VX can be one of the first power supply line VDD, an initial signal line (e.g., one of the first initial signal line Vinit1, the second initial signal line Vinit2, or the third initial signal line Vinit3), a turn-off signal line VGL, or a high-voltage power supply line VGH.

[0221] It should be understood that in other exemplary embodiments, the control circuit may have other structures. For example, as shown in FIG29, which is a schematic diagram of another exemplary embodiment of the display panel of this disclosure, FIG29 only illustrates one pixel driving circuit.

[0222] As shown in Figure 29, the ninth transistor T9, the tenth transistor T10, and the second transistor T2 can be P-type transistors. When the signal on the fourth gate line G4 is at the first level, the pixel driving circuit, under the control of the first gate line G1, the additional first gate line G1-1, and the control circuit, drives the corresponding light-emitting device to maintain its original brightness or refresh its brightness. The signals on the first gate line G1 and the additional first gate line G1-1 have opposite polarities. The orthographic projections of the first gate line G1 and the additional first gate line G1-1 onto the substrate can extend along a first direction, and the orthographic projection of the fourth gate line G4 onto the substrate can extend along a second direction.

[0223] When the signal on the fourth gate line G4 is at the second level, the second transistor T2 is disconnected under the control of the signal on the fourth gate line G4 or the high-voltage power supply line VGH, and the pixel driving circuit drives the corresponding light-emitting device to maintain its original brightness. The second level can be a high level.

[0224] As shown in Figure 29, when the signal of the fourth gate line G4 is at the first level, and the first gate line G1 is at the first level during the first reset phase and data write phase of a working frame of the pixel driving circuit, the control circuit provides the signal of the fourth gate line G4 to the gate of the second transistor T2 during the first reset phase and data write phase of a working frame of the pixel driving circuit. The second transistor T2 is turned on under the control of the signal of the fourth gate line G4, and the pixel driving circuit drives the corresponding light-emitting device to refresh the brightness in this working frame. The first level can be a low level.

[0225] When the signal of the fourth gate line G4 is at the first level and the first gate line G1 is at the second level in one working frame of the pixel driving circuit, the control circuit provides the signal of the high voltage power supply line VGH to the gate of the second transistor T2. The second transistor T2 is turned off under the control of the signal of the high voltage power supply line, and the pixel driving circuit drives the corresponding light-emitting device to maintain the original brightness.

[0226] In the equivalent circuit diagram shown in Figure 29, the first level of the signal on the fourth gate line G4 can be the control signal for refreshing the brightness, and the second level can be the control signal for maintaining the brightness. In the first reset stage and the data writing stage of a working frame of the pixel driving circuit, the first level of the signal on the first gate line G1 is the control signal for refreshing the brightness, and the second level is the control signal for maintaining the brightness.

[0227] In other exemplary embodiments, the pixel driving circuit may also have other structures. For example, the pixel driving circuit may include a driving transistor and a switching transistor, with the second electrode of the switching transistor connected to the gate of the driving transistor. A control circuit is connected to the switching transistor. As long as the control circuit can control the switching transistor's on / off state, it can achieve control of the local refresh rate of the display panel. The connection of the second electrode of the switching transistor to the gate of the driving transistor may include: the second electrode of the switching transistor being directly electrically connected to the gate of the driving transistor; or the second electrode of the switching transistor being connected to the gate of the driving transistor through a capacitor, i.e., the two electrodes of the capacitor are respectively connected to the second electrode of the switching transistor and the gate of the driving transistor.

[0228] In this exemplary embodiment, there can be one or more switching transistors. When there are multiple switching transistors, there can also be multiple control circuits. The control circuits and switching transistors are configured accordingly, and the control circuits are used to control the on / off state of their corresponding switching transistors.

[0229] For example, Figure 30 shows a schematic diagram of another exemplary embodiment of the display panel of this disclosure. The plurality of control circuits may include a first control circuit 601 to a fourth control circuit 604. The gate of the first transistor T1 is connected to the first control circuit 601, the gate of the second transistor T2 is connected to the second control circuit 602, the gate of the fourth transistor T4 is connected to the third control circuit 603, and the gate of the eleventh transistor T11 is connected to the fourth control circuit 604. The structure of the first control circuit 601 to the fourth control circuit 604 can be the structure of the control circuit described in any of the above embodiments, and the circuit structures of the first control circuit 601 to the fourth control circuit 604 can be the same or different. In an exemplary embodiment, the first control circuit 601 to the fourth control circuit 604 can be the same control circuit connected to the control gates of the first transistor T1, the second transistor T2, the fourth transistor T4, and the eleventh transistor T11, respectively.

[0230] For example, as shown in Figure 31, which is a structural schematic diagram of another exemplary embodiment of the display panel of this disclosure, the plurality of control circuits may include a first control circuit 601 to a third control circuit 603, and the pixel driving circuit Pi may include a first transistor T1, a second transistor T2, a driving transistor T3, a fourth transistor T4, a fifth transistor T5, and a capacitor C; wherein, the gate of the first transistor T1 is connected to the first control circuit 601, the first terminal of the first transistor T1 is connected to the first low-voltage power supply line VSS1, and the second terminal of the first transistor T1 is connected to the third node N3; the gate of the second transistor T2 is connected to the second control circuit 602, the first terminal of the second transistor T2 is connected to the second low-voltage power supply line VSS2, and the second terminal of the second transistor T2 is connected to the first node N3; Point N1 is connected; the gate of the driving transistor is connected to the first node N1, the first electrode of the driving transistor is connected to the second node N2, and the second electrode of the driving transistor is connected to the third node N3; the gate of the fourth transistor T4 is connected to the third control circuit 603, the first electrode of the fourth transistor T4 is connected to the data line Da, and the second electrode of the fourth transistor T4 is connected to the first node N1; the gate of the fifth transistor T5 is connected to the enable signal line EM, the first electrode of the fifth transistor T5 is connected to the first power supply line VDD, and the second electrode of the fifth transistor T5 is connected to the second node N2; the first electrode of the capacitor C is connected to the first node N1, and the second electrode of the capacitor C is connected to the third node N3. The structure of the first control circuit 601 to the third control circuit 603 can be the structure of the control circuit described in any of the above embodiments, and the circuit structures of the first control circuit 601 to the third control circuit 603 can be the same or different; in an exemplary embodiment, the first control circuit 601 to the third control circuit 603 can be the same control circuit connected to the gates of the first transistor T1, the second transistor T2, and the fourth transistor T4 respectively. As can be seen from the above, the threshold compensation of the gate of the driving transistor T3 can be controlled by controlling the gate of the transistor connected to the driving transistor T3 in the pixel driving circuit Pi, thereby controlling the refresh of pixels in a local area of ​​the display panel.

[0231] For example, as shown in Figure 31, in this embodiment of the present disclosure, a light-emitting control transistor can be added between the N3 node and the anode of the light-emitting device, thereby isolating the influence of the voltage of the N3 node on the anode of the light-emitting device before light emission. Other working processes are the same as those in the above embodiments, and will not be repeated here.

[0232] Figure 34 is a schematic diagram of another exemplary embodiment of the display panel of this disclosure. Figure 34 illustrates the adjustment method of the local refresh rate of the display panel using nine display areas as an example. The display panel includes nine display areas P1-P9. Each display area includes multiple pixel driving circuits located in the same pixel driving circuit group and in the same pixel driving circuit row. For example, each display area may include one row and four columns of pixel driving circuits, and a control circuit is correspondingly provided in each display area. Accordingly, the display panel may be provided with three fourth gate lines G41, G42, and G43, and three first gate lines G11, G12, and G13.

[0233] The fourth gate line G41 controls the on / off state of the ninth transistor T9 in display areas P1, P4, and P7 along the column direction; the fourth gate line G42 controls the on / off state of the ninth transistor T9 in display areas P2, P5, and P8 along the column direction; and the fourth gate line G43 controls the on / off state of the ninth transistor T9 in display areas P3, P6, and P9 along the column direction. If the fourth gate lines G41 and G43 control the ninth transistor T9 in display areas P1, P4, P7, P3, P6, and P9 to be off, then the second transistor T2 in display areas P1, P4, P7, P3, P6, and P9 will be off. At this time, regardless of whether the first gate lines G11, G12, and G13 in display areas P1, P4, P7, P3, P6, and P9 output on or off signals, display areas P1, P4, P7, P3, P6, and P9 will not be refreshed, and the corresponding display areas P1, P4, P7, P3, P6, and P9 can achieve low-frequency display. If the fourth gate line G42 controls the ninth transistor T9 in display areas P2, P5, and P8 to turn on, then the second transistor T2 in display areas P2, P5, and P8 can receive signals from the first gate lines G11, G12, and G13 to control pixel scanning. At this time, the refresh frequency of display areas P2, P5, and P8 can be controlled by controlling the frequency of the gate drive signals output by the first gate lines G11, G12, and G13. For example, if the first gate line G11 outputs a valid level every frame, then display area P2 will refresh every frame; if the first gate line G12 outputs a valid level every three frames, then display area P5 will refresh every three frames. This method controls the refresh frequency of different display areas by controlling the frequency of the valid levels output by the fourth and first gate lines.

[0234] The display panel can also control the refresh rate of local areas through other driving methods. For example, the frequency of the effective level output of each first gate line can be the same. When the display panel scans each row of pixel driving circuits, the fourth gate line can select the on / off state of the ninth transistor T9 in the control circuit connected to it, so as to control whether the pixel driving circuits of different areas write data signals. For example, when scanning display areas P1, P2, and P3, the fourth gate line G41 can control the ninth transistor in display area P1 to turn on, the fourth gate line G42 can control the ninth transistor in display area P2 to turn on, and the fourth gate line G43 can control the ninth transistor in display area P3 to turn off, thereby controlling the refresh of display areas P1 and P2, while display area P3 does not refresh; when scanning display areas P4, P5, and P6, the fourth gate line G41 can control the ninth transistor in display area P4 to turn off, the fourth gate line G42 can control the ninth transistor in display area P5 to turn on, and the fourth gate line G43 can control the ninth transistor in display area P6 to turn off, thereby controlling the refresh of display area P5, while display areas P4 and P6 do not refresh.

[0235] Furthermore, the voltage of the low-level constant voltage signal in the low-frequency display area can be greater than the voltage of the same low-level constant voltage signal in the high-frequency display area; the voltage of the high-level constant voltage signal in the low-frequency display area can be less than the voltage of the same high-level constant voltage signal in the high-frequency display area. This setting can further reduce the power consumption of the display panel. The low-level constant voltage signal may include signals on the first initial signal line Vinit1, the second initial signal line Vinit2, the second power supply terminal VSS, and the turn-off signal line VGL; the high-level constant voltage signal may include signals on the third initial signal line Vinit3, the first power supply line VDD, and the high-voltage power supply line VGH.

[0236] The pixel driving circuit and control circuit in Figure 34 can be any of the pixel driving circuits and control circuits mentioned above. VGL / VGH in Figure 34 can be the shutdown signal line VGL in Figure 4 or the high-voltage power supply line VGH in Figure 29.

[0237] This exemplary embodiment also provides a display device, which includes the display panel described above. The display device can be a mobile phone, tablet computer, television, or other display device.

[0238] Other embodiments of this disclosure will readily occur to those skilled in the art upon consideration of the specification and practice of the disclosure herein. This application is intended to cover any variations, uses, or adaptations of this disclosure that follow the general principles of this disclosure and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this disclosure are indicated by the claims.

[0239] Other embodiments of this disclosure will readily occur to those skilled in the art upon consideration of the specification and practice of the disclosure herein. This application is intended to cover any variations, uses, or adaptations of this disclosure that follow the general principles of this disclosure and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this disclosure are indicated by the claims.

[0240] It should be understood that this disclosure is not limited to the precise structures described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of this disclosure is defined only by the appended claims.

Claims

1. A display panel, wherein, The display panel includes: Substrate; Multiple pixel driving circuits are arranged in an array along a first direction and a second direction, with the orthographic projections of the multiple pixel driving circuits on the substrate intersecting each other. The multiple pixel driving circuits distributed in the first direction form a pixel driving circuit row. The pixel driving circuit includes a driving transistor and a second transistor, wherein the first terminal of the second transistor is connected to the gate of the driving transistor. A first gate line, whose orthogonal projection on the substrate extends along the first direction, is used to provide gate drive signals to a plurality of second transistors located in the same pixel drive circuit row; A control circuit is provided, and at least one pixel driving circuit is correspondingly provided; The control circuit is connected to the gate of the second transistor and the first gate line in the corresponding pixel driving circuit. The control circuit is used to respond to a control signal to connect the gate of the second transistor and the first gate line, or to respond to a control signal to disconnect the gate of the second transistor from the first gate line.

2. The display panel according to claim 1, wherein, The second terminal of the second transistor is connected to the second terminal of the driving transistor.

3. The display panel according to claim 1, wherein, The control circuit is also used to respond to a control signal to transmit a turn-off signal to the gate of the second transistor.

4. The display panel according to any one of claims 1-3, wherein, The control circuit and a portion of the pixel driving circuit in the same row of pixel driving circuits are configured accordingly.

5. The display panel according to any one of claims 1-3, wherein, The plurality of pixel driving circuits distributed in the second direction form a pixel driving circuit column, and one or more adjacent pixel driving circuit columns form a pixel driving circuit group. The display panel includes a plurality of pixel driving circuit groups, and the pixel driving circuit groups are correspondingly provided with a plurality of control circuits; In the same pixel driving circuit group: the control circuit and the pixel driving circuit located in the same pixel driving circuit row are correspondingly arranged, and different control circuits correspond to different pixels. The pixel driving circuit in the pixel driving circuit row.

6. The display panel according to claim 5, wherein, The display panel also includes: The fifth gate line includes fifth gate line segments extending along the first direction and spaced apart along the first direction. The fifth gate line segments are correspondingly disposed with the pixel driving circuit group. A portion of the structure of the fifth gate line segment is used to form the gate of the second transistor located in the same pixel driving circuit row in the pixel driving circuit group corresponding to it. The control circuit is connected to the gate of the second transistor in its corresponding pixel driving circuit via the fifth gate segment.

7. The display panel according to claim 3, wherein, The display panel further includes: a shutdown signal line and a fourth gate line, and the control circuit includes: The ninth transistor has its first terminal connected to the first gate line, its second terminal connected to the gate of the second transistor, and its gate connected to the fourth gate line. The tenth transistor has its first terminal connected to the turn-off signal line, its second terminal connected to the gate of the second transistor, and its gate connected to the fourth gate line. The conduction signals of the ninth transistor and the tenth transistor have opposite polarities.

8. The display panel according to claim 5, wherein, The pixel driving circuit group includes two pixel driving circuit subgroups; In the corresponding pixel driving circuit group and the control circuit, the orthographic projection of the control circuit on the substrate is located between the orthographic projections of the two pixel driving circuit subgroups on the substrate.

9. The display panel according to claim 7, wherein, The pixel driving circuit also includes a first transistor and a fourth transistor; The first terminal of the first transistor is connected to the first initial signal line, the second terminal is connected to the second terminal of the driving transistor, and the gate is connected to the first reset signal line. The first terminal of the fourth transistor is connected to the data line, the second terminal is connected to the first terminal of the driving transistor, and the gate is connected to the second gate line. The display panel also includes: A first active layer is located on one side of the substrate. The first active layer includes a ninth active portion, which is used to form the channel region of the ninth transistor. In the same pixel driving circuit row, the ninth active portion is on the substrate. The projection is located between the orthogonal projection of the second gate line on the substrate and the orthogonal projection of the first reset signal line on the substrate.

10. The display panel according to claim 7, wherein, The pixel driving circuit also includes a fifth transistor; The first terminal of the fifth transistor is connected to the first power supply line, the second terminal is connected to the first terminal of the driving transistor, and the gate is connected to the enable signal line. The display panel also includes: The second active layer is located on one side of the substrate. The second active layer includes a tenth active portion, which is used to form the channel region of the tenth transistor. A third gate layer is located on the side of the second active layer away from the substrate. The third gate layer includes a fifth gate line, a portion of which is used to form the gate of the second transistor. In the same pixel driving circuit row, the orthographic projection of the tenth active part on the substrate is located between the orthographic projection of the fifth gate line on the substrate and the orthographic projection of the enable signal line on the substrate.

11. The display panel according to claim 5, wherein, The display panel further includes: a fourth gate line, the fourth gate line extending along the second direction by its orthogonal projection on the substrate. The fourth gate line is used to provide control signals to multiple control circuits corresponding to the same pixel driving circuit group.

12. The display panel according to claim 11, wherein, The pixel driving circuit group includes two pixel driving circuit subgroups; The orthographic projection of the fourth gate line on the substrate lies between the orthographic projections of the two pixel driving circuit subgroups in the same pixel driving circuit group on the substrate.

13. The display panel according to claim 12, wherein, The control circuit is also used to respond to a control signal to transmit a turn-off signal to the gate of the second transistor; The display panel further includes a shutdown signal line, the shutdown signal line extending along the second direction by its orthogonal projection on the substrate, and the shutdown signal line being used to provide shutdown signals to multiple control circuits corresponding to the same pixel driving circuit group. The orthogonal projection of the shutdown signal line onto the substrate is located in the same pixel driving circuit. The two pixel driving circuit subgroups in the group are positioned between the orthographic projections on the substrate, and the orthographic projection of the turn-off signal line on the substrate is located between the orthographic projection of the fourth gate line on the substrate and the orthographic projection of the pixel driving circuit subgroup on the substrate.

14. The display panel according to claim 8, wherein, The distance between the orthographic projections of two adjacent pixel driving circuit columns located in different pixel driving circuit groups on the substrate is less than the distance between the orthographic projections of two adjacent pixel driving circuit columns located in the same pixel driving circuit group but in different pixel driving circuit subgroups on the substrate.

15. The display panel according to claim 13, wherein, The display panel also includes: A first source / drain layer is located on one side of the substrate. The first source / drain layer includes a first bridging portion, which is connected to the gate of the driving transistor and the first electrode of the second transistor through vias. The second source / drain layer is located on the side of the first source / drain layer away from the substrate, and the second source / drain layer includes the fourth gate line and the turn-off signal line.

16. The display panel according to any one of claims 1-3, wherein, The display panel also includes: A first source / drain layer is located on one side of the substrate. The first source / drain layer includes a first bridging portion, which is connected to the gate of the driving transistor and the first electrode of the second transistor through vias. The first source / drain layer includes the first gate line.

17. The display panel according to any one of claims 1-3, wherein, The pixel driving circuit also includes a capacitor, the first electrode of which is connected to the gate of the driving transistor, and the second electrode of which is connected to the first power supply line. The first gate line includes a first sub-gate line and a second sub-gate line, and the orthographic projection of the first sub-gate line on the substrate and the orthographic projection of the second sub-gate line on the substrate both extend along the first direction; The display panel also includes: A second gate layer is located on one side of the substrate. The second gate layer includes a third conductive portion and a first sub-gate line. The third conductive portion is used to form the second electrode of the capacitor. The first source / drain layer is located on the side of the second gate layer opposite to the substrate. The first source-drain layer includes a first bridging portion, which is connected to the gate of the driving transistor and the first electrode of the second transistor through vias. The first source-drain layer also includes a second sub-gate line. The first sub-gate line and the second sub-gate line are connected by vias.

18. The display panel according to claim 17, wherein, The control circuit includes: The ninth transistor has its first terminal connected to the first gate line, its second terminal connected to the gate of the second transistor, and its gate connected to the fourth gate line. The tenth transistor has its first terminal connected to the turn-off signal line, its second terminal connected to the gate of the second transistor, and its gate connected to the fourth gate line. The display panel also includes: A first active layer is located between the substrate and the second gate layer. The first active layer includes a ninth active portion, which is used to form the channel region of the ninth transistor. The first source / drain layer further includes: The second bridging portion is connected to the gate of the tenth transistor and the gate of the ninth transistor respectively through vias; A protrusion is connected to the side of the second sub-gate line facing the second bridging portion, and the second sub-gate line is connected to the first sub-gate line through the through hole of the protrusion; Wherein, the orthographic projection of the protrusion on the substrate and the orthographic projection of at least a portion of the second bridging portion on the substrate are located on both sides of the orthographic projection of the ninth active portion on the substrate in the first direction.

19. The display panel according to claim 7, wherein, The display panel also includes: The second bridging portion is connected to the gate of the tenth transistor and the gate of the ninth transistor respectively through vias; The second bridging portion and the shutdown signal line are located in different conductive layers, and the orthographic projection of the shutdown signal line on the substrate and the orthographic projection of the second bridging portion on the substrate at least partially overlap.

20. The display panel according to any one of claims 1-3, wherein, The pixel driving circuit is connected to a first power line, and the first power line is used to provide a high-level signal to the pixel driving circuit. The control circuit includes a tenth transistor, the first terminal of which is connected to a turn-off signal line, the second terminal of which is connected to the gate of the second transistor, and the gate is connected to a fourth gate line. The display panel also includes: The second active layer is located on one side of the substrate. The second active layer includes a tenth active portion, which is used to form the channel region of the tenth transistor. The second source / drain layer is located on the side of the second active layer away from the substrate. The second source / drain layer includes a fifth conductive portion, which is connected to the first power line. In the same pixel driving circuit group, the orthogonal projections of the fifth conductive portions located in different pixel driving circuit subgroups and adjacent in the first direction are spaced apart on the substrate. The third source / drain layer is located on the side of the second source / drain layer away from the substrate. The third source / drain layer includes a sixteenth bridging portion. In the same pixel driving circuit group, the fifth conductive portions located in different pixel driving circuit subgroups and adjacent in the first direction are bridged by the sixteenth bridging portion. Wherein, the orthographic projection of the sixteenth bridging portion on the substrate and the orthographic projection of the tenth active portion on the substrate at least partially overlap.

21. The display panel according to claim 20, wherein, The third source / drain layer includes: The first power line, whose orthogonal projection on the substrate extends along the second direction, is connected via a via to the fifth conductive portion intersecting with its orthogonal projection on the substrate.

22. The display panel according to claim 8, wherein, The pixel driving circuit subgroup includes two pixel driving circuit columns; In the same subgroup of pixel driving circuits, two pixel driving circuits located in the same row of pixel driving circuits are arranged at least partially mirror-symmetrically.

23. The display panel according to any one of claims 1-3, wherein, The display panel further includes a light-emitting unit, and the pixel driving circuit further includes a first transistor, a fifth transistor, a seventh transistor, and an eighth transistor; The first terminal of the first transistor is connected to the first initial signal line, the second terminal is connected to the second terminal of the driving transistor, and the gate is connected to the first reset signal line. The first terminal of the fifth transistor is connected to the first power supply line, the second terminal is connected to the first terminal of the driving transistor, and the gate is connected to the enable signal line. The first electrode of the seventh transistor is connected to the second initial signal line, the second electrode is connected to the first electrode of the light-emitting unit, and the gate is connected to the second reset signal line. The first terminal of the eighth transistor is connected to the third initial signal line, and the second terminal is connected to the first terminal of the driving transistor. Wherein, the orthographic projection of the first initial signal line on the substrate and the orthographic projection of the second reset signal line in the adjacent previous row pixel driving circuit on the substrate at least partially overlap; The orthographic projection of the second initial signal line on the substrate and the orthographic projection of the first reset signal line in the adjacent next row pixel driving circuit on the substrate at least partially overlap; The orthographic projection of the third initial signal line on the substrate and the orthographic projection of the enable signal line in the current pixel driving circuit on the substrate at least partially overlap.

24. The display panel according to any one of claims 1-3, wherein, The display panel further includes a light-emitting unit, and the pixel driving circuit further includes: The first transistor has a first terminal connected to a first initial signal line and a second terminal connected to the second terminal of the driving transistor. The fourth transistor has its first terminal connected to the data line and its second terminal connected to the first terminal of the driving transistor. The fifth transistor has its first terminal connected to the first power supply line and its second terminal connected to the first terminal of the driving transistor. The sixth transistor has its first electrode connected to the second electrode of the driving transistor, and the second electrode connected to the first electrode of the light-emitting unit. The seventh transistor has its first electrode connected to the second initial signal line and its second electrode connected to the first electrode of the light-emitting unit. The eighth transistor has its first terminal connected to the third initial signal line and its second terminal connected to the first terminal of the driving transistor. The capacitor has a first electrode connected to the gate of the driving transistor and a second electrode connected to the first power supply line. The control circuit includes: The ninth transistor has its first terminal connected to the first gate line and its second terminal connected to the second crystal. The gate of the transistor; The tenth transistor has its first terminal connected to the turn-off signal line and its second terminal connected to the gate of the second transistor. Among them, the first transistor, the driving transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor, the eighth transistor, and the ninth transistor are P-type transistors, and the second transistor and the tenth transistor are N-type transistors.

25. The display panel according to any one of claims 1-3, wherein, The display panel includes P-type transistors and N-type transistors, and the display panel further includes: A first active layer is located on one side of the substrate, and a portion of the structure of the first active layer is used to form the channel region of the P-type transistor in the pixel driving circuit. A first gate layer is located on the side of the first active layer away from the substrate, and a portion of the structure of the first gate layer is used to form the gate of the P-type transistor in the pixel driving circuit. The second gate layer is located on the side of the first gate layer away from the substrate, and a portion of the structure of the second gate layer is used to form the bottom gate of the N-type transistor in the pixel driving circuit. The second active layer is located on the side of the second gate layer away from the substrate, and a portion of the structure of the second active layer is used to form the channel region of the N-type transistor in the pixel driving circuit. The third gate layer is located on the side of the second active layer away from the substrate, and a portion of the structure of the third gate layer is used to form the top gate of the N-type transistor in the pixel driving circuit. The first source / drain layer is located on the side of the third gate layer opposite to the substrate, and a portion of the structure of the first source / drain layer is used to form a bridging portion connecting different transistors.

26. A display panel, wherein, The display panel includes: Substrate; Multiple pixel driving circuits, wherein the orthographic projections of the multiple pixel driving circuits on the substrate are distributed in an array along a first direction and a second direction, the first direction and the second direction intersecting; The pixel driving circuit includes a driving transistor and a second transistor, wherein the first terminal of the second transistor is connected to the gate of the driving transistor, and the second terminal of the second transistor is connected to the second terminal of the driving transistor. The data line, whose orthogonal projection on the substrate extends along the second direction, the data... The data line is used to provide data signals to the pixel driving circuit; A control circuit is provided, and at least one pixel driving circuit is correspondingly provided; the control circuit is used to control the switching on and off of the gate of the driving transistor and the second terminal of the driving transistor according to a control signal; A fourth gate line, the fourth gate line extending along the second direction by its orthogonal projection on the substrate, the fourth gate line being used to provide the control signal to the control circuit.

27. A display panel, wherein, The display panel includes: Substrate; Multiple pixel driving circuits, wherein the orthographic projections of the multiple pixel driving circuits on the substrate are distributed in an array along a first direction and a second direction, the first direction and the second direction intersecting; The pixel driving circuit includes a driving transistor and a second transistor, wherein the first terminal of the second transistor is connected to the gate of the driving transistor, and the second terminal of the second transistor is connected to the second terminal of the driving transistor. A data line, whose orthogonal projection on the substrate extends along the second direction, is used to provide data signals to the pixel driving circuit. A control circuit is provided, and at least one pixel driving circuit is correspondingly provided; the control circuit is used to control the switching on and off of the gate of the driving transistor and the second terminal of the driving transistor according to a control signal; The fourth gate line is used to provide the control signal to the control circuit. The conductive layer on which the fourth gate line is located is located on the side of the conductive layer away from the substrate of the data line, or the fourth gate line and the data line are located on the same conductive layer.

28. A display device, wherein, The display device includes the display panel according to any one of claims 1-27.

Images