Display substrate and display apparatus

Abstract

A display substrate and a display apparatus, comprising: a substrate (11), a semiconductor layer (12), a gate metal layer (13), and a source / drain electrode layer (14). The semiconductor layer, the gate metal layer, and the source / drain electrode layer form multiple thin film transistors. The source / drain electrode layer (14) comprises a first light-emitting control signal line (207), and the gate metal layer (13) comprises a second light-emitting control signal line (209). The first light-emitting control signal line (207) and the second light-emitting control signal line (209) are connected to gate electrodes of different thin film transistors.

Description

Display substrate and display device

[0001] The present application claims priority to the Chinese patent application No. 202410696412.7, filed on May 31, 2024, and entitled "A display substrate and display device", the contents of which are to be understood as incorporated herein by reference. TECHNICAL FIELD

[0002] The embodiments of the present disclosure relate to, but are not limited to, the technical field of display, and in particular, to a display substrate and display device. BACKGROUND

[0003] In the current 7T1C (7 Thin Film Transistors, TFT, 1 capacitor C) pixel driving circuit, the circuit structure diagram of the 7T1C pixel driving circuit can be seen from FIG. 1. In the reset stage, the first light-emitting control transistor T5 and the second light-emitting control transistor T6 are in the off state, and the first reset transistor T4 is turned on to reset the gate of the driving transistor T2 (N2 node). When resetting the N2 node, the N1 node is easily coupled, resulting in display defects in the display product.

[0004] SUMMARY

[0005] The following is a summary of the subject matter of the detailed description of the present disclosure. This summary is not intended to limit the scope of protection of the claims.

[0006] An exemplary embodiment of the present disclosure provides a display substrate, comprising:

[0007] a substrate, a semiconductor layer, a gate metal layer, a source-drain electrode layer;

[0008] The semiconductor layer, the gate metal layer, and the source-drain electrode layer form a plurality of thin film transistors;

[0009] The source-drain electrode layer includes a first light-emitting control signal line, and the gate metal layer includes a second light-emitting control signal line;

[0010] The first light-emitting control signal line and the second light-emitting control signal line are connected to the gates of different thin film transistors;

[0011] The gate metal layer includes a first gate metal layer, a third insulating layer, and a second gate metal layer, and the source-drain electrode layer includes a first source-drain electrode layer, a fourth insulating layer, and a second source-drain electrode layer;

[0012] The first light-emitting control signal line is disposed in the first source-drain electrode layer, and the second light-emitting control signal line is disposed in the first gate metal layer;

[0013] The third insulating layer is arranged on a side of the first gate metal layer away from the substrate, and the second gate metal layer is arranged on a side of the third insulating layer away from the substrate.

[0014] The fourth insulating layer is arranged on a side of the first source-drain electrode layer away from the substrate, and the second source-drain electrode layer is arranged on a side of the fourth insulating layer away from the substrate.

[0015] In a possible implementation, the display substrate further includes:

[0016] a first insulating layer and a second insulating layer;

[0017] The semiconductor layer is arranged on the substrate, the first insulating layer is arranged on a side of the semiconductor layer away from the substrate, the gate metal layer is arranged on a side of the first insulating layer away from the substrate, the second insulating layer is arranged on a side of the gate metal layer away from the substrate, and the source-drain electrode layer is arranged on a side of the second insulating layer away from the substrate.

[0018] In a possible implementation,

[0019] The plurality of thin film transistors includes a first light-emitting control transistor and a second light-emitting control transistor.

[0020] The first light-emitting control transistor and the second light-emitting control transistor are configured to control a power supply positive voltage to be conducted to a light-emitting device.

[0021] The semiconductor layer includes a first channel and a second channel.

[0022] The first gate metal layer further includes a first gate and a second gate.

[0023] The first light-emitting control transistor includes the first channel and the first gate, and the second light-emitting control transistor includes the second channel and the second gate.

[0024] A first via is arranged between the first gate metal layer and the first source-drain electrode layer.

[0025] The first gate is connected to the first light-emitting control signal line through the first via, and the second gate is connected to the second light-emitting control signal line through direct contact.

[0026] In a possible implementation,

[0027] A second end of the second channel of the second light-emitting control transistor has no overlapping part with a projection of the first light-emitting control signal line on the substrate.

[0028] In a possible implementation,

[0029] The second end of the second channel of the second light-emitting control transistor has an overlapping portion with a projection of the second light-emitting control signal line on the substrate.

[0030] In a possible implementation, an area of the overlapping portion is not greater than 15 micrometers*15 micrometers.

[0031] In a possible implementation, the plurality of thin film transistors further include a first reset transistor;

[0032] The semiconductor layer further includes a third channel, and the first gate metal layer further includes a third gate electrode;

[0033] The first reset transistor includes the third channel and the third gate electrode.

[0034] In a possible implementation, in a column direction of the display substrate, a length of the third gate electrode of the first reset transistor ranges from 2 micrometers to 5 micrometers.

[0035] In a possible implementation, the first gate metal layer and the second gate metal layer constitute a plurality of storage capacitors.

[0036] The plurality of thin film transistors further include a compensation transistor;

[0037] The semiconductor layer further includes a fourth channel, and the first gate metal layer further includes a fourth gate electrode, a fifth gate electrode, and a sixth gate electrode;

[0038] The second gate metal layer includes a first plate electrode;

[0039] The compensation transistor includes the fourth channel, the fourth gate electrode, and the fifth gate electrode, and the storage capacitor includes the sixth gate electrode and the first plate electrode.

[0040] The fourth gate electrode and the fifth gate electrode form a T-shaped structure, and a suspended semiconductor between the fourth gate electrode and the fifth gate electrode is located in a first quadrant of the T-shaped structure, the first quadrant being closer to the sixth gate electrode than a second quadrant of the T-shaped structure.

[0041] The first plate electrode and a projection of the suspended semiconductor on the substrate have an overlapping portion.

[0042] In a possible implementation, the first source-drain electrode layer further includes a power positive signal line;

[0043] Projections of adjacent power positive signal lines and first light-emitting control signal lines on the substrate have no overlapping portion.

[0044] In a possible implementation, the first source-drain electrode layer further comprises a gate scanning signal line, an initialization signal line, a first reset signal line, and a second reset signal line.

[0045] In a possible implementation, the second source-drain electrode layer comprises a data signal line and a power negative signal line.

[0046] The exemplary embodiments of the present disclosure further provide a preparation method of a display substrate, the display substrate comprising a substrate, a semiconductor layer, a gate metal layer, and a source-drain electrode layer, the semiconductor layer, the gate metal layer, and the source-drain electrode layer forming a plurality of thin film transistors, the preparation method comprising:

[0047] forming a substrate;

[0048] forming a semiconductor layer;

[0049] forming a gate metal layer, the gate metal layer comprising a second light-emitting control signal line; the gate metal layer further comprising a first gate metal layer, a third insulating layer, and a second gate metal layer;

[0050] forming a source-drain electrode layer, the source-drain electrode layer comprising a first light-emitting control signal line; the source-drain electrode layer further comprising a first source-drain electrode layer, a fourth insulating layer, and a second source-drain electrode layer;

[0051] The first light-emitting control signal line and the second light-emitting control signal line are connected to the gates of different thin film transistors.

[0052] The first light-emitting control signal line is arranged in the first source-drain electrode layer, and the second light-emitting control signal line is arranged in the first gate metal layer.

[0053] The third insulating layer is arranged on a side of the first gate metal layer away from the substrate, and the second gate metal layer is arranged on a side of the third insulating layer away from the substrate.

[0054] The fourth insulating layer is arranged on a side of the first source-drain electrode layer away from the substrate, and the second source-drain electrode layer is arranged on a side of the fourth insulating layer away from the substrate.

[0055] In a possible implementation, the method further comprises:

[0056] forming a first insulating layer and a second insulating layer;

[0057] The semiconductor layer is arranged on the substrate, the first insulating layer is arranged on a side of the semiconductor layer away from the substrate, the gate metal layer is arranged on a side of the first insulating layer away from the substrate, the second insulating layer is arranged on a side of the gate metal layer away from the substrate, and the source-drain electrode layer is arranged on a side of the second insulating layer away from the substrate.

[0058] In a possible implementation, the plurality of thin film transistors includes a first light-emitting control transistor and a second light-emitting control transistor.

[0059] The first light-emitting control transistor and the second light-emitting control transistor are configured to control a power supply positive voltage to turn on the light-emitting device.

[0060] The semiconductor layer includes a first channel and a second channel.

[0061] The first gate metal layer further includes a first gate and a second gate.

[0062] The first light-emitting control transistor includes the first channel and the first gate, and the second light-emitting control transistor includes the second channel and the second gate.

[0063] A first via is arranged between the first gate metal layer and the first source-drain electrode layer.

[0064] The first gate is connected to the first light-emitting control signal line through the first via, and the second gate is connected to the second light-emitting control signal line through direct contact.

[0065] In a possible implementation,

[0066] A second end of the second channel of the second light-emitting control transistor has no overlapping part with a projection of the first light-emitting control signal line on the substrate.

[0067] In a possible implementation,

[0068] A second end of the second channel of the second light-emitting control transistor has an overlapping part with a projection of the second light-emitting control signal line on the substrate.

[0069] In a possible implementation, the plurality of thin film transistors further includes a first reset transistor.

[0070] The semiconductor layer further includes a third channel, and the first gate metal layer further includes a third gate.

[0071] The first reset transistor includes the third channel and the third gate.

[0072] In a possible implementation, the first gate metal layer and the second gate metal layer form a plurality of storage capacitors;

[0073] The plurality of thin film transistors further include a compensation transistor;

[0074] The semiconductor layer further includes a fourth channel, and the first gate metal layer further includes a fourth gate, a fifth gate and a sixth gate;

[0075] The second gate metal layer includes a first plate;

[0076] The compensation transistor includes the fourth channel, the fourth gate and the fifth gate, and the storage capacitor includes the sixth gate and the first plate;

[0077] The fourth gate and the fifth gate form a T-shaped structure, and a suspended semiconductor between the fourth gate and the fifth gate is located in a first quadrant of the T-shaped structure, the first quadrant being closer to the sixth gate than a second quadrant of the T-shaped structure;

[0078] The first plate and a projection of the suspended semiconductor on the substrate have an overlapping portion.

[0079] The display substrate can be used in a display device.

[0080] Other aspects can become apparent after reading and understanding the accompanying drawings and detailed description.

[0081] SUMMARY

[0082] FIG. 1 is a schematic diagram of a structure of a 7T1C pixel driving circuit;

[0083] FIG. 2a is a schematic diagram of a stack structure of a display substrate according to an example embodiment of the present disclosure;

[0084] FIG. 2b is a schematic diagram of a top view of a display substrate according to an example embodiment of the present disclosure;

[0085] FIG. 3a is a schematic diagram of a stack structure of a gate metal layer of a display substrate according to an example embodiment of the present disclosure;

[0086] FIG. 3b is a schematic diagram of a stack structure of a source / drain electrode layer of a display substrate according to an example embodiment of the present disclosure;

[0087] FIG. 4 is a schematic diagram of a stack structure of a display substrate according to another example embodiment of the present disclosure;

[0088] FIG. 5 is a schematic diagram of a structure of a 7T1C pixel driving circuit corresponding to a display substrate according to an example embodiment of the present disclosure;

[0089] Fig. 6 is a schematic view of the first quadrant and the second quadrant of the T-shaped structure;

[0090] Fig. 7a is a second schematic view from above of a display substrate according to an example embodiment of the present disclosure;

[0091] Fig. 7b is a third schematic view from above of a display substrate according to an example embodiment of the present disclosure;

[0092] Fig. 7c is a fourth schematic view from above of a display substrate according to an example embodiment of the present disclosure;

[0093] Fig. 7d is a fifth schematic view from above of a display substrate according to an example embodiment of the present disclosure;

[0094] Fig. 7e is a sixth schematic view from above of a display substrate according to an example embodiment of the present disclosure;

[0095] Fig. 7f is a seventh schematic view from above of a display substrate according to an example embodiment of the present disclosure;

[0096] Fig. 8 is a schematic view of a display device according to an example embodiment of the present disclosure;

[0097] Fig. 9 is an eighth schematic view from above of a display substrate according to an example embodiment of the present disclosure.

[0098] Detailed description

[0099] A detailed description of the present disclosure is further described below with reference to the accompanying drawings and examples. The following examples are used to illustrate the present disclosure and are merely exemplary, but are not used to limit the scope of the present disclosure. The examples in the present disclosure and the features in the examples can be combined with each other arbitrarily without conflict.

[0100] In the current 7T1C (7 Thin Film Transistors, TFT, 1 capacitor, C) pixel driving circuit, the circuit structure diagram of the 7T1C pixel driving circuit can be seen from Fig. 1. In the reset stage, the first light-emitting control transistor T5 (212) and the second light-emitting control transistor T6 (208) are in the off state, the first reset transistor T4 (215) is turned on to reset the gate of the driving transistor T2 (205), i.e. the N2 node (216), and the N1 node 219 is easily coupled when the N2 node (216) is reset, resulting in display defects such as FRR, hysteresis, etc. in the display product.

[0101] First, let's briefly explain what a thin-film transistor is. A thin-film transistor is a type of transistor that is made using thin-film materials. It is commonly used to drive and control the switching of pixels, allowing displays to have high resolution, fast response, and low power consumption, among other advantages. As shown in Figure 2a, a thin-film transistor typically consists of multiple layers, including a bottom substrate 11, a semiconductor layer 12, a gate metal layer 13, and so on.

[0102] Thin-film transistors play a crucial role in display technology, primarily used to control the brightness and color of pixels. They enable precise control over each pixel, resulting in high-quality image display, with higher resolution, thinner and more portable devices, and lower power consumption.

[0103] Thin-film transistors have several key features:

[0104] 1. High resolution: Thin-film transistors enable pixel-level control, providing high-resolution display effects. Each sub-pixel is driven by an independent thin-film transistor, allowing precise adjustment of brightness and color.

[0105] 2. Fast response: Thin-film transistors have fast response times, enabling rapid switching between on and off states, allowing for smooth video playback and dynamic image display.

[0106] 3. Low power consumption: Thin-film transistors require low current during operation, resulting in lower power consumption, making displays more energy-efficient and extending battery life.

[0107] 4. Uniformity: The manufacturing process of thin-film transistors is relatively simple, allowing for mass production, ensuring consistency and uniformity, resulting in a more uniform display screen in terms of brightness and color performance.

[0108] 5. Reliability: Thin-film transistors have high reliability and stability, allowing for long-term operation without frequent failures, making displays more durable and reliable.

[0109] The working principle of a thin-film transistor is based on the properties of semiconductor materials and the principles of field-effect transistors (FETs). Here is the working process of a thin-film transistor:

[0110] Substrate 11: The substrate 11 of a thin-film transistor is usually made of glass or plastic materials, providing support and insulation functions.

[0111] Insulating layer: The insulating layer of a thin-film transistor is usually made of insulating materials such as silicon dioxide.

[0112] Semiconductor layer 12: The semiconductor layer 12 is the core part of the thin film transistor, usually made of polycrystalline silicon or amorphous silicon material, and contains two regions of source and drain (forming a channel) in the semiconductor layer 12, which are controlled by a control electrode (gate metal layer).

[0113] Source-drain electrode layer 13: The source-drain electrode layer 13 includes the source and drain, which are two electrodes in the thin film transistor, connected to specific regions in the semiconductor layer 12, and when appropriate voltage is applied to the source and drain, a conductive channel (channel) is formed in the semiconductor layer 12.

[0114] Gate metal layer 14: The gate metal layer 14 is the control electrode in the thin film transistor, which can control the formation and disconnection of the conductive channel in the semiconductor layer 12 when appropriate voltage is applied to the gate.

[0115] The working principle of the thin film transistor is based on the principle of field effect transistor (FET), when voltage is applied to the gate, an electric field is formed, which forms a conductive channel in the semiconductor layer 12, which allows current to flow between the source and drain, thereby realizing the on-off state of the thin film transistor. By controlling the voltage on the gate, the conductive channel of the thin film transistor can be accurately controlled, and by applying different voltages to the gates of different thin film transistors, accurate control of each pixel can be achieved, thereby displaying the required image.

[0116] Next, a brief introduction to the 7T1C pixel driving circuit is given, and the circuit structure diagram of the 7T1C pixel driving circuit can be referred to Figure 1.

[0117] Referring to Figures 1 and 2b, the 7T1C pixel driving circuit includes a data writing transistor T1 (213), a driving transistor T2 (205), a compensation transistor T3 (204), a first reset transistor T4 (215), a first light-emitting control transistor T5 (212), a second light-emitting control transistor T6 (208), a second reset transistor T7 (211), and a storage capacitor Cst. D1 is a light-emitting device, VDD (206) is a positive power supply signal line, VSS is a negative power supply signal line, EM is a light-emitting control signal line, Gate (203) is a gate scanning signal line, Vinit1 (201) is a first initialization signal line, Vinit2 (220) is a second initialization signal line, Reset (N) 202 is a first reset signal line, Reset (N+1) 210 is a second reset signal line, Data (214) is a data signal line.

[0118] The gate of the first reset transistor T4 (215) is connected with the first reset signal line Reset (N) 202, the first end of the first reset transistor T4 (215) is connected with the N2 node (216), and the second end of the first reset transistor T4 (215) is connected with the first initialization signal line Vinit1 (201); the first plate of the storage capacitor Cst is connected with the power positive signal line VDD (206), and the second plate of the storage capacitor Cst is connected with the N2 node (216); the gate of the first light-emitting control transistor T5 (212) is connected with the light-emitting control signal line EM, the first end of the first light-emitting control transistor T5 (212) is connected with the power positive signal line VDD (206), and the second end of the first light-emitting control transistor T5 (212) is connected with the N1 node 219; the gate of the driving transistor T2 (205) is connected with the N2 node (216), the first end of the driving transistor T2 (205) is connected with the N1 node 219, and the second end of the driving transistor T2 (205) is connected with the N3 node (217); the gate of the compensation transistor T3 (204) is connected with the gate scanning signal line Gate (203), the first end of the compensation transistor T3 (204) is connected with the N2 node (216), and the second end of the compensation transistor T3 (204) is connected with the N3 node (217); the gate of the second light-emitting control transistor T6 (208) is connected with the light-emitting control signal line EM, the first end of the second light-emitting control transistor T6 (208) is connected with the N3 node (217), and the second end of the second light-emitting control transistor T6 (208) is connected with the N4 node (218); the gate of the data write transistor T1 (213) is connected with the gate scanning signal line Gate (203), the first end of the data write transistor T1 (213) is connected with the N1 node 219, and the second end of the data write transistor T1 (213) is connected with the data signal line Data (214); the gate of the second reset transistor T7 (211) is connected with the second reset signal line Reset (N+1) 210, the first end of the second reset transistor T7 (211) is connected with the N4 node (218), and the second end of the second reset transistor T7 (211) is connected with the second initialization signal line Vinit2 (220); the anode of the light-emitting device D1 is connected with the N4 node (218), and the cathode of the light-emitting device D1 is connected with the power negative signal line VSS.

[0119] The working timing of the 7T1C pixel driving circuit is divided into three stages. The first stage is a reset stage (step 1), and the reset of the anode of the light emitting device and the gate of the driving transistor T2 (205) is realized by the opening of the first reset transistor T4 (215) and the second reset transistor T7 (211). The second stage is a compensation and data writing stage (step 2), and the threshold voltage Vth of the driving transistor T2 (205) and the voltage of the data signal Data (214) are written into the N2 node (216) by the opening of the driving transistor T2 (205), the data writing transistor T1 (213) and the compensation transistor T3 (204). The third stage is a light emitting stage (step 3), and the anode of the light emitting device D1 is connected to the positive voltage VDD by the opening of the first light emitting control transistor T5 (212) and the second light emitting control transistor T6 (208), and the light emitting is completed. The above three stages (reset stage, compensation and data writing stage, and light emitting stage) are sequentially performed to complete the light emitting of a row of pixels.

[0120] In the display substrate corresponding to the above-mentioned 7T1C (7 thin film transistors, TFT, Thin Film Transistor, 1 capacitor C) pixel driving circuit, each sub-pixel corresponds to a light emitting control signal line EM, and different thin film transistors are connected to the same light emitting control signal line EM, that is, different thin film transistors are controlled by the same light emitting control signal. The switching time of the above-mentioned different transistors cannot be controlled separately, and the timing change of one transistor can only follow another transistor, which will cause circuit malfunctions such as node coupling influence and unstable node voltage of the pixel driving circuit, and further cause display malfunctions such as FRR (first frame response, the phenomenon is that the brightness of the first frame of the displayed picture is lower than that of the subsequent frames) and hysteresis.

[0121] The display substrate and the display device are provided.

[0122] First, a display substrate 1 provided by an example embodiment of the present disclosure is described in detail. Referring to FIG. 2a and FIG. 2b, FIG. 2a is a schematic diagram of a stack structure of a display substrate provided by an example embodiment of the present disclosure, and FIG. 2b is a top view schematic diagram of a display substrate provided by an example embodiment of the present disclosure (a top view schematic diagram based on the stack structure). The display substrate 1 includes:

[0123] a substrate 11, a semiconductor layer 12, a gate metal layer 13, and a source-drain electrode layer 14;

[0124] The semiconductor layer 12, the gate metal layer 13, and the source-drain electrode layer 14 form a plurality of thin film transistors T;

[0125] The source-drain electrode layer 14 comprises a first light-emitting control signal line EM1 (207), and the gate metal layer 13 comprises a second light-emitting control signal line EM2 (209).

[0126] The first light-emitting control signal line EM1 (207) and the second light-emitting control signal line EM2 (209) are connected to the gates of different thin film transistors T.

[0127] Only one sub-pixel unit is shown in FIG. 2b.

[0128] In the exemplary embodiments of the present disclosure, by splitting the light-emitting control signal EM into two independent control signals, i.e., the first light-emitting control signal EM1 (207) and the second light-emitting control signal EM2 (209), the gates of different thin film transistors T are controlled, so that the switching time of different thin film transistors T is controlled separately, and the timing of one thin film transistor T does not need to follow that of another thin film transistor T. In the reset stage of the pixel driving circuit, the second light-emitting control transistor T6 (208) is turned off, but the first light-emitting control transistor T5 (212) is turned on, so that the positive voltage VDD of the power supply is written to the N1 node 219, and the voltage of the N1 node 219 is more stable, and the N2 node (216) is not easily coupled to the N1 node 219, thereby improving the display defects of the display product.

[0129] In a possible implementation, referring to FIGS. 3a and 3b,

[0130] The gate metal layer 13 comprises a first gate metal layer 131, a third insulating layer 132, and a second gate metal layer 133; and the source-drain electrode layer 14 comprises a first source-drain electrode layer 141, a fourth insulating layer 142, and a second source-drain electrode layer 143.

[0131] The first light-emitting control signal line EM1 (207) is arranged in the first source-drain electrode layer 141, and the second light-emitting control signal line EM2 (209) is arranged in the first gate metal layer 131.

[0132] The third insulating layer 132 is arranged on the side of the first gate metal layer 131 away from the substrate 11, and the second gate metal layer 133 is arranged on the side of the third insulating layer 132 away from the substrate 11.

[0133] The fourth insulating layer 142 is arranged on the side of the first source-drain electrode layer 141 away from the substrate 11, and the second source-drain electrode layer 143 is arranged on the side of the fourth insulating layer 142 away from the substrate 11.

[0134] In the exemplary embodiments of the present disclosure, the first light-emitting control signal line EM1 (207) and the second light-emitting control signal line EM2 (209) are arranged in different levels of the display substrate.

[0135] In a possible implementation, referring to FIG. 4, which is a second schematic diagram of a stack structure of a display substrate provided in the exemplary embodiments of the present disclosure, the display substrate 1 further includes:

[0136] The first insulating layer 15 and the second insulating layer 16;

[0137] The semiconductor layer 12 is arranged on the substrate 11, the first insulating layer 15 is arranged on a side of the semiconductor layer 12 away from the substrate 11, the gate metal layer 13 is arranged on a side of the first insulating layer 15 away from the substrate 11, the second insulating layer 16 is arranged on a side of the gate metal layer 13 away from the substrate 11, and the source-drain electrode layer 14 is arranged on a side of the second insulating layer 16 away from the substrate 11.

[0138] In a possible implementation, referring to FIG. 2b,

[0139] The plurality of thin film transistors T include a first light-emitting control transistor T5 (212) and a second light-emitting control transistor T6 (208);

[0140] The first light-emitting control transistor T5 (212) and the second light-emitting control transistor T6 (208) are configured to control the conduction of a positive voltage of a power supply to a light-emitting device D1.

[0141] The semiconductor layer 12 includes a first channel and a second channel;

[0142] The first gate metal layer 131 further includes a first gate and a second gate;

[0143] The first light-emitting control transistor T5 (212) includes the first channel and the first gate, and the second light-emitting control transistor T6 (208) includes the second channel and the second gate.

[0144] A first via is arranged between the first gate metal layer 131 and the first source-drain electrode layer 141.

[0145] The first gate is connected to the first light-emitting control signal line EM1 (207) through the first via, and the second gate is connected to the second light-emitting control signal line EM2 (209) through direct contact.

[0146] The 7T1C pixel driving circuit structure corresponding to the exemplary embodiments of the present disclosure can be seen from FIG. 5. The gate of the first light-emitting control transistor T5 (212) is connected to the first light-emitting control signal line EM1 (207), and the gate of the second light-emitting control transistor T6 (208) is connected to the second light-emitting control signal line EM2 (209).

[0147] In a possible implementation, the light-emitting device D1 in FIG. 5 can be an OLED (Organic Light-Emitting Diode).

[0148] In the exemplary embodiments of the present disclosure, the two transistors of the first light-emitting control transistor T5 (212) and the second light-emitting control transistor T6 (208) are controlled using different GOA (Gate Driver on Array) control signals, that is, the first light-emitting control transistor T5 (212) is controlled using the first light-emitting control signal EM1 (207), the second light-emitting control transistor T6 (208) is controlled using the second light-emitting control signal EM2 (209), and the timing of the two transistors is staggered, so that the switching time of the first light-emitting control transistor T5 (212) and the switching time of the second light-emitting control transistor T6 (208) can be independently and flexibly controlled.

[0149] In an exemplary implementation, when the N2 node 216, that is, the gate of the driving transistor T2 (205), is reset (initialized), the first reset transistor T4 (215) is turned on, the first light-emitting control transistor T5 (212) is turned on, and the second light-emitting control transistor T6 (208) is turned off. In the reset stage, the first light-emitting control transistor T5 (212) is controlled to be turned on by the first light-emitting control signal EM1 (207), so that the power positive signal VDD is written to the N1 node 219, and the voltage of the N1 node 219 is ensured to be stable. In the data writing stage, the first light-emitting control transistor T5 (212) and the second light-emitting control transistor T6 (208) are controlled to be turned off at the same time, and the data writing transistor T1 (213) is turned on. Compared with the related art, in the reset stage, the first light-emitting control transistor T5 (212) is in the off state, and the N1 node 219 is easily coupled when the N2 node 216 is reset, which causes the display product to have FRR, hysteresis, and other display defects. In the present disclosure, the first light-emitting control transistor T5 (212) is controlled to be turned on in the reset stage, so that the voltage of the N1 node 219 is relatively stable before data writing, and the N1 node 219 is not easily coupled when the N2 node 216 is reset. The FRR, hysteresis, and other display defects of the display product are improved. One of the reasons for the FRR display defect is the channel defect of the driving transistor T2 (205), which can be improved after a certain bias voltage is applied.

[0150] In a possible implementation, referring to FIG. 2b,

[0151] The second end of the second channel of the second light-emitting control transistor T6 (208), that is, the second end of the second light-emitting control transistor T6 (208) / N4 node 218, has no overlapping part with the projection of the second light-emitting control signal line EM2 (209) on the substrate 11.

[0152] In an exemplary embodiment of the present disclosure, by the non-overlapping part of the projection of the first light-emitting control signal line EM1 (207) and the N4 node (218) on the substrate 11, that is, the non-overlapping of the first light-emitting control signal line EM1 (207) and the N4 node (218), the pixel can be avoided to be electrically coupled to be turned on.

[0153] In a possible implementation, referring to FIG. 2b,

[0154] The second end of the second channel of the second light-emitting control transistor T6 (208), that is, the second end of the second light-emitting control transistor T6 (208) / N4 node 218, has no overlapping part with the projection of the second light-emitting control signal line EM2 (209) on the substrate 11.

[0155] The area of the overlapping part is not greater than 15 microns*15 microns.

[0156] In an exemplary embodiment of the present disclosure, by reducing the overlapping area of the projection of the second light-emitting control signal line EM2 (209) and the N4 node (218) on the substrate 11, that is, reducing the overlapping of the second light-emitting control signal line EM2 (209) and the N4 node (218), the capacitive influence of the second light-emitting control signal line EM2 (209) on the N4 node (218) can be reduced.

[0157] In a possible implementation, referring to FIG. 2b, the plurality of thin film transistors T further includes a first reset transistor T4 (215);

[0158] The semiconductor layer 12 further includes a third channel, and the first gate metal layer 131 further includes a third gate electrode;

[0159] The first reset transistor T4 (215) includes the third channel and the third gate electrode;

[0160] In the column direction of the display substrate 1, the length of the third gate electrode of the first reset transistor T4 (215) ranges from 2 microns to 5 microns.

[0161] In the exemplary embodiment of the present disclosure, the gate of the first reset transistor T4 (215) is lengthened, which can shield the coupling effect of Data (214) on the N2 node (216).

[0162] In one possible implementation, referring to FIG. 2b, the first gate metal layer 131 and the second gate metal layer 133 form a plurality of storage capacitors Cst;

[0163] The plurality of thin film transistors T further comprise a compensation transistor T3 (204);

[0164] The semiconductor layer 12 further comprises a fourth channel, and the first gate metal layer 131 further comprises a fourth gate, a fifth gate, and a sixth gate;

[0165] The second gate metal layer 133 comprises a first plate;

[0166] The compensation transistor T3 (204) comprises the fourth channel, the fourth gate, and the fifth gate, and the storage capacitor Cst comprises the sixth gate and the first plate;

[0167] The fourth gate and the fifth gate form a T-shaped structure, and a floating semiconductor between the fourth gate and the fifth gate is located in a first quadrant of the T-shaped structure, which is closer to the sixth gate than a second quadrant of the T-shaped structure;

[0168] The first plate and a projection of the floating semiconductor on the substrate 11 have an overlapping portion.

[0169] The compensation transistor T3 (204) is a dual-gate transistor, the floating semiconductor between the two gates is shielded by the first plate of the storage capacitor Cst, and the floating semiconductor faces the second plate (the sixth gate) of the storage capacitor Cst, which can maximize the reduction of the wiring length of the second gate metal layer 133.

[0170] The dual-gate transistor can be regarded as being formed by connecting two transistors in series, and the bias voltage on the two gates controls the entire dual-gate transistor.

[0171] In one exemplary embodiment, the plurality of thin film transistors T further comprise a driving transistor T2 (205), the gate (the sixth gate) of the driving transistor T2 (205) is multiplexed as the second plate of the storage capacitor Cst, and the first plate of the storage capacitor Cst is connected to the positive power supply signal line VDD (206).

[0172] A schematic diagram of the first quadrant and the second quadrant of the T-shaped structure is shown in FIG. 6.

[0173] In the exemplary embodiments of the present disclosure, by setting the suspended semiconductor towards the second plate (sixth gate) of the storage capacitor Cst, the length of the trace of the second gate metal layer 133 can be maximally reduced.

[0174] In a possible implementation, referring to FIG. 2b, the first source-drain electrode layer 141 further comprises a power supply positive signal line VDD (206);

[0175] The projection of the adjacent power supply positive signal line VDD (206) and the first light-emitting control signal line EM1 (207) on the substrate 11 has no overlapping part.

[0176] In the exemplary embodiments of the present disclosure, by the non-overlapping projection of the power supply positive signal line VDD (206) and the first light-emitting control signal line EM1 (207) on the substrate 11, i.e., the non-overlapping of the power supply positive signal line VDD (206) and the first light-emitting control signal line EM1 (207), it is ensured that the first light-emitting control signal EM1 (207) does not affect the load of the power supply positive signal VDD (206).

[0177] In a possible implementation, referring to FIG. 2b, the first source-drain electrode layer 141 further comprises a gate scanning signal line Gate (203), a first initialization signal line Vinit1 (201), a second initialization signal line Vinit2 (220), a first reset signal line Reset (N) 202, and a second reset signal line Reset (N+1) 210.

[0178] Referring to FIG. 5, the gate of the data writing transistor T1 (213) is connected to the gate scanning signal line Gate (203), the gate of the compensation transistor T3 (204) is connected to the gate scanning signal line Gate (203), the gate of the first reset transistor T4 (215) is connected to the first reset signal line Reset (N) 202, the gate of the second reset transistor T7 (211) is connected to the second reset signal line Reset (N+1) 210, the second end of the first reset transistor T4 (215) is connected to the first initialization signal line Vinit1 (201), and the second end of the second reset transistor T7 (211) is connected to the second initialization signal line Vinit2 (220).

[0179] In a possible implementation, the second source-drain electrode layer 143 comprises a data signal line Data (214) and a power supply negative signal line VSS.

[0180] Referring to FIG. 5, the second end of the data writing transistor T1 (213) is connected to the data signal line Data (214), and the second end (negative electrode) of the light-emitting device D1 is connected to the power supply negative signal line VSS.

[0181] For any thin-film transistor in the pixel driving circuit of this disclosure, the thin-film transistor can be an N-type transistor or a P-type transistor, whichever is appropriate based on the actual situation. The first terminal of the thin-film transistor is the source or drain, and the second terminal is the drain or source corresponding to the first terminal. The thin-film transistor can be a P-type transistor or an N-type transistor, whichever is appropriate based on the actual situation, but the device connection method of the circuit needs to be adjusted accordingly. The alternative solutions are still within the protection scope of this disclosure.

[0182] The transistors used in the pixel driving circuit of this disclosure may be MOS transistors (metal-oxide-semiconductor field-effect transistors) or other types of transistors. The specific type can be selected according to the actual situation. The alternative scheme is still within the protection scope of this disclosure. The connection method of MOS transistors or other types of transistors can be referred to the connection method of TFT transistors, which will not be repeated here.

[0183] A simplified top view of the display substrate 1 with multiple layers provided in the exemplary embodiments of this disclosure can be seen in Figures 7a, 7b, 7c, 7d, 7e, and 7f.

[0184] Figure 7a shows semiconductor layer 12, which can be a polysilicon layer used to form the channels of multiple thin-film transistors T.

[0185] Figure 7b is a top view of the fabrication of the first gate metal layer 131, which is used to set the gates 1311 of multiple thin-film transistors T and the second light-emitting control signal line EM2 (209).

[0186] Figure 7c is a top view of the fabrication of the second gate metal layer 133, which is used to set the first electrode (metal electrode) 1333 of the storage capacitor Cst.

[0187] The first gate metal layer 131 is molybdenum (Mo) or titanium (Ti), and the second gate metal layer 133 is copper (Cu) or aluminum (Al); or, the first gate metal layer 131 is an alloy metal with molybdenum / titanium as the substrate, and the second gate metal layer 133 is an alloy metal with copper / aluminum as the substrate.

[0188] Figure 7d is a top view of the display substrate 1 after CNT via 151 is set. It is usually necessary to make vias in the thin film between two conductive layers in different layers to achieve the connection between the two conductive layers located in different layers.

[0189] Figure 7e is a schematic view from above after the preparation of the first source-drain electrode layer 141, which is used to set the gate scanning signal line Gate (203), the first initialization signal line Vinit1 (201), the second initialization signal line Vinit2 (220), the first reset signal line Reset (N) 202, the second reset signal line Reset (N+1) 210, the power positive signal line VDD (206), the first light-emitting control signal line EM1 (207), and the like. The first plate 1333 of the storage capacitor Cst is connected to the power positive signal line VDD (206) through the via hole 151. The connection line 221 of the reset N2 node (216) is used to connect the compensation transistor T3 and the first reset transistor T4 drain, and to connect the gate of the driving transistor T2. The first initialization signal line Vinit1 (201) is used to connect the second end of the first reset transistor T4 (215), and the second initialization signal line Vinit2 (220) can include VinitR (2201), VinitGB (2202), VinitR and VinitGB are signal lines of separate reset anodes, VinitR and VinitGB provide signals separately, VinitR (2201) is used to connect the second end of the second reset transistor T7 (211) in the red pixel (R), and VinitGB (2202) is used to connect the second end of the second reset transistor T7 (211) in the blue pixel (B) and the green pixel (G).

[0190] Fig. 7f is a top view of the display substrate 1 after the second source-drain electrode layer 143 is formed. The second source-drain electrode layer 143 is used to form the data signal line Data, the power negative signal line VSS, etc. Referring to Fig. 9, the N4 node potential 1431 in the second source-drain electrode layer 143 is located below the anode 300 and is used to flatten the anode 300, i.e., to serve as a pad for the anode 300, thereby improving the flatness of the anode 300, which can reduce the asymmetric color shift. In the example embodiment of the present disclosure, the N4 node potential 1431 refers to a structure that has a projection on the substrate that overlaps with the projection of the anode on the substrate and is closer to the substrate than the anode. The second source-drain electrode layer 143 further includes the ith first initialization signal line Vinit1 (vertical) 1432, the Nth data signal line Data 1433, the Mth power positive signal line VDD (vertical) 1430, the N+1th data signal line Data 1434, the jth anode reset signal line VinitR / VinitGB (vertical) 1435, the N+2th data signal line Data 1436, the M+1th power positive signal line VDD (vertical) 1437, the power negative signal line VSS 1438, the i+1th first initialization signal line Vinit1 (vertical) 1439. The first initialization signal line Vinit1 (vertical), the anode reset signal line VinitGB (vertical), the first initialization signal line Vinit1 (vertical), and the anode reset signal line VinitR (vertical) are periodically arranged in the vertical direction. The anode reset signal lines VinitR and VinitGB are alternately arranged into a network.

[0191] For example, the ith first initialization signal line Vinit1 (vertical) 1432 is connected to the first initialization signal line Vinit1 (201) in the horizontal direction, the jth anode reset signal line VinitGB (vertical) 1435 is connected to the VinitGB (2202) in the horizontal direction, and the i+1th first initialization signal line Vinit1 (vertical) 1439 is connected to the first initialization signal line Vinit1 (201) in the horizontal direction.

[0192] The data signal line Data (214) can be any data signal line Data.

[0193] The example embodiment of the present disclosure further provides a display device 2, as shown in Fig. 8, which includes the display substrate 1 according to any of the example embodiments described above.

[0194] In summary, the display substrate and the display device provided by the exemplary embodiments of the present disclosure include: a substrate, a semiconductor layer, a gate metal layer, and a source-drain electrode layer; the semiconductor layer, the gate metal layer, and the source-drain electrode layer form a plurality of thin film transistors; the source-drain electrode layer includes a first light-emitting control signal line, and the gate metal layer includes a second light-emitting control signal line; the first light-emitting control signal line and the second light-emitting control signal line are connected to the gates of different thin film transistors. By splitting the light-emitting control signal into two independent control signals, i.e., the first light-emitting control signal and the second light-emitting control signal, the two control signals are used to control the gates of different thin film transistors, so that the switching time of different thin film transistors is controlled separately, and the timing change of one thin film transistor does not need to follow another thin film transistor. In the reset stage of the pixel driving circuit, the second light-emitting control transistor T6 is closed, but the first light-emitting control transistor T5 is opened, so that the positive voltage VDD of the power supply is written to the N1 node, and the voltage of the N1 node is more stable, and the N2 node is not easily coupled to the N1 node, thereby improving the display defects of the display product.

[0195] In this document, relational terms such as first and second and the like can be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but can include other elements not expressly listed or inherent to such process, method, article, or apparatus. An element proceeded by "comprises... a" does not, without more constraints, exclude the existence of additional identical elements in the process, method, article, or apparatus that comprises the element.

[0196] The multiple exemplary embodiments in the present specification are described in a related manner, and the same or similar parts of the multiple exemplary embodiments can be referred to each other. Each exemplary embodiment focuses on the difference from other exemplary embodiments. In particular, for the system embodiments, since they are basically similar to the method embodiments, the description is relatively simple, and the related parts can be referred to the part of the description of the method embodiments.

[0197] The above only describes the preferred embodiments of the present disclosure and is not intended to limit the protection scope of the present disclosure. Any modification, equivalent replacement, improvement, and the like made within the spirit and principle of the present disclosure shall be included in the protection scope of the present disclosure.

Claims

1. A display substrate, comprising: a substrate, a semiconductor layer, a gate metal layer, a source-drain electrode layer; the semiconductor layer, the gate metal layer, and the source-drain electrode layer constitute a plurality of thin film transistors; the source-drain electrode layer comprises a first light-emitting control signal line, and the gate metal layer comprises a second light-emitting control signal line; the first light-emitting control signal line and the second light-emitting control signal line are connected to the gates of different thin film transistors; the gate metal layer comprises a first gate metal layer, a third insulating layer, and a second gate metal layer; and the source-drain electrode layer comprises a first source-drain electrode layer, a fourth insulating layer, and a second source-drain electrode layer; the first light-emitting control signal line is arranged in the first source-drain electrode layer, and the second light-emitting control signal line is arranged in the first gate metal layer; the third insulating layer is arranged on a side of the first gate metal layer away from the substrate, and the second gate metal layer is arranged on a side of the third insulating layer away from the substrate; the fourth insulating layer is arranged on a side of the first source-drain electrode layer away from the substrate, and the second source-drain electrode layer is arranged on a side of the fourth insulating layer away from the substrate. 2.The display substrate according to claim 1, further comprising: a first insulating layer and a second insulating layer; the semiconductor layer is arranged on the substrate, the first insulating layer is arranged on a side of the semiconductor layer away from the substrate, the gate metal layer is arranged on a side of the first insulating layer away from the substrate, the second insulating layer is arranged on a side of the gate metal layer away from the substrate, and the source-drain electrode layer is arranged on a side of the second insulating layer away from the substrate. 3.The display substrate according to claim 1, wherein the plurality of thin film transistors comprise a first light-emitting control transistor and a second light-emitting control transistor; the first light-emitting control transistor and the second light-emitting control transistor are used to control a power supply positive voltage to turn on a light-emitting device; the semiconductor layer comprises a first channel and a second channel; the first gate metal layer further comprises a first gate and a second gate; the first light-emitting control transistor comprises the first channel and the first gate, and the second light-emitting control transistor comprises the second channel and the second gate; a first via hole is arranged between the first gate metal layer and the first source-drain electrode layer; the first gate is connected to the first light-emitting control signal line through the first via hole, and the second gate is connected to the second light-emitting control signal line through direct contact. 4.The display substrate according to claim 3, wherein a second end of the second channel of the second light-emitting control transistor and a projection of the first light-emitting control signal line on the substrate have no overlapping part. 5.The display substrate according to claim 3, wherein a second end of the second channel of the second light-emitting control transistor and a projection of the second light-emitting control signal line on the substrate have an overlapping part. An area of the overlapping part is not greater than 15 micrometers*15 micrometers. 6.The display substrate of claim 5, wherein, the plurality of thin film transistors further comprise a first reset transistor. 7.The display substrate of claim 3, wherein, ​ The semiconductor layer further comprises a third channel, and the first gate metal layer further comprises a third gate; The first reset transistor comprises the third channel and the third gate. 8.The display substrate of claim 7, wherein, In a column direction of the display substrate, a length of the third gate of the first reset transistor ranges from 2 microns to 5 microns. 9.The display substrate of claim 3, wherein, The first gate metal layer and the second gate metal layer form a plurality of storage capacitors; The plurality of thin film transistors further comprises a compensation transistor; The semiconductor layer further comprises a fourth channel, and the first gate metal layer further comprises a fourth gate, a fifth gate, and a sixth gate; The second gate metal layer comprises a first plate; The compensation transistor comprises the fourth channel, the fourth gate, and the fifth gate; and the storage capacitor comprises the sixth gate and the first plate; The fourth gate and the fifth gate form a T-shaped structure; and a suspended semiconductor between the fourth gate and the fifth gate is located in a first quadrant of the T-shaped structure, which is closer to the sixth gate than a second quadrant of the T-shaped structure; The first plate and a projection of the suspended semiconductor on the substrate have an overlapping portion. 10.The display substrate of claim 1, wherein, The first source-drain electrode layer further comprises a power positive signal line; Projections of adjacent power positive signal lines and first light-emitting control signal lines on the substrate have no overlapping portion. 11.The display substrate of claim 10, wherein, The first source-drain electrode layer further comprises a gate scanning signal line, an initialization signal line, a first reset signal line, and a second reset signal line. 12.The display substrate of claim 1, wherein, The second source-drain electrode layer comprises a data signal line and a power negative signal line.

13. A preparation method of a display substrate, the display substrate comprising a substrate, a semiconductor layer, a gate metal layer, and a source-drain electrode layer, the semiconductor layer, the gate metal layer, and the source-drain electrode layer forming a plurality of thin film transistors, the preparation method comprising: forming a substrate; forming a semiconductor layer; forming a gate metal layer, the gate metal layer comprising a second light-emitting control signal line, the gate metal layer further comprising a first gate metal layer, a third insulating layer, and a second gate metal layer; forming a source-drain electrode layer, the source-drain electrode layer comprising a first light-emitting control signal line, the source-drain electrode layer further comprising a first source-drain electrode layer, a fourth insulating layer, and a second source-drain electrode layer; wherein the first light-emitting control signal line and the second light-emitting control signal line are connected to different gates of the thin film transistors; the first light-emitting control signal line is arranged in the first source-drain electrode layer, and the second light-emitting control signal line is arranged in the first gate metal layer; the third insulating layer is arranged on a side of the first gate metal layer away from the substrate, and the second gate metal layer is arranged on a side of the third insulating layer away from the substrate; the fourth insulating layer is arranged on a side of the first source-drain electrode layer away from the substrate, and the second source-drain electrode layer is arranged on a side of the fourth insulating layer away from the substrate.

14. The preparation method according to claim 13, further comprising: forming a first insulating layer and a second insulating layer. ​ The semiconductor layer is disposed on the substrate, the first insulating layer is disposed on a side of the semiconductor layer away from the substrate, the gate metal layer is disposed on a side of the first insulating layer away from the substrate, the second insulating layer is disposed on a side of the gate metal layer away from the substrate, and the source-drain electrode layer is disposed on a side of the second insulating layer away from the substrate.

15. The manufacturing method according to claim 13, wherein, The plurality of thin film transistors comprises a first light-emitting control transistor and a second light-emitting control transistor. The first light-emitting control transistor and the second light-emitting control transistor are configured to control a power supply positive voltage to be turned on to a light-emitting device. The semiconductor layer comprises a first channel and a second channel. The first gate metal layer further comprises a first gate and a second gate. The first light-emitting control transistor comprises the first channel and the first gate, and the second light-emitting control transistor comprises the second channel and the second gate. A first via is disposed between the first gate metal layer and the first source-drain electrode layer. The first gate is connected to the first light-emitting control signal line through the first via, and the second gate is connected to the second light-emitting control signal line through direct contact.

16. The manufacturing method according to claim 15, wherein, A second end of the second channel of the second light-emitting control transistor has no overlapping part with a projection of the first light-emitting control signal line on the substrate.

17. The manufacturing method according to claim 15, wherein, A second end of the second channel of the second light-emitting control transistor has an overlapping part with a projection of the second light-emitting control signal line on the substrate.

18. The method of making according to claim 15, wherein, The plurality of thin film transistors further comprises a first reset transistor. The semiconductor layer further comprises a third channel, and the first gate metal layer further comprises a third gate. The first reset transistor comprises the third channel and the third gate.

19. The method of making according to claim 15, wherein, The first gate metal layer and the second gate metal layer form a plurality of storage capacitors. The plurality of thin film transistors further comprises a compensation transistor. The semiconductor layer further comprises a fourth channel, and the first gate metal layer further comprises a fourth gate, a fifth gate, and a sixth gate. The second gate metal layer comprises a first plate. The compensation transistor comprises the fourth channel, the fourth gate, and the fifth gate, and the storage capacitor comprises the sixth gate and the first plate. The fourth gate and the fifth gate form a T-shaped structure, and a suspended semiconductor between the fourth gate and the fifth gate is located in a first quadrant of the T-shaped structure, which is closer to the sixth gate than a second quadrant of the T-shaped structure. A projection of the first plate and the suspended semiconductor on the substrate has an overlapping part.

20. A display device comprising the display substrate according to any one of claims 1-12. ​

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