Three-color micro-led device and manufacturing method therefor

Abstract

The present application relates to the technical field of light-emitting diodes (LEDs), and provides a three-color Micro-LED device and a manufacturing method therefor. The three-color Micro-LED device comprises a substrate (1), an n-type GaN layer (2), a mask layer (3), n-type GaN nanopillars (4), and a coating layer (100); each n-type GaN nanopillar (4) is arranged in a corresponding window of the mask layer (3) and extends away from the substrate (1); the coating layer (100) comprises a quantum well layer (5), an electron blocking layer (6), and a p-type GaN layer (7); the quantum well layer (5) is arranged on the outer surfaces of the n-type GaN nanopillars (4); the quantum well layer (5) comprises a Ga surface (92), an N surface (93), and an m / a surface (94) isolated from each other, and light emitted from the Ga surface (92), the N surface (93), and the m / a surface (94) has different wavelengths; the electron blocking layer (6) is arranged on the outer surface of the quantum well layer (5); and the p-type GaN layer (7) is arranged on the outer surface of the electron blocking layer (6). In the present application, the three-color Micro-LED device comprising a plurality of LED light-emitting structures is obtained, and each LED light-emitting structure comprises three p-type regions isolated from each other, so that the current density of a p-type electrode of each p-type region can be regulated and controlled, thereby assisting in adjustment of the brightness and the gray scale of light of different wavelengths, and ensuring the device performance.

Description

A tricolor Micro-LED device and its fabrication method

[0001] This application claims priority to Chinese Patent Application No. 202410671798.6, filed on May 28, 2024, which is incorporated herein by reference in its entirety. Technical Field

[0002] This application relates to the field of micro-light-emitting diode technology, for example to a three-color Micro-LED device and its fabrication method. Background Technology

[0003] With the continuous advancement of display technology, micro light-emitting diodes (Micro-LEDs) have gradually become an important development direction in the future display technology field due to their characteristics such as high brightness, high contrast, long lifespan, and low power consumption. The key to realizing the widespread application of Micro-LED technology in full-color displays lies in how to efficiently integrate RGB three-color Micro-LED chips on the same substrate. To achieve high-resolution full-color display effects, tens of thousands of tiny LEDs need to be precisely transferred from their original growth substrate to the target substrate; this technical process is called "mass transfer."

[0004] From a theoretical perspective, mass transfer technology offers the possibility of efficiently manufacturing Micro-LED displays, but it faces numerous technical challenges in practical operation. Firstly, ensuring color uniformity and consistency in the displayed image requires extremely high precision in the selection and placement of individual Micro-LEDs. Furthermore, when processing hundreds of millions of tiny LEDs, even a small damage rate can lead to significant defects and low yields; therefore, controlling the damage rate during the transfer process is also a technical issue.

[0005] Currently, one of the mainstream methods for achieving RGB full-color displays is to use InGaN materials to manufacture blue and green LEDs, while using InP materials to manufacture red LEDs. However, there is a material incompatibility issue between InGaN and InP-based LEDs. Due to the fundamental differences between InGaN-based and InP-based LEDs in terms of growth conditions, processing technology, and driving methods, integrating them into the same display system presents numerous challenges. For example, the mismatch in the thermal expansion coefficients of the two materials may lead to stress at different operating temperatures, severely affecting the reliability and lifespan of the device.

[0006] Given the complexity and cost of mass transfer technology, as well as the mismatch between InGaN and InP materials, researchers have explored a technique to directly stack RGB three-color quantum wells on the same substrate to integrate RGB three-color Micro-LEDs without relying on mass transfer technology. However, stacking quantum well layers of different wavelengths can lead to lattice mismatch and stress accumulation, thus affecting material quality and device performance. Furthermore, defects and non-radiative recombination centers that may appear at the interfaces of the stacked RGB three-color quantum wells can further reduce the device's luminous efficiency. Simultaneously, the stacked quantum well structure may also generate significant heat during operation; the accumulation and uneven distribution of heat will severely impact device performance and lifetime.

[0007] Based on this, this application provides a three-color Micro-LED device and its fabrication method to improve related technologies. Summary of the Invention

[0008] The purpose of this application is to provide a three-color Micro-LED device and its fabrication method, which can obtain a three-color Micro-LED device with multiple LED light-emitting structures, and each LED light-emitting structure has three mutually isolated p-type regions, so that the current density of the p-type electrode in each p-type region can be controlled, and the device performance can be avoided due to uneven heat distribution.

[0009] The objective of this application is achieved through the following technical solution:

[0010] In a first aspect, this application provides a tri-color Micro-LED device, comprising:

[0011] Substrate;

[0012] An n-type GaN layer is disposed on the substrate;

[0013] A mask layer is disposed on the n-type GaN layer, and the mask layer has multiple windows that expose part of the n-type GaN layer;

[0014] Multiple LED light-emitting structures, each LED light-emitting structure comprising: n-type GaN nanopillars and a coating layer, each n-type GaN nanopillar being disposed within a corresponding window and extending away from the substrate; the coating layer comprising:

[0015] A quantum well layer is disposed on the outer surface of the n-type GaN nanopillar; wherein the quantum well layer includes mutually isolated Ga facets, N facets and m / a facets, and light emitted from the Ga facets, the N facets and the m / a facets has different wavelengths;

[0016] An electron blocking layer is disposed on the outer surface of the quantum well layer;

[0017] A p-type GaN layer is disposed on the outer surface of the electron blocking layer.

[0018] Furthermore, the LED light-emitting structure also includes:

[0019] A p-type electrode is used to connect to the positive terminal of an external power supply; wherein, the p-type electrode includes a first p-type electrode, a second p-type electrode, and a third p-type electrode, the first p-type electrode being disposed on a p-type GaN layer located on the m / a plane; the second p-type electrode abutting against the p-type GaN layer located on the Ga plane and being disposed on the mask layer; the third p-type electrode abutting against the p-type GaN layer located on the N plane and being disposed on the mask layer;

[0020] An n-type electrode, disposed on the n-type GaN layer, is used to connect to the negative terminal of an external power supply.

[0021] Furthermore, the second p-type electrode includes a first sub-electrode and a second sub-electrode coupled to the first sub-electrode. The first sub-electrode is disposed on the mask layer, and the second sub-electrode is disposed on the first sub-electrode and abuts against the p-type GaN layer located on the Ga surface; and / or

[0022] The third p-type electrode includes a third sub-electrode and a fourth sub-electrode coupled to the third sub-electrode. The third sub-electrode is disposed on the mask layer, and the fourth sub-electrode is disposed on the third sub-electrode and abuts against the p-type GaN layer located on the N-plane.

[0023] Furthermore, the windows are multiple and arranged in a dot matrix pattern, each window is rectangular, the long side of the rectangle corresponds to the m / a plane direction of the n-type GaN layer, and the short side of the rectangle corresponds to the c plane direction and -c plane direction of the n-type GaN layer, respectively.

[0024] Furthermore, the length of the long side of the rectangle is 1 to 10 μm, the length of the short side of the rectangle is 100 to 500 nm, the distance between two adjacent windows along the long side of the rectangle is 1 to 5 μm, and the distance between two adjacent windows along the short side of the rectangle is 2 to 10 μm.

[0025] Furthermore, the area of ​​the Ga or N surface of the quantum well layer is larger than the area of ​​the non-polar sidewall surface.

[0026] Furthermore, the substrate is an r-plane sapphire substrate, an a / m-plane GaN substrate, or an a / m-plane AlN substrate; and / or

[0027] The thickness of the n-type GaN layer is 500 nm to 2 μm; and / or,

[0028] Furthermore, the thickness of the mask layer is 30–200 nm, and the material of the mask layer is SiNx, SiO2, or Al2O3;

[0029] The height of the n-type GaN nanopillars is 500–5000 nm;

[0030] Furthermore, the quantum well layer comprises alternating layers of InGaN and GaN with a cycle period of 1 to 10, wherein the thickness of the InGaN layer is 2 to 3 nm and the thickness of the GaN layer is 8 to 15 nm.

[0031] Furthermore, the thickness of the electron blocking layer is 10–30 nm, and the electron blocking layer is an AlGaN electron blocking layer;

[0032] Furthermore, the thickness of the p-type GaN layer is 50–300 nm.

[0033] Secondly, this application provides a method for fabricating a tri-color Micro-LED device, comprising the following steps:

[0034] An n-type GaN layer is epitaxially grown on a substrate, and a mask layer is deposited on the n-type GaN layer;

[0035] Multiple windows are opened on the mask layer to partially expose the n-type GaN layer, and n-type GaN nanopillars are epitaxially grown on the exposed n-type GaN layer.

[0036] A quantum well layer is grown on the outer surface of each of the n-type GaN nanopillars;

[0037] An electron blocking layer is grown on the outer surface of the quantum well layer, and a p-type GaN layer is grown on the outer surface of the electron blocking layer; wherein the quantum well layer, the electron blocking layer, and the p-type GaN layer form a cladding layer;

[0038] The cladding layer is etched to isolate the Ga, N, and m / a planes of the quantum well layer from each other, thereby obtaining the tricolor Micro-LED device.

[0039] The light emitted from the Ga surface, the N surface, and the m / a surface has different wavelengths.

[0040] Furthermore, forming the quantum well layer includes:

[0041] The quantum well layer is formed by alternately coating and growing 1 to 10 cycles of InGaN and GaN layers on the outer surface of the n-type GaN nanopillars.

[0042] The growth of the InGaN layer includes: under first growth conditions, introducing a first carrier gas and a first reaction source to grow an InGaN layer with a thickness of 2-3 nm; wherein the first growth conditions include a temperature of 700-800°C, a pressure of 200-600 mbar, a V / III ratio of 10000-40000 for the first reaction source, and the first carrier gas being N2; and / or,

[0043] The growth of the GaN layer includes: under a second growth condition, introducing a second carrier gas and a second reaction source to grow the GaN layer with a thickness of 8-15 nm; wherein the second growth condition includes a temperature of 830-950°C, a pressure of 200-600 mbar, a V / III ratio of 5000-20000 for the second reaction source, and the second carrier gas being N2.

[0044] Furthermore, the growth of the n-type GaN layer includes:

[0045] Under the third growth conditions, a third carrier gas and a third reaction source are introduced to epitaxially grow an n-type GaN layer with a thickness of 500 nm to 2 μm on the substrate; wherein the third growth conditions include: a temperature of 1000–1100 °C, a pressure of 100–400 mbar, a V / III ratio of 500–3000 for the third reaction source, and the third carrier gas being H2 or a mixture of H2 and N2; and / or,

[0046] The growth of the n-type GaN nanopillars includes: under fourth growth conditions, introducing a fourth carrier gas and a fourth reaction source, and growing the n-type GaN nanopillars with a height of 500–5000 nm; wherein, the fourth growth conditions include a temperature of 1000–1100 °C, a pressure of 50–200 mbar, a V / III ratio of 50–1000 for the fourth reaction source, and the fourth carrier gas being H2 or a mixture of H2 and N2; and / or,

[0047] The growth of the electron blocking layer includes: under fifth growth conditions, introducing a fifth carrier gas and a fifth reaction source to grow the electron blocking layer with a thickness of 10–30 nm; wherein the fifth growth conditions include a temperature of 950–1100 °C, a pressure of 100–200 mbar, a V / III ratio of 5000–10000 for the fifth reaction source, and the fifth carrier gas being H2 or a mixture of H2 and N2; and / or,

[0048] The growth of the p-type GaN layer includes: under the sixth growth conditions, introducing a sixth carrier gas and a sixth reaction source to grow the p-type GaN layer with a thickness of 50-300 nm; wherein, the sixth growth conditions include a temperature of 950-1100℃, a pressure of 100-400 mbar, a V / III ratio of 5000-20000 for the sixth reaction source, and the sixth carrier gas being H2 or a mixture of H2 and N2.

[0049] Furthermore, etching the coating layer includes:

[0050] Etch the r-face of the coating layer and the non-polar sidewall.

[0051] The tri-color Micro-LED device and its fabrication method disclosed in this application have at least the following advantages:

[0052] The fabrication method of this application can obtain a tricolor Micro-LED device with multiple LED light-emitting structures, and each LED light-emitting structure has three mutually isolated p-type regions. By adjusting the current density of the p-type electrode of each LED light-emitting structure, the brightness and grayscale of different wavelengths of light can be adjusted.

[0053] Furthermore, this application fabricates n-type GaN nanopillars with non-polar surfaces through selective area epitaxy, constructing three different polar surfaces: Ga, N, and m / a. This enables the integration of RGB three-color Micro-LED devices on a single n-type GaN nanopillar, significantly improving pixel integration density and facilitating the realization of smaller, higher-resolution Micro-LED devices, such as Micro-LED displays.

[0054] Furthermore, due to the special nature of the structure, the uniformity and density of the epitaxially grown material layers at the connection between the top and sides of the n-type GaN nanopillar are poor. This application can effectively prevent leakage and improve the reliability of the device by etching away the material layers that are covered by the epitaxial growth.

[0055] Furthermore, this application forms multiple LED light-emitting structures on the same substrate and constructs three mutually isolated p-type regions on different crystal planes of the n-type GaN nanopillars in each LED light-emitting structure. By utilizing the different incorporation efficiencies of In atoms in different crystal plane directions, the three colors of each LED light-emitting structure can be separately controlled, making it easier to control in terms of current driving and thermal management. Moreover, due to the sufficient strain relaxation of the n-type GaN nanopillars, the material structure characteristics and device performance will not be affected by stress accumulation when growing structures such as quantum well layers, and the situation where uneven heat distribution affects device performance can be avoided.

[0056] Furthermore, the manufacturing method of this application can reduce the process of transferring and assembling Micro-LEDs of different colors grown on different substrates, simplify the manufacturing process, improve production efficiency, and reduce costs. Attached Figure Description

[0057] The present application will be further described below with reference to the accompanying drawings and embodiments.

[0058] Figure 1 shows a schematic diagram of a structure of an embodiment of the tri-color Micro-LED device provided in this application;

[0059] Figure 2 shows a schematic diagram of the structure of the coating layer and nanopillars in the tricolor Micro-LED device provided in this application.

[0060] Figure 3 shows a schematic diagram of the structure of the mask layer provided in this application.

[0061] Figure 4 shows a schematic diagram of another embodiment of the tricolor Micro-LED device provided in this application.

[0062] Figure 5 shows a schematic flowchart of an embodiment of the fabrication method of the tricolor Micro-LED device provided in this application.

[0063] Figures 6A to 6E show cross-sectional schematic diagrams of the fabrication process of the tri-color Micro-LED device provided in this application.

[0064] Figure 7A shows a top view of Figure 6D.

[0065] Figure 7B shows a top view of Figure 6E.

[0066] Figure 8 shows a schematic diagram of the structure of the coating layer before and after etching provided in this application.

[0067] Figures 9A to 9G show cross-sectional schematic diagrams of the fabrication process of the P-type electrode in the tri-color Micro-LED device provided in this application.

[0068] Figure 10 shows a schematic diagram of the structure of a tricolor Micro-LED device in the prior art.

[0069] In the figure: 1. Substrate; 2. n-type GaN layer; 3. Mask layer; 4. n-type GaN nanopillars; 5. Quantum well layer; 6. Electron blocking layer; 7. p-type GaN layer; 801. First p-type electrode; 802. Second p-type electrode; 803. Third p-type electrode; 82. n-type electrode; 91. m / a plane; 92. Ga plane; 93. N plane; 94. r plane; 100. Coating layer; 201. First photoresist layer; 202. First electrode window; 203. Second photoresist layer; 204. Second electrode window; 802a. First sub-electrode; 802b. Second sub-electrode; 803a. Third sub-electrode; 803b. Fourth sub-electrode. Detailed Implementation

[0070] The technical solutions in this application will be described below with reference to the accompanying drawings and specific embodiments. It should be noted that, without conflict, the various embodiments or technical features described below can be arbitrarily combined to form new embodiments.

[0071] In the embodiments of this application, "at least one" refers to one or more, and "more than one" refers to two or more. "And / or" describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A alone, A and B simultaneously, or B alone, where A and B can be singular or plural. The character " / " generally indicates that the preceding and following related objects are in an "or" relationship. "At least one of the following" or similar expressions refer to any combination of these items, including any combination of single or plural items. For example, at least one of a, b, or c can represent: a, b, c, a and b, a and c, b and c, a and b and c, where a, b, and c can be single or multiple. It is worth noting that "at least one" can also be interpreted as "one or more".

[0072] It should also be noted that, in the embodiments of this application, the words "exemplary" or "for example" are used to indicate that they are examples, illustrations, or descriptions. Any implementation or design scheme described as "exemplary" or "for example" in the embodiments of this application should not be construed as being more preferred or advantageous than other implementations or design schemes. Specifically, the use of words such as "exemplary" or "for example" is intended to present the relevant concepts in a specific manner.

[0073] Please refer to Figures 1 and 2. Figure 1 is a structural schematic diagram of an embodiment of the three-color Micro-LED device provided in this application. Figure 2 is a structural schematic diagram of the cladding layer and nanopillars in the three-color Micro-LED device provided in this application. The three-color Micro-LED device includes: a substrate 1, an n-type GaN layer 2, a mask layer 3, and multiple LED light-emitting structures. The LED light-emitting structures include n-type GaN nanopillars 4 and a cladding layer 100.

[0074] The substrate 1 can be an r-plane sapphire substrate, an a / m-plane GaN substrate, or an a / m-plane AlN substrate to fabricate a tri-color Micro-LED device with an n-type GaN nanopillar 4 having a non-polar surface. The non-polar surface in the n-type GaN nanopillar 4 has good electron transport characteristics, which helps to improve the luminous efficiency and stability of the Micro-LED device, enabling the tri-color Micro-LED device to achieve richer color performance and improve display quality.

[0075] An n-type GaN layer 2 is disposed on the substrate 1, and the thickness of the n-type GaN layer 2 is 500 nm to 2 μm, for example, it can be 500 nm, 700 nm, 900 nm, 1.1 μm, 1.3 μm, 1.5 μm, 1.7 μm, 1.9 μm or 2 μm. Specifically, using r-plane sapphire, a / m-plane GaN or a / m-plane AlN as the substrate 1 can form a good lattice match with the n-type GaN layer 2, which can reduce lattice defects during the fabrication process and further improve the performance and reliability of the Micro-LED device.

[0076] A mask layer 3 is disposed on the n-type GaN layer 2. The thickness of the mask layer 3 is 30–200 nm, for example, it can be 30 nm, 50 nm, 70 nm, 90 nm, 110 nm, 130 nm, 150 nm, 170 nm, 190 nm, or 200 nm. The material of the mask layer 3 is preferably SiNx, SiO2, or Al2O3. Furthermore, multiple windows are formed on the mask layer 3 to partially expose the n-type GaN layer 2. Specifically, those skilled in the art can form multiple windows on the mask layer 3 according to actual needs, and arrange the multiple windows in a lattice-spaced manner to obtain a first exposed area arranged in a lattice-spaced manner. This not only achieves precise control and selective processing of the surface of the n-type GaN layer 2, but also protects the non-exposed parts of the n-type GaN layer 2, avoiding unnecessary processing or damage.

[0077] In application, windows can be set to any shape, such as: circle, ellipse, square, rectangle, triangle or polygon, etc. In one embodiment, as shown in Figure 3, each window is set to a rectangle, and the long side of the rectangle corresponds to the m / a plane 91 direction of the n-type GaN layer 2, and the short side of the rectangle corresponds to the c plane and -c plane directions of the n-type GaN layer 2, respectively.

[0078] Furthermore, the length of the long side of the rectangle, D1, is set to 1–10 μm, and the length of the short side, D2, is set to 100–500 nm. The distance between two adjacent windows along the long side of the rectangle, D3, is set to 1–5 μm, and the distance between two adjacent windows along the short side, D4, is set to 2–10 μm. For example, D1 can be 1 μm, 2 μm, 3 μm, 4 μm, 5 μm, 6 μm, 7 μm, 8 μm, 9 μm, or 10 μm. The luminescence density (D2) can be 100nm, 150nm, 200nm, 250nm, 300nm, 350nm, 400nm, 450nm, or 500nm; the luminescence density (D3) can be 1μm, 1.5μm, 2μm, 2.5μm, 3μm, 3.5μm, 4μm, 4.5μm, or 5μm; and the luminescence density (D4) can be 2μm, 3μm, 4μm, 5μm, 6μm, 7μm, 8μm, 9μm, or 10μm. In practical applications, because the Ga surface 92 and the N surface 93 have better electron transport characteristics, those skilled in the art can align the long side of the rectangular window with the Ga surface 92 and the N surface 93 of the n-type GaN layer 2. This ensures that the area of ​​the Ga surface 92 and the N surface 93 of the subsequently epitaxially grown n-type GaN nanopillars 4 is larger than the area of ​​the non-polar sidewalls, thereby improving the luminescence efficiency and stability of the n-type GaN nanopillars 4. n-type GaN nanopillars 4 are disposed within each window, and the extension direction of the n-type GaN nanopillars 4 is opposite to that of the substrate 1, forming n-type GaN nanopillars 4 with small size and high surface area; specifically, the height of the n-type GaN nanopillars 4 is 500 to 5000 nm, for example, it can be 500 nm, 1000 nm, 1500 nm, 2000 nm, 2500 nm, 3000 nm, 3500 nm, 4000 nm or 5000 nm.

[0079] The Ga surface 92, N surface 93 and m / a surface 91 of the coating layer 100 of this application are isolated from each other, and the area of ​​the Ga surface 92 or N surface 93 is larger than the area of ​​the non-polar sidewall surface.

[0080] In one embodiment, as shown in FIG2, the cladding layer 100 includes a quantum well layer 5, an electron blocking layer 6, and a p-type GaN layer 7.

[0081] Quantum well layer 5 is disposed on the outer surface of n-type GaN nanopillars 4. In application, quantum well layer 5 comprises alternating layers of InGaN and GaN layers with a cycle period of 1-10, for example, 1 cycle, 2 cycles, 3 cycles, 4 cycles, 5 cycles, 6 cycles, 7 cycles, 8 cycles, 9 cycles, or 10 cycles. Quantum well layer 5 comprises 1-10 layers of InGaN / GaN layers, enabling it to have multiple energy levels, thereby generating light of different wavelengths. Furthermore, by further adjusting the structure and composition of quantum well layer 5, multicolor emission of Micro-LED devices can be achieved to meet the needs of different application scenarios.

[0082] Furthermore, in order to ensure that the quantum well layer 5 has sufficient luminescence intensity while maintaining good stability and reliability, the thickness of the InGaN layer is set to 2-3 nm, and the thickness of the GaN layer is set to 8-15 nm; for example, the thickness of the InGaN layer can be 2 nm, 2.1 nm, 2.2 nm, 2.3 nm, 2.4 nm, 2.5 nm, 2.6 nm, 2.7 nm, 2.8 nm, 2.9 nm, or 3 nm, and the thickness of the GaN layer can be 8 nm, 8.5 nm, 9 nm, 9.5 nm, 10 nm, 10.5 nm, 11 nm, 10.5 nm, 11 nm, 11.5 nm, 12 nm, 12.5 nm, 13 nm, 13.5 nm, 14 nm, 14.5 nm, or 15 nm. In practical applications, the quantum well layer 5 includes mutually isolated Ga surface 92, N surface 93, and m / a surface 91. The light emitted from Ga surface 92, N surface 93, and m / a surface 91 has different wavelengths, resulting in the quantum well layer 5 having different emission wavelengths. In one embodiment, those skilled in the art can optimize the light-emitting performance of the device by controlling the area and ratio of different crystal surfaces, achieving more precise color control and higher color saturation.

[0083] An electron blocking layer 6 is disposed on the outer surface of the quantum well layer 5 to prevent electrons from overflowing from the n-type region to the p-type region of the device, thereby improving the device efficiency. Preferably, the electron blocking layer 6 is made of AlGaN and has a thickness of 10–30 nm, for example, 10 nm, 12 nm, 14 nm, 16 nm, 18 nm, 20 nm, 22 nm, 24 nm, 26 nm, 28 nm, or 30 nm.

[0084] The p-type GaN layer 7 is disposed on the outer surface of the electron blocking layer 6. The thickness of the p-type GaN layer 7 is 50 to 300 nm, for example, it can be 50 nm, 75 nm, 100 nm, 125 nm, 150 nm, 175 nm, 200 nm, 225 nm, 250 nm, 275 nm or 300 nm.

[0085] In one embodiment, as shown in FIG1, the tri-color Micro-LED device may further include p-type electrodes and n-type electrodes 82. Further, the p-type electrodes include a first p-type electrode 801, a second p-type electrode 802, and a third p-type electrode 803. The first p-type electrode 801 is disposed on the p-type GaN layer 7 located on the m / a plane 91; the second p-type electrode 802 abuts against the p-type GaN layer 7 located on the Ga plane 92 and is disposed on the mask layer 3; the third p-type electrode 803 abuts against the p-type GaN layer 7 located on the N plane 93 and is disposed on the mask layer 3. Preferably, the second p-type electrode 802 is disposed on the electron blocking layer 6 of the Ga plane 92, the first p-type electrode 801 is disposed on the electron blocking layer 6 of the m / a plane 91, and the third p-type electrode 803 is disposed on the electron blocking layer 6 of the N plane 93, and each p-type electrode is used to connect to the positive terminal of an external power supply. The n-type electrode 82 is disposed on the n-type GaN layer 2 and is used to connect to the negative terminal of an external power supply to form a complete current loop.

[0086] In one embodiment, as shown in FIG4, the second p-type electrode 802 includes a first sub-electrode and a second sub-electrode coupled to the first sub-electrode. The first sub-electrode is disposed on the mask layer 3, and the second sub-electrode is disposed on the first sub-electrode and abuts against the p-type GaN layer 7 located on the Ga surface 92. The third p-type electrode 803 includes a third sub-electrode and a fourth sub-electrode coupled to the third sub-electrode. The third sub-electrode is disposed on the mask layer 3, and the fourth sub-electrode is disposed on the third sub-electrode and abuts against the p-type GaN layer 7 located on the N surface 93.

[0087] In application, the entire device shares a single n-type electrode 82 to connect to the negative terminal of the external power supply, which simplifies the fabrication process and reduces the number of electrodes required. However, each crystal facet has an independent p-type electrode, allowing each p-type region of the LED light-emitting structure in the device to be independently connected to the positive terminal of the external power supply. Furthermore, when the second p-type electrode 802 of the Ga facet 92 of any LED light-emitting structure is connected to the positive terminal of the external power supply, the corresponding LED light-emitting structure emits blue light; when the third p-type electrode 803 of the N facet 93 of any LED light-emitting structure is connected to the positive terminal of the external power supply, the corresponding LED light-emitting structure emits red light; and when the first p-type electrode 801 of the m / a facet 91 of any LED light-emitting structure is connected to the positive terminal of the external power supply, the corresponding LED light-emitting structure emits green light. In application, when the p-type electrodes of the Ga facet 92, N facet 93, and m / a facet 91 of any LED light-emitting structure are all connected to the positive terminal of the external power supply, the corresponding LED light-emitting structure emits light of the corresponding color. In practical applications, the current density of each p-type electrode in each LED light-emitting structure of the controller can be adjusted according to actual needs to control the brightness and grayscale of different wavelengths of light.

[0088] In addition, this application introduces a method for fabricating a three-color Micro-LED device, which can obtain a three-color Micro-LED device with the above-mentioned technical features.

[0089] Please refer to Figures 5 and 6A-6E. Figure 5 is a flowchart illustrating an embodiment of the fabrication method of the tri-color Micro-LED device provided in this application. Figures 6A-6E are cross-sectional schematic diagrams illustrating the fabrication process of the tri-color Micro-LED device provided in this application. The fabrication method of this application includes the following steps:

[0090] Step S1: An n-type GaN layer 2 is epitaxially grown on substrate 1, and a mask layer 3 is deposited on the n-type GaN layer 2.

[0091] Step S1 includes steps S11 and S12.

[0092] Step S11: As shown in Figure 6A, an n-type GaN layer 2 is formed on the substrate 1.

[0093] Since the goal is to grow n-type GaN nanopillars 4 with non-polar surfaces, r-faced 94 sapphire, a / m-faced GaN, or a / m-faced AlN are selected as substrates 1. The n-type GaN layer 2 can be epitaxially grown on substrate 1 using methods such as metal-organic chemical vapor deposition (MOCVD), molecular beam epitaxy (MBE), or hydride vapor phase epitaxy (HVPE).

[0094] In one embodiment, under third growth conditions, a third carrier gas and a third reaction source are introduced to epitaxially grow an n-type GaN layer (2) on a substrate (1); wherein the third growth conditions include: a temperature of 1000–1100°C, a pressure of 100–400 mbar, a V / III ratio of 500–3000 for the third reaction source, and the third carrier gas being H2 or a mixture of H2 and N2; for example, the temperature can be 1000°C, 1010°C, 1020°C, 1030°C, 1040°C, 1050°C, 1060°C, 1070°C, etc. The temperature can be ℃, 1080℃, 1090℃ or 1100℃, and the pressure can be 100mbar, 125mbar, 150mbar, 175mbar, 200mbar, 225mbar, 250mbar, 300mbar, 325mbar, 350mbar, 375mbar or 400mbar. The V / III ratio of the third reaction source can be 500, 750, 1000, 1025, 1500, 1750, 2000, 2250, 2500, 2750 or 3000.

[0095] It is worth noting that the V / III ratio is the stoichiometric ratio of Group V elements to Group III elements.

[0096] Furthermore, the materials required to form the n-type GaN layer 2 include: trimethylgallium (TMGa), SiH4, and NH3. The flow rate of TMGa is 20–100 sccm, the flow rate of NH3 is 3000–12000 sccm, and the flow rate of SiH4 is 0.2–2 sccm. For example, the flow rate of TMGa can be 20 sccm, 30 sccm, 40 sccm, 50 sccm, 60 sccm, 70 sccm, 80 sccm, 90 sccm, or 100 sccm; the flow rate of NH3 can be 3000 sccm, 4000 sccm, 5000 sccm, 6000 sccm, 7000 sccm, 8000 sccm, 9000 sccm, 10000 sccm, 11000 sccm, or 12000 sccm; and the flow rate of SiH4 can be 0.2 sccm, 0.4 sccm, 0.6 sccm, 0.8 sccm, 1 sccm, 1.2 sccm, 1.4 sccm, 1.6 sccm, 1.8 sccm, or 2 sccm. Those skilled in the art can set the thickness of the n-type GaN layer 2 to 500 nm to 2 μm according to specific application requirements, such as device performance and material quality.

[0097] In one embodiment, after epitaxial growth is completed, those skilled in the art can continue to perform steps such as annealing or surface treatment to further improve the quality and performance of the n-type GaN layer 2.

[0098] The beneficial effects of the above technical solution are as follows: using r-plane 94 sapphire, a / m-plane GaN or a / m-plane AlN as substrate 1 can form a good lattice match with n-type GaN layer 2, which can reduce lattice defects in the fabrication process and further improve the performance and reliability of Micro-LED devices.

[0099] Step S12: As shown in Figure 6A, a mask layer 3 is formed on the n-type GaN layer 2.

[0100] Based on plasma-enhanced chemical vapor deposition (PECVD), low-pressure chemical vapor deposition (LPCVD), atomic layer deposition (ALD), or magnetron sputtering, this method utilizes SiN, which possesses both chemical and thermal stability. xMaterials such as SiO2 or Al2O3 are used to deposit a mask layer 3 on the n-type GaN layer 2 to protect the substrate 1 and the n-type GaN layer 2.

[0101] Furthermore, in order to ensure that the mask layer 3 has sufficient stability and uniformity to meet the requirements of subsequent nanopillar growth, the thickness of the mask layer 3 is set to 30-200 nm. Those skilled in the art can adjust the thickness of the mask layer 3 according to actual needs.

[0102] Step S2: Open multiple windows on the mask layer 3 to partially expose the n-type GaN layer 2, and epitaxially grow n-type GaN nanopillars 4 on the exposed n-type GaN layer 2.

[0103] Step S2 includes steps S21 and S22.

[0104] Step S21: Based on photolithography or etching technology, multiple windows are opened on the mask layer 3 to partially expose the n-type GaN layer 2, as shown in Figure 6B.

[0105] When multiple windows are opened, they are arranged in a lattice-spaced pattern to obtain a first exposed area with lattice-spaced patterns. Furthermore, the windows can be set to any shape, such as: circle, ellipse, square, rectangle, triangle, polygon, etc. Preferably, each window is set to a rectangle to control the area of ​​each crystal facet of the subsequent epitaxial growth of n-type GaN nanopillars 4.

[0106] In one embodiment, based on photolithography or etching technology, a plurality of rectangular windows arranged in a lattice-like pattern are formed on the mask layer 3, with the long side of each rectangular window corresponding to the m / a plane 91 direction of the n-type GaN layer 2, and the short side directions corresponding to the c-plane and -c-plane directions of the n-type GaN layer 2, respectively, as shown in Figure 3. Further, the length D1 of the long side of the rectangle is set to 1–10 μm, the length D2 of the short side of the rectangle is set to 100–500 nm, and the distance D3 between two adjacent windows along the long side of the rectangle is set to 1–5 μm, and the distance D4 between two adjacent windows along the short side of the rectangle is set to 2–10 μm. In application, those skilled in the art can align the long sides of the rectangular windows with the Ga plane 92 and N plane 93 of the n-type GaN layer 2, so that the area of ​​the Ga plane 92 and N plane 93 of the subsequently epitaxially grown n-type GaN nanopillars 4 is larger than the area of ​​the non-polar sidewalls.

[0107] Step S22: Based on the MOCVD method, n-type GaN nanopillars 4 are epitaxially grown on the n-type GaN layer 2 exposed in each window, as shown in Figure 6C.

[0108] Under the fourth growth conditions, a fourth carrier gas and a fourth reaction source are introduced to grow n-type GaN nanopillars 4. The fourth growth conditions include a temperature of 1000–1100 °C, a pressure of 50–200 mbar, a V / III ratio of 50–1000 for the fourth reaction source, and the fourth carrier gas being H2 or a mixture of H2 and N2. For example, the temperature can be 1000 °C, 1010 °C, 1020 °C, 1030 °C, 1040 °C, or 1000 mbar. The temperatures can be 050℃, 1060℃, 1070℃, 1080℃, 1090℃ or 1100℃, and the pressures can be 50mbar, 75mbar, 100mbar, 125mbar, 150mbar, 175mbar or 200mbar. The V / III ratio of the fourth reaction source can be 50, 100, 200, 300, 400, 500, 600, 700, 800, 900 or 1000.

[0109] Furthermore, the materials used to grow n-type GaN nanopillars include: TMGa, SiH4, and NH3. The flow rates of the source materials are: TMGa flow rate of 20–100 sccm, NH3 flow rate of 200–3000 sccm, and SiH4 flow rate of 0.2–2 sccm; for example, TMGa flow rates of 20 sccm, 30 sccm, 40 sccm, 50 sccm, 60 sccm, 70 sccm, 80 sccm, 90 sccm, or 100 sccm, and NH3 flow rates of 200 sccm, 300 sccm, 400 sccm, or 500 sccm. The SiH4 flow rates are 0.2 sccm, 0.4 sccm, 0.6 sccm, 0.8 sccm, 1 sccm, 1.2 sccm, 1.4 sccm, 1.6 sccm, 1.8 sccm, or 2 sccm, with values ​​ranging from 750 sccm, 1000 sccm, 1250 sccm, 1500 sccm, 1750 sccm, 2000 sccm, 2250 sccm, 2500 sccm, 2750 sccm, or 3000 sccm, respectively. Those skilled in the art can set the height of the n-type GaN nanopillars 4 to 5000 nm according to specific application requirements, such as device performance and material quality.

[0110] In one embodiment, after epitaxial growth is completed, those skilled in the art can characterize and test the obtained n-type GaN nanopillars 4 to evaluate whether their quality, structure, and performance meet expectations. For example, techniques such as scanning electron microscopy (SEM), transmission electron microscopy (TEM), or X-ray diffraction (XRD) can be used to analyze the morphology and structure of the n-type GaN nanopillars 4, and electrical testing methods can be used to evaluate the conductivity of the n-type GaN nanopillars 4.

[0111] By forming multiple rectangular windows arranged in a lattice on the mask layer 3, precise control and selective processing of the surface of the n-type GaN layer 2 can be achieved. Since the Ga facet 92 and the N facet 93 have better electron transport characteristics, aligning the long sides of the rectangular windows with the Ga facet 92 and the N facet 93 of the n-type GaN layer 2 ensures that the area of ​​the Ga facet 92 and the N facet 93 of the subsequently epitaxially grown n-type GaN nanopillars 4 is larger than the area of ​​the non-polar sidewalls, thus improving the luminous efficiency and stability of the n-type GaN nanopillars 4. Furthermore, the n-type GaN nanopillars 4, with their smaller size and higher surface area, can more effectively absorb and emit light, thereby improving the luminous efficiency of the device.

[0112] Step S3: A quantum well layer 5 is grown on the outer surface of each n-type GaN nanopillar 4.

[0113] Based on the MOCVD method, 1-10 cycles of InGaN and GaN layers are alternately grown on the outer surface of n-type GaN nanopillars 4 to form 1-10 InGaN / GaN layers, resulting in a quantum well layer 5 (see Figures 6D, 7A, and 2). Furthermore, the quantum well layer 5 is grown not only on the top surface of the n-type GaN nanopillars 4 but also on their sides, thus completely covering the outer surface of the n-type GaN nanopillars 4, increasing the luminescent area of ​​the quantum well, and improving the luminous efficiency and brightness of the device.

[0114] In one embodiment, under first growth conditions, a first carrier gas and a first reaction source are introduced to grow an InGaN layer; wherein, the first growth conditions include a temperature of 700–800°C, a pressure of 200–600 mbar, and a V / III ratio of 10000–40000 for the first reaction source. For example, the temperature can be 700°C, 710°C, 720°C, 730°C, 740°C, 750°C, 760°C, 770°C, 780°C, 790°C, or 800°C, and the pressure can be 200 mbar. The first reaction source can have a V / III ratio of 10000, 12500, 15000, 17500, 20000, 22500, 25000, 27500, 30000, 32500, 35000, 37500, or 40000; the first carrier gas is N2.

[0115] Under the second growth conditions, a second carrier gas and a second reaction source are introduced to grow a GaN layer. The second growth conditions include a temperature of 830–950°C, a pressure of 200–600 mbar, and a V / III ratio of 5000–20000 for the second reaction source. For example, the temperature can be 830°C, 850°C, 870°C, 890°C, 910°C, 930°C, or 950°C; the pressure can be 200 mbar, 250 mbar, 300 mbar, 350 mbar, 400 mbar, 450 mbar, 500 mbar, 550 mbar, or 600 mbar; and the V / III ratio of the first reaction source can be 5000, 7500, 10000, 12500, 15000, 17500, or 20000. The second carrier gas is N2.

[0116] Furthermore, the materials required for growing the InGaN layer include: triethylgallium (TEGa), trimethylindium (TMIn), and NH3. The Ga-In ratio is 0.1 to 0.4; for example, the TEGa flow rate can be 20 sccm, 30 sccm, 40 sccm, 50 sccm, 60 sccm, 70 sccm, or 80 sccm, the TMIn flow rate can be 50 sccm, 60 sccm, 70 sccm, 80 sccm, 90 sccm, 100 sccm, 110 sccm, 120 sccm, 130 sccm, 140 sccm, or 150 sccm, and the NH3 flow rate can be 5000 sccm, 7500 sccm, 10000 sccm, 12500 sccm, 15000 sccm, 17500 sccm, or 20000 sccm. The flow rate for TEGa is 20–80 sccm, for TMIn it is 50–150 sccm, and for NH3 it is 5000–20000 sccm. Those skilled in the art can set the thickness of the InGaN layer to 2–3 nm according to specific application requirements.

[0117] The materials required for growing the GaN layer include TMGa and NH3. The TMGa flow rate is 20–50 sccm, and the NH3 flow rate is 5000–20000 sccm; for example, the TMGa flow rate can be 20 sccm, 25 sccm, 30 sccm, 35 sccm, 40 sccm, 45 sccm, or 50 sccm, and the NH3 flow rate can be 5000 sccm, 7500 sccm, 10000 sccm, 12500 sccm, 15000 sccm, 17500 sccm, or 20000 sccm. Those skilled in the art can set the GaN layer thickness to 8–15 nm according to specific application requirements.

[0118] In one embodiment, after growth is complete, those skilled in the art can perform subsequent processing on the device, such as annealing or passivation, to further improve the device's performance and stability.

[0119] By fabricating multiple InGaN / GaN layers, the quantum well layer 5 possesses multiple energy levels, enabling the generation of light at different wavelengths and achieving multicolor emission in Micro-LED devices to meet the needs of various applications. Furthermore, due to the energy level difference between In and Ga, the quantum well layer 5 with InGaN / GaN layers can form an effective quantum confinement effect for electrons and holes, thereby improving the device's luminous efficiency. Moreover, by precisely controlling the thickness and composition of the quantum well layer 5, the optoelectronic performance of the device can be effectively tuned.

[0120] Step S4: An electron blocking layer 6 is grown on the outer surface of the quantum well layer 5, and a p-type GaN layer 7 is grown on the outer surface of the electron blocking layer 6; wherein, the quantum well layer 5, the electron blocking layer 6 and the p-type GaN layer 7 form a cladding layer 100.

[0121] Step S4 includes steps S41 and S42.

[0122] Step S41: Form electron blocking layer 6.

[0123] Using the MOCVD method, an electron blocking layer 6 is grown on the outer surface of the quantum well layer 5, as shown in Figures 6D, 7A, and 2. Specifically, the electron blocking layer 6 is made of AlGaN and is grown not only on the top surface of the quantum well layer 5 but also on its sides, thus completely covering the outer surface of the quantum well layer 5. This prevents electrons from overflowing from the n-type region to the p-type region of the device, thereby improving the device efficiency.

[0124] In one embodiment, under the fifth growth conditions, a fifth carrier gas and a fifth reaction source are introduced to grow an electron blocking layer 6; wherein the fifth growth conditions include a temperature of 950–1100°C, a pressure of 100–200 mbar, and a V / III ratio of 5000–10000 for the fifth reaction source. For example, the temperature can be 950°C, 970°C, 990°C, 1010°C, 1030°C, 1050°C, 1070°C, 1090°C, or 1100°C, and the pressure can be 1… 00mbar, 110mbar, 120mbar, 130mbar, 140mbar, 150mbar, 160mbar, 170mbar, 180mbar, 190mbar or 200mbar; the V / III ratio of the fifth reaction source can be 5000, 5500, 6000, 6500, 7000, 7500, 8000, 8500, 9000, 9500 or 10000; the fifth carrier gas is H2 or a mixture of H2 and N2.

[0125] Furthermore, the materials required to form the electron blocking layer 6 include: TMGa, trimethylaluminum (TMAl), and NH3. The flow rates of the source materials are: TMGa flow rate of 20–100 sccm, TMAl flow rate of 20–100 sccm, and NH3 flow rate of 2000–5000 sccm; for example, the TMGa flow rate can be 20 sccm, 30 sccm, 40 sccm, 50 sccm, 60 sccm, 70 sccm, 80 sccm, 90 sccm, or 100 sccm, the TMAl flow rate can be 20 sccm, 30 sccm, 40 sccm, 50 sccm, 60 sccm, 70 sccm, 80 sccm, 90 sccm, or 100 sccm, and the NH3 flow rate can be 2000 sccm, 2500 sccm, 3000 sccm, 3500 sccm, 4000 sccm, 4500 sccm, or 5000 sccm. Those skilled in the art can set the thickness of the electron blocking layer 6 to 10–30 nm according to specific application requirements.

[0126] Step S42: Form a p-type GaN layer 7.

[0127] Based on epitaxial growth technology, a p-type GaN layer 7 is grown on the outer surface of the electron blocking layer 6, as shown in Figures 2, 6D, and 7A. Furthermore, the p-type GaN layer 7 is grown not only on the top surface of the electron blocking layer 6, but also on the side surface of the electron blocking layer 6, thereby completely covering the outer surface of the electron blocking layer 6.

[0128] In one embodiment, under the sixth growth conditions, a sixth carrier gas and a sixth reaction source are introduced to grow a p-type GaN layer 7; wherein, the sixth growth conditions include a temperature of 950–1100°C, a pressure of 100–400 mbar, and a V / III ratio of the sixth reaction source of 5000–20000. For example, the temperature can be 950°C, 970°C, 990°C, 1010°C, 1030°C, 1050°C, 1070°C, 1090°C, or 1100°C, the pressure can be 100 mbar, 150 mbar, 200 mbar, 250 mbar, 300 mbar, 350 mbar, or 400 mbar, and the V / III ratio of the sixth reaction source can be 5000, 7500, 10000, 12500, 15000, 17500, or 20000; the sixth carrier gas is H2 or a mixture of H2 and N2.

[0129] Furthermore, the materials required to form the p-type GaN layer 7 include: TMGa, NH3, and Mg2+ (CP2Mg). The TMGa flow rate is 20–100 sccm, the NH3 flow rate is 1000–5000 sccm, and the CP2Mg flow rate is 100–400 sccm; for example, the TMGa flow rate can be 20 sccm, 30 sccm, 40 sccm, 50 sccm, 60 sccm, 70 sccm, 80 sccm, 90 sccm, or 100 sccm, the NH3 flow rate can be 1000 sccm, 1500 sccm, 2000 sccm, 2500 sccm, 3000 sccm, 3500 sccm, 4000 sccm, 4500 sccm, or 5000 sccm, and the CP2Mg flow rate can be 100 sccm, 150 sccm, 200 sccm, 250 sccm, 300 sccm, 350 sccm, or 400 sccm. Those skilled in the art can set the thickness of the p-type GaN layer 7 to 50–300 nm according to specific application requirements.

[0130] In one embodiment, after growth is complete, those skilled in the art can perform subsequent processing on the device, such as annealing, cleaning, and packaging, to further improve the device's performance and stability.

[0131] The p-type GaN layer is the p-type conductive region of a tri-color LED device, and its quality significantly impacts device performance. In this step, the thickness of the p-type GaN layer is controlled between 50 and 300 nm, a range that ensures sufficient conductivity and luminous efficacy. The growth temperature is set between 950 and 1100 °C, the pressure range is slightly wider (100–400 mbar), the V / III ratio is 5000–20000, and the carrier gas is H2 (or a mixture of H2 and N2). These parameters are chosen to optimize the crystal quality and electrical properties of the p-type GaN layer. During growth, strict control of the temperature and pressure within the reaction chamber, as well as the flow rate and ratio of the source material, is necessary to ensure uniform and consistent growth. Furthermore, real-time monitoring and adjustment of the growth process are required to address any potential anomalies.

[0132] Step S5: Etch the cladding layer 100 to isolate the Ga surface 92, N surface 93 and m / a surface 91 of the quantum well layer 5 from each other, to obtain a three-color Micro-LED device, wherein the light emitted from the Ga surface 92, N surface 93 and m / a surface 91 has different wavelengths.

[0133] Referring to Figures 1, 6E, and 8, based on etching technology, the connection between the top and side of the n-type GaN nanopillar 4 and the coating layer 100 of the non-polar sidewall are etched to expose the n-type GaN nanopillar 4 and isolate the Ga surface 92, N surface 93, and m / a surface 91 of the quantum well layer 5 from each other to obtain a three-color Micro-LED device.

[0134] It is worth noting that the r-plane of the cladding layer 100 is an inclined plane, namely the four planes BCGF, CDHG, DAEH, and ABFE in Figure 8(a); EFIV is the Ga plane, and GHKK is the N plane (or, EFIV is the N plane, and GHKK is the Ga plane). The non-polar sidewalls of the cladding layer 100 refer to the two sidewalls FGJI and EHKV of the cladding layer 100. After etching the r-plane and the non-polar sidewalls of the cladding layer 100, Figure 8(b) is obtained. After etching, the MNSQ plane is flush with the CBWR plane, and the LOTP plane is flush with the ADVU plane.

[0135] Due to the unique structure, the uniformity and density of the material layers epitaxially grown on the r-plane 94 at the junction of the top and sides of the n-type GaN nanopillar 4 are poor. Etching away this portion of the encapsulated material layer can effectively prevent leakage. In one embodiment, those skilled in the art can optimize the luminescent performance of the device by controlling the area and ratio of different crystal planes, achieving more precise color control and higher color saturation.

[0136] The photolithography process of this application may include processes such as resist coating, exposure, development, and resist removal; the etching process may be a dry etching process, such as inductively coupled plasma (ICP) etching, but is not limited to this. The gas used in the ICP process may be chlorine and / or hydrogen chloride. The power of ICP etching is 600–1000 W, the pressure is 2–5 Pa, and the voltage is 100–200 V; for example, the power may be 600 W, 650 W, 700 W, 750 W, 800 W, 850 W, 900 W, 950 W, or 1000 W, the pressure may be 2 Pa, 2.5 Pa, 3 Pa, 3.5 Pa, 4 Pa, 4.5 Pa, or 5 Pa, and the voltage may be 100 V, 110 V, 120 V, 130 V, 140 V, 150 V, 160 V, 170 V, 180 V, 190 V, or 200 V. During the etching process: Referring to Figure 6E and Figure 7B, the first photolithography etching is performed on the r-plane 94, with an etching depth not less than the growth thickness of the coating layer 100. After etching, the remaining photoresist is removed. Referring to Figure 1 and Figure 6E, the second photolithography etching is performed on two non-polar sides until the n-type GaN nanopillars 4 are exposed. After etching, the remaining photoresist is removed.

[0137] In practical applications, the fabrication method of tri-color Micro-LED devices also includes the following steps:

[0138] Step S6: Forming electrodes.

[0139] Using physical vapor deposition or sputtering methods, conductive materials are used to deposit a first p-type electrode 801 to a third p-type electrode 803 on each p-type GaN layer 7, and an n-type electrode 82 is deposited on the n-type GaN layer 2, as shown in Figure 1.

[0140] In application, the entire device shares a single n-type electrode 82 to connect to the negative terminal of the external power supply, which simplifies the fabrication process and reduces the number of electrodes required. However, each crystal facet has an independent p-type electrode, allowing the p-type region of each LED light-emitting structure in the device to be independently connected to the positive terminal of the external power supply. Furthermore, when the p-type electrode 81 of the Ga facet 92 of any LED light-emitting structure is connected to the positive terminal of the external power supply, the corresponding LED light-emitting structure emits blue light; when the p-type electrode 81 of the N facet 93 of any LED light-emitting structure is connected to the positive terminal of the external power supply, the corresponding LED light-emitting structure emits red light; and when the p-type electrode 81 of the m / a facet 91 of any LED light-emitting structure is connected to the positive terminal of the external power supply, the corresponding LED light-emitting structure emits green light. In application, when the p-type electrodes 81 of the Ga facet 92, N facet 93, and m / a facet 91 of any LED light-emitting structure are all connected to the positive terminal of the external power supply, the corresponding LED light-emitting structure emits light of the corresponding color. In practical applications, the current density of each p-type electrode 81 of each LED light-emitting structure in the control device can be adjusted according to actual needs to control the brightness and grayscale of different wavelengths of light.

[0141] In one embodiment, the following method can be used to fabricate the first p-type electrode 801 to the third p-type electrode 803:

[0142] (A) As shown in Figure 9A, a first photoresist layer 201 is formed on the surface of the device obtained in step S5.

[0143] (B) As shown in Figure 9B, the first photoresist layer 201 is photolithographically etched to form the first electrode window 202.

[0144] (C) As shown in Figure 9C, electrode material is deposited in the first electrode window 202 to form a first p-type electrode 801, a first sub-electrode 802a and a third sub-electrode 803a.

[0145] (D) As shown in Figure 9D, a second photoresist layer 203 is formed on the surface of the device obtained in step (D).

[0146] (E) As shown in Figure 9E, the second photoresist layer 203 is photolithographically etched to form the second electrode window 204.

[0147] (F) As shown in Figure 9F, electrode material is deposited in the second electrode window 204 to form the second sub-electrode 802b and the fourth sub-electrode 803b.

[0148] (G) Remove the first photoresist layer 201 and the second photoresist layer 203 to finally obtain the second p-type electrode 802 and the third p-type electrode 803, as shown in Figure 9G.

[0149] In one embodiment, after the electrode fabrication is completed, those skilled in the art can further package and test the device, and then apply it to various lighting and display devices.

[0150] Example 1:

[0151] Referring to Figures 2 and 4, this application provides a method for fabricating a three-color Micro-LED device, which includes the following steps:

[0152] Step S1: Provide an r-plane sapphire substrate, use the MOCVD method, set the temperature to 1000℃ and the pressure to 100mbar, introduce TMGa and NH3 as reaction sources (V / III ratio of 500), SiH4 as doping source and H2 as carrier gas, and epitaxially grow an n-type GaN layer 2 with a thickness of 500nm on the substrate 1.

[0153] Step S2: Deposit a mask layer 3 with a thickness of 30 nm on the n-type GaN layer 2 using the PECVD method.

[0154] Step S3: Based on photolithography, multiple windows are opened on the mask layer 3 to partially expose the n-type GaN layer 2. The window shape is rectangular, with the long side of the rectangle having a length of 1 μm and the short side having a length of 100 nm. The distance between two adjacent windows along the long side of the rectangle is 1 μm, and the distance between two adjacent windows along the short side of the rectangle is 2 μm.

[0155] Step S4: Using the MOCVD method, the temperature is set to 1000℃ and the pressure to 50mbar. TMGa and NH3 are introduced as reaction sources (V / III ratio is 50), SiH4 is introduced as a doping source, and H2 is introduced as a carrier gas. n-type GaN nanopillars 4 with a height of 500nm are epitaxially grown on the n-type GaN layer 2 exposed in each window.

[0156] Step S5: Using the MOCVD method with N2 as the carrier gas, InGaN and GaN layers are sequentially coated and grown on the outer surface of the n-type GaN nanopillar 4 to form a quantum well layer 5.

[0157] The InGaN layer has a thickness of 2nm. The growth conditions of the InGaN layer are as follows: the temperature is set at 700℃, the pressure is set at 200mbar, TMI, TEGa and NH3 are introduced as reaction sources (V / III ratio is 10000), and N2 is used as carrier gas.

[0158] The GaN layer has a thickness of 8 nm. The growth conditions for the GaN layer are: temperature of 830℃, pressure of 200 mbar, TMGa and NH3 as reaction sources (V / III ratio of 5000), and N2 as carrier gas.

[0159] Step S6: Using the MOCVD method, the temperature is set to 950℃ and the pressure to 100mbar. TMAl, TMGa and NH3 are introduced as reaction sources (V / III ratio is 5000), and H2 is used as the carrier gas to grow an electron blocking layer 6 with a thickness of 10nm on the outer surface of the quantum well layer 5.

[0160] Step S7: Based on epitaxial growth technology, the temperature is set to 950℃ and the pressure to 100mbar. TMGa and NH3 are introduced as reaction sources (V / III ratio is 5000), CP2Mg is used as a doping source, and H2 is used as a carrier gas. A p-type GaN layer 7 with a thickness of 50nm is grown on the outer surface of the electron blocking layer 6.

[0161] Step S8: Using etching technology, the connection between the top and side of the n-type GaN nanopillar 4 and the coating layer 100 of the non-polar sidewall are etched to expose the n-type GaN nanopillar 4 and isolate the Ga surface 92, N surface 93 and m / a surface 91 of the quantum well layer 5 from each other.

[0162] Step S9: Using physical vapor deposition or sputtering, deposit p-type electrodes on each p-type GaN layer 7 and n-type electrodes 82 on the n-type GaN layer 2 to obtain a tri-color Micro-LED device.

[0163] Example 2

[0164] Referring to Figures 2 and 4, this application provides a method for fabricating a three-color Micro-LED device, which includes the following steps:

[0165] Step S1: Provide an m-plane GaN substrate, use the MOCVD method, set the temperature to 1050℃ and the pressure to 250mbar, introduce TMGa and NH3 as reaction sources (V / III ratio of 1750), SiH4 as doping source, and H2 and N2 as carrier gases, and epitaxially grow an n-type GaN layer 2 with a thickness of 1.25μm on the substrate 1.

[0166] Step S2: Using the PECVD method, a mask layer 3 with a thickness of 115 nm is deposited on the n-type GaN layer 2.

[0167] Step S3: Based on photolithography, multiple windows are opened on the mask layer 3 to partially expose the n-type GaN layer 2. The window shape is rectangular, with the long side of the rectangle having a length of 5 μm and the short side having a length of 300 nm. The distance between two adjacent windows along the long side of the rectangle is 2.5 μm, and the distance between two adjacent windows along the short side of the rectangle is 6 μm.

[0168] Step S4: Using the MOCVD method, the temperature is set to 1050℃ and the pressure to 125mbar. TMGa and NH3 are introduced as reaction sources (V / III ratio of 525), SiH4 is introduced as a doping source, and H2 and N2 are introduced as carrier gases. n-type GaN nanopillars 4 with a height of 2750nm are epitaxially grown on the n-type GaN layer 2 exposed in each window.

[0169] Step S5: Using the MOCVD method with N2 as the carrier gas, InGaN and GaN layers are alternately coated and grown on the outer surface of the n-type GaN nanopillars 4, with a cycle period of 5, to form a quantum well layer 5.

[0170] The InGaN layer has a thickness of 2.5 nm. The growth conditions of the InGaN layer are as follows: the temperature is set at 750℃, the pressure is set at 400 mbar, and TMI, TEGa, and NH3 are introduced as reaction sources. The V / III ratio of the reaction sources is 35000.

[0171] The GaN layer has a thickness of 11.5 nm. The growth conditions for the GaN layer are: a temperature of 890℃, a pressure of 400 mbar, and the introduction of TMGa and NH3 as reaction sources. The V / III ratio of the reaction sources is 12500.

[0172] Step S6: Using the MOCVD method, the temperature is set to 1025℃ and the pressure to 150mbar. TMAl, TMGa and NH3 are introduced as reaction sources (V / III ratio is 7500), and H2 and N2 are used as carrier gases to grow an electron blocking layer 6 with a thickness of 20nm on the outer surface of the quantum well layer 5.

[0173] Step S7: Based on epitaxial growth technology, the temperature is set to 1025℃ and the pressure to 250mbar. TMGa and NH3 are introduced as reaction sources (V / III ratio is 12500), CP2Mg is used as a doping source, and H2 and N2 are used as carrier gases. A p-type GaN layer 7 with a thickness of 175nm is grown on the outer surface of the electron blocking layer 6.

[0174] Step S8: Using etching technology, the connection between the top and side of the n-type GaN nanopillar 4 and the coating layer 100 of the non-polar sidewall are etched to expose the n-type GaN nanopillar 4 and isolate the Ga surface 92, N surface 93 and m / a surface 91 of the quantum well layer 5 from each other.

[0175] Step S9: Using physical vapor deposition or sputtering, deposit p-type electrodes 81 on each p-type GaN layer 7 and n-type electrodes 82 on each n-type GaN layer 2 to obtain a tri-color Micro-LED device.

[0176] Example 3

[0177] Referring to Figures 2 and 4, this application provides a method for fabricating a three-color Micro-LED device, which includes the following steps:

[0178] Step S1: Provide an m-plane AlN substrate, use the MOCVD method, set the temperature to 1100℃ and the pressure to 400mbar, introduce TMGa and NH3 as reaction sources (V / III ratio of 3000), use SiH4 as doping source, and use H2 and N2 as carrier gases to epitaxially grow an n-type GaN layer 2 with a thickness of 2μm on the substrate 1.

[0179] Step S2: Deposit a mask layer 3 with a thickness of 200 nm on the n-type GaN layer 2 using the PECVD method.

[0180] Step S3: Based on photolithography, multiple windows are opened on the mask layer 3 to partially expose the n-type GaN layer 2. The window shape is rectangular, with the long side of the rectangle being 10 μm and the short side being 500 nm. The distance between two adjacent windows along the long side of the rectangle is 5 μm, and the distance between two adjacent windows along the short side of the rectangle is 10 μm.

[0181] Step S4: Using the MOCVD method, the temperature is set to 1100℃ and the pressure to 200mbar. TMGa and NH3 are introduced as reaction sources (V / III ratio of 1000), SiH4 is introduced as a doping source, and H2 and N2 are introduced as carrier gases. n-type GaN nanopillars 4 with a height of 5000nm are epitaxially grown on the n-type GaN layer 2 exposed in each window.

[0182] Step S5: Using the MOCVD method with N2 as the carrier gas, InGaN and GaN layers are alternately coated and grown on the outer surface of n-type GaN nanopillars 4, with a cycle period of 10, to form a quantum well layer 5.

[0183] The InGaN layer is 3 nm thick. The growth conditions of the InGaN layer are: temperature of 800℃, pressure of 600 mbar, TMI, TEGa and NH3 are introduced as reaction sources, and the V / III ratio of the reaction sources is 40000.

[0184] The GaN layer is 15 nm thick. The growth conditions for the GaN layer are: temperature 950℃, pressure 600 mbar, TMGa and NH3 are introduced as reaction sources, and the V / III ratio of the reaction sources is 20000.

[0185] Step S6: Using the MOCVD method, under the conditions of a temperature of 1100℃ and a pressure of 200mbar, TMAl, TMGa and NH3 are introduced as reaction sources (V / III ratio of 10000), and H2 and N2 are used as carrier gases to grow an electron blocking layer 6 with a thickness of 30nm on the outer surface of the quantum well layer 5.

[0186] Step S7: Based on epitaxial growth technology, the temperature is set to 1100℃ and the pressure to 400mbar. TMGa and NH3 are introduced as reaction sources (V / III ratio is 20000), CP2Mg is used as a doping source, and H2 and N2 are used as carrier gases. A p-type GaN layer 7 with a thickness of 300nm is grown on the outer surface of the electron blocking layer 6.

[0187] Step S8: Using etching technology, the connection between the top and side of the n-type GaN nanopillar 4 and the coating layer 100 of the non-polar sidewall are etched to expose the n-type GaN nanopillar 4 and isolate the Ga surface 92, N surface 93 and m / a surface 91 of the quantum well layer 5 from each other.

[0188] Step S9: Using physical vapor deposition or sputtering, deposit p-type electrodes 81 on each p-type GaN layer 7 and n-type electrodes 82 on each n-type GaN layer 2 to obtain a tri-color Micro-LED device.

[0189] Comparative Example 1

[0190] Comparative Example 1 shows a Micro-LED device fabricated using a stacked growth method. The Micro-LED device includes a substrate and multiple LED light-emitting units disposed on the substrate. Each LED light-emitting unit includes a stacked blue quantum well layer, a green quantum well layer, and a red quantum well layer, as shown in Figure 10. The specific fabrication process can be referred to the existing technology and will not be described in detail here.

[0191] The performance test results of the tricolor Micro-LED devices of Examples 1-3 and Comparative Example 1 are shown in Table 1.

[0192] Table 1 Performance test results of the three-color Micro-LED device

[0193] The test results show that the Micro-LED devices fabricated using the method of this application have lower turn-on voltages, improved intensity uniformity of RGB three-color Micro-LED devices, and alleviated the reduction in device efficiency under high current, which greatly helps to improve device performance.

[0194] In summary, the fabrication method of this application can obtain a tricolor Micro-LED device with multiple LED light-emitting structures, and each LED light-emitting structure has three mutually isolated p-type regions. By adjusting the current density of the p-type electrodes of each LED light-emitting structure, the brightness and grayscale of different wavelengths of light can be adjusted.

[0195] Furthermore, this application uses selective epitaxy to prepare n-type GaN nanopillars 4 with non-polar surfaces, constructing three different polar surfaces: Ga surface 92, N surface 93, and m / a surface 91. This enables the integration of RGB three-color Micro-LED devices on a single n-type GaN nanopillar 4, significantly improving pixel integration density and facilitating the realization of smaller, higher-resolution Micro-LED devices, such as Micro-LED displays.

[0196] Furthermore, due to the special nature of the structure, the uniformity and density of the epitaxially grown material layers at the connection between the top and side of the n-type GaN nanopillar 4 in this application are poor. Etching away the material layers that are covered by this part can effectively prevent leakage and improve the reliability of the device.

[0197] Furthermore, this application forms multiple LED light-emitting structures on the same substrate and constructs three mutually isolated p-type regions on different crystal planes of the n-type GaN nanopillars 4 in each LED light-emitting structure. By utilizing the different incorporation efficiencies of In atoms in different crystal plane directions, the three colors of each LED light-emitting structure can be separately controlled, making it easier to control in terms of current driving and thermal management. Moreover, due to the sufficient strain relaxation of the n-type GaN nanopillars 4, the material structure characteristics and device performance will not be affected by stress accumulation when growing structures such as the quantum well layer 5, and the situation where uneven heat distribution affects device performance can be avoided.

[0198] Furthermore, the manufacturing method of this application can reduce the process of transferring and assembling Micro-LEDs of different colors grown on different substrates, simplify the manufacturing process, improve production efficiency, and reduce costs.

[0199] The embodiments of this application have been described in detail above, but this application is not limited to this specific embodiment. Various modifications and alterations can be made within the scope of the spirit of this application as set forth in the claims.

Claims

1. A tri-color Micro-LED device, comprising: Substrate (1); n-type GaN layer (2), the n-type GaN layer (2) is disposed on the substrate (1); A mask layer (3) is disposed on the n-type GaN layer (2), and a plurality of windows are opened on the mask layer (3) to expose the n-type GaN layer (2) partially; Multiple LED light-emitting structures, each LED light-emitting structure comprising: n-type GaN nanopillars (4) and a coating layer (100), each n-type GaN nanopillar (4) being disposed within a corresponding window and extending away from the substrate (1); the coating layer comprising: A quantum well layer (5) is disposed on the outer surface of the n-type GaN nanopillar (4); wherein the quantum well layer (5) includes mutually isolated Ga surface (92), N surface (93) and m / a surface (91), and the light emitted from the Ga surface (92), the N surface (93) and the m / a surface (91) has different wavelengths; An electron blocking layer (6) is disposed on the outer surface of the quantum well layer (5); p-type GaN layer (7) is disposed on the outer surface of the electron blocking layer (6).

2. The tri-color Micro-LED device according to claim 1, wherein, The LED light-emitting structure also includes: A p-type electrode is used to connect to the positive terminal of an external power supply; wherein, the p-type electrode includes a first p-type electrode (801), a second p-type electrode (802), and a third p-type electrode (803). The first p-type electrode (801) is disposed on the p-type GaN layer (7) located on the m / a surface (91); the second p-type electrode (802) abuts against the p-type GaN layer (7) located on the Ga surface (92) and is disposed on the mask layer (3); the third p-type electrode (803) abuts against the p-type GaN layer (7) located on the N surface (93) and is disposed on the mask layer (3). The n-type electrode (82) is disposed on the n-type GaN layer (2) and is used to connect to the negative terminal of an external power supply.

3. The tri-color Micro-LED device according to claim 1, wherein, The second p-type electrode (802) includes a first sub-electrode and a second sub-electrode coupled to the first sub-electrode. The first sub-electrode is disposed on the mask layer (3), and the second sub-electrode is disposed on the first sub-electrode and abuts against the p-type GaN layer (7) located on the Ga surface (92); and / or The third p-type electrode (803) includes a third sub-electrode and a fourth sub-electrode coupled to the third sub-electrode. The third sub-electrode is disposed on the mask layer (3), and the fourth sub-electrode is disposed on the third sub-electrode and abuts against the p-type GaN layer (7) located on the N-plane (93).

4. The tri-color Micro-LED device according to claim 1, wherein, The windows are multiple and arranged in a dot matrix pattern. Each window is rectangular. The long side of the rectangle corresponds to the m / a plane direction of the n-type GaN layer (2), and the short side of the rectangle corresponds to the c plane direction and the -c plane direction of the n-type GaN layer (2), respectively.

5. The tri-color Micro-LED device according to claim 3, wherein, The long side of the rectangle has a length of 1 to 10 μm, the short side has a length of 100 to 500 nm, the distance between two adjacent windows along the long side of the rectangle is 1 to 5 μm, and the distance between two adjacent windows along the short side of the rectangle is 2 to 10 μm.

6. The tri-color Micro-LED device according to claim 1, wherein, The area of ​​the Ga surface (92) or N surface (93) of the quantum well layer (5) is greater than the area of ​​the nonpolar sidewall surface.

7. The tri-color Micro-LED device according to claim 1, wherein, The substrate (1) is an r-plane sapphire substrate, an a / m-plane GaN substrate, or an a / m-plane AlN substrate; and / or The thickness of the n-type GaN layer (2) is 500 nm to 2 μm; and / or, The thickness of the mask layer (3) is 30–200 nm, and the material of the mask layer (3) is SiNx, SiO2, or Al2O3; and / or, The height of the n-type GaN nanopillars (4) is 500–5000 nm; and / or, The quantum well layer (5) comprises alternating layers of InGaN and GaN with a cycle period of 1 to 10, wherein the thickness of the InGaN layer is 2 to 3 nm and the thickness of the GaN layer is 8 to 15 nm; and / or The electron blocking layer (6) has a thickness of 10–30 nm, and the electron blocking layer (6) is an AlGaN electron blocking layer (6); and / or, The thickness of the p-type GaN layer (7) is 50-300 nm.

8. A method for fabricating a three-color Micro-LED device, wherein, Includes the following steps: An n-type GaN layer (2) is epitaxially grown on a substrate (1), and a mask layer (3) is deposited on the n-type GaN layer (2); Multiple windows are opened on the mask layer (3) to partially expose the n-type GaN layer (2), and n-type GaN nanopillars (4) are epitaxially grown on the exposed n-type GaN layer (2); A quantum well layer (5) is grown on the outer surface of each of the n-type GaN nanopillars (4); An electron blocking layer (6) is grown on the outer surface of the quantum well layer (5), and a p-type GaN layer (7) is grown on the outer surface of the electron blocking layer (6); wherein the quantum well layer (5), the electron blocking layer (6) and the p-type GaN layer (7) form a cladding layer (100); The cladding layer (100) is etched to isolate the Ga surface (92), N surface (93) and m / a surface (91) of the quantum well layer (5) from each other, thereby obtaining the tricolor Micro-LED device; The light emitted from the Ga surface (92), the N surface (93), and the m / a surface (91) has different wavelengths.

9. The method for fabricating a tricolor Micro-LED device according to claim 8, wherein, Forming the quantum well layer (5) includes: The quantum well layer (5) is formed by alternately growing InGaN and GaN layers for 1 to 10 cycles on the outer surface of the n-type GaN nanopillar (4); The growth of the InGaN layer includes: under first growth conditions, introducing a first carrier gas and a first reaction source to grow an InGaN layer with a thickness of 2-3 nm; wherein the first growth conditions include a temperature of 700-800°C, a pressure of 200-600 mbar, a V / III ratio of 10000-40000 for the first reaction source, and the first carrier gas being N2; and / or, The growth of the GaN layer includes: under a second growth condition, introducing a second carrier gas and a second reaction source to grow the GaN layer with a thickness of 8-15 nm; wherein the second growth condition includes a temperature of 830-950°C, a pressure of 200-600 mbar, a V / III ratio of 5000-20000 for the second reaction source, and the second carrier gas being N2.

10. The method for fabricating a tri-color Micro-LED device according to claim 8, wherein, The growth of the n-type GaN layer (2) includes: Under the third growth conditions, a third carrier gas and a third reaction source are introduced to epitaxially grow an n-type GaN layer (2) with a thickness of 500 nm to 2 μm on the substrate (1); wherein the third growth conditions include: a temperature of 1000 to 1100 °C, a pressure of 100 to 400 mbar, a V / III ratio of 500 to 3000 for the third reaction source, and the third carrier gas being H2 or a mixture of H2 and N2; and / or, The growth of the n-type GaN nanopillars (4) includes: under fourth growth conditions, introducing a fourth carrier gas and a fourth reaction source, and growing the n-type GaN nanopillars (4) with a height of 500–5000 nm; wherein, the fourth growth conditions include a temperature of 1000–1100 °C, a pressure of 50–200 mbar, a V / III ratio of 50–1000 for the fourth reaction source, and the fourth carrier gas being H2 or a mixture of H2 and N2; and / or, The growth of the electron blocking layer (6) includes: under fifth growth conditions, introducing a fifth carrier gas and a fifth reaction source to grow the electron blocking layer (6) with a thickness of 10-30 nm; wherein, the fifth growth conditions include a temperature of 950-1100 °C, a pressure of 100-200 mbar, a V / III ratio of 5000-10000 for the fifth reaction source, and the fifth carrier gas being H2 or a mixture of H2 and N2; and / or, The growth of the p-type GaN layer (7) includes: under the sixth growth conditions, introducing a sixth carrier gas and a sixth reaction source to grow the p-type GaN layer (7) with a thickness of 50–300 nm; wherein the sixth growth conditions include a temperature of 950–1100 °C, a pressure of 100–400 mbar, a V / III ratio of 5000–20000 for the sixth reaction source, and the sixth carrier gas being H2 or a mixture of H2 and N2; and / or, Etching the coating layer (100) includes: The r-face and the non-polar sidewall of the etched coating layer (100) are etched.

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