Pixel circuit, pixel driving method and display apparatus

Abstract

Provided in the present disclosure are a pixel circuit, a pixel driving method and a display apparatus. The pixel circuit comprises a driving circuit, a first energy storage circuit, a data writing circuit and a compensation control circuit; a display cycle of the pixel circuit comprises a compensation stage and a writing stage which are independent of each other; under control of a scanning signal, the data writing circuit controls a data voltage to be provided to a writing node; and in the compensation stage, the compensation control circuit controls a first node to be connected to a third node under the control of a compensation control signal. During operation of the pixel circuit of the present disclosure, the compensation stage and the writing stage are independent of each other; in the writing stage, the data writing circuit performs data voltage writing, and in the compensation stage, the compensation control circuit performs threshold voltage compensation, such that the threshold voltage compensation is no longer limited by the cycle time, and the threshold voltage compensation and the data writing are separated from each other, thus achieving high-frequency driving display.

Description

Pixel circuits, pixel driving methods, and display devices

[0001] Cross-reference to related applications

[0002] This application claims priority to Chinese Patent Application No. 202410660602.3, filed in China on May 27, 2024, the entire contents of which are incorporated herein by reference. Technical Field

[0003] This disclosure relates to the field of display technology, and in particular to a pixel circuit, a pixel driving method, and a display device. Background Technology

[0004] With the rapid development of AMOLED (Active-matrix organic light-emitting diode), medium and large-sized tablet computers and laptops have become important future development directions. Customers have increasingly strong demands for high-frequency displays. Existing pixel circuits perform threshold voltage compensation and data voltage writing simultaneously. High-frequency technology leads to line time compression, which cannot effectively compensate for the threshold voltage of the driving transistor in the driving circuit, and thus cannot achieve high-frequency driving. Summary of the Invention

[0005] The main objective of this disclosure is to provide a pixel circuit, a pixel driving method, and a display device to solve the problem that when the pixel circuit performs threshold voltage compensation and data voltage writing simultaneously, the high-frequency technology causes line time compression, which cannot effectively compensate for the threshold voltage of the driving transistor in the driving circuit and thus cannot achieve high-frequency driving.

[0006] In one aspect, embodiments of this disclosure provide a pixel circuit, including a driving circuit, a first energy storage circuit, a data writing circuit, and a compensation control circuit; the display cycle of the pixel circuit includes mutually independent compensation and writing phases.

[0007] The control terminal of the driving circuit is electrically connected to the first node, the first terminal of the driving circuit is electrically connected to the second node, and the second terminal of the driving circuit is electrically connected to the third node. The driving circuit is used to generate a driving current under the control of the potential of the first node.

[0008] The first end of the first energy storage circuit is electrically connected to the first node, and the second end of the first energy storage circuit is electrically connected to the write node. The first energy storage circuit is used to store electrical energy.

[0009] The data writing circuit is electrically connected with a scan end, a data line and the writing node respectively, and is configured to, in the writing stage, control the data voltage provided by the data line to be provided to the writing node under the control of a scan signal provided by the scan end.

[0010] The compensation control circuit is electrically connected with a compensation control end, the first node and the third node respectively, and is configured to, in the compensation stage, control the first node and the third node to be in communication under the control of a compensation control signal provided by the compensation control end.

[0011] Optionally, the pixel circuit according to any one of the embodiments of the present disclosure further comprises a first initialization circuit.

[0012] The first initialization circuit is electrically connected with a first reset control end, a first initial voltage end and the writing node respectively, and is configured to, under the control of a first reset control signal provided by the first reset control end, control the first initial voltage end and the writing node to be in communication or disconnected.

[0013] Optionally, the pixel circuit according to any one of the embodiments of the present disclosure further comprises a second initialization circuit.

[0014] The second initialization circuit is electrically connected with a second reset control end, a second initial voltage end and the first node respectively, and is configured to, under the control of a second reset control signal provided by the second reset control end, control the second initial voltage end and the first node to be in communication or disconnected.

[0015] Optionally, the pixel circuit according to any one of the embodiments of the present disclosure further comprises a first light emitting control circuit, a second light emitting control circuit and a light emitting element.

[0016] The first light emitting control circuit is electrically connected with a first light emitting control end, a power voltage end and the second node respectively, and is configured to, under the control of a first light emitting control signal provided by the first light emitting control end, control the power voltage end and the second node to be in communication or disconnected.

[0017] The second light emitting control circuit is electrically connected with a second light emitting control end, the third node and a first pole of the light emitting element respectively, and is configured to, under the control of a second light emitting control signal provided by the second light emitting control end, control the third node and the first pole of the light emitting element to be in communication or disconnected.

[0018] A second pole of the light emitting element is electrically connected with a first voltage end.

[0019] Optionally, the pixel circuit according to any one of the embodiments of the present disclosure further comprises a third initialization circuit.

[0020] The third initialization circuit is electrically connected with the second reset control end, the third initial voltage end and the first pole of the light emitting element respectively, and is configured to control the third initial voltage end to be in communication or disconnected with the first pole of the light emitting element under the control of a second reset control signal provided by the second reset control end.

[0021] Optionally, the pixel circuit further comprises a fourth initialization circuit.

[0022] The fourth initialization circuit is electrically connected with the second reset control end, the fourth initial voltage end and the second node respectively, and is configured to control the fourth initial voltage end to be in communication or disconnected with the second node under the control of a second reset control signal provided by the second reset control end.

[0023] Optionally, the pixel circuit further comprises a second initialization circuit.

[0024] The second initialization circuit is electrically connected with the second reset control end, the second initial voltage end and the third node respectively, and is configured to control the second initial voltage end to be in communication or disconnected with the third node under the control of a second reset control signal provided by the second reset control end.

[0025] Optionally, the pixel circuit further comprises a second energy storage circuit.

[0026] The second energy storage circuit is electrically connected with the first node, and is configured to maintain the electric potential of the first node.

[0027] Optionally, the data writing circuit comprises a first transistor, the compensation control circuit comprises a second transistor, and the driving circuit comprises a driving transistor.

[0028] The gate of the driving transistor is electrically connected with the first node, the first pole of the driving transistor is electrically connected with the second node, and the second pole of the driving transistor is electrically connected with the third node.

[0029] The gate of the first transistor is electrically connected with the scanning end, the first pole of the first transistor is electrically connected with the data line, and the second pole of the first transistor is electrically connected with the writing node.

[0030] The gate of the second transistor is electrically connected with the compensation control end, the first pole of the second transistor is electrically connected with the first node, and the second pole of the second transistor is electrically connected with the third node.

[0031] Optionally, the first initialization circuit comprises a third transistor.

[0032] The gate of the third transistor is electrically connected with the first reset control end, the first pole of the third transistor is electrically connected with the first initial voltage end, and the second pole of the third transistor is electrically connected with the write node.

[0033] Optionally, the second initialization circuit comprises a fourth transistor.

[0034] The gate of the fourth transistor is electrically connected with the second reset control end, the first pole of the fourth transistor is electrically connected with the second initial voltage end, and the second pole of the fourth transistor is electrically connected with the first node.

[0035] Optionally, the first light-emitting control circuit comprises a fifth transistor, and the second light-emitting control circuit comprises a sixth transistor.

[0036] The gate of the fifth transistor is electrically connected with the first light-emitting control end, the first pole of the fifth transistor is electrically connected with the power voltage end, and the second pole of the fifth transistor is electrically connected with the second node.

[0037] The gate of the sixth transistor is electrically connected with the second light-emitting control end, the first pole of the sixth transistor is electrically connected with the third node, and the second pole of the sixth transistor is electrically connected with the first pole of the light-emitting element.

[0038] Optionally, the third initialization circuit comprises a seventh transistor.

[0039] The gate of the seventh transistor is electrically connected with the second reset control end, the first pole of the seventh transistor is electrically connected with the third initial voltage end, and the second pole of the seventh transistor is electrically connected with the first pole of the light-emitting element.

[0040] Optionally, the fourth initialization circuit comprises an eighth transistor.

[0041] The gate of the eighth transistor is electrically connected with the second reset control end, the first pole of the eighth transistor is electrically connected with the fourth initial voltage end, and the second pole of the eighth transistor is electrically connected with the second node.

[0042] Optionally, the second initialization circuit comprises a fourth transistor.

[0043] The gate of the fourth transistor is electrically connected with the second reset control end, the first pole of the fourth transistor is electrically connected with the second initial voltage end, and the second pole of the fourth transistor is electrically connected with the third node.

[0044] In a second disclosure, the pixel driving method is applied to the pixel circuit, and a display period of the pixel circuit includes a compensation phase and a write phase which are independent of each other. The pixel driving method includes:

[0045] In the write phase, the data writing circuit controls the data voltage provided by the data line to be provided to the write node under the control of the scanning signal.

[0046] In the compensation phase, the compensation control circuit controls the communication between the first node and the third node under the control of the compensation control signal.

[0047] In a third disclosure, the display device includes the pixel circuit.

[0048] The pixel circuit in the disclosure is independent of the compensation phase and the write phase in operation. In the write phase, the data writing circuit writes the data voltage, and in the compensation phase, the compensation control circuit compensates the threshold voltage, so that the threshold voltage compensation is no longer limited by the period time, the threshold voltage compensation and the data writing are separated from each other, and high-frequency driving display is achieved. BRIEF DESCRIPTION OF DRAWINGS

[0049] FIG. 1 is a structural diagram of a pixel circuit according to at least one embodiment of the disclosure;

[0050] FIG. 2 is a structural diagram of a pixel circuit according to at least one embodiment of the disclosure;

[0051] FIG. 3 is a structural diagram of a pixel circuit according to at least one embodiment of the disclosure;

[0052] FIG. 4 is a structural diagram of a pixel circuit according to at least one embodiment of the disclosure;

[0053] FIG. 5 is a structural diagram of a pixel circuit according to at least one embodiment of the disclosure;

[0054] FIG. 6 is a structural diagram of a pixel circuit according to at least one embodiment of the disclosure;

[0055] FIG. 7 is a structural diagram of a pixel circuit according to at least one embodiment of the disclosure;

[0056] FIG. 8 is a structural diagram of a pixel circuit according to at least one embodiment of the disclosure;

[0057] FIG. 9 is a structural diagram of a pixel circuit according to at least one embodiment of the disclosure;

[0058] FIG. 10 is a structural diagram of a pixel circuit according to at least one embodiment of the disclosure;

[0059] FIG. 11 is a circuit diagram of a pixel circuit according to at least one embodiment of the disclosure;

[0060] FIG. 12 is a timing diagram of the operation of the pixel circuit according to at least one embodiment of the present disclosure;

[0061] FIG. 13 is a circuit diagram of the pixel circuit according to at least one embodiment of the present disclosure;

[0062] FIG. 14 is a circuit diagram of the pixel circuit according to at least one embodiment of the present disclosure. DETAILED DESCRIPTION

[0063] The technical solutions in the embodiments of the present disclosure will be clearly and completely described below with reference to the drawings in the embodiments of the present disclosure. Obviously, the described embodiments are only part of the embodiments of the present disclosure, rather than all the embodiments. Based on the embodiments in the present disclosure, all other embodiments obtained by a person of ordinary skill in the art without creative labor fall within the scope of protection of the present disclosure.

[0064] The transistors used in all the embodiments of the present disclosure can be thin film transistors or field effect transistors or other devices with the same characteristics. In the embodiments of the present disclosure, in order to distinguish the two poles of the transistor other than the gate, one of the poles is referred to as the first pole and the other is referred to as the second pole.

[0065] In actual operation, when the transistor is a thin film transistor or a field effect transistor, the first pole can be a drain and the second pole can be a source, or the first pole can be a source and the second pole can be a drain.

[0066] As shown in FIG. 1, the pixel circuit according to the embodiments of the present disclosure includes a driving circuit 10, a first energy storage circuit 11, a data writing circuit 12 and a compensation control circuit 13; the display period of the pixel circuit includes a compensation phase and a writing phase which are independent of each other;

[0067] The control end of the driving circuit 10 is electrically connected with a first node N1, the first end of the driving circuit 10 is electrically connected with a second node N2, the second end of the driving circuit 10 is electrically connected with a third node N3, and the driving circuit 10 is configured to generate a driving current under the control of the potential of the first node N1.

[0068] The first end of the first energy storage circuit 11 is electrically connected with the first node N1, and the second end of the first energy storage circuit 11 is electrically connected with a writing node NW, and the first energy storage circuit 11 is configured to store electrical energy.

[0069] The data writing circuit 12 is electrically connected with a scanning end GT, a data line DL and the writing node NW respectively, and is configured to, in the writing phase, control the data voltage provided by the data line DL to be provided to the writing node NW under the control of the scanning signal provided by the scanning end GT.

[0070] The compensation control circuit 13 is electrically connected with the compensation control end R2, the first node N1 and the third node N3 respectively, and is configured to control the communication between the first node N1 and the third node N3 under the control of the compensation control signal provided by the compensation control end R2 in the compensation phase.

[0071] At least one embodiment of the pixel circuit shown in FIG. 1, the display period of the pixel circuit includes a compensation phase and a write phase which are independent of each other;

[0072] In the write phase, the data writing circuit 12 controls the data voltage provided by the data line DL to be provided to the write node NW under the control of the scanning signal.

[0073] In the compensation phase, the compensation control circuit 13 controls the communication between the first node N1 and the third node N3 under the control of the compensation control signal.

[0074] At least one embodiment of the pixel circuit in the present disclosure, the compensation phase and the write phase are independent of each other, in the write phase, the data writing circuit 12 performs data voltage writing, in the compensation phase, the compensation control circuit 13 performs threshold voltage compensation, so that the threshold voltage compensation is no longer limited by the cycle time, the threshold voltage compensation and the data writing are separated from each other, and high-frequency driving display is realized.

[0075] The pixel circuit in at least one embodiment of the present disclosure further comprises a first initialization circuit;

[0076] The first initialization circuit is electrically connected with the first reset control end, the first initial voltage end and the write node respectively, and is configured to control the communication or disconnection between the first initial voltage end and the write node under the control of the first reset control signal provided by the first reset control end.

[0077] In specific implementation, the pixel circuit can comprise a first initialization circuit, and the first initialization circuit provides the first initialization voltage provided by the first initial voltage end to the write node under the first reset control signal, and initializes the potential of the write node.

[0078] As shown in FIG. 2, on the basis of at least one embodiment of the pixel circuit shown in FIG. 1, the pixel circuit in at least one embodiment of the present disclosure further comprises a first initialization circuit 21.

[0079] The first initialization circuit 21 is electrically connected with the first reset control end EM3, the first initial voltage end I1 and the write node NW respectively, and is configured to control the communication or disconnection between the first initial voltage end I1 and the write node NW under the control of the first reset control signal provided by the first reset control end EM3.

[0080] The pixel circuit in at least one embodiment of the present disclosure further comprises a second initialization circuit.

[0081] The second initialization circuit is electrically connected with a second reset control end, a second initial voltage end and the first node respectively, and is configured to control the second initial voltage end to be in communication or disconnected with the first node under the control of a second reset control signal provided by the second reset control end.

[0082] In a specific implementation, the pixel circuit can further comprise a second initialization circuit, which writes a second initial voltage provided by the second initial voltage end into the first node under the control of a second reset control signal, and initializes the electric potential of the first node, so that the driving circuit can be turned on at the beginning of the compensation stage.

[0083] As shown in FIG. 3, on the basis of at least one embodiment of the pixel circuit shown in FIG. 2, the pixel circuit in at least one embodiment of the present disclosure further comprises a second initialization circuit 22.

[0084] The second initialization circuit 22 is electrically connected with a second reset control end R1, a second initial voltage end I2 and the first node N1 respectively, and is configured to control the second initial voltage end I2 to be in communication or disconnected with the first node N1 under the control of a second reset control signal provided by the second reset control end R1.

[0085] The pixel circuit in at least one embodiment of the present disclosure further comprises a first light-emitting control circuit, a second light-emitting control circuit and a light-emitting element.

[0086] The first light-emitting control circuit is electrically connected with a first light-emitting control end, a power voltage end and the second node respectively, and is configured to control the power voltage end to be in communication or disconnected with the second node under the control of a first light-emitting control signal provided by the first light-emitting control end.

[0087] The second light-emitting control circuit is electrically connected with a second light-emitting control end, the third node and a first pole of the light-emitting element respectively, and is configured to control the third node to be in communication or disconnected with the first pole of the light-emitting element under the control of a second light-emitting control signal provided by the second light-emitting control end.

[0088] A second pole of the light-emitting element is electrically connected with a first voltage end.

[0089] In a specific implementation, the pixel circuit can further comprise a first light-emitting control circuit, a second light-emitting control circuit and a light-emitting element, and the first light-emitting control circuit and the second light-emitting control circuit perform light-emitting control.

[0090] As shown in FIG. 4, on the basis of at least one embodiment of the pixel circuit shown in FIG. 3, the pixel circuit according to at least one embodiment of the present disclosure further comprises a first light-emitting control circuit 41, a second light-emitting control circuit 42 and a light-emitting element E1.

[0091] The first light-emitting control circuit 41 is electrically connected with a first light-emitting control end EM1, a power voltage end VDD and the second node N2 respectively, and is configured to control the power voltage end VDD and the second node N2 to be connected or disconnected under the control of a first light-emitting control signal provided by the first light-emitting control end EM1.

[0092] The second light-emitting control circuit 42 is electrically connected with a second light-emitting control end EM2, the third node N3 and the first pole of the light-emitting element E1 respectively, and is configured to control the third node N3 and the first pole of the light-emitting element E1 to be connected or disconnected under the control of a second light-emitting control signal provided by the second light-emitting control end EM2.

[0093] The second pole of the light-emitting element E1 is electrically connected with a first voltage end V1.

[0094] Optionally, the first voltage end can be a low voltage end.

[0095] The pixel circuit according to at least one embodiment of the present disclosure further comprises a third initialization circuit.

[0096] The third initialization circuit is electrically connected with a second reset control end, a third initial voltage end and the first pole of the light-emitting element respectively, and is configured to control the third initial voltage end and the first pole of the light-emitting element to be connected or disconnected under the control of a second reset control signal provided by the second reset control end.

[0097] In a specific implementation, the pixel circuit can comprise a third initialization circuit, which writes a third initial voltage provided by the third initial voltage end to the first pole of the light-emitting element under the control of the second reset control signal, and clears the residual charges of the first pole of the light-emitting element.

[0098] As shown in FIG. 5, on the basis of at least one embodiment of the pixel circuit shown in FIG. 4, the pixel circuit according to at least one embodiment of the present disclosure further comprises a third initialization circuit 23.

[0099] The third initialization circuit 23 is electrically connected with a second reset control end R1, a third initial voltage end I3 and the first pole of the light-emitting element E1 respectively, and is configured to control the third initial voltage end I3 and the first pole of the light-emitting element E1 to be connected or disconnected under the control of a second reset control signal provided by the second reset control end R1.

[0100] The pixel circuit in at least one embodiment of the present disclosure further comprises a fourth initialization circuit.

[0101] The fourth initialization circuit is electrically connected with the second reset control end, the fourth initial voltage end and the second node respectively, and is used for controlling the fourth initial voltage end to be connected or disconnected with the second node under the control of a second reset control signal provided by the second reset control end.

[0102] In a specific implementation, the pixel circuit can further comprise a fourth initialization circuit, which writes a fourth initial voltage provided by the fourth initial voltage end into the second node under the control of a second reset control signal, so as to improve the hysteresis of a driving transistor included in the driving circuit.

[0103] As shown in FIG. 6, on the basis of at least one embodiment of the pixel circuit shown in FIG. 5, the pixel circuit in at least one embodiment of the present disclosure further comprises a fourth initialization circuit 24.

[0104] The fourth initialization circuit 24 is electrically connected with a second reset control end R1, a fourth initial voltage end I4 and the second node N2 respectively, and is used for controlling the fourth initial voltage end I4 to be connected or disconnected with the second node N2 under the control of a second reset control signal provided by the second reset control end R1.

[0105] In a specific implementation, the pixel circuit can further comprise a fourth initialization circuit, which writes a fourth initial voltage provided by the fourth initial voltage end into the second node under the control of a second reset control signal, so as to improve the hysteresis of a driving transistor included in the driving circuit and improve low-frequency flicker (flicker phenomenon).

[0106] The pixel circuit in at least one embodiment of the present disclosure further comprises a second initialization circuit.

[0107] The second initialization circuit is electrically connected with the second reset control end, the second initial voltage end and the third node respectively, and is used for controlling the second initial voltage end to be connected or disconnected with the third node under the control of a second reset control signal provided by the second reset control end.

[0108] In a specific implementation, the pixel circuit can further comprise a second initialization circuit, which provides a second initial voltage provided by the second initial voltage end to the third node under the control of a second reset control signal, and initializes the potential of the third node.

[0109] At least one embodiment of the pixel circuit shown in FIG. 7 of the present disclosure is different from at least one embodiment of the pixel circuit shown in FIG. 6 of the present disclosure in that:

[0110] The second initialization circuit 22 is not electrically connected with the first node N1, and the second initialization circuit 22 is electrically connected with the third node N3, for controlling the second initialization voltage end I2 and the third node N3 to be connected or disconnected under the control of the second reset control signal provided by the second reset control end R1.

[0111] The pixel circuit in at least one embodiment of the present disclosure further comprises a second energy storage circuit;

[0112] The second energy storage circuit is electrically connected with the first node, for maintaining the potential of the first node.

[0113] As shown in FIG. 8, on the basis of at least one embodiment of the pixel circuit shown in FIG. 5, the pixel circuit in at least one embodiment of the present disclosure further comprises a second energy storage circuit 81;

[0114] The second energy storage circuit 81 is electrically connected with the first node N1, for maintaining the potential of the first node N1.

[0115] As shown in FIG. 9, on the basis of at least one embodiment of the pixel circuit shown in FIG. 6, the pixel circuit in at least one embodiment of the present disclosure further comprises a second energy storage circuit 81;

[0116] The second energy storage circuit 81 is electrically connected with the first node N1, for maintaining the potential of the first node N1.

[0117] As shown in FIG. 10, on the basis of at least one embodiment of the pixel circuit shown in FIG. 7, the pixel circuit in at least one embodiment of the present disclosure further comprises a second energy storage circuit 81;

[0118] The second energy storage circuit 81 is electrically connected with the first node N1, for maintaining the potential of the first node N1.

[0119] Optionally, the data writing circuit comprises a first transistor, the compensation control circuit comprises a second transistor, and the driving circuit comprises a driving transistor;

[0120] The gate of the driving transistor is electrically connected with the first node, the first pole of the driving transistor is electrically connected with the second node, and the second pole of the driving transistor is electrically connected with the third node;

[0121] The gate of the first transistor is electrically connected with the scanning end, the first pole of the first transistor is electrically connected with the data line, and the second pole of the first transistor is electrically connected with the writing node;

[0122] The gate of the second transistor is electrically connected with the compensation control end, the first pole of the second transistor is electrically connected with the first node, and the second pole of the second transistor is electrically connected with the third node.

[0123] Optionally, the first initialization circuit comprises a third transistor.

[0124] The gate of the third transistor is electrically connected with the first reset control end, the first pole of the third transistor is electrically connected with the first initial voltage end, and the second pole of the third transistor is electrically connected with the write node.

[0125] Optionally, the second initialization circuit comprises a fourth transistor.

[0126] The gate of the fourth transistor is electrically connected with the second reset control end, the first pole of the fourth transistor is electrically connected with the second initial voltage end, and the second pole of the fourth transistor is electrically connected with the first node.

[0127] Optionally, the first light-emitting control circuit comprises a fifth transistor, and the second light-emitting control circuit comprises a sixth transistor.

[0128] The gate of the fifth transistor is electrically connected with the first light-emitting control end, the first pole of the fifth transistor is electrically connected with the power voltage end, and the second pole of the fifth transistor is electrically connected with the second node.

[0129] The gate of the sixth transistor is electrically connected with the second light-emitting control end, the first pole of the sixth transistor is electrically connected with the third node, and the second pole of the sixth transistor is electrically connected with the first pole of the light-emitting element.

[0130] Optionally, the third initialization circuit comprises a seventh transistor.

[0131] The gate of the seventh transistor is electrically connected with the second reset control end, the first pole of the seventh transistor is electrically connected with the third initial voltage end, and the second pole of the seventh transistor is electrically connected with the first pole of the light-emitting element.

[0132] Optionally, the fourth initialization circuit comprises an eighth transistor.

[0133] The gate of the eighth transistor is electrically connected with the second reset control end, the first pole of the eighth transistor is electrically connected with the fourth initial voltage end, and the second pole of the eighth transistor is electrically connected with the second node.

[0134] Optionally, the second initialization circuit comprises a fourth transistor.

[0135] The gate of the fourth transistor is electrically connected with the second reset control end, the first electrode of the fourth transistor is electrically connected with the second initial voltage end, and the second electrode of the fourth transistor is electrically connected with the third node.

[0136] As shown in Fig. 11, on the basis of at least one embodiment of the pixel circuit shown in Fig. 8, the light emitting element is an organic light emitting diode O1;

[0137] The data writing circuit comprises a first transistor T1, the compensation control circuit comprises a second transistor T2, and the driving circuit comprises a driving transistor DT.

[0138] The gate of the driving transistor DT is electrically connected with the first node N1, the source of the driving transistor DT is electrically connected with the second node N2, and the drain of the driving transistor DT is electrically connected with the third node N3.

[0139] The gate of the first transistor T1 is electrically connected with the scanning end GT, the source of the first transistor T1 is electrically connected with the data line DL, and the drain of the first transistor T1 is electrically connected with the writing node NW.

[0140] The gate of the second transistor T2 is electrically connected with the compensation control end R2, the source of the second transistor T2 is electrically connected with the first node N1, and the drain of the second transistor T2 is electrically connected with the third node N3.

[0141] The first initialization circuit comprises a third transistor T3.

[0142] The gate of the third transistor T3 is electrically connected with the first reset control end EM3, the source of the third transistor T3 is electrically connected with the first initial voltage end I1, and the drain of the third transistor T3 is electrically connected with the writing node NW.

[0143] The second initialization circuit comprises a fourth transistor T4.

[0144] The gate of the fourth transistor T4 is electrically connected with the second reset control end R1, the source of the fourth transistor T4 is electrically connected with the second initial voltage end I2, and the drain of the fourth transistor T4 is electrically connected with the first node N1.

[0145] The first light emitting control circuit comprises a fifth transistor T5, and the second light emitting control circuit comprises a sixth transistor T6.

[0146] The gate of the fifth transistor T5 is electrically connected with the first light emitting control end EM1, the source of the fifth transistor T5 is electrically connected with the power voltage end VDD, and the drain of the fifth transistor T5 is electrically connected with the second node N2.

[0147] a gate of the sixth transistor T6 is electrically connected with the second light-emitting control terminal EM2, a source of the sixth transistor T6 is electrically connected with the third node N3, and a drain of the sixth transistor T6 is electrically connected with an anode of O1;

[0148] the third initialization circuit comprises a seventh transistor T7;

[0149] a gate of the seventh transistor T7 is electrically connected with the second reset control terminal R1, a source of the seventh transistor T7 is electrically connected with the third initial voltage terminal I3, and a drain of the seventh transistor T7 is electrically connected with the anode of O1;

[0150] a cathode of O1 is electrically connected with a low voltage terminal VSS;

[0151] the first energy storage circuit comprises a first capacitor C1, and the second energy storage circuit comprises a second capacitor C2;

[0152] a first terminal of C1 is electrically connected with the first node N1, and a second terminal of C1 is electrically connected with the write node NW;

[0153] a first terminal of C2 is electrically connected with the first node N1, and a second terminal of C2 is electrically connected with a power voltage terminal VDD.

[0154] In at least one embodiment of the pixel circuit shown in FIG. 11, all the transistors are p-type transistors, but the present disclosure is not limited thereto.

[0155] In at least one embodiment of the pixel circuit shown in FIG. 11, the voltage value of the first initial voltage Vinit1 provided by I1 is greater than or equal to 2V and less than or equal to 4V, the voltage value of the second initial voltage Vinit2 provided by I2 is greater than or equal to -4V and less than or equal to -2V, the difference between the voltage value of the third initial voltage Vinit3 provided by I3 and the voltage value of the low voltage signal provided by VSS is greater than 0V and less than or equal to 0.5V, the voltage value of the power voltage signal provided by VDD is greater than or equal to 3V and less than or equal to 6V, and the voltage value of the low voltage signal provided by VSS is greater than or equal to -4V and less than or equal to -2V.

[0156] FIG. 12 is a working timing diagram of at least one embodiment of the pixel circuit shown in FIG. 11.

[0157] As shown in FIG. 12, in the working process of at least one embodiment of the pixel circuit shown in FIG. 11 of the present disclosure, the display period can include a reset stage S1, a compensation stage S2, a write stage S3 and a light-emitting stage S4 arranged in sequence;

[0158] In the reset stage S1, R1 provides a low voltage signal, T4 and T7 are open, I2 provides a second initial voltage Vinit2 to N1, so that at the beginning of the compensation stage S2, DT can be turned on; I3 provides a third initial voltage Vinit3 to the anode of O1, clearing the residual charge of the anode of O1; EM1 provides a low voltage signal, EM3 provides a low voltage signal, T3 is open, I1 provides a first initial voltage Vinit1 to NW, T5 is open, the potential of N2 and the potential of NW are reset; EM2, R2 and GT all provide a high voltage signal, T2, DT, T6 and T1 are all off;

[0159] In the compensation stage S2, R2 provides a low voltage signal, and the duration of the compensation stage S2 is greater than or equal to 2H (1H is a row scanning time), T2 is open, N1 is communicated with N3; EM1 provides a low voltage signal, EM3 provides a low voltage signal, T5 is open, T3 is open, I1 provides a first initial voltage Vinit1 to NW; G1 and R1 all provide a high voltage signal, T4, T6, T1 and T7 are all off;

[0160] At the beginning of the compensation stage S2, DT is turned on, the power voltage signal provided by VDD charges C1 through T5, DT, T2, until DT is off, at this time, the potential of N1 is Vdd+Vth, Vdd is the voltage value of the power voltage signal, and Vth is the threshold voltage of DT;

[0161] In the write stage S3, G1 provides a low voltage signal, T1 is turned on, DL provides a data voltage Vdata to NW, the potential of NW changes from Vinit1 to Vdata, when the data voltage is written, through the capacitor voltage division, the potential of N1 changes to Vdd+Vth+(C2z / (C1z+C2z))×(Vdata-Vinit1); C1z is the capacitance value of C1, and C2z is the capacitance value of C2;

[0162] In the write stage S3, R1, EM2, EM1, EM3 and R2 all provide a high voltage signal, T2 is closed, T4 and T7 are closed, T6 is closed, T3 and T5 are closed;

[0163] In the light-emitting stage S4, EM1 and EM2 all provide a low voltage signal, T5 and T6 are both open, and DT drives O1 to emit light; the potential of N2 is Vdd, the potential of N3 is Vo1+Vss, Vss is the voltage value of the low voltage signal provided by VSS, and Vo1 is the on voltage of O1;

[0164] In the light-emitting stage S4, the gate-source voltage Vgs of DT is equal to Vth+(C2z / (C1z+C2z))×(Vdata-Vinit1), and Id is equal to K((C2z / (C1z+C2z))×(Vdata-Vinit1))2 ; wherein K is a current coefficient of the DT, and Id is a driving current generated by the DT.

[0165] As shown in FIG. 13, on the basis of at least one embodiment of the pixel circuit shown in FIG. 9, the light emitting element is an organic light emitting diode O1;

[0166] The data writing circuit comprises a first transistor T1, the compensation control circuit comprises a second transistor T2, and the driving circuit comprises a driving transistor DT;

[0167] The gate of the driving transistor DT is electrically connected with the first node N1, the source of the driving transistor DT is electrically connected with the second node N2, and the drain of the driving transistor DT is electrically connected with the third node N3;

[0168] The gate of the first transistor T1 is electrically connected with the scanning end GT, the source of the first transistor T1 is electrically connected with the data line DL, and the drain of the first transistor T1 is electrically connected with the writing node NW;

[0169] The gate of the second transistor T2 is electrically connected with the compensation control end R2, the source of the second transistor T2 is electrically connected with the first node N1, and the drain of the second transistor T2 is electrically connected with the third node N3;

[0170] The first initialization circuit comprises a third transistor T3;

[0171] The gate of the third transistor T3 is electrically connected with the first reset control end EM3, the source of the third transistor T3 is electrically connected with the first initial voltage end I1, and the drain of the third transistor T3 is electrically connected with the writing node NW;

[0172] The second initialization circuit comprises a fourth transistor T4;

[0173] The gate of the fourth transistor T4 is electrically connected with the second reset control end R1, the source of the fourth transistor T4 is electrically connected with the second initial voltage end I2, and the drain of the fourth transistor T4 is electrically connected with the first node N1;

[0174] The first light emitting control circuit comprises a fifth transistor T5, and the second light emitting control circuit comprises a sixth transistor T6;

[0175] The gate of the fifth transistor T5 is electrically connected with the first light emitting control end EM1, the source of the fifth transistor T5 is electrically connected with the power voltage end VDD, and the drain of the fifth transistor T5 is electrically connected with the second node N2;

[0176] The gate of the sixth transistor T6 is electrically connected with the second light-emitting control end EM2, the source of the sixth transistor T6 is electrically connected with the third node N3, and the drain of the sixth transistor T6 is electrically connected with the anode of O1;

[0177] The third initialization circuit comprises a seventh transistor T7.

[0178] The gate of the seventh transistor T7 is electrically connected with the second reset control end R1, the source of the seventh transistor T7 is electrically connected with the third initial voltage end I3, and the drain of the seventh transistor T7 is electrically connected with the anode of O1.

[0179] The cathode of O1 is electrically connected with the low-voltage end VSS.

[0180] The fourth initialization circuit comprises an eighth transistor T8.

[0181] The gate of the eighth transistor T8 is electrically connected with the second reset control end R1, the source of the eighth transistor T8 is electrically connected with the first initial voltage end I1, and the drain of the eighth transistor T8 is electrically connected with the second node N2.

[0182] In at least one embodiment of the pixel circuit shown in FIG. 13, all the transistors are p-type transistors, but are not limited thereto.

[0183] In at least one embodiment of the pixel circuit shown in FIG. 13, the fourth initial voltage end and the first initial voltage end I1 are the same initial voltage end.

[0184] As shown in FIG. 12, at least one embodiment of the pixel circuit shown in FIG. 13 is in operation,

[0185] The display period can comprise a reset stage S1, a compensation stage S2, a write stage S3 and a light-emitting stage S4 arranged in sequence.

[0186] In the reset stage S1, R1 provides a low-voltage signal, T4 and T7 are turned on, I2 provides the second initial voltage Vinit2 to N1, so that DT can be turned on at the beginning of the compensation stage S2; I3 provides the third initial voltage Vinit3 to the anode of O1, to clear the residual charges at the anode of O1; EM1 provides a low-voltage signal, EM3 provides a low-voltage signal, T3 is turned on, I1 provides the first initial voltage Vinit1 to NW, T5 is turned on, to reset the potential of N2 and the potential of NW; EM2, R2 and GT all provide high-voltage signals, T2, DT, T6 and T1 are all turned off;

[0187] In the reset stage S1, R1 provides a low voltage signal, T8 is turned on, and I1 provides a first initial voltage Vinit1 to N2, so as to improve the hysteresis of DT and the low frequency Flicker phenomenon;

[0188] In the compensation stage S2, R2 provides a low voltage signal, and the duration of the compensation stage S2 is greater than or equal to 2H (1H is a row scanning time), T2 is turned on, and N1 is connected with N3; EM1 provides a low voltage signal, EM3 provides a low voltage signal, T5 is turned on, T3 is turned on, I1 provides the first initial voltage Vinit1 to NW; G1 and R1 both provide a high voltage signal, and T4, T6, T1 and T7 are all turned off;

[0189] At the beginning of the compensation stage S2, DT is turned on, and the power voltage signal provided by VDD charges C1 through T5, DT and T2 until DT is turned off, at which time, the potential of N1 is Vdd+Vth, Vdd is the voltage value of the power voltage signal, and Vth is the threshold voltage of DT;

[0190] In the write stage S3, G1 provides a low voltage signal, T1 is turned on, DL provides a data voltage Vdata to NW, and the potential of NW changes from Vinit1 to Vdata; when the data voltage is written, the potential of N1 changes to Vdd+Vth+(C2z / (C1z+C2z))×(Vdata-Vinit1) through capacitive voltage division; C1z is the capacitance value of C1, and C2z is the capacitance value of C2;

[0191] In the write stage S3, R1, EM2, EM1, EM3 and R2 all provide a high voltage signal, T2 is turned off, T4 and T7 are turned off, T6 is turned off, and T3 and T5 are turned off;

[0192] In the light-emitting stage S4, EM1 and EM2 both provide a low voltage signal, T5 and T6 are both turned on, and DT drives O1 to emit light; the potential of N2 is Vdd, the potential of N3 is Vo1+Vss, Vss is the voltage value of the low voltage signal provided by VSS, and Vo1 is the on voltage of O1;

[0193] In the light-emitting stage S4, the gate-source voltage Vgs of DT is equal to Vth+(C2z / (C1z+C2z))×(Vdata-Vinit1), and Id is equal to K((C2z / (C1z+C2z))×(Vdata-Vinit1)) 2 ; wherein K is the current coefficient of DT, and Id is the driving current generated by DT.

[0194] As shown in FIG. 14, on the basis of at least one embodiment of the pixel circuit shown in FIG. 10, the light-emitting element is an organic light-emitting diode O1;

[0195] The data writing circuit comprises a first transistor T1, the compensation control circuit comprises a second transistor T2, and the driving circuit comprises a driving transistor DT;

[0196] The gate of the driving transistor DT is electrically connected with the first node N1, the source of the driving transistor DT is electrically connected with the second node N2, and the drain of the driving transistor DT is electrically connected with the third node N3;

[0197] The gate of the first transistor T1 is electrically connected with the scanning end GT, the source of the first transistor T1 is electrically connected with the data line DL, and the drain of the first transistor T1 is electrically connected with the writing node NW;

[0198] The gate of the second transistor T2 is electrically connected with the compensation control end R2, the source of the second transistor T2 is electrically connected with the first node N1, and the drain of the second transistor T2 is electrically connected with the third node N3;

[0199] The first initialization circuit comprises a third transistor T3;

[0200] The gate of the third transistor T3 is electrically connected with the first reset control end EM3, the source of the third transistor T3 is electrically connected with the first initial voltage end I1, and the drain of the third transistor T3 is electrically connected with the writing node NW;

[0201] The second initialization circuit comprises a fourth transistor T4;

[0202] The gate of the fourth transistor T4 is electrically connected with the second reset control end R1, the source of the fourth transistor T4 is electrically connected with the second initial voltage end I2, and the drain of the fourth transistor T4 is electrically connected with the third node N3;

[0203] The first light-emitting control circuit comprises a fifth transistor T5, and the second light-emitting control circuit comprises a sixth transistor T6;

[0204] The gate of the fifth transistor T5 is electrically connected with the first light-emitting control end EM1, the source of the fifth transistor T5 is electrically connected with the power voltage end VDD, and the drain of the fifth transistor T5 is electrically connected with the second node N2;

[0205] The gate of the sixth transistor T6 is electrically connected with the second light-emitting control end EM2, the source of the sixth transistor T6 is electrically connected with the third node N3, and the drain of the sixth transistor T6 is electrically connected with the anode of O1;

[0206] The third initialization circuit comprises a seventh transistor T7;

[0207] The gate of the seventh transistor T7 is electrically connected to the second reset control terminal R1, the source of the seventh transistor T7 is electrically connected to the third initial voltage terminal I3, and the drain of the seventh transistor T7 is electrically connected to the anode of O1.

[0208] The cathode of O1 is electrically connected to the low-voltage terminal VSS;

[0209] The fourth initialization circuit includes an eighth transistor T8;

[0210] The gate of the eighth transistor T8 is electrically connected to the second reset control terminal R1, the source of the eighth transistor T8 is electrically connected to the first initial voltage terminal I1, and the drain of the eighth transistor T8 is electrically connected to the second node N2.

[0211] In at least one embodiment of the pixel circuit shown in Figure 14, all transistors are p-type transistors, but this is not a limitation.

[0212] As shown in Figure 12, at least one embodiment of the pixel circuit shown in Figure 14 of this disclosure operates as follows:

[0213] The display cycle may include a reset phase S1, a compensation phase S2, a writing phase S3, and an e-light phase S4, which are set sequentially.

[0214] During the reset phase S1, R1 provides a low voltage signal, T4 and T7 are turned on, I2 provides a second initial voltage Vinit2 to N3; I3 provides a third initial voltage Vinit3 to the anode of O1 to clear residual charge on the anode of O1; EM1 provides a low voltage signal, EM3 provides a low voltage signal, T3 is turned on, I1 provides a first initial voltage Vinit1 to NW, T5 is turned on, resetting the potentials of N2 and NW; EM2, R2, and GT all provide high voltage signals, and T2, DT, T6, and T1 are all turned off.

[0215] During the reset phase S1, R1 provides a low voltage signal, T8 is turned on, and I1 provides the first initial voltage Vinit1 to N2 to improve the hysteresis phenomenon of DT and improve the low-frequency flicker phenomenon.

[0216] During compensation phase S2, R2 provides a low voltage signal, and the duration of compensation phase S2 is greater than or equal to 2H (1H is one line scan time). T2 is turned on, and N1 and N3 are connected. EM1 and EM3 provide low voltage signals. T5 and T3 are turned on, and I1 provides the first initial voltage Vinit1 to NW. G1 and R1 both provide high voltage signals, and T4, T6, T1, and T7 are all turned off.

[0217] At the beginning of the compensation stage S2, the potential of N3 is Vinit2, and the potential of N1 is Vinit2 due to the communication between N1 and N3, so that DT can be turned on;

[0218] At the beginning of the compensation stage S2, DT is turned on, and the power voltage signal provided by VDD charges C1 through T5, DT, and T2 until DT is turned off, at which time the potential of N1 is Vdd+Vth, Vdd is the voltage value of the power voltage signal, and Vth is the threshold voltage of DT;

[0219] In the write stage S3, G1 provides a low voltage signal, T1 is turned on, DL provides a data voltage Vdata to NW, and the potential of NW changes from Vinit1 to Vdata. When the data voltage is written, the potential of N1 changes to Vdd+Vth+(C2z / (C1z+C2z))×(Vdata-Vinit1) through capacitive voltage division; C1z is the capacitance value of C1, and C2z is the capacitance value of C2;

[0220] In the write stage S3, R1, EM2, EM1, EM3, and R2 all provide high voltage signals, T2 is turned off, T4 and T7 are turned off, T6 is turned off, and T3 and T5 are turned off;

[0221] In the light-emitting stage S4, EM1 and EM2 both provide low voltage signals, T5 and T6 are both turned on, and DT drives O1 to emit light; the potential of N2 is Vdd, the potential of N3 is Vo1+Vss, Vss is the voltage value of the low voltage signal provided by VSS, and Vo1 is the on voltage of O1;

[0222] In the light-emitting stage S4, the gate-source voltage Vgs of DT is equal to Vth+(C2z / (C1z+C2z))×(Vdata-Vinit1), and Id is equal to K((C2z / (C1z+C2z))×(Vdata-Vinit1)) 2 ; wherein K is the current coefficient of DT, and Id is the driving current generated by DT.

[0223] The pixel driving method disclosed in the embodiments of the present disclosure is applied to the pixel circuit described above, and the display period of the pixel circuit includes a compensation stage and a write stage which are independent of each other; the pixel driving method includes:

[0224] In the write stage, the data writing circuit controls the data voltage provided by the data line to be provided to the write node under the control of the scanning signal;

[0225] In the compensation stage, the compensation control circuit controls the communication between the first node and the third node under the control of the compensation control signal.

[0226] In the pixel driving method provided in the present disclosure, the compensation stage and the writing stage are independent of each other. In the writing stage, the data writing circuit performs data voltage writing, and in the compensation stage, the compensation control circuit performs threshold voltage compensation, so that the threshold voltage compensation is no longer limited by the cycle time, the threshold voltage compensation and the data writing are separated from each other, and high-frequency driving display is achieved.

[0227] The display device provided in the embodiments of the present disclosure includes the pixel circuit described above.

[0228] The above is the preferred embodiment of the present disclosure, and it should be pointed out that for those skilled in the art, without departing from the principles of the present disclosure, a number of improvements and refinements can be made, which should also be considered as the protection scope of the present disclosure.

Claims

1. A pixel circuit, comprising a driving circuit, a first energy storage circuit, a data writing circuit, and a compensation control circuit; the display cycle of the pixel circuit includes mutually independent compensation and writing phases; The control terminal of the driving circuit is electrically connected to the first node, the first terminal of the driving circuit is electrically connected to the second node, and the second terminal of the driving circuit is electrically connected to the third node. The driving circuit is used to generate a driving current under the control of the potential of the first node. The first end of the first energy storage circuit is electrically connected to the first node, and the second end of the first energy storage circuit is electrically connected to the write node. The first energy storage circuit is used to store electrical energy. The data writing circuit is electrically connected to the scanning end, the data line and the writing node respectively, and is used to control the data voltage provided by the data line to be provided to the writing node under the control of the scanning signal provided by the scanning end during the writing stage. The compensation control circuit is electrically connected to the compensation control terminal, the first node, and the third node, respectively, and is used to control the connection between the first node and the third node under the control of the compensation control signal provided by the compensation control terminal during the compensation phase.

2. The pixel circuit as described in claim 1, wherein, It also includes a first initialization circuit; The first initialization circuit is electrically connected to the first reset control terminal, the first initial voltage terminal, and the write node, respectively, and is used to control the connection or disconnection between the first initial voltage terminal and the write node under the control of the first reset control signal provided by the first reset control terminal.

3. The pixel circuit as described in claim 1, wherein, It also includes a second initialization circuit; The second initialization circuit is electrically connected to the second reset control terminal, the second initial voltage terminal, and the first node, respectively, and is used to control the connection or disconnection between the second initial voltage terminal and the first node under the control of the second reset control signal provided by the second reset control terminal.

4. The pixel circuit as described in claim 1, wherein, It also includes a first light-emitting control circuit, a second light-emitting control circuit, and a light-emitting element; The first light-emitting control circuit is electrically connected to the first light-emitting control terminal, the power supply voltage terminal, and the second node, respectively, and is used to control the connection or disconnection between the power supply voltage terminal and the second node under the control of the first light-emitting control signal provided by the first light-emitting control terminal. The second light-emitting control circuit is electrically connected to the second light-emitting control terminal, the third node, and the first electrode of the light-emitting element, respectively, and is used to control the connection or disconnection between the third node and the first electrode of the light-emitting element under the control of the second light-emitting control signal provided by the second light-emitting control terminal; The second electrode of the light-emitting element is electrically connected to the first voltage terminal.

5. The pixel circuit as described in claim 4, wherein, It also includes a third initialization circuit; The third initialization circuit is electrically connected to the second reset control terminal, the third initial voltage terminal, and the first electrode of the light-emitting element, respectively, and is used to control the third initial voltage terminal to be connected or disconnected from the first electrode of the light-emitting element under the control of the second reset control signal provided by the second reset control terminal.

6. The pixel circuit as described in claim 4 or 5, wherein, It also includes a fourth initialization circuit; The fourth initialization circuit is electrically connected to the second reset control terminal, the fourth initial voltage terminal, and the second node, respectively, and is used to control the connection or disconnection between the fourth initial voltage terminal and the second node under the control of the second reset control signal provided by the second reset control terminal.

7. The pixel circuit as described in claim 4, wherein, It also includes a second initialization circuit; The second initialization circuit is electrically connected to the second reset control terminal, the second initial voltage terminal, and the third node, respectively, and is used to control the connection or disconnection between the second initial voltage terminal and the third node under the control of the second reset control signal provided by the second reset control terminal.

8. The pixel circuit according to any one of claims 1 to 7, wherein, It also includes a second energy storage circuit; The second energy storage circuit is electrically connected to the first node and is used to maintain the potential of the first node.

9. The pixel circuit as described in claim 1, wherein, The data writing circuit includes a first transistor, the compensation control circuit includes a second transistor, and the driving circuit includes a driving transistor. The gate of the driving transistor is electrically connected to the first node, the first electrode of the driving transistor is electrically connected to the second node, and the second electrode of the driving transistor is electrically connected to the third node. The gate of the first transistor is electrically connected to the scan terminal, the first electrode of the first transistor is electrically connected to the data line, and the second electrode of the first transistor is electrically connected to the write node. The gate of the second transistor is electrically connected to the compensation control terminal, the first terminal of the second transistor is electrically connected to the first node, and the second terminal of the second transistor is electrically connected to the third node.

10. The pixel circuit as claimed in claim 2, wherein, The first initialization circuit includes a third transistor; The gate of the third transistor is electrically connected to the first reset control terminal, the first terminal of the third transistor is electrically connected to the first initial voltage terminal, and the second terminal of the third transistor is electrically connected to the write node.

11. The pixel circuit as claimed in claim 3, wherein, The second initialization circuit includes a fourth transistor; The gate of the fourth transistor is electrically connected to the second reset control terminal, the first terminal of the fourth transistor is electrically connected to the second initial voltage terminal, and the second terminal of the fourth transistor is electrically connected to the first node.

12. The pixel circuit as claimed in claim 4, wherein, The first light-emitting control circuit includes a fifth transistor, and the second light-emitting control circuit includes a sixth transistor; The gate of the fifth transistor is electrically connected to the first light-emitting control terminal, the first electrode of the fifth transistor is electrically connected to the power supply voltage terminal, and the second electrode of the fifth transistor is electrically connected to the second node. The gate of the sixth transistor is electrically connected to the second light-emitting control terminal, the first electrode of the sixth transistor is electrically connected to the third node, and the second electrode of the sixth transistor is electrically connected to the first electrode of the light-emitting element.

13. The pixel circuit as claimed in claim 5, wherein, The third initialization circuit includes a seventh transistor; The gate of the seventh transistor is electrically connected to the second reset control terminal, the first terminal of the seventh transistor is electrically connected to the third initial voltage terminal, and the second terminal of the seventh transistor is electrically connected to the first terminal of the light-emitting element.

14. The pixel circuit as claimed in claim 6, wherein, The fourth initialization circuit includes an eighth transistor; The gate of the eighth transistor is electrically connected to the second reset control terminal, the first terminal of the eighth transistor is electrically connected to the fourth initial voltage terminal, and the second terminal of the eighth transistor is electrically connected to the second node.

15. The pixel circuit as claimed in claim 7, wherein, The second initialization circuit includes a fourth transistor; The gate of the fourth transistor is electrically connected to the second reset control terminal, the first terminal of the fourth transistor is electrically connected to the second initial voltage terminal, and the second terminal of the fourth transistor is electrically connected to the third node.

16. A pixel driving method, applied to a pixel circuit as described in any one of claims 1 to 15, wherein the display cycle of the pixel circuit includes mutually independent compensation phases and writing phases; The pixel driving method includes: During the writing phase, the data writing circuit, under the control of the scan signal, controls the data voltage provided by the data line to be supplied to the writing node; During the compensation phase, the compensation control circuit controls the connection between the first node and the third node under the control of the compensation control signal.

17. A display device comprising a pixel circuit as claimed in any one of claims 1 to 15.

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