Integrated circuit having a contacting unit with pillars

Abstract

An integrated circuit (100) comprises an electronic circuit (2) formed in a substrate (1), and a connector (5) electrically connected to the electronic circuit (2) and extending to the outside of the substrate (1). The contacting unit (50) is made of conductive material and is positioned on the substrate (1). The contacting unit (50) is electrically connected to the connector (5) and comprises a plate-like base (54) and a plurality of pillars (55) positioned on the plate-like base (54).

Description

[0001] Description

[0002] INTEGRATED CIRCUIT HAVING A CONTACTING UNIT WITH PILLARS

[0003] Technical Field

[0004]

[0001] The present disclosure generally relates to integrated circuits. In particular, the present disclosure relates to integrated circuits having a contacting unit with a plurality of pillars and a method of manufacturing such integrated circuits.

[0005] Background

[0006]

[0002] Integrated circuits (IC) are used worldwide in a wide range of electronic devices, such as for example RFID tags. An integrated circuit, also known as chip, is made up of an electronic circuit which is etched into a small piece of semiconductor material, usually silicon. The electronic circuit may include multiple interconnected electronic components such as transistors, resistors and capacitors. The technique of photolithography is used to etch the electronic circuit into the small piece of semiconductor material. An integrated circuit usually includes two connectors which are electrically connected to the electronic circuit and extend to the outside of the small piece of semiconductor material. The connectors allow for the input and / or output of communication and / or powering to the electronic circuit. Components such as an antenna wire or the like may be connected to the electronic circuit via the connectors of the integrated circuit. A connector may correspond to a thin metal film using material such as aluminum, titanium or tungsten. A connector of an integrated circuit is also referred to as contact pad or bonding pad.

[0007]

[0003] To connect components such as an antenna wire to a connector of the integrated circuit, bonding processes such as ultrasonic bonding, thermocompression bonding, laser bonding, welding or conductive gluing are used.

[0004] The technique of photolithography has been improved over the last years and allow the manufacturers of integrated circuits to keep reducing the size of integrated circuits. Whereas a couple of years ago, integrated circuits were sized about 1.5 x 1.5 mm, today integrated circuits have a size in the range of about 0.5 x 0.5 mm. As a consequence of this size reduction of integrated circuits, also the connectors of the integrated circuits have decreased in size over the last years and making the bonding (hot and cold) of components such as an antenna wire to the connectors more and more difficult. To allow for the connection of large sized wires to the small connectors, several approaches have been developed.

[0008]

[0005] U.S. Pat. No. 5,572,410 discloses a chip being directly connected to wire antenna. In this patent, a wire is wound around a core and the two ends of the wire are soldered to metal paths deposited over the active layer of the chip. This technology, which is called “direct bonding”, minimizes the size of the resulting transponder, the number of its constituting elements as the related production costs. The metal paths which are extensions of the usual small pads of the chips, are called megabumps (or megapads) and show a dimension adapted to the connection of the antenna wire (which shows typically a diameter of 60-80 pm). For example, a typical chip used for such applications is the Hitag p from NXP, wherein the chip surface area is of 550x550 pm for 150 pm thickness and the megabump show a surface area of 294x164 pm (while the original pads are only 60x60 pm).

[0009]

[0006] A further known process to address the size reduction problematic is the RDL (redistribution layer) process. RDL includes the step of adding an extra metal layer on a chip (integrated circuit) that makes the connectors bigger in size and / or available in other locations of the chip.

[0010]

[0007] A problem with these approaches is the thermal load induced from any bonding process. The applied thermal stress may degrade the adhesion of the megabumps (extra metal layers) on the surface of the small piece of semiconductor material, which reduces the bonding strength of the megabumps (extra metal layers) on the surface of the small piece of semiconductor material. As a consequence, the quality of the electrical connection and the final product reliability decreases and the electrical connection failures increases.

[0011]

[0008] A further problem is the mechanical load induced during bonding process. The applied mechanical stress may also degrade the adhesion of the megabumps (extra metal layers) on the surface of the small piece of semiconductor material and thus decrease the quality of the electrical connection.

[0012]

[0009] The present disclosure is directed, at least in part, to improving or overcoming one or more aspects of prior systems.

[0013] Summary of the Disclosure

[0014]

[0010] According to a first aspect of the present disclosure, an integrated circuit includes an electronic circuit formed in a substrate and a connector which is electrically connected to the electronic circuit and extends to the outside of the substrate. The integrated circuit further includes a contacting unit which is made of conductive material and is positioned on the substrate. The contacting unit is electrically connected to the connector and includes a plate-like base and a plurality of pillars positioned on the plate-like base.

[0015]

[0011] According to a second aspect of the present disclosure, an RFID tag includes an integrated circuit according to the first aspect of the present disclosure and an antenna wire electrically connected to a contacting unit of the integrated circuit.

[0016]

[0012] According to a third aspect of the present disclosure, a method of manufacturing an integrated circuit includes the step of providing an electronic circuit formed in a substrate and a connector electrically connected to the electronic circuit and extending to the outside of the substrate. The method further includes the step of applying, for example by sputtering, a first layer of conductive material onto the substrate such that the first layer of conductive material is electrically connected to the connector and covers at least part of the surface of the substrate. The method further includes the step of applying a first template with first openings onto the first layer of conductive material, for example by photolithography, the step of applying, for example by electroplating, a second layer of conductive material onto the first layer such that it fills at least a part of the first openings and the step of applying a second template with second openings onto the second layer of conductive material respectively onto the first template, for example by photolithography, such that the second openings overlap with the first openings. Further, the method includes the step of applying, for example by electroplating, a third layer of conductive material onto the second layer such that it fills at least a part of the second openings. The method further includes the step of removing, for example by stripping off, the first and second templates, and the step of removing, for example by etching, a layer of material from the top of the body formed by the first, second and third layers of conductive material such that the first layer of conductive material in some portions is completely removed from the surface of the substrate.

[0017]

[0013] According to a fourth aspect of the present disclosure, a method of manufacturing an RFID tag includes the method steps according to the third aspect of the present disclosure and further includes the step of providing an antenna wire and the step of connecting the antenna wire to the contacting unit of the integrated circuit by bonding techniques such as ultrasonic bonding, thermocompression bonding, laser bonding, welding or conductive gluing.

[0018]

[0014] Other features and aspects of the present disclosure will be apparent from the following description and the accompanying drawings.

[0019] Brief Description of the Drawings

[0020]

[0015] Fig. 1 shows a schematic sectional view on an exemplary embodiment of an integrated circuit 100 according to the present disclosure.

[0021]

[0016] Fig. 2 corresponds to Fig. 1 but further includes an antenna wire 80 positioned on the contacting unit 50.

[0017] Fig. 3 shows a simplified schematic sectional view on a further exemplary embodiment of an integrated circuit 100 according to the present disclosure.

[0022]

[0018] Fig. 4 shows a top view on a portion of a further exemplary embodiment of an integrated circuit 100 according to the present disclosure.

[0023]

[0019] Fig. 5 shows a sectional view along line A-A of the integrated circuit 100 as shown in Fig. 4.

[0024]

[0020] Fig. 6 shows a sectional view along line B-B of the integrated circuit 100 as shown in Fig. 4.

[0025]

[0021] Fig. 7 shows a schematic sectional view on a further exemplary embodiment of an integrated circuit 100 according to the present disclosure.

[0026]

[0022] Fig. 8 shows an electronic circuit 2 embedded in a substrate 1 and a first connector 5 and a second connector 6 extending from the electronic circuit 2 to the outside of the substrate 1.

[0027]

[0023] Fig. 9 corresponds to Fig. 8, but in addition shows a first layer 10 of conductive material positioned on the substrate 1, the first connector 5 and the second connector 6.

[0028]

[0024] Fig. 10 corresponds to Fig. 9, but in addition shows a first template 14 positioned on the first layer 10 of conductive material.

[0029]

[0025] Fig. 11 corresponds to Fig. 10, but in addition shows a second layer 20 of conductive material which fills a part of the first openings 15 of the first template 14.

[0030]

[0026] Fig. 12 corresponds to Fig. 11, but in addition shows a second template 24 with second openings 25 which is positioned on the second layer 20 of conductive material and on the first template 14.

[0031]

[0027] Fig. 13 corresponds to Fig. 12, but in addition shows a third layer 30 of conductive material which fills a part of the second openings 25 of the second template 24.

[0032]

[0028] Fig. 14 corresponds to Fig. 13, but differs in that the first template 14 and the second template 24 is removed.

[0029] Fig. 15 corresponds to Fig. 14, but differs in that a layer of constant thickness (marked with dotted line) is removed from the top of the body formed by the first layer 10, the second layer 20 and the third layer 30 of conductive material.

[0033]

[0030] Fig. 16 is an overview of the method 300 of manufacturing an integrated circuit 100.

[0034]

[0031] Fig. 17 illustrates exemplary embodiments of integrated circuits in top view which differ in the shape of the plurality of pillars

[0035] Detailed Description

[0036]

[0032] The following is a detailed description of exemplary embodiments of the present disclosure. The exemplary embodiments described herein are intended to teach the principles of the present disclosure, enabling those of ordinary skill in the art to implement and use the present disclosure in many different environments and for many different applications. Therefore, the exemplary embodiments are not intended to be, and should not be considered as, a limiting description of the scope of protection. Rather, the scope of protection shall be defined by the appended claims.

[0037]

[0033] The present disclosure is based at least in part on the realization that the quality of the electrical connection of an integrated circuit to components (such as an antenna wire) may be improved by providing an integrated circuit with a specially formed contacting unit on the substrate of the integrated circuit, to which the components are connected. The contacting unit includes a plurality of pillars positioned on a plate like base. Compared to known connecting units such as megabumps or extra metal layers, the contacting unit of the present disclosure has an increased surface area to which components may be connected. As a consequence, the thermal cooling in the area of the contacting unit is improved which reduces the thermal stress (the thermal charge) on the integrated circuit. The reduced thermal stress reduces the degradation of the adhesion of the contacting unit on the surface of the substrate and, in case the substrate includes an outer protective layer, reduces the degradation of the outer protective layer from the rest of the substrate. During bonding the thermal energy flux is concentrated on the top surface of the pillars (bonding interface) and increases locally the temperature enhancing and accelerating the diffusion bonding process. At the same time the energy flowing in the pillar will be exposed to additional convection cooling on the length / height of the pillar reducing the temperature on the surface of the chip.

[0038]

[0034] It has been realized that that the pillars of the contacting unit may act as stress relive elements. The pillars may deform and thus reduce the mechanical charge on the integrated circuit.

[0039]

[0035] A further advantage is that the conductive material usage and thus the production costs may be reduced compared to other known connecting units such as megabumps (extra metal layers). The contacting units may be layout over large portions of the substrate's surface to ease the wire placement and increase machine throughput.

[0040]

[0036] It has been found that the quality of the electrical connection between a wire (such as an antenna copper wire) and a contacting unit with a plurality of pillars is improved. Before a wire is connected to the contacting unit, an insulation has been removed from the wire. However, small amounts of the insulation often remain on the wire. When the wire is hot-bonded to the contacting device, the heated and deformable wire is pressed onto the contacting unit. The pillars of the contacting unit pierce the wire and pierce the small amounts of insulation remained on the wire. The electrical connection between the contact unit and the wire is improved by this “piercing”.

[0041]

[0037] Another realization is that by first applying multiple layers of material onto the substrate and by removing a layer of material in a final step, a contacting unit according to the present disclosure may be manufactured. The method applies, for example by sputtering, a first layer of conductive material onto the substrate such that the first layer of conductive material is connected to the connector and covers at least part of the surface of the substrate. In a next step, the method applies a first template with first openings onto the first layer of conductive material. The first openings are through holes extending through the first template. The first openings (through holes) allow material to be filled into them such that the material is positioned on (in contact with) the first layer. The first template may for example be provided using photolithography.

[0042]

[0038] Photolithography is a well-known method. The method begins with a photosensitive material, called a photoresist, being provided on a substrate. A photomask that contains the desired pattern is then placed over the photoresist. Light is shone through the photomask, exposing the photoresist in certain areas. The exposed areas undergo a chemical change, making them either soluble or insoluble in a developer solution. By either removing photoresist that has been exposed or not, a template with openings (through holes) is developed. The openings of the template correspond to the desired pattern respectively an inverse / negative image of the desired pattern.

[0043]

[0039] The new method according to the present disclosure continues with applying, for example by electroplating, a second layer of conductive material onto the first layer such that it fills at least a part of the first openings of the first template. According to an exemplary embodiment, the second layer of conductive material may be filled into the first openings such that it does not exceed the height of the first openings, i.e., the second layer of conductive material does not protrude beyond the upper end of the first openings.

[0044]

[0040] The method then applies a second template with second openings onto the second layer of conductive material respectively onto the first template, for example by photolithography. The second template is positioned on the first template respectively the second layer of conductive material such that the second openings of the second template overlap with the first openings of the first template. In other words, the second template is positioned onto the second layer of conductive material respectively onto the first template such that the second openings of the second template are adjoining the second layer of conductive material. Accordingly, the second template is positioned onto the second layer of conductive material respectively onto the first template such that, when a third layer of conductive material is filled into the second openings of the second template, the third material of conductive material is positioned on the second layer of conductive material to be conductively connected to the second layer of conductive material.

[0045]

[0041] In a next step, a third layer of conductive material is applied onto the second layer such that it fills at least a part of the second openings, for example by electroplating. According to an exemplary embodiment, the third layer of conductive material may be filled into the second openings such that it does not exceed the height of the second openings, i.e., the third layer of conductive material does not protrude beyond the upper end of the second openings.

[0046]

[0042] The method further includes the step of removing, for example by stripping off, the first and second templates, and the step of removing, for example by etching, a layer of material from the top of the body formed by the first, second and third layers of conductive material such that the first layer of conductive material in some portions is completely removed from the surface of the substrate. The resulting body forms one or more contacting units which includes a plurality of pillars positioned on a plate-like base.

[0047]

[0043] The substrate in which the electronic circuit is formed may include a semiconductor material such as silicon. The semiconductor material may be provided as a wafer which is a thin slice of material. The substrate of the integrated circuit may comprise an outer protective layer having different material from the rest of the substrate and serving e.g., as protection of the electronic components or as electronic isolation. The substrate may for example include a semiconductor material such as silicon as base material and an outer protective layer called passivation made of material such as silicon nitride (Si3N4) or silicon dioxide (SiO2). In addition to this initial protective layer a thin Polyimide (PI) is typically used as a stress relief and protective insulating layer before packaging or redistribution layer (RDL). In the context of the present disclosure, substrate refers to both, the base material (such as silicon) and the outer protective layers such as passivation layer (silicon nitride or silicon dioxide) and PI (Polyimide) layer.

[0048]

[0044] The connector (contact pad, bonding pad) may be formed as an integral part of the electronic circuit or may be a separate unit electrically connected to the electronic circuit. An integrated circuit usually includes two connectors, but may comprise more than two connectors.

[0049]

[0045] The contacting unit is configured to be connected to other components such as for example an antenna wire. The contacting unit is made of a conductive material such as for example Copper (Cu) or gold (Au). The contacting unit includes a plate-like base and a plurality of pillars positioned on the plate-like base. The plurality of pillars is arranged on the plate-like base such that the pillars are connected to each other at their base via the plate-like base and both, electricity and heat may flow from one pillar to another pillar via the platelike base.

[0050]

[0046] The plate-like base may be of any shape, e.g., it may for example have the shape of a rectangular plate or an L-shaped plate or a combination thereof. Preferably, the plate-like base has a uniform thickness, but may also vary in thickness. The thickness is measured perpendicular to the surface of the substrate on which the plate-like base is positioned. The specially formed contacting-unit according to the present disclosure allows to provide a thin plate - like base in combination with the plurality of pillars. In an exemplary embodiment of the present disclosure, the plate-like base has a uniform thickness in the range of 0.25-10 pm, preferably in the range of 3-5 pm.

[0051]

[0047] A pillar of the plurality of pillars may for example have the shape of a right cylinder, i.e., the axis is perpendicular to the bases of the cylinder. According to another example, a pillar of the plurality of pillars may have the shape of a prism. The prism may for example be a triangular prism, a rectangular prism, a cuboid or a hexagonal prism. In the context of this disclosure, the feature “pillar” includes all structures whose main direction of extension is perpendicular to the plate-like base and whose side walls run in parallel to the main direction of extension, wherein the pillar’s bottom surface and the pillar’s opposite top surface are aligned parallel to the plate-like base and may have any shape, e.g. circular, rectangular or square. According to an exemplary embodiment, the feature “pillar” may also include structures whose main direction of extension is oblique to the plate-like base and whose side walls run in parallel to the main direction of extension, wherein the pillar’s bottom surface and the pillar’s opposite top surface are aligned in parallel or are obliqued to the plate-like base and may have any shape, e.g. a circular, rectangular or square. In an exemplary embodiment, the feature “pillar” may also include structures whose side walls run not in parallel to the main direction of extension, but whose side walls run towards each other such that the structure narrows towards the top respectively towards the bottom.

[0052]

[0048] In an exemplary embodiment of the present disclosure, at least one of the plurality of pillars is a right cylinder with circular bases, each of the circular bases having a diameter in the range of 10-80 pm, preferably in the range of 15-30 pm. Such pillar shape and pillar dimension has been proven to provide sufficient mechanical strength and to sufficiently increase the surface area of the contacting unit for improving the thermal cooling characteristics. All pillars of the plurality of pillars may have the above described dimension and shape.

[0053]

[0049] In a further exemplary embodiment of the present disclosure, at least one of the plurality of pillars is a rectangular prism (cuboid), whose bases having a width in the range of 10-80 pm and a depth in the range of 10-80 pm, preferably a width in the range of 15-30 pm and a depth in the range of 15-30 pm. Such pillar shape and pillar dimension has been proven to provide sufficient mechanical strength and to sufficiently increase the surface area of the contacting unit for improving the thermal cooling characteristics. All pillars of the plurality of pillars may have the above described shape and dimension.

[0050] According to a further exemplary embodiment, the pillars of the plurality of pillars differ in shape. For example, some pillars may have a shape of a cuboid and some pillars may have the shape of rectangular prism. Any other combination of different shapes is possible.

[0054]

[0051] An integrated circuit according to this disclosure includes at least one contacting unit with a plurality of pillars positioned on a plate-like base. However, the integrated circuit may comprise a plurality of contacting units, each of which has a plurality of pillars positioned on a plate-like base. The integrated may also comprise a plurality of contacting units, of which some are contacting units with a plurality of pillars positioned on a plate-like base (for example one, two or three) and some are contacting units without pillars such as megapads or an extra metal layer (for example one, two or three).

[0055]

[0052] According to an exemplary embodiment of the present disclosure, the integrated circuit includes a first connector and a second connector. Each of the first and second connectors is electrically connected to the electronic circuit and extends to the outside of the substrate. A first contacting unit is electrically connected to the first connector and a second contacting unit is electrically connected to the second connector. Each of the first and second contacting units is made of conductive material, is positioned on the substrate and includes a plate-like base and a plurality of pillars positioned on the plate-like base. The first contacting unit and the second contacting unit are separated from each other, i.e., although they are electrically connected via the first and second connectors and the electronic circuit, they are not (physically) in contact with each other in order to prevent a short circuit.

[0056]

[0053] The plurality of pillars may be evenly distributed on the plate-like base. According to an exemplary embodiment, at least one of the plurality of pillars is distanced from its adjacent pillar (pillars) by a distance in the range of 10-50 pm, preferably in the range of 20-30 pm. All pillars of the plurality of pillars may be distanced from its respective adjacent pillar (pillars) by this distance. This distance has been found to be particularly beneficial for cold bonding technologies such as conductive glues as this structure enhances the wetting of the glue and increases the bonding resistance especially in shared stress.

[0057]

[0054] According to a further exemplary embodiment, at least one of the plurality of pillars has a height of 10-80 pm, preferably a height of 15-30 pm. The height is measured perpendicular to the surface of the plate-like base on which the contacting unit is positioned. Such height has been proven to sufficiently increase the surface area of the contacting unit and to provide improved thermal cooling characteristics. In a preferred embodiment each pillar of the plurality of pillars has the same height.

[0058]

[0055] According to a further exemplary embodiment, at least one of the plurality of pillars includes a solder cap. After the electroplating of the third layer, an additional electroplating step for the deposition of Sn / Ag solder material is applied creating a fourth layer. The application of a Sn / Ag solder material will allow alternative bonding such as solder bonding.

[0059]

[0056] According to a further exemplary embodiment, the plate-like base includes a first layer made of a first conductive material and a second layer made of a second conductive material. The second conductive material is different from the first conductive material. By using such first and second layer, different materials may be advantageously combined with each other. For example, the first layer may be made of TiW, the second layer may be made of Cu, the third layer may be made of Cu and the fourth layer may be Sn / Ag.

[0060]

[0057] The combination of different materials may induce to introduce the correct UBM (under barrier metal) creating excellent barrier properties and adhesion in-between the layers. For example, in the above configuration a Ni diffusion barrier may be used in between the Cu and the Sn / Ag layers. Alternatively, the third layer been a Cu material, the surface will need to be finished with a Nickel-Gold UBM or a Nickel / Palladium / Gold UBM preventing any kind of corrosion which would degrade any bonding process.

[0058] Referring now to the method of manufacturing an integrated circuit, the first layer of conductive material may be applied onto the substrate by sputtering. The first template and the second template may be generated by photolithography. For filling the openings of the first and second templates with the second and third layer of conductive material electroplating may be applied template. The first and second templates may be removed by etching. The layer of material which is removed from the top of the body formed by the first, second and third layers of conductive material may be removed by etching. The mentioned techniques such as sputtering, electroplating and etching are given as examples only. The mentioned techniques may be replaced by any other technique.

[0061]

[0059] The layer of material which is removed from the body formed by the first, second and third layers of conductive material may have a uniform thickness. The uniform thickness may correspond to the thickness of the first layer of conductive material and may be in the range of 0.050-0.500 pm, preferably in the range of 0.075-0.350 pm.

[0062]

[0060] When removing the layer of material from the body formed by the first, second and third layers of conductive material, portions of the first layer of material are completely removed from the surface of the substrate to form the contacting unit. These portions correspond to the portions of the first layer of material which are not covered by the second layer and / or the third layer. In other words, the portions in which the first layer of material is completely removed from the surface of the substrate correspond to the portions of the first layer of material which are exposed to the outside.

[0063]

[0061] The conductive material of the first layer may be different from the conductive material of the second layer. In addition, the conductive material of the third layer may be different from the conductive material of the first and second layers.

[0064]

[0062] Fig. 1 shows a schematic sectional view on a further exemplary embodiment of an integrated circuit 100 according to the present disclosure. The integrated circuit 100 includes an electronic circuit 2 which is formed in a substrate 1. The substrate 1 includes an outer protective layer 3 called passivation made of material such as silicon nitride (Si3N4) or silicon dioxide (SiO2). A connector 5 extends from the electronic circuit 2 to the outside of the substrate 1. A contacting unit 50 is positioned on the substrate 1 such that it is in contact with the connector 5. The contacting unit 50 includes a plate-like base 54 and a plurality of pillars 55 positioned on the plate-like base 54. Of course, the electronic circuit 2 may have additional connectors 5 (not illustrated) to allow for the input and / or output of communication and / or powering to the electronic circuit.

[0065]

[0063] Fig. 2 corresponds to Fig. 1 but further includes an antenna wire 80 positioned on the contacting unit 50. The antenna wire 80 is positioned on the contacting unit 50 such that the antenna wire 80 is in contact with both the pillars 55 and the plate-like base 54 and such that the pillars 55 protrude into the antenna wire 80. The embodiment shown in Fig. 2 corresponds to an RFID tag 200 according to the present disclosure.

[0066]

[0064] Fig. 3 shows a simplified schematic sectional view on a further exemplary embodiment of an integrated circuit 100 according to the present disclosure. The integrated circuit 100 includes an electronic circuit 2. The substrate 1 may include an outer protective layer 3 called passivation made of material such as silicon nitride (Si3N4) or silicon dioxide (SiO2). The electronic circuit 2 is formed in the substrate 1. A first connector 6 and a second connector 7 extend from the electronic circuit 2 to the outside of the substrate 1. A first contacting unit 60 is positioned on the substrate 1 and is connected to the first connector 6. A second contacting unit 70 is positioned on the substrate 1 and is connected to the second connector 7. Each of the first contacting unit 60 and the second contacting unit 70 comprises a plate-like base 54 and a plurality of pillars 55 positioned on the plate-like base 54.

[0067]

[0065] Fig. 4 shows a top view on a portion of a further exemplary embodiment of an integrated circuit 100 according to the present disclosure. The integrated circuit 100 includes a substrate 1. A contacting unit 50 is positioned on top of the substrate 1. The contacting unit 50 is also positioned on top of a connector 5. The connector 5 is displayed in dashed line as it is positioned behind the contacting unit 50 in viewing direction. The contacting unit 50 includes a plate-like base 54 on which multiple pillars 55 are positioned. The plate-like base 54 includes an L-shaped portion, the L-shaped portion being positioned on top of the connector 5 and connecting the connector 5 with the rest of the plate-like base 54. Each of the multiple pillars is formed as a rectangular prism (cuboid), the bases of which having a width w and a depth d.

[0068]

[0066] Fig. 5 shows a sectional view along line A-A of the portion of the integrated circuit 100 as shown in Fig. 4. The integrated circuit 100 includes an electronic circuit 2. The electronic circuit 2 is formed in a substrate 1. The substrate 1 includes an outer protective layer 3. A contacting unit 50 is positioned on the substrate 1. The contacting unit 50 includes a plate-like base 54 on which fifteen pillars 55 are positioned. The fifteen pillars 55 are connected to each other at their base via a plate-like base 54.

[0069]

[0067] Fig. 6 shows a sectional view along line B-B of the portion of the integrated circuit 100 as shown in Fig. 4. The integrated circuit 100 comprises an electronic circuit 2. The electronic circuit 2 is formed in a substrate 1. The substrate 1 includes an outer protective layer 3. A connector 5 extends from the electronic circuit 2 to the outside of the substrate 1. A contacting unit 50 is positioned on the substrate 1 and in contact with the connector 5. The contacting unit 50 includes a plate-like base 54 on which two pillars 55 are positioned which are connected to each other at their base via a plate-like base 54.

[0070]

[0068] Fig. 7 shows a schematic sectional view on a further exemplary embodiment of an integrated circuit 100 according to the present disclosure. The integrated circuit 100 includes a substrate 1 with an electronic circuit 2. The substrate 1 includes an outer protective layer 3. A first connector 6 and a second connector 7 extend from the electronic circuit 2 to the outside of the substrate 1. A first contacting unit 60 is connected to the first connector 6. A second contacting unit 70 is connected to the second connector 7. Each of the first contacting unit 60 and the second contacting unit 70 includes at least three layers of material, namely a first layer 10 of conductive material, a second layer 20 of conductive material and a third layer 30 of conductive material. The first layer 10 of conductive material and the second layer 20 of conductive material form a plate-like base 54 and a third layer 30 of conductive material forms a plurality of pillars 55 positioned on the plate-like base 54. UBM (under barrier metal) layers are not displayed.

[0071]

[0069] Fig. 8 I is a top view and Fig. 8 II is a sectional view along line A- A in Fig. 8 I. Fig. 8 show an electronic circuit 2 embedded in a substrate 1 and a first connector 6 and a second connector 7 extending from the electronic circuit 2 to the outside of the substrate 1. The substrate 1 includes an outer protective layer 3.

[0072]

[0070] Fig. 9 I is a top view and Fig. 9 II is a sectional view along line A- A in Fig. 9 I. Fig. 9 correspond to Fig. 8, but in addition show a first layer 10 of conductive material positioned on the substrate 1, the first connector 5 and the second connector 6. This first layer covers the full surface.

[0073]

[0071] Fig. 10 I is a top view and Fig. 10 II is a sectional view along line A-A in Fig. 10 1. Fig. 10 correspond to Fig. 9, but in addition shows a first template 14 positioned on the first layer 10 of conductive material. The first template 14 includes first openings 15.

[0074]

[0072] Fig. 11 1 is a top view and Fig. 11 II is a sectional view along line A-A in Fig. 11 1. Fig. 11 correspond to Fig. 10, but in addition shows a second layer 20 of conductive material which is provided on the first layer 10 such that it fills a part of the first openings 15 of the first template 14.

[0075]

[0073] Fig. 12 I is a top view and Fig. 12 II is a sectional view along line A-A in Fig. 12 I. Fig. 12 corresponds to Fig. 11, but in addition shows a second template 24 which is positioned on the second layer 20 of conductive material and the first template 14. The second template 24 is positioned on the second layer 20 of conductive material such that the second openings 25 are positioned above the second layer 20 of conductive material. Accordingly, when viewing through the second openings 25 from above, the second layer 20 is visible. In other words, the second openings 25 adjoin the second layer 20 or in other words the second openings 25 overlap with the first openings 15. Due to this arrangement, when a material is filled into the second openings 25, the material is positioned on the second layer 20 of conductive material (is in contact with the second layer 20 of conductive material).

[0076]

[0074] Fig. 13 I is a top view and Fig. 13 II is a sectional view along line A-A in Fig. 13 I. Fig. 13 corresponds to Fig. 12, but in addition shows a third layer 30 of conductive material which is provided on the second layer 20 such that it fills a part of the second openings 25 of the second template 24. The third layer 30 of conductive material is in contact with the second layer 20 of conductive material.

[0077]

[0075] Fig. 14 I is a top view and Fig. 14 II is a sectional view along line A-A in Fig. 14 I. Fig. 14 corresponds to Fig. 13, but differs in that the first template 14 and the second template 24 are removed.

[0078]

[0076] Fig. 15 I is a top view and Fig. 15 II is a sectional view along line A-A in Fig. 15 1. Fig. 15 corresponds to Fig. 14, but differs in that a layer of material with constant thickness (marked with dotted line) is removed from the top of the body formed by the first layer 10 of conductive material, the second layer 20 of conductive material and the third layer 30 of conductive material. The layer of constant thickness is removed over the entire length of the body formed by the first layer 10 of conductive material, the second layer 20 of conductive material and the third layer 30 of conductive material, i.e., is partly removed from the first layer 10 of conductive material, the second layer 20 of conductive material and the third layer 30 of conductive material. The layer of constant thickness which is removed from the body corresponds to the thickness of the first layer 10 of conductive material such that the first layer 10 of conductive material is completely removed from the surface of the substrate 1 in these portions of the first layer 10 of conductive material which are not covered by the second layer 20 of conductive material and / or third layer 30 of conductive material. The first layer 10 of conductive material, the second layer 20 of conductive material and the third layer 30 of conductive material as a consequence form a first contacting unit 60 positioned on the left side of the substrate 1 and a second contacting unit 70 positioned on the right side of the substrate 1. The first contacting unit 60 and the second contacting unit 70 are not in contact with each other as the first layer 10 of conductive material positioned between them has been removed.

[0079]

[0077] Fig. 16 is an overview of the method steps required to manufacture an integrated circuit according to the present disclosure. Potential UBM (under barrier metal) have been excluded.

[0080]

[0078] Fig. 17 illustrates exemplary embodiments of integrated circuits according to the present disclosure in top view which differ in the shape of the plurality of pillars. In Fig. 17 1, each of the plurality of pillars has a shape of a right cylinder with circular bases. In Fig. 17 II, each of the plurality of pillars has a shape of a cuboid. In Fig. 17 III, each of the plurality of pillars has a shape of a rectangular prism. In Fig. 17 IV, each of the plurality of pillars has a shape of a triangular prism. In Fig. 17 V, each the plurality of pillars has a shape of a hexagonal prism. In Fig. 17 VI the shapes of the plurality of pillars provided on the contacting unit 60 or on the contacting unit 70 differ from each other. Some of the plurality of pillars have a shape of a cuboid and some of the plurality of pillars have the shape of a rectangular prism.

[0081] Industrial applicability

[0082]

[0079] With reference to Fig. 8 to Fig. 16, the method 300 of manufacturing an integrated circuit 100 according to the present disclosure is explained. Potential UBM (under barrier metal) have been excluded.

[0083]

[0080] In a first method step 301, an electronic circuit 2 formed in a substrate 1 and a connector 5 electrically connected to the electronic circuit 2 and extending to the outside of the substrate 1 is provided. The result of this method step is an arrangement as shown in Fig. 8.

[0084]

[0081] In a next method step 302, a first layer 10 of conductive material is applied onto the substrate 1. The first layer may have a uniform height. The first layer 10 of conductive material is applied such that it is connected to the connector 5 and covers at least part of the surface of the substrate 1. The first layer may be applied to the substrate 1 by sputtering, which is a well-known process in the chip manufacturing industry. The result of this method step is an arrangement as shown in Fig. 9.

[0085]

[0082] In a next method step 303, a first template 14 with first openings 15 is applied onto the first layer 10 of conductive material. The first template 14 with first openings 15 may for example be formed by photolithography, i.e., by providing a first photoresist, then a mask, then light to expose the photoresist in certain areas and then developing the first openings 15 by either removing photoresist that has been exposed or not. The result of this method step is an arrangement as shown in Fig. 10.

[0086]

[0083] In a next method step 304, a second layer 20 of conductive material is applied onto the first layer 10 of conductive material such that it fills, at least partly, the first openings 15 of the first template 14. The second layer 20 of conductive material may be applied by electroplating. The result of this method step is an arrangement as shown in Fig. 11.

[0087]

[0084] In a next method step 305, a second template 24 with second openings 25 is applied onto the second layer 20 of conductive material respectively onto the first template 14 such that the second openings overlap with the first openings 15. The second template 24 with second openings 25 may for example be formed by photolithography, i.e., by providing a second photoresist, then a mask, then light to expose the photoresist in certain areas and then developing the second openings by either removing photoresist that has been exposed or not. The second template 24 is positioned on the second layer 20 of conductive material respectively onto the first template 14 such that the second openings 25 are positioned above the second layer 20 of conductive material. Above in this context means that the second openings 25 are adjacent to the second layer 20, i.e., a third material may be applied onto the second layer 20 via the second openings 25. Due to this arrangement, a third material which is filled into the second openings 25 is positioned on the second layer 20 (is in contact with the second layer 20). The result of this method step is an arrangement as shown in Fig. 12.

[0088]

[0085] In a next method step 306, a third layer 30 of conductive material is applied onto the second layer 20 of conductive material such that it fills, at least partly, the second openings 25. The third layer 30 of conductive material is positioned on (is in contact with) the second layer 20 of conductive material. The third layer 30 of conductive material may be applied by electroplating. The result of this method step is an arrangement as shown in Fig. 13.

[0089]

[0086] In a next method step 307, the first template 14 and the second template 24 are removed, for example by stripping off, such that a body formed by the first, second and third layers 10, 20, 30 of material is formed on the substrate 1. The body has four pillars connected at their base. The first layer 10 of conductive material connects all four pillars which each other as shown in Fig. 14.

[0090]

[0087] In a final step 308, a layer of material is removed from the top of the body formed by the first, second and third layers 10, 20, 30 such that the first layer 10 of conductive material in some portions is completely removed from the surface of the substrate 1. The layer of material removed from the top of the body may have a uniform thickness. As a result of this method step, a contacting unit 60, 70 is formed on the substrate 1, as shown in Fig. 15. The embodiment shown in Fig. 15 includes a first contacting unit 60 and a second contacting unit 70, each of which includes two pillars 55 (formed by the third layer 30 of conductive material) positioned on a plate-like base 54 (formed by the first and second layer 10, 20 of conductive material). The plate-like base 54 of the first contacting unit 60 and the plate-like base 54 of the second contacting unit 70 are not in contact with each other as the first layer 10 of conductive material has been removed in the portion between the first and second contacting units 60, 70.

[0091]

[0088] It is explicitly stated that all features disclosed in the description and / or the claims are intended to be disclosed separately and independently from each other for the purpose of original disclosure as well as for the purpose of restricting the claimed invention independent of the composition of the features in the embodiments and / or the claims. It is explicitly stated that all value ranges or indications of groups of entities disclose every possible intermediate value or intermediate entity for the purpose of original disclosure as well as for the purpose of restricting the claimed invention, in particular as limits of value ranges. Potential UBM (under barrier metal) have been excluded.

[0092] List of references

[0093] 1 substrate

[0094] 2 electronic circuit

[0095] 3 outer protective layer

[0096] 5 connector

[0097] 6 first connector

[0098] 7 second connector

[0099] 10 first layer of conductive material

[0100] 14 first template

[0101] 15 first openings

[0102] 20 second layer of conductive material

[0103] 24 second template

[0104] 25 second openings

[0105] 30 third layer of conductive material

[0106] 50 contacting unit

[0107] 54 plate-like base

[0108] 55 pillars

[0109] 60 first contacting unit

[0110] 70 second contacting unit

[0111] 80 antenna wire

[0112] 100 integrated circuit

[0113] 200 RFID tag

[0114] 300 method of manufacturing an integrated circuit h height of pillar w width of pillar d depth of pillar

Claims

Claims1. An integrated circuit (100) comprising: an electronic circuit (2) formed in a substrate (1), a connector (5) electrically connected to the electronic circuit (2) and extending to the outside of the substrate (1), and a contacting unit (50) made of conductive material and positioned on the substrate (1), the contacting unit (50) being electrically connected to the connector (5) and comprising a plate-like base (54) and a plurality of pillars (55) positioned on the plate-like base (54).

2. The integrated circuit (100) according to claim 1, comprising a first connector (6) and a second connector (7), each of the first and second connectors (6, 7) is electrically connected to the electronic circuit (2) and extends to the outside of the substrate (1), and a first contacting unit (60) electrically connected to the first connector (6) and a second contacting unit (70) electrically connected to the second connector (7), each of the first and second contacting units (60, 70) is made of conductive material, positioned on the substrate (1) and comprising a plate-like base (54) and a plurality of pillars (55) positioned on the plate-like base (54).

3. The integrated circuit (100) according to any one of the preceding claims, wherein the substrate (1) comprises an outer protective layer (3).

4. The integrated circuit (100) according to any one of the preceding claims, wherein the plate-like base has a uniform thickness in the range of 0.25-10 pm, preferably in the range of 3-5 pm.

5. The integrated circuit (100) according to any one of the preceding claims, wherein at least one of the plurality of pillars (55) is a right cylinder with circular bases, each of the circular bases having a diameter in the range of 10-80 pm, preferably in the range of 15-30 pm.

6. The integrated circuit (100) according to any one of the preceding claims, wherein at least one of the plurality of pillars (55) is a rectangular prism (cuboid), whose rectangular bases having a width (w) in the range of 10-80 pm and a depth (d) in the range of 10-80 pm, preferably a width (w) in the range of 15-30 pm and a depth (d) in the range of 15-30 pm7. The integrated circuit (100) according to any one of the preceding claims, wherein at least one of the plurality of pillars (55) is distanced from the adjacent pillar by a distance in the range of 10-50 pm, preferably in the range of 20-30 pm.

8. The integrated circuit (100) according to any one of the preceding claims, wherein at least one of the plurality of pillars (55) has a height (h) in the range of 10-80 pm, preferably a height of 15-30 pm.

9. The integrated circuit (100) according to any one of the preceding claims, wherein at least one of the plurality of pillars (55) comprises an additional layer of solder material forming a solder cap.

10. The integrated circuit (100) according to any one of the preceding claims, wherein the plate-like base (55) comprises a first layer (10) of a first conductive material and a second layer (20) of a second conductive material, the first conductive material being different from the second conductive material.

11. The integrated circuit (100) according to claim 10, wherein the plurality of pillars (55) is formed by a third layer (30), the third layer (30) being made of a third conductive material different form the first and second conductive materials.

12. An RFID tag (200), comprising: the integrated circuit (100) according to any one of the preceding claims, and an antenna wire (80) electrically connected to a contacting unit (50) of the integrated circuit (100).

13. A method (300) of manufacturing an integrated circuit (100), the method (300) comprising the steps of: providing an electronic circuit (2) formed in a substrate (1) and a connector (5) electrically connected to the electronic circuit (2) and extending to the outside of the substrate (1), applying, for example by sputtering, a first layer (10) of conductive material onto the substrate (1) such that the first layer (10) of conductive material is electrically connected to the connector (5) and covers at least part of the surface of the substrate (1), applying a first template (14) with first openings (15) onto the first layer (10) of conductive material, for example by photolithography, applying, for example by electroplating, a second layer (20) of conductive material onto the first layer (10) such that it fills at least part of the first openings (15),applying a second template (24) with second openings (25) onto the second layer (20) of conductive material respectively onto the first template (14), for example by photolithography, such that the second openings (25) overlap with the first openings (15), applying, for example by electroplating, a third layer (30) of conductive material onto the second layer (20) such that it fills at least part of the second openings (25), removing, for example by stripping off, the first and second templates (14, 24), and removing, for example by etching, a layer of material from the top of the body formed by the first, second and third layers (10, 20, 30) of conductive material such that the first layer (10) of conductive material in some portions is completely removed from the surface of the substrate (1).

14. The method (300) according to claim 13, wherein the portions in which the first layer (10) of conductive material is completely removed from the surface of the substrate (1) correspond to the portions of the first layer (10) of conductive material which are not covered by the second layer (20) and / or the third layer (30) of conductive material.

15. The method (300) according to claim 13 or 14, wherein the layer of material removed from the body formed by the first, second and third layer (10, 20, 30) of conductive material has a uniform thickness in the range of 0.050-0.500 pm, preferably in the range of 0.075-0.350 pm.

16. The method (300) according to any one of claims 13 to 15, wherein the conductive material of the first layer (10) differs from the conductive material of the second layer (20).

17. The method (300) according to any one of claims 13 to 16, wherein the conductive material of the third layer (30) differs from the conductive material of the first and second layers (10, 20).

18. A method of manufacturing an RFID tag (200), the method comprising the method steps according to any one of claims 13-17, and further comprising the steps of: providing an antenna wire (80), and connecting the antenna wire (80) to the contacting unit (50) of the integrated circuit (100) by bonding techniques such as ultrasonic bonding, thermo- compression bonding, laser bonding, welding or conductive gluing.

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