Process and device for a chiplet system

Abstract

A process, for example a computer-implemented process, for a chiplet system having a plurality of chiplets, comprising: decoupling an address space of at least one chiplet from an address space of at least one other component, and, optionally, operating the at least one chiplet.

Description

[0001] Description

[0002] title

[0003] Procedures and for a

[0004] State of the art

[0005] The disclosure relates to a method for a chiplet system comprising multiple chiplets.

[0006] The disclosure further relates to a device for a chiplet system comprising several chiplets.

[0007] Disclosure of the invention

[0008] Some examples refer to a method, for example a computer-implemented method, for a chiplet system comprising multiple chiplets, comprising: decoupling an address space of at least one chiplet from an address space of at least one other component, and, optionally, operating the at least one chiplet. In some examples, this allows for increased flexibility, for example for operating multiple chiplets with a single memory device, which may be shared by the multiple chiplets.

[0009] In some examples, the method is provided to include at least one of the following elements: a) performing a first, for example, physical, address mapping for a first chiplet of the multiple chiplets, or b) performing a second, for example, physical, address mapping for a second chiplet of the multiple chiplets. In some examples, the method is provided to include at least one of the following elements: a) mapping a first, for example, physical, memory area of ​​one or the first chiplet of the multiple chiplets to a first address area of ​​a memory device, or b) mapping a first, for example, physical, memory area of ​​one or the second chiplet of the multiple chiplets to a second address area of ​​one or the memory device, where, for example, the second address area is different from the first address area.

[0010] In some examples, the procedure includes: mapping a second, for example physical, memory area of ​​one or the first chiplet of several chiplets to a third address area of ​​one or the memory device, mapping a second, for example physical, memory area of ​​one or the second chiplet of several chiplets to the third address area of ​​the memory device.

[0011] In some examples, the procedure is designed to include: specifying a configuration for decoupling, for example, for performing address translation, for example, during runtime, and, optionally, decoupling, for example, performing address translation, based on the configuration.

[0012] In some examples, specifying the configuration involves deploying the configuration to non-volatile memory.

[0013] Some examples refer to a device for carrying out the process according to the disclosure.

[0014] Some examples refer to a chiplet system with a device according to the disclosure.

[0015] Some examples refer to a computer-readable storage medium, comprising instructions that, when executed by a computer, cause it to perform the procedure according to the disclosure. Some examples refer to a computer program, comprising instructions that, when the program is executed by a computer, cause it to perform the procedure according to the disclosure.

[0016] Some examples refer to a data carrier signal that transmits and / or characterizes the computer program according to the disclosure.

[0017] Some examples relate to a use of the method according to the disclosure and / or the device according to the disclosure and / or the chiplet system according to the disclosure and / or the computer-readable storage medium according to the disclosure and / or the computer program according to the disclosure and / or the data carrier signal according to the disclosure for at least one of the following elements: a) decoupling an address space of at least one chiplet from an address space of at least one other component of a chiplet system, or b) physical address translation for at least one chiplet, or c) enabling multiple chiplets to share a storage device, or d) dividing an address space of at least one storage device among multiple chiplets, or e) dynamically configuring a physical address translation for at least one chiplet, or f) avoiding the provision of individual storage devices for chiplets.

[0018] Further features, applications, and advantages will become apparent from the following description of examples illustrated in the figures of the drawing. All described or illustrated features, individually or in any combination, constitute the subject matter of the disclosure, irrespective of their aggregation in the claims or their cross-reference, and irrespective of their formulation or representation in the description or in the drawing.

[0019] The drawing shows:

[0020] Fig. 1 schematically shows a block diagram according to some examples,

[0021] Fig. 2 schematically shows a flowchart according to some examples, Fig. 3 schematically shows a flowchart according to some examples,

[0022] Fig. 4 schematically shows a flowchart according to some examples,

[0023] Fig. 5 schematically shows memory areas according to some examples.

[0024] Fig. 6 schematically shows a flowchart according to some examples,

[0025] Fig. 7 schematically shows a flowchart according to some examples,

[0026] Fig. 8 schematically shows a block diagram according to some examples,

[0027] Fig. 9 schematically shows a block diagram according to some examples,

[0028] Fig. 10 schematically shows aspects of uses according to some examples.

[0029] Some examples, Fig. 1, 2, relate to a method, for example a computer-implemented method, for a chiplet system 10 comprising several chiplets 11, 12, ... (Fig. 1), comprising: decoupling 300 (Fig. 2) an address space AR-11 of at least one, for example first, chiplet 11 from an address space AR-12 of at least one other component, for example another, for example second, chiplet 12, and, optionally, operating 302 the at least one chiplet 11, for example using the decoupled address space AR-11. In some examples, this allows increased flexibility, for example for operating several chiplets 11, 12, ... with a memory device 20, which can be used, for example, by the several chiplets 11, 12, ...

[0030] In some examples, the memory device 20 is a main memory, for example RAM, such as DDR or HBM (high bandwidth memory). Thus, in some examples, one or more chiplets 11, 12, ... can share the main memory 20, so that in some examples no individual main memory needs to be provided for the respective chiplets. In some examples, Fig. 1, a further component 13 is provided, for example also in the form of a chiplet, for example in the form of a management chiplet, which has an interface 13a to the memory device 20.

[0031] In some examples, Fig. 1, the further component 13 can also be designed as a base chiplet, for example base die.

[0032] In some examples, Fig. 1, the further component 13 includes a device 200 which is designed to carry out at least some aspects of the disclosure, for example, to carry out aspects of the method according to Fig. 2.

[0033] In some examples, the additional component 13 forms part of the chiplet system 10.

[0034] In some examples, at least some of the components 11, 12, 13, 20 are arranged on a common substrate 15.

[0035] In some examples, the chiplets 11, 12, ... are connected to component 13 via their respective data interfaces 11a, 12a. In some examples, the data interfaces 11a, 12a are configured, for example, as die-to-die interfaces.

[0036] In some examples, the chiplets 11, 12, ... can be connected to the storage device 20 by means of the component 13 via their respective data interfaces 11a, 12a and interface 13a, wherein, for example, the device 200 can control a respective data connection or accesses of the chiplets 11, 12 to the storage device 20, for example at least with respect to an addressing, for example in order to realize the aforementioned decoupling 300 according to the disclosure.

[0037] In some examples, the device 200 can, for example, implement an address conversion such that memory addresses accessed by the respective chiplets 11, 12 are transformed by the device 200 into transformed memory addresses that correspond to predefinable, e.g., different memory areas of the storage device 20.

[0038] In some examples, Fig. 3, the method is provided to have at least one of the following elements: a) performing 310 a first, for example physical, address translation, for example address translation, ATL-1 for a first chiplet 11, or b) performing 312 a second, for example physical, address translation, for example address translation, ATL-2 for a second chiplet 12. In some examples, the decoupling 300 according to Fig. 2 can, for example, have at least one of the aspects 310, 312 according to Fig. 3.

[0039] In some examples, Fig. 4, 5, the method is provided to include at least one of the following elements: a) mapping 320 of a first, for example physical, memory area SB-1-11 of a first chiplet 11 to a first, for example physical, address area 20-AB-1 of a memory device, for example the memory device 20 according to Fig. 1, or b) mapping 322 of a first, for example physical, memory area SB-1-12 of a second chiplet 12 to a second, for example physical, address area 20-AB-2 of the memory device 20, wherein, for example, the second address area 20-AB-2 is different from the first address area 20-AB-1.

[0040] Fig. 5 shows, as an example, an address range or address space AR-20 of the memory device 20 (Fig. 1) as well as respective address ranges or address spaces AR-11 , AR-12 of the chiplets 11 , 12.

[0041] For example, the address space AR-20 extends from a start address OxFFOO 0000 (hexadecimal) to an end address OxFFFF FFFF.

[0042] For example, the address space AR-11 extends from a starting address 0x0000 0000 to an ending address OxFFFF FFFF.

[0043] For example, the address space AR-12 extends from a start address 0x0000 0000 to an end address OxFFFF FFFF. In some examples, Figs. 2, 4, 5, the decoupling 300 according to Fig. 2 can, for example, exhibit at least one of the aspects 320, 322 according to Fig. 4.

[0044] In some examples, Fig. 6, the method includes: mapping 330 of a second, for example physical, memory area SB-2-11 of one or the first chiplet 11 to a third, for example physical, address area 20-AB-3 of the memory device 20, mapping 332 of a second, for example physical, memory area SB-2-12 of the second chiplet 12 to the third address area 20-AB-3 of the memory device 20. This allows, in some examples, the creation of a shared address area or memory (e.g., "shared memory") in the memory device 20, which both chiplets 11 and 12 can access, with, for example, the two chiplets 11 and 12 receiving the shared address area mapped into their respective address spaces AR-11 and AR-12, e.g., at their own different address areas sm1 and sm2.

[0045] Since the other memory areas SB-1-11, SB-1-12 (Fig. 5) of the chiplets 11, 12 are transformed, for example, converted, to different address areas 20-AB-1, 20-AB-2 of the memory device 20 in some examples, these memory areas SB-1-11, SB-1-12 do not represent a shared memory area in the sense of the third memory area 20-AB-3, but are individually accessible, for example, only for the respective chiplet 11, 12.

[0046] Figure 5 shows that, using the principle according to the disclosure, several chiplets 11, 12 (e.g., more than two chiplets) can be provided, whose respective address spaces AR-11, AR-12, or parts thereof, e.g., flexibly, for example, dynamically (e.g., at runtime), can be mapped to predefined areas 20-AB-1, 20-AB-2, ... of the address space AR-20, thus allowing the several chiplets 11, 12, ... to share a physical memory device 20, e.g., without access conflicts arising. Furthermore, the principle according to the disclosure eliminates the need, in some examples, to align the memory layout of individual chiplets 11 with the memory layout of other chiplets 12. Instead, in some examples, a potentially necessary decoupling of memory areas or accesses, e.g.,on a common storage device 20, by means of the principle according to the disclosure, for example using the device 200, for example without having to modify the individual chiplets 11, 12. In some examples, the principle according to the disclosure thus enables a decoupling of the respective memory areas or their memory accesses that is transparent for the individual chiplets 11, 12.

[0047] In some examples, Fig. 7, the procedure is provided to include: specifying 340 a configuration CFG for decoupling, for example for performing address translation, for example during a runtime, and, optionally, decoupling 342, for example performing 342a address translation 300, 310, 312, ..., based on the configuration CFG.

[0048] In some examples, Fig. 7, it is provided that specifying 340 of the configuration CFG involves providing 340a of the configuration CFG in a non-volatile memory 13b (Fig. 1).

[0049] Some examples, Fig. 8, refer to a device 200 for carrying out at least some aspects of the method according to the disclosure.

[0050] In further examples, Fig. 8, it is provided that the device 200 (Fig.

[0051] 11) comprises: a computing device (“computer”) 202 comprising at least one computing core 202a, a storage device 204 associated with the computing device 202 for at least temporary storage of at least one of the following elements: a) data DAT, b) computer program PRG, for example, for executing the method according to the embodiments. In some examples, the data DAT is associated with, for example, information that can be used for decoupling 300 (Fig. 2) or at least one of the aspects 310, 312, 320, 322, 330, 332, 340, 342, CFG, e.g., information that describes a desired address translation. In other examples, the memory device 204 includes volatile memory (e.g., main memory (RAM)) 204a, and / or non-volatile (NVM) memory (e.g., flash EEPROM) 204b, or a combination thereof or with other memory types not explicitly mentioned.

[0052] Further examples relate to a computer-readable storage medium SM, comprising instructions PRG which, when executed by a computer 202, cause it to execute the method according to the embodiments.

[0053] Further examples relate to a computer program PRG, comprising instructions which, when the program PRG is executed by a computer 202, cause it to execute the method according to the embodiments.

[0054] Further examples relate to a data carrier signal DCS, which characterizes and / or transmits the computer program PRG according to the embodiments. The data carrier signal DCS is, for example, exchangeable (transmittable and / or receiveable) via an optional data interface 206 of the device 200.

[0055] In some examples, Fig. 8, at least part of the functionality of the device 200 can be implemented in the form of an application-specific integrated circuit (e.g. ASIC) and / or in the form of a programmable logic circuit (e.g. FPGA) and / or in the form of a, for example, pure hardware circuit.

[0056] Some examples, Fig. 1, refer to a chiplet system 10 with a device 200 according to the disclosure.

[0057] For example, as shown in Fig. 9, the chiplet system 10 can be designed or intended for applications in the automotive sector. For example, the chiplet system 10 can be integrated into a control unit or vehicle computer 50 for a vehicle, for example, a motor vehicle 1. In some examples, the chiplet system 10 can also be used in areas other than the automotive sector mentioned here as an example.

[0058] Some examples, Fig. 10, relate to a use 400 of the method according to the disclosure and / or the device 200 according to the disclosure and / or the chiplet system 10 according to the disclosure and / or the computer-readable storage medium SM according to the disclosure and / or the computer program PRG according to the disclosure and / or the data carrier signal DCS according to the disclosure for at least one of the following elements: a) decoupling 401 an address space of at least one chiplet 11 from an address space of at least one other component 11, 12, 20 of a chiplet system 10, or b) physical address translation 402 for at least one chiplet 11, 12, ..., or c) enabling 403 a storage device 20 to be shared by several chiplets 11, 12, ..., or d) dividing 404 an address space AR-20 (Fig. 5) of at least one storage device 20 among several chiplets 11 , 12, ..., or e) dynamic configuration 405 (Fig.10) a physical address translation for at least one chiplet 11 , 12, ..., or f) Avoiding 406 a provision of individual memory facilities for chiplets 11 , 12, .

[0059] In some examples, the principle according to the disclosure makes it possible to use, for example, semiconductors and / or IP components from a mass market / consumer sector (e.g., in the high-performance sector) for the chiplet system 10.

[0060] In some examples, the principle according to the disclosure enables synergies, for example for the use of chiplets from the consumer sector, for example through physical address translation as in some examples. This is because, in some examples, the address spaces of the (e.g., consumer) chiplets are decoupled, for example, from a central, e.g., shared, main memory 20 (Fig. 1).

[0061] In some examples, central memory areas 20-AB-1, 20-AB-2, ... (Fig. 5) (e.g., of a host physical memory) can be mapped to a memory architecture of chiplets 11, 12, ... (e.g., device physical memory), for example, flexibly mapped. This allows, for example, the resolution of dependencies between the individual address ranges of chiplets 11, 12, ... in some examples, see Fig. 5.

[0062] In some examples, the mapping of memory areas SB-1-11, SB-1-12, ... (Fig. 5) can be performed flexibly, e.g., at startup time (e.g., when the chiplet system 10 is activated). This can be done, for example, by a corresponding configuration CFG (Fig. 7), e.g., in non-volatile memory 13b (Fig. 1). In some examples, Fig. 1, the non-volatile memory 13b can be implemented, e.g., by element 204b according to Fig. 8.

Claims

Claims 1. Method, for example a computer-implemented method, for a chiplet system (10) comprising several chiplets (11 , 12, ...), comprising: decoupling (300) an address space (AR-11) of at least one chiplet (11) from an address space (AR-12) of at least one other component (12, 20), and, optionally, operating (302) the at least one chiplet (11).

2. Method according to claim 1, comprising at least one of the following elements: a) performing (310) a first, for example physical, address translation (ATL-1) for a first chiplet (11) of the several chiplets (11 , 12, ...), or b) performing (312) a second, for example physical, address translation (ATL-2) for a second chiplet (12) of the several chiplets (11 , 12, ...).

3. A method according to at least one of the preceding claims, comprising at least one of the following elements: a) mapping (320) of a first, for example physical, memory area (SB-1-11) of one or the first chiplet (10-1) of the several chiplets (10-1, 10-2, ...) to a first address area (20-AB-1) of a memory device (20), or b) mapping (322) of a first, for example physical, memory area (SB-1-12) of one or the second chiplet (10-2) of the several chiplets (10-1, 10-2, ...) to a second address area (20-AB-2) of one or the memory device (20), wherein, for example, the second address area (20-AB-2) is different from the first address area (20-AB-1).

4. Method according to at least one of the preceding claims, comprising: mapping (330) a second, for example physical, memory area (SB-2-11 ) of one or the first chiplet (10-1) of the several chiplets (10-1 , 10-2, ...) to a third address area (20-AB-3) a or the memory device (20), mapping (332) of a second, for example physical, memory area (SB-2-12) of one or the second chiplet (10-2) of the several chiplets (10-1 , 10-2, ...) to the third address area (20-AB-3) of the memory device (20).

5. Method according to at least one of the preceding claims, comprising: specifying (340) a configuration (CFG) for decoupling (300), for example for performing (310, 312) the address translation, for example during a runtime, and, optionally, decoupling (342), for example performing (342a) the address translation, based on the configuration (CFG).

6. Method according to claim 5, wherein the specification (340) of the configuration (CFG) comprises a provision (340a) of the configuration (CFG) in a non-volatile memory.

7. Device (200) for carrying out the method according to at least one of the preceding claims.

8. Chiplet system (10) with a device (200) according to claim 7.

9. Computer-readable storage medium (SM) comprising instructions (PRG) which, when executed by a computer (202), cause it to execute the method according to at least one of claims 1 to 6.

10. Computer program (PRG) comprising instructions which, when the program (PRG) is executed by a computer (202), cause it to execute the method according to at least one of claims 1 to 6.

11. Data carrier signal (DCS) that transmits and / or characterizes the computer program (PRG) according to claim 10.

12. Use (400) of the method according to at least one of claims 1 to 6 and / or the device (200) according to claim 7 and / or the chiplet system (10) according to claim 8 and / or the computer-readable storage medium (SM) according to claim 9 and / or computer program (PRG) according to claim 10 and / or data carrier signal (DCS) according to claim 11 for at least one of the following elements: a) decoupling (401) of an address space (AR-11) of at least one chiplet (11) from an address space (AR-12) of at least one other component (12, 20) of a chiplet systems (10), or b) physical address translation (402) for at least one chiplet (11, 12), or c) enabling (403) a shared use of a memory device (20) by several chiplets (11, 12), or d) dividing (404) an address space of at least one memory device (20) among several chiplets (11, 12), or e) dynamic configuration (405) of a physical address translation for at least one chiplet (11, 12), or f) avoiding (406) the provision of individual memory devices for chiplets (11, 12).

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