Sensing device, electronic apparatus, and method for controlling sensing device

Abstract

Provided is a sensing device for detecting the presence of an edge, the sensing device having improved edge detection accuracy.　The sensing device comprises a gain control circuit, an offset control circuit, and a comparator. The gain control circuit performs, as gain control, a control to increase or reduce at least one of a pair of pixel signals using a prescribed gain. The offset control circuit performs, as offset control, a control for superimposing a prescribed offset on at least one of the pair of pixel signals. The comparator compares the pair of pixel signals subjected to the gain control and the offset control, and outputs a comparison result.

Description

Sensing device, electronic device, and method for controlling sensing device

[0001] The present technology relates to a sensing device, and more particularly to a sensing device that compares signals using a comparator, an electronic device, and a method for controlling the sensing device.

[0002] Conventionally, sensing devices such as solid-state imaging devices have performed various signal processing such as pixel addition and CDS (Correlated Double Sampling) processing for the purpose of expanding the dynamic range, reducing noise, etc. For example, a device has been proposed that increases or decreases one of a pair of pixel signals by a gain and detects the presence or absence of an edge based on the comparison result (see, for example, Patent Document 1).

[0003] International Publication No. 2021 / 090538

[0004] The conventional technology described above attempts to achieve edge detection that is independent of the amount of ambient light by increasing or decreasing one of a pair of pixel signals using a gain. However, with the above device, if the difference between the pair of pixel signals is small, noise can lead to an erroneous determination of the presence or absence of an edge.

[0005] This technology was developed in light of these circumstances, and aims to improve the accuracy of edge detection in sensing devices that detect the presence or absence of edges.

[0006] The present technology has been made to solve the above-mentioned problems, and a first aspect thereof relates to a sensing device including a gain control circuit that performs gain control to increase or decrease at least one of a pair of pixel signals by a predetermined gain, an offset control circuit that performs offset control to superimpose a predetermined offset on at least one of the pair of pixel signals, and a comparator that compares the pair of pixel signals that have been subjected to the gain control and the offset control and outputs the comparison result, and a control method thereof, thereby improving edge detection accuracy.

[0007] In addition, in the first aspect, the sensor may further include a timing control circuit that sequentially selects a plurality of combinations of offset values ​​and gain values ​​and sets the combinations in the gain control circuit and the offset control circuit, thereby improving sensing performance.

[0008] In addition, in the first aspect, a plurality of latch circuits may be further provided for holding the comparison results corresponding to the plurality of combinations, thereby providing an effect of improving sensing performance.

[0009] In this first aspect, the timing control circuit may set the gain values ​​in ascending order and stop the comparator when an edge is detected, thereby reducing power consumption.

[0010] In this first aspect, the gain control circuit may include a first capacitive element, a second capacitive element, a first switch that opens and closes a path between the first capacitive element and a vertical signal line that transmits one of the pair of pixel signals, and a second switch that opens and closes a path between the second capacitive element and the vertical signal line that transmits one of the pair of pixel signals, thereby providing an effect of switching the gain value.

[0011] In the first aspect, the other ends of the first and second capacitance elements may be connected to the comparator, thereby providing an effect of switching the gain value.

[0012] In the first aspect, the other ends of the first and second capacitance elements may be connected to a ground node, thereby providing an effect of switching the gain value.

[0013] In addition, in the first aspect, the amplifier may further include an amplifier, a capacitance element having one end connected to an output terminal of the amplifier, and a switch for opening and closing a path between the input terminal of the amplifier and the other end of the capacitance element, thereby providing an effect of switching the gain value.

[0014] In addition, in this first aspect, the offset control circuit may include a capacitance element, an offset-side switch that opens and closes a path between an input node of the offset and one end of the capacitance element, and a pixel-side switch that opens and closes a path between a vertical signal line that transmits one of the pair of pixel signals and one end of the capacitance element, thereby providing an effect of switching the offset value.

[0015] In addition, in this first aspect, the offset may include first and second offsets, and the offset-side switch may include a first offset-side switch that opens and closes a path between an input node of the first offset and one end of the capacitance element, and a second offset-side switch that opens and closes a path between an input node of the second offset and one end of the capacitance element, thereby providing an effect of switching the offset value.

[0016] In addition, in the first aspect, the pixel circuit may further include a reference signal generation unit that generates a predetermined reference signal, a reference-side switch that opens and closes a path between the reference signal generation unit and the comparator, and a pixel-side switch that opens and closes a path between the gain control circuit and the offset control circuit and a vertical signal line that transmits the pixel signal, thereby providing an effect of reducing the circuit size.

[0017] In addition, in the first aspect, the image sensor may further include a pixel array unit in which a pair of pixels that generate the pair of pixel signals is arranged, and a signal processing circuit that processes the comparison result, thereby achieving the effect of extracting features and the like.

[0018] In addition, in this first aspect, the pixel array unit, the gain control circuit, the offset control circuit, and the comparator may be arranged on a predetermined pixel chip, and the signal processing circuit may be arranged on a predetermined circuit chip, thereby providing an effect of facilitating pixel miniaturization.

[0019] In addition, in this first aspect, the pixel array unit may be arranged on a predetermined pixel chip, and the gain control circuit, the offset control circuit, the comparator, and the signal processing circuit may be arranged on a predetermined circuit chip, thereby providing an effect of facilitating pixel miniaturization.

[0020] In addition, in the first aspect, an error cancellation circuit may be further provided that cancels an error in the output signal of the comparator, thereby improving the accuracy of edge detection in low illuminance situations.

[0021] In this first aspect, the error cancellation circuit may superimpose a predetermined compensation offset on the output signal, thereby eliminating mismatch components for each comparator and improving edge detection accuracy in low illuminance situations.

[0022] In addition, in this first aspect, the pixel circuit may further include a replica circuit having the same circuit configuration as the comparator, the error cancellation circuit holds an input offset of the replica circuit and superimposes the held input offset as a compensation offset on one of a pair of input signals of the comparator, the comparators are arranged for each pixel column, and the error cancellation circuit is commonly connected to each of the comparators. This improves area efficiency and improves edge detection accuracy in low illuminance situations.

[0023] According to a second aspect of the present technology, there is provided an electronic device including: a gain control circuit that performs gain control to increase or decrease at least one of a pair of pixel signals by a predetermined gain; an offset control circuit that performs offset control to superimpose a predetermined offset on at least one of the pair of pixel signals; a comparator that compares the pair of pixel signals that have been subjected to the gain control and the offset control and outputs a comparison result; and a signal processing circuit that processes the comparison result, thereby improving edge detection accuracy in the electronic device.

[0024] 1 is a block diagram showing an example configuration of an imaging device according to a first embodiment of the present technology. FIG. 2 is a block diagram showing an example configuration of an image sensor according to the first embodiment of the present technology. FIG. 3 is a circuit diagram showing an example configuration of a pixel according to the first embodiment of the present technology. FIG. 4 is an example cross-sectional view of a back-illuminated image sensor according to the first embodiment of the present technology. FIG. 5 is an example cross-sectional view of a front-illuminated image sensor according to the first embodiment of the present technology. FIG. 6 is a block diagram showing an example configuration of a column signal processing circuit according to the first embodiment of the present technology. FIG. 7 is a block diagram showing an example configuration of an edge detection unit according to the first embodiment of the present technology. FIG. 8 is a block diagram showing an example configuration of an edge detection unit that outputs 1 bit according to the first embodiment of the present technology. FIG. 9 is a circuit diagram showing an example configuration of an offset control circuit and a gain control circuit according to the first embodiment of the present technology. FIG. 10 is a circuit diagram showing an example configuration of a comparator according to the first embodiment of the present technology. FIG. 11 is a circuit diagram showing an example configuration of an edge detection unit in a third comparative example. FIG. 12 is a timing chart showing an example operation of an image sensor according to the third comparative example. FIG. 13 is a timing chart showing an example operation of an image sensor when illuminance is low according to the first embodiment of the present technology. 10 is a timing chart showing an example of operation of an image sensor when illuminance is high according to the first embodiment of the present technology. FIG. 11 is a diagram for comparing edge determination methods between a comparative example and the first embodiment of the present technology. FIG. 12 is a flowchart showing an example of operation of an image sensor according to the first embodiment of the present technology. FIG. 13 is a block diagram showing an example configuration of an edge detection unit according to a first modified example of the first embodiment of the present technology. FIG. 14 is a block diagram showing an example configuration of an edge detection unit according to a second modified example of the first embodiment of the present technology. FIG. 15 is a block diagram showing an example configuration of a column signal processing circuit according to the second embodiment of the present technology. FIG. 16 is a block diagram showing an example configuration of an edge detection unit according to a third embodiment of the present technology. FIG. 17 is a circuit diagram showing an example configuration of an offset control circuit and a gain control circuit according to the third embodiment of the present technology.10 is a timing chart showing an example of operation of an image sensor when illuminance is low in the third embodiment of the present technology. FIG. 11 is a diagram for explaining a method of setting a first gain value in the third embodiment of the present technology. FIG. 12 is a diagram for explaining a method of setting second and third gain values ​​in the third embodiment of the present technology. FIG. 13 is a diagram showing offset values ​​and gain values ​​for each combination in the third embodiment of the present technology. FIG. 14 is a flowchart showing an example of operation of an image sensor in the third embodiment of the present technology. FIG. 15 is a circuit diagram showing an example of configuration of an offset control circuit and a gain control circuit in a first modified example of the third embodiment of the present technology. FIG. 16 is a circuit diagram showing an example of configuration of an offset control circuit and a gain control circuit in a second modified example of the third embodiment of the present technology. FIG. 17 is a diagram for explaining control for holding a reset level and a signal level in the second modified example of the third embodiment of the present technology. FIG. 18 is a diagram for explaining a method of setting first to third gain values ​​in the second modified example of the third embodiment of the present technology. FIG. 19 is a circuit diagram showing an example of configuration of an offset control circuit and a gain control circuit in a third modified example of the third embodiment of the present technology. FIG. 19 is a diagram for explaining control of a timing control circuit in a fourth embodiment of the present technology. FIG. 19 is a timing chart showing an example of operation of an image sensor in the fourth embodiment of the present technology. FIG. 19 is a flowchart showing an example of operation of an image sensor in the fourth embodiment of the present technology. FIG. 10 is a diagram showing an example of a layered structure of an image sensor according to a fifth embodiment of the present technology. FIG. 11 is a diagram showing another example of a layered structure of an image sensor according to the fifth embodiment of the present technology. FIG. 12 is a graph showing an occurrence rate for each level at low illuminance in a comparative example and the first embodiment of the present technology. FIG. 13 is a diagram showing an example of an edge image at low illuminance in the first embodiment of the present technology. FIG. 14 is a graph showing an example of an edge ratio for each edge offset at low illuminance in the first embodiment of the present technology. FIG. 15 is a block diagram showing an example of a configuration of an edge detection unit according to a sixth embodiment of the present technology. FIG. 16 is a block diagram showing another example of the edge detection unit according to the sixth embodiment of the present technology. FIG. 17 is a circuit diagram showing an example of a configuration of a comparator and an error cancellation circuit according to the sixth embodiment of the present technology.13 is a circuit diagram showing another example of a comparator and an error cancellation circuit according to the sixth embodiment of the present technology. FIG. 14 is a diagram showing an example of an input signal to a comparator and an output signal of a comparator and an error cancellation circuit according to the sixth embodiment of the present technology. FIG. 15 is a diagram showing an example of an edge ratio and variance for each edge offset according to the sixth embodiment of the present technology. FIG. 16 is a diagram for explaining an error according to the sixth embodiment of the present technology. FIG. 17 is a timing chart showing an example of control of the error cancellation circuit according to the sixth embodiment of the present technology. FIG. 18 is a diagram for explaining operation of the error cancellation circuit according to the sixth embodiment of the present technology. FIG. 19 is a block diagram showing an example of a configuration of a column signal processing circuit according to a modified example of the sixth embodiment of the present technology. FIG. 19 is a circuit diagram showing an example of a configuration of a replica circuit and an error cancellation circuit according to a modified example of the sixth embodiment of the present technology. FIG. 19 is a block diagram showing an example of a schematic configuration of a vehicle control system. FIG. 19 is an explanatory diagram showing an example of installation positions of an outside-vehicle information detection unit and an imaging unit.

[0025] Hereinafter, modes for implementing the present technology (hereinafter referred to as embodiments) will be described. The description will be made in the following order. 1. First embodiment (an example in which a pixel signal is increased or decreased and an offset is superimposed) 2. Second embodiment (an example in which a circuit that increases or decreases a pixel signal and superimposes an offset and an analog-to-digital converter share a comparator) 3. Third embodiment (an example in which a gain value and an offset value are variable, and a pixel signal is increased or decreased and an offset is superimposed) 4. Fourth embodiment (an example in which a pixel signal is increased or decreased and an offset is superimposed, and the comparator is stopped when an edge is detected) 5. Fifth embodiment (an example in which a pixel signal is increased or decreased and an offset is superimposed in a stacked structure) 6. Sixth embodiment (an example in which a pixel signal is increased or decreased and an offset is superimposed, and an output error of the comparator is canceled) 7. Application example to a moving body

[0026] 1. First Embodiment [Configuration Example of Imaging Device] Fig. 1 is a block diagram showing a configuration example of an imaging device 100 according to a first embodiment of the present technology. The imaging device 100 is a device for capturing image data and includes an optical unit 110, an image sensor 200, and a DSP (Digital Signal Processing) circuit 120. The imaging device 100 further includes a display unit 130, an operation unit 140, a bus 150, a frame memory 160, a storage unit 170, and a power supply unit 180. Examples of the imaging device 100 include digital cameras such as digital still cameras, as well as smartphones, personal computers, and in-vehicle cameras with imaging functions. The imaging device 100 is an example of an electronic device as defined in the claims.

[0027] The optical unit 110 collects light from a subject and guides it to the image sensor 200. The image sensor 200 generates image data by photoelectric conversion in synchronization with a vertical synchronization signal. Here, the vertical synchronization signal is a periodic signal with a predetermined frequency that indicates the timing of imaging. The image sensor 200 supplies the generated image data to the DSP circuit 120 via a signal line 209. Note that the image sensor 200 is an example of a sensing device as defined in the claims.

[0028] The DSP circuit 120 performs predetermined signal processing on the image data from the image sensor 200. The DSP circuit 120 outputs the processed image data to a frame memory 160 or the like via a bus 150.

[0029] The display unit 130 displays image data. For example, a liquid crystal panel or an organic EL (Electro Luminescence) panel is assumed as the display unit 130. The operation unit 140 generates an operation signal in accordance with a user's operation.

[0030] The bus 150 is a common path for the optical unit 110, image sensor 200, DSP circuit 120, display unit 130, operation unit 140, frame memory 160, storage unit 170, and power supply unit 180 to exchange data with one another.

[0031] The frame memory 160 holds image data. The storage unit 170 stores various data such as image data. The power supply unit 180 supplies power to the image sensor 200, the DSP circuit 120, the display unit 130, and the like.

[0032] 2 is a block diagram showing a configuration example of an image sensor 200 according to the first embodiment of the present technology. The image sensor 200 includes a vertical scanning circuit 210, a digital-to-analog converter (DAC) 220, a timing control circuit 230, and a pixel array unit 240. The image sensor 200 further includes a column signal processing circuit 300, a horizontal scanning circuit 260, and a signal processing circuit 290. These circuits are arranged on a single semiconductor chip, for example.

[0033] In the pixel array section 240, a plurality of pixels 250 are arranged in a two-dimensional lattice pattern.

[0034] The timing control circuit 230 controls the operation timing of the vertical scanning circuit 210, the column signal processing circuit 300, etc. in synchronization with the vertical synchronization signal.

[0035] The timing control circuit 230 also receives a mode signal MODE that indicates the operation mode of the image sensor 200. The operation modes include an edge detection mode that detects the presence or absence of edges, and an imaging mode that only captures image data without detecting the presence or absence of edges. The timing control circuit 230 controls each circuit based on the operation mode. Note that the image sensor 200 can also capture image data while detecting the presence or absence of edges.

[0036] The vertical scanning circuit 210 sequentially selects and drives rows to output analog pixel signals. The DAC 220 generates a reference signal by DA (Digital to Analog) conversion and supplies it to the column signal processing circuit 300. For example, a sawtooth ramp signal is used as the reference signal. The pixels 250 generate pixel signals by photoelectric conversion under the control of the vertical scanning circuit 210. Each pixel 250 outputs a pixel signal to the column signal processing circuit 300.

[0037] The column signal processing circuit 300 performs signal processing such as CDS (Correlated Double Sampling) processing and AD (Analog to Digital) conversion processing on pixel signals for each column. The column signal processing circuit 300 supplies image data consisting of digital signals after signal processing to the signal processing circuit 290 under the control of the horizontal scanning circuit 260.

[0038] The horizontal scanning circuit 260 selects columns in order and causes the column signal processing circuit 300 to output digital signals in order.

[0039] The signal processing circuit 290 performs various signal processes on image data as necessary. In the imaging mode, the signal processing circuit 290 performs image processing such as defect correction, and supplies the processed image data to the DSP circuit 120. In the edge detection mode, the signal processing circuit 290 acquires edge determination results for each pixel and performs processing such as feature extraction. Furthermore, the signal processing circuit 290 can also perform object detection and recognition, such as person detection, face detection, and face recognition, based on the extracted features. The signal processing circuit 290 then supplies the processed data to the DSP circuit 120.

[0040] 3 is a circuit diagram showing an example of the configuration of a pixel 250 according to the first embodiment of the present technology. The pixel 250 includes a photoelectric conversion element 251, a transfer transistor 252, a reset transistor 253, a floating diffusion layer 254, an amplification transistor 255, and a selection transistor 256.

[0041] The photoelectric conversion element 251 converts incident light into an electric charge and generates the electric charge. The transfer transistor 252 transfers the electric charge from the photoelectric conversion element 251 to the floating diffusion layer 254 in accordance with a transfer signal TRG from the vertical scanning circuit 210.

[0042] The reset transistor 253 extracts charge from the floating diffusion layer 254 to initialize it in accordance with a reset signal RST from the vertical scanning circuit 210 .

[0043] The floating diffusion layer 254 accumulates electric charges and generates a voltage corresponding to the amount of electric charges. The amplifying transistor 255 forms a source follower circuit and outputs a voltage corresponding to the voltage of the floating diffusion layer 254.

[0044] The selection transistor 256 outputs the voltage signal from the amplification transistor 255 as a pixel signal SIG in accordance with a selection signal SEL from the vertical scanning circuit 210. The pixel signal SIG is supplied to the column signal processing circuit 300 via a corresponding vertical signal line VSL.

[0045] The circuit of pixel 250 is not limited to the four-transistor circuit shown in the figure, as long as it can generate a pixel signal through photoelectric conversion. For example, a five-transistor circuit can be configured by adding an overflow gate transistor that extracts charge from the photoelectric conversion element. Alternatively, a six-transistor circuit can be configured by adding an additional transistor that functions as an embedded analog memory. Alternatively, the eight-transistor pixel described in "Laurence Stark, et al., Back-illuminated voltage-domain global shutter CMOS image sensor with 3.75 μm pixels and dual in-pixel storage nodes, VLSI Symposium 2016" can be used. Alternatively, the pixel described in "Kazuko Nishimura, et al., An 8K / 4K-Resolution 60 fps 450 ke--Saturation-Signal Organic-Photoconductive-Film Global-Shutter CMOS Image Sensor with In-Pixel Noise Canceller, ISSCC 2018" can be used.

[0046] 4 is an example of a cross-sectional view of the image sensor 200 according to the first embodiment of the present technology. The image sensor 200 includes a substrate 530 and a wiring layer 520. An on-chip lens 511, a color filter 512, and a photoelectric conversion element 251 are arranged for each pixel. With the light incident side facing up, the color filter 512 is arranged below the on-chip lens 511, and the photoelectric conversion element 251 is arranged below the color filter 512.

[0047] Furthermore, a wiring layer 520 is formed on the upper surface of the substrate 530, and transistors such as the transfer transistor 252 described above are formed in the wiring layer 520. A photoelectric conversion element 251 of each pixel is disposed on top of the wiring layer 520. The structure illustrated in the figure is called a back-illuminated type.

[0048] 5, a front-side illumination type may be used instead of the back-side illumination type. In this front-side illumination type, a wiring layer 520 is formed below the color filter 512, and a photoelectric conversion element 251 is disposed below that.

[0049] [Configuration Example of Column Signal Processing Circuit] Fig. 6 is a block diagram showing a configuration example of a column signal processing circuit 300 according to the first embodiment of the present technology. The column signal processing circuit 300 includes a plurality of constant current sources 310, a plurality of ADCs 320, and a plurality of edge detection units 400. The constant current sources 310 and the ADCs 320 are arranged for each column. When the number of columns is N (N is an integer), N constant current sources 310 and N ADCs 320 are arranged. Furthermore, an edge detection unit 400 is arranged for each pixel pair in a row for which an edge is to be detected. For example, when detecting an edge between the 0th column and the 1st column and between the 1st column and the 2nd column, two edge detection units 400 are arranged for the 0th column to the 3rd column.

[0050] The constant current source 310 supplies a constant current to the corresponding vertical signal line.

[0051] The ADC 320 converts analog pixel signals of the corresponding columns into digital signals under the control of the timing control circuit 230. The ADC 320 supplies the digital signals to the signal processing circuit 290 under the control of the horizontal scanning circuit 260. For example, a single-slope ADC including a comparator and a counter is used as the ADC 320. Note that a successive approximation ADC including a comparator, a successive approximation logic circuit, and a register can also be used.

[0052] The edge detection unit 400 compares a pair of pixel signals and generates a signal indicating the presence or absence of an edge. The vertical signal lines of the corresponding columns are connected to this edge detection unit 400. For example, the vertical signal line VSL0 of the 0th column and the vertical signal line VSL1 of the 1st column are connected to the edge detection units 400 corresponding to the 0th and 1st columns. The edge detection unit 400 supplies the generated signal to the signal processing circuit 290 under the control of the timing control circuit 230.

[0053] In the edge detection mode, the timing control circuit 230 enables the edge detection unit 400 to compare a pair of pixel signals, and disables the ADC 320. On the other hand, in the imaging mode, the timing control circuit 230 enables the ADC 320 to perform AD conversion, and disables the edge detection unit 400.

[0054] 7 is a block diagram showing an example of the configuration of the edge detection unit 400 according to the first embodiment of the present technology. The edge detection unit 400 includes gain control circuits 410 and 420, offset control circuits 430 and 440, and comparators 450 and 465.

[0055] The gain control circuits 410 and 420 perform gain control to increase or decrease at least one of a pair of pixel signals by a predetermined gain. The gain control circuit 410 increases or decreases the pixel signal SIG1 transmitted via the vertical signal line VSL1 by using a gain. The gain control circuit 420 increases or decreases the pixel signal SIG0 transmitted via the vertical signal line VSL0 by using a gain. The gain value is set to a fixed value "g."

[0056] Although the offset control circuits 430 and 440 increase or decrease one of the pixel signals SIG0 and SIG1 (SIG0 or SIG1) using the gain, they can also increase or decrease both of them, as will be described later with reference to FIG.

[0057] 7, offset control circuits 430 and 440 perform offset control by superimposing a predetermined offset (such as an offset voltage) on at least one of a pair of pixel signals. The offset control circuit 430 superimposes an offset on the pixel signal SIG0, and the offset control circuit 440 superimposes an offset on the pixel signal SIG1. The offset value is set to a fixed value of "-c."

[0058] Although the offset control circuits 430 and 440 superimpose an offset on one of the pixel signals SIG0 and SIG1 (SIG0 or SIG1), they can also superimpose an offset on both of them.

[0059] The comparators 450 and 465 compare a pair of pixel signals that have been subjected to gain control and offset control.

[0060] A signal that has been subjected to offset control and gain control for the pixel signal SIG1 is input to a non-inverting input terminal (+) of the comparator 450. Furthermore, the pixel signal SIG0 is input to an inverting input terminal (-) of the comparator 450. The comparator 450 compares these signals and outputs the comparison result to the signal processing circuit 290 as VCO0.

[0061] A signal that has been subjected to offset control and gain control for the pixel signal SIG0 is input to the non-inverting input terminal (+) of the comparator 465. The pixel signal SIG1 is input to the inverting input terminal (-) of the comparator 465. The comparator 465 compares these signals and outputs the comparison result to the signal processing circuit 290 as VCO1.

[0062] The two-bit signal consisting of these comparison results VCO0 and VCO1 indicates whether or not an edge exists. For example, if the values ​​of these two bits are different, it is determined that an edge exists, and if the values ​​of these bits are different, it is determined that an edge does not exist.

[0063] For example, when the following equation is true, a low-level comparison result VCO0 is output: SIG0<SIG1*g-c (Equation 1) In the above equation, "*" indicates multiplication. The same applies to the following equations.

[0064] On the other hand, it is assumed that a high level comparison result VCO0 is output when the following equation is satisfied: SIG0>SIG1*g-c (Equation 2)

[0065] Also, it is assumed that a high level comparison result VCO1 is output when the following equation is satisfied: SIG1>SIG0*g-c (Equation 3)

[0066] On the other hand, it is assumed that a low level comparison result VCO1 is output when the following equation is satisfied: SIG1≦SIG0*g−c (Equation 4)

[0067] When both Equation 1 and Equation 3 are true, the following equation is true: SIG0<<SIG1 Equation 5 In the above equation, "<<" indicates the magnitude relationship to the extent to which an edge is determined to exist.

[0068] On the other hand, when both Equation 2 and Equation 4 are true, the following equation is true: SIG0>>SIG1 Equation 6 In the above equation, ">>" indicates the magnitude relationship to the extent to which an edge is determined to exist.

[0069] If the comparison results VCO1 and VCO2 have different values, either Equation 5 or Equation 6 holds. These Equations 5 and 6 indicate that the ratio of one of the pixel signals SIG0 and SIG1 to the other is equal to or greater than a certain value. In this case, it is determined that an edge exists.

[0070] On the other hand, if the comparison results VCO1 and VCO2 have the same value, neither Equation 5 nor Equation 6 holds. In this case, it is determined that there is no edge. Note that when g is less than "1," the calculations show that both the comparison results VCO1 and VCO2 are never "0." Also, when g is "1" or greater, the calculations show that both the comparison results VCO1 and VCO2 are never "1." However, because these cases can occur due to the influence of noise, edge determination results are set even for cases where the calculations do not hold.

[0071] Next, the advantages of control in which one of the pair of pixel signals SIG0 and SIG1 is increased or decreased by the gain g and compared will be described.

[0072] The pixel that generates pixel signal SIG0 receives light that is ambient light reflected from the surface of object A with reflectance Ra, and the pixel that generates pixel signal SIG1 receives light that is ambient light reflected from the surface of object B with reflectance Rb. The amount of ambient light is AL, and the gain g is less than 1.

[0073] Here, a first comparative example is considered in which the difference between pixel signals SIG0 and SIG1 is compared with a threshold value Th to detect the presence or absence of an edge. In this first comparative example, it is determined that an edge exists when the following formula is satisfied: SIG0-SIG1=Ra*AL-Rb*AL>Th (Formula 7)

[0074] Equation 7 can be transformed into the following equation: (Ra-Rb)>Th / AL Equation 8

[0075] As exemplified by Equation 7 and Equation 8, in the comparative example, the edge determination result may change depending on the amount of ambient light AL. This reduces the accuracy of edge detection. For example, the smaller the amount of ambient light AL, the smaller the difference, making edge detection more difficult. Changing the threshold value depending on the amount of ambient light can suppress the reduction in detection accuracy, but it is difficult to accurately measure the amount of light and fine-tune the threshold value accordingly.

[0076] Also, consider a second comparative example in which the difference between the logarithmic values ​​of the pixel signals SIG0 and SIG1 is compared with a threshold value Th to detect the presence or absence of an edge. In this second comparative example, it is determined that an edge exists when the following equation is satisfied: log(SIG0) - log(SIG1) = log(Ra * AL / Rb * AL) = log(Ra / Rb) > Th (Equation 9)

[0077] As shown in Equation 9, the second comparative example can suppress the influence of ambient light, but requires logarithmic calculations and is difficult to implement.

[0078] In contrast to these comparative examples, by introducing a method of determining a threshold value based on a signal rather than based on ambient light, the influence of ambient light can be easily suppressed.

[0079] Assume that the magnitude relationship between the pixel signals after attenuation remains unchanged whether only pixel signal SIG1 is attenuated by gain g or only pixel signal SIG0 is attenuated by gain g. In this case, the comparison results VCO1 and VCO2 will have different values ​​due to the connection relationship of the input terminals of comparators 450 and 465. In this case, the following equation holds: |Ra*AL-Rb*AL|>g*max(Ra, Rb)*AL ...Equation 10 In the above equation, max() is a function that returns the maximum value of the multiple input values ​​in (). Note that if gain g is greater than 1, the function min(), which returns the minimum value, is used instead of max().

[0080] When Ra is greater than Rb, Equation 10 can be transformed into the following equation: (Ra-Rb)*AL>g*Ra*AL Equation 11

[0081] Equation 11 can be transformed into the following equation: (1-g)*Ra*AL-Rb*AL>0 Equation 12

[0082] Furthermore, if 1-g is G, then Equation 12 can be transformed into the following equation: G*(Ra*AL)-(Rb*AL)>0 Equation 13

[0083] Dividing both sides of Equation 13 by the amount of light AL gives the following equation: G*Ra-Rb>0 Equation 14

[0084] That is, when the comparison results VCO1 and VCO2 are different values, Equation 14 holds. Equation 14 indicates that the ratio between pixel signals SIG0 and SIG1 is equal to or greater than a certain value (G in the above equation). In other words, the comparison results VCO0 and VCO1 are values ​​indicating that the ratio between pixel signals SIG0 and SIG1 is equal to or greater than a certain value. Because Equation 14 does not include a term that includes the light amount AL, the image sensor 200 can determine the presence or absence of an edge without relying on the light amount AL. This allows for improved edge detection accuracy compared to the first comparative example.

[0085] Although the edge detection unit 400 outputs two bits for each pixel pair, it can also output one bit.

[0086] 8 is a block diagram showing an example configuration of the edge detection unit 400 that outputs one bit according to the first embodiment of the present technology. In the same figure, for example, an edge determination circuit 470 is further provided. The edge determination circuit 470 generates and outputs a one-bit detection result EG indicating the presence or absence of an edge based on the comparison results VCO1 and VCO2. For example, an XOR (exclusive OR) gate is used as the edge determination circuit 470.

[0087] 9 is a circuit diagram showing an example of the configuration of the offset control circuit 430 and the gain control circuit 410 according to the first embodiment of the present technology. The offset control circuit 430 includes, for example, switches 431, 432, and 433 and a capacitance element 435. The gain control circuit 410 includes, for example, switches 411, 412, 413, and 414 and capacitance elements 417 and 418.

[0088] In the offset control circuit 430, the switch 431 opens and closes a path between the vertical signal line VSL1 and one end of a capacitance element 435 in accordance with a control signal SW3 a from the timing control circuit 230. The other end of the capacitance element 435 is connected to the non-inverting input terminal (+) of the comparator 450.

[0089] The switch 432 opens and closes a path between the ground node of the ground voltage GND and one end of the capacitance element 435 in accordance with a control signal SW3b from the timing control circuit 230. The switch 433 opens and closes a path between the ground node of the ground voltage GND and one end of the capacitance element 435 in accordance with a control signal SW3c from the timing control circuit 230. ｏｆｓ is input as an offset and opens and closes a path between the input node and one end of the capacitance element 435.

[0090] The switch 431 is an example of a pixel-side switch as defined in the claims, and the switch 433 is an example of an offset-side switch as defined in the claims.

[0091] In the edge detection mode, the timing control circuit 230 controls, for example, the DAC 220 to generate a constant offset voltage Vｏｆｓ Instead of the DAC 220, an offset voltage V ｏｆｓ It is also possible to provide a separate circuit for generating

[0092] It is possible to eliminate the switch 432 in the offset control circuit 430. In this case, the DAC 220 may generate the ground voltage GND when one end of the capacitance element 435 is grounded.

[0093] In the gain control circuit 410, the switch 411 opens and closes a path between the vertical signal line VSL1 and one end of the capacitance element 417 in accordance with a control signal SW0a from the timing control circuit 230. The switch 412 opens and closes a path between the ground node and one end of the capacitance element 417 in accordance with a control signal SW0b from the timing control circuit 230. The other end of the capacitance element 417 is connected to the non-inverting input terminal (+) of the comparator 450.

[0094] The switch 413 opens and closes a path between the vertical signal line VSL1 and one end of the capacitance element 418 in accordance with a control signal SW1 a from the timing control circuit 230. The switch 414 opens and closes a path between the ground node and one end of the capacitance element 418 in accordance with a control signal SW1 b from the timing control circuit 230. The other end of the capacitance element 418 is connected to the non-inverting input terminal (+) of the comparator 450. The switches 411 and 413 are examples of the first and second switches set forth in the claims, and the capacitance elements 417 and 418 are examples of the first and second capacitance elements set forth in the claims.

[0095] The non-inverting input terminal (+) of the comparator 450 receives the pixel signal Diff ｐо The pixel signal SIG0 from the vertical signal line VSL0 is input to the inverting input terminal (−) of the comparator 450 via the capacitance element 405. ｎо is entered as

[0096] Each switch shown in the figure is closed when the corresponding control signal is at a high level, and is open when the control signal is at a low level. The control method for each switch will be described later with reference to Figures 13 and 14.

[0097] 10 is a circuit diagram showing an example configuration of the offset control circuit 440 and the gain control circuit 420 according to the first embodiment of the present technology. The offset control circuit 440 includes, for example, switches 441, 442, and 443 and a capacitance element 445. The gain control circuit 420 includes, for example, switches 421, 422, 423, and 424 and capacitance elements 427 and 428.

[0098] The circuit configurations of the offset control circuit 440 and the gain control circuit 420 are similar to those of the offset control circuit 430 and the gain control circuit 410 illustrated in FIG. 9, except that they are connected to the vertical signal line VSL0 and the comparator 465.

[0099] The non-inverting input terminal (+) of the comparator 465 receives the pixel signal Diff ｐｅ The pixel signal SIG1 from the vertical signal line VSL1 is input to the inverting input terminal (−) of the comparator 465 via the capacitance element 406. ｎｅ is entered as

[0100] 11 is a circuit diagram showing an example of the configuration of a comparator 450 according to the fourth embodiment of the present technology. The comparator 450 includes pMOS transistors 451 to 455, nMOS transistors 456 to 460, and capacitance elements 461 to 463.

[0101] The pMOS transistors 451, 452, and 455 are connected in parallel to the power supply. The gate of the pMOS transistor 451 is connected to its own drain and to the gate of the pMOS transistor 452.

[0102] The drain of the nMOS transistor 456 is connected to the pMOS transistor 451, and the source is connected to the common node. The gate of the nMOS transistor 456 is connected to the offset control circuit 430 via a capacitance element 461. The drain of the nMOS transistor 457 is connected to the pMOS transistor 452, and the source is connected to the common node. The gate of the nMOS transistor 457 is connected to the capacitance element 405 via a capacitance element 462.

[0103] The nMOS transistor 458 is inserted between the common node and the ground terminal, and a predetermined bias voltage Vbias3 is input to the gate.

[0104] The pMOS transistor 453 shorts the drain and source of the nMOS transistor 456 when the inverted signal XAZPL is at a high level. The pMOS transistor 454 shorts the drain and source of the nMOS transistor 457 when the inverted signal XAZPR is at a high level. The inverted signal XAZPL is an inverted version of the auto-zero signal AZPL from the timing control circuit 230, and the inverted signal XAZPR is an inverted version of the auto-zero signal AZPR from the timing control circuit 230.

[0105] The connection point between the pMOS transistor 452 and the nMOS transistor 457 is connected to the gate of the pMOS transistor 455 .

[0106] The nMOS transistor 460 is inserted between the pMOS transistor 455 and the ground terminal. The comparison result VCO0 is output from the connection point of the pMOS transistor 455 and the nMOS transistor 460. The nMOS transistor 459 and the capacitance element 463 are connected in series between the connection point of the pMOS transistor 455 and the nMOS transistor 460 and the ground terminal. The auto-zero signal AZ is input to the gate of the nMOS transistor 459, and the connection point of the nMOS transistor 459 and the capacitance element 463 is connected to the gate of the nMOS transistor 460.

[0107] Using the circuit illustrated in the figure, the comparator 450 compares the pixel signal SIG1*g-c with the pixel signal SIG0. The timing control circuit 230 also shifts the input timing of the auto-zero signal AZPL, which initializes one of the positive and negative sides, and the auto-zero signal AZPR, which initializes the other side. By setting the input timing of the auto-zero signal AZPL to be different from that of the auto-zero signal AZPR in this way, the offset of the comparator 450 can be adjusted.

[0108] The configuration of the comparator 465 is similar to that of the comparator 450 .

[0109] Here, a configuration in which the gain is increased or decreased but no offset is superimposed will be considered as a third comparative example.

[0110] 12 is a circuit diagram showing an example of the configuration of the edge detection unit 400 in the third comparative example. The edge detection unit 400 in the third comparative example differs from that in the first embodiment in that the offset control circuits 430 and 440 are not provided.

[0111] 13 is a timing chart showing an example of the operation of the image sensor 200 of the third comparative example. When the edge detection mode is set, the vertical scanning circuit 210 starts exposure for each row in sequence using the rolling shutter method. The vertical scanning circuit 210 then selects rows to be read out in sequence, and the column signal processing circuit 300 reads pixel signals in the selected rows. This diagram shows the operation when reading out pixel signals from a certain row.

[0112] The vertical scanning circuit 210 transmits a high-level selection signal SEL to a selected row within one AD (Analog to Digital) period from timing T0 to T3. The vertical scanning circuit 210 also transmits a high-level reset signal RST over a pulse period from timing T0. This initializes the pixels 250, and the levels of each vertical signal line, such as vertical signal lines VSL0 and VSL1, become reset levels. This reset level is also called the P phase.

[0113] The timing control circuit 230 also transmits a high-level auto-zero signal AZ over the pulse period from timing T0, thereby executing auto-zero for the comparators 450 and 465. The timing control circuit 230 also sets the control signals SW0a and SW1b to a high level and the control signals SW0b and SW1a to a low level.

[0114] Then, the vertical scanning circuit 210 transmits a high-level transfer signal TRG to the selected row over the pulse period from timing T1. This transfers signal charges within the pixel 250, and the level of the vertical signal line becomes a signal level corresponding to the amount of exposure. This signal level is also called the D phase. The difference between the reset level and the signal level corresponds to the net pixel signal (SIG0 or SIG1). In the figure, the illuminance is low, and the level of the D phase is close to the P phase.

[0115] Then, the signal level stabilizes at the timing T ｄ０ Thereafter, the comparators 450 and 465 output valid comparison results VCO0 and VCO1. ｄ０ The values ​​of the comparison results VCO0 and VCO1 from the previous period are not used for edge detection, and their respective values ​​are irrelevant.

[0116] In the figure, it is assumed that there is no difference between the original pixel signals SIG0 and SIG1 and no edge exists.

[0117] When the illuminance is low, the pixel signal Diff input to the comparator 450 ｎо and Diff ｐо and the pixel signal Diff input to the comparator 465 ｎｅ and Diff ｐｅ Therefore, if noise occurs on the vertical signal lines VSL0 and VSL1, the edge may be erroneously detected due to the noise. For example, in the same figure, at timing T ｄ０ Thereafter, the comparison result VCO0 goes low and the comparison result VCO1 goes high. As a result, an edge is erroneously detected even though there is no edge. The arrows in the figure indicate the timing at which noise occurs.

[0118] [Example of Operation of Image Sensor] FIG. 14 is a timing chart showing an example of operation of the image sensor when the illuminance is low according to the first embodiment of the present technology.

[0119] The control of the vertical scanning circuit 210 and the control of the timing control circuit 230 regarding the control signals SW0a, SW0b, SW1a, and SW1b are the same as in the comparative example.

[0120] The timing control circuit 230 also sets the control signal SW3a to low level. At timing T2 immediately after the transfer, the timing control circuit 230 changes the control signal SW3b from high level to low level, and changes the control signal SW3c from low level to high level.

[0121] As a result, among the input signals to the comparator 450, the pixel signal Diff on the vertical signal VSL1 side ｐо Of the input signals to the comparator 465, the pixel signal Diff on the vertical signal line VSL0 side is ｐｅ The dashed line in the figure indicates the pixel signal Diff on the vertical signal VSL1 side. ｐо and Diff ｎｅ The waveform of

[0122] When an offset larger than the noise distribution is superimposed, the pixel signal level is very small under low illuminance conditions, so both Equation 2 and Equation 3 hold. ｄ０ After that, both the comparison results VCO0 and VCO1 go high, and it is determined that no edge is present. In this way, by superimposing an offset, it is possible to suppress erroneous edge detection at low illuminance.

[0123] 15 is a timing chart showing an example of the operation of the image sensor when the illuminance is high according to the first embodiment of the present technology. The control of the vertical scanning circuit 210 and the timing control circuit 230 is the same as that when the illuminance is low.

[0124] When the illuminance is high, immediately after timing T1 during transfer, the potential of the vertical signal line drops in accordance with the amount of exposure, and its level (i.e., D phase) becomes a value different from that of P phase. In the figure, the dashed dotted line indicates the waveform of the vertical signal line VSL1.

[0125] In addition, among the input signals to the comparator 450, the pixel signal Diff on the vertical signal VSL1 side ｐо In addition, among the input signals to the comparator 465, the pixel signal Diff on the vertical signal VSL0 side is ｐｅ The dashed line in the figure indicates the pixel signal Diff on the vertical signal VSL1 side. ｐо and Diff ｎｅ The waveform of

[0126] Under high illumination conditions, the difference between the pair of pixel signals being compared becomes large. Therefore, the comparison results VCO0 and VCO1 each have a value that corresponds to the magnitude relationship between the pixel signals SIG0 and SIG1. For example, when the magnitude relationship of Equation 5 holds, both Equation 1 and Equation 2 hold, and a low-level comparison result VCO0 and a high-level comparison result VCO1 are output. In this case, it is determined that an edge exists. In this way, the image sensor 200 can detect edges with high accuracy even under high illumination conditions.

[0127] 16 is a diagram for comparing the edge determination methods of the comparative example and the first embodiment of the present technology, in which the vertical axes a and b indicate the level of the pixel signal SIG1 and the horizontal axis indicates the level of the pixel signal SIG0.

[0128] The gray area in Fig. 1 indicates an area where an edge is determined to exist in a comparative example where no offset is superimposed, and the white area in Fig. 1 indicates an area where an edge is determined to exist in the comparative example. The gradient of the boundary of each area is a value according to the gain.

[0129] The gray area b in the figure indicates an area that is determined to have an edge in the first embodiment in which an offset is superimposed, and the white area b in the figure indicates an area that is determined to have no edge in the first embodiment.

[0130] As shown in the example of "a" in the figure, in the comparative example, when the illuminance is low and the difference between the pixel signals SIG0 and SIG1 is small, the white area becomes very narrow. Therefore, even if there is actually no edge and the signal is within a white area, there is a risk that it will be erroneously detected as being within a gray area (i.e., there is an edge) due to noise.

[0131] In contrast, in the first embodiment, as shown in Fig. 1B, an offset is superimposed, so that the white area is wide even when the illuminance is low, thereby making it possible to suppress false detection due to noise.

[0132] 17 is a flowchart showing an example of the operation of the image sensor 200 according to the first embodiment of the present technology. The operation of the image sensor 200 is started, for example, when the image sensor 200 is powered on.

[0133] The image sensor 200 determines whether the operation mode is set to the edge detection mode (step S901). If the operation mode is set to the edge detection mode (step S901: Yes), the vertical scanning circuit 210 in the image sensor 200 selects and drives one of the rows (step S902), and each pixel pair in the row generates a pair of pixel signals (e.g., SIG0 and SIG1) (step S903).

[0134] The comparator 450 then compares the pixel signal SIG0 with the offset- and gain-controlled SIG1*g−c, and the comparator 465 compares the offset- and gain-controlled SIG0*g−c with the pixel signal SIG1 (step S904).

[0135] Then, the image sensor 200 determines whether or not an edge exists for each pixel pair in the row based on the comparison results (step S905).

[0136] The vertical scanning circuit 210 determines whether all rows have been selected (step S906). If all rows have not been selected (step S906: No), the image sensor 200 changes the selected row and repeats step S902 and subsequent steps. On the other hand, if all rows have been selected (step S906: Yes), the image sensor 200 repeats step S901 and subsequent steps.

[0137] If the edge detection mode is not set (step S901: No), the image sensor 200 captures image data (step S907) and repeatedly executes step S901 and subsequent steps.

[0138] As described above, according to the first embodiment of the present technology, the offset control circuits 430 and 440 superimpose an offset on at least one of a pair of pixel signals, thereby making it possible to suppress erroneous offset detection when illuminance is low, thereby improving edge detection accuracy.

[0139] [First Modification] In the first embodiment described above, the offset control circuit 430 and the gain control circuit 410 perform offset control or gain control on the pixel signal SIG0, but this configuration is not limiting. The image sensor 200 in this first modification of the first embodiment differs from the first embodiment in that it performs gain control on the pixel signal SIG0 and offset control on the pixel signal SIG1.

[0140] 18 is a block diagram showing an example configuration of an edge detection unit 400 in a first modified example of the first embodiment of the present technology. The edge detection unit 400 in this first modified example of the first embodiment differs from the first embodiment in that an offset control circuit 430 superimposes an offset on the pixel signal SIG0, and an offset control circuit 440 superimposes an offset on the pixel signal SIG1. In this case, on the comparator 450 side, the pixel signal SIG1 is increased or decreased by a gain, and an offset is superimposed on the pixel signal SIG0. On the comparator 465 side, the pixel signal SIG0 is increased or decreased by a gain, and an offset is superimposed on the pixel signal SIG1.

[0141] As described above, according to the first modification of the first embodiment of the present technology, the gain control circuit performs gain control on one of a pair of pixel signals (e.g., SIG0), and the offset control circuit performs offset control on the other (e.g., SIG1). Therefore, the comparators 450 and 465 compare these signals to detect the gain.

[0142] [Second Modification] In the first embodiment described above, the offset control circuit and the gain control circuit perform offset control and gain control on one of a pair of pixel signals, but this configuration is not limiting. Image sensor 200 in this second modification of the first embodiment differs from the first embodiment in that the offset control circuit and the gain control circuit perform offset control and gain control on both of a pair of pixel signals.

[0143] 19 is a block diagram showing an example configuration of an edge detection unit 400 according to a second modification of the first embodiment of the present technology. In this second modification of the first embodiment, gain control circuits 410 and 420 increase or decrease both pixel signals SIG0 and SIG1 using gains. Furthermore, offset control circuits 430 and 440 superimpose offsets on both pixel signals SIG0 and SIG1.

[0144] The gain control circuit 410 controls the pixel signal SIG1 at a gain g １ and a gain control circuit 410-1 that increases or decreases the pixel signal SIG0 by a gain g ２ The gain control circuit 420 also includes a gain control circuit 410-2 that increases or decreases the pixel signal SIG0 by a gain g １ and a gain control circuit 420-1 that increases or decreases the pixel signal SIG1 by a gain g ２ and a gain control circuit 420-2 that increases or decreases the gain.

[0145] The offset control circuit 430 applies an offset "-c" to the pixel signal SIG1. １ " to the pixel signal SIG0, and ２The offset control circuit 440 includes an offset control circuit 430-2 that superimposes an offset "-c １ " to the pixel signal SIG1, and ２ and an offset control circuit 440-2 that superimposes the signal.

[0146] The pixel signal SIG1 is converted into a gain g １ The pixel signal SIG0 is increased or decreased by the gain g ２ The control that increases or decreases by their relative gain g １ / g ２ Therefore, the gain g in the formula 1 and the formula 2 is changed to the relative gain g １ / g ２ The same applies to the comparator 465 side. Also, in the offset control, c in the equation 1 etc. is replaced by c １ and c ２ Just replace it with the difference.

[0147] As shown in the diagram, the gain control circuit and the offset control circuit perform gain control and offset control on both of a pair of pixel signals, thereby making it possible to improve the symmetry of the circuit in terms of layout.

[0148] As described above, according to the second modification of the first embodiment of the present technology, the gain control circuit and the offset control circuit perform gain control and offset control on both of a pair of pixel signals, thereby increasing the symmetry of the circuit.

[0149] 2. Second Embodiment In the first embodiment described above, the comparators 450 and 465 are arranged in the edge detection unit 400 outside the ADC 320, but it is preferable to further reduce the circuit size. The image sensor 200 in this second embodiment differs from the first embodiment in that the ADC and the edge detection unit share the comparator.

[0150] 20 is a block diagram showing a configuration example of a column signal processing circuit 300 according to a second embodiment of the present technology. The column signal processing circuit 300 according to the second embodiment includes a plurality of switches, such as switches 331, 332, 333, and 334, a plurality of gain control circuits, a plurality of offset control circuits, a plurality of comparators, and a plurality of counters. Two switches are provided for each column. One gain control circuit, one offset control circuit, one comparator, and one counter are provided for each column.

[0151] For example, in a column corresponding to the vertical signal line VSL0, the switches 331 and 332, the gain control circuit 410, the offset control circuit 430, the comparator 450, and the counter 341 are arranged. In a column corresponding to the vertical signal line VSL1, the switches 333 and 334, the gain control circuit 420, the offset control circuit 440, the comparator 465, and the counter 342 are arranged.

[0152] The switch 331 receives a control signal SW from the timing control circuit 230. ＤＡＣ The switch 332 opens and closes the path between the DAC 220 and the non-inverting input terminal (+) of the comparator 450 in accordance with the control signal SW ＤＡＣ , and opens and closes a path between the vertical signal line VSL1 and the gain control circuit 410 and the offset control circuit 430. The switches 331 and 332 are controlled so that when one is closed, the other is open.

[0153] The switch 333 receives a control signal SW ＤＡＣ The switch 334 opens and closes the path between the DAC 220 and the non-inverting input terminal (+) of the comparator 465 in accordance with the control signal SW ＤＡＣ , and opens and closes a path between the vertical signal line VSL0 and the gain control circuit 420 and the offset control circuit 440. The switches 333 and 334 are controlled so that when one is closed, the other is open.

[0154] The DAC 220 is an example of a reference signal generating unit as set forth in the claims. The switches 331 and 333 are an example of a reference-side switch as set forth in the claims. The switches 332 and 334 are an example of a pixel-side switch as set forth in the claims.

[0155] The circuit configurations of gain control circuits 410 and 420, offset control circuits 430 and 440, and comparators 450 and 465 in the second embodiment are the same as those in the first embodiment, except that comparator 450 further outputs comparison result VCO0 to counter 341, and comparator 465 further outputs comparison result VCO1 to counter 342.

[0156] Counter 341 counts the count value over a period until comparison result VCO0 is inverted. Counter 342 counts the count value over a period until comparison result VCO1 is inverted. These counters 341 and 342 output digital signals indicating the count values ​​to signal processing circuit 290.

[0157] In the edge detection mode, the timing control circuit 230 disables the counters 341 and 342, controls the switches 331 and 333 to an open state, and controls the switches 332 and 334 to a closed state. The DAC 220 generates an offset voltage. The circuitry consisting of the gain control circuits 410 and 420, the offset control circuits 430 and 440, and the comparators 450 and 465 functions as the edge detection unit 400.

[0158] On the other hand, in the imaging mode, the timing control circuit 230 enables the counters 341 and 342, controls the switches 331 and 333 to a closed state, and controls the switches 332 and 334 to an open state. The DAC 220 generates a reference signal (such as a ramp signal). The comparator 450 and the counter 341 function as a single-slope ADC, and the comparator 465 and the counter 342 also function as a single-slope ADC.

[0159] As described above, the edge detection unit 400 and the ADC share the comparators 450 and 465, and therefore the circuit scale can be reduced compared to the first embodiment in which the comparators are not shared.

[0160] The first and second modifications of the first embodiment can be applied to the second embodiment, in which case a switch is further provided to bypass the circuit between the inverting input terminal (−) of the comparator and the vertical signal line.

[0161] As described above, according to the second embodiment of the present technology, the edge detection unit 400 and the ADC share the comparators 450 and 465, and therefore the circuit scale can be reduced.

[0162] 3. Third Embodiment In the first embodiment described above, the gain value and offset value are fixed and the edge detection unit 400 outputs a 2-bit signal, but this configuration can result in an insufficient amount of information. The image sensor 200 in this third embodiment differs from the first embodiment in that the gain value and offset value are variable and the number of bits output by the edge detection unit 400 is increased.

[0163] 21 is a block diagram showing an example configuration of the edge detection unit 400 according to the third embodiment of the present technology. The edge detection unit 400 according to the third embodiment differs from the first embodiment in that it further includes latch circuits 481 to 486.

[0164] Furthermore, timing control circuit 230 sequentially selects from a plurality of combinations each including an offset value and a gain value, and sets the selected values ​​in offset control circuits 430 and 440 and gain control circuits 410 and 420 .

[0165] For example, if the offset and gain values ​​are "g ０ " and "-c ０ " and "g １ " and "-c １ " and "g ２ " and "-c ２ " are set in order.

[0166] The comparator 450 outputs the comparison result VCO0 to the input terminals of the latch circuits 481, 482, and 483. The comparator 465 outputs the comparison result VCO1 to the latch circuits 484, 485, and 486.

[0167] The latch circuit 481 holds the comparison result VCO0 in accordance with the enable signal LTEN0 from the timing control circuit 230. The latch circuit 482 holds the comparison result VCO0 in accordance with the enable signal LTEN1 from the timing control circuit 230. The latch circuit 483 holds the comparison result VCO0 in accordance with the enable signal LTEN2 from the timing control circuit 230. The latch circuit 484 holds the comparison result VCO1 in accordance with the enable signal LTEN0. The latch circuit 485 holds the comparison result VCO1 in accordance with the enable signal LTEN1. The latch circuit 486 holds the comparison result VCO1 in accordance with the enable signal LTEN2.

[0168] The timing control circuit 230 sets the offset value and gain value as "g ０ " and "-c ０ When the setting is "YES", the enable signal LTENO is enabled to hold the comparison results in the latch circuits 481 and 484. At this time, the enable signals LTENO and LTENO are controlled to be disabled.

[0169] The timing control circuit 230 also sets the offset value and gain value as "g １ " and "-c １ When the setting is "ON", the enable signal LTENO is enabled to hold the comparison results in the latch circuits 482 and 485. At this time, the enable signals LTENO and LTENO2 are controlled to be disabled.

[0170] The timing control circuit 230 also sets the offset value and gain value as "g ２ " and "-c ２When the setting is "YES", the enable signal LTENO is enabled to hold the comparison results in the latch circuits 483 and 486. At this time, the enable signals LTENO and LTENO are controlled to be disabled.

[0171] As described above, the latch circuits 481 to 486 hold the comparison results of the three combinations, and output the held 6-bit signals to the signal processing circuit 290.

[0172] As shown in FIG. 8, an edge determination circuit 470 can be added. In this case, six bits can be combined into three bits, so only three latch circuits are required. Furthermore, a logic gate can be added to combine these three bits into one bit. However, it should be noted that the more the number of output bits is reduced, the less information there is, which may result in a decrease in edge detection accuracy.

[0173] Furthermore, although there are three combinations of offset values ​​and gain values, the number of combinations is not limited to three and may be two, four, or more. When there are four or more combinations, latch circuits are added according to the number.

[0174] 22 is a circuit diagram showing an example configuration of an offset control circuit 430 and a gain control circuit 410 according to the third embodiment of the present technology. The gain control circuit 410 according to the third embodiment differs from the first embodiment in that it further includes switches 415 and 416 and a capacitive element 419.

[0175] The switch 415 opens and closes the path between the vertical signal line VSL1 and one end of the capacitance element 419 in accordance with a control signal SW2 a from the timing control circuit 230. The switch 416 opens and closes the path between the ground node and one end of the capacitance element 419 in accordance with a control signal SW2 b from the timing control circuit 230. The other end of the capacitance element 419 is connected to the non-inverting input terminal (+) of the comparator 450. Furthermore, the switches 415 and 416 are closed when the corresponding control signal is at a high level, and are open when the corresponding control signal is at a low level.

[0176] The circuit configuration of the offset control circuit 430 of the third embodiment is the same as that of the first embodiment. When changing the offset value, the timing control circuit 230 controls the DAC 220 to set the offset voltage V оｆｓ Change the

[0177] 23 is a circuit diagram showing an example configuration of an offset control circuit 440 and a gain control circuit 420 according to the third embodiment of the present technology. The gain control circuit 420 according to the third embodiment differs from the first embodiment in that it further includes switches 425 and 426 and a capacitive element 429.

[0178] The switch 425 opens and closes the path between the vertical signal line VSL0 and one end of the capacitance element 429 in accordance with a control signal SW2a. The switch 426 opens and closes the path between the ground node and one end of the capacitance element 429 in accordance with a control signal SW2b. The other end of the capacitance element 429 is connected to the non-inverting input terminal (+) of the comparator 465. Furthermore, the switches 425 and 426 are closed when the corresponding control signal is at a high level, and are open when the corresponding control signal is at a low level.

[0179] 24 is a timing chart showing an example of operation of the image sensor when illuminance is low according to the third embodiment of the present technology. In the third embodiment, the control of the selection signal SEL, the reset signal RST, the transfer signal TRG, the auto-zero signal AZ, the control signal SW3 a, the control signal SW3 b, and the control signal SW3 c is the same as in the first embodiment.

[0180] At timing T0, the timing control circuit 230 sets the control signals SW0a, SW1a, and SW2a to a high level, and sets the control signals SW0b, SW1b, and SW2b to a low level. ｐ Immediately after this, the timing control circuit 230 sets the control signals SW1a and SW2b to a low level. ｄ０ From T ｄ１ The control signal SW1b is set to a high level during the period up to the timing T ｄ１ From T ｄ２During this time, the control signal SW2b is set to a high level.

[0181] The comparison result VCO0 is ｄ１ From T ｄ２ The signal changes to a low level before this timing, and an edge is detected after this timing.

[0182] 25 is a diagram for explaining a method for setting the first gain value according to the third embodiment of the present technology. In the figure, a indicates the timing T ｐ The timing T b in the figure shows the state of the offset control circuit 430 and the gain control circuit 410 at the time when the signal level is stabilized. ｄ０ 4 shows the states of the offset control circuit 430 and the gain control circuit 410 at

[0183] In a and b of the same figure, attention is focused on switches 411, 413, 415 and 432, and other switches are omitted.

[0184] As shown in FIG. 1A, at timing T ｐ At this time, the switches 411, 413, 415, and 432 are controlled to be in a closed state. ｉ＿ｐ and the level of the output terminals of the capacitance elements 417, 418, 419 and 435 is V ｏ＿ｐ The capacitance of the capacitance element 417 is C ０ and the capacitance of the capacitance element 418 is C １ and the capacitance of the capacitance element 419 is C ２ and the capacitance of the capacitance element 435 is C ３ In this case, the charge amount Q stored in each of the capacitance elements 417, 418, 419, and 435 is ０＿ｐ , Q １＿ｐ , Q ２＿ｐ and Q ３＿ｐ is expressed by the following formula: ０＿ｐ =C ０ (V ｏ＿ｐ -V ｉ＿ｐ )...Formula 15 Q １＿ｐ =C １ (V ｏ＿ｐ-V ｉ＿ｐ )...Formula 16 Q ２＿ｐ =C ２ (V ｏ＿ｐ -V ｉ＿ｐ ) ...Formula 17 Q ３＿ｐ =C ３ ・V ｏ＿ｐ ...Formula 18

[0185] Then, as shown in FIG. 1B, timing T ｄ０ At this time, the switches 413 and 415 are controlled to be in an open state. ｉ＿ｄ and the level of the output terminals of the capacitance elements 417, 418, 419 and 435 is V ｏ＿ｄ０ At this time, the charge amounts Q of the capacitance elements 417 and 435 are ０＿ｄ０ and Q ３＿ｄ０ is expressed by the following formula: ０＿ｄ０ =C ０ (V ｏ＿ｄ０ -V ｉ＿ｄ ) ...Formula 19 Q ３＿ｄ０ =C ３ ・V ｏ＿ｄ０ ...Formula 20

[0186] Furthermore, the law of conservation of charge gives the following equation: Q ０＿ｐ +Q ３＿ｐ =Q ０＿ｄ０ +Q ３＿ｄ０ ...Formula 21

[0187] By substituting the right-hand sides of Equations 15 and 18 and the right-hand sides of Equations 19 and 20 into Equation 21 and transforming it, the following equation is obtained.

[0188] In Equation 22, the left side corresponds to the output pixel signal, and the right side (V ｉ＿ｄ０ -V ｉ＿ｐ ) corresponds to the input pixel signal. Therefore, the ratio of these, C ０ / (C ０ +C ３ ) is the first set gain value g ０ This applies to:

[0189] 26 is a diagram for explaining a method for setting the second and third gain values ​​according to the third embodiment of the present technology. ｄ０ Timing T after ｄ１ 10. The state of the offset control circuit 430 and the gain control circuit 410 at the timing T ｄ２ 4 shows the states of the offset control circuit 430 and the gain control circuit 410 at

[0190] As shown in FIG. 1A, at timing T ｄ１ In this state, the switch 413 is controlled to be in a closed state. This control causes the levels of the output terminals of the capacitance elements 417, 418, 419, and 435 to fluctuate, and the levels are set to V ｏ＿ｄ１ At this time, the charge amounts Q of the capacitance elements 417, 418, and 435 are ０＿ｄ１ , Q １＿ｄ１ and Q ３＿ｄ１ is expressed by the following formula: ０＿ｄ１ =C ０ (V ｏ＿ｄ１ -V ｉ＿ｄ ) ...Formula 23 Q １＿ｄ１ =C １ (V ｏ＿ｄ１ -V ｉ＿ｄ )...Formula 24 Q ３＿ｄ１ =C ３ ・V ｏ＿ｄ１ ...Formula 25

[0191] Furthermore, the law of conservation of charge gives the following equation: Q ０＿ｐ +Q ２＿ｐ +Q ３＿ｐ =Q ０＿ｄ１ +Q １＿ｄ１ +Q ３＿ｄ１ ...Equation 26

[0192] Substituting the right-hand sides of Equations 15, 17, and 18 and the right-hand sides of Equations 23, 24, and 25 into Equation 26 and rearranging it, the following equation is obtained.

[0193] (C ０ +C １ ) / (C０ +C １ +C ３ ) is the second set gain value g １ This applies to:

[0194] Then, as shown in FIG. 1B, timing T ｄ２ In this case, the switch 415 is controlled to be in the closed state. In this case, the following equation can be obtained by the same method as used to derive equations 22 and 27.

[0195] (C ０ +C １ +C ２ ) / (C ０ +C １ +C ２ +C ３ ) is the third set gain value g ２ This applies to:

[0196] As illustrated in FIGS. 25 and 26, the timing control circuit 230 can switch the gain value by controlling the switch to which the capacitive element is connected.

[0197] 27 is a diagram showing offset values ​​and gain values ​​for each combination according to the third embodiment of the present technology, in which the vertical axes a, b, and c indicate the level of pixel signal SIG1, and the horizontal axis indicates the level of pixel signal SIG0.

[0198] The gray area a in the figure indicates the offset and gain values ​​are "g ０ " and "-c ０ The gray area b in the figure shows the area where an edge is determined to exist when the offset value and gain value are set to "g １ " and "-c １ The gray area c in the figure shows the area where an edge is determined to exist when the offset value and gain value are set to "g ２ " and "-c ２ " indicates the area that is determined to have an edge when "

[0199] As shown in a, b, and c in the figure, by switching the combination of offset and gain values, the area determined to have an edge changes, and the detection result also changes. Therefore, compared to the first embodiment in which the offset and gain values ​​are fixed, the amount of information increases and sensing performance can be improved.

[0200] 28 is a flowchart showing an example of the operation of the image sensor 200 according to the third embodiment of the present technology. The operation of the image sensor 200 according to the third embodiment differs from that according to the first embodiment in that steps S911 to S913 are executed instead of step S904.

[0201] After step S903, the comparator 450 calculates SIG0 and SIG1*g ０ -c ０ The comparator 465 compares SIG0*g ０ -c ０ Then, the timing control circuit 230 switches the gain value and the offset value, and the comparator 450 compares SIG0 with SIG1*g １ -c １ The comparator 465 compares SIG0*g １ -c １ Then, the timing control circuit 230 switches the gain value and the offset value, and the comparator 450 compares SIG0 with SIG1*g ２ -c ２ The comparator 465 compares SIG0*g ２ -c ２ and SIG1 (step S913). After step S913, steps S905 and subsequent steps are executed.

[0202] The first and second modifications of the first embodiment and the second embodiment can be applied to the third embodiment.

[0203] As described above, according to the third embodiment of the present technology, the gain value and the offset value are made variable and the number of bits output by the edge detection unit 400 is increased, thereby improving sensing performance.

[0204] [First Modification] In the third embodiment described above, the offset voltage V ｏｆｓ However, when the DAC 220 changes the offset value, it takes a certain amount of time for the changed voltage to stabilize. Therefore, the time required to detect an edge becomes longer than when the offset value is not changed. The image sensor 200 in this first modification of the third embodiment differs from the third embodiment in that one end of a capacitive element is connected to one of multiple nodes having different offset voltages.

[0205] 29 is a circuit diagram showing a configuration example of an offset control circuit 430 and a gain control circuit 410 according to a first modified example of the third embodiment of the present technology. The offset control circuit 430 according to the first modified example of the third embodiment differs from the first embodiment in that it further includes a switch 434.

[0206] In addition, the switch 432 connects one end of the capacitance element 435 to the offset voltage V ｏｆｓｂ The switch 433 connects one end of the capacitance element 435 to the node of the offset voltage V ｏｆｓｃ The switch 434 connects one end of the capacitance element 435 to the node of the offset voltage V ｏｆｓｄ The switch 432 is an example of a first offset-side switch as set forth in the claims, and the switch 434 is an example of a second offset-side switch as set forth in the claims.

[0207] Offset voltage V ｏｆｓｂ , V ｏｆｓｃ and V ｏｆｓｄ The value of the offset value c ０ , c １ and c ２ Corresponds to.

[0208] The circuit configuration of the offset control circuit 440 is the same as that of the offset control circuit 430 .

[0209] As shown in the figure, one end of the capacitance element 435 is connected to a capacitor having an offset voltage V ｏｆｓｂ , V ｏｆｓｃ and V ｏｆｓｄ By switching to one of the nodes, the time required to detect an edge can be shortened compared to when the output voltage of the DAC 220 is switched.

[0210] The first and second modifications of the first embodiment and the second embodiment can be applied to the first modification of the third embodiment.

[0211] As described above, according to the first modified example of the third embodiment of the present technology, the timing control circuit 230 switches the connection destination of one end of the capacitance element 435 to one of multiple nodes with different offset voltages, thereby shortening the time required to detect an edge.

[0212] [Second Modification] In the third embodiment described above, the output terminals of the capacitive elements 417, 418, 419, and 435 in the edge detection unit 400 are connected to a comparator, but this is not a limitation. The image sensor 200 in this second modification of the third embodiment differs from the third embodiment in that one end of each capacitive element is grounded.

[0213] 30 is a circuit diagram showing a configuration example of an offset control circuit 430 and a gain control circuit 410 according to a second modified example of the third embodiment of the present technology. In this second modified example of the third embodiment, the offset control circuit 430 includes switches 431, 432, and 433 and a capacitive element 435.

[0214] The switch 431 opens and closes the path between one end of the capacitance element 435 and the vertical signal line VSL1 in accordance with a control signal SW3a. The switch 432 opens and closes the path between the other end of the capacitance element 435 and the ground node in accordance with a control signal SW3b. The switch 433 opens and closes the path between the offset voltage Vｏｆｓ The path between the node and the other end of the capacitance element 435 is opened or closed.

[0215] The gain control circuit 410 also includes switches 411 to 416 and capacitance elements 417 to 419. The other end of each of the capacitance elements 417, 418, and 419 is grounded.

[0216] The switch 411 opens and closes the path between one end of the capacitance element 417 and the connection point of the switch 431 and the capacitance element 435 in accordance with a control signal SW0a. The switch 412 opens and closes the path between one end and the other end of the capacitance element 417 in accordance with a control signal SW0b. The switch 413 opens and closes the path between one end of the capacitance element 418 and the connection point of the switch 431 and the capacitance element 435 in accordance with a control signal SW1a. The switch 414 opens and closes the path between one end and the other end of the capacitance element 418 in accordance with a control signal SW1b. The switch 415 opens and closes the path between one end of the capacitance element 419 and the connection point of the switch 431 and the capacitance element 435 in accordance with a control signal SW2a. The switch 416 opens and closes the path between one end and the other end of the capacitance element 419 in accordance with a control signal SW2b.

[0217] In addition, a capacitance element 407 is inserted between the connection point of the switch 431 and the capacitance element 435 and the non-inverting input terminal (+) of the comparator 450 .

[0218] 31 is a diagram for explaining control for maintaining a reset level and a signal level in a second modified example of the third embodiment of the present technology. In the figure, a indicates a timing T ｐ The timing T b in the figure shows the state of the offset control circuit 430 and the gain control circuit 410 at the time when the signal level is stabilized. ｄ 4 shows the states of the offset control circuit 430 and the gain control circuit 410 at

[0219] In a and b of the same figure, attention is focused on switches 411, 413, and 415, and other switches are omitted.

[0220] As shown in FIG. 1A, at timing T ｐAt this time, the switches 411, 413, and 415 are controlled to be in a closed state. Ｐ The capacitance of the capacitor 417 is C ３ and the capacitance of the capacitance element 418 is C ２ and the capacitance of the capacitance element 419 is C １ and the capacitance of the capacitance element 435 is C ０ In this case, the charge amount Q stored in each of the capacitance elements 417, 418, 419, and 435 is ３ , Q ２ , Q １ and Q ０ is expressed by the following formula: ０ =C ０ V Ｐ ...Formula 29 Q １ =C １ V Ｐ ...Formula 30 Q ２ =C ２ V Ｐ ...Formula 31 Q ３ =C ３ V Ｐ ...Formula 32

[0221] Then, as shown in FIG. 1B, timing T ｄ At this time, the switches 411, 413, and 415 are controlled to be in an open state. Ｄ In this case, the amount of charge Q stored in the capacitor 435 is ０ Q' is expressed by the following formula: ０ '=C ０ V Ｄ ...Formula 33

[0222] 32 is a diagram for explaining a method for setting the first to third gain values ​​in the second modified example of the third embodiment of the present technology. ｄ Timing T afterｄ０ 10. The state of the offset control circuit 430 and the gain control circuit 410 at the timing T ｄ１ 10. The state of the offset control circuit 430 and the gain control circuit 410 at the timing T ｄ２ 4 shows the states of the offset control circuit 430 and the gain control circuit 410 at

[0223] As shown in FIG. 1A, at timing T ｄ０ The switch 415 is controlled to be in a closed state. The charge distribution between the capacitance elements 435 and 419 causes the level of the input terminal of the comparator 450 to fluctuate. This level is referred to as V ｉｎ In this case, the charge amount Q of the capacitance elements 435 and 419 is １ '' and Q ０ Q'' is expressed by the following formula: ０ ''=C ０ V ｉｎ ...Formula 34 Q １ ''=C １ V ｉｎ ...Formula 35

[0224] The law of conservation of charge gives us the following equation: Q ０ '+Q １ =Q ０ ''+Q １ ''...Formula 36

[0225] Substituting the right-hand sides of Equations 30 and 33 and the right-hand sides of Equations 34 and 35 into Equation 36 and rearranging it, the following equation is obtained.

[0226] C in Formula 37 ０ / (C ０ +C １ ) is the first set gain value g ０ This applies to:

[0227] Then, as shown in FIG. 1B, at timing T ｄ１The switch 413 is controlled to be in a closed state. The charge amount Q of the capacitance element 418 after the charge sharing among the capacitance elements 435, 419, and 418 ２ Q'' is expressed by the following formula: ２ ''=C ２ V ｉｎ ...Formula 38

[0228] The law of conservation of charge gives us the following equation: Q ０ '+Q １ +Q ２ =Q ０ ''+Q １ ''+Q ２ ''...Formula 39

[0229] Substituting the right-hand sides of Equations 30, 31, and 33 and the right-hand sides of Equations 34, 35, and 38 into Equation 39 and transforming it, the following equation is obtained.

[0230] C in Formula 40 ０ / (C ０ +C １ +C ２ ) is the second set gain value g １ This applies to:

[0231] Then, as shown in FIG. 1C, at timing T ｄ２ The switch 411 is controlled to be in the closed state. The following equation can be obtained by a method similar to that of equations 37 and 40.

[0232] C in Formula 41 ０ / (C ０ +C １ +C ２ +C ３ ) is the third set gain value g ２ This applies to:

[0233] As shown in FIGS. 31 and 32, one end of capacitance elements 417, 418, and 419 is grounded, and the other ends of the capacitance elements are connected to switches 411, 413, and 415, which are controlled by the timing control circuit 230, thereby switching the gain value.

[0234] The second embodiment can be applied to the second modified example of the third embodiment.

[0235] In this way, one end of the capacitance elements 417, 418, and 419 is grounded, and the timing control circuit 230 controls the switches 411, 413, and 415 connected to the other ends thereof, thereby making it possible to vary the gain value.

[0236] [Third Modification] In the third embodiment described above, a capacitance element and a switch are provided in the gain control circuit 410, but the circuit configuration of the gain control circuit 410 is not limited to this configuration. The image sensor 200 in this third modification of the third embodiment differs from the third embodiment in that an amplifier, a capacitance element, and a switch are provided in the gain control circuit 410.

[0237] 33 is a circuit diagram showing a configuration example of an offset control circuit 430 and a gain control circuit 410 in a third modified example of the third embodiment of the present technology. The offset control circuit 430 in the third modified example of the third embodiment differs from the third embodiment in that the switch 431 is eliminated.

[0238] In addition, a capacitive element 407 is inserted between the vertical signal line VSL 0 and the non-inverting input terminal (+) of the comparator 450 .

[0239] Moreover, the gain control circuit 410 in the third modification of the third embodiment includes capacitive elements 491 , 417 , 418 and 419 , an amplifier 492 , and switches 411 , 412 , 413 and 414 .

[0240] The capacitive element 491 is inserted between the vertical signal line VSL1 and the input terminal of the amplifier 492. One end of each of the capacitive elements 417, 418, and 419 is commonly connected to the output terminal of the amplifier 492.

[0241] The switch 411 opens and closes the path between the input terminal of the amplifier 492 and the other end of the capacitive element 417 in accordance with a control signal SW0 from the timing control circuit 230. The switch 412 opens and closes the path between the input terminal of the amplifier 492 and the other end of the capacitive element 418 in accordance with a control signal SW1 from the timing control circuit 230. The switch 413 opens and closes the path between the input terminal of the amplifier 492 and the other end of the capacitive element 419 in accordance with a control signal SW2 from the timing control circuit 230.

[0242] The switch 414 opens and closes the path between the input terminal and the output terminal of the amplifier 492 in accordance with the auto-zero signal AZ.

[0243] In addition, a capacitive element 406 is inserted between the output terminal of the amplifier 492 and the inverting input terminal (−) of the comparator 450. The gain control circuit 410 performs amplification using the amplifier 492, and the output thereof is input to the inverting input terminal (−) of the comparator 450.

[0244] The timing control circuit 230 controls each of the switches 411, 412, and 413 to change the value of the capacitance connected in parallel to the amplifier 492, thereby switching the gain value.

[0245] The circuit configurations of the gain control circuit 420 and the offset control circuit 440 are similar to those of the gain control circuit 410 and the offset control circuit 430 .

[0246] Moreover, the second embodiment can also be applied to the third modified example of the third embodiment.

[0247] As described above, according to the third modified example of the third embodiment of the present technology, the timing control circuit 230 changes the value of the capacitance connected in parallel to the amplifier 492, thereby making the gain value variable.

[0248] 4. Fourth Embodiment In the third embodiment described above, multiple gain values ​​are set in sequence, but it is preferable to further reduce power consumption. Image sensor 200 in this fourth embodiment differs from the third embodiment in that comparators 450 and 465 are stopped when an edge is detected.

[0249] FIG. 34 is a diagram for explaining the control of the timing control circuit 230 according to the fourth embodiment of the present technology.

[0250] In the fourth embodiment, the latch circuits 481 to 486 also output the held comparison results to the timing control circuit 230. The timing control circuit 230 sets multiple gain values ​​in ascending order. The timing control circuit 230 then references the comparison results VCO0 and VCO1 corresponding to the set gain values. As described above, if the values ​​of the comparison results VCO0 and VCO1 differ, this indicates that an edge has been detected. If the values ​​of the comparison results VCO0 and VCO1 differ (i.e., if an edge has been detected), the timing control circuit 230 stops the comparators 450 and 465.

[0251] 35 is a timing chart showing an example of the operation of the image sensor 200 according to the fourth embodiment of the present technology. Control of the selection signal SEL, the reset signal RST, the transfer signal TRG, the auto-zero signal AZ, and the control signals SW0a to SW3c in the fourth embodiment is the same as that in the third embodiment.

[0252] For example, the timing T ｄ０ Assume that the comparison result VCO0 becomes low level and the comparison result VCO1 becomes high level in this case. These comparison results indicate that an edge has been detected. If an edge is detected at a certain gain value, an edge will also be detected when a remaining gain value greater than that is set. Therefore, the detection result will not change thereafter, and there is no need to operate comparators 450 and 465. Therefore, timing control circuit 230 stops these comparators. This control allows for reduced power consumption compared to when the comparators are not stopped.

[0253] In addition, in a plurality of combinations, the offset values ​​may all be the same value (in other words, fixed values) or may be different values ​​(in other words, variable values).

[0254] 36 is a flowchart showing an example of the operation of the image sensor 200 according to the fourth embodiment of the present technology. The operation of the image sensor 200 according to the fourth embodiment differs from that of the first embodiment in that steps S921 to S923 are executed instead of step S905.

[0255] The timing control circuit 230 determines whether or not there is an edge based on the comparison results VCO0 and VCO1 (step S921). If there is an edge (step S921: Yes), the timing control circuit 230 stops the comparators 450 and 465 and executes step S906 and subsequent steps.

[0256] If there is no edge (step S921: No), the timing control circuit 230 determines whether or not all gain values ​​have been used for the determination (step S922). If all gain values ​​have been used for the determination (step S922: Yes), the timing control circuit 230 executes step S906 and subsequent steps. If all gain values ​​have not been used for the determination (step S922: No), the timing control circuit 230 changes the gain value to the next largest value (step S923) and executes step S904 and subsequent steps.

[0257] It should be noted that the first and second modified examples of the first embodiment, the second embodiment, and the first, second, and third modified examples of the third embodiment can be applied to the fourth embodiment.

[0258] As described above, according to the fourth embodiment of the present technology, the timing control circuit 230 stops the comparators 450 and 465 when an edge is detected, thereby reducing power consumption.

[0259] 5. Fifth Embodiment In the first embodiment described above, the circuits are arranged on a single semiconductor chip, but this configuration may make it difficult to miniaturize pixels. Image sensor 200 in this fifth embodiment differs from the first embodiment in that the circuits are distributed across multiple stacked semiconductor chips.

[0260] 37 is a diagram showing an example of a stacked structure of an image sensor 200 according to a fifth embodiment of the present technology. The image sensor 200 according to the fifth embodiment includes a circuit chip 202 and a pixel chip 201 stacked on the circuit chip 202. These chips are electrically connected via connecting portions such as vias. Note that, in addition to vias, they can also be connected by Cu-Cu bonding or bumps.

[0261] The pixel chip 201 includes a pixel array unit 240, a north column signal processing circuit 301, and a south column signal processing circuit 302.

[0262] The north column signal processing circuit 301 reads pixel signals and edge determination results from half of the pixels (such as odd-numbered columns) in the pixel array unit 240, and the south column signal processing circuit 302 reads pixel signals and the like from the remaining half. Various peripheral circuits, such as a signal processing circuit 290, are arranged on the circuit chip 202.

[0263] As shown in FIG. 38, it is also possible to arrange only the pixel array section 240 on the pixel chip 201 and arrange the remaining circuits on the circuit chip 202.

[0264] 37 and 38, miniaturization of pixels is facilitated by distributing circuits among stacked pixel chips 201 and circuit chips 202. It is also possible to stack three or more semiconductor chips and arrange circuits on them.

[0265] In addition, the first and second variants of the first embodiment, the second embodiment, the third embodiment, the first, second and third variants of the third embodiment, and the fourth embodiment can each be applied to the fifth embodiment.

[0266] In this way, according to the fifth embodiment of the present technology, since the circuits are distributed and arranged on the stacked pixel chip 201 and circuit chip 202, it becomes easy to miniaturize the pixels.

[0267] 6. Sixth Embodiment In the first embodiment described above, the offset control circuits 430 and 440 superimpose the offset c on at least one of a pair of pixel signals. Hereinafter, this offset c will be referred to as an "edge offset," and its setting will be described.

[0268] 39 is a graph showing the incidence rate for each level at low illuminance in a comparative example and the first embodiment of the present technology. In the figure, "a" shows an example of the incidence rate at low illuminance in a comparative example in which an edge offset is not superimposed, and "b" in the figure shows the incidence rate at low illuminance in the first embodiment in which an edge offset is superimposed. The thin solid line shows the incidence rate at each level of the pixel signal SIG0, and the dashed-dotted line shows the incidence rate at each level of the pixel signal SIG1. The thick line shows the incidence rate at each level of the difference signal between the pixel signals SIG0 and SIG1. The gray portion indicates an area where an edge is erroneously determined to exist due to noise components. Under low illuminance conditions, the gain g can be ignored.

[0269] As shown in a and b in the figure, the noise component distribution is a normal distribution. Also, as shown in b in the figure, the superposition of edge offset reduces erroneous determinations at low illuminance.

[0270] 40 is a diagram showing an example of an edge image at low illuminance in the first embodiment of the present technology. Here, the edge image is an image in which edge determination results for each pixel are arranged. In the first embodiment, edge images 701, 702, and 703 are generated under low illuminance by changing the edge offset value.

[0271] The edge offset corresponding to the edge image 701 is the smallest, the edge offset corresponding to the edge image 702 is larger than that of the edge image 701, and the edge offset corresponding to the edge image 703 is larger than that of the edge image 702.

[0272] As shown in the figure, erroneous edge determinations become noise and are most prevalent in edge image 701. Edge image 702 has fewer erroneous edge determinations than edge image 701, and edge image 703 has fewer erroneous edge determinations than edge image 702.

[0273] As mentioned above, the larger the edge offset, the fewer erroneous determinations there are. However, if the edge offset is excessive, it becomes impossible to determine edges where the difference between a pair of pixel signals is small, and the object recognition accuracy decreases. For this reason, it is necessary to manage the edge offset so that it is an appropriate value.

[0274] Fig. 41 is a graph showing an example of the edge ratio for each edge offset at low illuminance in the first embodiment of the present technology. Here, the edge ratio indicates the ratio of the number of pixels in which an edge is detected in the edge image to the total number of pixels. In the same figure, the vertical axis indicates the edge ratio, and the horizontal axis indicates the edge offset. The dotted line indicates ideal characteristics, and the solid curve is a plot of actually obtained evaluation values. The dashed-dotted line indicates the target value of the edge ratio.

[0275] As illustrated in the figure, ideally, the closer the edge offset is to "0," the closer the edge ratio is to "0.5." However, there is often variation in the input offset of the comparator for each column, and this variation causes the operating point of the comparator to vary for each column, resulting in an error in the output signal of the comparator. This output error causes the edge ratio to deviate from the ideal value. The image sensor 200 of the sixth embodiment differs from the first embodiment in that it is provided with a circuit that cancels the output error of the comparator.

[0276] 42 is a block diagram showing an example configuration of the edge detection unit 400 according to the sixth embodiment of the present technology. The edge detection unit 400 according to the sixth embodiment differs from the first embodiment in that it further includes error cancellation circuits 600 and 601.

[0277] The error cancellation circuit 600 cancels the error in the output signal of the comparator 450. The error cancellation circuit 601 cancels the error in the output signal of the comparator 465.

[0278] The pixel signal input to the non-inverting input (+) of the comparator 450 is defined as DIFF_A, and the pixel signal input to the inverting input (-) is defined as DIFF_B. The output signal of the comparator 450 is defined as VOUT2. The error cancellation circuit 600 cancels the error in the output signal VOUT2 and outputs the comparison result as VCO.

[0279] In the figure, the edge detection unit 400 performs offset control and gain control on one of the pixel signals SIG0 and SIG1, but is not limited to this configuration.

[0280] For example, as shown in FIG. 43, the edge-detecting unit 400 can perform gain control on one of the pixel signals SIG0 and SIG1, and offset control on the other.

[0281] As shown in FIG. 19, the edge detection unit 400 according to the sixth embodiment can also perform gain control and offset control on both the pixel signals SIG0 and SIG1.

[0282] 44 is a circuit diagram showing an example configuration of a comparator 450 and an error cancellation circuit 600 according to the sixth embodiment of the present technology. The circuit configuration of the comparator 450 is the same as that of the first embodiment. Note that an output signal from a connection node between a pMOS transistor 452 and an nMOS transistor 457 is designated as VOUT1.

[0283] The error cancellation circuit 600 also includes nMOS transistors 611 and 612 , a pMOS transistor 621 , a capacitance element 631 , and a switch 641 .

[0284] One end on the input side of the capacitive element 631 is connected to the output node of the comparator 450. The nMOS transistor 611 connects one end on the input side of the capacitive element 631 to a reference voltage VSS (ground voltage, etc.) in accordance with a reset signal ADD_RST from the timing control circuit 230. The capacitive element 631 can be initialized by the reset signal ADD_RST.

[0285] The pMOS transistor 621 and the nMOS transistor 612 are connected in series between the power supply voltage VDD and the reference voltage VSS. The gates of the pMOS transistor 621 and the nMOS transistor 612 are connected in common to one end on the output side of the capacitance element 631. A VCO signal indicating the comparison result is output from the connection node between the pMOS transistor 621 and the nMOS transistor 612.

[0286] The switch 641 opens and closes a path between one end on the output side of the capacitance element 631 and the connection node between the pMOS transistor 621 and the nMOS transistor 612 in accordance with a control signal ADD_PLS from the timing control circuit 230. For example, when the control signal ADD_PLS is at a high level, the switch 641 is closed.

[0287] With the circuit configuration illustrated in the figure, the error cancellation circuit 600 can superimpose an offset that compensates for the input offset onto the output signal VOUT2 of the comparator 450, thereby canceling the output error of the comparator 450. The offset that is superimposed to cancel this error is called a "compensation offset."

[0288] The circuit configurations of the comparator 450 and the error cancellation circuit 600 are not limited to those shown in the figure.

[0289] 45, a capacitive element 493 and a pMOS transistor 494 can be further provided in the comparator 450. Furthermore, a switch 642, nMOS transistors 613 and 614, and pMOS transistors 622 and 623 can be further provided in the error cancellation circuit 600.

[0290] In the comparator 450, a capacitive element 493 is inserted between the power supply voltage VDD and the node of VOUT1. A pMOS transistor 494 shorts both ends of the capacitive element 493 in accordance with a reset signal CMP_RST from the timing control circuit 230. The reset signal CMP_RST can initialize the capacitive element 493, which functions as a low-pass filter.

[0291] In the error cancellation circuit 600, the switch 642 shorts both ends of the capacitance element 631 in accordance with the control signal ADD_REG from the timing control circuit 230. For example, when the control signal ADD_REG is at a high level, the switch 642 is closed.

[0292] Here, it is assumed that the image sensor 200 of the sixth embodiment can be applied with the second embodiment in which the edge detection mode and the imaging mode are switched.

[0293] When the second embodiment is applied, in the edge detection mode, the timing control circuit 230 sets the control signal ADD_REG to, for example, a low level, and opens the switch 642. On the other hand, in the imaging mode, the timing control circuit 230 sets the control signal ADD_REG to, for example, a high level, and closes the switch 642.

[0294] Furthermore, the pMOS transistor 622 is inserted between the power supply voltage VDD and the nMOS transistor 612, and the nMOS transistor 613 is inserted between the nMOS transistor 612 and the reference voltage VSS.

[0295] The pMOS transistor 623 and the nMOS transistor 614 are connected in series between the power supply voltage VDD and the reference voltage VSS. An enable signal ADD_EN is input to the gates of the pMOS transistor 623 and the nMOS transistor 614 from the timing control circuit 230. The connection node between the pMOS transistor 623 and the nMOS transistor 614 is commonly connected to the gates of the pMOS transistor 622 and the nMOS transistor 613.

[0296] The error cancellation circuit 600 can be controlled to be enabled or disabled by the enable signal ADD_EN.

[0297] FIG. 46 is a diagram illustrating an example of an input signal to the comparator 450 and an output signal from the comparator 450 and the error cancellation circuit 600 according to the sixth embodiment of the present technology.

[0298] When the level of the input signal DIFF_A to the comparator 450 is higher than the input signal DIFF_B, the output VOUT1 of the first stage in the comparator 450 becomes high level, and the output VOUT2 of the second stage becomes low level. The final output signal VCO of the error cancellation circuit 600 becomes high level. The edge detection result EG becomes low level, indicating, for example, the absence of an edge.

[0299] On the other hand, when the level of the input signal DIFF_A to the comparator 450 is lower than the input signal DIFF_B, VOUT1 goes low and VOUT2 goes high. The output signal VCO of the error cancellation circuit 600 goes low. The edge detection result EG goes high, for example, indicating the presence of an edge.

[0300] Next, with reference to FIGS. 47 and 48, the error to be cancelled by the error cancellation circuit 600 will be described.

[0301] 47 is a diagram showing an example of edge ratios and variances for each edge offset according to the sixth embodiment of the present technology. The horizontal axis in the figure indicates the VSL-converted value of the offset (i.e., the edge offset) superimposed for edge detection, and the vertical axis indicates the edge ratio and its variance σ. If the target value of the variance σ is 2.5, the VSL-converted value of the required offset is the value indicated by the arrow.

[0302] In the case of an ideal comparator 450 with no input offset, the smaller the edge offset, the closer the edge ratio should be to 0.5. However, in the example shown in the figure, the edge ratio approaches 0.9.

[0303] For example, as shown in FIG. 48, a phenomenon equivalent to an offset (ie, input offset) cm occurring within the comparator 450 being carried on the vertical signal line VSL0 can be seen.

[0304] VOUT2, which is the output of the comparator 450, and the VCO, which is the final output, vary due to PVT (Process-Voltage-Temperature) variations and element variations. If the variations are to be absorbed solely by the edge offset, the edge offset must be set assuming the maximum mismatch. In this case, the dead zone of the edge will expand in many cases, degrading the detection limit at low illumination levels.

[0305] To solve this problem, in the error cancellation circuit 600, a capacitive element 631 is inserted between VOUT2 and VCO, and after the auto-zero of the comparator 450 is released by the auto-zero signal AZ, auto-zero is performed by the control signal ADD_PLS.

[0306] 49, the timing control circuit 230 changes the auto-zero signal AZ from high to low at timing T10, and then changes the inverted signals XAZPR and XAZPL from low to high at timing T11. The timing control circuit 230 then changes the control signal ADD_PLS to high from timing T12 immediately thereafter over the pulse period. The control signal ADD_REG is also controlled to low. This operation can cancel the F / T error due to the input offset.

[0307] However, after the auto-zero function of the comparator 450 is released at timing T11, it operates as an amplifier and has two stages of gain, so VOUT2 may fluctuate within the range of VSS-VDD due to the influence of noise. As a result, VOUT2 almost always has an edge due to the input offset, but in rare cases it may fall below the theoretical threshold and have no edge. As a result, if cancellation is not performed by the error cancellation circuit 600, the edge ratio will be approximately 0.9, as described above. The dashed dotted line in the figure shows the trajectory of VOUT2 when there is no edge.

[0308] When switching between the imaging mode and the edge detection mode, the timing control circuit 230 sets the control signal ADD_PLS to low level and the control signal ADD_REG to high level in the imaging mode. The thick dotted lines in the figure indicate the levels of the control signals in the imaging mode.

[0309] In the imaging mode, the reset level and the signal level are each AD converted, and the noise of the comparator is cancelled by CDS processing, which treats the difference component as a net signal. On the other hand, in the edge detection mode, the CDS processing is not executed, so the noise cannot be completely cancelled, and the error cancellation circuit 600 is required.

[0310] 50 is a diagram for explaining the operation of the error cancellation circuit according to the sixth embodiment of the present technology. As illustrated in FIG. 50A, the level of the pixel signal SIG0 on the vertical signal line VSL0 is higher than the level of the pixel signal SIG1 on the vertical signal line VSL1.

[0311] For example, as illustrated in FIG. 1B, assume that pixel signal SIG1 is attenuated by gain G and edge offset c is superimposed on pixel signal SIG0. As a result, DIFF_A, which is an input signal on the VSL1 side of comparator 450, becomes lower than DIFF_B, which is an input signal on the VSL0 side. An ideal comparator 450 would be able to output the comparison results as a VCO.

[0312] However, as illustrated in Fig. 1C, an input offset cm occurs in the actual comparator 450, and is superimposed on the input signal DIFF_A. In the first embodiment without the error cancellation circuit 600, this input offset causes the level of the input signal DIFF_A to be lower than the level of the input signal DIFF_B, causing an error in the VCO.

[0313] Therefore, as shown in d in the figure, in the sixth embodiment, the error cancellation circuit 600 superimposes cm', which is a compensation offset that compensates for the input offset cm, on VOUT2. This is equivalent to control in which cm' is superimposed on the input signal DIFF_B, and it is possible to cancel the error caused by the input offset.

[0314] The added compensation offset simply cancels the input offset, so it does not expand the edge dead zone. However, if the input offset varies, it is necessary to set an edge offset value that can absorb the variation in order to keep the edge ratio variance σ within a target value (e.g., 2.5). Therefore, it should be noted that the dead zone may expand near corners where the difference between a pair of pixel signals is minimum.

[0315] If the edge offset is linked to the input offset, the error cancellation circuit 600 can improve the detection limit for low-illuminance edges.

[0316] It should be noted that each of the second to fifth embodiments can be applied to the sixth embodiment.

[0317] As described above, according to the sixth embodiment of the present technology, the error cancellation circuit 600 cancels the output error of the comparator 450, and therefore, it is possible to improve the accuracy of detecting edges at low illuminance.

[0318] In the sixth embodiment described above, an error cancellation circuit 600 is arranged on the output side of each comparator, but it is preferable to improve area efficiency. Image sensor 200 in this modification of the sixth embodiment differs from the sixth embodiment in that an error cancellation circuit 600 is provided that is common to the comparators of each column.

[0319] 51 is a block diagram showing an example configuration of a column signal processing circuit 300 according to a modification of the sixth embodiment of the present technology. The column signal processing circuit 300 according to the modification of the sixth embodiment includes a replica circuit 650 and an error cancellation circuit 600. The error cancellation circuit 600 is commonly connected to one of a pair of input terminals (e.g., non-inverting input terminals) of comparators in each column, such as the comparators 450 and 465.

[0320] FIG. 52 is a circuit diagram showing a configuration example of a replica circuit 650 and an error cancellation circuit 600 according to a modification of the sixth embodiment of the present technology.

[0321] The replica circuit 650 includes pMOS transistors 651 to 655, nMOS transistors 656 to 660, and capacitance elements 661 to 663. The connection configuration of these elements is the same as the connection configuration of each element in the comparator 450. Furthermore, the same bias voltage Vb (such as a power supply voltage) is input to a pair of input terminals of the replica circuit 650.

[0322] The error cancellation circuit 600 of the sixth embodiment differs from the sixth embodiment in that it further includes an amplifier 643. The amplifier 643 amplifies the potential of the connection node between the pMOS transistor 621 and the nMOS transistor 612, and outputs the amplified potential to each comparator as a VCO.

[0323] The timing control circuit 230 sets the control signal ADD_RST to low level during auto-zeroing of the comparator, which allows the error cancellation circuit 600 to sample the input offset of the replica circuit 650.

[0324] After the auto-zero, the timing control circuit 230 sets the control signal ADD_RST to a high level and sets the control signal ADD_PLS to a high level for the duration of the pulse. This allows the error cancellation circuit 600 to hold the sampled input offset and superimpose it as a compensation offset onto one of the input signals DIFF_A and DIFF_B of the comparator. For example, if the input offset is superimposed on the input signal DIFF_B, the error cancellation circuit 600 superimposes the compensation offset onto the input signal DIFF_A.

[0325] The above-described circuit configuration can cancel the comparator output error due to PVT variations. By implementing this as part of the offset function without modifying the comparator circuit, the detection limit at low illuminance can be efficiently improved.

[0326] In the modification of the sixth embodiment, it is not necessary to arrange the error cancellation circuit 600 for each column, and therefore the area efficiency is better than that of the sixth embodiment. However, it should be noted that the mismatch component for each comparator cannot be removed.

[0327] In a modification of the sixth embodiment, it is also possible to arrange the error cancellation circuit 600 and the comparator having the circuit configuration shown in FIG.

[0328] Thus, according to the modified example of the sixth embodiment of the present technology, the error cancellation circuit 600 superimposes a compensation offset on each input signal of the comparator, thereby improving area efficiency compared to the sixth embodiment.

[0329] 6. Application Examples to Mobile Bodies The technology according to the present disclosure (the present technology) can be applied to various products. For example, the technology according to the present disclosure may be realized as a device mounted on any type of mobile body, such as an automobile, an electric vehicle, a hybrid electric vehicle, a motorcycle, a bicycle, personal mobility, an airplane, a drone, a ship, or a robot.

[0330] FIG. 53 is a block diagram showing a schematic configuration example of a vehicle control system, which is an example of a mobile object control system to which the technology of the present disclosure can be applied.

[0331] The vehicle control system 12000 includes a plurality of electronic control units connected via a communication network 12001. In the example shown in Fig. 53, the vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, an outside-vehicle information detection unit 12030, an inside-vehicle information detection unit 12040, and an integrated control unit 12050. Also shown as functional components of the integrated control unit 12050 are a microcomputer 12051, an audio / video output unit 12052, and an in-vehicle network I / F (Interface) 12053.

[0332] The drivetrain control unit 12010 controls the operation of devices related to the drivetrain of the vehicle in accordance with various programs. For example, the drivetrain control unit 12010 functions as a control device for a drive force generating device for generating a drive force of the vehicle, such as an internal combustion engine or a drive motor, a drive force transmission mechanism for transmitting the drive force to the wheels, a steering mechanism for adjusting the steering angle of the vehicle, and a braking device for generating a braking force of the vehicle.

[0333] The body system control unit 12020 controls the operation of various devices equipped in the vehicle body according to various programs. For example, the body system control unit 12020 functions as a control device for a keyless entry system, a smart key system, a power window device, or various lamps such as headlamps, backup lamps, brake lamps, turn signals, and fog lamps. In this case, radio waves transmitted from a portable device that serves as a key or signals from various switches can be input to the body system control unit 12020. The body system control unit 12020 receives these radio waves or signals and controls the vehicle's door lock device, power window device, lamps, etc.

[0334] The outside-vehicle information detection unit 12030 detects information outside the vehicle equipped with the vehicle control system 12000. For example, an imaging unit 12031 is connected to the outside-vehicle information detection unit 12030. The outside-vehicle information detection unit 12030 causes the imaging unit 12031 to capture images outside the vehicle and receives the captured images. The outside-vehicle information detection unit 12030 may perform object detection processing or distance detection processing for people, cars, obstacles, signs, characters on the road surface, etc. based on the received images.

[0335] The imaging unit 12031 is an optical sensor that receives light and outputs an electrical signal corresponding to the amount of light received. The imaging unit 12031 can output the electrical signal as an image or as distance measurement information. The light received by the imaging unit 12031 may be visible light or invisible light such as infrared light.

[0336] The in-vehicle information detection unit 12040 detects information inside the vehicle. For example, a driver state detection unit 12041 that detects the state of the driver is connected to the in-vehicle information detection unit 12040. The driver state detection unit 12041 includes, for example, a camera that captures an image of the driver, and the in-vehicle information detection unit 12040 may calculate the degree of fatigue or concentration of the driver based on the detection information input from the driver state detection unit 12041, or may determine whether the driver is dozing off.

[0337] The microcomputer 12051 can calculate control target values ​​for the driving force generating device, steering mechanism, or braking device based on the information inside and outside the vehicle acquired by the outside-vehicle information detection unit 12030 or the inside-vehicle information detection unit 12040, and output control commands to the drive system control unit 12010. For example, the microcomputer 12051 can perform cooperative control aimed at realizing the functions of an ADAS (Advanced Driver Assistance System), including vehicle collision avoidance or impact mitigation, following driving based on the distance between vehicles, maintaining vehicle speed, vehicle collision warning, vehicle lane departure warning, etc.

[0338] In addition, the microcomputer 12051 can perform cooperative control for the purpose of autonomous driving, which allows the vehicle to travel autonomously without relying on driver operation, by controlling the driving force generating device, steering mechanism, braking device, etc. based on information about the surroundings of the vehicle obtained by the outside vehicle information detection unit 12030 or the inside vehicle information detection unit 12040.

[0339] Furthermore, the microcomputer 12051 can output a control command to the body system control unit 12020 based on the information outside the vehicle acquired by the outside information detection unit 12030. For example, the microcomputer 12051 can control the headlamps according to the position of a preceding vehicle or an oncoming vehicle detected by the outside information detection unit 12030, and perform cooperative control aimed at preventing glare, such as switching from high beams to low beams.

[0340] The audio / video output unit 12052 transmits at least one of audio and video output signals to an output device capable of visually or audibly notifying information to vehicle occupants or the outside of the vehicle. In the example of Fig. 53, the output devices are exemplified by an audio speaker 12061, a display unit 12062, and an instrument panel 12063. The display unit 12062 may include, for example, at least one of an on-board display and a head-up display.

[0341] FIG. 54 is a diagram showing an example of the installation position of the imaging unit 12031.

[0342] In FIG. 54, the imaging unit 12031 includes imaging units 12101, 12102, 12103, 12104, and 12105.

[0343] The imaging units 12101, 12102, 12103, 12104, and 12105 are provided, for example, at positions such as the front nose, side mirrors, rear bumper, back door, and the top of the windshield inside the vehicle cabin of the vehicle 12100. The imaging unit 12101 provided on the front nose and the imaging unit 12105 provided on the top of the windshield inside the vehicle cabin mainly acquire images of the front of the vehicle 12100. The imaging units 12102 and 12103 provided on the side mirrors mainly acquire images of the sides of the vehicle 12100. The imaging unit 12104 provided on the rear bumper or back door mainly acquires images of the rear of the vehicle 12100. The imaging unit 12105 provided on the top of the windshield inside the vehicle cabin is mainly used to detect preceding vehicles, pedestrians, obstacles, traffic lights, traffic signs, lanes, etc.

[0344] 54 shows an example of the imaging ranges of the imaging units 12101 to 12104. Imaging range 12111 indicates the imaging range of the imaging unit 12101 provided on the front nose, imaging ranges 12112 and 12113 indicate the imaging ranges of the imaging units 12102 and 12103 provided on the side mirrors, respectively, and imaging range 12114 indicates the imaging range of the imaging unit 12104 provided on the rear bumper or back door. For example, by overlaying the image data captured by the imaging units 12101 to 12104, an overhead image of the vehicle 12100 viewed from above can be obtained.

[0345] At least one of the image capturing units 12101 to 12104 may have a function of acquiring distance information. For example, at least one of the image capturing units 12101 to 12104 may be a stereo camera made up of multiple image capturing elements, or may be an image capturing element having pixels for phase difference detection.

[0346] For example, based on the distance information obtained from the imaging units 12101 to 12104, the microcomputer 12051 can calculate the distance to each three-dimensional object within the imaging ranges 12111 to 12114 and the change in this distance over time (relative speed with respect to the vehicle 12100), thereby extracting as a preceding vehicle, in particular, the three-dimensional object that is the closest three-dimensional object on the path of the vehicle 12100 and traveling in approximately the same direction as the vehicle 12100 at a predetermined speed (e.g., 0 km / h or higher). Furthermore, the microcomputer 12051 can set a vehicle-to-vehicle distance to be maintained in advance in front of the preceding vehicle, and perform automatic braking control (including follow-up stop control), automatic acceleration control (including follow-up start control), etc. In this way, cooperative control can be performed for the purpose of autonomous driving, which allows the vehicle to travel autonomously without relying on driver operation.

[0347] For example, the microcomputer 12051 classifies and extracts three-dimensional object data regarding three-dimensional objects into two-wheeled vehicles, ordinary vehicles, large vehicles, pedestrians, utility poles, and other three-dimensional objects based on distance information obtained from the imaging units 12101 to 12104, and can use the data for automatic obstacle avoidance. For example, the microcomputer 12051 distinguishes obstacles around the vehicle 12100 into obstacles that are visible to the driver of the vehicle 12100 and obstacles that are difficult to see. The microcomputer 12051 then determines a collision risk that indicates the risk of collision with each obstacle, and when the collision risk is equal to or greater than a set value and a collision is possible, the microcomputer 12051 can provide driving assistance for collision avoidance by outputting an alarm to the driver via the audio speaker 12061 or the display unit 12062, or by performing forced deceleration or avoidance steering via the drive system control unit 12010.

[0348] At least one of the image capturing units 12101 to 12104 may be an infrared camera that detects infrared rays. For example, the microcomputer 12051 can recognize a pedestrian by determining whether a pedestrian is present in the images captured by the image capturing units 12101 to 12104. Such pedestrian recognition is performed, for example, by extracting feature points from the images captured by the image capturing units 12101 to 12104 as infrared cameras and performing pattern matching on a series of feature points that indicate the outline of an object to determine whether the object is a pedestrian. When the microcomputer 12051 determines that a pedestrian is present in the images captured by the image capturing units 12101 to 12104 and recognizes the pedestrian, the audio / image output unit 12052 controls the display unit 12062 to superimpose a rectangular outline on the recognized pedestrian for emphasis. The audio / image output unit 12052 may also control the display unit 12062 to display an icon or the like indicating the pedestrian at a desired position.

[0349] An example of a vehicle control system to which the technology according to the present disclosure can be applied has been described above. The technology according to the present disclosure can be applied to, for example, the imaging unit 12031 of the above-described configuration. Specifically, the imaging device of FIG. 1 can be applied to the imaging unit 12031. By applying the technology according to the present disclosure to the imaging unit 12031, it is possible to increase the accuracy of edge detection, improve image recognition accuracy, and improve the reliability of the vehicle control system.

[0350] Note that the above-described embodiment shows an example for realizing the present technology, and the matters in the embodiment and the matters specifying the invention in the claims correspond to each other. Similarly, the matters specifying the invention in the claims and the matters in the embodiment of the present technology having the same name correspond to each other. However, the present technology is not limited to the embodiment, and can be realized by applying various modifications to the embodiment within the scope of the gist thereof.

[0351] The effects described in this specification are merely examples and are not limiting, and other effects may also be obtained.

[0352] The present technology may also be configured as follows: (1) A sensing device comprising: a gain control circuit that performs gain control to increase or decrease at least one of a pair of pixel signals by a predetermined gain; an offset control circuit that performs offset control to superimpose a predetermined offset on at least one of the pair of pixel signals; and a comparator that compares the pair of pixel signals that have been subjected to the gain control and the offset control and outputs a comparison result. (2) The sensing device according to (1), further comprising: a timing control circuit that sequentially selects a plurality of combinations, each including an offset value and a gain value, and sets the combinations in the gain control circuit and the offset control circuit. (3) The sensing device according to (2), further comprising: a plurality of latch circuits that hold the comparison results corresponding to the plurality of combinations. (4) The timing control circuit sets the gain values ​​in ascending order, and the timing control circuit stops the comparator when an edge is detected. (5) The sensing device according to any one of (1) to (4), wherein the gain control circuit comprises: a first capacitive element, a second capacitive element, a first switch that opens and closes a path between the first capacitive element and a vertical signal line that transmits one of the pair of pixel signals, and a second switch that opens and closes a path between the second capacitive element and a vertical signal line that transmits one of the pair of pixel signals. (6) The sensing device according to (5), wherein the other ends of the first and second capacitive elements are connected to the comparator. (7) The sensing device according to (5), wherein the other ends of the first and second capacitive elements are connected to a ground node. (8) The sensing device according to any one of (1) to (4), wherein the gain control circuit comprises: an amplifier, a capacitive element having one end connected to an output terminal of the amplifier, and a switch that opens and closes a path between an input terminal of the amplifier and the other end of the capacitive element.(9) The sensing device according to any one of (1) to (8), wherein the offset control circuit comprises: a capacitive element; an offset-side switch that opens and closes a path between an input node of the offset and one end of the capacitive element; and a pixel-side switch that opens and closes a path between a vertical signal line that transmits one of the pair of pixel signals and one end of the capacitive element. (10) The sensing device according to (9), wherein the offset includes first and second offsets, and the offset-side switch includes a first offset-side switch that opens and closes the path between an input node of the first offset and one end of the capacitive element and a second offset-side switch that opens and closes the path between an input node of the second offset and one end of the capacitive element. (11) The sensing device according to any one of (1) to (10), further comprising: a reference signal generation unit that generates a predetermined reference signal; a reference-side switch that opens and closes a path between the reference signal generation unit and the comparator; and a pixel-side switch that opens and closes paths between the gain control circuit, the offset control circuit, and a vertical signal line that transmits the pixel signal. (12) The sensing device according to any one of (1) to (11), further comprising: a pixel array unit in which a pair of pixels that generate the pair of pixel signals is arranged; and a signal processing circuit that processes the comparison result. (13) The sensing device according to (12), wherein the pixel array unit, the gain control circuit, the offset control circuit, and the comparator are arranged on a predetermined pixel chip, and the signal processing circuit is arranged on a predetermined circuit chip. (14) The sensing device according to (12), wherein the pixel array unit is arranged on a predetermined pixel chip, and the gain control circuit, the offset control circuit, the comparator, and the signal processing circuit are arranged on a predetermined circuit chip. (15) The sensing device according to any one of (1) to (14), further comprising an error cancellation circuit that cancels an error in the output signal of the comparator. (16) The sensing device according to (15), wherein the error cancellation circuit superimposes a predetermined compensation offset on the output signal.(17) The sensing device according to (15), further comprising: a replica circuit having the same circuit configuration as the comparator, wherein the error cancellation circuit holds an input offset of the replica circuit and superimposes the held input offset as a compensation offset on one of a pair of input signals of the comparator, the comparators are arranged for each pixel column, and the error cancellation circuit is connected in common to each of the comparators. (18) An electronic device comprising: a gain control circuit that performs control to increase or decrease at least one of a pair of pixel signals by a predetermined gain as gain control; an offset control circuit that performs control to superimpose a predetermined offset on at least one of the pair of pixel signals as offset control; a comparator that compares the pair of pixel signals that have been subjected to the gain control and the offset control and outputs a comparison result; and a signal processing circuit that processes the comparison result. (19) A method for controlling a sensing device, comprising: a gain control procedure for performing gain control to increase or decrease at least one of a pair of pixel signals by a predetermined gain; an offset control procedure for performing offset control to superimpose a predetermined offset on at least one of the pair of pixel signals; and a comparison procedure for comparing the pair of pixel signals subjected to the gain control and the offset control and outputting a comparison result.

[0353] 100 Imaging device 110 Optical unit 120 DSP circuit 130 Display unit 140 Operation unit 150 Bus 160 Frame memory 170 Storage unit 180 Power supply unit 200 Image sensor 201 Pixel chip 202 Circuit chip 210 Vertical scanning circuit 220 DAC 230 Timing control circuit 240 Pixel array unit 250 Pixel 251 Photoelectric conversion element 252 Transfer transistor 253 Reset transistor 254 Floating diffusion layer 255 Amplification transistor 256 Selection transistor 260 Horizontal scanning circuit 290 Signal processing circuit 300 Column signal processing circuit 301 North column signal processing circuit 302 South column signal processing circuit 310 Constant current source 320 ADC 331 to 334, 411 to 416, 421 to 426, 431 to 434, 441 to 443, 641, 642 Switches 341, 342 Counter 400 Edge detection unit 405, 406, 407, 417 to 419, 427 to 429, 435, 445, 461 to 463, 491, 493, 631, 661 to 663 Capacitor elements 410, 410-1, 410-2, 420, 420-1, 420-2 Gain control circuits 430, 430-1, 430-2, 440, 440-1, 440-2 Offset control circuits 450, 465 Comparators 451 to 455, 494, 621 to 623, 651 to 655 pMOS transistors 456 to 460, 611 to 614, 656 to 660 nMOS transistors 470 edge determination circuit 481 to 486 latch circuit 492, 643 amplifier 511 on-chip lens 512 color filter 520 wiring layer 530 substrate 600, 601 error cancellation circuit 650 replica circuit 12031 imaging unit

Claims

1. A sensing device comprising: a gain control circuit that performs gain control to increase or decrease at least one of a pair of pixel signals by a predetermined gain; an offset control circuit that performs offset control to superimpose a predetermined offset on at least one of the pair of pixel signals; and a comparator that compares the pair of pixel signals that have been subjected to the gain control and the offset control and outputs the comparison result.

2. The sensing device according to claim 1, further comprising a timing control circuit that sequentially selects a plurality of combinations each including an offset value and a gain value and sets the combinations in the gain control circuit and the offset control circuit.

3. The sensing device according to claim 2, further comprising a plurality of latch circuits for holding the comparison results corresponding to the plurality of combinations, respectively.

4. The sensing device according to claim 2, wherein the timing control circuit sets the gain values ​​in ascending order and stops the comparator when an edge is detected.

5. The sensing device according to claim 1, wherein the gain control circuit comprises: a first capacitance element; a second capacitance element; a first switch that opens and closes a path between the first capacitance element and a vertical signal line that transmits one of the pair of pixel signals; and a second switch that opens and closes a path between the second capacitance element and a vertical signal line that transmits one of the pair of pixel signals.

6. The sensing device according to claim 5, wherein the other ends of the first and second capacitive elements are connected to the comparator.

7. The sensing device according to claim 5, wherein the other end of each of the first and second capacitive elements is connected to a ground node.

8. The sensing device according to claim 1, wherein the gain control circuit comprises: an amplifier; a capacitance element having one end connected to an output terminal of the amplifier; and a switch that opens and closes a path between the input terminal of the amplifier and the other end of the capacitance element.

9. The sensing device according to claim 1, wherein the offset control circuit comprises: a capacitance element; an offset-side switch that opens and closes a path between an input node of the offset and one end of the capacitance element; and a pixel-side switch that opens and closes a path between a vertical signal line that transmits one of the pair of pixel signals and one end of the capacitance element.

10. The sensing device according to claim 9, wherein the offset includes a first and a second offset, and the offset-side switches include a first offset-side switch that opens and closes a path between an input node of the first offset and one end of the capacitance element, and a second offset-side switch that opens and closes a path between an input node of the second offset and one end of the capacitance element.

11. The sensing device according to claim 1, further comprising: a reference signal generation unit that generates a predetermined reference signal; a reference-side switch that opens and closes a path between the reference signal generation unit and the comparator; and a pixel-side switch that opens and closes a path between the gain control circuit and the offset control circuit and a vertical signal line that transmits the pixel signal.

12. The sensing device according to claim 1, further comprising: a pixel array section in which a pair of pixels that generate the pair of pixel signals is arranged; and a signal processing circuit that processes the comparison result.

13. The sensing device according to claim 12, wherein the pixel array section, the gain control circuit, the offset control circuit and the comparator are arranged on a predetermined pixel chip, and the signal processing circuit is arranged on a predetermined circuit chip.

14. The sensing device according to claim 12, wherein the pixel array section is arranged on a predetermined pixel chip, and the gain control circuit, the offset control circuit, the comparator, and the signal processing circuit are arranged on a predetermined circuit chip.

15. The sensing device according to claim 1, further comprising an error cancellation circuit that cancels an error in the output signal of the comparator.

16. The sensing device according to claim 15, wherein the error cancellation circuit superimposes a predetermined compensation offset on the output signal.

17. The sensing device according to claim 15, further comprising a replica circuit having the same circuit configuration as said comparator, wherein said error cancellation circuit holds an input offset of said replica circuit and superimposes said held input offset as a compensation offset on one of a pair of input signals of said comparator, said comparators being arranged for each column of pixels, and said error cancellation circuit being connected in common to each of said comparators.

18. An electronic device comprising: a gain control circuit that performs gain control to increase or decrease at least one of a pair of pixel signals by a predetermined gain; an offset control circuit that performs offset control to superimpose a predetermined offset on at least one of the pair of pixel signals; a comparator that compares the pair of pixel signals that have been subjected to the gain control and the offset control and outputs a comparison result; and a signal processing circuit that processes the comparison result.

19. A method for controlling a sensing device, comprising: a gain control procedure for performing gain control to increase or decrease at least one of a pair of pixel signals by a predetermined gain; an offset control procedure for performing offset control to superimpose a predetermined offset on at least one of the pair of pixel signals; and a comparison procedure for comparing the pair of pixel signals that have been subjected to the gain control and the offset control and outputting a comparison result.

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