Display device and manufacturing method therefor

Abstract

The present invention relates to a display device capable of minimizing a defect rate and image quality deterioration, and a manufacturing method therefor, in which at least one of a drain electrode of a 1-2 transistor and a first data connection electrode is cut, a second data connection electrode is cut, and the second data connection electrode and a first data line are connected to each other.

Description

Display device and method for manufacturing the same

[0001] The present invention relates to a display device, and more particularly, to a display device capable of minimizing defect rate and image quality degradation, and a method for manufacturing the same.

[0002] Organic light-emitting diode (OLED) displays (OLEDs) are self-luminous and, unlike liquid crystal displays (LCDs), do not require a separate light source, allowing for reduced thickness and weight. Furthermore, OLEDs exhibit high-quality characteristics, such as low power consumption, high brightness, and fast response times, making them attractive as next-generation display devices for TVs, monitors, and portable electronic devices.

[0003] The purpose of the present invention is to provide a display device and a manufacturing method thereof in which the defect rate and image quality deterioration can be minimized.

[0004] The tasks of the present invention are not limited to the tasks mentioned above, and other technical tasks not mentioned will be clearly understood by those skilled in the art from the description below.

[0005] According to one embodiment of the present invention for achieving the above object, a display device comprises: a first light-emitting element; a 1-1 transistor including a drain electrode connected to a driving voltage line and a source electrode connected to a first anode electrode of the first light-emitting element; a 1-2 transistor including a gate electrode connected to a first scan line, a drain electrode connected to a first data line, and a source electrode connected to the gate electrode of the 1-1 transistor; a 1-3 transistor including a gate electrode connected to a second scan line, a drain electrode connected to the first anode electrode of the first light-emitting element, and a source electrode connected to an initialization voltage line; a second light-emitting element; a 2-1 transistor including a drain electrode connected to a driving voltage line and a source electrode connected to a second anode electrode of the second light-emitting element; a 2-2 transistor including a gate electrode connected to the first scan line, a drain electrode connected to a second data line, and a source electrode connected to the gate electrode of the 2-1 transistor; A 2-3 transistor including a gate electrode connected to the second scan line, a drain electrode connected to the second anode electrode of the second light-emitting element, and a source electrode connected to the initialization voltage line; a first data connection electrode connected to the first data line and the drain electrode of the 1-2 transistor; and a second data connection electrode connected to the second data line and the drain electrode of the 2-2 transistor, wherein at least one of the drain electrode of the 1-2 transistor and the first data connection electrode is cut off, the second data connection electrode is cut off, and the second data connection electrode and the first data line are connected to each other.

[0006] In addition, a display device according to an embodiment of the present invention for achieving the above object comprises: a first light-emitting element; a 1-1 transistor including a drain electrode connected to a driving voltage line and a source electrode connected to a first anode electrode of the first light-emitting element; a 1-2 transistor including a gate electrode connected to a first scan line, a drain electrode connected to a first data line, and a source electrode connected to the gate electrode of the 1-1 transistor; a 1-3 transistor including a gate electrode connected to a second scan line, a drain electrode connected to the first anode electrode of the first light-emitting element, and a source electrode connected to an initialization voltage line; a second light-emitting element; a 2-1 transistor including a drain electrode connected to a driving voltage line and a source electrode connected to a second anode electrode of the second light-emitting element; a 2-2 transistor including a gate electrode connected to the first scan line, a drain electrode connected to a second data line, and a source electrode connected to the gate electrode of the 2-1 transistor; A 2-3 transistor including a gate electrode connected to the second scan line, a drain electrode connected to the second anode electrode of the second light-emitting element, and a source electrode connected to the initialization voltage line; a first light-blocking layer overlapping the gate electrode of the 1-1 transistor; a first anode connection electrode overlapping the gate electrode of the 1-1 transistor and connected to the first light-blocking layer and the drain electrode of the 1-3 transistor; and a second anode connection electrode overlapping the gate electrode of the 2-1 transistor and connected to the second anode electrode, and a dummy electrode extending from the second anode connection electrode and overlapping the first light-blocking layer.

[0007] In addition, a method for manufacturing a display device according to an embodiment of the present invention for achieving the above object comprises the steps of forming, on a substrate, a 1-1 transistor including a drain electrode connected to a driving voltage line; a 1-2 transistor including a gate electrode connected to a first scan line, a drain electrode connected to a first data line, and a source electrode connected to the gate electrode of the 1-1 transistor; a 1-3 transistor including a gate electrode connected to a second scan line and a source electrode connected to an initialization voltage line; a 2-1 transistor including a drain electrode connected to a driving voltage line; a 2-2 transistor including a gate electrode connected to the first scan line, a drain electrode connected to a second data line, and a source electrode connected to the gate electrode of the 2-1 transistor; and a 2-3 transistor including a gate electrode connected to the second scan line and a source electrode connected to the initialization voltage line; forming a first insulating layer (ITL) on the 1-1 transistor, the 1-2 transistor, the 1-3 transistor, the 2-1 transistor, the 2-2 transistor, and the 2-3 transistor; The method comprises: forming a first data connection electrode connected to the first data line and the drain electrode of the 1-2 transistor on the first insulating layer; forming a second data connection electrode connected to the second data line and the drain electrode of the 2-2 transistor; forming a second insulating layer on the first data connection electrode and the second data connection electrode; cutting at least one of the drain electrode of the 1-2 transistor and the first data connection electrode; cutting the second data connection electrode; and connecting the second data connection electrode and the first data line to each other.

[0008] In addition, a method for manufacturing a display device according to an embodiment of the present invention for achieving the above object comprises the steps of: forming, on a substrate, a 1-1 transistor including a drain electrode connected to a driving voltage line; a 1-2 transistor including a gate electrode connected to a first scan line, a drain electrode connected to a first data line, and a source electrode connected to the gate electrode of the 1-1 transistor; a 1-3 transistor including a gate electrode connected to a second scan line and a source electrode connected to an initialization voltage line; a 2-1 transistor including a drain electrode connected to the driving voltage line; a 2-2 transistor including a gate electrode connected to the first scan line, a drain electrode connected to a second data line, and a source electrode connected to the gate electrode of the 2-1 transistor; a 2-3 transistor including a gate electrode connected to the second scan line and a source electrode connected to the initialization voltage line; and a first light-blocking layer overlapping the gate electrode of the 1-1 transistor; The method comprises the steps of forming a first insulating layer (ITL) on the first-1 transistor, the first-2 transistor, the first-3 transistor, the second-1 transistor, the second-2 transistor, the second-3 transistor and the first light-blocking layer; forming a first anode connection electrode on the first insulating layer, the first anode connection electrode overlapping the gate electrode of the first-1 transistor and connected to the first light-blocking layer and the drain electrode of the first-3 transistor; a second anode connection electrode overlapping the gate electrode of the second-1 transistor; and a dummy electrode extending from the second anode connection electrode and overlapping the first light-blocking layer.

[0009] Specific details of other embodiments are included in the detailed description and drawings.

[0010] According to the display device of the present invention, defect rates and image quality degradation can be minimized. For example, the visibility problem of defective pixels can be resolved by repairing defective pixels with high visibility through the pixel circuit of normal pixels with low visibility.

[0011] Meanwhile, the effects that can be obtained from the present invention are not limited to the effects mentioned above, and other effects that are not mentioned can be clearly understood by a person having ordinary skill in the technical field to which the present invention belongs from the description below.

[0012] FIG. 1 is a plan view schematically illustrating a portion of a display device according to one embodiment of the present invention.

[0013] Figure 2 is a circuit diagram of a display device according to one embodiment.

[0014] Figures 3 to 5 are plan views of a display device according to one embodiment.

[0015] Figure 6 is a cross-sectional view taken along line I-I' of Figure 3.

[0016] Fig. 7 is a circuit diagram for explaining a method of manufacturing a display device according to one embodiment.

[0017] FIGS. 8 to 18 are array drawings for explaining a method of manufacturing a display device according to one embodiment.

[0018] FIGS. 19 and 20 are drawings for explaining a repair process of a display device according to another embodiment.

[0019] FIGS. 21 to 23 are drawings for explaining a method of manufacturing a display device according to another embodiment.

[0020] FIGS. 24 and 25 are drawings for explaining a repair process of a display device according to another embodiment.

[0021] FIGS. 26 to 31 are drawings for explaining a method of manufacturing a display device according to another embodiment.

[0022] FIGS. 32 to 36 are drawings for explaining a method of manufacturing a display device according to another embodiment.

[0023] FIGS. 37 to 40 are drawings for explaining a method of manufacturing a display device according to another embodiment.

[0024] Fig. 41 is a circuit diagram of a display device according to one embodiment.

[0025] Figure 42 is a plan view of a display device according to one embodiment.

[0026] Fig. 43 is a circuit diagram for explaining a method of manufacturing a display device according to one embodiment.

[0027] FIGS. 44 to 47 are drawings for explaining a method of manufacturing a display device according to one embodiment.

[0028] Fig. 48 is a circuit diagram of a display device according to one embodiment.

[0029] Figures 49 to 51 are plan views of a display device according to one embodiment.

[0030] Figure 52 is a cross-sectional view taken along line A1-A1' of Figure 49.

[0031] Fig. 53 is a circuit diagram for explaining a method of manufacturing a display device according to one embodiment.

[0032] FIGS. 54 to 64 are array drawings for explaining a method of manufacturing a display device according to one embodiment.

[0033] The advantages and features of the present invention, and the methods for achieving them, will become clearer with reference to the embodiments described in detail below together with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but may be implemented in various different forms. These embodiments are provided solely to ensure that the disclosure of the present invention is complete and to fully inform those skilled in the art of the scope of the invention, and the present invention is defined solely by the scope of the claims.

[0034] When elements or layers are referred to as being "on" another element or layer, this includes both cases where the other element or layer is directly on top of the other element or layer, or where the other layer or layer is interposed therebetween. Like reference numerals refer to like elements throughout the specification. The shapes, sizes, ratios, angles, numbers, etc. disclosed in the drawings for explaining the embodiments are illustrative and therefore the present invention is not limited to the matters illustrated.

[0035] Although terms like "first" and "second" are used to describe various components, these components are not limited by these terms. These terms are used merely to distinguish one component from another. Therefore, it should be understood that a "first" component referred to below may also be a "second" component within the technical scope of the present invention.

[0036] The features of each of the various embodiments of the present invention can be partially or wholly combined or combined with each other, and various technical connections and operations are possible, and each embodiment can be implemented independently of each other or implemented together in a related relationship.

[0037] Specific embodiments are described below with reference to the attached drawings.

[0038] FIG. 1 is a plan view schematically illustrating a portion of a display device (100) according to one embodiment of the present invention.

[0039] A display device (100) according to one embodiment of the present invention may include a display panel (110), as illustrated in FIG. 1. The display device (100) may be any device that includes the display panel (110). For example, the display device (100) may be a variety of products, such as a smartphone, a tablet, a laptop, a television, or a billboard. The display panel (110) may include a display area (DA) and a non-display area (NDA) outside the display area (DA).

[0040] The display area (DA) is a portion that displays an image, and a plurality of pixels may be arranged in the display area (DA). When viewed from a direction approximately perpendicular to the display panel (110) (e.g., the third direction (DR3)), the display area (DA) may have various shapes, such as an oval, a polygon, or a shape of a specific shape.

[0041] A display panel (110) of a display device (100) according to one embodiment may have a display area (DA) having a shape in which a length in a first direction (DR1), which is a horizontal direction, is longer than a length in a second direction (DR2), which is a vertical direction. That the display panel (110) has a display area (DA) of such a shape can be understood as meaning that a substrate included in the display panel (110) has a display area (DA) of such a shape. Various driving circuits may be located in a peripheral area (PA) of the display panel (110).

[0042] Figure 2 is a circuit diagram of a display device (100) according to one embodiment.

[0043] A display device (100) according to one embodiment may include a plurality of pixels (PX1, PX2, PX3). FIG. 2 illustrates three adjacent pixels (PX1, PX2, PX3) among the plurality of pixels.

[0044] As illustrated in FIG. 2, the plurality of pixels (PX1, PX2, PX3) may include a first pixel (PX1), a second pixel (PX2), and a third pixel (PX3). Each of the first pixel (PX1), the second pixel (PX2), and the third pixel (PX3) may include a plurality of transistors, at least one capacitor, and at least one light emitting diode (LED) as a light emitting element.

[0045] For example, the first pixel (PX1) may include a 1-1 transistor (T11; hereinafter, an 11th transistor (T11)), a 1-2 transistor (T12; hereinafter, a 12th transistor (T12)), a 1-3 transistor (T13; hereinafter, a 13th transistor (T13)), a first capacitor (Cst1), and a first light-emitting element (ED1).

[0046] The second pixel (PX2) may include a 2-1 transistor (T21; hereinafter, a 21st transistor (T21)), a 2-2 transistor (T22; hereinafter, a 22nd transistor (T22)), a 2-3 transistor (T23; hereinafter, a 23rd transistor (T23)), a second capacitor (Cst2), and a second light-emitting element (ED2).

[0047] The third pixel (PX3) may include a third-first transistor (T31; hereinafter, the 31st transistor (T31)), a third-second transistor (T32; hereinafter, the 32nd transistor (T32)), a third-third transistor (T33; hereinafter, the 3-3rd transistor (T33)), a third capacitor (Cst3), and a third light-emitting element (ED3).

[0048] The first light-emitting element (ED1), the second light-emitting element (ED2), and the third light-emitting element (ED3) can provide light of different colors. For example, the first light-emitting element (ED1) can include a light-emitting layer that provides green light, the second light-emitting element (ED2) can include a light-emitting layer that provides red light, and the third light-emitting element (ED3) can include a light-emitting layer that provides blue light. However, the present invention is not limited thereto. For example, the first light-emitting element (ED1) can include a light-emitting layer that provides red light or blue light, the second light-emitting element (ED2) can include a light-emitting layer that provides green light or blue light, and the third light-emitting element (ED3) can include a light-emitting layer that provides blue light or green light.

[0049] The first pixel (PX1), the second pixel (PX2), and the third pixel (PX3) may have the same configuration. Hereinafter, the eleventh transistor (T11), the twelfth transistor (T12), the thirteenth transistor (T13), the first capacitor (Cst1), and the first light-emitting element (ED1) included in the first pixel (PX1) will be described as representative examples.

[0050] A gate electrode of an eleventh transistor (T11) is connected to a first electrode of a capacitor (Cst), a drain electrode of the eleventh transistor (T11) is connected to a driving voltage line (VDL) that transmits a driving voltage (ELVDD), and a source electrode of the eleventh transistor (T11) can be connected to an anode electrode of a first light-emitting element (ED1) and a second electrode of a first capacitor (Cst1). The eleventh transistor (T11) can receive data voltages (Vd1, Vd2, Vd3) according to a switching operation of the twelfth transistor (T12) and supply a driving current to the first light-emitting element (ED1) according to a voltage stored in the first capacitor (Cst1).

[0051] A gate electrode of a twelfth transistor (T12) is connected to a first scan line (SCL) that transmits a first scan signal (SC), a drain electrode of the twelfth transistor (T12) is connected to a first data line (DL1) that can transmit a data voltage or a reference voltage, and a source electrode of the twelfth transistor (T12) can be connected to a first electrode of a first capacitor (Cst1) and a gate electrode of an eleventh transistor (T11). A plurality of data lines (DL1, DL2, DL3) can transmit different data voltages. For example, a first data line (DL1) can transmit a first data voltage (Vd1), a second data line (DL2) can transmit a second data voltage (Vd2), and a third data line (DL3) can transmit a third data voltage (Vd3). The twelfth transistor (T12, T22, T32) of each pixel (PX1, PX2, PX3) can be connected to different data lines (DL1, DL2, DL3). For example, the twelfth transistor (T12) can be connected to the first data line (DL1), the twentieth transistor (T22) can be connected to the second data line (DL2), and the thirtieth transistor (T32) can be connected to the third data line (DL3).

[0052] The 12th transistor (T12) can be turned on in response to a first scan signal (SC) from a first scan line (SCL) to transmit a reference voltage or a first data voltage (Vd1) to the gate electrode of the 11th transistor (T11) and the first electrode of the first capacitor (Cst1).

[0053] A gate electrode of a 13th transistor (T13) is connected to a second scan line (SSL) that transmits a second scan signal (SS) from a second scan line (SSL), a drain electrode of the 13th transistor (T13) is connected to a second electrode of a first capacitor (Cst1), a source electrode of an 11th transistor (T11), and an anode electrode of a first light-emitting element (ED1), and the source electrode of the 13th transistor (T13) can be connected to an initialization voltage line (VIL) that transmits an initialization voltage (INIT). The 13th transistor (T13) is turned on according to the second scan signal (SS) to transmit the initialization voltage (INIT) to the anode electrode of the first light-emitting element (ED1) and the second electrode of the first capacitor (Cst1), thereby initializing a voltage of the anode electrode of the first light-emitting element (ED1).

[0054] A first electrode of a first capacitor (Cst1) is connected to a gate electrode of an eleventh transistor (T11), and a second electrode of the first capacitor (Cst1) is connected to a drain electrode of a thirteenth transistor (T13) and an anode electrode of a first light-emitting element (ED1). A cathode electrode (CAT) of the first light-emitting element (ED1) is connected to a common voltage line (VSL) that transmits a common voltage (ELVSS).

[0055] The first light-emitting element (ED1) can emit light with a brightness according to the driving current generated by the 11th transistor (T11).

[0056] An example of the operation of the circuit illustrated in Fig. 1, particularly an example of the operation during one frame, is described as follows. Here, the case where the transistors (T11, T12, T13) are N-type channel transistors is described as an example, but the present invention is not limited thereto.

[0057] When a frame starts, a high-level first scan signal (SC) and a high-level second scan signal (SS) may be supplied in an initialization section to turn on the 12th transistor (T12) and the 13th transistor (T13). A reference voltage from the first data line (DL1) may be supplied to the gate electrode of the 11th transistor (T11) and one terminal of the first capacitor (Cst1) through the turned-on 12th transistor (T12), and an initialization voltage (INIT) may be supplied to the source electrode of the 11th transistor (T11) and the anode electrode of the first light-emitting element (ED1) through the turned-on 13th transistor (T13). Accordingly, the source electrode of the 11th transistor (T11) and the anode electrode of the first light-emitting element (ED1) may be initialized with the initialization voltage (INIT) during the initialization section. At this time, the difference between the reference voltage and the initialization voltage (INIT) can be stored in the first capacitor (Cst1).

[0058] Next, when the second scan signal (SS) becomes low level while the first scan signal (SC) is maintained at a high level in the sensing section, the 12th transistor (T12) may be maintained in a turned-on state and the 13th transistor (T13) may be turned off. Through the turned-on 12th transistor (T12), the gate electrode of the 11th transistor (T11) and one end of the first capacitor (Cst1) may be maintained at the reference voltage, and through the turned-off 13th transistor (T13), the source electrode of the 11th transistor (T11) and the anode electrode of the first light-emitting element (ED1) may be electrically separated from the initialization voltage line (VIL). Accordingly, the 11th transistor (T11) may be turned off when a current flows from the drain electrode to the source electrode and the voltage of the source electrode becomes "reference voltage - Vth". Vth represents the threshold voltage of the 11th transistor (T11). At this time, the voltage difference between the gate electrode and the source electrode of the 11th transistor (T11) is stored in the capacitor (Cst), and sensing of the threshold voltage (Vth) of the 11th transistor (T11) can be completed. By generating a compensated data signal based on the characteristic information sensed during the sensing period, the characteristic deviation of the 11th transistor (T11), which may be different for each pixel, can be externally compensated.

[0059] Next, when a high-level first scan signal (SC) is supplied and a low-level second scan signal (SS) is supplied in the data input section, the 12th transistor (T12) can be turned on and the 13th transistor (T13) can be turned off. The data voltage from each data line (DL1, DL2, DL3) is supplied to the gate electrode of each 11th transistor (T11, T21, T31) and one end of each capacitor (Cst1, Cst2, Cst3) through each of the turned-on 12th transistors (T12, T22, T32) of each pixel (PX1, PX2, PX3). At this time, the source electrode of each 11th transistor (T11, T21, T31) and the anode electrode of each light-emitting element (ED1, ED2, ED3) can maintain the potential in the sensing section almost as it is by each 11th transistor (T11, T21, T31) being turned off.

[0060] Next, each of the 11th transistors (T11, T21, T31) turned on by the data voltages transmitted to the gate electrode in the light-emitting section generates driving currents according to the corresponding data voltages, and each light-emitting element (ED1, ED2, ED3) can emit light by each driving current.

[0061] FIGS. 3 to 5 are plan views of a display device (100) according to one embodiment. For example, FIG. 3 may be a plan view of a display device (100) including first to third pixels (PX1 to PX3) of FIG. 2. FIG. 3 may include drawings related to the first pixel. FIG. 4 is the same drawing as FIG. 3, and FIG. 4 may include drawings related to the second pixel. FIG. 5 is the same drawing as FIG. 3, and FIG. 5 may include drawings related to the third pixel. FIG. 6 is a cross-sectional view taken along line II' of FIG. 3.

[0062] As illustrated in FIG. 6, the display device (100) may include a substrate (SUB), a thin film transistor layer (TFTL), a light emitting element layer (EMTL), and an encapsulation layer (ENC). On the substrate (SUB), the thin film transistor layer (TFTL), the light emitting element layer (EMTL), and the encapsulation layer (ENC) may be sequentially arranged along a third direction (DR3). Here, the thin film transistor layer (TFTL) may include the aforementioned eleventh transistors (T11, T21, T31), twelfth transistors (T12, T22, T22), and thirteenth transistors (T13, T23, T33).

[0063] The substrate (SUB) may be a rigid substrate (SUB) or a flexible substrate (SUB) that can be bent, folded, rolled, etc. The substrate (SUB) may be made of an insulating material such as glass, quartz, or polymer resin. Examples of polymeric materials include polyethersulfone (PES), polyacrylate (PA), polyarylate (PAR), polyetherimide (PEI), polyethylene napthalate (PEN), polyethylene terepthalate (PET), polyphenylene sulfide (PPS), polyallylate, polyimide (PI), polycarbonate (PC), cellulose triacetate (CAT), cellulose acetate propionate (CAP), or combinations thereof. Alternatively, the first substrate (SUB) may include a metallic material.

[0064] As illustrated in FIG. 6, a first pattern layer may be disposed on the substrate (SUB). The first pattern layer may include, for example, a first light-blocking layer (BML1), a second light-blocking layer (BML2), a third light-blocking layer (BML3), a first data line (DL1), a second data line (DL2), a third data line (DL3), a driving voltage line (VDL), and an initialization voltage line (VIL), as illustrated in FIGS. 3 to 6. As illustrated in FIG. 6, a driving voltage line (VDL), the first light-blocking layer (BML1), and the third data line (DL3) may be disposed on the substrate (SUB).

[0065] The first light-shielding layer (BML1) may be formed of, for example, a metal material such as chromium (Cr) or molybdenum (Mo), or black ink or black dye. Meanwhile, when the light-shielding layer is formed of a metal material, the light-shielding layer can receive a static electricity supply. As a result, the light-shielding layer does not electrically float, and the transistors on the light-shielding layer can have their electrical characteristics stabilized. The second light-shielding layer (BML2) and the third light-shielding layer (BML3) may be formed of the same material as the first light-shielding layer (BML1) described above.

[0066] The first data line (DL1), the second data line (DL2), the third data line (DL3), the driving voltage line (VDL), and the initialization voltage line (VIL) may each extend along the first direction (DR1). The first data line (DL1) may be arranged between the second data line (DL2) and the third data line (DL3). The first data line (DL1), the second data line (DL2), the third data line (DL3), the driving voltage line (VDL), and the initialization voltage line (VIL) may be made of the same material as the first light-blocking layer (BML1) described above.

[0067] According to one embodiment, as illustrated in FIG. 3, the first data line (DL1) may be arranged at the uppermost side, and the third data line (DL3) may be arranged at the lowermost side. For example, among the first to third data lines (DL3), the second data line (DL2) may be arranged farthest from the gate structure (e.g., the 12th gate electrode (G12), the 32nd gate electrode (G32), and the 22nd gate electrode (G22)), and the third data line (DL3) may be arranged closest to the gate structure.

[0068] A buffer layer (BF) may be disposed on the first pattern layer. For example, as in the example illustrated in FIG. 6, the buffer layer (BF) may be disposed on the driving voltage line (VDL), the first light-shielding layer (BML1), and the third data line (DL3). The buffer layer (BF) may be a film for protecting the transistors (T1-T3) of the thin film transistor layer (TFTL) and the light-emitting layer (EL) of the light-emitting element layer (EMTL) from moisture penetrating through the substrate (SUB) that is vulnerable to moisture permeation. The buffer layer (BF) may be formed of a plurality of inorganic films that are alternately laminated. For example, the buffer layer (BF) may be formed as a multi-film in which one or more inorganic films of a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, and an aluminum oxide layer are alternately laminated.

[0069] A second pattern layer may be placed on the buffer layer (BF). The second pattern layer may include, as illustrated in FIGS. 3 to 6, a 1-1 active layer (AC11; hereinafter, an 11th active layer (AC11)), a 1-2 active layer (AC12; hereinafter, a 12th active layer (AC12)), a 1-3 active layer (AC13; hereinafter, a 13th active layer (AC13)), a 2-1 active layer (AC21; hereinafter, a 21st active layer (AC21)), a 2-2 active layer (AC22; hereinafter, a 22nd active layer (AC22)), a 23rd active layer (AC23; hereinafter, a 23rd active layer (AC23)), a 3-1 active layer (AC31; hereinafter, a 31st active layer (AC31)), a 3-2 active layer (AC32; hereinafter, a 32nd active layer (AC32)), and a 3-3 active layer (AC33; hereinafter, a 33rd active layer (AC33)). As shown in the example in Fig. 6, the 11th active layer (AC11) can be placed on the buffer layer (BF).

[0070] The eleventh active layer (AC11), the twelfth active layer (AC12), the thirteenth active layer (AC13), the twenty-first active layer (AC21), the twenty-second active layer (AC22), the twenty-third active layer (AC23), the thirty-first active layer (AC31), the thirty-second active layer (AC32), and the thirty-third active layer (AC33) may overlap with the first pattern layer therebelow. For example, as illustrated in FIG. 6, the eleventh active layer (AC11) may be disposed on the buffer layer (BF) so as to overlap with the driving voltage line (VDL) and the first light-shielding layer (BML1).

[0071] The eleventh active layer (AC11) may be an active layer made of low temperature polycrystalline silicon (LTPS). In addition, the eleventh active layer (AC11) may be an oxide-based active layer. For example, the first active layer may be an oxide semiconductor including indium-gallium-zinc-oxide (IGZO) or indium-gallium-zinc-tin oxide (IGZTO). The twelfth active layer (AC12), the thirteenth active layer (AC13), the twenty-first active layer (AC21), the twenty-second active layer (AC22), the twenty-third active layer (AC23), the thirty-first active layer (AC31), the thirty-second active layer (AC32), and the thirty-third active layer (AC33) may each include the same material as the eleventh active layer (AC11) described above.

[0072] As illustrated in FIG. 6, a gate insulating layer (GI) may be disposed on the second pattern layer. For example, as illustrated in FIG. 6, a gate insulating layer (GI) may be disposed on the eleventh active layer (AC11).

[0073] The gate insulating layer (GI) may include at least one of tetraethoxysilane (TetraEthylOrthoSilicate, TEOS), silicon nitride (SiNx), and silicon oxide (SiO2). For example, the gate insulating layer (GI) may have a double-layer structure in which a silicon nitride film having a thickness of 40 nm and a tetraethoxysilane film having a thickness of 80 nm are sequentially laminated.

[0074] A third pattern layer may be arranged on the gate insulating layer (GI). The third pattern layer may include, as illustrated in FIGS. 3 to 6, a first-first gate electrode (G11; hereinafter, the eleventh gate electrode (G11)), a first-second gate electrode (G12; hereinafter, the twelfth gate electrode (G12)), a first-third gate electrode (G13; hereinafter, the thirteenth gate electrode (G13)), a second-first gate electrode (G21; hereinafter, the twenty-first gate electrode (G21)), a second-second gate electrode (G22; hereinafter, the twenty-second gate electrode (G22)), a second-third gate electrode (G23; hereinafter, the twenty-third gate electrode (G23)), a third-first gate electrode (G31; hereinafter, the thirty-first gate electrode (G31)), a third-second gate electrode (G32; hereinafter, the thirty-second gate electrode (G32)), and a third-third gate electrode (G33; hereinafter, the thirty-third gate electrode (G33)). As shown in the example in Fig. 6, an 11th gate electrode (G11), a 12th gate electrode (G12), a 22nd gate electrode (G22), and a 32nd gate electrode (G32) can be arranged on the gate insulating layer (GI).

[0075] The 11th gate electrode (G11) is disposed on the gate insulating layer (GI) to overlap with the 11th active layer (AC11) and the first light-blocking layer (BML1), the 12th gate electrode (G12) is disposed on the gate insulating layer (GI) to overlap with the 12th active layer (AC12), the 13th gate electrode (G13) is disposed on the gate insulating layer (GI) to overlap with the 13th active layer (AC13), the 21st gate electrode (G21) is disposed on the gate insulating layer (GI) to overlap with the 21st active layer (AC21) and the second light-blocking layer (BML2), the 22nd gate electrode (G22) is disposed on the gate insulating layer (GI) to overlap with the 22nd active layer (AC22), the 23rd gate electrode (G23) is disposed on the gate insulating layer (GI) to overlap with the 23rd active layer (AC23), and the 31st gate electrode (G31) is disposed on the 31st The active layer (AC31) and the third light-shielding layer (BML3) may be disposed on the gate insulating layer (GI), the 32nd gate electrode (G32) may be disposed on the gate insulating layer (GI) to overlap with the 32nd active layer (AC32), and the 33rd gate electrode (G33) may be disposed on the gate insulating layer (GI) to overlap with the 33rd active layer (AC33).

[0076] A first intermediate capacitor (CC1) of the first capacitor (Cst1) can be formed in the overlapping region of the 11th gate electrode (G11) and the first light-shielding layer (BML1).

[0077] The region overlapping with the 11th gate electrode (G11) among the 11th active layer (AC11) is the channel region (CH11) of the 11th transistor (T11), and the two regions of the 11th active layer (AC11) that do not overlap with the 11th gate electrode (G11) and are planarly separated by the 11th gate electrode (G11) may be the 1-1st drain electrode (D11; hereinafter, the 11th drain electrode (D11)) and the 1-1st source electrode (S11; hereinafter, the 11th source electrode (S11)) of the 11th transistor (T11), respectively.

[0078] The region overlapping with the 12th gate electrode (G12) among the 12th active layer (AC12) is the channel region of the 12th transistor (T12), and the two regions of the 12th active layer (AC12) that do not overlap with the 12th gate electrode (G12) and are planarly separated by the 12th gate electrode (G12) may be the 12th drain electrode (D12; hereinafter, the 12th drain electrode (D12)) and the 12th source electrode (S12; hereinafter, the 12th source electrode (S12)) of the 1-2nd transistor (T12), respectively.

[0079] The region overlapping the 13th gate electrode (G13) among the 13th active layer (AC13) is a channel region of the 13th transistor (T13), and two regions of the 13th active layer (AC13) that do not overlap the 13th gate electrode (G13) and are planarly separated by the 13th gate electrode (G13) may be the 1-3rd drain electrode (D13; hereinafter, the 13th drain electrode (D13)) and the 1-3rd source electrode (S13; hereinafter, the 13th source electrode (S13)) of the 13th transistor (T13), respectively.

[0080] A first intermediate capacitor of the second capacitor (Cst2) can be formed in the overlapping region of the 21st gate electrode (G21) and the second light-shielding layer (BML2).

[0081] The region of the 21st active layer (AC21) that overlaps with the 21st gate electrode (G21) is a channel region of the 21st transistor (T21), and two regions of the 21st active layer (AC21) that do not overlap with the 21st gate electrode (G21) and are planarly separated by the 21st gate electrode (G21) may be the 21st drain electrode (D21; hereinafter, the 21st drain electrode (D21)) and the 2-1st source electrode (S21; hereinafter, the 21st source electrode (S21)) of the 2-1st transistor (T21), respectively.

[0082] The region of the 22nd active layer (AC22) that overlaps with the 22nd gate electrode (G22) is a channel region of the 22nd transistor (T22), and two regions of the 22nd active layer (AC22) that do not overlap with the 22nd gate electrode (G22) and are planarly separated by the 22nd gate electrode (G22) may be the 2-2nd drain electrode (D22; hereinafter, the 22nd drain electrode (D22)) and the 2-2nd source electrode (S22; hereinafter, the 22nd source electrode (S22)) of the 22nd transistor (T22), respectively.

[0083] The region of the 23rd active layer (AC23) that overlaps with the 23rd gate electrode (G23) is a channel region of the 23rd transistor (T23), and two regions of the 23rd active layer (AC23) that do not overlap with the 23rd gate electrode (G23) and are planarly separated by the 23rd gate electrode (G23) may be the 2-3rd drain electrode (D23; hereinafter, the 23rd drain electrode (D23)) and the 2-3rd source electrode (S23; hereinafter, the 23rd source electrode (S23)) of the 23rd transistor (T23), respectively.

[0084] A first intermediate capacitor of the third capacitor (Cst3) can be formed in the overlapping region of the 31st gate electrode (G31) and the third light-shielding layer (BML3).

[0085] The region of the 31st active layer (AC31) that overlaps with the 31st gate electrode (G31) is a channel region of the 31st transistor (T31), and two regions of the 31st active layer (AC31) that do not overlap with the 31st gate electrode (G31) and are planarly separated by the 31st gate electrode (G31) may be the 3-1st drain electrode (D31; hereinafter, the 31st drain electrode (D31)) and the 3-1st source electrode (S31; hereinafter, the 31st source electrode (S31)) of the 31st transistor (T31), respectively.

[0086] The region of the 32nd active layer (AC32) that overlaps with the 32nd gate electrode (G32) is a channel region of the 32nd transistor (T32), and two regions of the 32nd active layer (AC32) that do not overlap with the 32nd gate electrode (G32) and are planarly separated by the 32nd gate electrode (G32) may be the 3-2nd drain electrode (D32; hereinafter, the 32nd drain electrode (D32)) and the 3-2nd source electrode (S32; hereinafter, the 32nd source electrode (S32)) of the 32nd transistor (T32), respectively.

[0087] The region of the 33rd active layer (AC33) that overlaps with the 33rd gate electrode (G33) is a channel region of the 33rd transistor (T33), and two regions of the 33rd active layer (AC33) that do not overlap with the 33rd gate electrode (G33) and are planarly separated by the 33rd gate electrode (G33) may be the 3-3rd drain electrode (D33; hereinafter, the 33rd drain electrode (D33)) and the 3-3rd source electrode (S33; hereinafter, the 33rd source electrode (S33)) of the 33rd transistor (T33), respectively.

[0088] The 12th gate electrode (G12), the 22nd gate electrode (G22), and the 32nd gate electrode (G32) may be formed integrally. The gate structure including the 12th gate electrode (G12), the 22nd gate electrode (G22), and the 32nd gate electrode (G32) may extend along the first direction (DR1).

[0089] The 13th gate electrode (G13), the 23rd gate electrode (G23), and the 33rd gate electrode (G33) may be formed integrally. The gate structure including the 13th gate electrode (G13), the 23rd gate electrode (G23), and the 33rd gate electrode (G33) may extend along the first direction (DR1).

[0090] An interlayer insulating layer (ITL) may be disposed on the third pattern layer. For example, as illustrated in FIG. 6, an interlayer insulating layer (ITL) may be disposed on the eleventh gate electrode (G11), the twelfth gate electrode (G12), the twenty-second gate electrode (G22), and the thirty-second gate electrode (G32).

[0091] The interlayer dielectric layer (ITL) may include an inorganic film, such as a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer. Alternatively, the interlayer dielectric layer (ITL) may include a plurality of inorganic films.

[0092] A fourth pattern layer may be disposed on the interlayer insulating layer (ITL). The fourth pattern layer may include, as illustrated in FIGS. 3 to 6, a first anode connection electrode (ACE1), a second anode connection electrode (ACE2), a third anode connection electrode (ACE3), a first gate connection electrode (GCE1), a second gate connection electrode (GCE2), a third gate connection electrode (GCE3), a first data connection electrode (DCE1), a second data connection electrode (DCE2), a third data connection electrode (DCE3), a first drive connection electrode (VCE1), a second drive connection electrode (VCE2), a third drive connection electrode (VCE3), an initialization connection electrode (ICE), a first scan line (SCL), and a second scan line (SSL). As in the example illustrated in FIG. 6, the first drive connection electrode (VCE1) and the first anode connection electrode (ACE1) may be disposed on the interlayer insulating layer (ITL).

[0093] The first anode connection electrode (ACE1) may overlap with the eleventh gate electrode (G11). A second intermediate capacitor (CC2) of the first capacitor (Cst1) may be formed in an overlapping region of the first anode connection electrode (ACE1) and the eleventh gate electrode (G11). The first capacitor (Cst1) may include a first intermediate capacitor (CC1) and a second intermediate capacitor (CC2). The first anode connection electrode (ACE1) may be connected to the eleventh source electrode (S11) of the eleventh transistor (T11) through a second contact hole (CT2) penetrating the interlayer insulating layer (ITL) and the gate insulating layer (GI). In addition, the first anode connection electrode (ACE1) may be connected to the first light-shielding layer (BML1) through a twelfth contact hole (CT12) penetrating the interlayer insulating layer (ITL), the gate insulating layer (GI), and the buffer layer (BF). Additionally, the first anode connection electrode (ACE1) can be connected to the 13th drain electrode (D13) of the 13th transistor (T13) through a fifth contact hole (CT5) penetrating the interlayer insulating layer (ITL) and the gate insulating layer (GI).

[0094] The second anode connection electrode (ACE2) may overlap with the twenty-first gate electrode (G21). A second intermediate capacitor of the second capacitor (Cst2) may be formed in an overlapping area of ​​the second anode connection electrode (ACE2) and the twenty-first gate electrode (G21). The second capacitor (Cst2) may include a first intermediate capacitor and a second intermediate capacitor. The second anode connection electrode (ACE2) may be connected to the twenty-first source electrode (S21) of the twenty-first transistor (T21) through a second contact hole (CT2') penetrating the interlayer insulating layer (ITL) and the gate insulating layer (GI). In addition, the second anode connection electrode (ACE2) may be connected to the second light-shielding layer (BML2) through a twelfth contact hole (CT12') penetrating the interlayer insulating layer (ITL), the gate insulating layer (GI), and the buffer layer (BF). Additionally, the second anode connection electrode (ACE2) can be connected to the 23rd drain electrode (D23) of the 23rd transistor (T23) through a fifth contact hole (CT5') penetrating the interlayer insulating layer (ITL) and the gate insulating layer (GI).

[0095] The third anode connection electrode (ACE3) may overlap with the 31st gate electrode (G31). A second intermediate capacitor of the third capacitor (Cst3) may be formed in an overlapping area of ​​the third anode connection electrode (ACE3) and the 31st gate electrode (G31). The third capacitor (Cst3) may include a first intermediate capacitor and a second intermediate capacitor. The third anode connection electrode (ACE3) may be connected to the 31st source electrode (S31) of the 31st transistor (T31) through a second contact hole (CT2'') penetrating the interlayer insulating layer (ITL) and the gate insulating layer (GI). In addition, the third anode connection electrode (ACE3) may be connected to the third light-shielding layer (BML3) through a twelfth contact hole (CT12'') penetrating the interlayer insulating layer (ITL), the gate insulating layer (GI), and the buffer layer (BF). Additionally, the third anode connection electrode (ACE3) can be connected to the 33rd drain electrode (D33) of the 33rd transistor (T33) through a fifth contact hole (CT5'') penetrating the interlayer insulating layer (ITL) and the gate insulating layer (GI).

[0096] The first gate connection electrode (GCE1) may be connected to the eleventh gate electrode (G11) of the eleventh transistor (T11) through an eighth contact hole (CT8) penetrating the interlayer insulating layer (ITL). In addition, the first gate connection electrode (GCE1) may be connected to the twelfth source electrode (S12) of the twelfth transistor (T12) through a fourth contact hole (CT4) penetrating the interlayer insulating layer (ITL) and the gate insulating layer (GI).

[0097] The second gate connection electrode (GCE2) may be connected to the twenty-first gate electrode (G21) of the twenty-first transistor (T21) through an eighth contact hole (CT8') penetrating the interlayer insulating layer (ITL). In addition, the second gate connection electrode (GCE2) may be connected to the twenty-second source electrode (S22) of the twenty-second transistor (T22) through a fourth contact hole (CT4') penetrating the interlayer insulating layer (ITL) and the gate insulating layer (GI).

[0098] The third gate connection electrode (GCE3) may be connected to the 31st gate electrode (G31) of the 31st transistor (T31) through the 8th contact hole (CT8'') penetrating the interlayer insulating layer (ITL). In addition, the third gate connection electrode (GCE3) may be connected to the 32nd source electrode (S32) of the 32nd transistor (T32) through the 4th contact hole (CT4'') penetrating the interlayer insulating layer (ITL) and the gate insulating layer (GI).

[0099] The first data connection electrode (DCE1) may overlap the first data line (DL1) and the third data line (DL3) among the first to third data lines (DL1-DL3). The first data connection electrode (DCE1) may be connected to the twelfth drain electrode (D12) of the twelfth transistor (T12) through a third contact hole (CT3) penetrating the interlayer insulating layer (ITL) and the gate insulating layer (GI). In addition, the first data connection electrode (DCE1) may be connected to the first data line (DL1) through a tenth contact hole (CT10) penetrating the interlayer insulating layer (ITL), the gate insulating layer (GI), and the buffer layer (BF).

[0100] The second data connection electrode (DCE2) may overlap the first to third data lines (DL3). The second data connection electrode (DCE2) may be connected to the twenty-second drain electrode (D22) of the twenty-second transistor (T22) through a third contact hole (CT3') penetrating the interlayer insulating layer (ITL) and the gate insulating layer (GI). In addition, the second data connection electrode (DCE2) may be connected to the second data line (DL2) through a tenth contact hole (CT10') penetrating the interlayer insulating layer (ITL), the gate insulating layer (GI), and the buffer layer (BF).

[0101] The third data connection electrode (DCE3) may overlap with the third data line (DL3) among the first to third data lines (DL1-DL3). The third data connection electrode (DCE3) may be connected to the 32nd drain electrode (D32) of the 32nd transistor (T32) through a third contact hole (CT3'') penetrating the interlayer insulating layer (ITL) and the gate insulating layer (GI). In addition, the third data connection electrode (DCE3) may be connected to the third data line (DL3) through a tenth contact hole (CT10'') penetrating the interlayer insulating layer (ITL), the gate insulating layer (GI), and the buffer layer (BF).

[0102] The first driving connection electrode (VCE1) may be connected to the eleventh drain electrode (D11) of the eleventh transistor (T11) through a first contact hole (CT1) penetrating the interlayer insulating layer (ITL) and the gate insulating layer (GI). In addition, the first driving connection electrode (VCE1) may be connected to the driving voltage line (VDL) through a seventh contact hole (CT7) penetrating the interlayer insulating layer (ITL), the gate insulating layer (GI), and the buffer layer (BF).

[0103] The second driving connection electrode (VCE2) may be connected to the twenty-first drain electrode (D21) of the twenty-first transistor (T21) through a first contact hole (CT1') penetrating the interlayer insulating layer (ITL) and the gate insulating layer (GI). In addition, the second driving connection electrode (VCE2) may be connected to the driving voltage line (VDL) through a seventh contact hole (CT7') penetrating the interlayer insulating layer (ITL), the gate insulating layer (GI), and the buffer layer (BF).

[0104] The third driving connection electrode (VCE3) may be connected to the 31st drain electrode (D31) of the 31st transistor (T31) through a first contact hole (CT1'') penetrating the interlayer insulating layer (ITL) and the gate insulating layer (GI). In addition, the second driving connection electrode (VCE2) may be connected to the driving voltage line (VDL) through a seventh contact hole (CT7'') penetrating the interlayer insulating layer (ITL), the gate insulating layer (GI), and the buffer layer (BF).

[0105] The initialization connection electrode (ICE) may be connected to a thirteenth source electrode (S13) of a thirteenth transistor (T13) through a sixth contact hole (CT6) penetrating an interlayer insulating layer (ITL) and a gate insulating layer (GI). In addition, the initialization connection electrode (ICE) may be connected to a twenty-third source electrode (S23) of a twenty-third transistor (T23) through a sixth contact hole (CT6) penetrating an interlayer insulating layer (ITL) and a gate insulating layer (GI). In addition, the initialization connection electrode (ICE) may be connected to a thirty-third source electrode (S33) of a thirty-third transistor (T33) through a sixth contact hole (CT6) penetrating an interlayer insulating layer (ITL) and a gate insulating layer (GI). Additionally, the initialization connection electrode (ICE) can be connected to the initialization voltage line (VIL) through a 13th contact hole (CT13) penetrating the interlayer insulating layer (ITL), the gate insulating layer (GI), and the buffer layer (BF).

[0106] The first scan line (SCL) can be connected to the 12th gate electrode (G12) of the 12th transistor (T12), the 22nd gate electrode (G22) of the 22nd transistor (T22), and the 32nd gate electrode (G32) of the 32nd transistor (T32) through the 14th contact hole (CT14) penetrating the interlayer insulating layer (ITL). For example, the 12th gate electrode (G12), the 22nd gate electrode (G22), and the 32nd gate electrode (G32) can be formed integrally to form a first gate structure, and the above-described first scan line (SCL) can be connected to the first gate structure through the 14th contact hole (CT14).

[0107] The second scan line (SSL) can be connected to the 13th gate electrode (G13) of the 13th transistor (T13), the 23rd gate electrode (G23) of the 23rd transistor (T23), and the 33rd gate electrode (G33) of the 33rd transistor (T33) through the 15th contact hole (CT15) penetrating the interlayer insulating layer (ITL). For example, the 13th gate electrode (G13), the 23rd gate electrode (G23), and the 33rd gate electrode (G33) can be formed integrally to form a second gate structure, and the above-described second scan line (SSL) can be connected to the second gate structure through the 15th contact hole (CT15).

[0108] A protective layer (PAS) may be disposed on the fourth pattern layer. For example, as illustrated in FIG. 6, a protective layer (PAS) may be disposed on the first driving connection electrode (VCE1) and the first anode connection electrode (ACE1).

[0109] The protective layer (PAS) may include an organic film such as an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, or a polyimide resin.

[0110] A via layer (VA) may be disposed on the protective layer (PAS). For example, as illustrated in FIG. 6, a via layer (VA) may be disposed on the protective layer (PAS). The via layer (VA) may have a different etching rate than the protective layer (PAS). The via layer (VA) may have the same material and structure as the protective layer (PAS) described above. However, the protective layer (PAS) may have a higher etching rate than the via layer (VA).

[0111] A fifth pattern layer may be disposed on the via layer (VA). For example, as illustrated in FIGS. 3 to 6, a light emitting element layer (EMTL) including a fifth pattern layer may be disposed on the via layer (VA). In other words, a first anode electrode (AND1), a second anode electrode (AND2), and a third anode electrode (AND3) may be disposed as the fifth pattern layer on the via layer (VA).

[0112] The first anode electrode (AND1) may be connected to the first anode connection electrode (ACE1) through an eleventh contact hole (CT11) and a ninth contact hole (CT9) that penetrate a via layer (VA) and a protective layer (PAS). Here, the eleventh contact hole (CT11) and the ninth contact hole (CT9) may be connected to each other. In a planar view, the eleventh contact hole (CT11) may surround the ninth contact hole (CT9).

[0113] The second anode electrode (AND2) may be connected to the second anode connection electrode (ACE2) through an eleventh contact hole (CT11') and a ninth contact hole (CT9') that penetrate a via layer (VA) and a protective layer (PAS). Here, the eleventh contact hole (CT11') and the ninth contact hole (CT9') may be connected to each other. In a planar view, the eleventh contact hole (CT11') may surround the ninth contact hole (CT9').

[0114] The third anode electrode (AND3) may be connected to the third anode connection electrode (ACE3) through an eleventh contact hole (CT11'') and a ninth contact hole (CT9'') that penetrate a via layer (VA) and a protective layer (PAS). Here, the eleventh contact hole (CT11'') and the ninth contact hole (CT9'') may be connected to each other. In a planar view, the eleventh contact hole (CT11'') may surround the ninth contact hole (CT9'').

[0115] The aforementioned light emitting element layer (EMTL) may further include a first light emitting element (ED1), a second light emitting element (ED2), a third light emitting element (ED3), and a pixel defining layer (PDL).

[0116] The first light-emitting element (ED1) may include a first anode electrode (AND1), a first light-emitting layer (EL1), and a cathode electrode (CAT). The first light-emitting region (EA1) refers to a region in which the first anode electrode (AND1), the first light-emitting layer (EL1), and the cathode electrode (CAT) are sequentially laminated, and holes from the first anode electrode (AND1) and electrons from the cathode electrode (CAT) combine with each other in the first light-emitting layer (EL) to emit light.

[0117] In a top emission structure that emits light in the direction of the cathode electrode (CAT) based on the first light-emitting layer (EL), the first anode electrode (AND1) may be formed as a single layer of molybdenum (Mo), titanium (Ti), copper (Cu), or aluminum (Al), or may be formed as a stacked structure of aluminum and titanium (Ti / Al / Ti), a stacked structure of aluminum and ITO (ITO / Al / ITO), an APC alloy, and a stacked structure of an APC alloy and ITO (ITO / APC / ITO) to increase reflectivity. The APC alloy may be an alloy of silver (Ag), palladium (Pd), and copper (Cu).

[0118] The second light-emitting element (ED2) may include a second anode electrode (AND2), a second light-emitting layer, and a cathode electrode (CAT). The second light-emitting region refers to a region in which the second anode electrode (AND2), the second light-emitting layer, and the cathode electrode (CAT) are sequentially stacked, and holes from the second anode electrode (AND2) and electrons from the cathode electrode (CAT) combine with each other in the second light-emitting layer to emit light.

[0119] In a top emission structure that emits light in the direction of the cathode electrode (CAT) based on the second light-emitting layer, the second anode electrode (AND2) may be formed as a single layer of molybdenum (Mo), titanium (Ti), copper (Cu), or aluminum (Al), or may be formed as a stacked structure of aluminum and titanium (Ti / Al / Ti), a stacked structure of aluminum and ITO (ITO / Al / ITO), an APC alloy, and a stacked structure of an APC alloy and ITO (ITO / APC / ITO) to increase reflectivity. The APC alloy may be an alloy of silver (Ag), palladium (Pd), and copper (Cu).

[0120] The third light-emitting element (ED3) may include a third anode electrode (AND3), a third light-emitting layer, and a cathode electrode (CAT). The third light-emitting region refers to a region in which the third anode electrode (AND3), the third light-emitting layer, and the cathode electrode (CAT) are sequentially stacked, and holes from the third anode electrode (AND3) and electrons from the cathode electrode (CAT) combine with each other in the third light-emitting layer to emit light.

[0121] In a top emission structure that emits light in the direction of the cathode electrode (CAT) based on the third light-emitting layer, the third anode electrode (AND3) may be formed as a single layer of molybdenum (Mo), titanium (Ti), copper (Cu), or aluminum (Al), or may be formed as a stacked structure of aluminum and titanium (Ti / Al / Ti), a stacked structure of aluminum and ITO (ITO / Al / ITO), an APC alloy, and a stacked structure of an APC alloy and ITO (ITO / APC / ITO) to increase reflectivity. The APC alloy may be an alloy of silver (Ag), palladium (Pd), and copper (Cu).

[0122] A pixel defining layer (PDL) may serve to define light-emitting areas of a pixel (e.g., first to third light-emitting areas). To this end, the pixel defining layer (PDL) may be arranged on a via layer (VA) to expose a portion of a first anode electrode (AND1), a portion of a second anode electrode (AND2), and a portion of a third anode electrode (AND3). The pixel defining layer (PDL) may cover each edge of the first anode electrode (AND1), the second anode electrode (AND2), and the third anode electrode (AND3).

[0123] The pixel defining layer (PDL) can be formed of an organic film such as an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, or a polyimide resin.

[0124] A first light-emitting layer (EL1) may be formed on the first anode electrode (AND1). The first light-emitting layer (EL1) may include an organic material and emit light of a predetermined color. For example, the first light-emitting layer (EL1) may include a hole transport layer, an organic material layer, and an electron transport layer. The organic material layer may include a host and a dopant. The organic material layer may include a material that emits a predetermined light, and may be formed using a phosphorescent material or a fluorescent material.

[0125] For example, the organic material layer of the first light-emitting layer (EL1) that emits light of a first color (e.g., blue) may be a phosphorescent material that includes a host material including CBP or mCP and a dopant material including (4,6-F2ppy)2Irpic or L2BD111, but is not limited thereto.

[0126] The organic material layer of the first light-emitting layer (EL1) that emits light of a second color (e.g., green) may include a host material including CBP or mCP, and may be a phosphorescent material including a dopant material including Ir(ppy)3(fac tris(2-phenylpyridine)iridium). Alternatively, the organic material layer of the light-emitting layer (EL) that emits light of a second color may be a fluorescent material including Alq3(tris(8-hydroxyquinolino)aluminum), but is not limited thereto.

[0127] The organic material layer of the first light-emitting layer (EL1) that emits light of a third color (e.g., red) may be a phosphorescent material that includes a host material containing CBP (carbazole biphenyl) or mCP (1,3-bis(carbazol-9-yl)), and a dopant that includes at least one selected from PIQIr(acac)(bis(1-phenylisoquinoline)acetylacetonate iridium), PQIr(acac)(bis(1-phenylquinoline)acetylacetonate iridium), PQIr(tris(1-phenylquinoline)iridium), and PtOEP(octaethylporphyrin platinum). Alternatively, the organic material layer of the light-emitting layer (EL) that emits light of a third color may be a fluorescent material containing PBD:Eu(DBM)3(Phen) or Perylene, but is not limited thereto.

[0128] A second light-emitting layer may be formed on the second anode electrode (AND2), and a third light-emitting layer may be formed on the third anode electrode (AND3). The second light-emitting layer and the third light-emitting layer may each include an organic material and emit light of a predetermined color.

[0129] According to one embodiment, the first light-emitting layer (EL1) on the first anode electrode (AND1), the second light-emitting layer on the second anode electrode (AND2), and the third light-emitting layer on the third anode electrode (AND3) can each provide light of the same color (or light of the same wavelength). For example, the first light-emitting layer (EL1) on the first anode electrode (AND1), the second light-emitting layer on the second anode electrode (AND2), and the third light-emitting layer on the third anode electrode (AND3) can each provide blue light. However, the present invention is not limited thereto, and each light-emitting layer can provide light of a different color. For example, the first light-emitting layer (EL1) on the first anode electrode (AND1), the second light-emitting layer on the second anode electrode (AND2), and the third light-emitting layer on the third anode electrode (AND3) can each provide light of cyan (e.g., light in which blue light and green light are mixed).

[0130] The cathode electrode (CAT) may be disposed on the first light-emitting layer (EL1), the second light-emitting layer, and the third light-emitting layer. The cathode electrode (CAT) may be disposed to cover the first light-emitting layer (EL1), the second light-emitting layer, and the third light-emitting layer. The cathode electrode (CAT) may be a common layer disposed commonly on a plurality of light-emitting layers.

[0131] In the upper emission structure, the cathode electrode (CAT) can be formed of a transparent conductive material (TCO) that can transmit light, such as ITO or IZO, or a semi-transmissive conductive material, such as magnesium (Mg), silver (Ag), or an alloy of magnesium (Mg) and silver (Ag). When the cathode electrode (CAT) is formed of a semi-transmissive metallic material, the light emission efficiency can be increased by the micro cavity.

[0132] The encapsulation layer (ENC) may be formed on the light emitting element layer (EMTL), as illustrated in FIG. 6. The encapsulation layer (ENC) may include at least one inorganic film (TFE1, TFE3) to prevent oxygen or moisture from penetrating into the light emitting element layer (EMTL). In addition, the encapsulation layer (ENC) may include at least one organic film to protect the light emitting element layer (EMTL) from foreign substances such as dust. For example, the encapsulation layer (ENC) may include a first encapsulation inorganic layer (TFE1), an encapsulation organic layer (TFE2), and a second encapsulation inorganic layer (TFE3).

[0133] A first encapsulating inorganic layer (TFE1) may be disposed on a cathode electrode (CAT), an encapsulating organic layer (TFE2) may be disposed on the first encapsulating inorganic layer (TFE1), and a second encapsulating inorganic layer (TFE3) may be disposed on the encapsulating organic layer (TFE2). The first encapsulating inorganic layer (TFE1) and the second encapsulating inorganic layer (TFE3) may be formed as a multi-layer in which one or more inorganic layers of a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, and an aluminum oxide layer are alternately laminated. The encapsulating organic layer (TFE2) may be an organic film such as an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, or a polyimide resin.

[0134] Meanwhile, if a foreign substance or the like penetrates into a pixel (e.g., one of the first pixel (PX1), the second pixel (PX2), and the third pixel (PX3)) during the manufacturing process of the display device (100), causing an abnormality in the pixel and determining that the pixel is a defective pixel that cannot normally provide light, a repair process can be performed on the defective pixel. This repair process is described in detail as follows.

[0135] FIG. 7 is a circuit diagram for explaining a method of manufacturing a display device (100) according to one embodiment. For example, FIG. 7 may be a diagram for explaining a repair method of the display device (100) of FIG. 2 described above.

[0136] As illustrated in FIG. 7, if a problem occurs in at least one of the transistors of the first pixel (PX1) (for example, the eleventh transistor (T11)) and the first pixel (PX1) is determined to be a defective pixel that cannot normally provide light, a repair process may be performed on the first pixel (PX1). For example, the connection between the first pixel circuit of the first pixel (PX1) and the first signal lines may be disconnected, the connection between the second pixel circuit of the second pixel (PX2) and the second signal lines may be disconnected, the second pixel circuit of the second pixel (PX2) and one of the first signal lines may be connected to each other, and the second anode electrode of the second pixel (PX2) and the first anode electrode of the first pixel (PX1) may be connected to each other.

[0137] Here, disconnection of the first pixel circuit of the first pixel (PX1) and the first signal lines may mean, for example, disconnection of the first pixel circuit of the first pixel (PX1) and the first data line (DL1), disconnection of the first pixel circuit of the first pixel (PX1) and the first scan line (SCL), and disconnection of the first pixel circuit of the first pixel (PX1) and the driving voltage line (VDL). In addition, disconnection of the second pixel circuit of the second pixel (PX2) and the second signal line may mean, for example, disconnection of the second pixel circuit of the second pixel (PX2) and the second data line (DL2). In addition, connection of the second pixel circuit of the second pixel (PX2) and any one of the first signal lines may mean, for example, that the second pixel circuit of the second pixel (PX2) and the first data line (DL1) are electrically connected to each other. At this time, the first pixel (PX1) may be a pixel that provides green light, and the second pixel (PX2) may be a pixel that provides blue light. Alternatively, the first pixel (PX1) may be a pixel that provides red light, and the second pixel (PX2) may be a pixel that provides blue light.

[0138] This repair process is explained in more detail as follows:

[0139] For example, as illustrated in FIG. 7, the drain electrode of the 12th transistor (T12) may be cut along the first cutting line (CL1), the source electrode of the 12th transistor (T12) may be cut along the second cutting line (CL2), the drain electrode of the 11th transistor (T11) may be cut along the third cutting line (CL3), and the drain electrode of the 13th transistor (T13) may be cut along the fourth cutting line (CL4).

[0140] Accordingly, the first electrode of the first capacitor (Cst1) and the source electrode of the 12th transistor (T12) can be electrically separated, the first data line (DL1) and the drain electrode of the 12th transistor (T12) can be electrically separated, the gate electrode of the 11th transistor (T11) and the source electrode of the 12th transistor (T12) can be electrically separated, and the second electrode of the first capacitor (Cst1) and the drain electrode of the 13th transistor (T13) can be electrically separated.

[0141] Meanwhile, in order to electrically connect a pixel circuit (e.g., a 21st transistor (T21), a 22nd transistor (T22), a 23rd transistor (T23), a second capacitor (Cst2)) of a normally operating pixel, for example, a second pixel (PX2), to the first pixel (PX1), the second pixel (PX2) may be connected to the first data line (DL1) instead of the second data line (DL2), and further, the second anode electrode (AND2) of the second pixel (PX2) may be connected to the first anode electrode (AND1). To this end, according to one embodiment, the second data connection electrode (DCE2) may be cut along the fifth cut line (CL5), the second anode electrode (AND2) may be cut along the sixth cut line (CL6), the second data connection electrode (DCE2) may be connected to the first data line (DL1) in the first overlapping area (OV1) of the second data connection electrode (DCE2) and the first data line (DL1), and among the split electrodes of the cut second anode electrode (AND2), the split electrode connected to the source electrode of the 21st transistor (T21) may be connected to the first anode electrode (AND1). Here, the cut second anode electrode (AND2) and the first anode electrode (AND1) may be connected to each other by the connection electrode (CNE2). Accordingly, the pixel circuit of the second pixel (PX2), which is a normal pixel, may be connected to the first anode electrode (AND1) of the first pixel (PX1), which is a defective pixel.

[0142] By the repair process and the dark spot process, the first light-emitting element (ED1) of the first pixel (PX1), which is a defective pixel, can be normally driven by the pixel circuit of another pixel (e.g., the pixel circuit of the second pixel (PX2)). For example, the first light-emitting element (ED1) of the first pixel (PX1) can emit light by receiving a driving current generated through the pixel circuit of the second pixel (PX2) (e.g., the 21st transistor (T21), the 22nd transistor (T22), the 23rd transistor (T23) and the second capacitor (Cst2)). At this time, the second pixel (PX2) can receive the first data voltage (Vd1) through the first data line (DL1). Therefore, the first light-emitting element (ED1) of the first pixel (PX1) can provide light corresponding to the magnitude (or grayscale value) of the first data voltage (Vd1), which is the original data voltage.

[0143] According to one embodiment, the first pixel (PX1) may be a green pixel that provides green light, the second pixel (PX2) may be a blue pixel that provides blue light, and the third pixel (PX3) may be a red pixel that provides red light. In a unit pixel including a red pixel, a green pixel, and a blue pixel, the luminance contribution of the green pixel is the highest, and the luminance contribution of the blue pixel is the lowest. In other words, in a unit pixel including a red pixel, a green pixel, and a blue pixel, the visibility of the green pixel is the highest, and the visibility of the blue pixel is the lowest. Therefore, when a green pixel having a relatively highest luminance contribution is defective, the failure rate and deterioration of the image quality of the display device (100) can be minimized by driving the light-emitting element of the green pixel using the driving current from the pixel circuit of the blue pixel having a relatively lowest luminance contribution. Meanwhile, the luminance contribution (or visibility) of the red pixel may be higher than the luminance contribution (or visibility) of the blue pixel and lower than the luminance contribution (or visibility) of the green pixel.

[0144] FIGS. 8 to 18 are array diagrams for explaining a method of manufacturing a display device (100) according to one embodiment. For example, FIG. 8 may be a diagram for explaining a repair method of the display device (100) of FIG. 3 described above. Here, FIG. 9 is a process cross-sectional view taken along line II-II' of FIG. 8, FIG. 10 is a process cross-sectional view taken along line III-III' of FIG. 8, FIG. 11 is a process cross-sectional view taken along line IV-IV' of FIG. 8, FIGS. 12 to 14 are process cross-sectional views taken along line V-V' of FIG. 8, and FIGS. 15 to 18 are process cross-sectional views taken along line VI-VI' of FIG. 8.

[0145] A repair process according to one embodiment may be performed, for example, after a protective layer (PAS) is formed. For example, as illustrated in FIG. 9, after the first pattern layer (e.g., the third data line (DL3) and the first data line (DL1) of FIG. 9), the buffer layer (BF), the second pattern layer (e.g., the twelfth active layer (AC12) of FIG. 9), the gate insulating layer (GI), the third pattern layer (e.g., the eleventh gate electrode (G11) and the twelfth gate electrode (G12) of FIG. 9), the interlayer insulating layer (ITL), the fourth pattern layer (e.g., the first gate connection electrode (GCE1) and the first data connection electrode (DCE1) of FIG. 9)) and the protective layer (PAS) are sequentially disposed on the substrate (SUB), a test process may be performed to detect whether each pixel is defective. After this test process, when it is confirmed that a defect has occurred in the first pixel (PX1) among the first to third pixels (PX1-PX3), the following repair process may be performed.

[0146] For example, as illustrated in FIGS. 8 and 9, the 12th drain electrode (D12) and the 12th source electrode (S12) of the 12th transistor (T12) may be cut. According to one embodiment, the 12th drain electrode (D12) of the 12th transistor (T12) may be cut along the first cutting line (CL1), and the 12th source electrode (S12) of the 12th transistor (T12) may be cut along the second cutting line (CL2). For example, as illustrated in FIG. 9, when a laser beam (LB) is irradiated on the protective layer (PAS) along the first cutting line (CL1), the first data connection electrode (DCE1) on the first cutting line (CL1) and the 12th drain electrode (D12) of the 12th transistor (T12) may be cut. In addition, as the laser beam (LB) is irradiated on the protective layer (PAS) along the second cutting line (CL2), the first gate connection electrode (GCE1) on the second cutting line (CL2) and the 12th source electrode (S12) of the 12th transistor (T12) can be cut. Accordingly, the 12th drain electrode (D12) of the 12th transistor (T12) and the first data line (DL1) can be electrically isolated from each other, and the 12th source electrode (S12) of the 12th transistor (T12) and the 11th gate electrode (G11) of the 11th transistor (T11) can be electrically isolated from each other.

[0147] According to one embodiment, in a planar view, at least one of the twelfth drain electrode (D12) and the first data connection electrode (DCE1) can be cut along the first cutting line (CL1) between the third contact hole (CT3) and the channel region (CH12) of the twelfth transistor (T12).

[0148] According to one embodiment, in a planar view, at least one of the twelfth drain electrode (D12) and the first data connection electrode (DCE1) may be cut along the first cutting line (CL1) on the third contact hole (CT3).

[0149] According to one embodiment, from a planar viewpoint, at least one of the twelfth source electrode (S12) and the first gate connection electrode (GCE1) can be cut along the second cutting line (CL2) between the fourth contact hole (CT4) and the channel region (CH12) of the twelfth transistor (T12).

[0150] According to one embodiment, from a planar viewpoint, at least one of the twelfth source electrode (S12) and the first gate connection electrode (GCE1) can be cut along the second cutting line (CL2) on the fourth contact hole (CT4).

[0151] According to one embodiment, the protective layer (PAS), the first data connection electrode (DCE1), the interlayer insulating layer (ITL), the gate insulating layer (GI), and the twelfth drain electrode (D12) on the first cutting line (CL1) may be penetrated by the laser beam (LB), and a groove may be formed in the buffer layer (BF). In addition, the protective layer (PAS), the first gate connection electrode (GCE1), the interlayer insulating layer (ITL), the gate insulating layer (GI), and the twelfth source electrode (S12) on the second cutting line (CL2) may be penetrated by the laser beam (LB), and a groove may be formed in the buffer layer (BF).

[0152] Next, as illustrated in FIGS. 8 and 10, the eleventh drain electrode (D11) of the eleventh transistor (T11) may be cut. According to one embodiment, the eleventh drain electrode (D11) of the eleventh transistor (T11) may be cut along the third cutting line (CL3). For example, as illustrated in FIG. 10, when a laser beam (LB) is irradiated on the protective layer (PAS) along the third cutting line (CL3), the eleventh drain electrode (D11) on the third cutting line (CL3) may be cut. Accordingly, the eleventh drain electrode (D11) of the eleventh transistor (T11) and the driving voltage line (VDL) may be electrically separated from each other.

[0153] According to one embodiment, in a planar view, at least one of the eleventh drain electrode (D11), the first driving connection electrode (VCE1) and the first anode connection electrode (ACE1) can be cut along the third cutting line (CL3) between the first contact hole (CT1) and the channel region (CH11) of the eleventh transistor (T11).

[0154] According to one embodiment, the protective layer (PAS), the interlayer insulating layer (ITL), the gate insulating layer (GI) and the eleventh drain electrode (D11) on the third cutting line (CL3) may be penetrated by the laser beam (LB), and a groove may be formed in the buffer layer (BF).

[0155] Next, as illustrated in FIGS. 8 and 11, the first anode connection electrode (ACE1) may be cut. According to one embodiment, the first anode connection electrode (ACE1) may be cut along the fourth cutting line (CL4). For example, as illustrated in FIG. 11, when a laser beam (LB) is irradiated onto the protective layer (PAS) along the fourth cutting line (CL4), the first anode connection electrode (ACE1) on the fourth cutting line (CL4) may be cut. Accordingly, the 13th drain electrode (D13) of the 13th transistor (T13) and the first light-shielding layer (BML1) may be electrically separated from each other. In other words, the 13th drain electrode (D13) of the 13th transistor (T13) and one electrode of the first capacitor (Cst1) may be electrically separated.

[0156] According to one embodiment, in a planar view, at least one of the thirteenth drain electrode (D13) and the first anode connection electrode (ACE1) can be cut along the fourth cut line (CL4) between the fifth contact hole (CT5) and the channel region (CH13) of the thirteenth transistor (T13).

[0157] According to one embodiment, the protective layer (PAS) and the first anode connection electrode (ACE1) on the fourth cutting line (CL4) may be penetrated by the laser beam (LB), and a groove may be formed in the interlayer insulating layer (ITL).

[0158] Meanwhile, the third cutting line (CL3) and the fourth cutting line (CL4) described above can be connected as a single line, and at this time, the laser beam (LB) can be continuously irradiated along the third cutting line (CL3) and the fourth cutting line (CL4). In this case, the protective layer (PAS), the first anode connection electrode (ACE1), the interlayer insulating layer (ITL), and the gate insulating layer (GI) on the fourth cutting line (CL4) can be penetrated by the laser beam (LB), and a groove can be formed in the buffer layer (BF).

[0159] Thereafter, as illustrated in FIGS. 8 and 12, the second data connection electrode (DCE2) may be cut. According to one embodiment, the second data connection electrode (DCE2) may be cut along the fifth cutting line (CL5). For example, as illustrated in FIG. 12, when a laser beam (LB) is irradiated on the protective layer (PAS) along the fifth cutting line (CL5), the second data connection electrode (DCE2) on the fifth cutting line (CL5) may be cut. Accordingly, the 22nd drain electrode (D22) of the 22nd transistor (T22) and the second data line (DL2) may be electrically isolated from each other.

[0160] According to one embodiment, in a planar view, at least one of the 22nd drain electrode (D22) and the second data connection electrode (DCE2) may be cut along the fifth cut line (CL5) between the 10th contact hole (CT10') and the channel region (CH22) of the 22nd transistor (T22).

[0161] According to one embodiment, the protective layer (PAS) and the second data connection electrode (DCE2) on the fifth cutting line (CL5) may be penetrated by the laser beam (LB), and a groove may be formed in the interlayer insulating layer (ITL).

[0162] Meanwhile, the third cutting line (CL3) and the fourth cutting line (CL4) described above can be connected as a single line, and at this time, the laser beam (LB) can be continuously irradiated along the third cutting line (CL3) and the fourth cutting line (CL4). In this case, the protective layer (PAS), the first anode connection electrode (ACE1), the interlayer insulating layer (ITL), and the gate insulating layer (GI) on the fourth cutting line (CL4) can be penetrated by the laser beam (LB), and a groove can be formed in the buffer layer (BF).

[0163] Next, as illustrated in FIGS. 8 and 13, the second data connection electrode (DCE2) and the first data line (DL1) may be electrically connected to each other. According to one embodiment, the second data connection electrode (DCE2) and the first data line (DL1) may be electrically connected to each other in the first overlapping area (OV1) of the second data connection electrode (DCE2) and the first data line (DL1). For example, as illustrated in FIG. 13, when a laser beam (LB) is irradiated onto the protective layer (PAS) in the first overlapping area (OV1) of the second data connection electrode (DCE2) and the first data line (DL1), the second data connection electrode (DCE2) and the first data line (DL1) may come into contact (or direct contact) with each other in the first overlapping area (OV1). Accordingly, the 22nd drain electrode (D22) of the 22nd transistor (T22) and the first data line (DL1) can be electrically connected to each other.

[0164] According to one embodiment, a protective layer (PAS), an interlayer insulating layer (ITL), a gate insulating layer (GI), and a buffer layer (BF) may be penetrated by a laser beam (LB) in a first overlapping region (OV1) of a second data connection electrode (DCE2) and a first data line (DL1), and a groove may be formed in the first data line (DL1).

[0165] According to one embodiment, a portion of the second data connection electrode (DCE2) in the first overlapping region (OV1) may be disposed within each through hole of the interlayer insulating layer (ITL), the gate insulating layer (GI) and the buffer and within the groove of the first data line (DL1).

[0166] Additionally, as illustrated in FIGS. 8 and 14, a first connection electrode (CNE1) may be further disposed on the protective layer (PAS). For example, the first connection electrode (CNE1) may be disposed on the protective layer (PAS) in the first overlapping region (OV1) and around the first overlapping region (OV1). A portion of the first connection electrode (CNE1) may be disposed within each through hole of the protective layer (PAS), the interlayer insulating layer (ITL), the gate insulating layer (GI), and the buffer layer (BF) (e.g., a through hole formed by irradiating the laser beam (LB) into the first overlapping region (OV1) of FIG. 13) and within a groove of the first data line (DL1) (e.g., a groove formed by irradiating the laser beam (LB) into the first overlapping region (OV1) of FIG. 13). At this time, a part of the first connection electrode (CNE1) may be in contact (or directly in contact) with the second data connection electrode (DCE2) and the first data line (DL1) within the aforementioned through hole and groove. By the first connection electrode (CNE1), the connection state between the second data connection electrode (DCE2) and the first data line (DL1) may be improved. The first connection electrode (CNE1) may include, for example, conductive ink. Meanwhile, the first connection electrode (CNE1) may be omitted.

[0167] Next, as illustrated in FIGS. 8 and 15, a ninth contact hole (CT9) that penetrates the protective layer (PAS) to expose the first anode connection electrode (ACE1), a ninth contact hole (CT9') that penetrates the first protective layer (PAS) to expose the second anode connection electrode (ACE2), and a ninth contact hole (CT9") that penetrates the first protective layer (PAS) to expose the third anode connection electrode (ACE3) can be formed.

[0168] Thereafter, a via layer (VA) may be formed on the protective layer (PAS) to fill the ninth contact holes (CT9, CT9', CT9"). At this time, the first connection electrode (CNE1) on the protective layer (PAS) may be covered by the via layer (VA). Since the first connection electrode (CNE1) is covered by the via layer (VA), oxidation of the first connection electrode (CNE1) in a subsequent process may be prevented.

[0169] Next, eleventh contact holes (CT11, CT11', CT11") may be formed to penetrate the via layer (VA) so as to overlap with the ninth contact holes (CT9, CT9', CT9"). The first anode connection electrode (ACE1) may be exposed by the eleventh contact hole (CT11) and the ninth contact hole (CT9) overlapping with the first anode connection electrode (ACE1), the second anode connection electrode (ACE2) may be exposed by the eleventh contact hole (CT11') and the ninth contact hole (CT9') overlapping with the second anode connection electrode (ACE2), and the third anode connection electrode (ACE3) may be exposed by the eleventh contact hole (CT11") and the ninth contact hole (CT9") overlapping with the third anode connection electrode (ACE3).

[0170] Thereafter, a first anode electrode (AND1), a second anode electrode (AND2), and a third anode electrode (AND3) can be placed on the via layer (VA). At this time, the first anode electrode (AND1) can be connected to the first anode connection electrode (ACE1) through the eleventh contact hole (CT11) of the via layer (VA) and the ninth contact hole (CT9) of the protective layer (PAS), the second anode electrode (AND2) can be connected to the second anode connection electrode (ACE2) through the eleventh contact hole (CT11') of the via layer (VA) and the ninth contact hole (CT9') of the protective layer (PAS), and the third anode electrode (AND3) can be connected to the third anode connection electrode (ACE3) through the eleventh contact hole (CT11") of the via layer (VA) and the ninth contact hole (CT9") of the protective layer (PAS).

[0171] Next, the second anode electrode (AND2) may be cut. According to one embodiment, the second anode electrode (AND2) may be cut along the sixth cutting line (CL6). For example, as illustrated in FIG. 15, when a laser beam (LB) is irradiated onto the second anode electrode (AND2) along the sixth cutting line (CL6), the second anode electrode (AND2) on the sixth cutting line (CL6) may be cut. For example, the second anode electrode (AND2) may include a first split electrode (EE1) and a second split electrode (EE2) that are separated from each other based on the sixth cutting line (CL6). The first split electrode (EE1) may be connected to the second anode connection electrode (ACE2) through the eleventh contact hole (CT11) and the ninth contact hole (CT9), while the second split electrode (EE2) may be electrically and physically separated from the second anode connection electrode (ACE2). Accordingly, the first split electrode (EE1) may be connected to the 21st source electrode (S21) of the 21st transistor (T21), while the second split electrode (EE2) may be separated from the 21st source electrode (S21) of the 21st transistor (T21). At this time, in a planar view as illustrated in FIG. 8, the first split electrode (EE1) may be smaller than the second split electrode (EE2). For example, in a planar view, the area of ​​the first split electrode (EE1) may be smaller than the area of ​​the second split electrode (EE2). Therefore, when the driving current is supplied to the second anode electrode (AND2), the area of ​​the actual light-emitting area of ​​the darkened second pixel (PX2) may be minimized. Here, the actual light-emitting area of ​​the darkened second pixel (PX2) may be an area corresponding to the first split electrode (EE1) of the second anode electrode (AND2).

[0172] According to one embodiment, a groove can be formed in the via layer (VA) on the sixth cutting line (CL6) by the laser beam (LB).

[0173] Thereafter, as illustrated in FIGS. 8 and 16, a second connection electrode (CNE2) may be disposed on the via layer (VA). For example, the second connection electrode (CNE2) may be disposed on the via layer (VA) to overlap the first anode electrode (AND1) and the second anode electrode (AND2). Specifically, the second connection electrode (CNE2) may be disposed on the via layer (VA) to overlap the first segment electrode (EE1) of the first anode electrode (AND1) and the second anode electrode (AND2). One side of the second connection electrode (CNE2) may be in contact (or direct contact) with the first anode electrode (AND1), and the other side of the second connection electrode (CNE2) may be in contact (or direct contact) with the first segment electrode (EE1) of the second anode electrode (AND2). Accordingly, the first split electrode (EE1) of the first anode electrode (AND1) and the second anode electrode (AND2) can be electrically connected to each other. The second connection electrode (CNE2) can include, for example, conductive ink.

[0174] According to one embodiment, the pixel circuit of the second pixel (PX2) is connected to the first pixel (PX1) through the first split electrode (EE1) of the second anode electrode (AND2), so that the first pixel (PX1) can be repaired and the second pixel (PX2) can be darkened.

[0175] According to one embodiment, as illustrated in FIG. 8, the first split electrode (EE1) of the first anode electrode (AND1) and the second anode electrode (AND2) may have a straight line shape that connects them in the shortest path.

[0176] Next, as illustrated in FIGS. 8 and 17, a pixel defining layer (PDL) may be disposed on the first anode electrode (AND1), the second anode electrode (AND2), and the second connection electrode (CNE2). A portion of the first anode electrode (AND1) may be exposed through the first emission area (EA1) defined by the pixel defining layer (PDL), and a portion of the second anode electrode (AND2) may be exposed through the second emission area (EA2) defined by the pixel defining layer (PDL).

[0177] According to one embodiment, the first connection electrode (CNE1) may be covered by a pixel definition layer (PDL). However, the present invention is not limited thereto, and for example, at least a portion of the first connection electrode (CNE1) may be disposed within at least one of the first emission area (EA1) and the second emission area (EA).

[0178] According to one embodiment, the first segmented electrode (EE1) of the second anode electrode (AND2) may be covered by a pixel defining layer (PDL). For example, at least a portion of the first segmented electrode (EE1) may be covered by the pixel defining layer (PDL). As an example, FIG. 17 illustrates an embodiment in which the entire first segmented electrode (EE1) is covered by the pixel defining layer (PDL).

[0179] Next, as illustrated in FIGS. 8 and 18, a first light-emitting layer (EL1) may be disposed on a first anode electrode (AND1) through a first light-emitting area (EA1) of a pixel defining layer (PDL), and a second light-emitting layer (EL2) may be disposed on a second anode electrode (AND2) through a second light-emitting area (EA2) of the pixel defining layer (PDL). Meanwhile, although not illustrated, a third light-emitting layer may be disposed on a third anode electrode (AND3).

[0180] Thereafter, a cathode electrode (CAT) can be placed on the first light-emitting layer (EL1), the second light-emitting layer (EL2), and the third light-emitting layer.

[0181] Next, an encapsulation layer (ENC) may be disposed on the cathode electrode (CAT). The encapsulation layer (ENC) may include a first encapsulation inorganic layer (TFE1), an encapsulation organic layer (TFE2), and a second encapsulation inorganic layer (TFE3).

[0182] Next, as illustrated in FIGS. 8 and 19, a filler (400) may be placed on the encapsulating layer (ENC). The filler (400) may be formed of a material that can transmit light. For example, the filler (400) may be formed of an organic material. In one embodiment, the filler (400) may be formed of a silicone-based organic material, an epoxy-based organic material, or a mixture of a silicone-based organic material and an epoxy-based organic material.

[0183] Next, a color conversion substrate (500) may be placed on the filler (400). According to one embodiment, the color conversion substrate (500) may include a color conversion pattern that converts the color of incident light. According to one embodiment, the color conversion substrate (500) may include at least one of a color filter and a wavelength conversion pattern as the color conversion pattern. According to one embodiment, the color conversion substrate (500) may include both a color filter and a wavelength conversion pattern. For example, a first pixel (PX1) may include a first wavelength conversion pattern (QD1) and a first color filter (CF1) overlapping a first light-emitting area (EA1), a second pixel (PX2) may include a second wavelength conversion pattern (QD2) and a second color filter (CF2) overlapping a second light-emitting area (EA2), and although not shown, a third pixel (PX3) may include a third wavelength conversion pattern and a third color filter overlapping a third light-emitting area (EA3 of FIG. 20).

[0184] The first wavelength conversion pattern (QD1) may be a wavelength conversion pattern that converts or shifts the peak wavelength of incident light into light of a different specific peak wavelength and then emits the light. For example, the first wavelength conversion pattern (QD1) may convert blue light from the first light-emitting layer (EL1) into green light and provide the converted light to the first color filter (CF1).

[0185] The second wavelength conversion pattern (QD2) may be a wavelength conversion pattern that converts or shifts the peak wavelength of incident light into light of a different specific peak wavelength and emits the light. For example, the second wavelength conversion pattern (QD2) may transmit blue light from the second light-emitting layer (EL2) and provide it to the second color filter (CF2).

[0186] The third wavelength conversion pattern may be a wavelength conversion pattern that converts or shifts the peak wavelength of incident light into light of a different specific peak wavelength and emits the light. For example, the third wavelength conversion pattern may convert blue light from the third light-emitting layer (EL3 in FIG. 20) into red light and provide it to the third color filter.

[0187] The first color filter (CF1), the second color filter (CF1), and the third color filter can selectively transmit light of different colors (or different wavelengths). For example, the first color filter (CF1) can selectively transmit green light, the second color filter (CF1) can selectively transmit blue light, and the third color filter can selectively transmit red light.

[0188] At this time, the first light-emitting layer (EL1), the second light-emitting layer (EL1), and the third light-emitting layer described above may be formed integrally. For example, the first light-emitting layer (EL1), the second light-emitting layer (EL1), and the third light-emitting layer may all have a tandem structure that provides blue light (or cyan light). For example, the first light-emitting layer (EL1), the second light-emitting layer (EL1), and the third light-emitting layer may each include a red light-emitting layer, a green light-emitting layer, and a blue light-emitting layer laminated along the third direction (DR3).

[0189] The first pixel (PX1) repaired through the processes described above can emit light normally, and the second pixel (PX2) can be darkened. In other words, the first pixel (PX1), which is a defective pixel, can be normally driven through the pixel circuit of the second pixel (PX2), which is a normal pixel, and the light-emitting element (ED2) of the second pixel (PX2) can be darkened. Meanwhile, since the second pixel (PX2) is the pixel with the lowest luminance contribution, the deterioration of the image quality of the display device (100) can be minimized even when the second pixel is darkened.

[0190] Meanwhile, the repair process of the display device (100) according to one embodiment may be performed according to the drawing arrangement order of FIGS. 9 to 18, but is not limited thereto. For example, the process of FIG. 10 may be performed before the process of FIG. 9, and the order of the repair process of the display device (100) according to one embodiment may be modified in various ways.

[0191] FIGS. 19 and 20 are drawings for explaining a repair process of a display device (100) according to another embodiment. For example, the process illustrated in FIGS. 19 and 20 may be performed after the process illustrated in FIG. 18 described above. Here, FIG. 20 may be a plan view of the cathode electrode (CAT) of FIG. 19.

[0192] As illustrated in FIGS. 19 and 20, the cathode electrode (CAT) corresponding to the second light-emitting area (EA2) can be removed. For example, as illustrated in FIG. 19, a laser beam (LB) is irradiated onto the cathode electrode (CAT) overlapping the second light-emitting area (EA2) on the color conversion substrate (500), so that the cathode electrode (CAT) overlapping the second light-emitting area (EA2) can be selectively removed. At this time, a part of the second light-emitting layer (EL2) can be removed by the laser beam (LB). Accordingly, as illustrated in FIGS. 19 and 20, the cathode electrode (CAT) can have a through hole (80; or opening) in the area overlapping the second light-emitting area (EA2). The second light-emitting layer (EL2) can be exposed through the through hole (80) of the cathode electrode (CAT). In other words, the cathode electrode (CAT) according to one embodiment overlaps the first light-emitting area (EA1) and the third light-emitting area (EA3), but does not overlap the second light-emitting area (EA2). According to one embodiment, in a planar view, the size of the through hole (80) may be equal to or smaller than the size of the second light-emitting area (EA).

[0193] In this way, darkening of the second pixel (PX2) can be performed more reliably as the cathode electrode (CAT) is selectively removed from the second light-emitting area (EA2). For example, if darkening of the second pixel (PX2) is not properly performed despite the cutting process of the second anode electrode (AND2) as in FIG. 15, darkening of the second pixel (PX2) can be performed by selectively removing the cathode electrode (CAT) of the second light-emitting area (EA2) of the second pixel (PX2) as illustrated in FIG. 19.

[0194] Meanwhile, the order of some steps in the aforementioned repair processes may be changed, as explained below with reference to FIGS. 21 to 23.

[0195] FIGS. 21 to 23 are drawings for explaining a method of manufacturing a display device (100) according to another embodiment.

[0196] For example, the process sequence illustrated in FIGS. 12 to 14 described above can be changed to the process sequence illustrated in FIGS. 21 to 23.

[0197] After the process of FIG. 11 described above, as illustrated in FIG. 8 and FIG. 21, the second data connection electrode (DCE2) and the first data line (DL1) may be electrically connected to each other. According to one embodiment, the second data connection electrode (DCE2) and the first data line (DL1) may be electrically connected to each other in the first overlapping area (OV1) of the second data connection electrode (DCE2) and the first data line (DL1). For example, as illustrated in FIG. 21, when a laser beam (LB) is irradiated onto the protective layer (PAS) in the first overlapping area (OV1) of the second data connection electrode (DCE2) and the first data line (DL1), the second data connection electrode (DCE2) and the first data line (DL1) may come into contact (or direct contact) with each other in the first overlapping area (OV1). Accordingly, the 22nd drain electrode (D22) of the 22nd transistor (T22) and the first data line (DL1) can be electrically connected to each other.

[0198] According to one embodiment, a protective layer (PAS), an interlayer insulating layer (ITL), a gate insulating layer (GI), and a buffer layer (BF) may be penetrated by a laser beam (LB) in a first overlapping region (OV1) of a second data connection electrode (DCE2) and a first data line (DL1), and a groove may be formed in the first data line (DL1).

[0199] According to one embodiment, a portion of the second data connection electrode (DCE2) in the first overlapping region (OV1) may be disposed within each of the through holes of the interlayer insulating layer (ITL), the gate insulating layer (GI) and the buffer layer (BF) and the groove of the first data line (DL1).

[0200] Next, as illustrated in FIGS. 8 and 22, a first connection electrode (CNE1) may be disposed on the protective layer (PAS). For example, the first connection electrode (CNE1) may be disposed on the protective layer (PAS) in the first overlapping region (OV1) and around the first overlapping region (OV1). A portion of the first connection electrode (CNE1) may be disposed within each through hole of the protective layer (PAS), the interlayer insulating layer (ITL), the gate insulating layer (GI), and the buffer layer (BF) (e.g., a through hole formed by irradiating the laser beam (LB) into the first overlapping region (OV1) of FIG. 13) and within a groove of the first data line (DL1) (e.g., a groove formed by irradiating the laser beam (LB) into the first overlapping region (OV1) of FIG. 13). At this time, a part of the first connection electrode (CNE1) may be in contact (or direct contact) with the second data connection electrode (DCE2) and the first data line (DL1) within the above-described through hole and groove.

[0201] Next, as illustrated in FIGS. 8 and 23, the second data connection electrode (DCE2) may be cut. According to one embodiment, the second data connection electrode (DCE2) may be cut along the fifth cutting line (CL5). For example, as illustrated in FIG. 23, when a laser beam (LB) is irradiated on the protective layer (PAS) along the fifth cutting line (CL5), the second data connection electrode (DCE2) on the fifth cutting line (CL5) may be cut. Accordingly, the 22nd drain electrode (D22) of the 22nd transistor (T22) and the second data line (DL2) may be electrically isolated from each other.

[0202] According to one embodiment, the protective layer (PAS) and the second data connection electrode (DCE2) on the fifth cutting line (CL5) may be penetrated by the laser beam (LB), and a groove may be formed in the interlayer insulating layer (ITL).

[0203] Meanwhile, the third cutting line (CL3) and the fourth cutting line (CL4) described above can be connected as a single line, and at this time, the laser beam (LB) can be continuously irradiated along the third cutting line (CL3) and the fourth cutting line (CL4). In this case, the protective layer (PAS), the first anode connection electrode (ACE1), the interlayer insulating layer (ITL), and the gate insulating layer (GI) on the fourth cutting line (CL4) can be penetrated by the laser beam (LB), and a groove can be formed in the buffer layer (BF).

[0204] According to the process sequence of FIGS. 21 to 23, since the cutting process of the second data connection electrode (DCE2) is performed after the formation of the first connection electrode (CNE1), when the conductive ink used as the first connection electrode (CNE1) is applied, the conductive ink can be prevented from flowing into the cut portion of the second data connection electrode (DCE2). Accordingly, the cut portions of the second data connection electrode (DCE2) can be prevented from being connected by the first connection electrode (CNE1).

[0205] FIG. 24 and FIG. 25 are drawings for explaining a repair process of a display device (100) according to another embodiment. For example, FIG. 24 is a drawing in which a seventh cutting line and an eighth cutting line are further arranged in FIG. 8 described above, and FIG. 25 may be a cross-sectional view taken along line VII-VII' of FIG. 24.

[0206] As illustrated in FIGS. 24 and 25, the 13th drain electrode (D13) and the 13th source electrode (S13) of the 13th transistor (T13) may be cut. According to one embodiment, the 13th drain electrode (D13) of the 13th transistor (T13) may be cut along the seventh cutting line (CL7), and the 13th source electrode (S13) of the 13th transistor (T13) may be cut along the eighth cutting line (CL8). For example, as illustrated in FIG. 25, when a laser beam (LB) is irradiated on the protective layer (PAS) along the seventh cutting line (CL7), the first anode connection electrode (ACE1) on the seventh cutting line (CL7) and the 13th drain electrode (D13) of the 13th transistor (T13) may be cut. In addition, as the laser beam (LB) is irradiated on the protective layer (PAS) along the eighth cutting line (CL8), the initialization connection electrode (ICE) on the eighth cutting line (CL8) and the 13th source electrode (S13) of the 13th transistor (T13) may be cut. Accordingly, the 13th drain electrode (D13) of the 13th transistor (T13) and the first light-shielding layer (BML1) may be electrically isolated from each other, and the 13th source electrode (S13) of the 13th transistor (T13) and the initialization voltage line (VIL) may be electrically isolated from each other. Accordingly, the 13th drain electrode (D13) of the 13th transistor (T13) and one electrode of the first capacitor (Cst1) may be electrically isolated from each other.

[0207] According to one embodiment, in a planar view, at least one of the thirteenth drain electrode (D13) and the first anode connection electrode (ACE1) can be cut along the seventh cutting line (CL7) between the fifth contact hole (CT5) and the channel region (CH13) of the thirteenth transistor (T13).

[0208] According to one embodiment, in a planar view, at least one of the thirteenth drain electrode (D13) and the first anode connection electrode (ACE1) can be cut along the seventh cutting line (CL7) on the fifth contact hole (CT5).

[0209] According to one embodiment, in a planar view, at least one of the thirteenth source electrode (S13) and the initialization connection electrode (ICE) can be cut along the eighth cutting line (CL8) between the sixth contact hole (CT6) and the channel region (CH13) of the thirteenth transistor (T13).

[0210] According to one embodiment, from a planar viewpoint, at least one of the thirteenth source electrode (S13) and the initialization connection electrode (ICE) can be cut along the eighth cutting line (CL8) on the sixth contact hole (CT6).

[0211] According to one embodiment, the protective layer (PAS), the first anode connection electrode (ACE1), the interlayer insulating layer (ITL), the gate insulating layer (GI), and the thirteenth drain electrode (D13) on the seventh cutting line (CL7) may be penetrated by the laser beam (LB), and a groove may be formed in the buffer layer (BF). In addition, the protective layer (PAS), the initialization connection electrode (ICE), the interlayer insulating layer (ITL), the gate insulating layer (GI), and the thirteenth source electrode (S13) on the eighth cutting line (CL8) may be penetrated by the laser beam (LB), and a groove may be formed in the buffer layer (BF).

[0212] According to one embodiment, the processes of FIGS. 24 and 25 may be performed, for example, between the processes of FIG. 11 and FIG. 12 described above.

[0213] According to one embodiment, the processes of FIGS. 24 and 25 may be performed, for example, between the processes of FIG. 12 and FIG. 13 described above.

[0214] According to one embodiment, the processes of FIGS. 24 and 25 may be performed, for example, in place of the process of FIG. 11 described above. As a specific example, after the process of FIG. 10 described above is performed, the processes of FIGS. 24 and 25 may be performed instead of the process of FIG. 11.

[0215] Meanwhile, the processes of FIGS. 24 and 25 can be omitted.

[0216] FIGS. 26 to 31 are drawings for explaining a method of manufacturing a display device (100) according to another embodiment. For example, FIG. 26 is a drawing in which a third connection electrode (CNE3) is arranged instead of the second connection electrode (CNE2) in FIG. 8 described above, and FIGS. 27 to 31 may be cross-sectional views taken along line VIII-VIII' of FIG. 26.

[0217] According to one embodiment, the processes of FIGS. 26 to 31 may be performed after the process of FIG. 14 described above. In this case, the processes of FIGS. 15 to 18 described above may be replaced with the processes of FIGS. 26 to 31. In other words, a method for manufacturing a display device (100) according to one embodiment may include the processes of FIGS. 9 to 14 and FIGS. 26 to 31.

[0218] After the process of FIG. 14, as illustrated in FIGS. 26 and 27, each of the ninth contact holes (CT9, CT9') exposing the first anode connection electrode (ACE1) and the second anode connection electrode (ACE2) may be formed in the protective layer (PAS). One of the ninth contact holes (CT9, CT9') may penetrate the protective layer (PAS) to expose the first anode connection electrode (ACE1), and the other of the ninth contact holes (CT9, CT9') may penetrate the protective layer (PAS) to expose the second anode connection electrode (ACE2).

[0219] Next, as illustrated in FIGS. 26 and 28, a third connection electrode (CNE3) may be disposed on the protective layer (PAS). The third connection electrode (CNE3) may be connected to the first anode connection electrode (ACE1) and the second anode connection electrode (ACE2). For example, one side of the third connection electrode (CNE3) may be connected to the first anode connection electrode (ACE1) through the ninth contact hole (CT9), and the other side of the third connection electrode (CNE3) may be connected to the second anode connection electrode (ACE2) through the ninth contact hole (CT9'). In other words, one side of the third connection electrode (CNE3) may contact (or directly contact) the first anode connection electrode (ACE1) through the ninth contact hole (CT9), and the other side of the third connection electrode (CNE3) may contact (or directly contact) the second anode connection electrode (ACE2) through the ninth contact hole (CT9'). Accordingly, the first anode connection electrode (ACE1) and the second anode connection electrode (ACE2) may be electrically connected to each other by the third connection electrode (CNE3). The third connection electrode (CNE3) may include, for example, conductive ink.

[0220] According to one embodiment, as illustrated in FIG. 26, the third connection electrode (CNE3) may have a straight line shape that connects the ninth contact holes (CT9, CT9') along the shortest path.

[0221] Next, as illustrated in FIGS. 26 and 29, a via layer (VA) may be formed on the protective layer (PAS) and the third connection electrode (CNE3). At this time, the via layer (VA) may also be disposed on the first connection electrode (CNE1) described above. In other words, the first connection electrode (CNE1) and the third connection electrode (CNE3) may be covered by the via layer (VA).

[0222] Next, as illustrated in FIGS. 26 and 30, eleventh contact holes (CT11, CT11') overlapping with the ninth contact holes (CT9, CT9'), respectively, may be formed in the via layer (VA). In a planar view, one of the eleventh contact holes (CT11, CT11') may surround the ninth contact hole (CT9) overlapping with the first anode connection electrode (ACE1) and the third connection electrode (CNE3), and another of the eleventh contact holes (CT11, CT11') may surround the ninth contact hole (CT9') overlapping with the second anode connection electrode (ACE2) and the third connection electrode (CNE3). The ninth contact holes (CT9, CT9') may each penetrate the via layer (VA) to expose the third connection electrode (CNE3), respectively.

[0223] Thereafter, as illustrated in FIGS. 26 and 31, a first anode electrode (AND1) and a second anode electrode (AND2) may be disposed on the via layer (VA). The first anode electrode (AND1) may be connected to one side of the third connection electrode (CNE3) through the eleventh contact hole (CT11), and the second anode electrode (AND2) may be connected to the other side of the third connection electrode (CNE3) through the eleventh contact hole (CT11'). Therefore, the first anode electrode (AND1) and the second anode electrode (AND2) may be electrically connected to each other through the third connection electrode (CNE3).

[0224] Next, as illustrated in FIG. 26, as the second anode electrode (AND2) is cut along the sixth cutting line (CL6), the second anode electrode (AND2) can be separated into a first split electrode (EE1) and a second split electrode (EE2). For a detailed description of the cutting process of the second anode electrode (AND2), refer to, for example, the process and related description of FIG. 15 described above. In this way, as the second anode electrode (AND2) is separated into the first split electrode (EE1) and the second split electrode (EE2), the first split electrode (EE1) can be connected to the third connection electrode (CNE3), while the second split electrode (EE2) can be electrically separated from the third connection electrode (CNE3). In other words, the first split electrode (EE1) of the first anode electrode (AND1) and the second anode electrode (AND2) can be electrically connected to each other by the third connection electrode (CNE3). Accordingly, the pixel circuit of the second pixel (PX2) is connected to the first pixel (PX1) through the first split electrode (EE1) of the second anode electrode (AND2), so that the first pixel (PX1) can be repaired and the second pixel (PX2) can be darkened.

[0225] Thereafter, a pixel defining layer (PDL) may be disposed on the first anode electrode (AND1) and the second anode electrode (AND2), a first light-emitting layer (EL1) and a second light-emitting layer (EL2) connected to the first anode electrode (AND1) and the second anode electrode (AND2) may be disposed on the pixel defining layer (PDL), a cathode electrode (CAT) connected to the first light-emitting layer (EL1) and the second light-emitting layer (EL2) may be disposed, and an encapsulation layer (ENC) may be disposed on the cathode electrode (CAT). For a description of these processes, refer to the description of the related processes in, for example, FIGS. 16, 17, and 18 described above.

[0226] According to one embodiment, the display device (100) may include the second connection electrode (CNE2) and the third connection electrode (CNE3) described above together. In this case, after the processes of FIGS. 9 to 14 are sequentially performed, the processes of FIGS. 27 to 30 are sequentially performed, and then, as in FIG. 26, a process of dividing the second anode electrode (AND2) into the first split electrode (EE1) and the second split electrode (EE2) along the sixth cutting line (CL6) is performed (e.g., see FIG. 15), and then, a process of electrically connecting the first split electrode (EE1) of the first anode electrode (AND1) and the second anode electrode (AND2) to each other using the second connection electrode (CNE2) may be performed (e.g., see FIG. 16).

[0227] FIGS. 32 to 36 are drawings for explaining a method of manufacturing a display device (100) according to another embodiment. For example, FIG. 32 is a drawing in which a fourth connection electrode (CNE4) is arranged instead of the second connection electrode (CNE2) in FIG. 8 described above, and FIGS. 33 to 36 may be cross-sectional views taken along line IX-IX' of FIG. 32.

[0228] According to one embodiment, the processes of FIGS. 32 to 36 may be performed after the process of FIG. 14 described above. In this case, the processes of FIGS. 15 to 18 described above may be replaced with the processes of FIGS. 32 to 36. In other words, a method for manufacturing a display device (100) according to one embodiment may include the processes of FIGS. 9 to 14 and FIGS. 32 to 36.

[0229] After the process of FIG. 14, as illustrated in FIGS. 32 and 33, auxiliary contact holes (CTa, CTa') exposing the first anode connection electrode (ACE1) and the second anode connection electrode (ACE2), respectively, may be formed in the protective layer (PAS). One of the auxiliary contact holes (CTa, CTa') may penetrate the protective layer (PAS) to expose the first anode connection electrode (ACE1), and the other of the auxiliary contact holes (CTa, CTa') may penetrate the protective layer (PAS) to expose the second anode connection electrode (ACE2). At this time, the auxiliary contact holes (CTa, CTa') may be formed simultaneously with the ninth contact holes (CT9, CT9') of FIG. 32 described above. For a detailed description of the process of forming these ninth contact holes (CT9, CT9'), refer to, for example, the description of FIG. 27 described above and the related process.

[0230] Next, as illustrated in FIGS. 32 and 34, a fourth connection electrode (CNE4) may be disposed on the protective layer (PAS). The fourth connection electrode (CNE4) may be connected to the first anode connection electrode (ACE1) and the second anode connection electrode (ACE2). For example, one side of the fourth connection electrode (CNE4) may be connected to the first anode connection electrode (ACE1) through an auxiliary contact hole (CTa), and the other side of the fourth connection electrode (CNE4) may be connected to the second anode connection electrode (ACE2) through an auxiliary contact hole (CTa'). In other words, one side of the fourth connection electrode (CNE4) may contact (or directly contact) the first anode connection electrode (ACE1) through the auxiliary contact hole (CTa), and the other side of the fourth connection electrode (CNE4) may contact (or directly contact) the second anode connection electrode (ACE2) through the auxiliary contact hole (CTa'). Accordingly, the first anode connection electrode (ACE1) and the second anode connection electrode (ACE2) may be electrically connected to each other by the fourth connection electrode (CNE4). The fourth connection electrode (CNE4) may include, for example, conductive ink.

[0231] According to one embodiment, as illustrated in FIG. 32, the fourth connection electrode (CNE4) may have a straight line shape that connects the auxiliary contact holes (CTa, CTa') along the shortest path.

[0232] Next, as illustrated in FIGS. 32 and 35, a via layer (VA) may be formed on the protective layer (PAS) and the fourth connection electrode (CNE4). At this time, the via layer (VA) may also be disposed on the first connection electrode (CNE1) described above. In other words, the first connection electrode (CNE1) and the fourth connection electrode (CNE4) may be covered by the via layer (VA).

[0233] Next, as illustrated in FIG. 32, eleventh contact holes (CT11, CT11') overlapping with the ninth contact holes (CT9, CT9'), respectively, may be formed in the via layer (VA). In a planar view, one (CT11) of the eleventh contact holes (CT11, CT11') may surround the ninth contact hole (CT9) overlapping with the first anode connection electrode (ACE1), and the other (CT11') of the eleventh contact holes (CT11, CT11') may surround the ninth contact hole (CT9') overlapping with the second anode connection electrode (ACE2). The ninth contact holes (CT9, CT9') may each penetrate the via layer (VA) to expose the third connection electrode (CNE3), respectively. For a detailed description of the formation process of these 11th contact holes (CT11, CT11'), refer to, for example, the description of the aforementioned FIG. 30 and related processes.

[0234] Thereafter, as illustrated in FIGS. 32 and 36, a first anode electrode (AND1) and a second anode electrode (AND2) may be disposed on the via layer (VA). At this time, as illustrated in FIG. 32, the first anode electrode (AND1) may be connected to the first anode connection electrode (ACE1) through the eleventh contact hole (CT11) and the ninth contact hole (CT9), and the second anode electrode (AND2) may be connected to the second anode connection electrode (ACE2) through the eleventh contact hole (CT11') and the ninth contact hole (CT9'). Therefore, the first anode electrode (AND1) and the second anode electrode (AND2) may be electrically connected to each other through the first anode connection electrode (ACE1), the second anode connection electrode (ACE2), and the fourth connection electrode (CNE4). In other words, unlike the embodiments of FIGS. 26 to 31 described above, the first anode electrode (AND1) and the second anode electrode (AND2) in the embodiments of FIGS. 32 to 36 are not directly connected to the fourth connection electrode (CNE4), but may be indirectly connected to the fourth connection electrode (CNE4) through the first anode connection electrode (ACE1) and the second anode connection electrode (ACE2).

[0235] Next, as illustrated in FIG. 32, as the second anode electrode (AND2) is cut along the sixth cutting line (CL6), the second anode electrode (AND2) can be separated into a first split electrode (EE1) and a second split electrode (EE2). For a detailed description of the cutting process of the second anode electrode (AND2), refer to, for example, the process and related description of FIG. 15 described above. As such, as the second anode electrode (AND2) is separated into the first split electrode (EE1) and the second split electrode (EE2), the first split electrode (EE1) can be connected to the fourth connection electrode (CNE4) via the second anode connection electrode (ACE2), while the second split electrode (EE2) can be electrically separated from the fourth connection electrode (CNE4). In other words, the first split electrode (EE1) of the first anode electrode (AND1) and the second anode electrode (AND2) can be electrically connected to each other by the fourth connecting electrode (CNE4). Here, the first anode electrode (AND1) can be connected to the fourth connecting electrode (CNE4) via the first anode connecting electrode (ACE1). Accordingly, the pixel circuit of the second pixel (PX2) can be connected to the first pixel (PX1) via the first split electrode (EE1) of the second anode electrode (AND2), so that the first pixel (PX1) can be repaired and the second pixel (PX2) can be darkened.

[0236] Thereafter, a pixel defining layer (PDL) may be disposed on the first anode electrode (AND1) and the second anode electrode (AND2), a first light-emitting layer (EL1) and a second light-emitting layer (EL2) connected to the first anode electrode (AND1) and the second anode electrode (AND2) may be disposed on the pixel defining layer (PDL), a cathode electrode (CAT) connected to the first light-emitting layer (EL1) and the second light-emitting layer (EL2) may be disposed, and an encapsulation layer (ENC) may be disposed on the cathode electrode (CAT). For a description of these processes, refer to the description of the related processes in, for example, FIGS. 16, 17, and 18 described above.

[0237] According to the embodiment related to FIGS. 32 to 36, the fourth connection electrode (CNE4) is disposed on the protective layer (PAS) so as not to overlap with the eleventh contact holes (CT11, CT11'), so that the fourth connection electrode (CNE4) is not exposed and can be maintained in a state covered by the via layer (VA) during the process of forming the eleventh contact holes (CT11, CT11', CT11") penetrating the via layer (VA) (e.g., the process of FIG. 30). Therefore, when forming the eleventh contact holes (CT11, CT11', CT11"), the fourth connection electrode (CNE4) can be prevented from being oxidized or damaged.

[0238] According to one embodiment, the display device (100) may include the second connection electrode (CNE2) and the fourth connection electrode (CNE4) described above together. In this case, after the processes of FIGS. 9 to 14 are sequentially performed, the processes of FIGS. 33 to 36 are sequentially performed, and then, as in FIG. 26, a process of dividing the second anode electrode (AND2) into the first split electrode (EE1) and the second split electrode (EE2) along the sixth cutting line (CL6) is performed (e.g., see FIG. 15), and then, a process of electrically connecting the first split electrode (EE1) of the first anode electrode (AND1) and the second anode electrode (AND2) to each other using the second connection electrode (CNE2) may be performed (e.g., see FIG. 16).

[0239] FIGS. 37 to 40 are drawings for explaining a method of manufacturing a display device (100) according to another embodiment. For example, FIG. 37 is a drawing in which a fifth connection electrode (CNE5) is further arranged in FIG. 8 described above, and FIGS. 38 to 40 may be cross-sectional views taken along line X-X' of FIG. 37.

[0240] According to one embodiment, the processes of FIGS. 37 to 40 may be performed after the process of FIG. 12 described above. In this case, the processes of FIGS. 13 and 14 described above may be replaced with the processes of FIGS. 39 and 40. In other words, a method for manufacturing a display device (100) according to one embodiment may include the processes of FIGS. 9 to 12, and FIGS. 39 and 40.

[0241] After the process of FIG. 12, as illustrated in FIGS. 37 to 39, a first through hole (HL1) exposing the first data line (DL1) and a second through hole (HL2) exposing the second data connection electrode (DCE2) may be formed. The first through hole (HL1) may penetrate the protective layer (PAS), the interlayer insulating layer (ITL), the gate insulating layer (GI), and the buffer layer (BF). The second through hole may penetrate the protective layer (PAS). At this time, a groove may be formed in each of the first data line (DL1) and the second data connection electrode (DCE2) by irradiation with a laser beam (LB). Meanwhile, the first through hole (HL1) and the second through hole (HL2) described above may be formed, for example, by an etching process instead of the laser beam (LB). For example, the first through hole (HL1) and the second through hole (HL2) can be formed by an etching process that forms the ninth contact holes (CT9, CT9' CT9'') of the aforementioned protective layer (PAS). In this case, the first through hole (HL1), the second through hole (HL1) and the ninth contact holes (CT9, CT9' CT9'') can be formed simultaneously by a single etching process.

[0242] Next, as illustrated in FIGS. 37 to 40, a fifth connection electrode (CNE5) may be disposed on the protective layer (PAS). The fifth connection electrode (CNE5) may be connected to the second data line (DL2) and the second data connection electrode (DCE2). For example, one side of the fifth connection electrode (CNE5) may contact (or directly contact) the first data line (DL1) through the first through hole (HL1), and the other side of the fifth connection electrode (CNE5) may contact (or directly contact) the second data connection electrode (DCE2) through the second through hole (HL2). Accordingly, the first data line (DL1) and the second data connection electrode (DCE2) may be electrically connected to each other. In other words, the 22nd drain electrode (D22) of the 22nd transistor (T22) can be electrically connected to the first data line (DL1) via the second data connection electrode (DCE2) and the fifth connection electrode (CNE5). The fifth connection electrode (CNE5) can include conductive ink.

[0243] According to one embodiment, the fifth connection electrode (CNE5) may overlap the first to third data lines (DL1-DL3), as illustrated in FIG. 37. Additionally, the fifth connection electrode (CNE5) may overlap the second data connection electrode (DCE2).

[0244] According to one embodiment, as illustrated in FIG. 37, the fifth connecting electrode (CNE5) may have a bent shape. However, the present invention is not limited thereto, and the fifth connecting electrode (CNE5) may also have a straight shape that connects the first through hole (HL1) and the second through hole (HL2) via the shortest path.

[0245] Fig. 41 is a circuit diagram of a display device (100) according to one embodiment.

[0246] The display device (100) of FIG. 41 has a difference from the display device (100) of FIG. 2 described above in the connection relationship between each pixel (PX1-PX3) and data lines (DL1-DL3), and also has a difference from the display device (100) of FIG. 2 in that it further includes an auxiliary connection electrode (AXE). These differences will be described in detail as follows.

[0247] As illustrated in FIG. 41, the second data line (DL2) can be placed between the first data line (DL1) and the third data line (DL3).

[0248] The auxiliary connection electrode (AXE) can be connected to the second data connection electrode (DCE2). The auxiliary connection electrode (AXE) can overlap the first data line (DL1), the second data line (DL2), and the third data line (DL3).

[0249] Fig. 42 is a plan view of a display device (100) according to one embodiment. For example, Fig. 42 may be a plan view of a display device (100) including the first to third pixels of Fig. 41.

[0250] The display device (100) of FIG. 42 has differences from the display device (100) of FIG. 3 described above in the arrangement positions of the data lines (DL1-DL3) and the shapes of the first data connection electrode (DCE1) and the second data connection electrode (DCE2), and also has differences from the display device (100) of FIG. 3 in that it further includes an auxiliary connection electrode (AXE). These differences will be described in detail as follows.

[0251] As illustrated in FIGS. 41 and 42, the second data line (DL2) may be arranged between the first data line (DL1) and the third data line (DL3). At this time, the first data line (DL1) may be arranged at the uppermost side, and the third data line (DL3) may be arranged at the lowermost side. For example, among the first to third data lines (DL1-DL3), the first data line (DL1) may be arranged farthest from a gate structure (e.g., the 12th gate electrode (G12), the 32nd gate electrode (G32), and the 22nd gate electrode (G22)), and the third data line (DL3) may be arranged closest to the gate structure.

[0252] The first data connection electrode (DCE1) can overlap the first to third data lines (DL1-DL3).

[0253] The second data connection electrode (DCE2) can overlap the second data line (DL2) and the third data line (DL3).

[0254] According to one embodiment, the display device (100) of FIG. 41 may further include an auxiliary connection electrode (AXE).

[0255] The auxiliary connection electrode (AXE) may be connected to the second data connection electrode (DCE2). For example, the auxiliary connection electrode (AXE) may be formed integrally with the second data connection electrode (DCE2). The auxiliary connection electrode (AXE) may be included in, for example, the fourth pattern layer. One side of the auxiliary connection electrode (AXE) may be connected to the twenty-second drain electrode (D22) of the twenty-second transistor (T22) through the third contact hole (CT3'). The auxiliary connection electrode (AXE) may overlap the first to third data lines (DL1-DL3).

[0256] According to one embodiment, the display device (100) of FIG. 41 may further include the fifth connection electrode (CNE5) of FIG. 37 described above instead of the auxiliary connection electrode (AXE). Such fifth connection electrode (CNE5) may be connected to the 22nd drain electrode (D22) of the 22nd transistor (T22), and the other side of the fifth connection electrode (CNE5) may overlap the first data line (DL1). At this time, the other side of the fifth connection electrode (CNE5) may be connected to the first data line (DL1) through a through hole.

[0257] Fig. 43 is a circuit diagram for explaining a method of manufacturing a display device (100) according to one embodiment. For example, Fig. 43 may be a diagram for explaining a repair method of the display device (100) of Fig. 41 described above.

[0258] The repair method of the display device (100) of FIG. 43 is different from the repair method of the display device (100) of FIG. 7 described above in that it connects the first data line (DL1) and the second pixel (PX2) by utilizing an auxiliary connection electrode (AXE). This difference will be described in detail as follows.

[0259] For example, in order to connect a pixel circuit (e.g., the 21st transistor (T21), the 22nd transistor (T22), the 23rd transistor (T23), the second capacitor (Cst2)) of a normally operating pixel, for example, the second pixel (PX2), to the first pixel (PX1), the second pixel (PX2) may be connected to the first data line (DL1) instead of the second data line (DL2). To this end, according to one embodiment, the second data connection electrode (DCE2) may be cut along the eighth cut line (CL8), and the auxiliary connection electrode (AXE) may be connected to the first data line (DL1) in the second overlapping area (OV2) of the auxiliary connection electrode (AXE) and the first data line (DL1).

[0260] According to one embodiment, the first pixel (PX1) may be a green pixel that provides green light, the second pixel (PX2) may be a blue pixel that provides blue light, and the third pixel (PX3) may be a red pixel that provides red light. In a unit pixel including a red pixel, a green pixel, and a blue pixel, the luminance contribution of the green pixel is the highest, and the luminance contribution of the blue pixel is the lowest. Therefore, when a green pixel with a relatively highest luminance contribution fails, the light-emitting element of the green pixel is driven using a driving current from the pixel circuit of the blue pixel with a relatively lowest luminance contribution, thereby minimizing the defect rate and deterioration of image quality of the display device (100).

[0261] FIGS. 44 to 47 are drawings for explaining a method of manufacturing a display device (100) according to one embodiment. For example, FIGS. 44 to 47 may be drawings for explaining a repair method of the display device (100) of FIG. 42. Here, FIGS. 45 to 47 are cross-sectional views taken along line XI-XI' of FIG. 42.

[0262] First, as illustrated in FIG. 45, a substrate (SUB) may be prepared on which a first pattern layer (e.g., a third data line (DL3), a second data line (DL2), a first data line (DL1)), a buffer layer (BF), a second pattern layer (e.g., a 22nd active layer (AC22)), a gate insulating layer (GI), a third pattern layer, an interlayer insulating layer (ITL), a fourth pattern layer (e.g., an auxiliary connecting electrode (AXE)), and a protective layer (PAS) are disposed.

[0263] Next, as illustrated in FIG. 44, the second data connection electrode (DCE2) may be cut. According to one embodiment, the second data connection electrode (DCE2) may be cut along the eighth cutting line (CL8). For example, as the laser beam (LB) is irradiated onto the protective layer (PAS) along the eighth cutting line (CL8), the second data connection electrode (DCE2) on the eighth cutting line (CL8) may be cut. Accordingly, the 22nd drain electrode (D22) of the 22nd transistor (T22) and the second data line (DL2) may be electrically separated from each other. For a detailed description regarding the separation process of the second data connection electrode (DCE2), refer to, for example, the aforementioned FIG. 12 and the related description.

[0264] Next, as illustrated in FIGS. 44 and 46, the auxiliary connection electrode (AXE) and the first data line (DL1) may be electrically connected to each other. According to one embodiment, the auxiliary connection electrode (AXE) and the first data line (DL1) may be electrically connected to each other in the second overlapping region (OV2) of the auxiliary connection electrode (AXE) and the first data line (DL1). For example, as illustrated in FIG. 46, when a laser beam (LB) is irradiated on the protective layer (PAS) in the second overlapping region (OV2) of the auxiliary connection electrode (AXE) and the first data line (DL1), the auxiliary connection electrode (AXE) and the first data line (DL1) may come into contact (or direct contact) with each other in the second overlapping region (OV2). Accordingly, the 22nd drain electrode (D22) of the 22nd transistor (T22) and the first data line (DL1) may be electrically connected to each other.

[0265] According to one embodiment, the protective layer (PAS), the interlayer insulating layer (ITL), the gate insulating layer (GI) and the buffer layer (BF) may be penetrated by the laser beam (LB) in the second overlapping region (OV2) of the auxiliary connecting electrode (AXE) and the first data line (DL1), and a groove may be formed in the first data line (DL1).

[0266] According to one embodiment, a portion of the auxiliary connection electrode (AXE) in the second overlapping region (OV2) may be disposed within each through hole of the interlayer insulating layer (ITL), the gate insulating layer (GI) and the buffer and within the groove of the first data line (DL1).

[0267] Additionally, as illustrated in FIGS. 44 and 47, a sixth connection electrode (CNE6) may be further disposed on the protective layer (PAS). For example, the sixth connection electrode (CNE6) may be disposed on the protective layer (PAS) in the second overlapping region (OV2) and around the second overlapping region (OV2). A portion of the sixth connection electrode (CNE6) may be disposed within each through hole of the protective layer (PAS), the interlayer insulating layer (ITL), the gate insulating layer (GI), and the buffer layer (BF) (e.g., a through hole formed by irradiating the laser beam (LB) into the second overlapping region (OV2) of FIG. 46) and within a groove of the first data line (DL1) (e.g., a groove formed by irradiating the laser beam (LB) into the second overlapping region (OV2) of FIG. 46). At this time, a part of the sixth connection electrode (CNE6) may be in contact with the auxiliary connection electrode (AXE) and the first data line (DL1) within the above-described through hole and groove. By the sixth connection electrode (CNE6), the connection state between the auxiliary connection electrode (AXE) and the first data line (DL1) may be improved. The sixth connection electrode (CNE6) may include, for example, conductive ink. Meanwhile, the sixth connection electrode (CNE6) may be omitted.

[0268] According to one embodiment, the repair process in FIGS. 44 to 47 may further include, for example, the processes related to FIGS. 9 to 12 described above, and the processes related to FIGS. 15 to 18.

[0269] According to one embodiment, the cutting process of the second data connection electrode (DCE2) may be performed after the connecting process of the auxiliary connection electrode (AXE). For related embodiments, see, for example, FIGS. 21 to 23 and their associated descriptions.

[0270] According to one embodiment, when the second data connection electrode (DCE2) does not overlap with the first data line (DL1; e.g., the data line connected to the defective pixel), the repair process can be performed normally through the auxiliary connection electrode (AXE) instead of the second data connection electrode (DCE2).

[0271] Fig. 48 is a circuit diagram of a display device (100) according to one embodiment.

[0272] The display device (100) of FIG. 48 has a difference from the display device (100) of FIG. 2 described above in terms of the arrangement of pixels, and also has a difference from the display device (100) of FIG. 2 described above in that it further includes a dummy electrode (DME). These differences will be described in detail as follows.

[0273] As illustrated in FIG. 48, the first pixel (PX1) may be positioned between the third pixel (PX3) and the second pixel (PX2).

[0274] As illustrated in FIG. 48, one side of the dummy electrode (DME) may be connected to the second capacitor (Cst2) of the second pixel (PX2) and the second anode electrode (AND2; or, the second anode connection electrode (ACE2) to be described later) of the second light-emitting element (ED2). The other side of the dummy electrode (DME) may extend to the first pixel (PX1). The other side of the dummy electrode (DME) may overlap with one electrode of the first capacitor (Cst1) (e.g., the first light-blocking layer (BML1) to be described later).

[0275] FIGS. 49 to 51 are plan views of a display device (100) according to one embodiment. For example, FIG. 49 may be a plan view of a display device (100) including the first to third pixels of FIG. 48.

[0276] Fig. 49 includes diagrams related to the first pixel. Fig. 50 is the same diagram as Fig. 49, and Fig. 50 includes diagrams related to the second pixel. Fig. 51 is the same diagram as Fig. 49, and Fig. 51 includes diagrams related to the third pixel. Fig. 52 is a cross-sectional view taken along line A1-A1' of Fig. 49.

[0277] As illustrated in FIG. 52, the display device (100) may include a substrate (SUB), a thin film transistor layer (TFTL), a light emitting element layer (EMTL), and an encapsulation layer (ENC). On the substrate (SUB), the thin film transistor layer (TFTL), the light emitting element layer (EMTL), and the encapsulation layer (ENC) may be sequentially arranged along a third direction (DR3). Here, the thin film transistor layer (TFTL) may include the aforementioned eleventh transistors (T11, T21, T31), twelfth transistors (T12, T22, T22), and thirteenth transistors (T13, T23, T33).

[0278] Since the substrate (SUB) of Fig. 52 is the same as the substrate (SUB) of Fig. 6 described above, a description of the substrate (SUB) of Fig. 52 refers to Fig. 6 and the related description.

[0279] As illustrated in FIG. 52, a first pattern layer may be arranged on the substrate (SUB). The first pattern layer may include, for example, a first light-shielding layer (BML1), a second light-shielding layer (BML2), a third light-shielding layer (BML3), a first data line (DL1), a second data line (DL2), a third data line (DL3), a driving voltage line (VDL), and an initialization voltage line (VIL), as illustrated in FIGS. 49 to 51. The first light-blocking layer (BML1), the second light-blocking layer (BML2), the third light-blocking layer (BML3), the first data line (DL1), the second data line (DL2), the third data line (DL3), the driving voltage line (VDL) and the initialization voltage line (VIL) of FIGS. 49 to 51 are the same as the first light-blocking layer (BML1), the second light-blocking layer (BML2), the third light-blocking layer (BML3), the first data line (DL1), the second data line (DL2), the third data line (DL3), the driving voltage line (VDL) and the initialization voltage line (VIL) of FIGS. 3 to 5 described above, respectively, so that the first light-blocking layer (BML1), the second light-blocking layer (BML2), the third light-blocking layer (BML3), the first data line (DL1), the second data line (DL2), the third data line (DL3), the driving voltage line (VDL) and the initialization voltage of FIGS. 49 to 51 For a description of the line (VIL), see FIGS. 3 to 5 and the related descriptions.

[0280] A buffer layer (BF) may be disposed on the first pattern layer. The buffer layer (BF) of Fig. 52 is identical to the buffer layer (BF) of Fig. 6 described above, and therefore, for a description of the buffer layer (BF) of Fig. 52, refer to Fig. 6 and its related description.

[0281] A second pattern layer may be disposed on the buffer layer (BF). The second pattern layer may include an eleventh active layer (AC11), a twelfth active layer (AC12), a thirteenth active layer (AC13), a twenty-first active layer (AC21), a twenty-second active layer (AC22), a twenty-third active layer (AC23), a thirty-first active layer (AC31), a thirty-second active layer (AC32), and a thirty-third active layer (AC33), as illustrated in FIGS. 49 to 51. The 11th active layer (AC11), the 12th active layer (AC12), the 13th active layer (AC13), the 21st active layer (AC21), the 22nd active layer (AC22), the 23rd active layer (AC23), the 31st active layer (AC31), the 32nd active layer (AC32) and the 33rd active layer (AC33) of FIGS. 49 to 51 are the same as the 11th active layer (AC11), the 12th active layer (AC12), the 13th active layer (AC13), the 21st active layer (AC21), the 22nd active layer (AC22), the 23rd active layer (AC23), the 31st active layer (AC31), the 32nd active layer (AC32) and the 33rd active layer (AC33) of FIGS. 3 to 5 described above, so the 11th active layer (AC11), the 12th active layer (AC12), the 13th active layer (AC13) of FIGS. 49 to 51 For descriptions of the active layer (AC13), the 21st active layer (AC21), the 22nd active layer (AC22), the 23rd active layer (AC23), the 31st active layer (AC31), the 32nd active layer (AC32), and the 33rd active layer (AC33), refer to the descriptions related to FIGS. 3 to 5.

[0282] However, the 11th active layer (AC11) and the 21st active layer (AC21) of FIGS. 49 to 51 may be formed integrally.

[0283] As illustrated in Fig. 52, a gate insulating layer (GI) may be disposed on the second pattern layer. Since the gate insulating layer (GI) of Fig. 52 is identical to the gate insulating layer (GI) of Fig. 6 described above, a description of the gate insulating layer (GI) of Fig. 52 refers to Fig. 6 and its related description.

[0284] A third pattern layer may be disposed on the gate insulating layer (GI). The third pattern layer may include an eleventh gate electrode (G11), a twelfth gate electrode (G12), a thirteenth gate electrode (G13), a twenty-first gate electrode (G21), a twenty-second gate electrode (G22), a twenty-third gate electrode (G23), a thirty-first gate electrode (G31), a thirty-second gate electrode (G32), and a thirty-third gate electrode (G33), as illustrated in FIGS. 49 to 51. The 11th gate electrode (G11), the 12th gate electrode (G12), the 13th gate electrode (G13), the 21st gate electrode (G21), the 22nd gate electrode (G22), the 23rd gate electrode (G23), the 31st gate electrode (G31), the 32nd gate electrode (G32) and the 33rd gate electrode (G33) of FIGS. 49 to 51 are the same as the 11th gate electrode (G11), the 12th gate electrode (G12), the 13th gate electrode (G13), the 21st gate electrode (G21), the 22nd gate electrode (G22), the 23rd gate electrode (G23), the 31st gate electrode (G31), the 32nd gate electrode (G32) and the 33rd gate electrode (G33) of FIGS. 3 to 5 described above, respectively, and therefore, the 11th gate electrode (G11), the 12th gate electrode (G12), the 13th gate electrode (G13) of FIGS. 49 to 51 For descriptions of the electrode (G13), the 21st gate electrode (G21), the 22nd gate electrode (G22), the 23rd gate electrode (G23), the 31st gate electrode (G31), the 32nd gate electrode (G32), and the 33rd gate electrode (G33), refer to the related descriptions in FIGS. 3 to 5.

[0285] An interlayer insulating layer (ITL) may be disposed on the third pattern layer. Since the interlayer insulating layer (ITL) of FIG. 52 is identical to the interlayer insulating layer (ITL) of FIG. 6 described above, a description of the interlayer insulating layer (ITL) of FIG. 52 refers to FIG. 6 and its related description.

[0286] A fourth pattern layer may be disposed on the interlayer insulating layer (ITL). The fourth pattern layer may include, as illustrated in FIGS. 49 to 51, a first anode connection electrode (ACE1), a second anode connection electrode (ACE2), a third anode connection electrode (ACE3), a first gate connection electrode (GCE1), a second gate connection electrode (GCE2), a third gate connection electrode (GCE3), a first data connection electrode (DCE1), a second data connection electrode (DCE2), a third data connection electrode (DCE3), a first drive connection electrode (VCE1), a second drive connection electrode (VCE2), an initialization connection electrode (ICE), a first scan line (SCL), and a second scan line (SSL).

[0287] The first anode connection electrode (ACE1), the second anode connection electrode (ACE2), the third anode connection electrode (ACE3), the first gate connection electrode (GCE1), the second gate connection electrode (GCE2), the third gate connection electrode (GCE3), the first data connection electrode (DCE1), the second data connection electrode (DCE2), the third data connection electrode (DCE3), the first drive connection electrode (VCE1), the second drive connection electrode (VCE2), the initialization connection electrode (ICE), the first scan line (SCL) and the second scan line (SSL) of FIGS. 49 to 51 are the first anode connection electrode (ACE1), the second anode connection electrode (ACE2), the third anode connection electrode (ACE3), the first gate connection electrode (GCE1), the second gate connection electrode (GCE2), the third gate connection electrode (GCE3), the first data connection electrode (DCE1), the second data connection electrode (DCE2), the third data Since the connection electrode (DCE3), the first drive connection electrode (VCE1), the second drive connection electrode (VCE2), the initialization connection electrode (ICE), the first scan line (SCL) and the second scan line (SSL) are the same as each other, the description of the first anode connection electrode (ACE1), the second anode connection electrode (ACE2), the third anode connection electrode (ACE3), the first gate connection electrode (GCE1), the second gate connection electrode (GCE2), the third gate connection electrode (GCE3), the first data connection electrode (DCE1), the second data connection electrode (DCE2), the third data connection electrode (DCE3), the first drive connection electrode (VCE1), the second drive connection electrode (VCE2), the initialization connection electrode (ICE), the first scan line (SCL) and the second scan line (SSL) of FIGS. 49 to 51 refers to FIGS. 3 to 5 and the related descriptions.

[0288] However, the second driving connection electrode (VCE2) of FIGS. 49 to 51 may be commonly connected to the 11th drain electrode (D11) of the 11th transistor (T11) and the 21st drain electrode (D21) of the 21st transistor (T21).

[0289] However, the first scan line (SCL) of FIGS. 49 to 51 may be connected to the 12th gate electrode (G12) of the 12th transistor (T12) through the 14th contact hole (CT14) penetrating the interlayer insulating layer (ITL), to the 22nd gate electrode (G22) of the 22nd transistor (T22) through the 14th contact hole (CT14') penetrating the interlayer insulating layer (ITL), and to the 32nd gate electrode (G32) of the 32nd transistor (T32) through the 14th contact hole (CT14") penetrating the interlayer insulating layer (ITL).

[0290] However, the second scan line (SSL) of FIGS. 49 to 51 may be connected to the 13th gate electrode (G13) of the 13th transistor (T13) through the 15th contact hole (CT15) penetrating the interlayer insulating layer (ITL), to the 23rd gate electrode (G23) of the 23rd transistor (T23) through the 15th contact hole (CT15') penetrating the interlayer insulating layer (ITL), and to the 33rd gate electrode (G33) of the 33rd transistor (T33) through the 15th contact hole (CT15") penetrating the interlayer insulating layer (ITL).

[0291] A protective layer (PAS) may be disposed on the fourth pattern layer. The protective layer (PAS) of FIG. 52 is identical to the protective layer (PAS) of FIG. 6 described above, and therefore, for a description of the protective layer (PAS) of FIG. 52, refer to FIG. 6 and its related description.

[0292] A via layer (VA) may be arranged on the protective layer (PAS). Since the via layer (VA) of FIG. 52 is identical to the via layer (VA) of FIG. 6 described above, a description of the via layer (VA) of FIG. 52 refers to FIG. 6 and its related description.

[0293] A fifth pattern layer may be disposed on the via layer (VA). For example, as illustrated in FIG. 52, a light emitting element layer (EMTL) including the fifth pattern layer may be disposed on the via layer (VA). Since the light emitting element layer (EMTL) of FIG. 52 is identical to the light emitting element layer (EMTL) of FIG. 6 described above, a description of the light emitting element layer (EMTL) of FIG. 52 refers to FIG. 6 and its related description.

[0294] The aforementioned light emitting element layer (EMTL) may further include a first light emitting element (ED1), a second light emitting element (ED2), a third light emitting element (ED3), and a pixel defining layer (PDL). The first light emitting element (ED1), the second light emitting element (ED2), the third light emitting element (ED3), and the pixel defining layer (PDL) of FIG. 52 are each identical to the first light emitting element (ED1), the second light emitting element (ED2), the third light emitting element (ED3), and the pixel defining layer (PDL) of FIG. 6, and therefore, for a description of the first light emitting element (ED1), the second light emitting element (ED2), the third light emitting element (ED3), and the pixel defining layer (PDL) of FIG. 52, refer to FIG. 6 and the related description.

[0295] A first light-emitting layer (EL1) may be formed on a first anode electrode (AND1), a second light-emitting layer (EL2) may be formed on a second anode electrode (AND2), and a third light-emitting layer may be formed on a third anode electrode (AND3). The first light-emitting layer (EL1), the second light-emitting layer (EL2), and the third light-emitting layer of FIG. 52 are the same as the first light-emitting layer (EL1), the second light-emitting layer (EL2), and the third light-emitting layer of FIG. 6, respectively, and therefore, for a description of the first light-emitting layer (EL1), the second light-emitting layer (EL2), and the third light-emitting layer of FIG. 52, refer to FIG. 6 and the related description.

[0296] The cathode electrode (CAT) may be disposed on the first light-emitting layer (EL1), the second light-emitting layer (EL2), and the third light-emitting layer. Since the cathode electrode (CAT) of Fig. 52 is the same as the cathode electrode (CAT) of Fig. 6 described above, the description of the cathode electrode (CAT) of Fig. 52 refers to Fig. 6 and its related description.

[0297] The encapsulation layer (ENC) can be formed on the light emitting element layer (EMTL). Since the encapsulation layer (ENC) of Fig. 52 is identical to the encapsulation layer (ENC) of Fig. 6 described above, a description of the encapsulation layer (ENC) of Fig. 52 refers to Fig. 6 and its related description.

[0298] Meanwhile, if a foreign substance or the like penetrates into a pixel (e.g., one of the first pixel (PX1), the second pixel (PX2), and the third pixel (PX3)) during the manufacturing process of the display device (100), causing an abnormality in the pixel and determining that the pixel is a defective pixel that cannot normally provide light, a repair process can be performed on the defective pixel. This repair process is described in detail as follows.

[0299] Fig. 53 is a circuit diagram for explaining a method of manufacturing a display device (100) according to one embodiment. For example, Fig. 53 may be a diagram for explaining a repair method of the display device (100) of Fig. 48 described above.

[0300] As illustrated in FIG. 53, if at least one of the transistors of the first pixel (PX1) (e.g., the 11th transistor (T11)) is abnormal and the first pixel (PX1) is judged to be a defective pixel that cannot normally provide light, a repair process can be performed on the first pixel (PX1). This repair process is described in detail as follows.

[0301] For example, as illustrated in FIG. 53, the gate electrode of the eleventh transistor (T11) may be cut along the first cutting line (CL1'), the drain electrode of the eleventh transistor (T11) may be cut along the first cutting line (CL1'), the drain electrode of the thirteenth transistor (T13) may be cut along the third cutting line (CL3'), the source electrode of the thirteenth transistor (T13) may be cut along the fourth cutting line (CL4'), the drain electrode of the twenty-second transistor (T22) may be cut along the fifth cutting line (CL5'), the source electrode of the twenty-second transistor (T22) may be cut along the sixth cutting line (CL6'), and the second anode electrode (AND2) may be cut along the seventh cutting line (CL7').

[0302] Accordingly, the gate electrode of the 11th transistor (T11) and the first capacitor (Cst1) are electrically separated, the drain electrode of the 11th transistor (T11) and the driving voltage line (VDL) are electrically separated, the drain electrode of the 13th transistor (T13) and the first capacitor (Cst1) are electrically separated, the source electrode of the 13th transistor (T13) and the initialization voltage line (VIL) can be electrically separated, the drain electrode of the 22nd transistor (T22) and the second capacitor (Cst2) can be electrically separated, the source electrode of the 22nd transistor (T22) and the second data line (DL2) can be electrically separated, and a part of the second anode electrode (AND2) can be separated from the source electrode of the 21st transistor (T21).

[0303] Meanwhile, in order to electrically connect a pixel circuit (e.g., a 21st transistor (T21), a 22nd transistor (T22), a 23rd transistor (T23), and a second capacitor (Cst2)) of a normally operating pixel, for example, a second pixel (PX2), to the first pixel (PX1), the gate electrode of the 21st transistor (T21) of the second pixel (PX2) is connected to the source electrode of the 12th transistor (T12) via the first connection electrode (CNE1), and the dummy electrode (DME) of the second pixel (PX2) and one electrode of the first capacitor (Cst1) can be electrically connected in an overlapping region (OV) of the dummy electrode (DME) and one electrode of the first capacitor (Cst1).

[0304] By the repair process and the darkening process, the first light-emitting element (ED1) of the first pixel (PX1), which is a defective pixel, can be normally driven by another pixel (e.g., the second pixel (PX2)). For example, the first light-emitting element (ED1) of the first pixel (PX1) can emit light by receiving a driving current generated through the pixel circuit of the second pixel (PX2) (e.g., the 21st transistor (T21), the 22nd transistor (T22), the 23rd transistor (T23), and the second capacitor (Cst2)). At this time, the 21st transistor (T21) of the second pixel (PX2) can receive the first data voltage (Vd1) from the first data line (DL1) through the 12th transistor (T12) of the first pixel (PX1). The driving current provided from the 21st transistor (T21) based on the first data voltage (Vd1) can be supplied to the first anode electrode (AND1) of the first pixel (PX2) through the dummy electrode (DME). Accordingly, the first light-emitting element (ED1) of the first pixel (PX1) can provide light corresponding to the magnitude (or grayscale value) of the first data voltage (Vd1), which is the original data voltage.

[0305] According to one embodiment, the first pixel (PX1) may be a green pixel that provides green light, the second pixel (PX2) may be a blue pixel that provides blue light, and the third pixel (PX3) may be a red pixel that provides red light. In a unit pixel including a red pixel, a green pixel, and a blue pixel, the luminance contribution of the green pixel is the highest, and the luminance contribution of the blue pixel is the lowest. Therefore, when a green pixel with a relatively highest luminance contribution fails, the light-emitting element of the green pixel is driven using a driving current from the pixel circuit of the blue pixel with a relatively lowest luminance contribution, thereby minimizing the defect rate and deterioration of image quality of the display device (100).

[0306] FIGS. 54 to 64 are array diagrams for explaining a method of manufacturing a display device (100) according to one embodiment. For example, FIG. 54 may be a diagram for explaining a repair method of the display device (100) of FIG. 49 described above. Here, FIGS. 55 and 56 are process cross-sectional views taken along line A2-A2' of FIG. 54, FIG. 57 is a process cross-sectional view taken along line A3-A3' of FIG. 54, FIG. 58 is a process cross-sectional view taken along line A4-A4' of FIG. 54, FIG. 59 is a process cross-sectional view taken along line A5-A5' of FIG. 54, FIGS. 60 and 61 are process cross-sectional views taken along line A6-A6' of FIG. 54, and FIGS. 62 to 64 are process cross-sectional views taken along line A7-A7' of FIG. 54.

[0307] A repair process according to one embodiment may be performed, for example, after a protective layer (PAS) is formed. For example, as illustrated in FIG. 55, after the first pattern layer (e.g., the first data line (DL1)), the buffer layer (BF), the second pattern layer (e.g., the eleventh active layer (AC11)), the gate insulating layer (GI), the third pattern layer (e.g., the eleventh gate electrode (G11) and the twelfth gate electrode (G12)), the interlayer insulating layer (ITL), the fourth pattern layer (e.g., the first gate connection electrode (GCE1) and the first anode connection electrode (ACE1)) and the protective layer (PAS) are sequentially disposed on the substrate (SUB), a test process may be performed to detect whether each pixel is defective. After this test process, when it is confirmed that a defect has occurred in the first pixel (PX1) among the first to third pixels (PX1-PX3), the following repair process may be performed.

[0308] For example, as illustrated in FIGS. 54 and 56, the eleventh gate electrode (G11) of the eleventh transistor (T11) may be cut. According to one embodiment, the eleventh gate electrode (G11) of the eleventh transistor (T11) may be cut along the first cutting line (CL1'). For example, as illustrated in FIG. 56, when a laser beam (LB) is irradiated onto the protective layer (PAS) along the first cutting line (CL1), the eleventh gate electrode (G11) on the first cutting line (CL1') may be cut. Accordingly, the eleventh gate electrode (G11) of the eleventh transistor (T11) and the twelfth source electrode (S12) of the twelfth transistor (T12) may be electrically separated from each other.

[0309] According to one embodiment, from a planar viewpoint, at least one of the eleventh gate electrode (G11) and the first gate connection electrode (GCE1) can be cut along the first cutting line (CL1') between the eighth contact hole (CT8) and the channel region (CH11) of the eleventh transistor (T11).

[0310] According to one embodiment, the protective layer (PAS), the first gate connection electrode (GCE1), the interlayer insulating layer (ITL), and the eleventh gate electrode (G11) on the first cutting line (CL1') may be penetrated by the laser beam (LB), and a groove may be formed in the gate insulating layer (GI).

[0311] Next, as illustrated in FIGS. 54 and 57, the eleventh drain electrode (D11) of the eleventh transistor (T11) may be cut. According to one embodiment, the eleventh drain electrode (D11) of the eleventh transistor (T11) may be cut along the second cutting line (CL2'). For example, as illustrated in FIG. 57, when a laser beam (LB) is irradiated onto the protective layer (PAS) along the second cutting line (CL2'), the eleventh drain electrode (D11) on the second cutting line (CL2') may be cut. Accordingly, the eleventh drain electrode (D11) of the eleventh transistor (T11) and the driving voltage line (VDL) may be electrically isolated from each other.

[0312] According to one embodiment, in a planar view, at least one of the eleventh drain electrode (D11), the first driving connection electrode (VCE1) and the first anode connection electrode (ACE1) can be cut along the second cutting line (CL2') between the first contact hole (CT1) and the channel region (CH11) of the eleventh transistor (T11).

[0313] According to one embodiment, the protective layer (PAS), the interlayer insulating layer (ITL), the gate insulating layer (GI) and the eleventh drain electrode (D11) on the second cutting line (CL2') may be penetrated by the laser beam (LB), and a groove may be formed in the buffer layer (BF).

[0314] Next, as illustrated in FIG. 54 and FIG. 58, the 13th drain electrode (D13) and the 13th source electrode (S13) of the 13th transistor (T13) may be cut, respectively. According to one embodiment, the 13th drain electrode (D13) of the 13th transistor (T13) may be cut along the third cutting line (CL3'), and the 13th source electrode (S13) of the 13th transistor (T13) may be cut along the fourth cutting line (CL4').

[0315] For example, as illustrated in FIG. 58, when a laser beam (LB) is irradiated onto the protective layer (PAS) along the third cutting line (CL3'), the 13th drain electrode (D13) on the third cutting line (CL3') can be cut, and when the laser beam (LB) is irradiated onto the protective layer (PAS) along the fourth cutting line (CL4'), the 13th source electrode (S13) on the fourth cutting line (CL4') can be cut. Accordingly, the 13th drain electrode (D13) of the 13th transistor (T13) and the first capacitor (Cst1) can be electrically separated, and also the 13th source electrode (S13) of the 13th transistor (T13) and the initialization voltage line (VIL) can be electrically separated from each other.

[0316] According to one embodiment, in a planar view, at least one of the thirteenth drain electrode (D13) and the first anode connection electrode (ACE1) can be cut along the third cutting line (CL3') between the fifth contact hole (CT5) and the channel region (CH13) of the thirteenth transistor (T13).

[0317] According to one embodiment, in a planar view, at least one of the thirteenth source electrode (S13) and the initialization connection electrode (ICE) can be cut along the fourth cutting line (CL4') between the sixth contact hole (CT6) and the channel region (CH13) of the thirteenth transistor (T13).

[0318] According to one embodiment, the protective layer (PAS), the interlayer insulating layer (ITL), the gate insulating layer (GI), and the 13th drain electrode (D13) on the third cutting line (CL3') may be penetrated by the laser beam (LB), and a groove may be formed in the buffer layer (BF). Furthermore, according to one embodiment, the protective layer (PAS), the interlayer insulating layer (ITL), the gate insulating layer (GI), and the 13th source electrode (S13) on the fourth cutting line (CL4') may be penetrated by the laser beam (LB), and a groove may be formed in the buffer layer (BF).

[0319] Thereafter, as illustrated in FIG. 54 and FIG. 59, the 22nd drain electrode (D22) and the 22nd source electrode (S22) of the 22nd transistor (T22) may be cut, respectively. According to one embodiment, the 22nd drain electrode (D22) of the 22nd transistor (T22) may be cut along the fifth cutting line (CL5'), and the 22nd source electrode (S22) of the 22nd transistor (T22) may be cut along the sixth cutting line (CL6').

[0320] For example, as illustrated in FIG. 59, when a laser beam (LB) is irradiated onto the protective layer (PAS) along the fifth cutting line (CL5'), the 22nd drain electrode (D22) on the fifth cutting line (CL5') can be cut, and when a laser beam (LB) is irradiated onto the protective layer (PAS) along the sixth cutting line (CL6'), the 22nd source electrode (S22') on the sixth cutting line (CL6) can be cut. Accordingly, the 22nd drain electrode (D22) of the 22nd transistor (T22) and the second data line (DL2) can be electrically separated, and also the 22nd source electrode (S22) of the 22nd transistor (T22) and the gate electrode of the 21st transistor (T21) can be electrically separated from each other.

[0321] According to one embodiment, in a planar view, at least one of the 22nd drain electrode (D22) and the second data connection electrode (DCE2) may be cut along the fifth cut line (CL5') between the fifth contact hole (CT5) and the channel region (CH22) of the 22nd transistor (T22).

[0322] According to one embodiment, from a planar viewpoint, at least one of the 22nd source electrode (S22) and the second gate connection electrode (GCE2) may be cut along the sixth cutting line (CL6') between the 6th contact hole (CT6) and the channel region (CH22) of the 22nd transistor (T22).

[0323] According to one embodiment, the protective layer (PAS), the interlayer insulating layer (ITL), the gate insulating layer (GI), and the twenty-second drain electrode (D22) on the fifth cutting line (CL5') may be penetrated by the laser beam (LB), and a groove may be formed in the buffer layer (BF). Furthermore, according to one embodiment, the protective layer (PAS), the interlayer insulating layer (ITL), the gate insulating layer (GI), and the twenty-second source electrode (S22) on the sixth cutting line (CL6') may be penetrated by the laser beam (LB), and a groove may be formed in the buffer layer (BF).

[0324] Next, as illustrated in FIGS. 54 to 60, a first through hole (HL1') exposing the first gate connection electrode (GCE1) and a second through hole (HL2') exposing the second gate connection electrode (GCE2) may be formed. The first through hole (HL1') and the second through hole (HL2') may each penetrate the protective layer (PAS). At this time, a groove may be formed in the first gate connection electrode (GCE1) and the second gate connection electrode (GCE2), respectively, by irradiation with a laser beam (LB). Meanwhile, the above-described first through hole (HL1') and second through hole (HL2') may also be formed by, for example, an etching process instead of the laser beam (LB). For example, the first through hole (HL1') and the second through hole (HL2') can be formed by an etching process that forms the ninth contact holes (CT9, CT9' CT9'') of the aforementioned protective layer (PAS). In this case, the first through hole (HL1'), the second through hole (HL2'), and the ninth contact holes (CT9, CT9' CT9'') can be formed simultaneously by a single etching process.

[0325] Next, as illustrated in FIGS. 54 and 61, a first connection electrode (CNE1') may be disposed on the protective layer (PAS). The first connection electrode (CNE1') may be connected to the first gate connection electrode (GCE1) and the second gate connection electrode (GCE2). For example, one side of the first connection electrode (CNE1') may contact (or directly contact) the first gate connection electrode (GCE1) through the first through hole (HL1'), and the other side of the first connection electrode (CNE1') may contact (or directly contact) the second gate connection electrode (GCE2) through the second through hole (HL2'). Accordingly, the first gate connection electrode (GCE1) and the second gate connection electrode (GCE2) may be electrically connected to each other. In other words, the twelfth source electrode (S12) of the twelfth transistor (T12) may be electrically connected to the twenty-first gate electrode (G21) of the twenty-first transistor (T21) via the first gate connection electrode (GCE1), the first connection electrode (CNE1'), and the second gate connection electrode (GCE2). The first connection electrode (CNE1') may include conductive ink.

[0326] According to one embodiment, the first connection electrode (CNE1') may overlap the first gate connection electrode (GCE1), the driving voltage line (VDL), and the second gate connection electrode (GCE2), as illustrated in FIG. 54.

[0327] According to one embodiment, as illustrated in FIG. 54, the first connection electrode (CNE1') may have a straight line shape that connects the first through hole (HL1') and the second through hole (HL2') in the shortest path.

[0328] Thereafter, as illustrated in FIGS. 54, 62, and 63, the dummy electrode (DME) and the first light-shielding layer (BML1) may be electrically connected to each other. According to one embodiment, the dummy electrode (DME) and the first light-shielding layer (BML1) may be electrically connected to each other in the overlapping region (OV) of the dummy electrode (DME) and the first light-shielding layer (BML1). For example, as illustrated in FIG. 63, when the laser beam (LB) is irradiated onto the protective layer (PAS) in the overlapping region (OV) of the dummy electrode (DME) and the first light-shielding layer (BML1), the dummy electrode (DME) and the first light-shielding layer (BML1) may come into contact (or direct contact) with each other in the overlapping region (OV). Accordingly, the second anode connection electrode (ACE2; or second anode electrode (AND2)) and the first anode connection electrode (ACE1; or first anode electrode (AND1)) can be electrically connected to each other.

[0329] According to one embodiment, the protective layer (PAS), the interlayer insulating layer (ITL), the gate insulating layer (GI) and the buffer layer (BF) may be penetrated by the laser beam (LB) in the overlapping region (OV) of the dummy electrode (DME) and the first light-shielding layer (BML1), and a groove may be formed in the first light-shielding layer (BML1).

[0330] According to one embodiment, a portion of the dummy electrode (DME) in the overlapping region (OV) may be disposed within each of the through holes of the interlayer insulating layer (ITL), the gate insulating layer (GI), and the buffer layer (BF) and within the groove of the first light-shielding layer (BML1).

[0331] Additionally, as illustrated in FIGS. 54 and 64, a second connection electrode (CNE2') may be further disposed on the protective layer (PAS). For example, the second connection electrode (CNE2') may be disposed on the protective layer (PAS) in the overlapping region (OV) and around the overlapping region (OV). A portion of the second connection electrode (CNE2') may be disposed within each through hole of the protective layer (PAS), the interlayer insulating layer (ITL), the gate insulating layer (GI), and the buffer layer (BF) (e.g., a through hole formed by irradiating the laser beam (LB) into the overlapping region (OV) of FIG. 63) and within a groove of the first light-shielding layer (BML1) (e.g., a groove formed by irradiating the laser beam (LB) into the overlapping region (OV) of FIG. 63). At this time, a part of the second connection electrode (CNE2') may be in contact (or direct contact) with the dummy electrode (DME) and the first light-shielding layer (BML1) within the above-described through hole and groove. By the second connection electrode (CNE2'), the connection state between the dummy electrode (DME) and the first light-shielding layer (BML1) may be improved. The second connection electrode (CNE2') may include, for example, conductive ink. Meanwhile, the second connection electrode (CNE2') may be omitted.

[0332] Next, ninth contact holes (CT9, CT9', CT9") that penetrate the protective layer (PAS) and expose the first anode connection electrode (ACE1), the second anode connection electrode (ACE2), and the third anode connection electrode (ACE3) may be formed, and then a via layer (VA) may be formed on the protective layer (PAS). Subsequently, eleventh contact holes (CT11, CT11', CT11") that penetrate the via layer (VA) and expose the first anode connection electrode (ACE1), the second anode connection electrode (ACE2), and the third anode connection electrode (ACE3) may be formed.

[0333] Thereafter, on the via layer (VA), a first anode electrode (AND1), a second anode electrode (AND2), and a third anode electrode (AND3) may be arranged to be connected to a first anode connection electrode (ACE1), a second anode connection electrode (ACE2), and a third anode connection electrode (ACE3) through eleventh contact holes (CT11, CT11', CT11") and ninth contact holes (CT9, CT9', CT9").

[0334] Next, as illustrated in FIG. 54, the second anode electrode (AND2) may be cut. According to one embodiment, the second anode electrode (AND2) may be cut along the seventh cutting line (CL7'). For example, as the laser beam (LB) is irradiated onto the second anode electrode (AND2) along the seventh cutting line (CL7'), the second anode electrode (AND2) on the seventh cutting line (CL7') may be cut. For example, the second anode electrode (AND2) may include a first divided electrode (EE1) and a second divided electrode (EE2) that are separated from each other based on the seventh cutting line (CL7'). The first split electrode (EE1) is connected to the second anode connection electrode (ACE2) through the eleventh contact hole (CT11) and the ninth contact hole (CT9), while the second split electrode (EE2) can be electrically and physically separated from the second anode connection electrode (ACE2). Accordingly, the first split electrode (EE1) can be connected to the twenty-first source electrode (S21) of the twenty-first transistor (T21), while the second split electrode (EE2) can be separated from the twenty-first source electrode (S21) of the twenty-first transistor (T21). At this time, in a planar view as illustrated in FIG. 54, the first split electrode (EE1) can be smaller than the second split electrode (EE2). For example, in a planar view, the area of ​​the first split electrode (EE1) can be smaller than the area of ​​the second split electrode (EE2). Therefore, when the driving current is supplied to the second anode electrode (AND2), the area of ​​the actual light-emitting area of ​​the darkened second pixel (PX2) can be minimized. Here, the actual light-emitting area of ​​the darkened second pixel (PX2) may be an area corresponding to the first segmented electrode (EE1) of the second anode electrode (AND2). For a detailed description of the cutting process of the second anode electrode (AND2) of FIG. 54, refer to FIG. 15 and the related description described above.

[0335] Meanwhile, as illustrated in FIG. 54, a third connection electrode (CNE3) connecting the first split electrode (EE1) of the second anode electrode (AND2) and the first anode electrode (AND1) may be further disposed on the via layer (VA). The third connection electrode (CNE3) may include conductive ink. For a description of this third connection electrode (CNE3'), refer to FIG. 16 and the related description.

[0336] Those skilled in the art will appreciate that the present disclosure may be implemented in other specific forms without altering the technical spirit or essential characteristics thereof. Therefore, the embodiments described above should be understood as illustrative in all respects and not restrictive. The scope of this disclosure is defined by the claims set forth below rather than the detailed description above, and all changes or modifications derived from the meaning and scope of the claims and their equivalents should be construed as being included within the scope of this disclosure.

[0337] Meanwhile, this specification and drawings disclose preferred embodiments of this specification, and although specific terms are used, they are used only in a general sense to easily explain the technical contents of this specification and help understand the invention, and are not intended to limit the scope of this specification. It will be apparent to those skilled in the art to which this specification pertains that other modified examples based on the technical ideas of this specification are possible in addition to the embodiments disclosed herein.

Claims

First light emitting element; A first transistor including a drain electrode connected to a driving voltage line and a source electrode connected to a first anode electrode of the first light-emitting element; A 1-2 transistor including a gate electrode connected to a first scan line, a drain electrode connected to a first data line, and a source electrode connected to the gate electrode of the 1-1 transistor; A first-third transistor including a gate electrode connected to a second scan line, a drain electrode connected to a first anode electrode of the first light-emitting element, and a source electrode connected to an initialization voltage line; Second light emitting element; A second-1 transistor including a drain electrode connected to a driving voltage line and a source electrode connected to a second anode electrode of the second light-emitting element; A 2-2 transistor including a gate electrode connected to the first scan line, a drain electrode connected to the second data line, and a source electrode connected to the gate electrode of the 2-1 transistor; A second-third transistor including a gate electrode connected to the second scan line, a drain electrode connected to the second anode electrode of the second light-emitting element, and a source electrode connected to the initialization voltage line; A first data connection electrode connected to the first data line and the drain electrode of the first-second transistor; and Including a second data connection electrode connected to the second data line and the drain electrode of the second-2 transistor, At least one of the drain electrode of the first-second transistor and the first data connection electrode is cut off, The above second data connection electrode is cut off, A display device in which the second data connection electrode and the first data line are connected to each other. In the first paragraph, The drain electrode of the first-second transistor and the first data connection electrode are connected to each other through the first contact hole of the insulating layer, A display device, in which at least one of the drain electrode of the first-second transistor and the first data connection electrode is cut on the first contact hole, from a planar viewpoint. In the first paragraph, A display device further comprising a first gate connection electrode connected to the source electrode of the first-second transistor and the gate electrode of the first-first transistor. In the third paragraph, A display device in which at least one of the source electrode of the first-second transistor and the first gate connection electrode is cut off. In the fourth paragraph, The source electrode and the first gate connection electrode of the above 1-2 transistor are connected to each other through the second contact hole of the insulating layer, A display device in which at least one of the source electrode of the first-second transistor and the first gate connection electrode is cut on the second contact hole, from a planar viewpoint. In the first paragraph, The second data connection electrode and the second data line are connected to each other through a third contact hole of the insulating layer, The second data connection electrode and the drain electrode of the second-second transistor are connected to each other through the fourth contact hole of the insulating layer, In a planar view, the second data connection electrode is a display device cut between the third contact hole and the fourth contact hole. In the first paragraph, A display device further comprising a drain electrode of the first transistor and a first driving connection electrode connected to the driving voltage line. In paragraph 7, A display device in which the drain electrode of the above-mentioned 1-1 transistor is cut off. In paragraph 8, The drain electrode of the first transistor and the first driving connection electrode are connected to each other through the fifth contact hole of the insulating layer, In a planar view, the drain electrode of the first-first transistor is cut between the fifth contact hole and the channel region of the first-first transistor. In the first paragraph, A first light-shielding layer overlapping the gate electrode of the first transistor; and A display device further comprising a first anode connection electrode overlapping the gate electrode of the first transistor and connected to the first light-blocking layer, the drain electrode of the first transistor, and the first anode electrode. In Article 10, A display device in which the first anode connection electrode is cut off. In Article 11, The first anode connection electrode and the first light-shielding layer are connected to each other through the sixth contact hole of the insulating layer, The first anode connection electrode and the drain electrode of the first-third transistor are connected to each other through the seventh contact hole of the insulating layer, In a planar view, the first anode connection electrode is cut between the sixth contact hole and the seventh contact hole, the display device. In Article 10, A display device in which at least one of the drain electrode of the first-third transistor and the first anode connection electrode is cut off. In the 13th paragraph, The first anode connection electrode and the drain electrode of the first-third transistor are connected to each other through the seventh contact hole of the insulating layer, A display device in which, from a planar viewpoint, at least one of the drain electrode of the first-third transistor and the first anode connection electrode is cut on the seventh contact hole. In the first paragraph, A display device further comprising a source electrode of the first-third transistor and an initialization connection electrode connected to the initialization voltage line. In Article 15, A display device in which at least one of the source electrode of the first-third transistor and the initialization connection electrode is cut off. In Article 16, The source electrode of the above 1-3 transistor and the initialization connection electrode are connected to each other through the 8th contact hole of the insulating layer, A display device in which, from a planar viewpoint, at least one of the source electrode and the initialization connection electrode of the first-third transistor is cut between the eighth contact hole and the channel region of the first-third transistor. In the first paragraph, A display device further comprising a first connection electrode disposed to overlap an intersection area of ​​the second data connection electrode and the first data line, and connected to the second data connection electrode and the first data line. In Article 18, A display device wherein the first connecting electrode includes conductive ink. In the first paragraph, A display device in which the second anode electrode is cut off. In Article 20, Further comprising a second anode connection electrode connected to the second anode electrode, The cut second anode electrode comprises a first split electrode and a second split electrode that are separated from each other, A display device in which the first split electrode is connected to the second anode connection electrode. In Article 21, A display device in which the first split electrodes of the first anode electrode and the second anode electrode are connected to each other. In paragraph 22, A display device further comprising a second connecting electrode connecting the first split electrodes of the first anode electrode and the second anode electrode to each other. In Article 23, A display device in which the second connecting electrode is disposed on the same layer as the first anode electrode and the second anode electrode. In Article 21, A display device in which, from a planar perspective, the size of the first segmented electrode is smaller than the size of the second segmented electrode. In the first paragraph, A pixel definition layer disposed on the first anode electrode and the second anode electrode, defining a first light-emitting region exposing the first anode electrode and a second light-emitting region exposing the second anode electrode; A first light-emitting layer disposed on the first anode electrode corresponding to the first light-emitting area of ​​the pixel definition layer; A second light-emitting layer disposed on the second anode electrode corresponding to the second light-emitting area of ​​the pixel definition layer; and A display device further comprising a common electrode on the first light-emitting layer and the second light-emitting layer. In Article 26, A display device in which the common electrode has a through hole exposing the second light-emitting layer. In Article 27, In a planar view, the size of the through hole is equal to or smaller than the size of the second light-emitting area. In the first paragraph, A first anode connection electrode connected to the first anode electrode; a second anode connection electrode connected to the second anode electrode; and A display device further comprising a third connecting electrode connecting the first anode connecting electrode and the second anode connecting electrode to each other. In paragraph 29, One side of the third connecting electrode is connected to the first anode connecting electrode through the ninth contact hole of the insulating layer, A display device in which the other side of the third connecting electrode is connected to the second anode connecting electrode through the 10th contact hole of the insulating layer. In Article 30, The first anode electrode and the second anode electrode are disposed on the third connecting electrode, The first anode electrode is connected to one side of the third connection electrode through the 11th contact hole of the insulating layer, A display device in which the second anode electrode is connected to the other side of the third connection electrode through the 12th contact hole of the insulating layer. In Article 30, The first anode electrode is connected to the first anode connection electrode through the 13th contact hole of the insulating layer, A display device in which the second anode electrode is connected to the second anode connection electrode through the 14th contact hole of the insulating layer. In the first paragraph, A display device further comprising a fourth connection electrode connecting the first data line and the second data connection electrode to each other. In Article 33, One side of the fourth connecting electrode is connected to the first data line through the first through hole of the insulating layer, A display device in which the other side of the fourth connection electrode is connected to the second data connection electrode through the second through hole of the insulating layer. In the first paragraph, The first data connection electrode overlaps the first data line, A display device in which the second data connection electrode overlaps the first data line and the second data line. In the first paragraph, The first data connection electrode overlaps the first data line and the second data line, A display device in which the second data connection electrode overlaps the second data line. In Article 36, A display device further comprising an auxiliary connection electrode overlapping the first data line and the second data line and connected to the source electrode of the second-second transistor. In Article 37, A display device in which the auxiliary connection electrode is formed integrally with the second data connection electrode. In Article 37, A display device in which the auxiliary connection electrode and the second data line are connected to each other. In paragraph 39, A display device further comprising a fifth connection electrode arranged to overlap with an intersection area of ​​the auxiliary connection electrode and the first data line, and connected to the auxiliary connection electrode and the first data line. In the first paragraph, A display device in which the first light-emitting element and the second light-emitting element provide lights of different colors. In Article 41, A display device wherein the first light-emitting element provides green light and the second light-emitting element provides blue light. First light emitting element; A first transistor including a drain electrode connected to a driving voltage line and a source electrode connected to a first anode electrode of the first light-emitting element; A 1-2 transistor including a gate electrode connected to a first scan line, a drain electrode connected to a first data line, and a source electrode connected to the gate electrode of the 1-1 transistor; A first-third transistor including a gate electrode connected to a second scan line, a drain electrode connected to a first anode electrode of the first light-emitting element, and a source electrode connected to an initialization voltage line; Second light emitting element; A second-1 transistor including a drain electrode connected to a driving voltage line and a source electrode connected to a second anode electrode of the second light-emitting element; A 2-2 transistor including a gate electrode connected to the first scan line, a drain electrode connected to the second data line, and a source electrode connected to the gate electrode of the 2-1 transistor; A second-third transistor including a gate electrode connected to the second scan line, a drain electrode connected to the second anode electrode of the second light-emitting element, and a source electrode connected to the initialization voltage line; A first light-shielding layer overlapping the gate electrode of the first transistor; A first anode connection electrode overlapping the gate electrode of the first transistor and connected to the first light-shielding layer and the drain electrode of the first transistor; and It includes a second anode connection electrode that overlaps with the gate electrode of the second-1 transistor and is connected to the second anode electrode, A display device comprising a dummy electrode extending from the second anode connection electrode and overlapping the first light-blocking layer. In paragraph 43, A display device in which the above dummy electrode and the first light-blocking layer are connected to each other. In Article 44, A display device further comprising a first connection electrode arranged to overlap with an overlapping area of ​​the dummy electrode and the first light-blocking layer, and connected to the dummy electrode and the first light-blocking layer. In Article 45, The first connecting electrode is a display device including conductive ink. In paragraph 43, A display device further comprising a first gate connection electrode connected to the gate electrode of the first-1 transistor and the source electrode of the first-2 transistor. In Article 47, A display device in which at least one of the gate electrode of the first transistor and the first gate connection electrode is cut off. In Article 48, The gate electrode of the above 1-1 transistor and the first gate connection electrode are connected through the first contact hole of the insulating layer, A display device in which, from a planar viewpoint, at least one of the gate electrode of the first-first transistor and the first gate connection electrode is cut between the first contact hole and the channel region of the first-first transistor. In paragraph 43, A display device further comprising a drain electrode of the first transistor and a first driving connection electrode connected to the driving voltage line. In Article 50, A display device in which the drain electrode of the above-mentioned 1-1 transistor is cut off. In paragraph 51, The drain electrode of the first transistor and the first driving connection electrode are connected to each other through the second contact hole of the insulating layer, In a planar view, the drain electrode of the first-first transistor is cut between the second contact hole and the channel region of the first-first transistor. In paragraph 43, A display device in which the drain electrode of the above 1-3 transistor is cut off. In paragraph 53, The first anode connection electrode and the drain electrode of the first-third transistor are connected to each other through the third contact hole of the insulating layer, In a planar view, the drain electrode of the first-third transistor is cut between the third contact hole and the channel region of the first-third transistor. In paragraph 43, A display device further comprising a source electrode of the first-third transistor and an initialization connection electrode connected to the initialization voltage line. In Article 55, A display device in which the source electrode of the above 1-3 transistor is cut off. In paragraph 56, The source electrode of the above 1-3 transistor and the initialization connection electrode are connected to each other through the fourth contact hole of the insulating layer, In a planar view, the source electrode of the first-third transistor is cut between the fourth contact hole and the channel region of the first-third transistor. In paragraph 43, A display device in which the drain electrode of the above-mentioned 2-2 transistor is cut off. In Article 58, A drain electrode of the first-second transistor and a first data connection electrode connected to the first data line; A display device further comprising a drain electrode of the second-second transistor and a second data connection electrode connected to the second data line. In paragraph 59, The second data connection electrode and the drain electrode of the second-second transistor are connected to each other through the fifth contact hole of the insulating layer, In a planar view, the drain electrode of the 2-2 transistor is cut between the fifth contact hole and the channel region of the 2-2 transistor. In paragraph 43, A display device in which the source electrode of the above-mentioned 2-2 transistor is cut off. In Article 58, A first gate connection electrode connected to the gate electrode of the first-1 transistor and the source electrode of the first-2 transistor; and A display device further comprising a second gate connection electrode connected to the gate electrode of the second-1 transistor and the source electrode of the second-2 transistor. In paragraph 62, The second gate connection electrode and the source electrode of the second-second transistor are connected to each other through the sixth contact hole of the insulating layer, A display device in which the source electrode of the 2-2 transistor is cut between the 6th contact hole and the channel region of the 2-2 transistor. In paragraph 43, A first gate connection electrode connected to the gate electrode of the first-1 transistor and the source electrode of the first-2 transistor; and It further includes a second gate connection electrode connected to the gate electrode of the 2-1 transistor and the source electrode of the 2-2 transistor, A display device in which the first gate connection electrode and the second gate connection electrode are connected to each other. In paragraph 64, A display device further comprising a second connection electrode connecting the first gate connection electrode and the second gate connection electrode to each other. In Article 65, One side of the second connection electrode is connected to the first gate connection electrode through the first through hole of the insulating layer, A display device in which the other side of the second connecting electrode is connected to the second gate connecting electrode through a second through hole of the insulating layer. A step of forming, on a substrate, a first transistor including a drain electrode connected to a driving voltage line; a first transistor including a gate electrode connected to a first scan line, a drain electrode connected to a first data line, and a source electrode connected to the gate electrode of the first transistor; a first transistor including a gate electrode connected to a second scan line and a source electrode connected to an initialization voltage line; a second transistor including a drain electrode connected to a driving voltage line; a second transistor including a gate electrode connected to the first scan line, a drain electrode connected to a second data line, and a source electrode connected to the gate electrode of the second transistor; and a second transistor including a gate electrode connected to the second scan line and a source electrode connected to the initialization voltage line; A step of forming a first insulating layer on the 1-1 transistor, the 1-2 transistor, the 1-3 transistor, the 2-1 transistor, the 2-2 transistor, and the 2-3 transistor; A step of forming, on the first insulating layer, a first data connection electrode connected to the first data line and the drain electrode of the first-second transistor; and a second data connection electrode connected to the second data line and the drain electrode of the second-second transistor; A step of forming a second insulating layer on the first data connection electrode and the second data connection electrode; A step of cutting at least one of the drain electrode of the first-second transistor and the first data connection electrode; a step of cutting the second data connection electrode; and A method for manufacturing a display device, comprising the step of connecting the second data connection electrode and the first data line to each other. In Article 67, The drain electrode of the first-second transistor and the first data connection electrode are connected to each other through the first contact hole of the first insulating layer, The step of cutting at least one of the drain electrode of the first-second transistor and the first data connection electrode is: A method for manufacturing a display device, comprising the step of irradiating a laser beam toward a first data connection electrode on the first contact hole on the second insulating layer. In Article 67, A method for manufacturing a display device further comprising the step of forming a first gate connection electrode connected to the source electrode of the first-second transistor and the gate electrode of the first-first transistor on the first insulating layer. In Article 69, A method for manufacturing a display device further comprising the step of cutting at least one of the source electrode and the first gate connection electrode of the first-second transistor. In Article 70, The source electrode of the first-second transistor and the first gate connection electrode are connected to each other through the second contact hole of the first insulating layer, The step of cutting at least one of the source electrode and the first gate connection electrode of the first-second transistor is: A method for manufacturing a display device, comprising the step of irradiating a laser beam toward a first gate connection electrode on the second contact hole on the second insulating layer. In Article 67, The second data connection electrode and the second data line are connected to each other through the third contact hole of the first insulating layer, The second data connection electrode and the drain electrode of the second-second transistor are connected to each other through the fourth contact hole of the first insulating layer, The step of cutting the second data connection electrode is: A method for manufacturing a display device, comprising the step of irradiating a laser beam toward a second data connection electrode between the third contact hole and the fourth contact hole on the second insulating layer. In Article 67, A method for manufacturing a display device, comprising the step of further forming a drain electrode of the first-first transistor and a first driving connection electrode connected to the driving voltage line on the first insulating layer. In paragraph 73, A method for manufacturing a display device further comprising the step of cutting the drain electrode of the first transistor. In paragraph 74, The drain electrode of the first transistor and the first driving connection electrode are connected to each other through the fifth contact hole of the first insulating layer, The step of cutting the drain electrode of the above 1-1 transistor is: A method for manufacturing a display device, comprising the step of irradiating a laser beam toward the drain electrode of the first-first transistor between the fifth contact hole and the channel region of the first-first transistor on the second insulating layer. In Article 67, A step of forming a first light-blocking layer overlapping the gate electrode of the first-first transistor on the substrate; and A method for manufacturing a display device further comprising the step of forming a first anode connection electrode on the first insulating layer, the first anode connection electrode overlapping the gate electrode of the first-1 transistor and connected to the first light-blocking layer and the drain electrode of the first-3 transistor. In paragraph 76, A method for manufacturing a display device, further comprising the step of cutting the first anode connection electrode. In paragraph 77, The first anode connection electrode and the first light-shielding layer are connected to each other through the sixth contact hole of the first insulating layer, The first anode connection electrode and the drain electrode of the first-third transistor are connected to each other through the seventh contact hole of the first insulating layer, The step of cutting the first anode connection electrode is: A method for manufacturing a display device, comprising the step of irradiating a laser beam toward a first anode connection electrode between the sixth contact hole and the seventh contact hole on the second insulating layer. In paragraph 76, A method for manufacturing a display device, further comprising the step of cutting at least one of the drain electrode of the first-third transistor and the first anode connection electrode. In paragraph 79, The first anode connection electrode and the drain electrode of the first-third transistor are connected to each other through the seventh contact hole of the first insulating layer, The step of cutting at least one of the drain electrode of the first-third transistor and the first anode connection electrode is: A method for manufacturing a display device, comprising the step of irradiating a laser beam toward a first anode connection electrode on a seventh contact hole on the second insulating layer. In Article 67, A method for manufacturing a display device further comprising the step of forming, on the first insulating layer, a source electrode of the first-third transistor and an initialization connection electrode connected to the initialization voltage line. In paragraph 81, A method for manufacturing a display device further comprising the step of cutting at least one of the source electrode and the initialization connection electrode of the first to third transistors. In paragraph 82, The source electrode of the first-third transistor and the initialization connection electrode are connected to each other through the eighth contact hole of the first insulating layer, The step of cutting at least one of the source electrode and the initialization connection electrode of the above 1-3 transistor is: A method for manufacturing a display device, comprising the step of irradiating a laser beam toward an initial connection electrode between the eighth contact hole and the channel region of the first-third transistor on the second insulating layer. In Article 67, The step of connecting the second data connection electrode and the first data line to each other is: A method for manufacturing a display device, comprising the step of irradiating a laser beam toward an overlapping area of ​​the second data connection electrode and the first data line on the second insulating layer. In paragraph 84, A method for manufacturing a display device further comprising the step of forming a first connection electrode connected to the second data connection electrode and the first data line on the second insulating layer in an overlapping area of ​​the second data connection electrode and the first data line. In Article 85, A method for manufacturing a display device in which the first connecting electrode is formed of conductive ink. In Article 67, A step of forming a first anode connection electrode connected to the source electrode of the 1-1 transistor and a second anode connection electrode connected to the source electrode of the 2-1 transistor on the first insulating layer; A step of forming a third insulating layer on the second insulating layer; A step of forming a first anode electrode connected to the first anode connection electrode and a second anode electrode connected to the second anode connection electrode in the third insulating layer; A step of cutting the second anode electrode to form a first split electrode connected to the second anode connection electrode and a second split electrode separated from the second anode connection electrode; and A method for manufacturing a display device further comprising the step of connecting the first anode electrode and the first split electrode. In Article 87, The step of connecting the first anode electrode and the first split electrode is: A method for manufacturing a display device, comprising the step of forming a second connecting electrode connecting the first anode electrode and the first split electrode on the third insulating layer. In Article 87, A step of forming a pixel definition layer defining a first light-emitting area and a second light-emitting area on the first anode electrode and the second anode electrode; A step of forming a first light-emitting layer and a second light-emitting layer on the first light-emitting region and the second light-emitting region, respectively; and A step of forming a cathode electrode on the first light-emitting layer and the second light-emitting layer; A method for manufacturing a display device further comprising the step of removing a cathode electrode corresponding to the second light-emitting region. A step of forming, on a substrate, a first transistor including a drain electrode connected to a driving voltage line; a first transistor including a gate electrode connected to a first scan line, a drain electrode connected to a first data line, and a source electrode connected to the gate electrode of the first transistor; a first transistor including a gate electrode connected to a second scan line and a source electrode connected to an initialization voltage line; a second transistor including a drain electrode connected to a driving voltage line; a second transistor including a gate electrode connected to the first scan line, a drain electrode connected to a second data line, and a source electrode connected to the gate electrode of the second transistor; a second transistor including a gate electrode connected to the second scan line and a source electrode connected to the initialization voltage line; and a first light-blocking layer overlapping the gate electrode of the first transistor; A step of forming a first insulating layer on the first transistor, the first transistor, the first transistor, the second transistor, the second transistor, the second transistor, and the first light-blocking layer; A method for manufacturing a display device, comprising the steps of forming, on the first insulating layer, a first anode connection electrode overlapping the gate electrode of the 1-1 transistor and connected to the first light-blocking layer and the drain electrode of the 1-3 transistor; a second anode connection electrode overlapping the gate electrode of the 2-1 transistor; and a dummy electrode extending from the second anode connection electrode and overlapping the first light-blocking layer. In Article 90, A method for manufacturing a display device further comprising the step of connecting the dummy electrode and the first light-blocking layer to each other. A step of disconnecting the connection between the first pixel circuit of the first pixel and the first signal lines; A step of disconnecting the connection between the second pixel circuit of the second pixel and the second signal line; A step of connecting the second pixel circuit of the second pixel and one of the first signal lines to each other; and A step of connecting the second anode electrode of the second pixel and the first anode electrode of the first pixel to each other, A method for manufacturing a display device in which the visibility of the first pixel is higher than the visibility of the second pixel. In paragraph 92, The step of disconnecting the connection between the first pixel circuit and the first signal lines is: A step of disconnecting the connection between the first pixel circuit of the first pixel and the first data line; A step of disconnecting the connection between the first pixel circuit of the first pixel and the first scan line; and A step of disconnecting the connection between the first pixel circuit of the first pixel and the driving voltage line, The step of disconnecting the connection between the pixel circuit of the second pixel and the second signal line includes the step of disconnecting the connection between the second pixel circuit of the second pixel and the second data line, A method for manufacturing a display device, wherein the step of connecting the second pixel circuit of the second pixel and one of the first signal lines includes the step of connecting the second pixel circuit of the second pixel and the first data line to each other. In paragraph 92, The above first pixel is a pixel that provides green light, A method for manufacturing a display device in which the second pixel is a pixel that provides blue light. In paragraph 92, The above first pixel is a pixel that provides red light, A method for manufacturing a display device in which the second pixel is a pixel that provides blue light.

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