High-throughput entropy decoding architecture

The high-throughput decoding architecture with parallel decoders and a free-space arbitration scheme addresses bandwidth mismatches, enhancing decoding efficiency and throughput for neural network computations.

WO2025250144A1PCT designated stage Publication Date: 2025-12-04GOOGLE LLC
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Patent Information

Application Number
PCT/US2024/032108
Authority / Receiving Office
WO · WO
Patent Type
Applications
Current Assignee / Owner
Filing Date
2024-05-31
Publication Date
2025-12-04

AI Technical Summary

Technical Problem

Existing data decoding technologies face challenges in achieving high-throughput data transfers due to bandwidth mismatches and throughput bottlenecks, particularly in the context of neural network computations, where Huffman decoding is a low-bandwidth operation that limits performance in high-throughput scenarios.

Method used

A high-throughput decoding architecture is implemented using a hardware integrated circuit with multiple decoders operating in parallel, employing a free-space based arbitration scheme to manage buffer space efficiently, ensuring consistent data flow and reducing latency through a block interleaved decoding technique.

Benefits of technology

This approach enhances decoding efficiency and throughput, enabling efficient decompression of machine-learning data, reducing memory space and bandwidth requirements, and improving compute utilization and energy consumption.

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Abstract

Methods and systems, including computer-readable media, are described for high-throughput data decoding at an integrated circuit. A system receives addresses that specify memory locations storing encoded data at a memory device. Each of the addresses are provided by a respective decoder of the circuit. For each address: the system generates a request for an encoded block of an encoded data stream that includes multiple encoded blocks. Over multiple clock cycles, the system processes each of the requests corresponding to the addresses based on available buffer space for storing encoded data in at least one of the decoders. In response to processing each request, the system retrieves multiple encoded blocks from non-contiguous memory locations of the memory and decodes the encoded blocks based on an interleaved configuration used to generate a corresponding encoded data stream. A portion of the encoded blocks are decoded in parallel across two or more decoders.
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Citation Information

Patent Citations

  • Entropy coding supporting mode switching

    US20180109813A1

  • Variable width interleaved coding for graphics processing

    US20220301228A1