Wide parallel access

Abstract

Multiple (e.g., four) stacks of dynamic random access memory (DRAM) devices are coupled with, and attached to, a buffer device to form a memory assembly. The buffer device interfaces between a controller (e.g., host) and the memory device stacks such that each memory device stack function as independent memory subchannels. The buffer device serializes, deserializes, and sequences commands and data communicated between the host and the memory device stacks such that DRAM timing constraints (e.g., column-to-column access delay - tCCD_S) are decoupled from the host interface timing and / or protocol. This decoupling may increase host interface / bus utilization. In other words, for example, the memory device stacks may be accessed using a relatively (relative to the host interface) wide and slow parallel command and data interface while the host interface communicates at a high (relative to tCCD_S) per pin bitrate.

Description

WIDE PARALLEL ACCESSBRIEF DESCRIPTION OF THE DRAWINGS

[0001] Figure l is a diagram illustrating an example memory system.

[0002] Figure 2 is a block diagram illustrating a buffer device.

[0003] Figures 3 A-3E are diagrams illustrating a memory device.

[0004] Figures 4A-4B are diagrams illustrating interconnections of an example memory device stack.

[0005] Figures 5A-5B are timing diagrams illustrating example read operations directed to multiple memory device stack subchannels.

[0006] Figure 6A-6B are timing diagrams illustrating example read and write operations directed to multiple memory device stack subchannels.

[0007] Figure 7 is a diagram illustrating an example wide-narrow modal memory device floorplan.

[0008] Figure 8 illustrates an example memory assembly with subchannel die stacks overlapping quadrants of a buffer device.

[0009] Figure 9 is a flowchart of a method of operating a memory assembly.

[0010] Figure 10 is a flowchart of a method of accessing multiple subchannel memory stacks of a memory assembly.

[0011] Figure 11 is a flowchart of method of accessing data and error detection and correction information using multiple subchannel memory stacks of a memory assembly.

[0012] Figure 12 is a block diagram of a processing system.DETAILED DESCRIPTION OF THE EMBODIMENTS

[0013] In an embodiment, multiple (e.g., four) stacks of dynamic random access memory (DRAM) devices are coupled with, and attached to, a buffer device to form a memory assembly. The buffer device interfaces between a controller (e.g., host) and the memory device stacks such that each memory device stack functions as independent memory subchannels. In an embodiment, the buffer device serializes, deserializes, and sequences commands and data communicated between the host and the memory device stacks such that DRAM timing constraints (e.g., column-to-column access delay - tccD s) are decoupled from the host interface timing and / or protocol. This decoupling may increase host interface / bus utilization. In other words, for example, the memory device stacks may be accessed using a relatively (relative to the host interface) wide and slow parallel command and data interface while the host interface communicates at a high (relative to tccD s) per pin bitrate. Forexample, the buffer device may communicate with the controller using two 10-bit wide unidirectional links while each of ten (10) memory devices in each memory device stack receive commands via a 38-bit wide command address bus, and communicate data via respective 64-bit data busses. The buffer device may serialize, deserialize, and sequence commands and data such that in-order execution of commands from the host is maintained.

[0014] Figure 1 is a diagram illustrating an example memory system. In Figure 1, memory system 100 comprises assembly 110 and controller 120. Assembly 110 includes memory device stacks 130a-130b and buffer device 140. Buffer device 140 includes host / controller unidirectional transmit interface 141, host / controll er unidirectional receive interface 142, control circuitry 145, memory subchannel interface “A” 146a and memory subchannel interface “B” 146b. Memory device stacks 130a- 130b respectively include memory integrated circuit devices 130aa-130ae and memory integrated circuit devices 130ba- 130be.

[0015] Each of memory devices 130aa-130be respectively include memory arrays 135aa- 135be and memory subchannel interfaces 136aa-136be. Memory device stack 130a is operatively coupled with buffer device 140 via memory subchannel interface A 137a and memory subchannel 137a. Each of memory integrated circuits 130aa-130ae of memory device stack 130a are respectively operatively coupled with buffer device 140 via memory subchannel interfaces 136aa-136ae, memory subchannel 137a, and memory subchannel interface A 137a. Memory device stack 130b is operatively coupled with buffer device 140 via memory subchannel interface A 137b and memory subchannel 137b. Each of memory integrated circuits 130ba-130be of memory device stack 130b are respectively operatively coupled with buffer device 140 via memory subchannel interfaces 136ba-136be, memory subchannel 137b, and memory subchannel interface B 146b.

[0016] In Figure 1, two memory device stacks 130a-130b are illustrated. However, it should be understood that this is representative. Additional memory device stacks (e.g., 2 additional for a total of four) may interface with buffer device 140 via appropriate memory subchannel interfaces (e.g., a memory subchannel interface “C” and a memory subchannel interface “D”).

[0017] Controller 120 and memory devices 130aa-130be may be integrated circuit type device, such as are commonly referred to as “chips”. A memory controller, such as controller 120, manages the flow of commands and data got to and from memory devices and / or memory assemblies. A memory controller can be a separate, standalone chip, or integrated into another chip. For example, a memory controller may be included on a single die with amicroprocessor, or included as part of a more complex integrated circuit system such as a clock of a system on a chip (SoC).

[0018] Controller 120 includes unidirectional receive interface (Rx) 121, unidirectional transmit interface (Tx) 122, and control circuitry 125. Receive interface 121 of controller 120 is operatively coupled to transmit interface 141 of buffer device 140 of assembly 110. Transmit interface 122 of controller 120 is operatively coupled to receive interface 142 of buffer device 140 of assembly 110. Thus, it should be understood that, in an embodiment, controller 120 is operatively coupled with assembly 110 via unidirectional communication links.

[0019] In an embodiment, each of memory device stacks 130a-130d respectively include ten (10) memory devices that are interconnected and stacked with each other. However, other numbers of devices (e.g., 8, 12, 14, 20, etc.) are contemplated. In an embodiment, eight of the ten memory devices in each memory device stack 130a-130b are used to store data, and two memory devices in each memory device stack 130a- 130b are used to store error detection and correction (EDC) information.

[0020] In an embodiment, the EDC information stored by the memory devices in a memory device stack (e.g., memory device stack 130a) is associated with (i.e., protects) the data stored by the memory devices in that memory device stack (e.g., memory devices 130aa- 130ae). In another embodiment, the EDC information stored by the memory devices in a memory device stack (e.g., memory device stack 130a) is associated with (i.e., protects) the data stored by the memory devices in a different memory device stack (e.g., memory devices 130ba-130be in memory device stack 130b). In this manner, a “die kill” level of EDC protection may be achieved. “Die kill” refers to the ability to detect and correct errors that affect all bits transmitted by a single die in an accessed DRAM stack. Common EDC code require 2 times (2x) the amount of bits (symbols) to detect and correct a symbol worth of bits. For example, if a die provides 64 bits of data per access (1 symbol), then 128 EDC bits (2 symbols) are required to perform the “die kill” correction.

[0021] In an embodiment, memory device stacks 130a-130b of assembly 110 each function as separate independent memory subchannels. Thus, assembly 101 may function and appear to controller 120 as four separate and independent memory channels whose commands and data must pass through, and are ordered by, a single interface with buffer device 140. To access one of memory stacks 130a-130b of assembly 110, controller 120 may transmit a command packet via transmit interface 122 and receive interface 142 thatcombines both row operations, column operations, and associated row and column address information.

[0022] Based on commands from controller 120 received via receive interface 142, buffer device accesses memory device stacks 130a- 13 Ob. For example, in response to a command from controller 120, buffer device 140 (and control circuitry 145, in particular) may translate the command packet into command and address transaction (e.g., precharge, activate, read, write, refresh, mode register set, etc.) that are compatible with memory channel interfaces 136aa-136be of memory device 130aa-130be, and transmit those command and address transactions to the addressed memory stack 130a- 130b via the corresponding subchannel interface 146a-146b. Based on the command and address transaction, data is communicated between the individual memory devices (e.g., memory devices 130aa-130ae) of the memory device stack (e.g., memory device stack 130a) via the corresponding memory subchannel (e.g., memory subchannel 137a). Also, in response to the command, buffer device 140 serializes or deserializes, as appropriate, data communicated via the accessed memory subchannel 137a- 137b.

[0023] For example, in response to a read command from controller 120 directed to memory subchannel 137a (i.e., memory device stack 130a), buffer device 140 may issue a read command sequence (e.g., ACT, RD) via memory subchannel interface 146a. In response, each of the memory device 130aa-130ae respectively provides one access granularity worth of data bits read from its memory array 135aa-135ae in parallel (e.g., 64 bit access granularity). Buffer device 140 serialized the data received via memory subchannel A 137a into a data packet with less width (i.e., fewer bits, more and higher speed transfers) than was used to transfer data via memory subchannel 137a. In an embodiment, each of the accessed memory devices (e.g., 8 devices) provides 64 bits of data concurrently (overlapping but not necessarily with the same timing), which is then serialized by buffer device 140 down to eight (8) bits and transmitted to controller 120 at a much smaller (e.g., l / 8thor less) transfer interval (a.k.a., time between symbols).

[0024] Thus, it should be understood that, in an embodiment, memory system 100 includes a high-speed unidirectional interface between buffer device 140 and controller 120. Memory system 100 may also include, in an embodiment, a core access speed (e.g., cycling at, for example, a selected or specified column-to-column access interval - sometimes referred to as tcco s) cycling of accesses to memory device stacks 130a-130b. This slower and simpler interface (relative to a higher-speed, more serialized interface) between memorydevices 130aa-130be and buffer device may not need a training sequence / period to ensure reliable operation - thereby increasing the availability of memory system 100.

[0025] The unidirectional high-speed interface between controller 120 and buffer device 140 may allow for overlapping accesses between subchannels 137a-137b. These overlapping accesses may include read and write accesses mixed with each other. Overlapping same accesses (e.g. read accesses) may reduce transport latency between controller 120 and memory device stacks 130a- 130b. In an embodiment, the protocol used between buffer device 140 and controller 120 preserves the order of execution of accesses to memory device stacks 130a- 130b. In an embodiment, the protocol used between buffer device 140 and controller 120 is decoupled from the DRAM timing parameters of memory devices 130aa- 130be. This may allow for controller 120 to more efficiently schedule accesses to memory device stacks 130a- 130b.

[0026] For another example, consider an assembly 110 where: (1) each memory device stack 130a- 130b includes ten (10) memory devices 110aa-l lObe; (2) eight memory devices of each memory device stack 130a- 130b are configured or assigned to store data; (3) two memory devices of each memory device stack 130a- 130b are configured or assigned to store EDC information; (4) transmit interface 122, receive interface 142, transmit interface 141, and receive interface 121 are all ten bits wide (i.e., each communicates via ten data links - e.g., ten single-ended signaling wires or twenty differential signaling wires), where eight bits are assigned / configured to communicate data and two are assigned / configured to communicate EDC information; and (5) each memory device 130aa-130be communicates bidirectionally and in parallel with buffer device 140 64 bits per communication transfer (i.e., each communicates via 64 data links - e.g., 64 single-ended signaling wires or 128 differential signaling wires). In this example, buffer device 140 would communicate 512 bits of data from / to an accessed memory device stack 130a- 130b per column-to-column cycle and 128 bits of EDC information per column-to-column cycle. For a read, buffer device serializes data from the accessed memory device stack into eight-bit wide transfers (i.e., number of data links assigned to data), and serializes the EDC from the accessed memory device stack for communication to controller 120. For a write, buffer device deserializes data from the eight-bit transfers from controller into 512 bit wide transfers to the accessed memory device stack, and deserializes the EDC information from the two bit transfers from controller into 128 bit wide transfers to the accessed memory device stack. To generalize this example, if data blocks communicated with memory stacks 130a-130b are N (e.g., N=512) number of bits in size, the parallel transfer units communicated with controller are M (e.g.,M=8) number of bits in size, the data bursts with controller 120 have P number of parallel transfer units, where P is equal to N divided by M (e.g., P=64=512 / 8), and N, M, and P are positive integers greater than two.

[0027] As discussed herein, EDC information and data may, in response to the same command to assembly 101, be accessed using different memory device stacks. In this embodiment, for a read, buffer device serializes data from the addressed memory device stack into eight-bit wide transfers (i.e., number of data links assigned for data), and serializes the EDC from a different (e.g., hardwired, command specified, and / or mode specified) memory device stack for communication to controller 120. For a write, buffer device deserializes data from the eight-bit transfers from controller into 512 bit wide transfers to the addressed memory device stack, and deserializes the EDC information from the two bit transfers from controller into 128 bit wide transfers to the different memory device stack.

[0028] As discussed herein, buffer 140 and / or memory devices 130aa-130be of memory stacks 130a-130b may be placed in, and / or operate in various modes (e.g., by setting values in registers). These modes include, but are not limited to, a “wide” mode, a “narrow” mode”, a “bottom die” mode, an EDC information access mode, and so on. These modes may be set and / or entered via a variety of techniques and / or methods that communicate to buffer 140 and / or memory devices 130aa-130be the mode they are to assume and / or operate according to. These techniques and methods may include, but are not limited to, for example, register programming (e.g., mode register set command), tying a pin to a specific voltage, power on detection of signal levels that programs a register to set the mode (e.g., at a packaging stage, after disposition in a system, etc.), information provided with an access command (e.g., mode bit in a command field), and / or information accompanying a command (e.g., mode / data / access type signal generated by buffer 140 in response to a command and provided to one or more of memory devices 130aa-130be).

[0029] Figure 2 is a block diagram illustrating a buffer device. In Figure 2, buffer device 200 comprises data transmit interface 24 Id, EDC information transmit interface 24 le, data receive interface 242d, EDC information receive interface 242e, data serializer 25 Id, EDC information serializer 25 le, deserializer 252d, EDC information deserializer 252e, packet selector 253, EDC check circuitry 254, command / address (CA) sequencer 255, data read first-in first-out buffer (FIFO) 261, EDC read FIFO 262, column address FIFO 263, row address FIFO 264, command FIFO 265, data write FIFO 266, EDC information FIFO 267, data read multiplexor (MUX)271, EDC read MUX 272, column address demultiplexer (DMUX) 273, row address DMUX 274, command DMUX 275, write data DMUX 276, andEDC information DMUX 277, channel “A” data through-silicon vias (TSVs) 281, channel “A” EDC TSVs 282, and channel “A” command / address (CA) TSVs 283. Buffer device 200 may be an example of buffer device 140.

[0030] Channel A data TSVs are operatively coupled with an input of data MUX 271 and an output of write data DMUX 276. Channel A EDC TSVs are operatively coupled with an input of EDC MUX 272 and an output of EDC DMUX 277. Channel A CA TSVs are operatively coupled with an output of column address DMUX 273, row address DMUX 274, and command DMUX 275. In Figure 2, the other inputs of MUXs 271-272 and other outputs of DMUXs 273-277 are not illustrated as being connected. However, it should be understood that these inputs and outputs are connected to TSVs for another three subchannels (e.g., subchannels B, C, and D) in order to steer commands and data to / from those subchannels in a manner similar to that shown in Figure 2 with respect to subchannel A. In other words, in Figure 2, these additional TSV groups B-D have not been illustrated for the purposes of brevity and clarity. In an embodiment, the TSVs for each subchannel A-D are each located in different quadrants of buffer device 200.

[0031] Data receive interface 242d receives commands, addresses, and write data (e.g., from controller 120). These commands, addresses, and data are provided to deserializer 252d. The deserialized commands, addresses, and data are provided to packet selector 253. Packet selector 253 distributes column addresses to column address FIFO 263, row addresses to row address FIFO 264, commands to command FIFO 265, and write data to write FIFO266. CA sequencer 255 at least controls column address FIFO 263, row address FIFO 264, and command FIFO 265 to output, via the corresponding DMUXs 273-275, sequences of commands and addresses according to the protocol of subchannels A-D. Column address DMUX 273, row address DMUX 274, and command DMUX 275 steer, under the control of CA sequencer 255 and / or control circuitry 245, these sequences of commands and addresses to the subchannel A-D specified by the host.

[0032] Similarly, control circuitry 245 controls data FIFO 266, EDC information FIFO267, write data DMUX 276, and EDC DMUX 277 to respectively steer, to the appropriate subchannel A-D and at the appropriate time, write data and EDC information. Read data from a memory device stack is supplied by subchannels A-D to data MUX 271. EDC information read from a memory device stack is supplied by subchannels A-D to EDC MUX 272. Control circuitry 245 controls read data MUX 271, EDC MUX 272, read data FIFO 261, EDC information FIFO 262, to respectively select and buffer, from the appropriate subchannel A-D and at the appropriate time, read data and EDC information. The output ofdata FIFO 261 is provided to serializer 25 Id. The output of EDC FIFO 262 is provided to serializer 25 le. The output of serializer 25 Id is provided to data transmit interface 24 Id. The output of serializer 25 le is provided to EDC information transmit interface 24 le.

[0033] Figures 3 A-3E are diagrams illustrating a memory device. In Figures 3 A-3E, memory device 300 comprises active circuitry (top) side 301, bottom (no active circuitry) side 302, memory array 335, memory array control circuitry 331, command / address multiplexor 332, buffer and deserializer 333, command / address receivers 334, narrow mode command / address (CA) pads 385, latch 336, transfer gates 337, receiver / buffer 338, wide mode command / address (CA) pads 383, narrow mode data pads 386, CA TSV group 373, narrow mode receivers 341, deserializer 342, write data MUX 345, read data DMUX 346, serializer 347, narrow mode data drivers 348, wide mode data pad groups 38 la-38 Id, transfer gates and buffer functions 361a-361d, data FIFOs 362a-362d, data pad / TSV shift 350, and data TSV groups 37 la-37 Id.

[0034] Wide mode CA pads 383 are operatively coupled with buffer 338. The output of buffer 338 is operatively coupled with transfer gates 337 and CA TSV group 373. Transfer gates 337 are controlled by an external signal ENECC. The output of transfer gates 337 is operatively coupled with the input to command / address latch 336. Latch 336 is controlled (clocked) by an internally clock signal ICLK, which is derived from an externally provided clock (not shown). The externally provided clock may be provided by the buffer 140. The output of latch 336 is operatively coupled to a first input of CA MUX 332. The output of CA MUX 332 is operatively coupled to array control circuitry 331. Array control circuitry 331 provides memory cell array 335 with control signals, row address signals, and column address signals.

[0035] Narrow mode CA pads 385 are operatively coupled to narrow mode CA receivers334. The output of CA receivers 334 is operatively coupled to buffer and deserializer 333, the output of deserializer 333 is operatively coupled to a second input to CA MUX 332. Narrow mode data pads 386 are operatively coupled to narrow mode receivers 341 and narrow mode data drivers 348. The output of narrow mode receivers 341 is operatively coupled to deserializer 342. The output of deserializer 342 is operatively coupled to a first input of write data MUX 345. The output of write data MUX is operatively coupled to array335.

[0036] Array 335 is also operatively coupled to the input of read data DMUX 346. A first output of read data DMUX 346 is operatively coupled to serializer 347. The output of serializer 347 is operatively coupled to narrow mode data drivers 348. The output serializer347 and narrow mode data drivers 348 may be timed by an output clock (not shown) derived from an DLL 355. The output of data drivers 348 is operatively coupled to narrow mode data pads 386.

[0037] A second output of read data DMUX 346 is operatively coupled to latch 343, FIFO 362a, and transfer gates 361a. Latch 363 is controlled (clocked) by the clock signal ICLK. A data strobe signal DS generated by memory device 300 may, when FIFO 362a is enabled, control (clock) the input to FIFO 362b. A control signal BDC (a.k.a., Bottom Die Control) indicates whether memory device 300 is the bottom die in a memory device stack and should therefore operate in a “bottom die” mode or a “non-bottom die” mode. In particular, in a “bottom die” mode, data from array 335 or from other memory devices in the memory device stack and received via data TSV groups 37 la-37 Id should be respectively stored in FIFOs 362a-362d. In a “non-bottom die” mode, data from array 335 or from other memory devices in the memory device stack and received via data TSV groups 371a-371d is routed (after being shifted by shift 350, if appropriate) directly to wide mode data pad groups 38 la-38 Id without first being stored in a FIFO 362a-362d.

[0038] The output of FIFO 362a is controlled (clocked) by an external strobe signal (e.g., generated by a buffer device) DOS (a.k.a., Data Output Strobe). The output of FIFO 362a is operatively coupled to buffer / transfer gates 361a. The outputs of transfer gates / buffer 36 la-36 Id are operatively coupled with wide mode data pad groups 38 la-38 Id.

[0039] Data TSV group 371a is operatively coupled with FIFO 362b and transfer gates 361b via shift 350. A data strobe signal DS[1] provided by the die immediately above memory device 300 may, when FIFO 362b is enabled, control (clock) the input to FIFO 362b. Data TSV group 371b is operatively coupled with FIFO 362c and transfer gates 361c via shift 350. A data strobe signal DS[2] provided by the die two dies above memory device 300 may, when FIFO 362c is enabled, control (clock) the input to FIFO 362c. This pattern continues for N number of wide mode pad groups 38 lb-38 Id, transfer gates 361b-361d, and data TSV groups 37 lb-371 d. In an embodiment, data TSV groups 371a-371d are disposed such that when memory devices are stacked, data TSV group 371a is coupled to wide mode data pad group 381a, data TSV group 371b is coupled to wide mode data pad group 381b, and so on.

[0040] Because shift 350 moves the data communicated via each DQ TSV group to the right (in Figure 2) by one TSV group, data communicated with the memory device immediately above a particular memory device in the stack via data TSV group 371a is communicated with the device immediately below this particular memory device in the stackvia wide mode data pad group 381b. Likewise, because of the shift 350 in the memory device two dies above the current memory device, data communicated with the memory device two dies above the particular memory device in the stack via data TSV group 371b is communicated with the device immediately below this particular memory device in the stack via wide mode data pad group 381c, and so on for the other dies disposed above of this particular memory device die.

[0041] In narrow mode operation, wide mode CA pads 383, buffer 338, CA TSV group 373, wide mode pad groups 38 la-38 Id, transfer gates 36 la-36 Id, FIFOs 362a-362d and data TSV groups 371a-371d are not used and / or not enabled. In narrow mode operation, CA MUX 332 is set to provide commands / addresses received via narrow mode pads 385 to array control circuitry 331. In narrow mode operation, write data MUX 345 is set to provide data received via narrow mode data pads 386 and deserialized by deserializer 342 to array 335. In narrow mode operation, read data DMUX 346 is set to provide data received from array 335 and serialized by serializer 347 to narrow mode data pads 386.

[0042] In narrow mode operation, commands and addresses (e.g., a read command and associated row and column addresses) are received at narrow mode CA pads 385 and coupled to array control circuitry 331 via CA receivers 334, deserializer 333, and CA MUX 332.Array control circuitry 331 controls array 335 to access the addressed data in array 335. This is illustrated in Figure 3B by arrow 391 running from narrow mode CA pads 385 to array 335 via CA receivers 334, deserializer 333, CA MUX 332, and array control circuitry 331. Based on a read command, for example, data accessed from array 335 is routed by read data DMUX 346 to serializer 347. Serializer 347 serializes the accessed data and provides it to data drivers 348 where the serialized data is output via narrow mode data pads 386. This is illustrated in Figure 3B by arrow 392 running from array 335 to narrow mode data pads via read data DMUX 346, serializer 347, data drivers 348, and through narrow mode data pads 386.

[0043] The narrow mode of the memory device is intended for instances when the memory device is used as a standalone device, or packaged in a single die package as part of a memory module (e.g., on a DIMM). The narrow data interface transmits / receives an access granularity worth of bits at a parallel unit interval which is much shorter than tccD s. For example, if the access granularity is 64b and the narrow data interface is 4b, the unit transfer time is (tccD s / 64)*4 = tccD s / 16.

[0044] The wide operation mode is intended for instances where the memory die is used in a manner similar to that illustrated in Fig. 1 where the data interface receives / transmits dataover a wide data interface. For example, if the data interface width matches the access granularity of the memory device, the parallel unit interval equals tccD s. I.e., (tccD s / 64)x64= tccD s.

[0045] In wide and non-bottom die mode operation, and wide and bottom die mode operation, narrow mode CA pads 385, CA receivers 334, deserializer 333, narrow mode data pads 386, narrow mode data receivers 341, deserializer 342, serializer 347, and narrow mode data drivers 348 are not used and / or not enabled. In wide and non-bottom die mode operation, and wide and bottom die mode operation, operation, CA MUX 332 is set to provide commands / addresses received via wide mode CA pads 383 and synchronized to ICLK by latch 336 to array control circuitry 331. In wide and non-bottom die mode operation, and wide and bottom die mode operation, write data MUX 345 is set to provide parallel data received via wide mode data pad group 381a and synchronized to ICLK by latch 343 to array 335.

[0046] In wide and non-bottom die mode operation, read data DMUX 346 and transfer gates 361a are set to provide parallel data received from array 335 to wide mode data pad group 381a. In wide and bottom die mode operation, read data DMUX 346 and transfer gates 361a are set to provide parallel data received from array 335 to FIFO 362a and transfer gates 361a are set to provide parallel data received from FIFO 362a to wide mode data pad group 381a.

[0047] In wide non-bottom die mode operation, commands and addresses (e.g., a read command and associated row and column addresses are receive at wide mode CA pads 383 in parallel and coupled to array control circuitry 331 via buffer 338, transfer gates 337, latch 336 (to synchronize CA signals to internal clock ICLK), and CA MUX 332. This is illustrated in Figure 3C by arrow 393b running from wide mode CA pads 383 to array 335 via buffer 338, transfer gates 337, latch 336, CA MUX 332, and array control circuitry 331. Array control circuitry 331 controls array 335 to access the addressed data in array 335. In wide non-bottom die mode operation, commands and addresses are also coupled to CA TSV group 373 after being buffered by buffer 338. This is illustrated in Figure 3C by arrow 393a breaking off from arrow 393b after buffer 338 and running through CA TSV group 373.

[0048] Based on a read command, for example, in wide non-bottom die mode, data accessed from array 335 is routed by read data DMUX 346 to wide mode data pad group 381a via transfer gates 361a (thereby bypassing FIFO 362a). This is illustrated in Figure 3C by arrow 394a running from array 335 through wide mode data pad group 381a via transfer gates 361a. Also based on the read command, one or more of data TSV groups 371a-371dmay receive data read from the arrays of other memory devices in the memory device stack. Data received via the one or more of data TSV groups 371a-371d is routed and shifted to wide mode data pad groups 38 lb-381 d. This is illustrated in Figure 3C by arrow 394b running though wide mode data TSV group 371a and through wide mode data pad group 381b via transfer gates 361b, and arrow 394c running though wide mode data TSV group 371b and through wide mode data pad group 381c via transfer gates 361c.

[0049] In wide bottom die mode operation, commands and addresses (e.g., a read command and associated row and column addresses are receive at wide mode CA pads 383 in parallel and coupled to array control circuitry 331 via buffer 338, transfer gates 337, latch 336 (to synchronize CA signals to internal clock ICLK), and CA MUX 332. This is illustrated in Figure 3D by arrow 393d running from wide mode CA pads 383 to array 335 via buffer 338, transfer gates 337, latch 336, CA MUX 332, and array control circuitry 331. Array control circuitry 331 controls array 335 to access the addressed data in array 335. In wide bottom die mode operation, commands and addresses are also coupled to CA TSV group 373 after being buffered by buffer 338. This is illustrated in Figure 3D by arrow 393c breaking off from arrow 393d after buffer 338 and running through CA TSV group 373.

[0050] Based on a read command, for example, in wide bottom die mode, data accessed from array 335 is routed by read data DMUX 346 to transfer gates 361a and FIFO 362a. FIFO 362a is configured in wide bottom die mode to, in response to internal data strobe signal DS, store the data from array 335 in FIFO 362a. Transfer gates 361a-361d are configured to prevent data from directly reaching wide mode data pads 38 la-38 Id without first being buffered / synchronized by FIFOs 361a-362d. This is illustrated in Figure 3D by arrow 395a running from array 335 into FIFO 362a and arrows 395b-395d running through wide mode data TSV groups 371a-371c into 362b-362d. In wide bottom die mode and based on the external timing reference signal DOS, read data associated with one or more read commands is clocked out of FIFOs 362a-362d and output via wide mode data pad groups 381a-381d. This is illustrated in Figure 3D by arrows 396a-396d running from FIFOs 362a- 362d through wide mode data pads 38 la-38 Id respectively via transfer gates and buffers 361a-361d.

[0051] As discussed herein, in both wide and non-bottom die mode operation, and wide and bottom die mode operation, commands and addresses (e.g., a write command and associated row and column addresses are receive at wide mode CA pads 383 in parallel and coupled to array control circuitry 331 via buffer 338, transfer gates 337, latch 336 (to synchronize CA signals to internal clock ICLK), and CA MUX 332. This is illustrated inFigure 3E by arrow 393f running from wide mode CA pads 383 to array 335 via buffer 338, transfer gates 337, latch 336, CA MUX 332, and array control circuitry 331. Array control circuitry 331 controls array 335 to access the addressed data in array 335. In wide and nonbottom die mode operation, and wide and bottom die mode operation, commands and addresses are also coupled to CA TSV group 373 after being buffered by buffer 338. This is illustrated in Figure 3E by arrow 393e breaking off from arrow 393f after buffer 338 and running through CA TSV group 373.

[0052] Based on a write command, for example, in wide and non-bottom die mode operation, and wide and bottom die mode operation, data to be written to array 335 is routed from wide mode data pad group 381a by transfer gates 361a to latch 343 where it is synchronized by ICLK. This is illustrated in Figure 3E by arrow 397a running from wide mode data pad group 381a via transfer gates 361a to latch 343. After synchronization to ICLK, the write data for memory device 300 is selected by write data MUX 345 to be provided to array 335. Also based on the write command, one or more of wide mode data pad groups 38 lb-371 d receive write data (e.g., from a controller) to be written to the arrays of other memory devices in the memory device stack. Write data received via the one or more of wide mode data pad groups 38 lb-371 d is routed and shifted (by shift 350) to wide mode data TSV groups 371a-371d. This is illustrated in Figure 3E by arrow 397b running though wide mode data pad group 381b and through wide mode data TSV group 371a via transfer gates 361b, arrow 397c running though wide mode data pad group 381c and wide mode data TSV group 371b via transfer gates 361c, and arrows 396e-396d.

[0053] Figures 4A-4B are diagrams illustrating interconnections of an example memory device stack. In Figures 4A-4B, memory device stack 400 is illustrated comprising bottom memory device 410a, memory device 410b, and memory device 410c. It should be understood, however, that additional memory devices may be included in memory device stack 410. Memory device 410b is stacked on top of bottom memory device 410a. Memory device 410c is stacked on top of memory device 410b.

[0054] Bottom memory device 410a includes wide mode data pad groups 481aa-481ad, wide mode CA pads 483a, narrow mode CA pads 485a, narrow mode data pads 486a, memory array 435a, shift 450a, data TSV groups 471aa-471ad, and CA TSV group 473a. Memory device 410b includes wide mode data pad groups 481ba-481bd, wide mode CA pads 483b, narrow mode CA pads 485b, narrow mode data pads 486b, memory array 435b, shift 450b, data TSV groups 471ba-471bd, and CA TSV group 473b. Memory device 410c isillustrated including at least wide mode data pad groups 481ca-481cd, wide mode CA pads 483c, narrow mode CA pads 485c, and narrow mode data pads 486c.

[0055] Wide mode CA pads 483 a and wide mode data pad groups 481aa-481ad of bottom die 410a are (or are to) be operatively coupled with a buffer device (not shown in Figures 4A- 4B — e.g., one quadrant / channel of buffer device 140). CA TSV group 473a of bottom memory device 410a is operatively coupled (or connected) with wide mode CA pads 483b of memory device 410b. Data TSV groups 471aa-471ad of memory device 410a are respectively operatively coupled with wide mode data pad groups 481ba-481bd of memory device 410b. CA TSV group 473b of memory device 410b is operatively coupled (or connected) with wide mode CA pads 483b of memory device 410b. Data TSV groups 471ba- 471bd of memory device 410b are respectively operatively coupled with wide mode data pad groups 481ca-481cd of memory device 410c.

[0056] In each of memory devices 410a-410c, data communicated via respective wide mode data pad groups 481aa-481ca is communicated with the internal circuitry of that memory device 410a-410c and not “passed along” to the next device in the memory device stack 400. Also in each of memory devices 410a-410c, shift function 450a-450c respectively couples data to / from wide mode data pad groups 481ab-481bb to data TSV groups 471aa- 471bb. Thus, for example, data communicated with a buffer device (not shown in Figures 4A-4B) via wide mode data pad group 48 lab of memory device 410a is communicated with wide mode data pad group 481ba of memory device 410b, data communicated via wide mode data pad group 48 lac of memory device 410a is communicated with wide mode data pad group 481bb of memory device 410b and wide mode data pad group 48 lea of memory device 410c. In Figure 4B, arrows illustrate the “shifting” accomplished by the interconnection of memory devices 410a-410c in a stack and their respective internal shift function circuitry / wiring 450a-450c.

[0057] Figures 5A-5B are timing diagrams illustrating example read operations directed to multiple memory device stack subchannels. In Figures 5A-5B, example communication between a controller (e.g., controller 120), an assembly (e.g., assembly 110), and devices of the assembly (e.g., buffer device 140, memory device 130aa, memory device 130ab, etc.) is illustrated from the perspective of the unidirectional transmit and receive interfaces of the controller. In Figures 5A-5B, the controller transmits, in succession and on the controller transmit interface (CTR TX), a first read command directed / addressed to subchannel A (RDCA1), a second read command directed / addressed to subchannel B (RDCB1), and a third read command directed / addressed to subchannel A (RDCA2). In response, the assemblytransmits a first activate command (ACTA1) on subchannel A (CH-A) concurrently with a second activate command (ACTB1) on subchannel B (CH-B), followed by a third activate command (ACTA2) on subchannel A. The commands transmitted on CH-A and CH-B are timing referenced to a clock CLK that is cycling at a (minimum or selected) column-to- column delay interval for the memory devices on subchannel A and subchannel B. An arrow from the RDCA1 command on the controller transmit interface leading to the ACTA1 command on subchannel A is illustrated in Figure 5B by an arrow from the RDCA1 command on the controller transmit interface to the ACTA1 command on subchannel A.

[0058] The ACTA1 and ACTA2 command are propagated through and to the memory devices (e.g., memory devices 130aa-130ae) of the memory device stack (e.g., memory device stack 130a) that is coupled with subchannel A. As each command is received by a respective memory device, it is synchronized to an internal clock of the memory device. This is illustrated in Figure 5B by the arrow from the rising edge of ICLK-A DO (internal clock, subchannel A, die #0) to the start of the ACTA1 command on the internal command bus of die #0 (CMD-A DO), and the arrow from the rising edge of ICLK-A DI (internal clock, subchannel A, die #1) to the start of the ACTA1 command on the internal command bus of die #1 (CMD-A DI).

[0059] Further in response to the RDCA1, RDCB1, RDCA2 sequence transmitted by the controller, the assembly transmits a first read command (RDA1) on CH-A concurrently with a second read command (RDB1) on CH-B, followed by a third read command (RDA2) on CH-A. An arrow from the RDCA1 command on the controller transmit interface leading to the RDA1 command on subchannel A is illustrated in Figure 5B by an arrow from the RDCA1 command on the controller transmit interface to the RDA1 command on subchannel A.

[0060] The RDA1 and RDA2 command, along with column address information (CA- Al, CA-A2) on column address links (COL-A) and row address information (RA-A1, RA- A2) on row address links (ROW-A), are propagated through and to the memory devices (e.g., memory devices 130aa-130ae) of the memory device stack (e.g., memory device stack 130a) that is coupled with subchannel A. In response to the RDA1 and RDA2 commands (and associated row and column address information), the memory devices coupled with subchannel A output (in parallel - e.g., 64 bits) data read from their respective memory arrays (e.g., on wide data mode pad group 381a) and propagate their portion of the parallel read data down the memory device stack (e.g., shifting over one TSV / pad group each die). This is illustrated in Figures 5A-5B by the DQA1D0 (a.k.a., data associated with read Al from die#0) followed by DQA2D0 on the data (DQ) bus for the subchannel A die #0 (DQ-A DO), and the DQA1D1 (a.k.a., data associated with read Al from die #1) followed by DQA2D1 on the data (DQ) bus for the subchannel A die #1 (DQ-A DI). The propagated read data from the memory devices of the memory device stack is stored in a FIFO by the bottom die of the subchannel A memory device stack (not shown in Figure 5B).

[0061] Similarly, the RDB1 command, along with column address information on the column address links and row address information on row address links, is propagated through and to the memory devices (e.g., memory devices 130ba-130be) of the memory device stack (e.g., memory device stack 130b) that is coupled with subchannel B. In response to the RDB1 (and associated row and column address information), the memory devices coupled with subchannel B output data read from their respective memory arrays and propagate their portion of the parallel read data down the memory device stack (e.g., shifting over one TSV / pad group each die). This is illustrated in Figures 5A-5B by the DQB1D0 (a.k.a., data associated with read Bl from die #0) for the subchannel B die #0 (DQ-B DO), and the DQB1D1 (a.k.a., data associated with read Bl from die #1) on the data (DQ) bus for the subchannel B die #1 (DQ-B DI). The propagated read data from the memory devices of the memory device stack is stored in a FIFO by the bottom die of the subchannel B memory device stack (not shown in Figures 5A-5B).

[0062] The read data remains in the FIFOs of the bottom die of the memory device stacks until the buffer device clocks the read data out of the FIFOs using the DOS (Data Output Strobe) signal. This is illustrated in Figure 5B by the arrows running from the rising edge of the DOS signal to the start of the wide (e.g., 512 bit) output from the bottom die for RDA1 (A1DQ) and RDA2 (A2DQ) of the subchannel A memory device stack wide data bus (DATA-A). A similar response on subchannel B occurs and is illustrated in Figures 5A-5B by the output from the bottom die for RDB1 (B1DQ) appearing on the subchannel B memory device stack wide data bus (DATA-B).

[0063] The buffer device, as described herein, serializes the read data from RD Al, RDB1, RDA2 and transmits the corresponding read data to the controller in the order the read commands were received. This is illustrated in Figure 5B by the arrows respectively running from A1DQ and A2DQ on DATA-A to DQA1 and DQA2 at the controller receive interface (CTR RX).

[0064] Figure 6A-6B are timing diagrams illustrating example read and write operations directed to multiple memory device stack subchannels. In Figures 6A-6B, example communication between a controller (e.g., controller 120), an assembly (e.g., assembly 110),and devices of the assembly (e.g., buffer device 140, memory device 130aa, memory device 130ab, etc.) is illustrated from the perspective of the unidirectional transmit and receive interfaces of the controller. In Figures 6A-6B, the controller transmits, in succession and via the controller transmit interface (CTR TX), and in the following order: a read command directed / addressed to subchannel B (RDCB1), a write command directed / addressed to subchannel A (WRCA1), and a read command directed / addressed to subchannel C (RDCC1), a read command directed / addressed to subchannel B (RDCB2), and a read command directed / addressed to subchannel A (RDCA2). In response, the assembly concurrently transmits an activate command ACTA1 on subchannel A (CH-A), an activate command ACTB1 on subchannel B (CH-B), an activate command ACTC1 on subchannel C (CH-C), and an activate command ACTD1 on subchannel D (CH-D). This is representatively illustrated in Figure 6B by the arrow running from WRCA1 to ACTA1 on CH-A. After those concurrent transmissions, the assembly concurrently transmits an activate command ACTA2 on CH-A and an activate command ACTB1 on CH-B. The commands transmitted on CH-A, CH-B, CH-C, and CH-D are timing referenced to a clock CLK that is cycling at a (minimum or selected) column-to-column delay interval for the memory devices on subchannels A-D.

[0065] The ACTA1, ACTB1, ACTC1, ACTD1, ACTA2, and ACTB2 commands are propagated through the corresponding memory device stacks to the memory devices (e.g., memory devices 130aa-130ae) of the memory device stack (e.g., memory device stack 130a) that are coupled with the corresponding subchannel. As each command is received by a respective memory device, it is synchronized to a respective internal clock (notionally represented by the single ICLK in Figures 6A-6B) of the memory device.

[0066] Further in response to corresponding commands of the command sequence (RDCB1, WRCA1, RDCC1, RDB2, WRCD1, WRCA2) transmitted by the controller, the assembly concurrently transmits write command WRA1 followed by write command WRA2 on CH-A, read command RDB1 followed by read command RDB2 on CH-B, read command RDC1 on CH-C, and write command WRD1 on CH-D. This is representatively illustrated in Figure 6B by the arrows running from WRCA1 to WRA1 on CH-A.

[0067] The WRA1, RDB1, RDC1, WRD1, WRA2, and RDB2 commands, along with column address information and row address information, are propagated through and to the memory devices (e.g., memory devices 130aa-130ae) of the corresponding memory device stack. In addition, for the write commands WRA1, WRA2, and WRD1, parallel write data is propagated up through the corresponding memory device stack (e.g., shifting over one TSV / pad group each die) to the memory devices of the respective memory device stack. Thisis representatively illustrated in Figure 6B by the arrows running from WDA1, WDD1, and WDA2, respectively, to WDA1D0 (a.k.a., write data for write Al to die #0) on DQ-A for die #0, WDD1D0 on DQ-D for die #0, and WDA2D0 on DQ-A for die #0.

[0068] In response to the read commands RDB1, RDC1 and RDB2 commands (and associated row and column address information), the memory devices coupled with the corresponding subchannel output data read from their respective memory arrays and propagate their portion of the parallel read data down the memory device stack (e.g., shifting over one TSV / pad group each die). This is illustrated in Figure 6A-6B by the DQB1D0 (a.k.a., data associated with read Bl from die #0) followed by DQB2D0 on the data (DQ) bus for the subchannel B die #0 (DQ-B DO), and the DQC1D0 for the subchannel C die #0 (DQ- C DO). The propagated read data from the memory devices of the memory device stack is stored in a FIFO by the bottom die of the subchannel A memory device stack (not shown in Figures 6A-6B).

[0069] The read data remains in the FIFOs of the bottom die of the memory device stacks until the buffer device clocks the read data out of the FIFOs using the DOS (Data Output Strobe) signal. The buffer device, as described herein, serializes the read data from RDB1, RDB2, and RDC1 and transmits the corresponding read data to the controller in the order the read commands were received. This is illustrated in Figures 6A-6B by B1DQ and B2DQ of DATA-B, C1DQ on DATA-C, and the sequence DQB1, DQC1, and DQB2 at the controller receive interface (CTR RX).

[0070] Figure 7 is a diagram illustrating an example wide-narrow modal memory device floorplan. In Figure 7, memory device 700 comprises DQ TSVs 771, CA TSVs 773, and copper pillars 789. Connections are made between DQ TSVs 771 and copper pillars 789 by traces 788a on the top metal layer. Connections are made between CA TSVs 773 and copper pillars 789 by traces 788b on the top metal layer.

[0071] Figure 8 illustrates an example memory assembly with subchannel die stacks overlapping quadrants of a buffer device. In Figure 8, memory device stacks 830a-830d are illustrated only by their outlines (e.g., wireframe) to allow for visibility. In Figure 8, assembly 800 is illustrated with memory device stacks 830a-830c disposed partially on substrate 801 and partially on buffer device 840. In particular, each of memory device stacks 830a-830d is disposed on (over) different quadrants of buffer device 840. In this manner, buffer device 840 may be smaller (i.e., less area) than buffer device 840 and still make connections (e.g., through-silicon vias - TSVs) with the subchannels of memory device stacks 830a-830c (and the memory devices therein).

[0072] Figure 9 is a flowchart of a method of operating a memory assembly. One or more steps illustrated in Figure 9 may be performed by, for example, memory system 100, and / or its components. By an assembly comprising a buffer integrated circuit and a plurality of memory integrated circuit device stacks disposed at least partially on the buffer integrated circuit, a first command to be performed by a first stack of the plurality of memory integrated circuit device stack is received, where the plurality of memory integrated circuit device stacks are operating at a column-to-column access interval (902). For example, assembly 110 may receive, from controller 120, a command to be performed by memory device stack 130a where subchannel A 137a is being operated by buffer device 140 with a column-to-column access interval approximately equal to, or equal to, a specified tcco s (or more) associated with the memory devices 130aa-130ae of memory device stack 130a.

[0073] By the buffer integrated circuit and with the first stack, a first data block associated with the first command is communicated where the first data block is communicated using first parallel transfer units having a first number of bits using a first transfer interval and the first transfer interval is equal to or approximately equal to the column-to-column access interval tcco s divided by the access granularity multiplied by the number bits of data provided by each memory integrated circuit of the first device stack (904). For example, in response to a read command, memory device stack 130a may transmit, to buffer device 140, blocks of 512 data bits in parallel (e.g., 64 bits from each of 8 memory devices 130aa-130ae) where the cycle time for each 512 bit block is equal to tcco s. I.e., (tcco s / 64)x64= tcco s. By the buffer integrated circuit and with the controller, the first data block is communicated using second parallel transfer units having a second number of bits using a second transfer interval where the second transfer interval is less than the column-to-column access interval (906). For example, in response to the read command, buffer device 140 may transmit, to controller 120, the blocks of 512 data bits in 8-bit wide transfer units where the cycle time for each 8 bit transfer unit is equal to, or less than (tcco s / 512) x 8=tccD s / 64.

[0074] Figure 10 is a flowchart of a method of accessing multiple subchannel memory stacks of a memory assembly. One or more steps illustrated in Figure 10 may be performed by, for example, memory system 100, and / or its components. By an assembly comprising a buffer integrated circuit and a plurality of memory integrated circuit device stacks disposed at least partially on the buffer integrated circuit, a first command to be performed by a first stack of the plurality of memory integrated circuit device stack is received, where the plurality of memory integrated circuit device stacks are operating at a column-to-columnaccess interval (1002). For example, assembly 110 may receive, from controller 120, a first read command to be performed by memory device stack 130a where subchannel A 137a is being operated by buffer device 140 with a column-to-column access interval approximately equal to, or equal to, a specified tcco s (or more) associated with the memory devices 130aa- 130ae of memory device stack 130a.

[0075] By the buffer integrated circuit and with the first stack, a first data block associated with the first command is communicated where the first data block is communicated using first parallel transfer units having a first number of bits using a first transfer interval and the first transfer interval is equal to or approximately equal to the column-to-column access interval tcco s divided by the access granularity multiplied by the number bits of data provided by each memory integrated circuit of the first device stack (1004). For example, in response to a read command, memory device stack 130a may transmit, to buffer device 140, blocks of 512 data bits in parallel (e.g., 64 bits from each of 8 memory devices 130aa-130ae) where the cycle time for each 512 bit block is equal to tcco s. I.e., (tcco s / 64)x64= tcco s. By the buffer integrated circuit and with the controller, the first data block is communicated using second parallel transfer units having a second number of bits using a second transfer interval where the second transfer interval is less than the column-to-column access interval (1006). For example, in response to the first read command, buffer device 140 may transmit, to controller 120, the first block of 512 data bits in 8-bit wide transfer units where the cycle time for each 8 bit transfer unit is equal to, or less than, (tcco s / 512)x8= teen s / 64.

[0076] By the assembly, a second command to be performed by a second stack of the plurality of memory integrated circuit device stacks is received (1008). For example, assembly 110 may receive, from controller 120, a second read command to be performed by memory device stack 130b. By the buffer integrated circuit and with the second stack, a second data block associated with the second command is communicated where the second data block is communicated using the first parallel transfer units and the first transfer interval (1010). For example, in response to the second read command, memory device stack 130b may transmit, to buffer device 140, a second block of 512 data bits in parallel (e.g., 64 bits from each of 8 memory devices 130ba-130be) with a cycle time that is the same as the first block of 512 data bits.

[0077] By the buffer integrated circuit and with the controller, the second data block is communicated using the second parallel transfer units and the second transfer interval (1012). For example, in response to the second read command, buffer device 140 may transmit, tocontroller 120, the second block of 512 data bits in 8-bit wide transfer units where the cycle time for each 8-bit transfer unit is the same as the first block of 512 data bits.

[0078] Figure 11 is a flowchart of method of accessing data and error detection and correction information using multiple subchannel memory stacks of a memory assembly. One or more steps illustrated in Figure 11 may be performed by, for example, memory system 100, and / or its components. By an assembly comprising a buffer integrated circuit and a plurality of memory integrated circuit device stacks disposed at least partially on the buffer integrated circuit, a first command to be performed by a first stack of the plurality of memory integrated circuit device stack is received, where the plurality of memory integrated circuit device stacks are operating at a column-to-column access interval (1102). For example, assembly 110 may receive, from controller 120, a first read command to be performed by memory device stack 130a where subchannel A 137a is being operated by buffer device 140 with a column-to-column access interval approximately equal to, or equal to, a specified tccD s (or more) associated with the memory devices 130aa-130ae of memory device stack 130a.

[0079] By the buffer integrated circuit and with the first stack, a first data block associated with the first command is communicated where the first data block is communicated using first parallel transfer units having a first number of bits using a first transfer interval and the first transfer interval is equal to or approximately equal to the column-to-column access interval tccD s divided by the access granularity multiplied by the number of bits of data provided by each memory integrated circuit of the first stack (1104). For example, in response to the first read command, memory device stack 130a may transmit, to buffer device 140, a first block of 512 data bits in parallel (e.g., 64 bits from each of 8 memory devices 130aa-130ae) where the cycle time for each 512 bit block communicated is equal to tccD s. I.e., (tccD s / 64)*64=tccD s. By the buffer integrated circuit and with the controller, the first data block is communicated using second parallel transfer units having a second number of bits using a second transfer interval where the second transfer interval is less than the column-to-column access interval (1106). For example, in response to the first read command, buffer device 140 may transmit, to controller 120, the first block of 512 data bits in 8-bit wide transfer units where the cycle time for each 8-bit transfer unit is less than (tccD s / 512)*8= tccD s / 64.

[0080] By the buffer integrated circuit and with a second stack, first error detection and correction (EDC) information associated with the first command is communicated using third parallel transfer units having a third number of bits and the first transfer interval (1108). Forexample, in response to the first read command, memory device stack 130b may transmit, to buffer device 140, a block of 128 EDC information bits in parallel (e.g., 64 bits from each of two of memory devices 130aa-130ae) with a cycle time that is the same as the first block of 512 data bits. By the buffer integrated circuit and with the controller, the first EDC information is communicated using fourth parallel transfer units having a fourth number of bits and the second transfer interval (1110). For example, in response to the first read command, buffer device 140 may transmit, to controller 120, the block of 128 EDC information data bits in 2-bit wide transfer units where the cycle time for each 2-bit transfer unit is the same as the 8-bit transfers used with the first block of 512 data bits.

[0081] The methods, systems and devices described above may be implemented in computer systems, or stored by computer systems. The methods described above may also be stored on a non-transitory computer readable medium. Devices, circuits, and systems described herein may be implemented using computer-aided design tools available in the art, and embodied by computer-readable files containing software descriptions of such circuits. This includes, but is not limited to one or more elements of memory system 100, and its components. These software descriptions may be: behavioral, register transfer, logic component, transistor, and layout geometry-level descriptions. Moreover, the software descriptions may be stored on storage media or communicated by carrier waves.

[0082] Data formats in which such descriptions may be implemented include, but are not limited to: formats supporting behavioral languages like C, formats supporting register transfer level (RTL) languages like Verilog and VHDL, formats supporting geometry description languages (such as GDSII, GDSIII, GDSIV, CIF, and MEBES), and other suitable formats and languages. Moreover, data transfers of such files on machine-readable media may be done electronically over the diverse media on the Internet or, for example, via email. Note that physical files may be implemented on machine-readable media such as: 4 mm magnetic tape, 8 mm magnetic tape, 3-1 / 2 inch floppy media, CDs, DVDs, and so on.

[0083] Figure 12 is a block diagram illustrating one embodiment of a processing system 1200 for including, processing, or generating, a representation of a circuit component 1220. Processing system 1200 includes one or more processors 1202, a memory 1204, and one or more communications devices 1206. Processors 1202, memory 1204, and communications devices 1206 communicate using any suitable type, number, and / or configuration of wired and / or wireless connections 1208.

[0084] Processors 1202 execute instructions of one or more processes 1212 stored in a memory 1204 to process and / or generate circuit component 1220 responsive to user inputs1214 and parameters 1216. Processes 1212 may be any suitable electronic design automation (EDA) tool or portion thereof used to design, simulate, analyze, and / or verify electronic circuitry and / or generate photomasks for electronic circuitry. Representation 1220 includes data that describes all or portions of memory system 100, and its components, as shown in the Figures.

[0085] Representation 1220 may include one or more of behavioral, register transfer, logic component, transistor, and layout geometry -level descriptions. Moreover, representation 1220 may be stored on storage media or communicated by carrier waves.

[0086] Data formats in which representation 1220 may be implemented include, but are not limited to: formats supporting behavioral languages like C, formats supporting register transfer level (RTL) languages like Verilog and VHDL, formats supporting geometry description languages (such as GDSII, GDSIII, GDSIV, CIF, and MEBES), and other suitable formats and languages. Moreover, data transfers of such files on machine-readable media may be done electronically over the diverse media on the Internet or, for example, via email.

[0087] User inputs 1214 may comprise input parameters from a keyboard, mouse, voice recognition interface, microphone and speakers, graphical display, touch screen, or other type of user interface device. This user interface may be distributed among multiple interface devices. Parameters 1216 may include specifications and / or characteristics that are input to help define representation 1220. For example, parameters 1216 may include information that defines device types (e.g., NFET, PFET, etc.), topology (e.g., block diagrams, circuit descriptions, schematics, etc.), and / or device descriptions (e.g., device properties, device dimensions, power supply voltages, simulation temperatures, simulation models, etc.).

[0088] Memory 1204 includes any suitable type, number, and / or configuration of non- transitory computer-readable storage media that stores processes 1212, user inputs 1214, parameters 1216, and circuit component 1220.

[0089] Communications devices 1206 include any suitable type, number, and / or configuration of wired and / or wireless devices that transmit information from processing system 1200 to another processing or storage system (not shown) and / or receive information from another processing or storage system (not shown). For example, communications devices 1206 may transmit circuit component 1220 to another system. Communications devices 1206 may receive processes 1212, user inputs 1214, parameters 1216, and / or circuit component 1220 and cause processes 1212, user inputs 1214, parameters 1216, and / or circuit component 1220 to be stored in memory 1204.

[0090] Implementations discussed herein include, but are not limited to, the following examples:

[0091] Example 1 : A memory integrated circuit, comprising: a first data interface configured to, in a first mode of the memory integrated circuit, operate using first parallel transfer units having a first number of bits, where the first parallel transfer units are to be communicated externally to the memory integrated circuit; a second data interface configured to, in a second mode of the memory integrated circuit, operate using second parallel transfer units having a second number of bits, where the second parallel transfer units are to be communicated externally to the memory integrated circuit; and a third data interface configured to, in the second mode of the memory integrated circuit, operate using the second parallel transfer units and is to communicate the second parallel transfer units using the second transfer interval, where the third data interface is configured to communicate with another memory integrated circuit that is stacked with the memory integrated circuit.

[0092] Example 2: The memory integrated circuit of example 1, wherein, in a third mode of the memory integrated circuit, the second data interface is configured to communicate with a buffer device using the second parallel transfer units and the second transfer interval.

[0093] Example 3. The memory integrated circuit of example 2, further comprising: memory array circuitry to be operated with a minimum column-to-column access interval, where the first parallel transfer units are to be communicated externally to the memory integrated circuit using a first transfer interval, the first transfer interval to be substantially smaller than the minimum column-to-column access interval, and where the second parallel transfer units are to be communicated externally to the memory integrated circuit using a second transfer interval, the second transfer interval to be substantially equal, or exceed the minimum column-to-column access interval, wherein a timing of the second transfer interval is determined by a timing reference signal received via the buffer device.

[0094] Example 4: The memory integrated circuit of example 2, wherein a data type signal received via the buffer device determines, in the second mode, whether the memory integrated circuit functions as one of a data storage memory device of a memory device stack and an error detection and correction (EDC) information storage memory device of the memory device stack.

[0095] Example 5: The memory integrated circuit of example 1, wherein the first mode and the second mode are determined during a packaging process for the memory integrated circuit.

[0096] Example 6: The memory integrated circuit of example 1, wherein, in the first mode, data blocks accessed in response to single commands are communicated in data bursts of the first parallel transfer units.

[0097] Example 7: The memory integrated circuit of example 6, wherein, in the second mode, the second number of bits equals a size of the data blocks.

[0098] Example 8: A memory device, comprising: a first memory device stack disposed at least partially on a buffer device, the first memory device stack having a bottom memory device die coupled with a buffer device; and the buffer device having a first data interface and a second data interface, the first data interface configured to communicate data with a controller, the second data interface configured to communicate data with the first memory device stack via the bottom memory device, the first data interface to be operated using first parallel transfer units having a first number of bits, the second data interface to be operated using second parallel transfer units having a second number of bits.

[0099] Example 9: The memory device of example 8, wherein the first memory device stack is to be operated according to a minimum column-to-column access interval, and where the first parallel transfer units are to be communicated with the controller by the buffer device using a first transfer interval, the first transfer interval to be substantially smaller than the minimum column-to-column access interval, and where the second parallel transfer units are to be communicated by the buffer device with the first memory device stack using a second transfer interval, the second transfer interval to be substantially equal to, or greater than, the minimum column-to-column access interval.

[0100] Example 10: The memory device of example 8, wherein the bottom memory device die comprises: first-in first-out (FIFO) circuitry to buffer data accessed from the first memory device stack and communicate the buffered data with the buffer device using the second parallel transfer units and the second transfer interval.

[0101] Example 11 : The memory device of example 8, wherein a timing of the second transfer interval is determined by a timing reference signal received via the buffer device.

[0102] Example 12: The memory device of example 8, further comprising: a second memory device stack disposed at least partially on the buffer device.

[0103] Example 13: The memory device of example 8, wherein the buffer device further comprises: sequencer circuitry to receive commands transmitted by the controller in a first order and to transmit commands to the first memory device stack and a second memory device stack in a second order that maintains communication of data with the bottom memory device die in the first order.

[0104] Example 14: The memory device of example 12, further comprising: a third memory device stack and a fourth memory device stack each disposed at least partially on the buffer device.

[0105] Example 15: A method, comprising: receiving, by an assembly comprising a buffer integrated circuit and a plurality of memory integrated circuit device stacks disposed at least partially on the buffer integrated circuit, a first command to be performed by a first stack of the plurality of memory integrated circuit device stacks; communicating, by the buffer integrated circuit and with the first stack, a first data block associated with the first command, the first data block to be communicated using first parallel transfer units having a first number of bits; and communicating, by the buffer integrated circuit and with a controller, the first data block using second parallel transfer units having a second number of bits.

[0106] Examplel6: The method of example 15, wherein the plurality of memory integrated circuit device stacks are to be operated according to a minimum column-to-column access interval, and wherein the first parallel transfer units are communicated with the first stack using a first transfer interval, the first transfer interval to be substantially equal, or exceed, the minimum column-to-column access interval, and wherein the second parallel transfer units are communicated with the controller using a second transfer interval, the second transfer interval to be substantially smaller than the minimum column-to-column access interval, and the method further comprises: receiving, by the assembly and from the controller, a second command to be performed by a second stack of the plurality of memory integrated circuit device stacks; communicating, by the buffer integrated circuit and with the second stack, a second data block associated with the second command, the second data block to be communicated using the first parallel transfer units and the first transfer interval; and communicating, by the buffer integrated circuit and with the controller, the second data block using the second parallel transfer units and the second transfer interval.

[0107] Example 17: The method of example 16, wherein the first command and the second command are respectively transmitted to the first stack and the second stack in a same order as the first command and the second command are received by the assembly.

[0108] Example 18: The method of example 16, further comprising: communicating, by a second stack and based on the first command, first error detection and correction (EDC) information using third parallel transfer units having a third number of bits using the first transfer interval; and communicating, by the buffer integrated circuit and based on the first command, the first EDC information with the controller.

[0109] Example 19: The method of example 18, wherein the first command includes first row address information and first column address information, and the second command includes second row address information and second column address information.

[0110] Example 20: The method of example 15, wherein the first data block is N number of bits in size, the first parallel transfer units are N number of bits in size, and the first transfer interval is the column-to-column access interval.[OHl] The foregoing description of the invention has been presented for purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise form disclosed, and other modifications and variations may be possible in light of the above teachings. The embodiment was chosen and described in order to best explain the principles of the invention and its practical application to thereby enable others skilled in the art to best utilize the invention in various embodiments and various modifications as are suited to the particular use contemplated. It is intended that the appended claims be construed to include other alternative embodiments of the invention except insofar as limited by the prior art.

Claims

CLAIMSWhat is claimed is:

1. A memory integrated circuit, comprising: a first data interface configured to, in a first mode of the memory integrated circuit, operate using first parallel transfer units having a first number of bits, where the first parallel transfer units are to be communicated externally to the memory integrated circuit; a second data interface configured to, in a second mode of the memory integrated circuit, operate using second parallel transfer units having a second number of bits, where the second parallel transfer units are to be communicated externally to the memory integrated circuit; and a third data interface configured to, in the second mode of the memory integrated circuit, operate using the second parallel transfer units and is to communicate the second parallel transfer units using the second transfer interval, where the third data interface is configured to communicate with another memory integrated circuit that is stacked with the memory integrated circuit.

2. The memory integrated circuit of claim 1, wherein, in a third mode of the memory integrated circuit, the second data interface is configured to communicate with a buffer device using the second parallel transfer units and the second transfer interval.

3. The memory integrated circuit of claim 2, further comprising: memory array circuitry to be operated with a minimum column-to-column access interval, where the first parallel transfer units are to be communicated externally to the memory integrated circuit using a first transfer interval, the first transfer interval to be substantially smaller than the minimum column-to- column access interval, and where the second parallel transfer units are to be communicated externally to the memory integrated circuit using a second transfer interval, the second transfer interval to be substantially equal, or exceed the minimum column-to-column access interval, wherein a timing of the second transfer interval is determined by a timing reference signal received via the buffer device.

4. The memory integrated circuit of claim 2, wherein a data type signal received via the buffer device determines, in the second mode, whether the memory integrated circuit functions as one of a data storage memory device of a memory device stack and an error detection and correction (EDC) information storage memory device of the memory device stack.

5. The memory integrated circuit of claim 1, wherein the first mode and the second mode are determined during a packaging process for the memory integrated circuit.

6. The memory integrated circuit of claim 1, wherein, in the first mode, data blocks accessed in response to single commands are communicated in data bursts of the first parallel transfer units.

7. The memory integrated circuit of claim 6, wherein, in the second mode, the second number of bits equals a size of the data blocks.

8. A memory device, comprising: a first memory device stack disposed at least partially on a buffer device, the first memory device stack having a bottom memory device die coupled with a buffer device; and the buffer device having a first data interface and a second data interface, the first data interface configured to communicate data with a controller, the second data interface configured to communicate data with the first memory device stack via the bottom memory device, the first data interface to be operated using first parallel transfer units having a first number of bits, the second data interface to be operated using second parallel transfer units having a second number of bits.

9. The memory device of claim 8, wherein the first memory device stack is to be operated according to a minimum column-to-column access interval, and where the first parallel transfer units are to be communicated with the controller by the buffer device using a first transfer interval, the first transfer interval to be substantially smaller than the minimum column-to-column access interval, and where the second parallel transfer units are to becommunicated by the buffer device with the first memory device stack using a second transfer interval, the second transfer interval to be substantially equal to, or greater than, the minimum column-to-column access interval.

10. The memory device of claim 9, wherein the bottom memory device die comprises: first-in first-out (FIFO) circuitry to buffer data accessed from the first memory device stack and communicate the buffered data with the buffer device using the second parallel transfer units and the second transfer interval.

11. The memory device of claim 9, wherein a timing of the second transfer interval is determined by a timing reference signal received via the buffer device.

12. The memory device of claim 8, further comprising: a second memory device stack disposed at least partially on the buffer device.

13. The memory device of claim 8, wherein the buffer device further comprises: sequencer circuitry to receive commands transmitted by the controller in a first order and to transmit commands to the first memory device stack and a second memory device stack in a second order that maintains communication of data with the bottom memory device die in the first order.

14. The memory device of claim 12, further comprising: a third memory device stack and a fourth memory device stack each disposed at least partially on the buffer device.

15. A method, comprising: receiving, by an assembly comprising a buffer integrated circuit and a plurality of memory integrated circuit device stacks disposed at least partially on the buffer integrated circuit, a first command to be performed by a first stack of the plurality of memory integrated circuit device stacks; communicating, by the buffer integrated circuit and with the first stack, a first data block associated with the first command, the first data block to becommunicated using first parallel transfer units having a first number of bits; and communicating, by the buffer integrated circuit and with a controller, the first data block using second parallel transfer units having a second number of bits.

16. The method of claim 15, wherein the plurality of memory integrated circuit device stacks are to be operated according to a minimum column-to-column access interval, and wherein the first parallel transfer units are communicated with the first stack using a first transfer interval, the first transfer interval to be substantially equal, or exceed, the minimum column- to-column access interval, and wherein the second parallel transfer units are communicated with the controller using a second transfer interval, the second transfer interval to be substantially smaller than the minimum column-to-column access interval, and the method further comprises: receiving, by the assembly and from the controller, a second command to be performed by a second stack of the plurality of memory integrated circuit device stacks; communicating, by the buffer integrated circuit and with the second stack, a second data block associated with the second command, the second data block to be communicated using the first parallel transfer units and the first transfer interval; and communicating, by the buffer integrated circuit and with the controller, the second data block using the second parallel transfer units and the second transfer interval.

17. The method of claim 16, wherein the first command and the second command are respectively transmitted to the first stack and the second stack in a same order as the first command and the second command are received by the assembly.

18. The method of claim 16, further comprising: communicating, by a second stack and based on the first command, first error detection and correction (EDC) information using third parallel transfer units having a third number of bits using the first transfer interval; and communicating, by the buffer integrated circuit and based on the first command, the first EDC information with the controller.

19. The method of claim 18, wherein the first command includes first row address information and first column address information, and the second command includes second row address information and second column address information.

20. The method of claim 15, wherein the first data block is N number of bits in size and the first parallel transfer units are N number of bits in size.

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