Device manufacturing method, memory device, and semiconductor apparatus

Abstract

The present disclosure relates to a device manufacturing method, a memory device, and a semiconductor apparatus. The device manufacturing method comprises: providing a substrate; and sequentially forming on the substrate, from bottom to top, a lower electrode material layer, a storage material layer, an upper electrode material layer and an isolation material portion, so as to produce a first trench assembly and a second trench assembly, wherein the first trench assembly is configured to be used for forming a memory device, the second trench assembly is configured to be used for forming an isolation component, and the first trench assembly and the second trench assembly are electrically isolated from each other.

Description

Device manufacturing method, memory device, and semiconductor device

[0001] Cross Reference to Related Applications

[0002] This application is based on and claims priority to Chinese Patent Application No. 202410733571.X, filed on June 6, 2024, the disclosure of which is incorporated herein in its entirety. TECHNICAL FIELD

[0003] The present disclosure relates to the technical field of storage, and more particularly, to a device manufacturing method, a memory device, and a semiconductor device. BACKGROUND

[0004] A memory device is a device with a memory function, whose electrical state can be controlled to record corresponding data. With the rapid development of information technology, the application of memory devices is becoming more and more widespread, and the performance requirements for memory devices themselves and other electronic devices that may exist and be related to memory devices are also becoming higher and higher. Therefore, there is a need to improve the existing device manufacturing technology.

[0005] SUMMARY

[0006] It is one of the objectives of the present disclosure to provide a device manufacturing method, a memory device, and a semiconductor device.

[0007] According to a first aspect of the present disclosure, a device manufacturing method is provided, comprising:

[0008] providing a substrate, wherein the substrate comprises an active region in which a first trench and a second trench are formed; and

[0009] forming, on the substrate, a lower electrode material layer, a storage material layer, an upper electrode material layer, and an isolation material portion in sequence from bottom to top to generate a first trench assembly and a second trench assembly;

[0010] wherein the first trench assembly is formed by the lower electrode material layer, the storage material layer, the upper electrode material layer, and the portion of the isolation material portion located in the first trench, and the first trench assembly is configured to form a memory device,

[0011] the second trench assembly is formed by the lower electrode material layer, the storage material layer, the upper electrode material layer, and the portion of the isolation material portion located in the second trench, and the second trench assembly is configured to form an isolation component,

[0012] the first trench assembly and the second trench assembly are electrically isolated from each other.

[0013] In some embodiments, sequentially forming, on the substrate, a lower electrode material layer, a memory material layer, an upper electrode material layer, and an isolation material portion from bottom to top to produce the first trench assembly and the second trench assembly comprises:

[0014] forming a patterned lower electrode material layer on the substrate, wherein the lower electrode material layer includes a first lower electrode material portion covering inner walls of the first trench and a second lower electrode material portion covering inner walls of the second trench, and the first lower electrode material portion and the second lower electrode material portion are disconnected from each other;

[0015] sequentially depositing a continuous thin film of the memory material, a continuous thin film of the upper electrode material, and the isolation material;

[0016] performing etching to remove at least a portion of the isolation material, at least a portion of the upper electrode material, and at least a portion of the memory material outside of the first trench and the second trench to form a patterned memory material layer, an upper electrode material layer, and an isolation material portion, wherein the memory material layer includes a first memory material portion in the first trench and a second memory material portion in the second trench, the upper electrode material layer includes a first upper electrode material portion in the first trench and a second upper electrode material portion in the second trench, and the isolation material portion includes a first isolation material portion filling in the first trench and a second isolation material portion filling in the second trench.

[0017] In some embodiments, forming a patterned lower electrode material layer on the substrate comprises:

[0018] depositing a continuous thin film of the lower electrode material on the substrate;

[0019] depositing an etch resist layer, wherein at least a portion of the etch resist layer fills in the first trench and the second trench;

[0020] performing etching to remove at least a portion of the lower electrode material outside of the first trench and the second trench to form a patterned lower electrode material layer; and

[0021] removing the remaining etch resist layer.

[0022] In some embodiments, the etch resist layer includes a bottom anti-reflective layer.

[0023] In some embodiments, at least one of the lower electrode material, the memory material, and the upper electrode material is deposited by atomic layer deposition.

[0024] In some embodiments, depositing the isolation material comprises:

[0025] depositing an isolation material by high-density plasma chemical vapor deposition, wherein the isolation material covers the entire upper surface of the upper electrode material; and

[0026] chemically mechanically polishing an upper surface of the deposited isolation material.

[0027] In some embodiments, twice the total thickness of the lower electrode material layer, the storage material layer, and the upper electrode material layer is less than the minimum width of the first trench, and twice the total thickness of the lower electrode material layer, the storage material layer, and the upper electrode material layer is less than the minimum width of the second trench; and / or

[0028] An angle between at least one side surface of the first trench and a bottom surface thereof is greater than or equal to 90°, and an angle between at least one side surface of the second trench and a bottom surface thereof is greater than or equal to 90°.

[0029] In some embodiments, a depth of at least one of the first trench and the second trench is 300-400 nm or 400-500 nm; and / or

[0030] A width of at least one of the first trench and the second trench is 130-190 nm or 190-250 nm.

[0031] In some embodiments, at least one of the lower electrode material layer and the upper electrode material layer is formed of at least one of titanium, titanium nitride, titanium silicon nitride, titanium aluminum nitride, titanium carbonitride, tantalum nitride, tantalum silicon nitride, tantalum aluminum nitride, tungsten nitride, tungsten silicide, doped polysilicon, and transparent conductive oxide; and / or

[0032] The storage material layer is formed of at least one of phase change storage material, ferroelectric material, zirconium oxide, hafnium oxide, titanium oxide, aluminum oxide, nickel oxide, and iron oxide.

[0033] In some embodiments, after the first trench assembly and the second trench assembly are generated, the device preparation method further comprises:

[0034] forming other electronic devices different from the memory devices on the substrate, wherein at least two adjacent devices are respectively arranged on both sides of the second trench assembly as the isolation component.

[0035] In some embodiments, after the first trench assembly and the second trench assembly are generated, the device preparation method further comprises:

[0036] forming a dielectric protection layer over the device, a conductive connection within the dielectric protection layer, and a wiring layer over the dielectric protection layer, wherein the conductive connection includes a first conductive connection and a second conductive connection that are electrically connected to portions of the lower electrode material layer and the upper electrode material layer within the first trench, respectively, and the wiring layer includes a first wiring layer and a second wiring layer that are electrically connected to the first conductive connection and the second conductive connection, respectively.

[0037] In some embodiments, forming the first conductive connection that is electrically connected to the portion of the lower electrode material layer within the first trench includes:

[0038] forming a contact in a portion of the substrate adjacent to the first trench assembly, wherein the contact is electrically connected to the first lower electrode material portion of the lower electrode material layer within the first trench, and the contact is formed of a metal silicide; and

[0039] forming the first conductive connection over the contact, wherein the first conductive connection is configured to electrically connect the contact to the first wiring layer.

[0040] In some embodiments, forming the second conductive connection that is electrically connected to the portion of the upper electrode material layer within the first trench includes:

[0041] etching at least a portion of a first isolation material portion of the fill of the isolation material in the first trench until a portion of the upper electrode material layer is exposed; and

[0042] forming the second conductive connection over the exposed portion of the upper electrode material layer, wherein the second conductive connection is configured to electrically connect the upper electrode material layer to the second wiring layer.

[0043] In some embodiments, where the upper electrode material layer includes an upper electrode lead portion that is outside of the first trench and electrically connected to the portion of the upper electrode material layer within the first trench, forming the second conductive connection that is electrically connected to the portion of the upper electrode material layer within the first trench includes:

[0044] forming the second conductive connection over the upper electrode lead portion, wherein the second conductive connection is configured to electrically connect the upper electrode material layer to the second wiring layer.

[0045] According to a second aspect of the present disclosure, there is provided a memory device including, in order from bottom to top along an inner wall of a first trench in a substrate, a first lower electrode material portion, a first storage material portion, and a first upper electrode material portion.

[0046] In some embodiments, the memory device is prepared according to the device preparation method as described above.

[0047] According to a third aspect of the present disclosure, there is provided a semiconductor device including one or more memory devices as described above.

[0048] In some embodiments, the semiconductor device further includes another electronic device different from the memory device.

[0049] Other features of the present disclosure, and its advantages, will become apparent in the following detailed description of exemplary embodiments of the present disclosure, taken in conjunction with the accompanying drawings. BRIEF DESCRIPTION OF DRAWINGS

[0050] The accompanying drawings, which are incorporated in and constitute a part of the specification, illustrate embodiments of the present disclosure and, together with the description, serve to explain the principles of the present disclosure.

[0051] The present disclosure can be understood more readily by reference to the following detailed description of exemplary embodiments of the present disclosure and the attached drawings, which form a part of this disclosure. It is to be understood that the terminology used in the description herein is for the purpose of describing the particular embodiments only and is not intended to be limiting.

[0052] FIG. 1 shows a schematic cross-sectional structure of a memory device;

[0053] FIG. 2 shows a photograph of a cross-sectional structure of a memory device;

[0054] FIG. 3 shows a flowchart of a device preparation method according to an exemplary embodiment of the present disclosure;

[0055] FIGS. 4(a) to 4(j) show schematic views of a device preparation process according to a specific embodiment of the present disclosure.

[0056] Note that, in the following embodiments, the same reference numerals are sometimes used across different drawings to indicate the same or similar parts or parts having the same function, and repeated description thereof is omitted. In this specification, like numbers and letters designate like items throughout the specification, and like elements are not described repeatedly.

[0057] For ease of understanding, the position, size, range, and the like of each structure shown in the drawings and the like are sometimes not actual ones. Therefore, the disclosed invention is not limited to the position, size, range, and the like disclosed in the drawings and the like. In addition, the drawings are not necessarily drawn to scale, and some features can be exaggerated to show specific components in detail. DETAILED DESCRIPTION

[0058] Various exemplary embodiments of the present disclosure will now be described in detail below with reference to the accompanying drawings. Note that the relative arrangement of components and steps, numerical expressions, and numerical values set forth in these embodiments are not limiting to the scope of the present disclosure unless otherwise specifically stated. In some embodiments, the memory device is prepared according to the device preparation method as described above.

[0047] According to a third aspect of the present disclosure, there is provided a semiconductor device including one or more memory devices as described above.

[0048] In some embodiments, the semiconductor device further includes another electronic device different from the memory device.

[0049] Other features of the present disclosure, and its advantages, will become apparent in the following detailed description of exemplary embodiments of the present disclosure, taken in conjunction with the accompanying drawings. BRIEF DESCRIPTION OF DRAWINGS

[0050] The accompanying drawings, which are incorporated in and constitute a part of the specification, illustrate embodiments of the present disclosure and, together with the description, serve to explain the principles of the present disclosure.

[0051] The present disclosure can be understood more readily by reference to the following detailed description of exemplary embodiments of the present disclosure and the attached drawings, which form a part of this disclosure. It is to be understood that the terminology used in the description herein is for the purpose of describing the particular embodiments only and is not intended to be limiting.

[0052] FIG. 1 shows a schematic cross-sectional structure of a memory device;

[0053] FIG. 2 shows a photograph of a cross-sectional structure of a memory device;

[0054] FIG. 3 shows a flowchart of a device preparation method according to an exemplary embodiment of the present disclosure;

[0055] FIGS. 4(a) to 4(j) show schematic views of a device preparation process according to a specific embodiment of the present disclosure.

[0056] Note that, in the following embodiments, the same reference numerals are sometimes used across different drawings to indicate the same or similar parts or parts having the same function, and repeated description thereof is omitted. In this specification, like numbers and letters designate like items throughout the specification, and like elements are not described repeatedly.

[0057] For ease of understanding, the position, size, range, and the like of each structure shown in the drawings and the like are sometimes not actual ones. Therefore, the disclosed invention is not limited to the position, size, range, and the like disclosed in the drawings and the like. In addition, the drawings are not necessarily drawn to scale, and some features can be exaggerated to show specific components in detail. DETAILED DESCRIPTION

[0058] Various exemplary embodiments of the present disclosure will now be described in detail below with reference to the accompanying drawings. Note that the relative arrangement of components and steps, numerical expressions, and numerical values set forth in these embodiments are not limiting to the scope of the present disclosure unless otherwise specifically stated.

[0059] The following description of at least one exemplary embodiment is merely illustrative in nature and is in no way intended to limit the disclosure, its application or uses.

[0060] Techniques, methods, and devices known to those of ordinary skill in the relevant art can not be discussed in detail herein. However, where appropriate, such techniques, methods, and devices can be viewed as part of the specification.

[0061] Generally, the device performance of a memory device is positively related or proportional to the effective area of its two electrodes and the storage material therebetween. In other words, the device performance of a memory device is related to the area of the overlapping region of the two electrodes and the storage material therebetween, the larger the area of the overlapping region, i.e. the larger the effective area of the memory device, the larger the polarization area, and thus the more polarization charges can be stored at the same voltage, resulting in better sensitivity, stability, and reliability of the memory device, and helping to prolong the life of the device. In order to increase the effective area of the memory device, as shown in FIGS. 1 and 2, the memory device 100' can be provided with a three-dimensional (3D) structure, which can include a lower electrode material layer 120', a storage material layer 130', and an upper electrode material layer 140' stacked in sequence along the wall of the trench, thereby improving the storage density and achieving better cell performance and reliability under the same cell area.

[0062] However, such a process for forming 3D structures is generally performed after the processes for forming front-stage devices 200' (other electronic devices different from memory devices, such as logic devices, etc.) and conductive connectors 410', etc. are completed, thus possibly causing some problems. For example, in the process of forming memory devices 100', it can be necessary to heat them to activate the devices, and the heat budget associated with this can adversely affect the front-stage devices 200' that have already been formed. In addition, as shown in FIGS. 1 and 2, in order to lead out the lower electrode material layer 120' of the memory devices 100' to be electrically connected to other electronic devices or external circuits, etc., the memory devices 100' are generally disposed above the conductive connectors 410'. However, due to the difference in hardness between the conductive connectors 410' and the dielectric material 300' adjacent thereto, over-polishing of the dielectric material 300' can occur during chemical mechanical polishing (CMP), causing the conductive connectors 410' to protrude to some extent relative to the dielectric material 300' adjacent thereto (as clearly shown in the A area of the photograph in FIG. 2), i.e., the substrate for forming the memory devices 100' can be uneven, thus causing steps, even discontinuities or breaks, to be introduced into the corresponding film layers in the process of forming the memory devices 100', resulting in a decrease in the performance of the memory devices 100' or even failure of the memory devices 100'.

[0063] To solve the above problems, the present disclosure proposes a device preparation method. In an exemplary embodiment of the present disclosure, as shown in FIGS. 3 and 4(a), the device preparation method can include:

[0064] In step S910, a substrate 110 is provided.

[0065] The substrate 110 includes an active region 113. In a specific example, the substrate 110 can be based on silicon material, and the active region 113 can be formed by doping silicon. However, it can be understood that other materials of the substrate 110 can also be used, and the active region 113 is formed accordingly, which is not limited here. The first trench 111 and the second trench 112 can be formed in the active region 113. It can be understood that more trenches can also be formed in the active region 113 according to needs, which is not limited here, and only the first trench 111 and the second trench 112 are taken as examples for illustration here.

[0066] In some embodiments, the trenches in the active region can be formed based on photolithography and etching processes. Specifically, a patterned etch-resist layer (photoresist layer) can be formed on the substrate or the active region, and then a layer of etch-resist material (e.g., silicon nitride, etc.) can be formed on the substrate or the active region by a deposition and lift-off process on the regions outside the trenches, and then the exposed portions of the substrate or the active region not covered by the layer of etch-resist material can be etched by dry etching or wet etching to remove the substrate or the active region material in the corresponding regions, thereby forming the trenches, and finally the layer of etch-resist material can be selectively removed or retained (in the case of retaining the layer of etch-resist material, it can exist as a part of the substrate) as needed to form the structure as shown in FIG. 4(a).

[0067] Further, as shown in FIGS. 3 and 4(b) to 4(g), the device preparation method can further include:

[0068] At step S920, a lower electrode material layer 120, a storage material layer 130, an upper electrode material layer 140, and an isolation material portion 150 are sequentially formed on the substrate 110 from bottom to top to produce a first trench assembly 101 and a second trench assembly 102.

[0069] The first trench assembly 101 can be formed by the portions of the lower electrode material layer 120, the storage material layer 130, the upper electrode material layer 140, and the isolation material portion 150 located in the first trench 111, and the first trench assembly 101 can be configured to form a memory device. Specifically, the portions of the lower electrode material layer 120, the storage material layer 130, and the upper electrode material layer 140 in the first trench assembly 101 can form a memory device, and can be electrically connected to other electronic devices or external circuits via conductive connectors, etc. as described later, thereby achieving the desired storage function.

[0070] In addition, the second trench assembly 102 can be formed by the portions of the lower electrode material layer 120, the storage material layer 130, the upper electrode material layer 140, and the isolation material portion 150 located in the second trench 112, and the second trench assembly 102 can be configured to form an isolation component. Specifically, at least the portion of the isolation material portion 150 in the second trench assembly 102 can be used to achieve electrical isolation between devices. In addition, in some embodiments, the portion of the storage material layer 130 in the second trench assembly 102 is also formed of an electrically insulating material, and thus can also help achieve electrical isolation between devices.

[0071] Here, to avoid the mutual influence between the memory device and the isolation component, the first trench assembly 101 and the second trench assembly 102 can be electrically isolated from each other. For example, the electrical isolation between the first trench assembly 101 and the second trench assembly 102 can be achieved by breaking the portion of the lower electrode material between the first trench assembly 101 and the second trench assembly 102, or by breaking the portion of the upper electrode material between the first trench assembly 101 and the second trench assembly 102, or by breaking the portion of both the lower electrode material and the upper electrode material between the first trench assembly 101 and the second trench assembly 102, as will be described in detail later.

[0072] In a specific embodiment, as shown in FIGS. 4(b) to 4(d), sequentially forming the lower electrode material layer 120, the memory material layer 130, the upper electrode material layer 140 and the isolation material portion 150 on the substrate 110 from bottom to top to generate the first trench assembly 101 and the second trench assembly 102 can include: forming a patterned lower electrode material layer 120 on the substrate 110. The lower electrode material layer 120 can include a first lower electrode material portion 121 covering the inner walls (including the bottom wall and the side wall) of the first trench 111 and a second lower electrode material portion 122 covering the inner walls (including the bottom wall and the side wall) of the second trench 112, and the first lower electrode material portion 121 and the second lower electrode material portion 122 are disconnected from each other. In some embodiments, the patterned lower electrode material layer 120 can only exist on the inner walls of the trenches. Alternatively, in other embodiments, the patterned lower electrode material layer 120 can not only cover the inner walls of the trenches, but also extend onto the upper surface of the region of the active area 113 adjacent to the trenches for subsequent electrical connection, etc.

[0073] In a specific example, forming the patterned lower electrode material layer 120 on the substrate 110 can include: depositing a continuous thin film of lower electrode material on the substrate 110 (as shown in FIG. 4(b)); depositing an etch-resistant layer 160 (as shown in FIG. 4(c)), wherein at least a portion of the etch-resistant layer 160 fills in the first trench 111 and the second trench 112; etching to remove at least a portion of the lower electrode material outside the first trench 111 and the second trench 112, thereby forming the patterned lower electrode material layer 120; and removing the remaining etch-resistant layer 160 (as shown in FIG. 4(d)).

[0074] In some embodiments, etching can be performed directly after the deposition of the etch resist layer 160. This is because the difference between the thickness of the portion of the etch resist layer in the trenches and the thickness of the portion outside the trenches is usually large enough, so that during the etching process, even if the etch resist and the lower electrode material in the areas outside the trenches have been completely removed, there is still enough etch resist in the trenches to protect the lower electrode material in the trenches. Alternatively, in other embodiments, after the deposition of the etch resist layer 160, at least part of the etch resist above the lower electrode material outside the trenches can also be removed based on a photolithography process, as needed, and then etching is performed to form the desired patterned lower electrode material layer 120. Alternatively, in other embodiments, similar to the process of forming the trenches in the active region as described above, a corresponding etch resist layer can also be formed as needed to further improve the etching ratio to form the desired patterned lower electrode material layer 120.

[0075] In some embodiments, the etch resist layer 160 can be formed only of photoresist. Alternatively, in other embodiments, the etch resist layer 160 can be a bottom anti-reflective layer (BARC). BARC is a photoresist layer coated after an anti-reflective coating is first coated, and its purpose is to reduce the amount of light reflected from the surface of the substrate back to the photoresist layer, to reduce the standing wave effect and improve the photolithography effect.

[0076] In general, the etch resist layer 160 can be formed of a polymer material with good fluidity, so that the etch resist layer 160 can be deposited by spin coating or the like, so that part of it fills the first trench 111 and the second trench 112, and the other part is distributed on the upper surface of the lower electrode material outside the trenches. Accordingly, after etching is completed, the remaining etch resist layer 160 can be removed by high temperature or solution dissolution. For example, substantially most of the etch resist can be first removed by heating in an oxygen-containing environment, and then the remaining etch resist is cleaned off using a wet process.

[0077] Further, as shown in FIGS. 4(e) to 4(g), sequentially forming, from bottom to top, the lower electrode material layer 120, the storage material layer 130, the upper electrode material layer 140 and the isolation material portion 150 on the substrate 110 to generate the first trench assembly 101 and the second trench assembly 102 can include: sequentially depositing continuous thin film of storage material, continuous thin film of upper electrode material and isolation material; and performing etching to remove at least part of the isolation material, at least part of the upper electrode material and at least part of the storage material outside the first trench 111 and the second trench 112, thereby forming the patterned storage material layer 130, the upper electrode material layer 140 and the isolation material portion 150. Among them, the storage material layer 130 can include the first storage material portion 131 located in the first trench 111 and the second storage material portion 132 located in the second trench 112, the upper electrode material layer 140 can include the first upper electrode material portion 141 located in the first trench 111 and the second upper electrode material portion 142 located in the second trench 112, and the isolation material portion 150 can include the first isolation material portion 151 filled in the first trench 111 and the second isolation material portion 152 filled in the second trench 112.

[0078] In some embodiments, the storage material layer 130 can be formed of phase change storage material, and accordingly, the memory device is a phase change memory device (PCM). Here, the phase change memory device is a kind of non-volatile memory device, which utilizes the difference in electrical conductivity between the crystalline state and the amorphous state of the material to store data, has the excellent characteristics of not losing data when power off, low power consumption, high read-write speed, high integration, etc., and is compatible with the Complementary Metal Oxide Semiconductor (CMOS) process, and is expected to replace the current mainstream products such as Static Random Access Memory (SRAM), Dynamic Random Access Memory (DRAM) and Flash, and become the future mainstream commercial product. Further, in some embodiments, the storage material layer 130 can be formed of ferroelectric material. The ferroelectric material has ferroelectricity, which refers to the spontaneous polarization of the material within a certain temperature range, and the spontaneous polarization disappears when the temperature is higher than a certain critical value. Therefore, the storage of data can be realized by using the phase change of the ferroelectric material. In some specific examples, at least one of zirconium oxide, hafnium oxide, titanium oxide, aluminum oxide, nickel oxide and iron oxide can be used as the material of the storage material layer 130.

[0079] In addition, in some embodiments, the storage material layer 130 can be formed by an atomic layer deposition (ALD) method. The storage material layer 130 formed by such a method can conformally grow on the substrate 110 on which the lower electrode material layer 120 has been formed, and form a good contact with the underlying lower electrode material layer 120, which can help improve the performance of the memory device and avoid process contamination, etc.

[0080] In some embodiments, the lower electrode material layer 120 and the upper electrode material layer 140 can be formed of the same electrode material. Alternatively, in other embodiments, the lower electrode material layer 120 and the upper electrode material layer 140 can also be formed of different electrode materials. The electrode material is a conductive material, such as a conductive metal or a conductive compound, etc. In a specific example, at least one of the lower electrode material layer 120 and the upper electrode material layer 140 can be formed of at least one of titanium, titanium nitride, titanium silicon nitride, titanium aluminum nitride, titanium carbon nitride, tantalum nitride, tantalum silicon nitride, tantalum aluminum nitride, tungsten nitride, tungsten silicide, doped polysilicon, and transparent conductive oxide. For example, the titanium nitride material has a certain adhesion, which helps form a conductive film with high quality, thereby improving the performance of the device.

[0081] In addition, in some embodiments, at least one of the lower electrode material and the upper electrode material can be deposited by an ALD method to help improve the performance of the memory device and avoid process contamination, etc. Alternatively, in other embodiments, at least one of the lower electrode material and the upper electrode material can also be deposited by a physical vapor deposition (PVD) method to effectively increase the deposition rate, improve the preparation efficiency of the device, etc.

[0082] In some embodiments, as shown in FIGS. 4(f) and 4(g), depositing the isolation material can include: depositing the isolation material by a high-density plasma chemical vapor deposition (HDP CVD) method; and performing chemical mechanical polishing on an upper surface of the deposited isolation material to form the isolation material with a flat upper surface. In some specific examples, the isolation material can cover the entire upper surface of the upper electrode material. Alternatively, in other specific examples, the isolation material can just fill the trench and be substantially flush with the upper surface of the upper electrode material. In both cases, the upper surface can be further flattened by the CMP process as described above for the subsequent process. In some specific examples, the isolation material can be formed of an electrically insulating oxide, nitride, oxynitride, etc., which is not limited herein.

[0083] In some embodiments, the isolation material, the upper electrode material and the storage material can be etched in the same process operation to form the structure as shown in FIG. 4(g). Considering that the etching stops only when reaching the substrate 110 and the difference in etching rate between different materials, in a specific example, the first trench assembly 101 and the second trench assembly 102 can slightly protrude relative to the upper surface of the substrate 110, as presented in FIG. 4(g). In addition, in some embodiments, the portions of the upper electrode material outside the first trench 111 and the second trench 112 can be completely removed by etching, as shown in FIG. 4(g), i.e., the upper electrode material layer 140 only includes the first upper electrode material portion 141 and the second upper electrode material portion 142. Alternatively, in other embodiments, at least a portion of the upper electrode material outside the first trench 111 and connected to the first upper electrode material portion 141 can also be reserved, so as to subsequently electrically connect the memory device to other electronic devices or external circuits, as will be described in detail later.

[0084] According to the above description, it can be known that the first lower electrode material portion 121 in the first trench 111 and the second lower electrode material portion 122 in the second trench 112 can be formed synchronously, the first storage material portion 131 in the first trench 111 and the second storage material portion 132 in the second trench 112 can be formed synchronously, the first upper electrode material portion 141 in the first trench 111 and the second upper electrode material portion 142 in the second trench 112 can be formed synchronously, and the first isolation material portion 151 filled in the first trench 111 and the second isolation material portion 152 filled in the second trench 112 can be formed synchronously, accordingly, the first trench assembly 101 which can be used to form the memory device and the second trench assembly 102 which can be used to form the isolation component can be formed synchronously, i.e., the memory device in the present application can be formed synchronously with the isolation component, instead of being additionally prepared before or after forming the isolation component.

[0085] In some embodiments, in order to guarantee the performance of the memory device, the total thickness of the lower electrode material layer 120, the storage material layer 130 and the upper electrode material layer 140 can be less than twice the minimum width of the first trench 111, and the total thickness of the lower electrode material layer 120, the storage material layer 130 and the upper electrode material layer 140 can be less than twice the minimum width of the second trench 112. In this way, on the one hand, the undesired connection or short circuit of the storage material or the electrode material deposited on the opposite side walls of the trench is avoided, and on the other hand, the wider trench also helps the lower electrode material layer 120, the storage material layer 130 and the upper electrode material layer 140 to conformably grow on the inner wall of the trench. For example, in some specific examples, the thickness of at least one of the lower electrode material layer 120 and the upper electrode material layer 140 can be on the order of several nanometers to tens of nanometers (e.g., 10-20 nm or 20-40 nm), and the thickness of the storage material layer 130 can also be on the order of several nanometers to tens of nanometers (e.g., 5-10 nm or 10-20 nm). In addition, in order to guarantee the electrical isolation effect of the isolation component, the depth and width of the trench should be large enough. For example, in some specific examples, the depth of at least one of the first trench 111 and the second trench 112 can be 300-400 nm or 400-500 nm. In addition, the width of at least one of the first trench 111 and the second trench 112 can be 130-190 nm or 190-250 nm. It can be understood that other sizes of memory devices and trenches can also be set as needed, which are not limited herein.

[0086] In addition, as shown in FIG. 4(a), the included angle a between at least one side surface of the first trench 111 and the bottom surface thereof can be greater than or equal to 90°, and similarly, the included angle a between at least one side surface of the second trench 112 and the bottom surface thereof can be greater than or equal to 90°. In the case where the included angle a is equal to 90°, the planar area occupied by the memory device can be reduced while the quality of the subsequent film layer deposition is maintained as much as possible. In the case where the included angle a is greater than 90°, it can help the film layer to grow better into the trench, form a more reliable connection between the film layers deposited on the inner wall of the trench, and also help to avoid the gap between the upper film layer and the lower film layer when the subsequent film layer is deposited by using a method such as physical vapor deposition, so that one or more film layers can be formed with high quality.

[0087] Further, as shown in FIG. 4(h), after the first trench assembly 101 and the second trench assembly 102 are generated, the device fabrication method can further include forming other electronic devices 200 on the substrate 110, which are different from the memory devices. Among the formed devices, at least two adjacent devices can be respectively arranged on both sides of the second trench assembly 102 as an isolation component, to achieve electrical isolation between the devices. In some embodiments, the other electronic devices can include logic devices and the like, which can cooperate with the memory devices to achieve desired functions. In a specific example, after the logic device 100 as shown in FIG. 4(g) is formed, a CMOS logic device 200 or the like can be fabricated based on a CMOS process or the like, as illustrated in FIG. 4(h).

[0088] In addition, in some embodiments, as shown in FIGS. 4(i) and 4(j), after the first trench assembly 101 and the second trench assembly 102 are generated, the device fabrication method can further include forming a dielectric protective layer 300 above the devices, conductive connections inside the dielectric protective layer 300, and wiring layers above the dielectric protective layer 300. The devices here can include all devices formed on the substrate 110, including the memory devices 100 and the other electronic devices 200 that can exist. The dielectric protective layer 300 can be formed of the same or different dielectric material as the isolation material, to avoid the adverse effects of oxygen, water, dust, and the like in the air on the devices, thereby prolonging the service life of the devices. In addition, the dielectric protective layer 300 can also serve as a carrier for the subsequently formed conductive connections and wiring layers and the like. For example, the dielectric protective layer 300 can be formed of insulating oxides, insulating nitrides, insulating oxynitrides, and the like, including silicon oxide, aluminum oxide, silicon nitride, aluminum nitride, and the like. Among them, the conductive connections can include first and second conductive connections 410 and 420 respectively electrically connected to the portions of the lower electrode material layer 120 and the upper electrode material layer 140 in the first trench 111, and the wiring layers can include first and second wiring layers 510 and 520 respectively electrically connected to the first and second conductive connections 410 and 420, to connect the memory devices to other electronic devices or external circuits. It can be understood that in the presence of other electronic devices, more conductive connections and / or wiring layers can also be included to guide the corresponding electronic devices to other devices or external circuits. Among them, the conductive connections and the wiring layers can be formed of conductive materials, such as metal materials such as copper, tungsten, and other conductive compound materials, and the like.

[0089] It can be understood that the conductive connections associated with multiple devices can be formed synchronously to simplify the process, and the following will be described by taking the preparation of the conductive connections associated with the memory devices as an example. Specifically, as shown in FIGS. 4(h) to 4(j), forming the first conductive connection 410 electrically connected to the portion of the lower electrode material layer 120 located in the first trench 111 can include: forming a contact 600 in the portion of the substrate 110 adjacent to the first trench assembly 101, where the contact 600 can be electrically connected to the first lower electrode material portion 121 of the lower electrode material layer 120 located in the first trench 111; and forming the first conductive connection 410 above the contact 600, where the first conductive connection 410 can be configured to electrically connect the contact 600 to the first wiring layer 510.

[0090] Specifically, the contact 600 can be prepared based on a silicide or salicide process, etc. (metal silicide) process. For example, the active region 113 can be etched to form a space accommodating the contact 600, and then a metal (e.g., cobalt, etc.) is filled in the space, and then heated to make the metal and the silicon in the active region 113 react at high temperature to produce a metal silicide (e.g., cobalt silicide) as the contact 600. Such a metal silicide contact can effectively reduce the contact barrier, thereby reducing the contact resistance and improving the stability and performance of the device.

[0091] In some embodiments, as shown in FIGS. 4(i) and 4(j), forming the second conductive connection 420 electrically connected to the portion of the upper electrode material layer 140 located in the first trench 111 can include: etching at least a portion of the first isolation material portion 151 of the isolation material 150 filled in the first trench 111 until a portion of the upper electrode material layer 140 is exposed; and forming the second conductive connection 420 above the exposed portion of the upper electrode material layer 140, where the second conductive connection 420 can be configured to electrically connect the upper electrode material layer 140 to the second wiring layer 520.

[0092] Alternatively, in some other embodiments, in the case where the upper electrode material layer includes an upper electrode lead portion located outside the first trench and electrically connected to the portion of the upper electrode material layer located in the first trench, forming the second conductive connection electrically connected to the portion of the upper electrode material layer located in the first trench can include forming the second conductive connection over the upper electrode lead portion, where the second conductive connection can be configured to electrically connect the upper electrode material layer to the second wiring layer. For example, the upper electrode lead portion can be located on the side of the first trench assembly opposite the contact portion, such as on the left side of the first trench assembly 101 in FIG. 4(i), and the second conductive connection can be formed directly on the upper electrode lead portion located on the upper surface of the substrate 110, without the need to etch the first isolation material portion to expose the upper electrode material layer, thereby facilitating simplification of the process.

[0093] In some embodiments, as shown in FIG. 4(i), the via can be formed by etching at the corresponding position of the dielectric protection layer 300, and then the conductive material such as tungsten can be filled in the via to form the corresponding conductive connection. In addition, it can be understood that after the dielectric protection layer and the conductive connection are formed, a CMP process can also be performed to make the upper surfaces of the dielectric protection layer 300 and the conductive connection flat, thereby improving the quality of subsequent processes.

[0094] Further, as shown in FIG. 4(j), one or more patterned wiring layers can be formed at the corresponding position of the dielectric protection layer 300 by processes such as photolithography and etching, or by processes such as photolithography, deposition, and stripping, and the one or more wiring layers can be electrically connected to the corresponding one or more conductive connections.

[0095] In addition, in the embodiments of the present disclosure, since the second trench assembly 102 is used as an isolation component, no conductive connection or the like is generally provided to connect the second trench assembly 102 to other electronic devices or external circuits to ensure its electrical isolation effect.

[0096] The present disclosure also provides a memory device. As described above, the memory device 100 can include a first lower electrode material portion 121, a first storage material portion 131, and a first upper electrode material portion 141 stacked in sequence from bottom to top along the inner wall of the first trench 111 in the substrate 110. Among them, the first lower electrode material portion 121 and the first upper electrode material portion 141 respectively serve as two electrodes of the memory device 100, while the first storage material portion 131 serves as a functional layer of the memory device. By applying a corresponding voltage to the first storage material portion 131 between the first lower electrode material portion 121 and the first upper electrode material portion 141, the electrical state of the first storage material portion 131 can be changed as needed, thereby enabling the storage of data. In addition, the various parameters described above in relation to the structure of the device in the device preparation method can be applied to the memory device described herein, either individually or in combination. In addition, it can be understood that the memory device of the present disclosure can be prepared by the device preparation method as described above.

[0097] Further, the present disclosure also provides a semiconductor device. As shown in FIG. 4(j), the semiconductor device can include one or more memory devices 100 as described above. For example, the semiconductor device can be a memory device that can include a plurality of memory devices arranged in an array, thereby enabling the storage of a large amount of data. In a specific example, the memory device can be a non-volatile memory or the like used in a computer.

[0098] Further, in some embodiments, as shown in FIG. 4(j), the semiconductor device can also include other electronic devices 200 different from the memory devices 100. For example, the other electronic devices 200 can include logic devices or the like, which can work with the memory devices 100 to achieve the desired functions. For example, the logic devices can include CMOS devices or the like. It can be understood that, as needed, the other electronic devices can also be other types of devices different from the memory devices and the logic devices, which are not limited herein.

[0099] In the technical solution of the present disclosure, the memory device can be formed in advance synchronously with the isolation component, or in other words, the first trench assembly in which the memory device is located in the semiconductor device can be formed synchronously with the second trench assembly for forming the isolation component, and then other electronic devices, dielectric protection layers, conductive connecting members and / or wiring layers, etc. are formed as needed. In this way, the other electronic devices can be formed after the formation of the memory device, so that the adverse effects of the thermal budget associated with the formation process of the memory device on the other electronic devices can be avoided, thereby helping to improve the performance of the entire semiconductor device, enhance the reliability of the devices and semiconductor device therein, and prolong the service life of the devices and semiconductor device. In addition, the device preparation method of the present disclosure can effectively reduce the process steps required in the preparation process of the entire semiconductor device, for example, at least three layers of masks and associated processes can be saved, thereby reducing production costs and improving production efficiency. Moreover, since the memory device is formed synchronously with the isolation component, the substrate is substantially flat at this time, so that the introduction of steps or even discontinuity or breakage, etc. in the film layer of the memory device can be avoided, which helps to improve the performance of the memory device. In addition, the memory device of the present disclosure is at least integrated on the bottom wall and side wall of the trench, forming a 3D structure of the memory device, which helps to increase the effective area of the memory device, thereby enhancing the performance of the memory device. Further, since the storage material layer in the memory device can be electrically insulating itself, its presence in the isolation component can help to achieve electrical isolation between devices, without damaging the original trench isolation performance, and even can improve the trench isolation performance to some extent.

[0100] The words "left," "right," "front," "back," "top," "bottom," "over," "under," "upper," "lower," and the like in the description and the claims, if any, are used for descriptive purposes and not necessarily for describing permanent relative positions. It is to be understood that the use of such terms can be interchanged in suitable circumstances, so that the embodiments of the present disclosure described herein, for example, can operate in other orientations than those shown or otherwise described herein. For example, when the device in the drawings is inverted, a feature that was originally described as "above" other features can now be described as "below" the other features. The device can also be oriented in other ways (rotated 90 degrees or in other orientations), and the relative spatial relationships will be interpreted accordingly.

[0101] In the description and claims, the terms "on", "attached to", "connected to", "coupled to", or "in contact with" one element to another element, among others, can mean the element is either directly on, directly attached to, directly connected to, directly coupled to, or directly in contact with the other element or one or more intervening elements can also be present. In contrast, the terms "directly on", "directly attached to", "directly connected to", "directly coupled to", or "directly in contact with" one element to another element mean that there are no intervening elements present. In the description and claims, one feature being arranged "adjacent" to another feature can mean that the feature has a portion that overlaps with the adjacent feature or a portion that is above or below the adjacent feature.

[0102] As used herein, the word "exemplary" means "serving as an example, instance, or illustration," and not "preferred" or "advantageous over other implementations." In addition, the disclosure is not limited to any expressed or implied theory of operation by any of the arrangements described in technical field, background, summary or detailed description of the application.

[0103] As used herein, the word "substantially" means including any minor variations as a result of design or manufacturing tolerances, environmental influences, and / or other factors. The word "substantially" also allows for differences between a perfect or ideal situation and a real-world implementation.

[0104] In addition, the terms "first", "second", and other similar terms are also used herein, merely for purposes of reference, and thus do not imply a order or sequence unless clearly indicated by the context.

[0105] It will also be understood that, when used in this document, the term "comprising" is taken to mean the inclusion of one or more features, elements, steps, operations, units and / or components, but not to the exclusion of other features, elements, steps, operations, units and / or components, and that the indefinite articles "a" or "an" are used herein to refer to one or more items.

[0106] In the present disclosure, the term "providing" is used in a broad sense to cover all ways of obtaining an object, and thus "providing an object" includes, but is not limited to, "purchasing", "preparing / manufacturing", "arranging / setting", "installing / fitting", and / or "ordering" the object, etc.

[0107] As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.

[0108] Those skilled in the art will realize that the boundaries between the above described operations merely illustrative. The multiple operations can be combined into a single operation, a single operation can be distributed in additional operations and operations can be executed at least partially overlapping in time. Moreover, alternative embodiments can include a number of instances of a particular operation, and the order of the operations can be altered in other various embodiments. However, other modifications, variations and alternatives are also possible. The aspects and elements of all such embodiments can be combined in any manner and / or with other aspects or elements, in accordance with the application, to provide additional embodiments within the scope of the present disclosure. Thus, the description and drawings merely exemplify the principles of the present disclosure. The scope of the present disclosure should not be limited by the specific illustrative disclosure given above.

[0109] While specific embodiments of the disclosure have been described above with reference to exemplary examples, it is to be understood that various other adaptations and modifications of the disclosure can be employed without departing from the scope of the disclosure. Therefore, the true scope of the disclosure is not to be limited to any of the foregoing embodiments. Rather, it is intended to cover all adaptations, modifications, and alterations that fall within the scope of the disclosure. The disclosures of each patent, patent application, and publication cited or described in this document are hereby incorporated herein by reference, each in its entirety.

Claims

1. A device fabrication method, comprising: providing a substrate, wherein the substrate comprises an active region in which a first trench and a second trench are formed; and forming, on the substrate, a lower electrode material layer, a memory material layer, an upper electrode material layer, and an isolation material portion sequentially from bottom to top to produce a first trench assembly and a second trench assembly; wherein the first trench assembly is formed from portions of the lower electrode material layer, the memory material layer, the upper electrode material layer, and the isolation material portion that are located in the first trench, and the first trench assembly is configured for forming a memory device, the second trench assembly is formed from portions of the lower electrode material layer, the memory material layer, the upper electrode material layer, and the isolation material portion that are located in the second trench, and the second trench assembly is configured for forming an isolation component, the first trench assembly and the second trench assembly are electrically isolated from each other.

2. A device production method according to claim 1, wherein forming, on the substrate, a lower electrode material layer, a memory material layer, an upper electrode material layer, and an isolation material portion sequentially from bottom to top to produce a first trench assembly and a second trench assembly comprises: forming a patterned lower electrode material layer on the substrate, wherein the lower electrode material layer comprises a first lower electrode material portion covering inner walls of the first trench and a second lower electrode material portion covering inner walls of the second trench, and the first lower electrode material portion and the second lower electrode material portion are disconnected from each other; sequentially depositing a continuous thin film of memory material, a continuous thin film of upper electrode material, and an isolation material; performing etching to remove at least a portion of the isolation material, at least a portion of the upper electrode material, and at least a portion of the memory material that are outside of the first trench and the second trench, thereby forming a patterned memory material layer, an upper electrode material layer, and an isolation material portion, wherein the memory material layer comprises a first memory material portion located in the first trench and a second memory material portion located in the second trench, the upper electrode material layer comprises a first upper electrode material portion located in the first trench and a second upper electrode material portion located in the second trench, and the isolation material portion comprises a first isolation material portion filling in the first trench and a second isolation material portion filling in the second trench. forming a patterned lower electrode material layer on the substrate comprises:

3. A device production method according to claim 2, wherein depositing a continuous thin film of lower electrode material on the substrate; depositing an etch resist layer, wherein at least a portion of the etch resist layer fills in the first trench and the second trench; performing etching to remove at least a portion of the lower electrode material that are outside of the first trench and the second trench, thereby forming a patterned lower electrode material layer; and removing the remaining etch resist layer. the etch resist layer comprises a bottom anti-reflective layer.

4. A device production method according to claim 3, wherein at least one of the lower electrode material, the memory material, and the upper electrode material is deposited by atomic layer deposition.

5. A device production method according to claim 2, wherein depositing the isolation material comprises:

6. A device production method according to claim 2, wherein depositing the isolation material by high-density plasma chemical vapor deposition, wherein the isolation material covers an entire upper surface of the upper electrode material; and chemically mechanically polishing an upper surface of the deposited isolation material. ​ 7. A device production method according to claim 1, wherein a total thickness of the lower electrode material layer, the storage material layer, and the upper electrode material layer is less than twice a minimum width of the first trench and less than twice a minimum width of the second trench; and / or an angle between at least one side surface of the first trench and a bottom surface thereof is greater than or equal to 90°, and an angle between at least one side surface of the second trench and a bottom surface thereof is greater than or equal to 90°.

8. A device production method according to claim 1, wherein a depth of at least one of the first trench and the second trench is 300-400 nm or 400-500 nm; and / or a width of at least one of the first trench and the second trench is 130-190 nm or 190-250 nm.

9. A device production method according to claim 1, wherein at least one of the lower electrode material layer and the upper electrode material layer is formed of at least one of titanium, titanium nitride, titanium silicon nitride, titanium aluminum nitride, titanium carbonitride, tantalum nitride, tantalum silicon nitride, tantalum aluminum nitride, tungsten nitride, tungsten silicide, doped polysilicon, and transparent conductive oxide; and / or the storage material layer is formed of at least one of phase change storage material, ferroelectric material, zirconium oxide, hafnium oxide, titanium oxide, aluminum oxide, nickel oxide, and iron oxide.

10. A device production method according to claim 1, wherein after the first trench assembly and the second trench assembly are generated, the device manufacturing method further includes: forming, on the substrate, other electronic devices different from the memory devices, wherein at least two adjacent devices are respectively disposed on both sides of the second trench assembly as the isolation component.

11. A device production method according to claim 1, wherein after the first trench assembly and the second trench assembly are generated, the device manufacturing method further includes: forming a dielectric protection layer above the devices, a conductive connection inside the dielectric protection layer, and a wiring layer above the dielectric protection layer, wherein the conductive connection includes a first conductive connection and a second conductive connection respectively electrically connected with portions of the lower electrode material layer and the upper electrode material layer in the first trench, and the wiring layer includes a first wiring layer and a second wiring layer respectively electrically connected with the first conductive connection and the second conductive connection.

12. A device production method according to claim 11, wherein forming the first conductive connection electrically connected with the portion of the lower electrode material layer in the first trench includes: forming a contact in a portion of the substrate adjacent to the first trench assembly, wherein the contact is electrically connected with a first lower electrode material portion of the lower electrode material layer in the first trench, and the contact is formed of a metal silicide; and forming the first conductive connection above the contact, wherein the first conductive connection is configured to electrically connect the contact to the first wiring layer.

13. A device production method according to claim 11, wherein forming the second conductive connection electrically connected with the portion of the upper electrode material layer in the first trench includes: etching at least a portion of a first isolation material portion of the isolation material portion filled in the first trench until a portion of the upper electrode material layer is exposed; and forming the second conductive connection above the exposed portion of the upper electrode material layer, wherein the second conductive connection is configured to electrically connect the upper electrode material layer to the second wiring layer.

14. A device production method according to claim 11, wherein In a case where the upper electrode material layer includes an upper electrode lead portion outside the first trench and electrically connected to the portion of the upper electrode material layer in the first trench, forming the second conductive connection electrically connected to the portion of the upper electrode material layer in the first trench includes: forming the second conductive connection over the upper electrode lead portion, wherein the second conductive connection is configured to electrically connect the upper electrode material layer to the second wiring layer.

15. A memory device including, stacked in order from bottom to top along an inner wall of a first trench in a substrate, a first lower electrode material portion, a first storage material portion, and a first upper electrode material portion.

16. The memory device of claim 15, wherein, The memory device is manufactured by the device manufacturing method according to any one of claims 1 to 14.

17. A semiconductor apparatus including one or more memory devices according to claim 15 or 16.

18. The semiconductor apparatus according to claim 17, further including other electronic devices different from the memory devices.

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