Array substrate of electronic paper device, and display apparatus

Abstract

An array substrate of an electronic paper device, and a display apparatus. The array substrate is provided with a plurality of sub-pixels arranged in a plurality of rows and a plurality of columns. The array substrate comprises a base substrate (111), a plurality of first signal lines (101) and a plurality of second signal lines (102), wherein the plurality of first signal lines (101) are disposed on the base substrate (111) and at least partially extend in a first direction (R1), at least one of the plurality of first signal lines (101) is electrically connected to two adjacent rows of sub-pixels, the plurality of second signal lines (102) are disposed on the base substrate (111) and at least partially extend in a second direction (R2), the second direction (R2) being different from the first direction (R1), the two adjacent rows of sub-pixels comprise a first sub-pixel (P1) and a second sub-pixel (P2), which are located in the same column, and the plurality of second signal lines (102) comprise a first signal sub-line (1021) and a second signal sub-line (1022), the first signal sub-line (1021) being electrically connected to the first sub-pixel (P1), and the second signal sub-line (1022) being electrically connected to the second sub-pixel (P2). The array substrate can realize a narrow-frame design, and has a lower preparation cost.

Description

Array substrate of electronic paper device and display device

[0001] This application claims priority to Chinese Patent Application No. 202410732707.5, filed on June 06, 2024, the disclosure of which is incorporated herein in its entirety as part of the present application. TECHNICAL FIELD

[0002] Embodiments of the present disclosure relate to an array substrate of an electronic paper device and a display device. BACKGROUND

[0003] Electronic Paper Display (EPD) has gradually been applied in education, medical treatment and many other fields and people's daily reading life due to its eye protection, low power consumption, portability, and the like.

[0004] At present, how to reduce the frame of the electronic paper display to improve the display effect of the display and reduce the production cost of the display while ensuring the resolution is one of the main problems faced by manufacturers. SUMMARY

[0005] At least one embodiment of the present disclosure provides an array substrate of an electronic paper device, the array substrate having a plurality of sub-pixels arranged in a plurality of rows and a plurality of columns, and comprising a substrate substrate, a plurality of first signal lines and a plurality of second signal lines, the plurality of first signal lines being disposed on the substrate substrate and extending at least partially along a first direction, wherein at least one first signal line of the plurality of first signal lines is electrically connected to two adjacent rows of sub-pixels, the plurality of second signal lines being disposed on the substrate substrate and extending at least partially along a second direction different from the first direction, wherein the two adjacent rows of sub-pixels comprise a first sub-pixel and a second sub-pixel located in the same column, the plurality of second signal lines comprise a first sub-signal line and a second sub-signal line, the first sub-signal line being electrically connected to the first sub-pixel, and the second sub-signal line being electrically connected to the second sub-pixel.

[0006] For example, in the array substrate provided by at least one embodiment of the present disclosure, the first sub-signal line and the second sub-signal line are respectively located on opposite sides of the column in which the first sub-pixel and the second sub-pixel are located.

[0007] For example, in the array substrate provided by at least one embodiment of the present disclosure, there are two second signal lines between two adjacent columns of sub-pixels.

[0008] For example, in the array substrate provided by at least one embodiment of the present disclosure, the first signal line is a scan line configured to provide a scan signal, and the second signal line is a data line configured to provide a data signal.

[0009] For example, in the array substrate provided by at least one embodiment of the present disclosure, the at least one first signal line comprises a first lead line and a first branch line and a second branch line electrically connected to the first lead line, the first branch line and the second branch line extend along the first direction, the two adjacent rows of sub-pixels comprise a first row of sub-pixels and a second row of sub-pixels, the first branch line is electrically connected to the first row of sub-pixels, and the second branch line is electrically connected to the second row of sub-pixels.

[0010] For example, in the array substrate provided by at least one embodiment of the present disclosure, at least part of the first lead line extends along the second direction.

[0011] For example, in the array substrate provided by at least one embodiment of the present disclosure, the first row of sub-pixels comprises the first sub-pixel, the second row of sub-pixels comprises the second sub-pixel, the first branch line is arranged between the first row of sub-pixels and the second row of sub-pixels, and the second branch line is arranged on a side of the second row of sub-pixels away from the first row of sub-pixels, the first sub-pixel comprises a first transistor and a first pixel electrode electrically connected to the first transistor, the second sub-pixel comprises a second transistor and a second pixel electrode electrically connected to the second transistor, the first transistor is arranged on a side of the first pixel electrode close to the first branch line, and the second transistor is arranged on a side of the second pixel electrode close to the second branch line.

[0012] For example, in the array substrate provided by at least one embodiment of the present disclosure, in the second direction, the first transistor and the second transistor are arranged in a staggered manner.

[0013] For example, in the array substrate provided by at least one embodiment of the present disclosure, the first transistor comprises a first gate electrode electrically connected to the first branch line, a first electrode electrically connected to the first sub-signal line and a second electrode spaced from the first electrode, the second transistor comprises a second gate electrode electrically connected to the second branch line, a third electrode electrically connected to the second sub-signal line and a fourth electrode spaced from the third electrode, the first gate electrode and the second gate electrode extend along the second direction, the first electrode and the second electrode are arranged on the same side of the first branch line, and the third electrode and the fourth electrode are arranged on the same side of the second branch line.

[0014] For example, in the array substrate provided by at least one embodiment of the present disclosure, the first gate electrode and the first branch line are arranged in the same layer and integrally connected, and the second gate electrode and the second branch line are arranged in the same layer and integrally connected.

[0015] For example, in the array substrate provided by at least one embodiment of the present disclosure, the first electrode is arranged in the same layer as the first sub-signal line and is integrally connected with the first sub-signal line, and the third electrode is arranged in the same layer as the second sub-signal line and is integrally connected with the second sub-signal line.

[0016] For example, in the array substrate provided by at least one embodiment of the present disclosure, the first row of sub-pixels includes the first sub-pixel, the second row of sub-pixels includes the second sub-pixel, the first transistor includes a first gate electrode electrically connected with the first branch line, a first electrode electrically connected with the first sub-signal line, and a second electrode spaced apart from the first electrode, the second transistor includes a second gate electrode electrically connected with the second branch line, a third electrode electrically connected with the second sub-signal line, and a fourth electrode spaced apart from the third electrode, the first gate electrode and the second gate electrode extend along the first direction, and the first electrode and the second electrode are respectively arranged on opposite sides of the first branch line, and the third electrode and the fourth electrode are respectively arranged on opposite sides of the second branch line in the second direction.

[0017] For example, in the array substrate provided by at least one embodiment of the present disclosure, the at least one first signal line includes a first lead line and a first signal main line electrically connected with the first lead line, the first signal main line extends along the first direction and connects the two adjacent rows of sub-pixels.

[0018] For example, in the array substrate provided by at least one embodiment of the present disclosure, the first signal main line is arranged between the two adjacent rows of sub-pixels, the first sub-pixel includes a first transistor and a first pixel electrode electrically connected with the first transistor, the second sub-pixel includes a second transistor and a second pixel electrode electrically connected with the second transistor, and the first transistor and the second transistor are arranged between the first pixel electrode and the second pixel electrode.

[0019] For example, in the array substrate provided by at least one embodiment of the present disclosure, at least part of the first lead line extends along the second direction.

[0020] For example, in the array substrate provided by at least one embodiment of the present disclosure, the plurality of second signal lines are arranged on a side of the plurality of first signal lines away from the substrate substrate, and the first pixel electrode and the second pixel electrode are arranged on a side of the plurality of second signal lines away from the substrate substrate.

[0021] At least one embodiment of the present disclosure also provides a display device, which includes the array substrate provided by the embodiments of the present disclosure. BRIEF DESCRIPTION OF DRAWINGS

[0022] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present disclosure and not limit the present disclosure.

[0023] FIG. 1 is a schematic cross-sectional view of an electronic paper display according to at least one embodiment of the present disclosure;

[0024] FIGS. 2A, 2B and 2C are schematic structural views of an electronic paper display in different states according to at least one embodiment of the present disclosure;

[0025] FIG. 3 is a partial circuit diagram of the electronic paper display in FIG. 1;

[0026] FIG. 4 is a circuit connection diagram of a partial sub-pixel of the electronic paper display in FIG. 1;

[0027] FIG. 5 is a circuit connection diagram of an array substrate of an electronic paper device according to at least one embodiment of the present disclosure;

[0028] FIG. 6 is a circuit connection diagram of a partial sub-pixel of the array substrate in FIG. 5;

[0029] FIG. 7 is a schematic cross-sectional view of a sub-pixel in FIG. 6 along the dotted line NN;

[0030] FIG. 8A is a plan view of a first transistor in the array substrate according to at least one embodiment of the present disclosure;

[0031] FIG. 8B is a plan view of a second transistor in the array substrate according to at least one embodiment of the present disclosure;

[0032] FIG. 9 is a schematic cross-sectional view of the first transistor and the second transistor in FIGS. 8A and 8B along the dotted line BB;

[0033] FIGS. 10A and 10B are plan views of the first transistor and the second transistor in the array substrate according to at least one embodiment of the present disclosure after a shift of a first metal layer and a second metal layer;

[0034] FIG. 11A is a schematic cross-sectional view of the first transistor in FIG. 10A along the dotted line CC;

[0035] FIG. 11B is a schematic cross-sectional view of the second transistor in FIG. 10B along the dotted line DD;

[0036] FIG. 12 is a circuit connection diagram of another array substrate according to at least one embodiment of the present disclosure;

[0037] FIG. 13A is a plan view of a first transistor in the array substrate in FIG. 12;

[0038] FIG. 13B is a plan view of a second transistor in the array substrate in FIG. 12;

[0039] Figures 14A and 14B are schematic planar views of the first transistor and the second transistor in another array substrate provided by at least one embodiment of the present disclosure after the first metal layer and the second metal layer are offset.

[0040] Figure 15 is a circuit connection diagram of another array substrate provided in at least one embodiment of the present disclosure;

[0041] Figure 16 is a circuit connection diagram of some sub-pixels of the array substrate in Figure 15;

[0042] Figure 17A is a planar schematic diagram of the first transistor in the array substrate of Figure 16;

[0043] Figure 17B is a planar schematic diagram of the second transistor in the array substrate of Figure 16; and

[0044] Figure 18 is a cross-sectional schematic diagram of a display device provided in at least one embodiment of the present disclosure. Detailed Implementation

[0045] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the described embodiments of this disclosure without creative effort are within the scope of protection of this disclosure.

[0046] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as “comprising” or “including” mean that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. Terms such as “connected” or “linked” are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. Terms such as “upper,” “lower,” “left,” and “right” are used only to indicate relative positional relationships, and these relative positional relationships may change accordingly when the absolute position of the described objects changes.

[0047] Figure 1 is a cross-sectional schematic diagram of an electronic paper display provided in at least one embodiment of the present disclosure. As shown in Figure 1, the electronic paper display includes structures such as an array substrate 01, an adhesive 02, a display layer 03, a counter electrode 04, a counter substrate 05, and a protective film 06.

[0048] For example, as shown in FIG. 1, the array substrate 01 can include a substrate and driving circuit and pixel electrode and other structures for a plurality of sub-pixels A arranged on the substrate. The display layer 03 can be an electronic ink layer including an adhesive and display units for a plurality of sub-pixels A arranged in the adhesive, each display unit of each sub-pixel A is, for example, a microcapsule structure, each display unit includes transparent electrophoretic liquid 031, white particles 032 and black particles 033, the white particles 032 can be, for example, titanium dioxide particles, positively charged, and the black particles 033 can be, for example, carbon black particles, negatively charged. The adhesive 02 is used to adhere the display layer 03 and the array substrate 01.

[0049] For example, as shown in FIG. 1, the opposing substrate 05 can include a PET film (PolyEthylene Terephthalate), and the opposing electrode 04 arranged on the opposing substrate 05 can be used as a common electrode, for example, an ITO (Indium Tin Oxides) transparent electrode is used to have a high light transmittance and to provide a common voltage for a plurality of sub-pixels. The opposing electrode 04 on the opposing substrate 05 and the pixel electrode of the array substrate 01 display the display units correspondingly. The protective film 06 is used to protect the opposing substrate 05, which can be, for example, an organic film.

[0050] For example, FIGS. 2A, 2B and 2C respectively show the structural schematic diagrams of the electronic paper display in different states. As shown in FIG. 2B, in the initial state, the reflective particles such as white particles 032 and black particles 033 are suspended in the transparent electrophoretic liquid 031, and the particles are uniformly arranged and randomly move, at this time, the electronic paper display does not display a picture. As shown in FIGS. 2A and 2C, when an electric field is applied between the pixel electrode and the opposing electrode 04, the white particles 032 and the black particles 033 move under the action of the electric field to realize display.

[0051] For example, as shown in FIG. 2A, when a negative voltage is applied to the opposing electrode 04 and a positive voltage is applied to the pixel electrode, under the action of the electric field, the white particles 032 gather on the side of the opposing electrode 04, and the black particles 033 gather on the side of the pixel electrode, at this time, under the reflection of natural light, the electronic paper display displays a white picture; as shown in FIG. 2C, when a positive voltage is applied to the opposing electrode 04 and a negative voltage is applied to the pixel electrode, under the action of the electric field, the white particles 032 gather on the side of the pixel electrode, and the black particles 033 gather on the side of the transparent electrode layer, at this time, under the reflection of natural light, the electronic paper display displays a black picture; thus, the electronic paper display can control each sub-pixel differently to realize the display of text and images.

[0052] For example, in some embodiments, at least one of the white particles 032 and the black particles 033 of each display unit can also be replaced by other reflective particles with colors, for example, the white particles 032 are replaced by particles that can reflect various colors such as red, green, blue, etc., and then under the control described above, the electronic paper display can realize color display.

[0053] For example, FIG. 3 shows a partial circuit diagram of the above-mentioned electronic paper display, and FIG. 4 shows a circuit connection diagram of a partial sub-pixel. As shown in FIGS. 3 and 4, the electronic paper display includes a display area AA and a peripheral area NA surrounding the display area AA, the display area AA is provided with a plurality of sub-pixels A for display operation, and the peripheral area NA is provided with an integrated circuit 10. A plurality of scan lines 11 are led out from the integrated circuit 10 and extend to the display area AA along the row direction, each scan line 11 is electrically connected to a row of sub-pixels A, for example, a driving circuit such as a transistor 14 of a row of sub-pixels, to provide a scanning signal for the row of sub-pixels A; a plurality of data lines 12 are led out from the integrated circuit 10 and extend to the display area AA along the column direction, each data line 12 is electrically connected to a column of sub-pixels A, for example, a driving circuit such as a transistor 14 of a column of sub-pixels, to provide a data signal for the column of sub-pixels A.

[0054] For example, the scanning signal can control whether the transistor 14 is turned on or not, and the data signal can control whether the sub-pixel A emits light or not. Thus, through the above-mentioned arrangement, the scanning signal and the data signal of each sub-pixel are not completely the same, so that each sub-pixel is independently controlled.

[0055] For example, in the peripheral area NA, the extension of the plurality of scan lines 11 needs to occupy a certain space, so that the peripheral area NA has a certain width. When the resolution of the electronic paper display is high, the number of scan lines 11 is large, and the space occupied by the plurality of scan lines 11 is larger, resulting in a wider peripheral area NA, which is difficult to realize a narrow frame design and meet the user's demand for narrow frame.

[0056] For example, for a display with a resolution of N*M (M and N are positive integers), the number of scan lines 11 on one side (for example, the left side or the right side) of the display area AA is N / 2, and assuming that the pitch of each scan line 11 (that is, the sum of the width of one scan line 11 and the spacing between adjacent scan lines 11) is P, then the calculation formula of the width X required by the peripheral area NA on one side (for example, the left side or the right side) of the display area AA is: X=P×(N / 2)+K,

[0057] Wherein, K is the width required by other designs except the scanning line 11. It can be seen that the larger N is, the larger X is; under the trend that the resolution of the current display is gradually increasing, the required peripheral area NA becomes wider, which on one hand increases the production cost, and on the other hand makes the display frame larger and difficult to realize the narrow frame design.

[0058] The array substrate of the electronic paper device and the display device including the array substrate provided by at least one embodiment of the present disclosure have a plurality of sub-pixels arranged in multiple rows and multiple columns, and include a substrate, a plurality of first signal lines and a plurality of second signal lines. The plurality of first signal lines are disposed on the substrate and extend at least partially along a first direction. At least one of the plurality of first signal lines is electrically connected to two adjacent rows of sub-pixels. The plurality of second signal lines are disposed on the substrate and extend at least partially along a second direction. The second direction is different from the first direction. Two adjacent rows of sub-pixels include a first sub-pixel and a second sub-pixel in the same column. The plurality of second signal lines include a first sub-signal line and a second sub-signal line. The first sub-signal line is electrically connected to the first sub-pixel. The second sub-signal line is electrically connected to the second sub-pixel.

[0059] The array substrate provided by the embodiments of the present disclosure can achieve narrow frame design without changing or even increasing the size and resolution (PPI) of the display, and can reduce product design and manufacturing costs and power consumption by designing the connection relationship between the first signal line, the second signal line and the sub-pixel.

[0060] The array substrate of the electronic paper device and the display device provided by the embodiments of the present disclosure will be described below through several specific examples.

[0061] The array substrate of the electronic paper device provided by at least one embodiment of the present disclosure is shown in FIG. 5, the circuit connection diagram of the array substrate is shown in FIG. 6, and the cross-sectional view of the sub-pixel P along the dashed line NN in FIG. 6 is shown in FIG. 7. As shown in FIGS. 5-7, the array substrate has a display area AA and a peripheral area NA surrounding the display area AA. The display area AA has a plurality of sub-pixels P arranged in multiple rows and multiple columns. The array substrate includes a substrate 111, a plurality of first signal lines 101 and a plurality of second signal lines 102.

[0062] As shown in FIGS. 5-7, a plurality of first signal lines 101 are disposed on the substrate 111, for example, on the first metal layer M1, at least part of the plurality of first signal lines 101 extend along the first direction R1, for example, at least part of each first signal line 101 extend along the first direction R1. At least one first signal line 101 is electrically connected to two adjacent rows of sub-pixels P to provide the same first signal to the two adjacent rows of sub-pixels P. For example, in some embodiments, most or all of the plurality of first signal lines 101 are electrically connected to two adjacent rows of sub-pixels P to provide the same first signal to the two adjacent rows of sub-pixels P.

[0063] As shown in FIGS. 5-7, a plurality of second signal lines 102 are disposed on the substrate 111, for example, on the second metal layer M2, the second metal layer M2 is on the side of the first metal layer M1 away from the substrate 111, that is, the plurality of second signal lines 102 are disposed on the side of the plurality of first signal lines 101 away from the substrate 111. For example, at least part of the plurality of second signal lines 102 extend along the second direction R2, for example, at least part of each second signal line 102 extend along the second direction R2, the second direction R2 is different from the first direction R1.

[0064] For example, in some examples, the second direction R2 is perpendicular to the first direction R1.

[0065] As shown in FIG. 6, the two adjacent rows of sub-pixels P include a first sub-pixel P1 and a second sub-pixel P2 in the same column, the plurality of second signal lines 102 include a first sub-signal line 1021 and a second sub-signal line 1022, the first sub-signal line 1021 is electrically connected to the first sub-pixel P, and the second sub-signal line 1022 is electrically connected to the second sub-pixel P, so that the first sub-pixel P can receive the second signal provided by the first sub-signal line 1021, and the second sub-pixel P can receive the second signal provided by the second sub-signal line 1022.

[0066] Thus, since the two adjacent rows of sub-pixels P obtain the first signal by using the same first signal line, the number of first signal lines 101 in the peripheral area NA is reduced, and by connecting the first sub-pixel and the second sub-pixel in the same column receiving the same first signal by using different second signal lines, the sub-pixels receiving the same first signal receive different second signals, and thus the first sub-pixel and the second sub-pixel can also be displayed independently. Thus, the number of first signal lines 101 in the peripheral area NA is reduced, a narrow frame can be achieved, and the circuit design and manufacturing of the array substrate are simpler, and the preparation cost of the array substrate can be reduced.

[0067] For example, in the case that each first signal line 101 is electrically connected to two adjacent rows of sub-pixels P, for a display with a resolution of N*M (M and N are both positive integers), the number of first signal lines 101 on one side (for example, the left side or the right side) of the display area AA is N / 4, assuming that the pitch of each first signal line 101 (that is, the sum of the width of one first signal line 101 and the spacing between adjacent first signal lines 101) is P, then the calculation formula of the width X required by the peripheral area NA on one side (for example, the left side or the right side) of the display area AA is: X=P*(N / 4)+K,

[0068] wherein K is the width required by other designs except the first signal line 101. It can be seen that through the above design of the embodiments of the present disclosure, the width X of the peripheral area NA can be greatly reduced, so as to facilitate the realization of narrow frame.

[0069] For example, for a medium-sized product of 12 inches, the resolution is 960*640 (that is, the case that N is 960 and M is 640), and the pitch of the first signal line 101 is designed to be 15 μm. At this time, for a conventional array substrate, the width required by the first signal line 101 in the peripheral area NA is at least 7.2 mm, and if the above design of the embodiments of the present disclosure is adopted, the width required by the first signal line 101 in the peripheral area NA can be reduced to 3.6 mm, realizing a 50% reduction in the side frame. The reduced frame can on the one hand increase the utilization rate of the array substrate on the substrate when a plurality of array substrates are made on a large substrate, and on the other hand can reduce the manufacturing cost of the array substrate; for example, for a larger and higher resolution product, when more or larger integrated circuits 100 are required, the above design of the embodiments of the present disclosure can also save the cost of the integrated circuit 100.

[0070] For example, in some embodiments, as shown in FIG. 7, the first sub-signal line 1021 and the second sub-signal line 1022 are respectively located on the opposite sides of the column where the first sub-pixel P1 and the second sub-pixel P2 are located. For example, there are two second signal lines 102 between two adjacent columns of sub-pixels P, that is, the first sub-signal line 1021 and the second sub-signal line 1022. Thus, each sub-pixel corresponds to one first signal line 101 and two second signal lines 102.

[0071] For example, in some embodiments, as shown in FIG. 7, the first sub-pixel P1 includes the first transistor T1 and the first pixel electrode 115A electrically connected with the first transistor T1, and the second sub-pixel P2 includes the second transistor T2 and the second pixel electrode 115B electrically connected with the second transistor T2. For example, the first pixel electrode 115A and the second pixel electrode 115B are arranged on the pixel electrode layer 115, which is on the side of the second metal layer M2 away from the substrate 111, that is, the first pixel electrode 115A and the second pixel electrode 115B are arranged on the side of the plurality of second signal lines 102 away from the substrate 111.

[0072] For example, as shown in FIG. 6, in the second direction R2, the first transistor T1 and the second transistor T2 are arranged in a staggered manner, that is, in the second direction R2, the transistors of adjacent sub-pixels are not arranged in alignment.

[0073] For example, in the same column of sub-pixels, the transistors of the sub-pixels in the odd rows are arranged in alignment in the second direction R2, the transistors of the sub-pixels in the even rows are arranged in alignment in the second direction R2, and the transistors of the sub-pixels in the odd rows are arranged in a staggered manner with the transistors of the sub-pixels in the even rows in the second direction R2.

[0074] For example, as shown in FIG. 6, in the first sub-pixel P1, the first transistor T1 is arranged on the side of the first pixel electrode 115A close to the first sub-signal line 1021, which is shown as the left side in the figure, and in the second sub-pixel P2, the second transistor T2 is arranged on the side of the second pixel electrode 115B close to the second sub-signal line 1022, which is shown as the right side in the figure, thereby facilitating the electrical connection of the first transistor T1 and the second transistor T2 with the first sub-signal line 1021 and the second sub-signal line 1022, respectively, to obtain the corresponding second signals.

[0075] For example, in some embodiments, as shown in FIGS. 5 and 6, the first direction R1 is the row direction of the plurality of sub-pixels P, the first signal line 101 is a scan line configured to provide a scan signal, that is, the first signal is a scan signal; the second direction R2 is the column direction of the plurality of sub-pixels P, and the second signal line 102 is a data line configured to provide a data signal, that is, the second signal is a data signal. For example, in another embodiment, the first direction R1 and the second direction R2 can be interchanged, that is, the first direction R1 is the column direction of the plurality of sub-pixels P, and the second direction R2 is the row direction of the plurality of sub-pixels P; in another embodiment, the first signal line 101 and the second signal line 102 can also be interchanged, for example, the first signal line 101 is a data line configured to provide a data signal, and the second signal line 102 is a scan line configured to provide a scan signal. The embodiments of the present disclosure do not make specific limitations on this.

[0076] For example, in some embodiments, as shown in FIGS. 5 and 6, at least one first signal line 101 (for example, each first signal line 101) includes a first lead line 1010 located at the peripheral area NA, one end of which is electrically connected to the integrated circuit 100, and a first branch line 1011 and a second branch line 1012 electrically connected to the first lead line 1010, the first branch line 1011 and the second branch line 1012 extending from the first lead line 1010 to the display area AA and extending along the first direction R1, two adjacent rows of sub-pixels P including a first row of sub-pixels RW1 and a second row of sub-pixels RW2, the first row of sub-pixels RW1 including a first sub-pixel P1, and the second row of sub-pixels RW2 including a second sub-pixel P2, the first branch line 1011 being electrically connected to the first row of sub-pixels RW1, and the second branch line 1012 being electrically connected to the second row of sub-pixels RW2.

[0077] For example, as shown in FIG. 5, at least part of the first lead line 1010 extends along the second direction R2 and extends to the integrated circuit 100 to obtain a corresponding scanning signal from the integrated circuit 100.

[0078] For example, as shown in FIGS. 5 and 6, the first branch line 1011 is arranged between the first row of sub-pixels RW1 and the second row of sub-pixels RW2, the second branch line 1012 is arranged on a side of the second row of sub-pixels RW2 away from the first row of sub-pixels RW1, the first transistor T1 is arranged on a side of the first pixel electrode 115A close to the first branch line 1011, and the second transistor T2 is arranged on a side of the second pixel electrode 115B close to the second branch line 1012. At this time, the first transistor T1 is arranged at one corner position of the first pixel electrode 115A, and the second transistor T2 is arranged at one corner position of the second pixel electrode 115B. For example, in the embodiments of FIGS. 3 and 4, the first transistor T1 is arranged at the lower left corner position of the first pixel electrode 115A, and the second transistor T2 is arranged at the lower right corner position of the second pixel electrode 115B.

[0079] For example, FIG. 8A shows a plan view of the first transistor T1, FIG. 8B shows a plan view of the second transistor T2, and FIG. 9 shows a cross-sectional view of the first transistor T1 and the second transistor T2 along the dashed line BB in the drawing. Since the cross-section of the first transistor T1 and the second transistor T2 along the dashed line BB in the drawing is substantially the same, both are shown and described by using FIG. 9.

[0080] For example, as shown in FIG. 8A, the first transistor T1 includes a first gate G1 electrically connected with the first branch line 1011, a first electrode S1 electrically connected with the first sub-signal line 1021, and a second electrode D1 spaced from the first electrode S1. In this way, the first transistor T1 receives the first signal through the first gate G1 and receives the second signal through the first electrode S1. For example, the first electrode S1 can serve as the source of the first transistor T1, and the second electrode D1 can serve as the drain of the first transistor T1, or, in other embodiments, the first electrode S1 can serve as the drain of the first transistor T1, and the second electrode D1 can serve as the source of the first transistor T1, and embodiments of the present disclosure do not make specific limitations in this regard.

[0081] For example, as shown in FIG. 8B, the second transistor T2 includes a second gate G2 electrically connected with the second branch line 1012, a third electrode S2 electrically connected with the second sub-signal line 1022, and a fourth electrode D2 spaced from the third electrode S2. In this way, the second transistor T2 receives the first signal through the second gate G2 and receives the second signal through the third electrode S2. For example, the third electrode S2 can serve as the source of the second transistor T2, and the fourth electrode D2 can serve as the drain of the second transistor T2, or, in other embodiments, the third electrode S2 can serve as the drain of the second transistor T1, and the fourth electrode D2 can serve as the source of the second transistor T2, and embodiments of the present disclosure do not make specific limitations in this regard.

[0082] For example, as shown in FIG. 8A and FIG. 8B, the first gate G1 and the second gate G2 extend along the second direction R2, that is, the length direction of the first gate G1 and the second gate G2 is the second direction R2, the first electrode S1 and the second electrode D1 are disposed on the same side of the first branch line 1011, which is shown as the upper side in the figure, and the third electrode S2 and the fourth electrode D2 are disposed on the same side of the second branch line 1012, which is shown as the upper side in the figure.

[0083] For example, in some embodiments, as shown in FIG. 8A and FIG. 9, the first gate G1 and the first branch line 1011 are disposed in the same layer and integrally connected, and the first gate G1 can be regarded as a portion protruding from the first branch line 1011, at this time, the extension direction of the first gate G1 is perpendicular to the extension direction of the first branch line 1011. For example, the first gate G1 and the first branch line 1011 are disposed in the first metal layer M1. As shown in FIG. 8B and FIG. 9, the second gate G2 and the second branch line 1012 are disposed in the same layer and integrally connected, and the second gate G2 can be regarded as a portion protruding from the second branch line 1012, at this time, the extension direction of the second gate G2 is perpendicular to the extension direction of the second branch line 1012. For example, the second gate G2 and the second branch line 1012 are also disposed in the first metal layer M1.

[0084] For example, in some examples, the first metal layer M1 can adopt a metal material such as copper, aluminum, titanium, cobalt, nickel, or an alloy material thereof, and can be formed into a single-layer structure or a multi-layer structure, for example, a molybdenum / aluminum double-layer structure, a titanium / aluminum / titanium triple-layer structure, or the like.

[0085] It should be noted that, in the embodiments of the present disclosure, the two (or more) functional layers or structural layers are formed in the same layer and with the same material in the layer structure of the display substrate, that is, in the preparation process, the two functional layers or structural layers can be formed from the same material layer, and the required patterns and structures can be formed through the same patterning process.

[0086] For example, in some embodiments, as shown in FIGS. 6 and 9, the first electrode S1 is arranged in the same layer as the first sub-signal line 1021 and integrally connected, and the first electrode S1 can be regarded as a portion protruding from the first sub-signal line 1021, for example, the extension direction of the first electrode S1 is perpendicular to the extension direction of the first sub-signal line 1021. For example, the first electrode S1 and the first sub-signal line 1021 are arranged in the second metal layer M2, and the second electrode D1 is also arranged in the second metal layer M2. The third electrode S2 is arranged in the same layer as the second sub-signal line 1022 and integrally connected, and the third electrode S2 can be regarded as a portion protruding from the second sub-signal line 1022, for example, the extension direction of the third electrode S2 is perpendicular to the extension direction of the second sub-signal line 1022. For example, the third electrode S2 and the second sub-signal line 1022 are arranged in the second metal layer M2, and the fourth electrode D2 is also arranged in the second metal layer M2.

[0087] For example, in some examples, the second metal layer M2 can adopt a metal material such as copper, aluminum, titanium, cobalt, nickel, or an alloy material thereof, and can be formed into a single-layer structure or a multi-layer structure, for example, a molybdenum / aluminum double-layer structure, a titanium / aluminum / titanium triple-layer structure, or the like.

[0088] For example, in some embodiments, as shown in FIGS. 7 and 9, the array substrate can further include a first insulating layer 112 arranged on the side of the first metal layer M1 away from the substrate 111, and the first insulating layer 112 can adopt an inorganic insulating material such as silicon oxide, silicon nitride, or silicon oxynitride, for example. For example, the array substrate can further include a semiconductor material layer 113 arranged on the side of the first insulating layer 112 away from the substrate 111, and the semiconductor material layer 113 is used to form an active layer of each transistor, and can adopt a semiconductor material such as amorphous silicon, polycrystalline silicon, or metal oxide (such as IGZO), for example.

[0089] For example, in some embodiments, as shown in FIG. 7, the array substrate can further include a second insulating layer 114 disposed on the side of the second metal layer M2 away from the substrate 111, which can be made of inorganic insulating materials such as silicon oxide, silicon nitride, or silicon oxynitride, or organic insulating materials such as polyimide or resin. For example, a pixel electrode layer 115 is disposed on the side of the second insulating layer 114 away from the substrate 111, which includes pixel electrodes for multiple sub-pixels, and can be made of transparent conductive materials such as transparent metal oxides such as ITO, IZO, and the like.

[0090] For example, in some embodiments, the substrate 111 can be made of rigid substrates such as glass, quartz, or flexible substrates such as polyimide, and the embodiments of the present disclosure do not make specific limitations on the materials of the various structures in the array substrate.

[0091] For example, in some embodiments, the first transistor T1 and the second transistor T2 can be double-gate transistors, so that the first transistor T1 and the second transistor T2 have lower off-state current Ioff. off At this time, as shown in FIG. 8A, the first transistor T1 can further include a third gate G3 and a fifth electrode S3 and a sixth electrode D3, the fifth electrode S3 is integrally connected with the second electrode D1, and the sixth electrode D3 is electrically connected with the first pixel electrode 115A; the second transistor T2 can further include a fourth gate G4 and a seventh electrode S4 and an eighth electrode D4, the seventh electrode S4 is integrally connected with the fourth electrode D2, and the eighth electrode D4 is electrically connected with the second pixel electrode 115B.

[0092] For example, in the embodiments of FIGS. 8A, 8B, and 9, the first metal layer M1 and the second metal layer M2 are in a design state, at this time, as shown in FIG. 6, the first transistor T1 of the first sub-pixel P1 is located on the left side of the first pixel electrode 115A, and the second transistor T2 of the second sub-pixel P2 is located on the right side of the second pixel electrode 115B, therefore, the electrodes of the first transistor T1 and the second transistor T2 in the connected state or the same function are basically in a symmetrical state, for example, the sixth electrode D3 of the first transistor T1 electrically connected with the first pixel electrode 115A is located on the right side of the first transistor, and the eighth electrode D4 of the second transistor T2 electrically connected with the second pixel electrode 115B is located on the left side of the second transistor, since the overlapping area (gate-source capacitance Cgs) of the sixth electrode D3 and the third gate G3 is consistent with the overlapping area (gate-source capacitance Cgs) of the eighth electrode D4 and the fourth gate G4, and the overlapping area (gate-source capacitance Cgs) of other electrodes of the electrodes in the connected state or the same function and the gate is also consistent, therefore, the gate-source capacitance Cgs of the first transistor T1 and the second transistor T2 is consistent, and the functional state is also consistent, and the first sub-pixel P1 and the second sub-pixel P2 can display normally.

[0093] However, in the preparation process of the array substrate, due to process errors, such as alignment errors, etc., the various film layers in the array substrate can be offset, such as the first metal layer M1 and the second metal layer M2 being offset, at this time, as shown in FIGS. 10A and 10B, when the first metal layer M1 and the second metal layer M2 are offset, the gate-source capacitance Cgs formed by the electrodes and the gate in the same connection state or the same function in the first transistor T1 of the first sub-pixel P1 and the second transistor T2 of the second sub-pixel P2 can have a large difference, thereby causing display abnormalities of the first sub-pixel P1 and the second sub-pixel P2.

[0094] For example, FIG. 11A shows a cross-sectional schematic view of the first transistor T1 after being offset (for example, the second metal layer is offset to the left relative to the first metal layer), and FIG. 11B shows a cross-sectional schematic view of the second transistor T2 after being offset, as shown in FIGS. 11A and 11B, the overlapping area (gate-source capacitance Cgs) of the sixth electrode D3 of the first transistor T1 and the third gate G3 is greater than the overlapping area (gate-source capacitance Cgs) of the eighth electrode D4 of the second transistor T2 and the fourth gate G4, thereby possibly causing the above-mentioned gate-source capacitance Cgs of the first transistor T1 and the second transistor T2 to be inconsistent, causing display abnormalities of the first sub-pixel P1 and the second sub-pixel P2.

[0095] In this regard, in some embodiments, the first transistor T1 and the second transistor T2 can also adopt other layouts to weaken or avoid such display abnormalities caused by preparation process deviations.

[0096] For example, FIG. 12 shows a circuit connection diagram of a sub-pixel in another array substrate provided by at least one embodiment of the present disclosure, and FIG. 13A shows a planar schematic view of the first transistor T1 in the array substrate, and FIG. 13B shows a planar schematic view of the second transistor T2 in the array substrate.

[0097] In combination with FIGS. 12, 13A and 13B, the first transistor T1 includes a first gate G1 electrically connected with the first branch line 1011, a first electrode S1 electrically connected with the first sub-signal line 1021, and a second electrode D1 spaced apart from the first electrode S1. The second transistor T2 includes a second gate G2 electrically connected with the second branch line 1012, a third electrode S2 electrically connected with the second sub-signal line 1022, and a fourth electrode D2 spaced apart from the third electrode S2. For example, the first gate G1 and the second gate G2 extend along the first direction R1, that is, the same as the extending direction of the first branch line 1011 and the second branch line 1012, the first electrode S1 and the second electrode D1 are respectively arranged on the opposite sides of the first branch line 1011, and the third electrode S2 and the fourth electrode D2 are respectively arranged on the opposite sides of the second branch line 1012 in the second direction R2.

[0098] For example, the first gate G1 can be regarded as a portion protruding from the first branch line 1011, and the first gate G1 extending along the first direction R1 means that the length direction of the first gate G1 is the first direction R1 in the figure; similarly, the second gate G2 can be regarded as a portion protruding from the second branch line 1012, and the second gate G2 extending along the first direction R1 means that the length direction of the second gate G2 is the first direction R1 in the figure.

[0099] For example, in some embodiments, the first transistor T1 and the second transistor T2 can be double-gate transistors, and the first transistor T1 can further include a third gate G3, a fifth electrode S3 and a sixth electrode D3, the fifth electrode S3 is integrally connected with the second electrode D1, and the sixth electrode D3 is electrically connected with the first pixel electrode 115A; the second transistor T2 can further include a fourth gate G4, a seventh electrode S4 and an eighth electrode D4, the seventh electrode S4 is integrally connected with the fourth electrode D2, and the eighth electrode D4 is electrically connected with the second pixel electrode 115B.

[0100] For example, FIGS. 14A and 14B show the planar schematic diagrams of the first transistor and the second transistor in FIGS. 13A and 13B when the first metal layer and the second metal layer are offset, as shown in FIGS. 14A and 14B, the second metal layer is offset to the left relative to the first metal layer, and at this time, the overlapping area (gate-source capacitance Cgs) of the sixth electrode D3 of the first transistor T1 and the first gate G1 is not much different from the overlapping area (gate-source capacitance Cgs) of the eighth electrode D4 of the second transistor T2 and the second gate G2, or in other words, even if the overlapping area (gate-source capacitance Cgs) of the sixth electrode D3 of the first transistor T1 and the first gate G1 is slightly larger than the overlapping area (gate-source capacitance Cgs) of the eighth electrode D4 of the second transistor T2 and the second gate G2, the difference is much smaller than the case in FIGS. 11A and 11B, and basically will not affect the display of the sub-pixel. Therefore, through the above setting of the structure of the first transistor and the second transistor, the display abnormality caused by the preparation process deviation can be reduced or eliminated.

[0101] For example, FIG. 15 shows a circuit connection diagram of another array substrate provided in at least one embodiment of the present disclosure, and FIG. 16 shows a circuit connection diagram of part of the sub-pixels in the above array substrate, as shown in FIGS. 15 and 16, at least one first signal line 101 (for example, each first signal line 101) includes a first lead line 1010 and a first signal main line 1013 electrically connected with the first lead line 1010, the first signal main line 1013 extends along the first direction R1 and connects two adjacent rows of sub-pixels P.

[0102] For example, the first lead line 1010 is provided in the peripheral region NA, extends at least partially in the second direction R2, and extends to the integrated circuit 100 to acquire a corresponding scan signal from the integrated circuit 100. The first signal main line 1013 extends from the first lead line 1010 to the display region AA, and is provided between two adjacent rows of the sub-pixels P to connect the two adjacent rows of the sub-pixels P. The first sub-pixel P1 includes the first transistor T1 and the first pixel electrode 115A electrically connected to the first transistor T1, and the second sub-pixel P2 includes the second transistor T2 and the second pixel electrode 115B electrically connected to the second transistor T2, and the first transistor T1 and the second transistor T2 are provided between the first pixel electrode 115A and the second pixel electrode 115B.

[0103] That is, in the embodiment of FIGS. 15 and 16, the first transistor T1 is provided on the side of the first pixel electrode 115A close to the second pixel electrode 115B, and the second transistor T2 is provided on the side of the second pixel electrode 115B close to the first pixel electrode 115A, so that the transistors of the two adjacent rows of the sub-pixels P are arranged between the two adjacent rows of the sub-pixels P and in a row, and the side of the second pixel electrode 115B away from the first pixel electrode 115A no longer has a transistor.

[0104] For example, FIG. 17A shows a plan view of the first transistor T1 in the above embodiment, and FIG. 17B shows a plan view of the second transistor T2 in the above embodiment. As shown in FIG. 17A, the first transistor T1 includes a first gate G1 electrically connected to the first signal main line 1013, a first electrode S1 electrically connected to the first sub-signal line 1021, and a second electrode D1 spaced apart from the first electrode S1. As shown in FIG. 17B, the second transistor T2 includes a second gate G2 electrically connected to the first signal main line 1013, a third electrode S2 electrically connected to the second sub-signal line 1022, and a fourth electrode D2 spaced apart from the third electrode S2.

[0105] For example, in the second direction R2, the first electrode S1 and the second electrode D1 are provided on opposite sides of the first signal main line 1013, and the third electrode S2 and the fourth electrode D2 are provided on opposite sides of the first signal main line 1013.

[0106] For example, in some embodiments, the first transistor T1 and the second transistor T2 can be double-gate transistors, and the first transistor T1 can further include a third gate G3 and a fifth electrode S3 and a sixth electrode D3, the fifth electrode S3 is integrally connected with the second electrode D1, and the sixth electrode D3 is electrically connected with the first pixel electrode 115A; and the second transistor T2 can further include a fourth gate G4 and a seventh electrode S4 and an eighth electrode D4, the seventh electrode S4 is integrally connected with the fourth electrode D2, and the eighth electrode D4 is electrically connected with the second pixel electrode 115B. At this time, the sixth electrode D3 in the first transistor T1 for electrical connection with the first pixel electrode 115A and the eighth electrode D4 in the second transistor T2 for electrical connection with the second pixel electrode 115B are located on opposite sides of the first signal main line 1013.

[0107] For example, in the first transistor T1 and the second transistor T2, each gate can be regarded as a portion protruding from the first signal main line 1013, and the length direction thereof is substantially along the first direction R1.

[0108] Similarly, in the embodiments of FIGS. 15 and 16, if the first metal layer and the second metal layer are offset due to a preparation process or the like, for example, the second metal layer is offset to the left relative to the first metal layer, even if the overlapping area (gate-source capacitance Cgs) of the sixth electrode D3 of the first transistor T1 and the first gate G1 is slightly larger than the overlapping area (gate-source capacitance Cgs) of the eighth electrode D4 of the second transistor T2 and the second gate G2, the difference is much smaller than in the case of FIGS. 11A and 11B, and basically does not affect the display of the sub-pixel, so the embodiments of FIGS. 15 and 16 can also achieve the technical effect of reducing or eliminating display abnormalities caused by preparation process deviations.

[0109] For example, the array substrate provided by the embodiments of the present disclosure can be applied in products such as electronic price tags, electronic table cards, electronic door plates, billboards, electronic paper readers, etc.

[0110] At least one embodiment of the present disclosure further provides a display device, which includes the array substrate provided by the embodiments of the present disclosure.

[0111] For example, the display device can further include an opposite substrate opposite to the array substrate and a display layer between the opposite substrate and the array substrate. In one example, the display layer can be an electronic ink layer, so that the display device can be an electronic paper display, for example, implemented as an electronic price tag, an electronic table card, an electronic door plate, a billboard, an electronic paper reader, etc.

[0112] For example, FIG. 18 shows a cross-sectional schematic view of a display device provided by at least one embodiment of the present disclosure, as shown in FIG. 18, the display device includes an array substrate 201, a counter substrate 205, and a display layer 202 between the array substrate 201 and the counter substrate 205, which are provided by embodiments of the present disclosure. For example, the array substrate 201 can be electrically connected to the display layer 202 through a silver paste hole 203, and the display layer 202 can be an electronic ink layer in various forms.

[0113] For example, the counter substrate 205 is provided with a counter electrode 204, for example, an indium zinc oxide (ITO) electrode, and the counter substrate 205 can be a PET substrate, for example. The counter electrode 204 is bonded to a protective film 207 through a bonding adhesive 206, and the side surfaces of the array substrate 201 and the counter substrate 205 are sealed by an encapsulating adhesive 208.

[0114] The following points also need to be explained:

[0115] (1) The drawings of the embodiments of the present disclosure only relate to the structures involved in the embodiments of the present disclosure, and other structures can be referred to the general design.

[0116] (2) For the sake of clarity, in the drawings used to describe the embodiments of the present disclosure, the thickness of a layer or region is exaggerated or reduced, that is, these drawings are not drawn according to the actual proportion. It can be understood that when an element such as a layer, film, region or substrate is referred to as being located "on" or "under" another element, it can be "directly" located on or under another element or there can be an intermediate element.

[0117] (3) In the case of no conflict, the embodiments of the present disclosure and the features in the embodiments can be combined with each other to obtain new embodiments.

[0118] The above is only a specific embodiment of the present disclosure, but the protection scope of the present disclosure is not limited thereto, and the protection scope of the present disclosure should be subject to the protection scope of the claims.

Claims

1. An array substrate of an electronic paper device, having a plurality of sub-pixels arranged in a plurality of rows and a plurality of columns, and comprising: a substrate, a plurality of first signal lines disposed on the substrate and extending at least partially in a first direction, wherein at least one of the plurality of first signal lines is electrically connected to two adjacent rows of sub-pixels, and a plurality of second signal lines disposed on the substrate and extending at least partially in a second direction different from the first direction, wherein the two adjacent rows of sub-pixels comprise a first sub-pixel and a second sub-pixel in the same column, the plurality of second signal lines comprise a first sub-signal line and a second sub-signal line, the first sub-signal line is electrically connected to the first sub-pixel, and the second sub-signal line is electrically connected to the second sub-pixel. The first sub-signal line and the second sub-signal line are respectively located on opposite sides of the column in which the first sub-pixel and the second sub-pixel are located. There are two second signal lines between two adjacent columns of sub-pixels. The first signal line is a scan line configured to provide a scan signal. The second signal line is a data line configured to provide a data signal.

2. The array substrate according to claim 1, wherein, The at least one first signal line comprises a first lead line and a first branch line and a second branch line electrically connected to the first lead line, the first branch line and the second branch line extend in the first direction.

3. The array substrate according to claim 1 or 2, wherein, The two adjacent rows of sub-pixels comprise a first row of sub-pixels and a second row of sub-pixels.

4. The array substrate according to any one of claims 1 to 3, wherein, The first branch line is electrically connected to the first row of sub-pixels, and the second branch line is electrically connected to the second row of sub-pixels. At least part of the first lead line extends in the second direction.

5. The array substrate according to any one of claims 1 to 4, wherein, The first row of sub-pixels comprises the first sub-pixel, and the second row of sub-pixels comprises the second sub-pixel. The first branch line is disposed between the first row of sub-pixels and the second row of sub-pixels, and the second branch line is disposed on a side of the second row of sub-pixels away from the first row of sub-pixels. The first sub-pixel comprises a first transistor and a first pixel electrode electrically connected to the first transistor, and the second sub-pixel comprises a second transistor and a second pixel electrode electrically connected to the second transistor.

6. The array substrate according to claim 5, wherein, The first transistor is disposed on a side of the first pixel electrode close to the first branch line, and the second transistor is disposed on a side of the second pixel electrode close to the second branch line.

7. The array substrate according to claim 5 or 6, wherein, In the second direction, the first transistor and the second transistor are arranged in a staggered manner. The first transistor comprises a first gate electrically connected to the first branch line, a first electrode electrically connected to the first sub-signal line, and a second electrode spaced apart from the first electrode. The second transistor comprises a second gate electrically connected to the second branch line, a third electrode electrically connected to the second sub-signal line, and a fourth electrode spaced apart from the third electrode. The first gate and the second gate extend in the second direction, the first electrode and the second electrode are disposed on the same side of the first branch line, and the third electrode and the fourth electrode are disposed on the same side of the second branch line.

8. The array substrate according to claim 7, wherein, The first gate and the first branch line are disposed in the same layer and integrally connected.

9. The array substrate according to claim 7 or 8, wherein, ​ ​ ​ 10. The array substrate of claim 9, wherein, ​ The second gate is arranged in the same layer as the second branch line and is integrally connected.

11. The array substrate according to claim 9 or 10, wherein, The first electrode is arranged in the same layer as the first sub-signal line and is integrally connected, The third electrode is arranged in the same layer as the second sub-signal line and is integrally connected.

12. The array substrate of claim 5, wherein, The first row of sub-pixels includes the first sub-pixel, and the second row of sub-pixels includes the second sub-pixel, The first transistor includes a first gate electrically connected to the first branch line, a first electrode electrically connected to the first sub-signal line, and a second electrode spaced from the first electrode, The second transistor includes a second gate electrically connected to the second branch line, a third electrode electrically connected to the second sub-signal line, and a fourth electrode spaced from the third electrode, The first gate and the second gate extend along the first direction, and the first electrode and the second electrode are respectively arranged on opposite sides of the first branch line, and the third electrode and the fourth electrode are respectively arranged on opposite sides of the second branch line in the second direction.

13. The array substrate according to any one of claims 1-3, wherein, The at least one first signal line includes a first lead line and a first signal main line electrically connected to the first lead line, the first signal main line extending along the first direction and connecting the adjacent two rows of sub-pixels.

14. The array substrate of claim 13, wherein, The first signal main line is arranged between the adjacent two rows of sub-pixels, The first sub-pixel includes a first transistor and a first pixel electrode electrically connected to the first transistor, and the second sub-pixel includes a second transistor and a second pixel electrode electrically connected to the second transistor, The first transistor and the second transistor are arranged between the first pixel electrode and the second pixel electrode.

15. The array substrate of claim 14, wherein, At least part of the first lead line extends along the second direction.

16. The array substrate according to claim 7 or 14, wherein, The plurality of second signal lines are arranged on a side of the plurality of first signal lines away from the substrate substrate; The first pixel electrode and the second pixel electrode are arranged on a side of the plurality of second signal lines away from the substrate substrate.

17. A display device comprising the array substrate of any one of claims 1-16.

Images