Phase change memory control method and apparatus, storage system, and electronic device

Abstract

Embodiments of the present application relates to the technical field of storage. Disclosed are a phase change memory control method and apparatus, a storage system, and an electronic device. The method comprises: receiving a first write instruction for a target phase change memory cell; determining that the target phase change memory cell does not satisfy a complete crystallization condition, and controlling a read / write circuit to apply a first electrical pulse to the target phase change memory cell, the first electrical pulse being used for performing a set operation on a phase change memory cell in a target phase change memory; receiving a second write instruction for the target phase change memory cell; and determining that the target phase change memory cell satisfies the complete crystallization condition, and controlling the read / write circuit to apply a second electrical pulse to the target phase change memory cell, the second electrical pulse being used for performing a set operation on the target phase change memory cell, the pulse width of the second electrical pulse being greater than the pulse width of the first electrical pulse, and / or the amplitude of the second electrical pulse being greater than the amplitude of the first electrical pulse. By using the present application, the service life of the phase change memory can be prolonged.

Description

Control method, device, storage system and electronic equipment of phase change memory

[0001] The present application claims priority from the Chinese patent application No. 202410740845.8, filed on June 7, 2024, and entitled "Control method, device, storage system and electronic equipment of phase change memory", the content of which is incorporated herein by reference in its entirety. TECHNICAL FIELD

[0002] The present application relates to the technical field of storage, in particular to a control method, device, storage system and electronic equipment of phase change memory. BACKGROUND

[0003] Among numerous new types of memories, phase change memory (PCM) is considered as a solution for next-generation non-volatile memory due to its high density and fast operation speed, and is used in persistent memory (PM), storage class memory (SCM), solid-state drive (SSD), embedded storage, etc.

[0004] Phase change memory usually uses a large amplitude and a short pulse for reset operation (writing data 0) to make the phase change material in the phase change memory cell amorphous, and the memory cell presents high resistance; uses a small amplitude and a long pulse for set operation (writing data 1) to make the phase change material in the phase change memory cell crystallize, and the phase change memory cell presents low resistance. In order to improve the writing speed, the pulse width and amplitude of the set operation are usually set to be very small.

[0005] However, experiments show that under the set operation of short pulse width and small amplitude, the crystallization degree of the phase change material in the phase change memory cell is low, which leads to a low service life of the phase change memory. How to improve the service life of the phase change memory has become a problem to be solved at present. SUMMARY

[0006] The present application provides a control method, device, storage system and electronic equipment of phase change memory, which can improve the service life of the phase change memory, and the corresponding technical solutions are as follows:

[0007] In a first aspect, a control method of a phase change memory is provided, and the method comprises:

[0008] Receiving a first write instruction for a target phase change memory cell in a phase change memory. Determining that the target phase change memory cell does not satisfy a full crystallization condition, and controlling a read-write circuit to apply a first electrical pulse to the target phase change memory cell, wherein the first electrical pulse is used to perform a set operation on the target phase change memory cell. Receiving a second write instruction for the target phase change memory cell. Determining that the target phase change memory cell satisfies the full crystallization condition, and controlling the read-write circuit to apply a second electrical pulse to the target phase change memory cell, wherein the second electrical pulse is used to perform the set operation on the target phase change memory cell, and the second electrical pulse has a pulse width greater than a pulse width of the first electrical pulse, and / or the second electrical pulse has an amplitude greater than an amplitude of the first electrical pulse.

[0009] Currently, in order to improve the write speed, a first electrical pulse with a narrow pulse width and a small amplitude is usually applied to the phase change memory cell to perform a set operation. However, such an electrical pulse makes the crystallization degree of the phase change material in the phase change memory cell lower, which reduces the service life of the phase change memory. Based on this, the technical solution provided in the present application first determines whether the phase change memory cell satisfies a full crystallization condition before performing a set operation on the phase change memory cell. In the case that the phase change memory cell satisfies the full crystallization condition, a second electrical pulse with a wider pulse width and / or a greater amplitude than the first electrical pulse is applied to the phase change memory cell by the read-write circuit to perform a set operation on the phase change memory cell. The second electrical pulse can make the crystallization degree of the phase change memory cell higher, thereby improving the fatigue characteristics of the phase change memory cell and prolonging the service life of the phase change memory.

[0010] In a possible implementation, the method further includes:

[0011] Counting the number of times that each phase change memory cell in the phase change memory performs a set operation. Correspondingly, the process of determining whether the target phase change memory cell satisfies the full crystallization condition can be as follows:

[0012] If it is determined that the counted number of times that the target phase change memory cell performs a set operation does not reach a first threshold value, it is determined that the target phase change memory cell does not satisfy the full crystallization condition. If it is determined that the counted number of times that the target phase change memory cell performs a set operation reaches the first threshold value, it is determined that the target phase change memory cell satisfies the full crystallization condition.

[0013] In the technical solution provided in the present application, the number of times that each phase change memory cell performs a set operation is counted, which makes the full crystallization determination granularity accurate to each phase change memory cell, so that the determination is more accurate and the service life of the phase change memory is more effectively prolonged.

[0014] In a possible implementation, the method further includes:

[0015] The number of times each phase change memory cell is applied with the second electric pulse is counted. In a case where it is determined that the number of times the target phase change memory cell is applied with the second electric pulse reaches a second threshold value, the number of times the counted target phase change memory cell is subjected to the set operation is reset to zero, and the number of times the counted target phase change memory cell is applied with the second electric pulse is reset to zero.

[0016] In the technical solutions provided in the present application, considering that the length of time and the current of the second electric pulse are large, in order to meet the requirement of high-speed reading and writing, after a certain number of second electric pulses are applied, the first electric pulse is continuously applied instead.

[0017] In a possible implementation, the method further includes:

[0018] For each memory region in the phase change memory, the total number of times each phase change memory cell in the memory region is subjected to the set operation is counted. Correspondingly, the process of determining whether the target phase change memory cell meets the complete crystallization condition can be as follows:

[0019] If it is determined that the total number of times all phase change memory cells in the memory region to which the target phase change memory cell belongs are subjected to the set operation does not reach a third threshold value, it is determined that the target phase change memory cell does not meet the complete crystallization condition. If it is determined that the total number of times all phase change memory cells in the memory region to which the target phase change memory cell belongs are subjected to the set operation reaches the third threshold value, it is determined that the target phase change memory cell meets the complete crystallization condition.

[0020] In the technical solutions provided in the present application, the number of times the set operation is performed can also be counted in units of memory regions, to determine whether the phase change memory cell meets the complete crystallization condition. Compared with counting in units of single phase change memory cells, the amount of counting is less, and certain storage resources are saved.

[0021] In a possible implementation, the method further includes:

[0022] For each memory region in the phase change memory, the total number of times all phase change memory cells in the memory region are applied with the second electric pulse is counted. In a case where the total number of times all phase change memory cells in the memory region to which the target phase change memory cell belongs are applied with the second electric pulse reaches a second threshold value, the total number of times each phase change memory cell in the counted target memory region is subjected to the set operation is reset to zero, and the total number of times all phase change memory cells in the memory region to which the target phase change memory cell belongs are applied with the second electric pulse is reset to zero.

[0023] In the technical solutions provided in the present application, considering that the length of time and the current of the second electric pulse are large, in order to meet the requirement of high-speed reading and writing, after a certain number of second electric pulses are applied, the first electric pulse is continuously applied instead.

[0024] In a possible implementation, the method for determining whether the target phase change memory cell satisfies the complete crystallization condition can further include the following steps.

[0025] If it is determined that the data stored in the storage region to which the target phase change memory cell belongs does not reach the fourth threshold, it is determined that the target phase change memory cell does not satisfy the complete crystallization condition. If it is determined that the data stored in the storage region to which the target phase change memory cell belongs reaches the fourth threshold, it is determined that the target phase change memory cell satisfies the complete crystallization condition.

[0026] In a possible implementation, the storage region is one of a storage block, a storage array, a storage row, and a storage column.

[0027] In a second aspect, a control device of a phase change memory is provided, and the device includes:

[0028] a receiving module configured to receive a first write instruction for a target phase change memory cell in the phase change memory;

[0029] a control module configured to determine that the target phase change memory cell does not satisfy a complete crystallization condition, and control a read-write circuit to apply a first electrical pulse to the target phase change memory cell, where the first electrical pulse is used to perform a set operation on the target phase change memory cell.

[0030] the receiving module is configured to receive a second write instruction for the target phase change memory cell;

[0031] the control module is configured to determine that the target phase change memory cell satisfies the complete crystallization condition, and control the read-write circuit to apply a second electrical pulse to the target phase change memory cell, where the second electrical pulse is used to perform a set operation on the target phase change memory cell, the pulse width of the second electrical pulse is greater than the pulse width of the first electrical pulse, and / or the amplitude of the second electrical pulse is greater than the amplitude of the first electrical pulse.

[0032] In a possible implementation, the device further includes a statistics module configured to:

[0033] count a number of times of performing a set operation on each phase change memory cell in the phase change memory;

[0034] the control module is configured to:

[0035] determine that the number of times of performing a set operation on the target phase change memory cell counted does not reach a first threshold;

[0036] determine that the number of times of performing a set operation on the target phase change memory cell counted reaches the first threshold.

[0037] In a possible implementation, the statistics module is further configured to:

[0038] counting a number of times each phase change memory cell in the phase change memory is applied with the second electric pulse;

[0039] in a case where it is determined that the number of times the target phase change memory cell is applied with the second electric pulse reaches a second threshold, zeroing the counted number of times the target phase change memory cell is operated with the set operation and zeroing the counted number of times the target phase change memory cell is applied with the second electric pulse.

[0040] In a possible implementation, the apparatus further includes a counting module configured to:

[0041] counting, for each memory region in the phase change memory, a total number of times each phase change memory cell in the memory region is operated with the set operation;

[0042] the control module is configured to:

[0043] determining that a total number of times all phase change memory cells in a memory region to which the target phase change memory cell belongs are operated with the set operation does not reach a third threshold;

[0044] determining that the total number of times all phase change memory cells in the memory region to which the target phase change memory cell belongs are operated with the set operation reaches the third threshold.

[0045] In a possible implementation, the counting module is further configured to:

[0046] counting, for each memory region in the phase change memory, a total number of times all phase change memory cells in the memory region are applied with the second electric pulse. In a case where the total number of times all phase change memory cells in a memory region to which the target phase change memory cell belongs are applied with the second electric pulse reaches a second threshold, zeroing the counted total number of times each phase change memory cell in the target memory region is operated with the set operation and zeroing the counted total number of times all phase change memory cells in the memory region to which the target phase change memory cell belongs are applied with the second electric pulse.

[0047] In a possible implementation, the control module is configured to:

[0048] determining that data stored in a memory region to which the target phase change memory cell belongs does not reach a fourth threshold;

[0049] determining that the data stored in the memory region to which the target phase change memory cell belongs reaches the fourth threshold.

[0050] In a possible implementation, the memory region is one of a memory block, a memory array, a memory row, and a memory column.

[0051] In a third aspect, a chip is provided, which includes a storage controller and a phase change memory, and the storage controller is configured to perform the control method of the phase change memory as described in the first aspect and any possible implementation of the first aspect.

[0052] In a fourth aspect, a storage system is provided, which includes a storage controller and a phase change memory, and the storage controller is configured to perform the control method of the phase change memory as described in the first aspect and any possible implementation of the first aspect.

[0053] In a fifth aspect, an electronic device is provided, which includes a processor and a storage system as described in the fourth aspect.

[0054] The processor is configured to send a read-write instruction to the storage system, so that the storage system implements a read-write operation.

[0055] In a sixth aspect, a computer readable storage medium is provided, which includes computer program instructions, and when the computer program instructions are executed by a computing device cluster, the computing device cluster performs the control method of the phase change memory as described in the first aspect and any possible implementation of the first aspect.

[0056] In a seventh aspect, a computer program product including instructions is provided, and when the instructions are run by a computing device cluster, the computing device cluster performs the control method of the phase change memory as described in the first aspect and any possible implementation of the first aspect. BRIEF DESCRIPTION OF DRAWINGS

[0057] FIG. 1 is a structural schematic diagram of a storage chip according to an embodiment of the present application;

[0058] FIG. 2 is a structural schematic diagram of a peripheral circuit according to an embodiment of the present application;

[0059] FIG. 3 is a structural schematic diagram of a storage system according to an embodiment of the present application;

[0060] FIG. 4 is a flow schematic diagram of a control method of a phase change memory according to an embodiment of the present application;

[0061] FIG. 5 is a schematic diagram of an operation pulse of a phase change memory cell according to an embodiment of the present application;

[0062] FIG. 6 is a structural schematic diagram of a control device of a phase change memory according to an embodiment of the present application;

[0063] FIG. 7 is a structural schematic diagram of a storage system according to an embodiment of the present application. DETAILED DESCRIPTION

[0064] In order to make the purpose, technical solutions and advantages of the present application clearer, the embodiments of the present application will be further described in detail below with reference to the drawings.

[0065] In order to make the purpose, technical solutions and advantages of the present application clearer, the embodiments of the present application will be further described in detail below with reference to the drawings.

[0066] Resistive memory: using the change of resistance to store or read data, for example, resistive memory can realize the storage of "0" in high resistance state, and can realize the storage of "1" in low resistance state.

[0067] Phase change memory (PCM): a new type of non-volatile semiconductor memory based on chalcogenide compounds, which belongs to a kind of resistive memory, and can realize the storage of "0" and "1" by using the different resistances of the crystalline and amorphous states of the phase change material constituting the phase change memory.

[0068] Write operation: the write operation can also be called set operation, which is a process of medium temperature crystallization, and a long pulse width and medium amplitude electric pulse is applied to the phase change memory cell for heating, so that the temperature of the phase change material in the phase change memory cell rises above the crystallization temperature and below the melting temperature, resulting in crystallization of the phase change material in the phase change memory cell, which presents a low resistance state, that is, realizes the storage of "1".

[0069] Erase operation: the erase operation can also be called reset operation, which is a process of high temperature quenching, and a short pulse width and high amplitude electric pulse is applied to the phase change memory cell, so that the temperature of the phase change material in the phase change memory cell rises above the melting point and then rapidly undergoes annealing, the phase change material enters the amorphous state from the molten state, which presents a high resistance state, that is, realizes the storage of "0".

[0070] Read operation: a low enough current can be applied to both ends of the phase change memory cell, and the read voltage parameter is compared with the standard voltage value, so as to determine the resistance value. If a high voltage is obtained, it means that the phase change material of the phase change memory cell is in a high resistance state, and the data stored in the phase change memory cell is "0"; if a low voltage is obtained, it means that the phase change material of the phase change memory cell is in a low resistance state, and the data stored in the phase change memory cell is "1".

[0071] Word line: a signal line required for selecting a row of phase change memory cells in a storage array, which can complete the selection of a phase change memory cell together with a bit line.

[0072] Bit line: a signal line required for selecting a column in a storage array, which can complete the selection of a phase change memory cell together with a word line. By applying corresponding electric pulses to the word line and the bit line, the write operation, the erase operation or the read operation on the selected phase change memory cell can be realized.

[0073] Figure 1 is a structural schematic diagram of a storage chip according to an embodiment of the present application. As shown in Figure 1, the storage chip 100 includes at least one storage array 110 and a peripheral circuit 120. The at least one storage array 110 constitutes a phase change memory, and the peripheral circuit 120 can also be referred to as a read-write circuit according to its function. The storage array 110 includes a plurality of phase change memory cells arranged in an array. In the plurality of phase change memory cells, the memory cells in the same row are connected to the same word line (WL), and the phase change memory cells in the same column are connected to the same bit line (BL). The storage chip 100 shown in the embodiment of the present application can be a two-dimensional storage chip, i.e., the storage chip includes a single storage array 110, or a three-dimensional storage chip, i.e., the storage chip includes a plurality of storage arrays 110.

[0074] Figure 2 is a schematic diagram of the peripheral circuit 120 according to an embodiment of the present application. As shown in Figure 2, the peripheral circuit 120 includes a control circuit 121, a driving circuit 122, a word line control circuit 123, and a bit line control circuit 124.

[0075] After receiving an operation request corresponding to a read operation, a write operation, or an erase operation, the control circuit 121 can control the driving circuit 122 to apply an operation voltage corresponding to the read operation, the write operation, or the erase operation to one or more memory cells corresponding to the operation request, so as to implement the read operation, the write operation, or the erase operation on the memory cells.

[0076] The driving circuit 122 can select the memory cells corresponding to the operation request by controlling the word line control circuit 123 and the bit line control circuit 124, and then apply the corresponding operation voltage to the selected memory cells.

[0077] The word line control circuit 123 includes a word line switch circuit 1231 and a first sensing circuit 1232, and the bit line control circuit 124 includes a bit line switch circuit 1241 and a second sensing circuit 1242. The word line switch circuit 1231 is connected to each word line in the storage array 110 through a switch tube (not shown in Figure 2). The word line control circuit 123 can turn on the word line connected to the selected memory cell. The bit line switch circuit 1241 is connected to each bit line in the storage array 110 through a switch tube (not shown in Figure 2).

[0078] The word line control circuit 1231 can turn on the switch tube corresponding to the word line connected to a memory cell, and the bit line switch circuit 1241 can turn on the switch tube corresponding to the bit line connected to the memory cell, so as to select the memory cell and apply the corresponding operation voltage to the selected memory cell by the driving circuit 122.

[0079] The first sensing circuit 1232 or the second sensing circuit 1242 can be used to detect the current size of the selected storage unit connected word line or bit line, and then realize the sensing of the storage state corresponding to the storage unit.

[0080] FIG. 3 is a schematic diagram of a storage system provided by an embodiment of the present application. As shown in FIG. 3, the storage system 300 includes a storage controller 200 and one or more storage chips 100 as shown in FIG. 1. The storage controller 200 is a hardware device for controlling the storage chip 100 to perform read / write operations. The storage controller 200 can send an operation request corresponding to a read operation, a write operation or an erase operation to the storage chip 100, so that the peripheral circuit 120 in the storage chip 100 selects the storage unit through the word line and the bit line, and applies a read voltage, a write voltage or an erase voltage to the selected storage unit, thereby realizing the execution of the read operation, the write operation or the erase operation. The storage controller 200 can also receive the read result of the read operation performed by the peripheral circuit 120, and perform verification, error correction and other processing on the read result.

[0081] The read / write principle of the phase change storage unit will be described below:

[0082] When a set operation pulse is applied to the phase change storage unit, the phase change material of the phase change storage unit is a medium temperature crystallization process. A long-time and medium-intensity electric pulse is applied to heat the phase change material, so that the temperature of the phase change material rises above the crystallization temperature and below the melting temperature, resulting in crystallization, i.e. a low resistance state. In this case, the phase change memory writes data "1".

[0083] When a reset operation pulse is applied to the phase change storage unit, the phase change material of the phase change storage unit is a high-temperature quenching process. A short-time and high-intensity electric pulse is applied to the phase change material, so that the temperature of the phase change material rises above the melting point and then rapidly undergoes annealing. The material will change from a molten state to an amorphous state, i.e. a high resistance state. In this case, the phase change memory writes data "0".

[0084] When a read operation pulse is applied, a low enough current is applied across the device to obtain a voltage parameter, which is compared with a standard value to determine the resistance value. If a high voltage is obtained, it is a high resistance state, and it is determined that the stored data is "0"; if a low voltage is obtained, it is a low resistance state, and it is determined that the stored data is "1". Since the current flowing through the phase change region is very small, it is not enough to cause any phase change of the phase change material, and it is a non-destructive read.

[0085] Since the set operation is usually performed by applying a first electrical pulse with a narrow pulse width and a small amplitude on the phase change memory cell to improve the write speed, the phase change material in the phase change memory cell is only partially crystallized by the first electrical pulse, which reduces the service life of the phase change memory. Based on this, the technical scheme provided in the present application is that, before performing the set operation on the phase change memory cell, it is determined whether the phase change memory cell satisfies the complete crystallization condition, and in the case that the phase change memory cell satisfies the complete crystallization condition, a second electrical pulse with a wider pulse width and / or a larger amplitude than the first electrical pulse is applied to the phase change memory cell by the read-write circuit to perform the set operation on the phase change memory cell. The second electrical pulse can make the phase change memory cell crystallize more completely, thereby improving the fatigue characteristics of the phase change memory cell and prolonging the service life of the phase change memory.

[0086] The control method of the phase change memory provided in the embodiments of the present application will be described below with reference to the accompanying drawings. Referring to FIG. 4, the method can be implemented by a storage controller, and the method can include the following steps:

[0087] Step 501: receiving a write instruction for a target phase change memory cell.

[0088] The write instruction is an instruction for writing data "1", which can also be referred to as a set operation instruction, and the target phase change memory cell can be any phase change memory cell in the phase change memory.

[0089] In implementation, when the computing device needs to write data to the phase change memory, the storage controller can be sent a write instruction for a target phase change memory cell by the processor.

[0090] Step 502: determining whether the target phase change memory cell satisfies a complete crystallization condition.

[0091] In implementation, after receiving the write instruction for the target phase change memory cell, the storage controller determines whether the target phase change memory cell satisfies the complete crystallization condition.

[0092] In the embodiments of the present application, various methods for determining whether the target phase change memory cell satisfies the complete crystallization condition are provided, which will be described below by way of example:

[0093] Method one:

[0094] The storage controller respectively counts the number of times of performing the set operation on each phase change memory cell in the phase change memory, and when determining whether the target phase change memory cell satisfies the complete crystallization condition, the storage controller can determine whether the counted number of times of performing the set operation on the target phase change memory cell reaches a first threshold value. The first threshold value can be configured by relevant personnel according to the actual situation of the phase change memory. For example, the first threshold value is 1E4 times, where 1E4 is a scientific notation, which can also be written as 104 .

[0095] If it is determined that the number of times the target phase change memory cell performs the set operation reaches the first threshold, it is determined that the target phase change memory cell meets the complete crystallization condition. If it is determined that the number of times the target phase change memory cell performs the set operation does not reach the first threshold, it is determined that the target phase change memory cell does not meet the complete crystallization condition.

[0096] In one possible implementation, the number of times counted above can also be the number of times each phase change memory cell in the phase change memory performs a regular set operation, i.e., the number of times the first electric pulse is applied. Accordingly, method one can be as follows:

[0097] The storage controller counts the number of times each phase change memory cell in the phase change memory is applied with the first electric pulse respectively. When judging whether the target phase change memory cell meets the complete crystallization condition, the storage controller can judge whether the number of times the target phase change memory cell is applied with the first electric pulse reaches the first threshold.

[0098] If it is determined that the number of times the target phase change memory cell is applied with the first electric pulse reaches the first threshold, it is determined that the target phase change memory cell meets the complete crystallization condition. If it is determined that the number of times the target phase change memory cell is applied with the first electric pulse does not reach the first threshold, it is determined that the target phase change memory cell does not meet the complete crystallization condition.

[0099] Method two:

[0100] For each storage region in the phase change memory, the storage controller can count the total number of times all phase change memory cells in the storage region perform the set operation. When judging whether the target phase change memory cell meets the complete crystallization condition, it can be judged whether the total number of times all phase change memory cells in the storage region to which the target phase change memory cell belongs perform the set operation reaches a second threshold. The second threshold can be configured by relevant personnel according to the actual situation of the storage region division and the phase change memory, for example, the second threshold is 1E5 times. The storage region can be one of a storage block, a storage array, a storage row, and a storage column, wherein the size of the storage block can be divided by relevant personnel according to actual needs, or the existing storage block division method can be reused.

[0101] If it is determined that the total number of times all phase change memory cells in the storage region to which the target phase change memory cell belongs perform the set operation reaches the second threshold, it is determined that the target phase change memory cell meets the complete crystallization condition. If it is determined that the total number of times all phase change memory cells in the storage region to which the target phase change memory cell belongs perform the set operation does not reach the second threshold, it is determined that the target phase change memory cell does not meet the complete crystallization condition.

[0102] In a possible implementation, the number of times counted in the above manner can also be the total number of times that all phase change storage units in each storage area are subjected to the regular set operation, i.e., the total number of times that all phase change storage units in each storage area are subjected to the first electric pulse. Accordingly, the second method can be as follows:

[0103] For each storage area in the phase change memory, the storage controller can count the total number of times that all phase change storage units in the storage area are subjected to the first electric pulse. When determining whether the target phase change storage unit satisfies the complete crystallization condition, it can be determined whether the total number of times that all phase change storage units in the storage area to which the target phase change storage unit belongs are subjected to the first electric pulse reaches a second threshold value.

[0104] If it is determined that the total number of times that all phase change storage units in the storage area to which the target phase change storage unit belongs are subjected to the first electric pulse reaches the second threshold value, it is determined that the target phase change storage unit satisfies the complete crystallization condition. If it is determined that the total number of times that all phase change storage units in the storage area to which the target phase change storage unit belongs are subjected to the first electric pulse does not reach the second threshold value, it is determined that the target phase change storage unit does not satisfy the complete crystallization condition.

[0105] The third method is as follows:

[0106] For each storage area in the phase change memory, the storage controller can count the amount of data stored in the storage area. When determining whether the target phase change storage unit satisfies the complete crystallization condition, it can be determined whether the amount of data stored in the storage area to which the target phase change storage unit belongs reaches a third threshold value. The third threshold value can be configured by relevant personnel according to the actual situation of the phase change memory and the division of the storage area, for example, the third threshold value is 1 GB.

[0107] If it is determined that the amount of data stored in the storage area to which the target phase change storage unit belongs reaches the third threshold value, it is determined that the target phase change storage unit satisfies the complete crystallization condition. If it is determined that the amount of data stored in the storage area to which the target phase change storage unit belongs does not reach the third threshold value, it is determined that the target phase change storage unit does not satisfy the complete crystallization condition.

[0108] In step 503, in a case where it is determined that the target phase change storage unit does not satisfy the complete crystallization condition, the read-write circuit is controlled to apply the first electric pulse to the target phase change storage unit.

[0109] The first electric pulse is used to perform the set operation on the target phase change storage unit in the phase change memory, and the first electric pulse can also be referred to as a high-speed set operation pulse.

[0110] In implementation, the storage controller controls the read-write circuit to apply a first electrical pulse to the target phase change memory cell to perform a set operation on the target phase change memory cell to make the target phase change memory cell store data "1" in the case that it is determined that the target phase change memory cell does not satisfy the complete crystallization condition.

[0111] The high-speed set operation pulse can be a square wave, a trapezoidal wave, a triangular wave, etc. For example, the high-speed set operation pulse can be a square wave, and the pulse width of the high-speed set operation pulse can be 100 nanoseconds (ns). For another example, the high-speed set operation pulse can be a trapezoidal wave, and correspondingly, the high-speed set operation pulse can be divided into two parts, one part has an amplitude of 150 μA, and the other part has an amplitude of 50 μA, the average amplitude is 100 μA, and the pulse width of the two parts is 50 ns. Therefore, the amplitude of the high-speed set operation pulse under this waveform can be considered as the average amplitude 100 μA, and the pulse width can be the sum of the pulse widths of the two parts, i.e. 100 ns. In FIG. 5, an example of a reset operation pulse is also shown. In this example, the reset operation pulse is a square wave, the pulse width is 10 ns, and the amplitude is 800 μA.

[0112] In step 504, the storage controller controls the read-write circuit to apply a second electrical pulse to the target phase change memory cell in the case that it is determined that the target phase change memory cell satisfies the complete crystallization condition.

[0113] The pulse width of the second electrical pulse is greater than the pulse width of the first electrical pulse, and / or the amplitude of the second electrical pulse is greater than the amplitude of the first electrical pulse. The second electrical pulse can also be referred to as a complete crystallization set operation pulse.

[0114] In implementation, the storage controller controls the read-write circuit to apply a second electrical pulse to the target phase change memory cell to perform a set operation on the target phase change memory cell to make the target phase change memory cell store data "1" in the case that it is determined that the target phase change memory cell satisfies the complete crystallization condition.

[0115] Continuing to refer to FIG. 5, compared with the high-speed set operation pulse, the complete crystallization set operation pulse has a longer pulse width and / or a greater amplitude. The pulse width and the amplitude of the complete crystallization set operation pulse can be configured by relevant personnel according to actual needs. For example, the pulse width can be between 700 ns and 900 ns, and the amplitude can be between 260 μA and 400 μA. As shown in FIG. 5, the amplitude of the complete crystallization set operation pulse can be 320 μA, the pulse width can be 800 ns, and the waveform can be a square wave.

[0116] It is worth mentioning that the waveform, pulse width, amplitude of the first electric pulse and the second electric pulse described above or shown in the figures are only examples. In some possible implementations, the first electric pulse can be a square wave, a trapezoidal wave, a triangular wave, etc. Similarly, the second electric pulse can also be a square wave, a trapezoidal wave, a triangular wave, etc. The waveform of the first electric pulse and the second electric pulse can be the same or different. The first electric pulse and the second electric pulse only need to satisfy that the pulse width of the second electric pulse is greater than the pulse width of the first electric pulse, and / or the amplitude of the second electric pulse is greater than the amplitude of the first electric pulse, and the degree of crystallization of the phase change material in the phase change memory cell caused by the second electric pulse is higher than the degree of crystallization of the phase change material in the phase change memory cell caused by the first electric pulse. The specific configuration of the waveform, pulse width, and amplitude of the first electric pulse and the second electric pulse is not limited in the embodiments of the present application.

[0117] In a possible implementation, the second electric pulse can completely crystallize the phase change material in the phase change memory cell.

[0118] In a possible implementation, for the method one in step 502, the number of times that the target phase change memory cell is applied with the second electric pulse can also be counted. In the case where the number of times that the target phase change memory cell is applied with the second electric pulse reaches a fourth threshold value, the number of times that the target phase change memory cell is subjected to the set operation (or the number of times that the target phase change memory cell is applied with the first electric pulse) is reset to zero, and the number of times that the target phase change memory cell is applied with the second electric pulse is reset to zero, and the counting of the next round is restarted. The fourth threshold value can be configured by relevant personnel according to actual needs. For example, the fourth threshold value is 10 times.

[0119] For the method two in step 502, for each memory region in the phase change memory, the number of times that each phase change memory cell in the memory region is applied with the second electric pulse can also be counted. In the case where the number of times that each phase change memory cell in the memory region to which the target phase change memory cell belongs is applied with the second electric pulse reaches a fourth threshold value, the total number of times that each phase change memory cell in the memory region to which the target phase change memory cell belongs is subjected to the set operation (or the total number of times that all phase change memory cells in the memory region to which the target phase change memory cell belongs are applied with the first electric pulse) is reset to zero, and the number of times that the target phase change memory cell is applied with the second electric pulse is reset to zero, and the counting of the next round is restarted.

[0120] Alternatively, for the method two in step 502, for each storage region in the phase change memory, the total number of times that all phase change storage cells in the storage region are applied with the second electric pulse can also be counted. In the case that the total number of times that all phase change storage cells in the storage region to which the target phase change storage cell belongs are applied with the second electric pulse reaches a fifth threshold value, the total number of times that each phase change storage cell in the storage region to which the target phase change storage cell belongs is counted for the set operation is reset to zero (or the total number of times that all phase change storage cells in the storage region to which the target phase change storage cell belongs are applied with the first electric pulse is reset to zero), and the total number of times that all phase change storage cells in the storage region to which the target phase change storage cell belongs are applied with the second electric pulse is reset to zero, and the counting of the next round is restarted. The fifth threshold value can be configured by relevant personnel according to actual needs. For example, the fifth threshold value is 100 times.

[0121] Alternatively, for the method two in step 502, for each storage region in the phase change memory, the average number of times that all phase change storage cells in the storage region are applied with the second electric pulse can also be counted. In the case that the average number of times that all phase change storage cells in the storage region to which the target phase change storage cell belongs are applied with the second electric pulse reaches a fourth threshold value, the total number of times that all phase change storage cells in the storage region to which the target phase change storage cell belongs are counted for the set operation is reset to zero (or the total number of times that all phase change storage cells in the storage region to which the target phase change storage cell belongs are applied with the first electric pulse is reset to zero), and the average number of times that all phase change storage cells in the storage region to which the target phase change storage cell belongs are applied with the second electric pulse is reset to zero, and the counting of the next round is restarted.

[0122] A large number of experimental results show that, in the case that the phase change storage cell is continuously applied with the first electric pulse for the set operation, the write number of the phase change storage cell is about 1E4.5 times, or even less. In the case that the technical solution provided in the embodiments of the present application is adopted, after 1E4 set operations are performed on the phase change storage cell, the phase change material of the phase change storage cell is completely crystallized by applying the second electric pulse once, and the write number of the phase change storage cell can reach 1E7 times. It can be seen that, by adopting the technical solution provided in the present application, the phase change storage cell can have more erase and write numbers and a longer service life, and at the same time, the read and write speeds are basically not affected, and the high-speed read and write requirement can still be met.

[0123] The embodiments of the present application also provide a control device of a phase change memory. The device can be a storage controller. As shown in FIG. 6, the device includes a receiving module 710 and a control module 720, wherein:

[0124] The receiving module 710 is configured to receive a first write instruction for a target phase change storage cell in the phase change memory.

[0125] The control module 720 is configured to determine that the target phase change memory cell does not satisfy the complete crystallization condition, and control the read-write circuit to apply a first electrical pulse to the target phase change memory cell, where the first electrical pulse is used to perform a set operation on the target phase change memory cell.

[0126] The receiving module 710 is configured to receive a second write instruction for the target phase change memory cell.

[0127] The control module 720 is configured to determine that the target phase change memory cell satisfies the complete crystallization condition, and control the read-write circuit to apply a second electrical pulse to the target phase change memory cell, where the second electrical pulse is used to perform a set operation on the target phase change memory cell, the pulse width of the second electrical pulse is greater than the pulse width of the first electrical pulse, and / or the amplitude of the second electrical pulse is greater than the amplitude of the first electrical pulse.

[0128] In a possible implementation, the apparatus further includes a statistical module configured to:

[0129] count the number of times that each phase change memory cell in the phase change memory performs a set operation;

[0130] The control module 720 is configured to:

[0131] determine that the number of times that the target phase change memory cell performs a set operation counted by the statistical module does not reach a first threshold value;

[0132] determine that the number of times that the target phase change memory cell performs a set operation counted by the statistical module reaches the first threshold value.

[0133] In a possible implementation, the statistical module is further configured to:

[0134] count the number of times that each phase change memory cell in the phase change memory is applied with the second electrical pulse;

[0135] In a case where it is determined that the number of times that the target phase change memory cell is applied with the second electrical pulse reaches a second threshold value, the number of times that the target phase change memory cell performs a set operation counted by the statistical module is reset to zero, and the number of times that the target phase change memory cell is applied with the second electrical pulse counted by the statistical module is reset to zero.

[0136] In a possible implementation, the apparatus further includes a statistical module configured to:

[0137] count, for each memory region in the phase change memory, the total number of times that each phase change memory cell in the memory region performs a set operation;

[0138] The control module 720 is configured to:

[0139] determining whether a total number of times that all phase change memory cells in a storage region to which the target phase change memory cell belongs perform set operations reaches a third threshold value;

[0140] determining whether a total number of times that all phase change memory cells in a storage region to which the target phase change memory cell belongs perform set operations reaches the third threshold value.

[0141] In a possible implementation, the statistical module is further configured to:

[0142] For each storage region in the phase change memory, a total number of times that all phase change memory cells in the storage region are applied with the second electric pulse is counted. In a case where the total number of times that all phase change memory cells in a target storage region to which the target phase change memory cell belongs are applied with the second electric pulse reaches a second threshold value, a total number of times that each phase change memory cell in the target storage region performs set operations is reset, and the total number of times that all phase change memory cells in the target storage region to which the target phase change memory cell belongs are applied with the second electric pulse is reset.

[0143] In a possible implementation, the control module 720 is configured to:

[0144] determining whether data stored in a storage region to which the target phase change memory cell belongs reaches a fourth threshold value;

[0145] determining whether data stored in a storage region to which the target phase change memory cell belongs reaches the fourth threshold value.

[0146] In a possible implementation, the storage region is one of a storage block, a storage array, a storage row, and a storage column.

[0147] Since the set operation is usually performed by applying a first electric pulse with a narrow pulse width and a small amplitude on the phase change memory cell at present in order to improve the write speed, however, such an electric pulse only causes a small part of the phase change material of the phase change memory cell to crystallize, which reduces the service life of the phase change memory. Based on this, the technical scheme provided in the present application first determines whether the phase change memory cell satisfies the complete crystallization condition before performing the set operation on the phase change memory cell, and in a case where the phase change memory cell satisfies the complete crystallization condition, controls the read-write circuit to apply a second electric pulse with a wider pulse width and / or a larger amplitude than the first electric pulse on the phase change memory cell to perform the set operation on the phase change memory cell. The second electric pulse can make the phase change memory cell crystallize more completely, thereby improving the fatigue characteristics of the phase change memory cell and prolonging the service life of the phase change memory.

[0148] It should be noted that the control device of the phase change memory provided in the above embodiment is only used for example to illustrate the division of the above functional modules when performing control on the phase change memory. In actual application, the above functions can be completed by different functional modules according to the needs, that is, the internal structure of the storage controller is divided into different functional modules to complete all or part of the functions described above. In addition, the control device of the phase change memory provided in the above embodiment and the control method of the phase change memory belong to the same concept, and the specific implementation process is described in the method embodiment, which will not be repeated here.

[0149] The embodiment of the present application further provides a structural schematic diagram of an electronic device, as shown in FIG. 7, which includes a processor and a storage system as described in the above embodiment. The processor is configured to send a read-write instruction to the storage system to enable the storage system to perform a read-write operation.

[0150] The processor is, for example, a general central processing unit (CPU), a network processor (NP), a graphics processing unit (GPU), a neural-network processing unit (NPU), a data processing unit (DPU), a microprocessor or one or more integrated circuits. For example, the processor includes an application-specific integrated circuit (ASIC), a programmable logic device (PLD) or a combination thereof. The PLD is, for example, a complex programmable logic device (CPLD), a field-programmable gate array (FPGA), a generic array logic (GAL) or any combination thereof.

[0151] In the embodiments described above, all or part of the embodiments can be implemented by software, hardware, firmware or any combination thereof, and when implemented by software, all or part of the embodiments can be implemented in the form of a computer program product. The computer program product includes one or more computer instructions, which, when loaded and executed by a device, generate all or part of the processes or functions described in the embodiments of the present application. The computer instructions can be stored in a computer readable storage medium or transmitted from one computer readable storage medium to another computer readable storage medium, for example, the computer instructions can be transmitted from one website, computer, server or data center to another website, computer, server or data center through wired (such as coaxial cable, optical fiber, digital subscriber line) or wireless (such as infrared, wireless, microwave, etc.) mode. The computer readable storage medium can be any available medium accessible by a device or a data storage device such as a server, data center, etc. containing one or more available media. The available media can be magnetic media (such as floppy disk, hard disk and magnetic tape, etc.), optical media (such as digital video disk (digital video disk, DVD), etc.), or semiconductor media (such as solid state disk, etc.).

[0152] The terms "first", "second", and the like in the present application are used to distinguish between elements or items having substantially the same function and the same meaning, and it should be understood that there is no logical or chronological dependency between "first" and "second", and the number and execution order are not limited. It should also be understood that although the following description uses the terms first, second, and the like to describe various elements, these elements should not be limited by the terms. These terms are only used to distinguish one element from another. For example, without departing from the scope of various examples, a first storage unit can be referred to as a second storage unit, and similarly, a second storage unit can be referred to as a first storage unit. The first storage unit and the second storage unit can be collectively referred to as storage units, and in some cases, different storage units can be referred to respectively. For example, without departing from the scope of various examples, a first write instruction can be referred to as a second write instruction, and similarly, a second write instruction can be referred to as a first write instruction. The first write instruction and the second write instruction can be collectively referred to as write instructions, and in some cases, different write instructions can be referred to respectively.

[0153] In the present application, the term "at least one" means one or more, and the term "multiple" in the present application means two or more.

[0154] The above description is only the specific implementation of the present application, but the protection scope of the present application is not limited to this, any skilled person in the art can easily think of various equivalent modifications or replacements within the technical range disclosed by the present application, and these modifications or replacements should be covered in the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

Claims

1. A control method of a phase change memory, characterized by, The method comprises: receiving a first write instruction for a target phase change memory cell in the phase change memory; determining that the target phase change memory cell does not satisfy a complete crystallization condition, and controlling a read-write circuit to apply a first electrical pulse to the target phase change memory cell, wherein the first electrical pulse is used for a set operation on the target phase change memory cell; receiving a second write instruction for the target phase change memory cell; determining that the target phase change memory cell satisfies the complete crystallization condition, and controlling the read-write circuit to apply a second electrical pulse to the target phase change memory cell, wherein the second electrical pulse is used for the set operation on the target phase change memory cell, a pulse width of the second electrical pulse is greater than a pulse width of the first electrical pulse, and / or an amplitude of the second electrical pulse is greater than an amplitude of the first electrical pulse.

2. The method of claim 1, wherein, The method further comprises: counting a number of times of set operations on each phase change memory cell in the phase change memory; the determining that the target phase change memory cell does not satisfy the complete crystallization condition comprises: determining that the counted number of times of set operations on the target phase change memory cell does not reach a first threshold value; the determining that the target phase change memory cell satisfies the complete crystallization condition comprises: determining that the counted number of times of set operations on the target phase change memory cell reaches the first threshold value.

3. The method of claim 2, wherein, The method further comprises: counting a number of times of application of the second electrical pulse to each phase change memory cell in the phase change memory; in a case where the counted number of times of application of the second electrical pulse to the target phase change memory cell reaches a second threshold value, resetting the counted number of times of set operations on the target phase change memory cell and resetting the counted number of times of application of the second electrical pulse to the target phase change memory cell.

4. The method of claim 1, wherein, The method further comprises: for each memory region in the phase change memory, counting a total number of times of set operations on phase change memory cells in the memory region; the determining that the target phase change memory cell does not satisfy the complete crystallization condition comprises: determining that a total number of times of set operations on all phase change memory cells in a memory region to which the target phase change memory cell belongs does not reach a third threshold value; the determining that the target phase change memory cell satisfies the complete crystallization condition comprises: determining that the total number of times of set operations on all phase change memory cells in the memory region to which the target phase change memory cell belongs reaches the third threshold value.

5. The method of claim 4, wherein, The method further comprises: for each memory region in the phase change memory, counting a total number of times of application of the second electrical pulse to all phase change memory cells in the memory region; in a case where the total number of times of application of the second electrical pulse to all phase change memory cells in the memory region to which the target phase change memory cell belongs reaches a second threshold value, resetting the counted total number of times of set operations on phase change memory cells in the target memory region and resetting the counted total number of times of application of the second electrical pulse to all phase change memory cells in the memory region to which the target phase change memory cell belongs.

6. The method of claim 1, wherein, the determining that the target phase change memory cell does not satisfy the complete crystallization condition comprises: determining that data stored in a storage region to which the target phase change memory cell belongs does not reach a fourth threshold value; the determining that the target phase change memory cell satisfies the complete crystallization condition comprises: determining that data stored in a storage region to which the target phase change memory cell belongs reaches the fourth threshold value.

7. The method according to any one of claims 4-6, characterized in that, The storage region is one of a storage block, a storage array, a storage row, and a storage column.

8. A control device of a phase change memory, characterized by comprising: The apparatus comprises: a receiving module configured to receive a first write instruction for a target phase change memory cell in the phase change memory; a control module configured to determine that the target phase change memory cell does not satisfy the complete crystallization condition, and control a read-write circuit to apply a first electric pulse to the target phase change memory cell, wherein the first electric pulse is used to perform a set operation on the target phase change memory cell; the receiving module is configured to receive a second write instruction for the target phase change memory cell; the control module is configured to determine that the target phase change memory cell satisfies the complete crystallization condition, and control the read-write circuit to apply a second electric pulse to the target phase change memory cell, wherein the second electric pulse is used to perform a set operation on the target phase change memory cell, a pulse width of the second electric pulse is greater than a pulse width of the first electric pulse, and / or an amplitude of the second electric pulse is greater than an amplitude of the first electric pulse.

9. A storage system, characterized by The storage system comprises a storage controller and a phase change memory, and the storage controller is configured to perform the control method of the phase change memory according to any one of claims 1-7.

10. An electronic device, comprising: The electronic device comprises a processor and the storage system according to claim 9. The processor is configured to send a read-write instruction to the storage system to enable the storage system to perform a read-write operation.

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