Optoelectronic component comprising an optoelectronic semiconductor chip and an additional chip associated with said optoelectronic semiconductor chip

Abstract

The invention relates to an optoelectronic component (100), comprising: - a carrier (110) having a recess (120); - an optoelectronic semiconductor chip (130), wherein the optoelectronic semiconductor chip (130) is mounted with an underside (132) on an upper side (111) of the carrier (110) and at least partially covers the recess (120) of the carrier (110); and - an additional chip (140) associated with the optoelectronic semiconductor chip (130), wherein the additional chip (140) is arranged in the recess (120) of the carrier (110) and is mounted with an upper side (141) on the underside (132) of the optoelectronic semiconductor chip (130).

Description

[0001] OPTOELECTRONIC COMPONENT WITH AN OPTOELECTRONIC SEMICONDUCTOR CHIP AND AN ADDITIONAL CHIP ASSOCIATED TO THE OPTOELECTRONIC SEMICONDUCTOR CHIP

[0002] DESCRIPTION

[0003] The present invention relates to an optoelectronic component comprising an optoelectronic semiconductor chip and an additional chip associated with the optoelectronic semiconductor chip. The invention further relates to a lighting device comprising such an optoelectronic component.

[0004] This patent application claims priority over German patent application DE 10 2024 115 867 . 0, the disclosure content of which is hereby incorporated by reference.

[0005] Optoelectronic components, such as light-emitting diodes (LEDs), are used as light sources in various lighting devices. A typical optoelectronic component usually consists of a housing with a substrate (e.g., leadframe, printed circuit board (PCB)) and at least one light-emitting semiconductor chip mounted on the substrate. In addition to the light-emitting semiconductor chip, optoelectronic components are often equipped with one or more other chips. For example, in LED components, an ESD diode or an NTC resistor is frequently used alongside the LED chip. Typically, the additional chips and the optoelectronic semiconductor chips are arranged side by side on the substrate. In an LED component, an ESD diode can be placed in the same cavity as the LED chip or embedded in the component's housing.Such an additional chip requires additional space, leading to an increase in component size. Furthermore, the additional chips are typically contacted via wire bonding, which also requires additional space and introduces reliability risks. Due to the increased space requirement of the additional chip, a true chip-size package (CSP) cannot be achieved by arranging the LED chip and ESD chip side by side.

[0006] To reduce the space required for the additional chip, it would also be possible, in principle, to arrange the additional chip on the underside of the substrate. However, this arrangement would require corresponding additional electrical conductor structures to electrically connect the additional chip to the semiconductor chip located on the top side of the substrate.

[0007] In optoelectronic components with light-emitting semiconductor chips, it may be necessary to measure the actual temperature of the semiconductor chips in order to regulate the brightness via the operating current and prevent premature aging. For this purpose, an NTC resistor is usually placed on the substrate near the optoelectronic semiconductor chip, which also increases the space requirement and, moreover, makes it more difficult to determine the actual temperature of the optoelectronic semiconductor chip due to the spatial separation between the optoelectronic semiconductor chip and the NTC resistor.

[0008] It is therefore an object of the invention to provide an optoelectronic component for a lighting device which has the smallest possible component size. This object is achieved by an optoelectronic component with the features of independent claim 1. Furthermore, the object is achieved by a lighting device with the features of independent claim 12. Further advantageous embodiments are specified in the dependent claims.

[0009] According to a first aspect, an optoelectronic component is provided, comprising a carrier with a recess and an optoelectronic semiconductor chip, wherein the optoelectronic semiconductor chip is mounted with one underside on a top side of the carrier and at least partially covers the recess of the carrier. Furthermore, the optoelectronic component comprises an additional chip associated with the optoelectronic semiconductor chip, wherein the additional chip is arranged in the recess of the carrier and is mounted with one top side directly on the underside of the optoelectronic semiconductor chip. The arrangement of the additional chip below the optoelectronic semiconductor chip results in a reduction of the space requirements of both chips. This enables, for example, a true chip-size package, in which the lateral dimensions of the optoelectronic component are essentially determined by the size of the optoelectronic chip.Furthermore, by arranging the additional chip directly below the semiconductor chip, direct contact between the two components can be achieved. This increases the reliability of the electrical connection between the two components. Additionally, the direct contact of the two components, when using an additional chip in the form of an NTC resistor, enables measurement of the actual temperature of the optoelectronic semiconductor chip. By placing the additional chip in a recess of the substrate, no additional vertical space is required for the chip, allowing for a minimal component height or even a reduction in overall component height.

[0010] With regard to the direct mounting of the additional chip, it is intended that the additional chip is attached directly to the underside of the optoelectronic semiconductor chip and is in direct mounting contact with the optoelectronic semiconductor chip.

[0011] In one possible embodiment, the direct mounting of the additional chip on the underside of the optoelectronic semiconductor chip is achieved by means of a material-fit attachment of the additional chip to the optoelectronic semiconductor chip. This attachment can be realized using a fastening material, for example, solder, adhesive, or another suitable fastening material.

[0012] In another embodiment, the optoelectronic semiconductor chip is designed to completely overlap the additional chip laterally. This results in a particularly small component footprint, enabling especially small component sizes.

[0013] In another embodiment, the optoelectronic semiconductor chip has one or more electrical connection structures on its underside, wherein the optoelectronic semiconductor chip is electrically connected via at least one of these electrical connection structures to at least one electrical conductor structure arranged on the top side of the substrate. The connection structures on the underside of the semiconductor chip reduce the chip's footprint, thus enabling a smaller component size.

[0014] In another embodiment, the additional chip has at least one electrical connection structure on its upper surface, which is electrically connected to at least one electrical connection structure on the underside of the optoelectronic semiconductor chip. This simplifies the electrical connection between the two components. Additional electrical conductor structures, usually required for contacting the components, can be omitted.

[0015] In another embodiment, the recess extends through the entire carrier, and the additional chip has at least one further electrical connection structure on its underside. This makes it possible to directly connect the additional chip to an electrical conductor structure on the top side of a base carrier that houses the optoelectronic component. Thus, additional electrical conductor structures for contacting the additional chip are not necessary.

[0016] In another embodiment, the recess is designed as a depression that does not completely penetrate the substrate, with the additional chip having at least two electrical connection structures on its upper surface, each of which is electrically connected to an electrical connection structure located on the underside of the optoelectronic semiconductor chip. This arrangement enables electrical and / or thermal isolation of the additional chip from the base substrate.

[0017] In another embodiment, the additional chip is designed as an ESD diode, an NTC resistor, or an AS IC chip. The ESD diode protects the semiconductor chip from overvoltages, and its direct placement beneath the semiconductor chip eliminates the need for additional electrical conductors. By placing an NTC resistor directly adjacent to the optoelectronic semiconductor chip, the chip's temperature can be measured with exceptional accuracy. Finally, even with an AS IC chip positioned directly beneath the semiconductor chip, electrical conductors for connecting the two components are unnecessary.

[0018] In another embodiment, the optoelectronic component comprises at least two additional chips associated with the optoelectronic semiconductor chip, with each additional chip being mounted on the underside of the optoelectronic semiconductor chip. By arranging several additional chips within the semiconductor chip, a particularly large reduction in component size can be achieved.

[0019] In another embodiment, a first additional chip is designed as an ESD diode associated with the optoelectronic semiconductor chip, and a second additional chip is designed as an NTC resistor associated with the optoelectronic semiconductor chip. An advantage of this arrangement is that both the ESD diode and the NTC resistor are relatively small components that can be easily arranged and electrically connected below the optoelectronic semiconductor chip in the manner shown here.

[0020] In another embodiment, the substrate can be a lead frame, a printed circuit board, a ceramic substrate, a routable QFN substrate, or a MIS substrate. A lead frame offers particularly good heat dissipation. Using a printed circuit board allows for relatively complex rewiring and relatively cost-effective manufacturing of the component. A ceramic substrate combines good thermal conductivity with good electrical insulation. In contrast, a routable QFN substrate is particularly well-suited for implementing more complex rewiring.

[0021] In another embodiment, the optoelectronic component is designed as an LED. By arranging the additional chips beneath the semiconductor chip, so-called chip-size packages can be realized, particularly in LED components, enabling the construction of lighting devices with a particularly high component density. This allows for exceptionally high luminous intensity and / or resolution.

[0022] According to a further aspect, a lighting device is provided comprising a base carrier and at least one optoelectronic component mounted on the base carrier. The optoelectronic component comprises a carrier with a recess, an optoelectronic semiconductor chip mounted with its underside on a top side of the carrier and at least partially covering the recess of the carrier, and at least one additional chip associated with the optoelectronic semiconductor chip, which is arranged in the recess of the carrier and is mounted with its top side directly on the underside of the optoelectronic semiconductor chip. The optoelectronic component is mounted with its underside on a top side of the base carrier and is electrically connected to an electrical conductor structure arranged on the base carrier via at least one electrical conductor structure located on the underside of the carrier.The advantages already mentioned in connection with the previously described optoelectronic component also apply to such a lighting device. In particular, due to the reduced component size and the smaller footprint of a single optoelectronic component on the base carrier, a larger number of optoelectronic components can be accommodated side by side than is possible with conventional optoelectronic components. This allows, for example, lighting devices with higher luminous intensities to be realized. Similarly, lighting devices can also be realized that, with the same number of optoelectronic components and the same luminous intensity, have a smaller lateral dimension.

[0023] In one embodiment, the recess extends through the entire carrier, with the additional chip located in the recess being mounted on the base carrier with one underside facing down. The advantages already mentioned in connection with a similarly designed optoelectronic component also apply to a lighting device designed in this way.

[0024] In one embodiment, the additional chip is provided to have at least one further electrical connection structure on its underside, which is electrically connected to at least one electrical conductor structure arranged on the base carrier. The advantages already mentioned in connection with the correspondingly designed optoelectronic component also apply to a lighting device designed in this way. In particular, the wiring to the carrier of the optoelectronic component can be simplified by a direct electrical connection of at least certain electrical connections of the additional chip to corresponding electrical conductor structures on the base carrier.

[0025] In one embodiment, the additional chip is designed as an ESD diode, an NTC resistor, or an AS IC chip. The advantages already mentioned in connection with a correspondingly designed optoelectronic component also apply to these variants of the lighting device.

[0026] The properties, features, and advantages of this invention described above, as well as the manner in which they are achieved, will become clearer and more readily understandable in connection with the following description of the exemplary embodiments, which are explained in more detail in conjunction with the drawings. The drawings show:

[0027] Fig. 1 schematically shows a cross-section through an arrangement comprising an optoelectronic component mounted on a base carrier with a conductor frame, an LED chip mounted thereon, and an additional chip mounted on the underside of the LED chip and arranged in a recess of the conductor frame.

[0028] Fig. 2 schematically shows a cross-section through another arrangement, which is essentially analogous to the arrangement from Figure 1, but in which the optoelectronic component has a printed circuit board as a carrier.

[0029] Fig. 3 schematically shows a cross-section through another arrangement, which is essentially analogous to the arrangement in Figure 1, except that the additional chip is connected to its own electrical conductor structure of the base carrier. Fig. 4 schematically shows a cross-section through another arrangement, which is essentially analogous to the arrangement in Figure 2, except that the additional chip is mounted on the underside of the LED chip in a central area of ​​the LED chip and is also connected to its own electrical conductor structure of the base carrier.

[0030] Fig. 5 schematically shows a top view of an optoelectronic component designed according to Figure 1, wherein the additional chip is arranged in a corner of the semiconductor chip.

[0031] Fig. 6 schematically shows a top view of an arrangement corresponding to Figure 1, in which the optoelectronic component shown in Figure 5 is mounted on a base carrier designed as a printed circuit board.

[0032] Fig. 7 schematically shows a top view of another optoelectronic component designed according to Figure 1, wherein the additional chip is arranged in a central edge region of the semiconductor chip.

[0033] Fig. 8 schematically shows a top view of another arrangement corresponding to Figure 1, in which the optoelectronic component shown in Figure 7 is mounted on a base carrier designed as a printed circuit board.

[0034] Fig. 9 schematically shows a top view of another optoelectronic component designed according to Figure 1, wherein two different additional chips are arranged in an edge region on the underside of the optoelectronic semiconductor chip.

[0035] Fig. 10 schematically shows a top view of an arrangement corresponding to Fig. 1, in which the optoelectronic component shown in Fig. 9 is mounted on a base carrier designed as a printed circuit board. Fig. 11 schematically shows a cross-section through an alternative arrangement with an optoelectronic component mounted on a base carrier, comprising a carrier designed as a conductor frame, an LED chip mounted thereon as a flip chip, and an additional chip mounted on the underside of the LED chip and arranged in a recess of the conductor frame.

[0036] Fig. 12 schematically shows a top view of an optoelectronic component designed according to Figure 11, wherein the additional chip is arranged in a corner of the LED chip.

[0037] Fig. 13 schematically shows a top view of an arrangement corresponding to Figure 11, in which the optoelectronic component shown in Figure 12 is mounted on a base carrier designed as a printed circuit board.

[0038] Fig. 14 schematically shows a cross-section through an alternative embodiment of the optoelectronic component with an LED chip mounted on a circuit board as a flip chip and an AS IC chip arranged on the underside of the LED chip and electrically connected via two electrical terminals on the underside of the LED chip, and

[0039] Fig. 15 schematically shows a cross-section through an alternative embodiment of the optoelectronic component from Figure 14, wherein the AS IC chip arranged on the underside of the LED chip designed as a flip chip is electrically connected via only one electrical connection on the underside of the LED chip.

[0040] The following concept involves placing or mounting an additional chip (e.g., an ESP diode or NTC resistor for temperature measurement) directly onto the underside of the optoelectronic semiconductor chip (e.g., an LED chip), which serves as the mounting surface. The terms "directly mounted," "directly arranged," and "directly placed" are used synonymously in this disclosure and each refers to an arrangement in which the additional chip is directly attached to the optoelectronic semiconductor chip and is in direct contact with it. These terms also include attachments made using solder, adhesive, or other fastening materials.

[0041] The terms "directly mounted," "directly arranged," or "directly placed" do not include arrangements in which, apart from one of the aforementioned mounting materials, at least one other component, such as a support element, a layer, or a comparable support structure, is arranged between the additional chip and the optoelectronic semiconductor chip. Therefore, arrangements in which the optoelectronic semiconductor chip is attached to the top side of a support structure, while the additional chip is attached to the bottom side of the support structure without being in direct mounting contact with the optoelectronic semiconductor chip, are excluded from the terms "directly mounted," "directly arranged," or "directly placed."

[0042] The substrate or carrier for the semiconductor chip is provided with a corresponding recess or opening. The thickness of the carrier and the additional chip are preferably matched to each other. If the carrier has a continuous recess, the additional chip can be contacted directly via the base carrier on which the respective optoelectronic component is mounted.

[0043] Figure 1 shows an arrangement consisting of a base carrier 210 and an optoelectronic component 100 mounted thereon, with an associated additional chip 140. The arrangement preferably forms part of a lighting device 200, which typically comprises a plurality of optoelectronic components mounted on the base carrier 210. For the sake of clarity, however, only a single optoelectronic component 100 is shown here. The optoelectronic component 100 is preferably an LED component comprising a carrier 110 and an LED chip 130 mounted thereon, wherein, in the example shown here, the LED chip 130 emits light radiation 101, 102 substantially in the z-direction. In principle, however, optoelectronic components with several LED chips mounted on the carrier can also be used.Furthermore, optoelectronic components can also be used that contain other light-emitting semiconductor chips (e.g., laser diodes) instead of LED chips 130. In the present example, the carrier 110 is designed in the form of a lead frame and typically comprises several carrier parts 110.1, 110.2, each forming electrically isolated conductor structures. The carrier parts 110.1, 110.2 can be produced, for example, from a metal foil using a suitable etching process. As shown in Figure 1, the LED chip 130, mounted directly on the carrier 111, has an electrical connection structure 134 on its underside 132, which electrically connects the LED chip 130 to an electrical conductor structure 113 formed by the top side 111 of a first carrier part 110.1.Furthermore, the LED chip 130 has a further electrical connection structure 133 on a top surface 131, which is connected via a bond wire 118 to an electrical conductor structure on the top surface 111 of a second carrier part 110.2. As shown in the present example, a conversion element 150 can also be arranged on the top surface 131 of the LED chip 130, which causes a conversion of at least a part of the light radiation 101 emitted by the LED chip 130 with a first wavelength into light radiation 102 with a second wavelength.

[0044] As can be further seen from Figure 1, an additional chip 140 is mounted on the underside 132 of the semiconductor chip 130. This additional chip is a component associated with the semiconductor chip 140, such as an ESD diode, an NTC resistor, or a chip with another function necessary for the operation of the optoelectronic component 100. The additional chip 140 is housed in a recess 120 of the carrier 110, located between the two carrier parts 110.1 and 110.2. This recess is designed as an opening that completely penetrates the carrier 110. The height of the additional chip 140 is preferably adapted to the height of the carrier 110, so that the additional chip 140 extends to the underside 112 of the carrier 110 and is flush with the carrier 110.

[0045] As can be further seen from Figure 1, the additional chip 140 is laterally overlaid on all sides by the semiconductor chip 130 positioned above it, so that the additional chip 140 is completely covered by the semiconductor chip 130, or rather, is located entirely below the semiconductor chip 130. The exact lateral position of the additional chip 140 with respect to the semiconductor chip 130 depends on the specific application. In the present example, the additional chip 140 is located in an edge region of the semiconductor chip 130.

[0046] As can be further seen from Figure 1, the additional chip 140 is electrically connected to the electrical connection structure 134 on the underside 132 of the semiconductor chip 130 via an electrical connection structure 143 arranged on its upper side. Furthermore, the additional chip 140 has another electrical connection structure 144 on its underside, which serves for electrical connection to an electrical conductor structure 213.2 arranged on the upper side 211 of the respective base carrier 210. In the embodiment shown here, the additional chip 140 is electrically connected to an electrical conductor structure 213.2, to which the second carrier part 110.2 is also electrically connected via an electrical connection structure 114.2 formed by the underside 112 of the second carrier part. However, the carrier part 110... 1 via an electrical connection structure 114 illustrated by the underside 212 of the first carrier part.1 is electrically connected to another electrical conductor structure 213.1 formed on the upper surface 211 of the base carrier 210. As shown by way of example in Figure 1, the electrical connection between the electrical connection structures 114.1, 114.2, 144 on the underside 112 of the component 100 and the electrical conductor structures 213.1, 213.2 on the upper surface 211 of the base carrier 210 is made using solder 119. In principle, however, other suitable materials can also be used for this purpose, such as an electrically conductive adhesive.

[0047] As can be further seen from Figure 1, the carrier 110, the optoelectronic semiconductor chip 130, and the additional chip 140 arranged below it are, in the present example, encased in a potting compound 170, which forms the housing 160 of the optoelectronic component 100. The housing 160 preferably encloses all components of the component 100, with essentially only the electrical connection structures 114.1, 114.2, 144 being accessible on the underside 112 of the component 100 at the surface of the housing 160. As shown by way of example in Figure 1, parts of the carrier 110 overmolded by the housing material (e.g., lead frame, ceramic, PCB, etc.) can also be flush with the surface of the housing 160 at the side faces.

[0048] Optoelectronic semiconductor chips can, in principle, also be mounted on substrates or carriers other than a leadframe. Figure 2 shows an arrangement 200 analogous to Figure 1, consisting of a base carrier 210 and an optoelectronic component 100 mounted thereon with an associated additional chip 140. However, in this arrangement, the optoelectronic component 100 uses a printed circuit board (PCB) as a carrier 110 instead of a leadframe. Such a PCB 110 typically consists of a plate made of an electrically insulating material (dielectric) on whose top and bottom surfaces 111, 112 metal layers are arranged. Electrical conductor structures 113.1, 113.2, 114.1 are embedded in the metal layers.

[0049] 114.2 structured in the form of metallic conductor tracks. The conductor tracks 113.1, 113.2 on the top side 111 of the carrier 110 and the conductor tracks 114.1, 114.2 on the bottom side 112 of the carrier 110 are electrically connected to each other via metallic contacts 117. In principle, printed circuit boards can also consist of several layers of structured metal layers and dielectrics arranged one above the other.

[0050] Even when using a printed circuit board as the carrier 110 for the component 100, the additional chip 140 can, in principle, extend over the entire height of the carrier 110 and be directly connected to conductor structures on the top surface of the base carrier 110 in an analogous manner to the embodiment shown in Figure 1. As shown by way of example in Figure 2, the additional chip 140 can be connected not directly, but via an electrical conductor structure 114 arranged on the underside 112 of the carrier 110.

[0051] 213.2 on the upper surface 211 of the base carrier 210 is electrically connected. For this purpose, the second conductor structure 114.2 extends on the underside 112 of the carrier 110 to below the additional chip 140 and contacts the electrical connection structure 144 on the underside of the additional chip 140. In the present embodiment, the lower connection structure 114.2 of the carrier 110 completely spans the recess 120 formed in the carrier 110, so that the recess 120 essentially has the form of a blind hole. The carrier extends approximately from the depth of the recess in the upper metallization of the carrier 110 directly below the LED chip and in the dielectric of the carrier 110 to the lower metal layer of the carrier 110, which contacts the ESD chip. Accordingly, the additional chip 140 has a slightly lower height than the entire carrier 110.If the substrate is constructed in the form of a stack of layers consisting of several superimposed layers of metal layers and dielectrics, the additional chip can, in principle, protrude through several of these metal layers and dielectric layers.

[0052] As can be seen from the exemplary embodiment shown in Figure 2, the additional chip 140 can also be located at the outermost edge of the semiconductor chip 130. In this case, too, maximum space savings are achieved. Depending on the application, it may even be possible for certain areas of the additional chip 140 to extend over the edge of the semiconductor chip 130 positioned above it. Such an arrangement can be useful or advantageous, for example, in cases where such an arrangement does not require significant space and / or where contacting the top surface 141 of the additional chip 140 is useful or necessary for electrical, thermal, or other reasons.Furthermore, in principle, there are also conceivable applications in which the edge area of ​​the semiconductor chip 110 has a niche-shaped recess and the additional chip 140 arranged below the semiconductor chip 110 extends partially into the area of ​​this niche-shaped recess (not shown here).

[0053] Figure 3 shows an embodiment of the arrangement 200, consisting of a base carrier 210 and an optoelectronic component 110 mounted thereon, with an associated additional chip 140. This arrangement is essentially analogous to the arrangement shown in Figure 1. However, in the example shown here, the additional chip 140 is connected via its lower electrical connection structure 144 to its own electrical conductor structure 213.2 on the upper surface 211 of the base carrier 210. This conductor structure runs separately from the electrical conductor structure 213.3 of the base carrier 20, which is associated with the second carrier part 110.2. In this way, among other things, an electrical connection of the additional chip 140 can be achieved that is independent of the power supply to the semiconductor chip 130.Figure 4 shows a further embodiment of a corresponding arrangement 200 consisting of a base carrier 210 and an optoelectronic component 110 mounted thereon with an associated additional chip 140, which is essentially constructed analogously to the embodiments shown in the preceding Figures 1 to 3. The essential difference is that the additional chip 140 is now located not in an edge region of the semiconductor chip 130, but in a central region of the semiconductor chip 130. In order to realize a separate electrical connection of the additional chip 140, the base carrier 210 has an additional conductor structure 213 on its upper surface 211, which is electrically connected to the lower electrical connection structure 144 of the additional chip 140. The conductor structure 213In the present case, 2 is electrically connected via an electrical conductor 214 running within the dielectric substrate of the base carrier 210. However, other electrical contacts of the conductor structure are also possible in principle.

[0054] 213.2 is possible, for example, via a conductor track running on the underside of the base substrate, which is electrically connected to the conductor structure 213.2 via a via. Furthermore, conductor tracks 213.2 running suitably on the top side 211 of the base carrier 210 can also enable the electrical contacting of the conductor structure 213.2. Additionally, rewiring for contacting the electrical connection structure 114.3 could also be carried out in the substrate 110 of the component 100.

[0055] As shown in the exemplary embodiment depicted in Figure 4, the conductor structure 213.2 can also be electrically connected to a further electrical connection structure 114.2 arranged on the underside 112 of the first support part 110.1. This connection structure is routed separately from the electrical conductor structures of the semiconductor chip via such a conductor structure, which is appropriately routed separately on the underside 112 of the support 110.1.

[0056] 114 . 2 an external electrical contacting of the additional chip 140 can in principle also be realized without the additional conductor track 214 .

[0057] Figure 5 shows a top view of an optoelectronic component 100, which, analogous to the LED component in Figure 1, has a carrier 110 in the form of a two-part lead frame. As can be seen, the additional chip 140 is arranged in a recess 120 of the first carrier part 110.1, which in this drawing is located below the lower right corner of the semiconductor chip 130. The additional chip 140 is completely overlaid laterally by the semiconductor chip 130 positioned above it. Furthermore, it can be seen that a trench-shaped recess runs through the carrier 110, dividing the carrier 100 into the two carrier parts 110.1 and 110.2.

[0058] Figure 6 shows a top view of an arrangement 200 in which the optoelectronic component 100 from Figure 5 is mounted on a base carrier 210. It can be seen that the two electrical conductor structures 213.1, 213.2, arranged on the upper surface 211 of the base carrier 210, each below their respective support section 110.1, 110.2, are electrically isolated from each other by a separating groove 216 running along the upper surface 211 of the base carrier 210. The second conductor structure 213.2 has a web-shaped extension 215 extending towards the recess 120 to below the additional chip 140, which contacts the electrical connection structure on the underside of the additional chip 140.

[0059] Figure 7 shows a top view of another embodiment of the optoelectronic component 100 from Figure 1. Here, the additional chip 140 is also arranged at the right edge of the first carrier part 110.1 below the semiconductor chip, but in a central section of the right edge of the semiconductor chip 130. Accordingly, the rectangular recess 120 is formed as a niche-shaped indentation in the right side wall of the first carrier part 110.1. In this arrangement as well, the additional chip 140 is preferably completely overlaid laterally by the semiconductor chip 130 arranged above it.

[0060] Figure 8 shows a top view of an arrangement 200 in which the optoelectronic component 100 from Figure 7 is mounted on a base carrier 210. In this arrangement as well, the two components on the upper surface 211 of the base carrier 210 are each located below their respective carrier section.

[0061] 110.1, 110.2 arranged electrical conductor structures

[0062] 213.1, 213.2 are electrically isolated from each other by a separating trench 216 running on the top side of the base carrier 210. In this arrangement as well, the second conductor structure 213.2 of the base carrier 210 has a web-shaped extension 215 extending towards the recess 120 to below the additional chip 140, which contacts the electrical connection structure on the underside of the additional chips 140.

[0063] Depending on the application, the optoelectronic component 100 can also comprise several additional chips 140, each assigned to the semiconductor chip 130, which can have the same or different functions. It is advantageous to arrange as many of the additional chips 140 as possible under the semiconductor chip 130. However, it is also possible for only some of the additional chips 140 to be arranged under the semiconductor chip 130, while others are arranged elsewhere in the component 100. In the following, an embodiment of the optoelectronic component 100 is described in conjunction with Figures 9 and 10, which has a total of two additional chips 140.1 and 140.2 arranged under the semiconductor chip 130. Figure 9 shows a top view of the relevant optoelectronic component 100, which is essentially constructed analogously to the component from Figure 1. The first additional chip is 140.1 is also arranged in a central section of the right edge region of the first carrier part 110 . 1 below the semiconductor chip 130. Accordingly, the associated recess 120 . 1 is analogous to the embodiment shown in Figure 7 in the form of a niche-shaped indentation in the right side wall of the first carrier part.

[0064] 110.1. In contrast, the second additional chip 140.2 is arranged analogously to the embodiment shown in Figure 5 in a recess 120.2 of the first carrier part 110.1, located below the lower right corner of the semiconductor chip 130 in the present drawing. In the present example, both recesses 120.1, 120.2 are separated from each other by a rib-shaped extension 215 of the first carrier part 110.1. In principle, however, it is also possible to accommodate several additional chips 140 in a common recess 120 of the first carrier part 110.1. As can be seen from Figure 9, in this arrangement as well, the additional chips 140.1, 140.2 are preferably completely overlaid laterally by the semiconductor chip 130 arranged above them.

[0065] As can also be seen from Figure 9, the support comprises a total of three support parts 110.1, 110.2, 110.3 in addition to the first support part, each separated by trench-shaped partition structures.

[0066] 121.1, 121.2 are electrically isolated from each other.

[0067] Figure 10 shows a top view of an arrangement 200 in which the optoelectronic component 100 from Figure 9 is mounted on a base carrier 210. In the present embodiment, the base carrier 210 comprises a total of three electrical conductor structures 213.1, 213.2, 213.3 on its upper surface 211, each serving for the electrical contacting of a carrier part 110.1, 110.2, 110.3. The conductor structures

[0068] 213.1, 213.2, 213.3 are each arranged below their respective support parts 110.1, 110.2, 110.3 and are electrically insulated from one another by two separating grooves 216.1, 216.2 running on the upper surface of the base support 210. As can also be seen in Figure 10, the second conductor structure 213.2 of the base support 210 has a first web-shaped extension extending towards the first recess 120.1 to below the first additional chip 140.1.

[0069] 215.1, which contacts the electrical connection structure on the underside of the first additional chip 140.1. Furthermore, the third conductor structure 213.3 of the base carrier 210 has a second rib-shaped extension 215.2 extending towards the second recess 120.2 to below the second additional chip 140.2, which contacts the electrical connection structure on the underside of the second additional chip.

[0070] Contacted 140.2.

[0071] The concept described here can also be applied in principle to optoelectronic components with a structure different from those shown as examples in Figures 1 to 10. Figure 11 shows a corresponding embodiment of an optoelectronic component 100 mounted on a base carrier 210, which has an optoelectronic semiconductor chip 130 in the form of a flip chip mounted on a carrier 110. In this design, all electrical connection structures 134.1, 134.2 for electrically contacting the semiconductor chip 130 are located on the underside 132 of the semiconductor chip 130. Since electrical contacts using bond wires are eliminated, a particularly compact carrier 110 can be used, thus reducing the space requirement of the optoelectronic component 100.To further reduce the space requirement, the additional chip 140 assigned to the respective semiconductor chip 130 is arranged in a recess 120 of the carrier on the underside 132 of the semiconductor chip 130, as already described in the previously described embodiments.

[0072] The support 110, shown here as an example in the form of a lead frame, comprises two support sections 110.1, 110.2, which are electrically insulated from each other by a separating trench 121 running through a central area. On the upper surface 111 of each support section 110.1, 110.2, an electrical conductor structure 113.1, 113.2 is formed, to which one of the electrical connection structures 134.1, 134.2 is connected.

[0073] 134.2 of the semiconductor chip 130 is connected. In contrast, the undersides 112 of the two carrier parts 110.1 form

[0074] 110.2 two electrical conductor structures 114.1, 114.2, each of which is electrically connected to one of the two electrical conductor structures 213.1, 213.2 formed on the top surface 211 of the base support 210.

[0075] In the present example, component 100 has an additional chip 140 mounted in the middle section below the semiconductor chip 130, which is located in a recess 120 adjacent to the separating groove 121 in the second carrier part 110.2. The additional chip 140 is connected via its lower electrical connection structure to the first electrical conductor structure 213.1 of the base carrier 210 and via its upper electrical connection structure to the second electrical connection structure 134.2 of the semiconductor chip 130.

[0076] In the present embodiment, the component 100 has a housing 160 which is designed in the form of a frame structure extending along the edge of the carrier on the upper surface 111 and encompassing the semiconductor chip 130.

[0077] Figure 12 shows a top view of the optoelectronic component 100 from Figure 11. It is evident that the carrier 110 is designed as a two-part lead frame. As can also be seen, the additional chip 140 is arranged in a recess 120 formed in the lower left corner of the second carrier part 110.1. The additional chip 140 is completely overlaid laterally by the semiconductor chip 130 located above it. Furthermore, it is evident that the recess adjoins a dividing groove 121 running through the carrier 110, which divides the carrier 100 into the two carrier parts 110.1 and 110.2.

[0078] Figure 13 shows a top view of an arrangement 200 with the optoelectronic component 100 from Figure 12 mounted on a base carrier 210. It can be seen that the two electrical conductor structures 213.1, 213.2, arranged on the upper surface 211 of the base carrier 210 below their respective support sections 110.1, 110.2, are electrically isolated from each other by a separating groove 216 running along the upper surface 211 of the base carrier 210. The first conductor structure 213.1 has a web-shaped extension 215 extending towards the recess 120 to below the additional chip 140, which contacts the electrical connection structure on the underside of the additional chip 140. Simultaneously, the second conductor structure

[0079] 213.2 in this area a corresponding recess, the contour of which preferably corresponds substantially to the contour of the rectangular recess 120 in the second support part 110.2 arranged above it.

[0080] In the embodiments shown in Figures 1 to 13, the additional chips each have two electrical connections, which is particularly common with simple components (e.g., EDS diode or NTC resistor, etc.). However, the concept described here can also be applied to other additional chips associated with the semiconductor chip, such as an ASIC chip for controlling the operation of the semiconductor chip. Figure 14 shows an example of a cross-section through a corresponding optoelectronic component 100. The component 100 comprises a carrier 110 in the form of a printed circuit board, an optoelectronic semiconductor chip 130 designed as a flip chip and mounted on the carrier 110, and a more complex additional chip 140 mounted on the underside 132 of the semiconductor chip 130, which in this example is designed as an ASIC chip associated with the semiconductor chip 130.As can be seen from Figure 14, the additional chip 140 has two electrical connection structures on its upper side 141.

[0081] 143.1, 143.2, each with an electrical connection structure 134.1 on the underside 132 of the semiconductor chip 130,

[0082] 134.2 are electrically connected. On its underside 142, the additional chip 140 has three electrical reject structures.

[0083] Figures 144.1, 144.2, and 144.3 are shown. These connection structures serve for the direct electrical connection of the additional chip 140 to corresponding electrical conductor structures on the top surface of a base carrier (not shown here) that accommodates the component 100. As can be seen in Figure 14, the additional chip 140 is located in a cavity 120 of the carrier 110, which in this example is arranged under a central section of the semiconductor chip 130. The additional chip is embedded in a potting compound 170, which fills the cavity 120.

[0084] Figure 15 shows another embodiment of an optoelectronic component 100, which includes an additional chip 140 designed as an ASIC chip. In this component 100, which is essentially constructed analogously to the component shown in Figure 14, the additional chip 140 is located in an edge region of the semiconductor chip 110. Furthermore, the additional chip is electrically connected via a single electrical connection structure 143 to only one electrical connection structure 134.2 arranged on the underside 132 of the semiconductor chip 130. Depending on the application, the number of electrical connections on the top side of the ASIC chip 140 can vary. The ASIC chip can contact either one or more contacts of the flip chip 130. In the present example, the additional chip has only two electrical connection structures 144.1 and 144.2 on its underside.Here too, the number of contacts on the underside of the ASIC chip 140 can vary depending on the application.

[0085] Besides simple add-on chips (e.g., ESD diode or NTC resistor) with only one contact or solder pad on the underside, more complex ASIC chips can also be used. In this case, the semiconductor chip is, in a sense, mounted on the ASIC chip, but the ASIC chip is completely or substantially overlapped laterally by the semiconductor chip. Preferably, at least one electrical or thermal connection runs outside of and parallel to the ASIC chip. Depending on the application, at least one of the electrical contacts of the semiconductor chip may also not be connected to the ASIC chip. If an ESD diode is used as the add-on chip, it is already connected to the back of the semiconductor chip (e.g., the cathode of the LED chip). This eliminates the need for a wire bond to connect the ESD chip, thus saving additional space.When using an NTC resistor, it sits directly on the semiconductor chip in an ideal position for determining the chip's temperature. With suitable rewiring, the NTC chip can also be positioned centrally on the back of the semiconductor chip, allowing for uniform heat dissipation laterally in all directions. The NTC chip is electrically and thermally connected to the back of the optoelectronic semiconductor chip (e.g., the cathode of an LED) and is preferably soldered to the substrate's metallization. This eliminates the need for the wire bond typically used for contacting the chip, thus saving additional space.

[0086] The invention has been illustrated and described in more detail with reference to preferred embodiments. However, the invention is not limited to the disclosed examples. Rather, other variations can be derived from them by a person skilled in the art without departing from the scope of protection of the invention.

[0087] REFERENCE MARK LIST

[0088] 100 optoelectronic components

[0089] 101, 102 emitted light radiation

[0090] 110 carriers

[0091] 111 Top of the carrier

[0092] 112 Underside of the carrier

[0093] 113 electrical conductor structures on the top of the support

[0094] 114 electrical conductor structures on the underside of the support

[0095] 115 Bridge

[0096] 117 Through-hole plating structure

[0097] 118 Bond wire

[0098] 119 Lot

[0099] 120 Recess in the top of the carrier

[0100] 130 optoelectronic semiconductor chip

[0101] 131 Top side of the optoelectronic semiconductor chip

[0102] 132 Underside of the optoelectronic semiconductor chip

[0103] 133 Electrical connection structure on the top side of the optoelectronic semiconductor chip

[0104] 134 Electrical connection structure on the underside of the optoelectronic semiconductor chip

[0105] 140 additional chips

[0106] 141 Top side of the additional chip

[0107] 142 Underside of the additional chip

[0108] 143 Electrical connection structure on the top side of the add-on chip

[0109] 144 Electrical connection structure on the underside of the add-on chip

[0110] 150 conversion element

[0111] 160 cases

[0112] 170 potting compound

[0113] 200 optoelectronic device

[0114] 210 Base carrier of the optoelectronic device

[0115] 211 Top side of the base support

[0116] 213 electrical conductor structure on the top of the

[0117] Foundation

[0118] 214 electrical conductor structure within base frame

[0119] 215 rib-shaped structure 216 dividing trench on the top of the base support

Claims

PATENT CLAIMS 1. Optoelectronic component (100) comprising: - a support (110) with a recess (120) , - an optoelectronic semiconductor chip (130) , wherein the optoelectronic semiconductor chip (130) is mounted with a bottom side (132) on a top side (111) of the carrier (110) and at least partially covers the recess (120) of the carrier (110), and - an additional chip (140) associated with the optoelectronic semiconductor chip (130), wherein the additional chip (140) is arranged in the recess (120) of the carrier (110) and is mounted with a top side (141) directly on the bottom side (132) of the optoelectronic semiconductor chip (130).

2. Optoelectronic component (100) according to claim 1, wherein the optoelectronic semiconductor chip (130) completely overlaps the additional chip (140) laterally.

3. Optoelectronic component (100) according to claim 1 or 1, wherein the optoelectronic semiconductor chip (130) has one or more electrical connection structures (134) on a bottom surface (132), and wherein the optoelectronic semiconductor chip (130) is electrically connected via at least one of these electrical connection structures (134) to at least one electrical conductor structure (113) arranged on the top surface (111) of the carrier (110).

4. Optoelectronic component (100) according to one of claims 1 to 3, wherein the additional chip (140) has at least one electrical connection structure (143) on the top side (141) which is electrically connected to at least one electrical connection structure (134) on the bottom side (132) of the optoelectronic semiconductor chip (130).

5. Optoelectronic component (100) according to claim 2, wherein the recess (120) extends through the entire carrier (110), and wherein the additional chip (140) has at least one further electrical connection structure (144) on a bottom side (142).

6. Optoelectronic component (100) according to one of claims 1 to 4, wherein the recess (120) is formed in the form of a depression which does not completely penetrate the carrier (110), and wherein the additional chip (140) has at least two electrical connection structures (143) on the top side (141), which are each electrically connected to an electrical connection structure (134) arranged on the bottom side (132) of the optoelectronic semiconductor chip (130).

7. Optoelectronic component (100) according to one of the preceding claims, wherein the additional chip (140) is designed in the form of an ESD diode, an NTC resistor or an ASIC chip.

8. Optoelectronic component (100) according to one of the preceding claims, wherein the optoelectronic component (100) has at least two additional chips (140.1, 140.2) associated with the optoelectronic semiconductor chip (130), wherein the additional chips (140.1, 140.2) are each mounted on the underside (132) of the optoelectronic semiconductor chip (130).

9. Optoelectronic component (100) according to claim 8, wherein a first additional chip (140.1) is configured in the form of an ESD diode associated with the optoelectronic semiconductor chip (130), and wherein a second additional chip (140.2) is configured in the form of a is formed by an NTC resistor associated with the optoelectronic semiconductor chip (130).

10. Optoelectronic component (100) according to one of the preceding claims, wherein the carrier (110) is in the form of a lead frame, a printed circuit board, a ceramic carrier, a routable QFN carrier or a MIS carrier.

11. Optoelectronic component (100) according to one of the preceding claims, wherein the optoelectronic component (100) is designed in the form of an LED component.

12. Lighting device (200) comprising a base carrier (210) and at least one optoelectronic component (100) mounted on the base carrier (210), which is designed according to one of claims 1 to 11, wherein the optoelectronic component (100) has a carrier (110) with a recess (120), an optoelectronic semiconductor chip (130) mounted with a bottom surface (132) on a top surface (111) of the carrier (110) and at least partially covering the recess (120) of the carrier (110), and at least one additional chip (140) associated with the optoelectronic semiconductor chip (130), which is arranged in the recess (120) of the carrier (110) and has a top surface (141) directly on the bottom surface (132) of the optoelectronic semiconductor chip. (130) is mounted, comprising, wherein the optoelectronic component (100) is mounted with the underside (112) of the carrier (110) on a top side (211) of the base carrier (210), and wherein the optoelectronic component (100) is electrically connected with at least one electrical conductor structure (114) arranged on the underside (112) of the carrier (110) to an electrical conductor structure (213) arranged on the base carrier (210).

13. Lighting device (200) according to claim 12, wherein the recess (120) extends through the entire carrier (110), wherein the additional chip arranged in the recess (120) (140) is mounted with a bottom surface (142) on the base support (210).

14. Lighting device (200) according to one of claims 12 or 13, wherein the additional chip (140) on the underside (142) has at least one further electrical connection structure (144) which is electrically connected to at least one electrical conductor structure (213) arranged on the base carrier (210).

15. Lighting device (200) according to one of claims 12 to 14, wherein the additional chip (140) is in the form of an ESD diode, an NTC resistor or an ASIC chip.

16. Lighting device (200) according to one of claims 12 to 15, wherein the optoelectronic component (100) is designed in the form of an LED component.

Images