Imaging device and imaging method

Abstract

The present invention makes it possible to read a pixel signal of a read level corresponding to the illuminance incident on each pixel from each pixel while suppressing a decrease in frame rate.　This imaging device comprises: a pixel capable of generating pixel signals of a plurality of read levels; a determination circuit that determines the read level of the pixel signal in the pixel; and a switching circuit that switches the read level of the pixel signal on the basis of a determination result of the read level of the pixel signal. The pixel may be provided with a sample-and-hold circuit that samples and holds the pixel signal on the basis of a global shutter operation.

Description

Imaging device and imaging method

[0001] The present technology relates to an imaging device and an imaging method, and more particularly to an imaging device and an imaging method capable of switching pixel readout levels.

[0002] There is a technique for switching and reading out the conversion efficiency of pixels to expand the dynamic range of an imaging device. For example, a technique is disclosed in which a selection circuit is provided that connects one of a plurality of capacitance elements that holds a voltage output according to the conversion efficiency controlled by opening and closing a path between a floating diffusion layer and an additional capacitance to a subsequent node (see, for example, Patent Document 1).

[0003] WO 2023 / 62947

[0004] However, in the above-mentioned conventional technology, pixel signals at each conversion efficiency are read out from each pixel, which may result in a decrease in frame rate.

[0005] This technology was developed in light of these circumstances, and aims to enable pixel signals to be read from each pixel at a readout level that corresponds to the illuminance incident on each pixel while suppressing a decrease in frame rate.

[0006] The present technology has been made to solve the above-mentioned problems, and a first aspect thereof is an imaging device including a pixel capable of generating pixel signals of multiple readout levels, a determination circuit configured to determine the readout level of the pixel signal within the pixel, and a switching circuit configured to switch the readout level of the pixel signal based on a determination result of the readout level of the pixel signal. This provides an effect of realizing readout from the pixel according to the readout level of the pixel signal without performing readout for each readout level of the pixel signal.

[0007] In the first aspect, the pixel may generate pixel signals of the plurality of readout levels based on switching of conversion efficiency, thereby providing a single photoelectric conversion element within the pixel to provide an effect of switching the readout level of the pixel signal.

[0008] In addition, in the first aspect, the pixel may include a photoelectric conversion element, an amplifying transistor that amplifies the pixel signal, a floating diffusion connected to a gate of the amplifying transistor, a transfer transistor that transfers charge accumulated in the photoelectric conversion element to the floating diffusion, a selection transistor that selects an output of the pixel signal amplified by the amplifying transistor, and a switching transistor that switches a conversion efficiency of the amplifying transistor, thereby providing an effect that pixel signals of a plurality of readout levels are generated based on switching of the conversion efficiency.

[0009] In addition, in the first aspect, the switching circuit may switch the switching transistor on and off based on a result of determining the readout level of the pixel signal, thereby providing an effect that the conversion efficiency is switched based on the result of determining the readout level of the pixel signal.

[0010] In addition, in the first aspect, the pixel may include a horizontal overflow storage capacitor and a pass transistor that sets a path through which charge stored in the horizontal overflow storage capacitor is transferred to the floating diffusion, and the switching circuit may switch the switching transistor and the pass transistor on and off based on a determination result of a readout level of the pixel signal. This brings about an effect that switching between three stages of conversion efficiency is realized based on the determination result of the readout level of the pixel signal.

[0011] In addition, in the first aspect, the pixel may include a plurality of photoelectric conversion elements having different sensitivities, and the switching circuit may switch the photoelectric conversion elements used to generate the pixel signal based on a determination result of a readout level of the pixel signal. Thus, by providing a plurality of photoelectric conversion elements within the pixel, an effect is achieved in which the readout level of the pixel signal can be switched.

[0012] In addition, in the first aspect, the pixel may include a plurality of photoelectric conversion elements having different exposure times, and the switching circuit may switch the photoelectric conversion elements used to generate the pixel signal based on a determination result of a readout level of the pixel signal. This brings about an effect that the readout level of the pixel signal can be switched by providing a plurality of photoelectric conversion elements within the pixel.

[0013] In the first aspect, the pixel may include a photoelectric conversion element capable of switching an exposure time, and the switching circuit may switch the exposure time for exposure by the photoelectric conversion element based on a determination result of a readout level of the pixel signal. This brings about an effect that the readout level of the pixel signal can be switched by providing a single photoelectric conversion element within the pixel.

[0014] In the first aspect, the determination circuit may be shared by a plurality of pixels, thereby achieving a space-saving determination circuit and realizing readout from the pixels according to the readout level of the pixel signal.

[0015] In addition, in the first aspect, after the readout level of the pixel signal is switched based on a determination result of the readout level of the pixel signal, the pixel signal may be read out from the pixel based on a rolling shutter operation, thereby achieving readout from the pixel according to the readout level of the pixel signal without performing readout for each readout level of the pixel signal.

[0016] In the first aspect, the pixel may include a sample-and-hold circuit that samples and holds the pixel signal based on a global shutter operation, thereby achieving readout from the pixel according to the readout level of the pixel signal without sample-and-holding for each readout level of the pixel signal.

[0017] In addition, in the first aspect, the sample and hold circuit may include a first sample and hold capacitor that holds a charge corresponding to a P-phase level and a second sample and hold capacitor that holds a charge corresponding to a D-phase level, and the determination circuit may determine the readout level of the pixel signal between sampling of the P-phase level and sampling of the D-phase level in one frame period. This brings about the effect that readout from the pixel according to the D-phase level is realized without performing readout for each D-phase level.

[0018] In the first aspect, the determination circuit may be separated from the first sample-and-hold capacitor and the second sample-and-hold capacitor when determining the readout level of the pixel signal, thereby reducing the load on the readout of the pixel signal when determining the readout level of the pixel signal.

[0019] In addition, in the first aspect, the pixel switching circuit may include a first sample-and-hold transistor that sets the sampling timing of the P-phase level and a second sample-and-hold transistor that sets the sampling timing of the D-phase level, and the switching circuit may switch the second sample-and-hold transistor on and off based on a determination result of the readout level of the pixel signal. This brings about an effect that readout from the pixel according to the readout level of the pixel signal is realized without performing readout for each readout level of the pixel signal.

[0020] In the first aspect, a vertical signal line may be provided that is shared between reading out pixel signals from the pixels and reading out determination results of readout levels of the pixel signals, thereby providing the effect of reading out determination results of readout levels of pixel signals while suppressing an increase in the number of wirings.

[0021] In the first aspect, the pixel circuit may further include a vertical signal line used for reading out pixel signals from the pixels, and a readout line used for reading out determination results of readout levels of the pixel signals, thereby providing an effect that the determination results of the readout levels of the pixel signals are read out separately from the pixel signals.

[0022] A second aspect of the present invention is an imaging method including the steps of: generating a pixel signal within a pixel; determining a readout level of the pixel signal within the pixel; switching the readout level of the pixel signal based on a result of determining the readout level of the pixel signal; and reading out the pixel signal from the pixel based on a rolling shutter operation after the readout level of the pixel signal has been switched. This provides the effect of realizing readout from the pixel according to the readout level of the pixel signal without performing readout for each readout level of the pixel signal.

[0023] In the second aspect, the pixel signal may not be read from the pixel before the readout level of the pixel signal is determined, thereby achieving an effect of speeding up the readout of the pixel signal from the pixel according to the illuminance of incident light incident on the pixel.

[0024] A third aspect of the present invention is an imaging method including the steps of: generating a pixel signal within a pixel capable of sampling and holding the pixel signal; determining a readout level of the pixel signal within the pixel; switching the readout level of the pixel signal based on a result of determining the readout level of the pixel signal; sampling and holding the pixel signal based on a global shutter operation after the readout level of the pixel signal has been switched; and reading out the sampled and held pixel signals row by row. This provides the effect of realizing readout from pixels according to the readout level of the pixel signal without sample-and-holding the pixel signal for each readout level.

[0025] In the third aspect, the D-phase level of the pixel signal may not be sampled and held in the pixel before determining the readout level of the pixel signal, thereby achieving an effect of speeding up the readout of the pixel signal from the pixel according to the illuminance of incident light incident on the pixel.

[0026] 1 is a block diagram showing an example of the configuration of an imaging device according to a first embodiment. FIG. 2 is a block diagram showing an example of the configuration of a solid-state imaging device according to the first embodiment. FIG. 3 is a diagram showing a first example of the circuit configuration of a pixel provided in the solid-state imaging device according to the first embodiment. FIG. 4 is a flowchart showing a readout process of a pixel signal in the solid-state imaging device according to the first embodiment. FIG. 5 is a diagram showing the relationship between the readout level of a pixel signal and the amount of light in the solid-state imaging device according to the first embodiment. FIG. 6 is a timing chart showing an example of an operation period allocated to one frame of the solid-state imaging device according to the first embodiment. FIG. 7 is a timing chart showing an example of a waveform of each part at low illuminance in a global shutter operation of the first circuit configuration example of the pixel according to the first embodiment. FIG. 8 is a timing chart showing an example of a waveform of each part at high illuminance in a global shutter operation of the first circuit configuration example of the pixel according to the first embodiment. FIG. 9 is a timing chart showing an example of a waveform of each part at a readout operation of the first circuit configuration example of the pixel according to the first embodiment. FIG. 10 is a diagram showing a first example of the circuit configuration of a comparator according to the first embodiment. FIG. 11 is a diagram showing a second example of the circuit configuration of a comparator according to the first embodiment. FIG. 12 is a diagram showing the relationship between the voltage of each part and the amount of light in the second circuit configuration example of the comparator according to the first embodiment. FIG. 1 is a diagram showing an example of a circuit configuration subsequent to a comparator according to the first embodiment. FIG. 2 is a diagram showing a second example of a circuit configuration of a pixel provided in the solid-state imaging device according to the first embodiment. FIG. 3 is a timing chart showing an example of a waveform of each unit in a global shutter operation of the second example of a circuit configuration of the pixel according to the first embodiment. FIG. 4 is a diagram showing a fourth example of a circuit configuration of a pixel provided in the solid-state imaging device according to the first embodiment. FIG. 5 is a diagram showing an example of a circuit configuration of a pixel provided in the solid-state imaging device according to the second embodiment. FIG. 6 is a timing chart showing an example of a waveform of each unit during a pixel readout operation according to the second embodiment. FIG. 7 is a diagram showing an example of a circuit configuration of a pixel provided in the solid-state imaging device according to the third embodiment. FIG. 8 is a flowchart showing a pixel signal readout process of the solid-state imaging device according to the third embodiment.10 is a timing chart showing an example of a waveform of each part at low illuminance in a rolling shutter operation of a pixel according to a third embodiment. FIG. 11 is a timing chart showing an example of a waveform of each part at high illuminance in a rolling shutter operation of a pixel according to the third embodiment. FIG. 12 is a diagram showing an example of a circuit configuration of a pixel provided in a solid-state imaging device according to a fourth embodiment. FIG. 13 is a flowchart showing a readout process of a pixel signal of a solid-state imaging device according to the fourth embodiment. FIG. 14 is a timing chart showing an example of a waveform of each part at low illuminance in a global shutter operation of a pixel according to the fourth embodiment. FIG. 15 is a timing chart showing an example of a waveform of each part at medium illuminance in a global shutter operation of a pixel according to the fourth embodiment. FIG. 16 is a timing chart showing an example of a waveform of each part at high illuminance in a global shutter operation of a pixel according to the fourth embodiment. FIG. 17 is a diagram showing a first example of a circuit configuration of a pixel provided in a solid-state imaging device according to a fifth embodiment. FIG. 18 is a diagram showing a second example of a circuit configuration of a pixel provided in a solid-state imaging device according to the fifth embodiment. FIG. 19 is a diagram showing a third example of a circuit configuration of a pixel provided in a solid-state imaging device according to the fifth embodiment. FIG. 19 is a diagram showing a fourth example of a circuit configuration of a pixel provided in a solid-state imaging device according to the fifth embodiment. 10 is a diagram showing a fifth example of a circuit configuration of a pixel provided in a solid-state imaging device according to a fifth embodiment. FIG. 11 is a diagram showing a sixth example of a circuit configuration of a pixel provided in a solid-state imaging device according to the fifth embodiment. FIG. 12 is a diagram showing an example of a circuit configuration of a pixel provided in a solid-state imaging device according to the sixth embodiment. FIG. 13 is a flowchart showing a readout process of a pixel signal of the solid-state imaging device according to the sixth embodiment. FIG. 14 is a timing chart showing an example of an operation period allocated to one frame of the solid-state imaging device according to the sixth embodiment. FIG. 15 is a timing chart showing an example of a waveform of each part at low illuminance in a global shutter operation of the first example of a circuit configuration of a pixel according to the sixth embodiment. FIG. 16 is a timing chart showing an example of a waveform of each part at high illuminance in a global shutter operation of the first example of a circuit configuration of a pixel according to the sixth embodiment. FIG. 17 is a diagram showing an example of a circuit configuration of a pixel provided in a solid-state imaging device according to a seventh embodiment. FIG. 18 is a flowchart showing a readout process of a pixel signal of the solid-state imaging device according to the seventh embodiment.13 is a timing chart showing an example of a waveform of each part at low illuminance in the global shutter operation of the pixel according to the seventh embodiment. FIG. 14 is a timing chart showing an example of a waveform of each part at high illuminance in the global shutter operation of the pixel according to the seventh embodiment. FIG. 15 is a diagram showing an example of a circuit configuration of a pixel provided in a solid-state imaging device according to the eighth embodiment. FIG. 16 is a flowchart showing a readout process of a pixel signal of the solid-state imaging device according to the eighth embodiment. FIG. 17 is a timing chart showing an example of a waveform of each part at low illuminance in the global shutter operation of the pixel according to the eighth embodiment. FIG. 18 is a timing chart showing an example of a waveform of each part at high illuminance in the global shutter operation of the pixel according to the eighth embodiment. FIG. 19 is a diagram showing an example of a circuit configuration of a pixel provided in a solid-state imaging device according to the ninth embodiment. FIG. 19 is a flowchart showing a readout process of a pixel signal of the solid-state imaging device according to the ninth embodiment. FIG. 19 is a timing chart showing an example of an operation period allocated to one frame of the solid-state imaging device according to the ninth embodiment. FIG. 19 is a timing chart showing an example of a waveform of each part at low illuminance in the global shutter operation of the pixel of the first circuit configuration example according to the ninth embodiment. 13 is a timing chart showing an example of waveforms of each part at high illuminance in global shutter operation of a first circuit configuration example of a pixel according to a ninth embodiment. FIG. 14 is a perspective view showing a first stacking example of a solid-state imaging device according to a tenth embodiment. FIG. 15 is a diagram showing division positions of pixels in the first stacking example of a solid-state imaging device according to the tenth embodiment. FIG. 16 is a perspective view showing a second stacking example of a solid-state imaging device according to the tenth embodiment. FIG. 17 is a diagram showing division positions of pixels in the second stacking example of a solid-state imaging device according to the tenth embodiment. FIG. 18 is a block diagram showing a schematic configuration example of a vehicle control system. FIG. 19 is an explanatory diagram showing an example of an installation position of an imaging unit.

[0027] Hereinafter, modes for implementing the present technology (hereinafter referred to as embodiments) will be described. The descriptions will be made in the following order. 1. First Embodiment (an example in which a pixel is provided with a determination circuit that determines the readout level of a pixel signal that can be sampled and held based on a global shutter operation and a switching circuit that switches the readout level of the pixel signal) 2. Second Embodiment (an example in which a pixel is provided with a determination circuit that determines the readout level of a pixel signal that can be sampled and held based on a global shutter operation and a switching circuit that switches the conversion efficiency when the pixel signal is generated, and a readout line that outputs the determination result from the pixel) 3. Third Embodiment (an example in which a pixel is provided with a determination circuit that determines the readout level of a pixel signal that is read out based on a rolling shutter operation and a switching circuit that switches the conversion efficiency when the pixel signal is generated, and a readout line that outputs the determination result from the pixel) 4. Fourth Embodiment (an example in which a pixel is provided with a determination circuit that determines the conversion efficiency of a pixel signal that can be sampled and held over three levels based on a global shutter operation and a switching circuit that switches the readout level of the pixel signal) 5. 5. Fifth Embodiment (an example in which a determination circuit that determines the read level of a pixel signal that can be sampled and held based on a global shutter operation is shared by a plurality of pixels) 6. Sixth Embodiment (an example in which a pixel is provided with a determination circuit that determines the read level of a pixel signal that can be sampled and held based on a global shutter operation and a switching circuit that switches the D-phase level to be sampled and held) 7. Seventh Embodiment (an example in which a pixel is provided with a determination circuit that determines the read level of a pixel signal that can be sampled and held based on a global shutter operation and a switching circuit that switches between a high-sensitivity photodiode and a low-sensitivity photodiode used to generate pixel signals) 8. Eighth Embodiment (an example in which a pixel is provided with a determination circuit that determines the read level of a pixel signal that can be sampled and held based on a global shutter operation and a switching circuit that switches between a long-time exposure unit and a short-time exposure unit) 9. Ninth Embodiment (an example in which a pixel is provided with a determination circuit that determines the read level of a pixel signal that can be sampled and held based on a global shutter operation and a switching circuit that switches the exposure time of a photodiode) 10. Tenth Embodiment (an example in which pixel array units are stacked) 11. Application to a Moving Body

[0028] 1. First Embodiment FIG. 1 is a block diagram showing an example of the configuration of an imaging device according to a first embodiment.

[0029] In the figure, the imaging device 100 includes an optical system 101, a solid-state imaging device 102, an imaging control unit 103, an image processing unit 104, a storage unit 105, a display unit 106, and an operation unit 107. The imaging control unit 103, the image processing unit 104, the storage unit 105, the display unit 106, and the operation unit 107 are connected to one another via a bus 108. The imaging device 100 may be used as a standalone device, or may be incorporated into a mobile terminal such as a smartphone, an authentication device, a monitoring device, a vehicle, or a drone.

[0030] The optical system 101 causes light from a subject to be incident on the solid-state imaging device 102, and forms an optical image on the light-receiving surface of the solid-state imaging device 102. The optical system 101 may include, for example, a focus lens, a zoom lens, and an aperture. The optical system 101 may also include multiple lenses, such as a wide-angle lens, a standard lens, and a telephoto lens.

[0031] The solid-state imaging device 102 converts an optical image formed on the light-receiving surface into an electrical signal for each pixel, digitizes the electrical signal, and outputs it. At this time, the solid-state imaging device 102 can output pixel signals at multiple readout levels according to the illuminance of incident light. The solid-state imaging device 102 is, for example, a CMOS (Complementary Metal Oxide Semiconductor) image sensor. The CMOS image sensor may be a back-illuminated image sensor or a front-illuminated image sensor.

[0032] The imaging control unit 103 controls imaging by the solid-state imaging device 102 based on instructions from the operation unit 107. At this time, the imaging control unit 103 can control the exposure time, exposure amount, imaging timing, etc. of the solid-state imaging device 102.

[0033] The image processing unit 104 performs image processing based on the output from the solid-state imaging device 102. The image processing includes, for example, gamma correction, white balance processing, sharpness processing, and gradation conversion processing. The image processing unit 104 may include a processor that executes processing based on software. The image processing unit 104 can also combine pixel signals having different readout levels output from the solid-state imaging device 102 to generate a high dynamic range (HDR) image.

[0034] The storage unit 105 stores images captured by the solid-state imaging device 102 and stores imaging parameters of the solid-state imaging device 102. The storage unit 105 can also store a program that operates the imaging device 100 based on software. The storage unit 105 may include a read-only memory (ROM), a random access memory (RAM), and a memory card.

[0035] The display unit 106 displays captured images and various information that supports the image capturing operation. The display unit 106 may be a liquid crystal display, an organic EL (Electro Luminescence) display, or a micro LED display.

[0036] The operation unit 107 provides a user interface for operating the imaging device 100. The operation unit 107 may include, for example, buttons, dials, and switches provided on the imaging device 100. The operation unit 107 may be configured as a touch panel together with the display unit 106.

[0037] Depending on the configuration of the imaging device 100, some of the above functions may not be present, or conversely, the imaging device 100 may further include functions that are not disclosed.

[0038] FIG. 2 is a block diagram showing an example of the configuration of the solid-state imaging device according to the first embodiment.

[0039] In the figure, the solid-state imaging device 102 includes a pixel array section 111, a vertical scanning circuit 112, a column readout circuit 113, a column signal processing section 114, a horizontal scanning circuit 115, and a control circuit 116.

[0040] The pixel array unit 111 includes a plurality of pixels PIX. These pixels PIX are arranged in a matrix along the row direction (also referred to as the horizontal direction) and the column direction (also referred to as the vertical direction). Each pixel PIX can generate pixel signals at a plurality of readout levels. Each pixel PIX may generate a plurality of readout levels based on switching of conversion efficiency, sensitivity, or exposure time. Each pixel PIX may include a capacitor that accumulates charge overflowing from a photodiode. This capacitor may be a lateral overflow accumulation capacitor. In this case, each pixel PIX may constitute a lateral overflow integration capacitor (LOFIC) pixel. Each pixel PIX may include a plurality of photodiodes with different sensitivities. Each pixel PIX may include a sample-and-hold circuit that samples and holds charge transferred from the photodiode. Each pixel PIX may read out a pixel signal based on a rolling shutter operation or a global shutter operation. Each pixel PIX can form a source follower with the column readout circuit 113 when reading out a signal.

[0041] Each pixel PIX is connected to a horizontal drive line 118 for each row and to a vertical signal line 117 for each column. The horizontal drive line 118 drives each pixel PIX for each row when reading out a signal from each pixel 120. The vertical signal line 117 transmits a potential based on a current that flows when reading out a signal from each pixel PIX to the column signal processing unit 114 for each column.

[0042] The pixels PIX may be arranged in a Bayer array or a quad-Bayer array. The light received by each pixel PIX may be visible light, near infrared light (NIR), short wavelength infrared light (SWIR), ultraviolet light, X-rays, or the like.

[0043] The vertical scanning circuit 112 scans the pixels PIX to be read in the column direction. The vertical scanning circuit 112 may be configured using vertical registers. The vertical scanning circuit 112 may also include a decoder that specifies the pixels PIX to be read.

[0044] The column readout circuit 113 can form a source follower with each pixel PIX when reading out a signal from the pixel PIX. At this time, the column readout circuit 113 can change the potential of each vertical signal line 117 based on the charge held in each pixel PIX.

[0045] The column signal processing unit 114 processes signals transmitted in the column direction from each pixel PIX. For example, the column signal processing unit 114 can perform correlated double sampling (CDS) processing based on the signals transmitted in the column direction from each pixel PIX. The column signal processing unit 114 can also perform analog-to-digital (AD) conversion processing based on the signals transmitted in the column direction from each pixel PIX, and output an image pickup signal Gout.

[0046] The column signal processing unit 114 includes a column ADC unit 114A. The column ADC unit 114A can perform AD conversion processing in parallel for each column. At this time, the column ADC unit 114A can perform AD conversion for each column based on the result of comparing the pixel signal read from each pixel PIX with a reference signal.

[0047] The horizontal scanning circuit 115 scans the pixels PIX to be read in the row direction. The horizontal scanning circuit 115 may be configured using a horizontal register.

[0048] The control circuit 116 controls the vertical scanning circuit 112, the column readout circuit 113, the column signal processing unit 114, and the horizontal scanning circuit 115. For example, the control circuit 116 can control the scanning timing in the column direction, the scanning timing in the row direction, the operation timing of the column readout circuit 113, and the processing timing of the column signal processing unit 114. At this time, the control circuit 116 can coordinate the vertical scanning circuit 112, the column readout circuit 113, the column signal processing unit 114, and the horizontal scanning circuit 115 so that the accumulation operation, the shutter operation, and the read operation are performed for each row in each frame.

[0049] FIG. 3 is a diagram showing a first example of a circuit configuration of a pixel provided in the solid-state imaging device according to the first embodiment.

[0050] In the figure, the pixel PIX can sample and hold a pixel signal based on a global shutter operation and output the sampled and held pixel signal. The pixel PIX switches the readout level V1 of the pixel signal within the pixel PIX based on the determination result of the readout level V1 of the pixel signal. The pixel PIX can generate pixel signals at multiple readout levels V1. At this time, the pixel PIX can prevent the pixel signal from being output from the pixel PIX before determining the readout level V1 of the pixel signal. Furthermore, in the global shutter operation, the pixel PIX can prevent the D-phase level of the pixel signal from being sampled and held in the pixel PIX before determining the readout level of the pixel signal. The pixel signal read out from the pixel PIX is transmitted to an ADC (Analog to Digital Converter) 135 via a vertical signal line 117. The ADC 135 performs A / D conversion of the pixel signal read out from the pixel PIX. An ADC 135 can be provided for each column.

[0051] The pixel PIX includes a photodiode PD, a transfer transistor 122, reset transistors 123 and 126, a switching transistor 124, amplification transistors 125 and 127, a selection transistor 128, and floating diffusions FD1 and FD2. The pixel PIX further includes a sample-and-hold circuit SH, a decision value readout transistor 129, current sources 130 and 134, a comparator 131, a latch circuit 132, and a selector 133. The sample-and-hold circuit SH includes sample-and-hold capacitors C1 and C2 and sample-and-hold transistors ST1 and ST2.

[0052] The transfer transistor 122, the reset transistor 123, the switching transistor 124, the amplifying transistors 125 and 127, the selection transistor 128, the decision value readout transistor 129, and the sample-and-hold transistors ST1 and ST2 may be MOS (Metal Oxide Semiconductor) transistors.

[0053] The photodiode PD performs photoelectric conversion and accumulates the photoelectrically converted charge. The transfer transistor 122 transfers the charge accumulated in the photodiode PD to the floating diffusion FD1. The reset transistor 123 resets the photodiode PD and the floating diffusion FD1. The switching transistor 124 switches the conversion efficiency of the amplification transistor 125. The amplification transistor 125 outputs a signal corresponding to the potential of the floating diffusion FD1. The reset transistor 126 resets the floating diffusion FD2. The amplification transistor 127 outputs a signal corresponding to the potential of the floating diffusion FD2. The selection transistor 128 selects the output of the amplification transistor 127. The judgment value read transistor 129 sets the read timing of the judgment result VCO of the read level V1. At this time, the pixel PIX can output the judgment result VCO of the read level V1 to the vertical signal line 117.

[0054] The sample and hold circuit SH samples and holds the pixel signal output from the amplification transistor 125. At this time, the sample and hold circuit SH can sample and hold the pixel signal based on the global shutter operation. The sample and hold capacitor C1 samples and holds the P-phase level (also called the reset level) output from the amplification transistor 125. The sample and hold capacitor C2 samples and holds the D-phase level (also called the signal level) output from the amplification transistor 125. The sample and hold transistor ST1 sets the sampling timing of the P-phase level output from the amplification transistor 125. The sample and hold transistor ST2 sets the sampling timing of the D-phase level output from the amplification transistor 125.

[0055] The current source 130 forms a source follower with the amplifying transistor 125. The current source 134 forms a source follower with the amplifying transistor 127. The decision value read transistor 129 sets the read timing of the decision result VCO latched in the latch circuit 132.

[0056] The comparator 131 determines the readout level V1 of the pixel signal output from the amplification transistor 125 within the pixel PIX. At this time, the comparator 131 compares the readout level V1 of the pixel signal with a reference voltage VRF. If the readout level V1 of the pixel signal is less than the reference voltage VRF, the comparator 131 can determine that the illuminance of the incident light entering the pixel PIX is high. If the illuminance of the incident light entering the pixel PIX is high, the comparator 131 can set the determination result VCO of the readout level of the pixel signal to a high level. On the other hand, if the readout level V1 of the pixel signal is equal to or greater than the reference voltage VRF, the comparator 131 can determine that the illuminance of the incident light entering the pixel PIX is low. If the illuminance of the incident light entering the pixel PIX is low, the comparator 131 can set the determination result VCO of the readout level of the pixel signal to a low level. At this time, the comparator 131 may be separated from the sample-and-hold circuit SH when determining the readout level V1 of the pixel signal. The comparator 131 is an example of a determination circuit described in the claims.

[0057] The latch circuit 132 latches the determination result VCO of the read level V1 of the pixel signal output from the amplifying transistor 125. The comparator 131 and the latch circuit 132 are activated based on an activation signal CM.

[0058] The selector 133 switches the readout level V1 of the pixel signal output from the amplification transistor 125. At this time, the selector 133 can switch between the determination result VCO of the readout level V1 of the pixel signal and the switching signal FDGi based on the switching signal FEL. The switching signal FDGi can be set to a high level when the floating diffusion FD1 is reset, and can turn on the switching transistor 124. As a result, by turning on the reset transistor 123 when the floating diffusion FD1 is reset, the floating diffusion FD1 can be connected to the power supply potential VDD via the reset transistor 123 and the switching transistor 124. Note that the selector 133 is an example of a switching circuit as defined in the claims.

[0059] The transfer transistor 122 is connected between the cathode of the photodiode PD and the floating diffusion FD1. The reset transistor 123 is connected between the power supply potential VDD and the switching transistor 124. The switching transistor 124 is connected between the reset transistor 123 and the floating diffusion FD1. A capacitance C0 is connected between the power supply potential VDD and the connection point between the reset transistor 123 and the switching transistor 124. The capacitance C0 can be used to set the conversion efficiency of the amplification transistor 125. The amplification transistor 127 and the selection transistor 128 are connected in series. The drain of the amplification transistor 127 is connected to the power supply potential VDD. The gate of the amplification transistor 127 is connected to the floating diffusion FD2. The source of the selection transistor 128 is connected to the vertical signal line 117. The reset transistor 126 is connected between the floating diffusion FD2 and the power supply potential VDD. The sample and hold circuit SH is connected between the source of the amplification transistor 125 and the floating diffusion FD2. The decision value read transistor 129 is connected between the output of the latch circuit 132 and the floating diffusion FD2. The sample and hold capacitor C1 and the sample and hold transistor ST1 are connected in series. The sample and hold capacitor C2 and the sample and hold transistor ST2 are connected in series. These series circuits are connected in parallel between the source of the amplification transistor 125 and the floating diffusion FD2.

[0060] A transfer signal TRG is applied to the gate of the transfer transistor 122. A reset signal RST is applied to the gate of the reset transistor 123. A switching signal FDG is applied to the gate of the switching transistor 124. A reset signal RB is applied to the gate of the reset transistor 126. A selection signal SEL is applied to the gate of the selection transistor 128. A sample and hold signal SR is applied to the gate of the sample and hold transistor ST1. A sample and hold signal SD is applied to the gate of the sample and hold transistor ST2. A decision value readout signal SB is applied to the gate of the decision value readout transistor 129. The transfer signal TRG, reset signals RST, RB, selection signal SEL, switching signal FDGi, and sample and hold signals SR, SD can be transmitted to the pixel PIX via the horizontal drive line 118 in FIG. 2.

[0061] FIG. 4 is a flowchart showing a pixel signal readout process of the solid-state imaging device according to the first embodiment.

[0062] In the figure, the reset transistor 123 and the switching transistor 124 are turned on, and the floating diffusion FD1 is reset (step S101).

[0063] Next, the sample-and-hold transistor ST1 is turned on, and the P-phase level output from the amplifying transistor 125 is sampled by the sample-and-hold capacitor C1 (step S102).

[0064] Next, the transfer transistor 122 is turned on, and the charge accumulated in the photodiode PD is transferred to the floating diffusion FD1 (step S103).

[0065] Next, the comparator 131 determines the illuminance based on the readout level V1 of the pixel signal output from the amplifier transistor 125 (step S104). The illuminance determination can be performed with the switching transistor 124 turned off and high conversion efficiency maintained. If the illuminance is high, the switching transistor 124 is turned on to switch to low conversion efficiency (step S105). Then, the sample-and-hold transistor ST2 is turned on, and the D-phase level output from the amplifier transistor 125 at low conversion efficiency is sampled by the sample-and-hold capacitor C2 (step S106).

[0066] On the other hand, when the illuminance is low, the switching transistor 124 is turned off to maintain high conversion efficiency. Then, the sample-and-hold transistor ST2 is turned on, and the D-phase level output from the amplification transistor 125 with high conversion efficiency is sampled by the sample-and-hold capacitor C2 (step S106).

[0067] 5 is a diagram showing the relationship between the readout level of a pixel signal and the amount of light in the solid-state imaging device according to the first embodiment. In the diagram, a shows the relationship between the sensor output and the amount of light, b shows the relationship between the HDR (High Dynamic Range) image synthesis output and the amount of light, and c shows the relationship between the SNR and the amount of light. The sensor output indicates a digital output obtained by AD-converting a pixel signal read from pixel PIX in a column signal processing unit.

[0068] In the figure, a comparator 131 compares the HCG (High Conversion Gain) output with a decision threshold STH. The decision threshold STH can be set based on a reference voltage VRF. When the HCG output reaches the decision threshold STH, a selector 133 switches to the LCG (Low Conversion Gain) output. The decision threshold STH can be set lower than a saturation level SAL.

[0069] In the diagram, at b, the HCG output is adopted when the output is less than the decision threshold STH, and the LCG output is adopted when the output is equal to or greater than the decision threshold STH. By combining the HCG output and the LCG output, the dynamic range can be improved by the conversion efficiency ratio compared to when only the LCG output or the HCG output is used.

[0070] In Fig. 10C, the HCG output is used when the signal is less than the threshold STH, and the LCG output is used when the signal is equal to or greater than the threshold STH, and the HCG output and the LCG output are combined. This makes it possible to improve the dynamic range while suppressing a decrease in SNR.

[0071] FIG. 6 is a timing chart showing an example of an operation period assigned to one frame of the solid-state imaging device according to the first embodiment.

[0072] In the figure, one frame is assigned a global shutter period GS and a readout period RD. During the global shutter period GS, a global shutter operation is simultaneously performed for all pixels PIX arranged in the pixel array section 111. During the global shutter operation, P-phase sampling, illuminance determination, and D-phase sampling are simultaneously performed for each pixel PIX arranged in the pixel array section 111. During D-phase sampling, based on the illuminance determination result for each pixel PIX, only one of the HCG output and the LCG output is D-phase sampled individually for each pixel PIX. Here, only one of the HCG output and the LCG output according to the illuminance determination result for each pixel PIX can be D-phase sampled for each pixel PIX. This eliminates the need to D-phase sample both the HCG output and the LCG output for each pixel PIX, thereby shortening the global shutter period GS.

[0073] During the readout period RD, P-phase readout and D-phase readout are performed for each row of the pixels PIX arranged in the pixel array section 111. Here, during the P-phase readout and D-phase readout, only one of the HCG output and the LCG output corresponding to the illuminance determination result of each pixel PIX needs to be read from each pixel PIX, and there is no need to read both the HCG output and the LCG output from each pixel PIX, thereby shortening the readout period RD. In this case, when the illuminance determination is performed within the pixel PIX, the readout period RD with conversion efficiency switching can be made equal to the readout period RD without conversion efficiency switching. On the other hand, when the illuminance determination is performed outside the pixel PIX, the readout period RD with conversion efficiency switching is twice the readout period RD without conversion efficiency switching.

[0074] FIG. 7 is a timing chart showing an example of waveforms at various parts during low illuminance in the global shutter operation of the first circuit configuration example of the pixel according to the first embodiment.

[0075] In the figure, the global shutter operation includes a PD reset period P11, an exposure period P12, an FD reset period P13, a P-phase sampling period P14, a charge transfer period P15, an illuminance determination period P16, a conversion efficiency switching period P17, and a D-phase sampling period P18.

[0076] During the PD reset period P11, the reset signal RB, sample-and-hold signals SR and SD, active signal CM, and switching signal FEL are set to low levels. At this time, the reset transistor 126 and sample-and-hold transistors ST1 and ST2 are turned off, the comparator 131 and latch circuit 132 are inactivated, and the selector 133 selects the switching signal FDGi. Then, the transfer signal TRG, reset signal RST, and switching signal FDG rise, turning on the transfer transistor 122, reset transistor 123, and switching transistor 124. At this time, the conversion efficiency of the amplification transistor 125 is set to low, and the charges in the photodiode PD and floating diffusion FD1 are reset.

[0077] During the exposure period P12, the transfer signal TRG, the reset signal RST, and the switching signal FDG fall, turning off the transfer transistor 122, the reset transistor 123, and the switching transistor 124. At this time, the conversion efficiency of the amplification transistor 125 is set to high conversion efficiency, and charge is accumulated in the photodiode PD according to the amount of incident light.

[0078] In the FD reset period P13, the reset signal RST and the switching signal FDG rise, turning on the reset transistor 123 and the switching transistor 124. At this time, the conversion efficiency of the amplification transistor 125 is set to low, and the charge of the floating diffusion FD1 is reset.

[0079] During the P-phase sampling period P14, the reset signal RB and the sample-and-hold signal SR rise, turning on the reset transistor 126 and the sample-and-hold transistor ST1. At this time, a charge corresponding to the P-phase level output from the amplifier transistor 125 is held in the sample-and-hold capacitor C1.

[0080] During the charge transfer period P15, the transfer signal TRG rises, turning on the transfer transistor 122. At this time, the charge accumulated in the photodiode PD is transferred to the floating diffusion FD1. A voltage corresponding to the charge transferred to the floating diffusion FD1 is then applied to the gate of the amplification transistor 125. Then, based on the source follower operation between the amplification transistor 125 and the current source 130, a read level V1 corresponding to the voltage applied to the gate of the amplification transistor 125 is input to the comparator 131.

[0081] In an illuminance determination period P16, an active signal CM rises, and the comparator 131 and the latch circuit 132 are activated. Then, the comparator 131 compares the read level V1 of the pixel signal with a reference voltage VRF, and the determination result VCO of the read level V1 is latched in the latch circuit 132. At low illuminance, the read level V1 of the pixel signal becomes equal to or higher than the reference voltage VRF, and the determination result VCO is set to a low level.

[0082] During the conversion efficiency switching period P17, the switching signal FEL rises. At this time, the selector 133 selects the determination result VCO latched in the latch circuit 132 as the switching signal FDG and applies it to the gate of the switching transistor 124. Here, during low illuminance, the determination result VCO is set to a low level. Therefore, the switching signal FDG remains at a low level, and the switching transistor 124 is turned off. Therefore, the conversion efficiency of the amplification transistor 125 is set to a high conversion efficiency, and the readout level V1 of the pixel signal is set to the HCG output.

[0083] In the D-phase sampling period P18, the reset signal RB and the sample-and-hold signal SD rise, turning on the reset transistor 126 and the sample-and-hold transistor ST2. At this time, a charge corresponding to the high-conversion-efficiency D-phase level (HCG output) output from the amplifier transistor 125 is held in the sample-and-hold capacitor C2.

[0084] FIG. 8 is a timing chart showing an example of waveforms at various parts during high illuminance in the global shutter operation of the first circuit configuration example of the pixel according to the first embodiment.

[0085] In the figure, the operations during the PD reset period P11, exposure period P12, FD reset period P13, P-phase sampling period P14 and charge transfer period P15 at high illuminance are the same as those at low illuminance.

[0086] In an illuminance determination period P16, an active signal CM rises, and the comparator 131 and the latch circuit 132 are activated. Then, the comparator 131 compares the read level V1 of the pixel signal with a reference voltage VRF, and the determination result VCO of the read level V1 is latched in the latch circuit 132. At high illuminance, the read level V1 of the pixel signal becomes less than the reference voltage VRF, and the determination result VCO is set to a high level.

[0087] During the conversion efficiency switching period P17, the switching signal FEL rises. At this time, the selector 133 selects the determination result VCO latched in the latch circuit 132 as the switching signal FDG and applies it to the gate of the switching transistor 124. At this time, under high illuminance, the determination result VCO is set to a high level. Therefore, the switching signal FDG rises and the switching transistor 124 is turned on. Therefore, the conversion efficiency of the amplification transistor 125 is set to a low conversion efficiency, and the readout level V1 of the pixel signal is set to the LCG output.

[0088] In the D-phase sampling period P18, the reset signal RB and the sample-and-hold signal SD rise, turning on the reset transistor 126 and the sample-and-hold transistor ST2. At this time, a charge corresponding to the D-phase level (LCG output) with low conversion efficiency output from the amplifier transistor 125 is held in the sample-and-hold capacitor C2.

[0089] FIG. 9 is a timing chart showing an example of waveforms at various parts during a readout operation of the first circuit configuration example of the pixel according to the first embodiment.

[0090] In the figure, this read operation is provided with a P-phase read period P21, a D-phase read period P22, and a determination result read period P23.

[0091] During the P-phase readout period P21, the reset signal RST, the switching signal FDG, and the selection signal SEL are set to a high level. At this time, the reset transistor 123, the switching transistor 124, and the selection transistor 128 are turned on. The sample and hold signal SD, the reset signal RB, the decision value readout signal SB, and the switching signal FEL are set to a low level. At this time, the sample and hold transistor ST2, the reset transistor 126, and the decision value readout transistor 129 are turned off, and the switching signal FDGi is selected by the selector 133. Then, the sample and hold signal SR rises, turning on the sample and hold transistor ST1. At this time, the charge held in the sample and hold capacitor C1 is transferred to the floating diffusion FD2. A voltage corresponding to the charge transferred to the floating diffusion FD2 is applied to the gate of the amplification transistor 127. Then, based on the source follower operation between the amplifier transistor 127 and the current source 134, the potential VSL of the vertical signal line 117 is set in accordance with the P-phase level applied to the gate of the amplifier transistor 127, and is input to the ADC 135. Thereafter, the sample and hold signal SR falls, and the sample and hold transistor ST1 is turned off.

[0092] After the P-phase read period P21, the reset signal RB rises, turning on the reset transistor 126. At this time, the floating diffusion FD2 is reset. After that, the set signal RB falls, turning off the reset transistor 126.

[0093] During the D-phase readout period P22, the sample and hold signal SD rises, turning on the sample and hold transistor ST2. At this time, the charge held in the sample and hold capacitor C2 is transferred to the floating diffusion FD2. A voltage corresponding to the charge transferred to the floating diffusion FD2 is then applied to the gate of the amplifier transistor 127. Then, based on the source follower operation between the amplifier transistor 127 and the current source 134, the potential VSL of the vertical signal line 117 is set according to the D-phase level applied to the gate of the amplifier transistor 127, and input to the ADC 135. Thereafter, the sample and hold signal SD falls, turning off the sample and hold transistor ST2.

[0094] During the judgment result read period P23, the judgment value read signal SB rises, turning on the judgment value read transistor 129. At this time, charge corresponding to the judgment result VCO is transferred to the floating diffusion FD2. A voltage corresponding to the charge transferred to the floating diffusion FD2 is then applied to the gate of the amplification transistor 127. Then, based on the source follower operation between the amplification transistor 127 and the current source 134, the potential VSL of the vertical signal line 117 is set according to the judgment voltage applied to the gate of the amplification transistor 127, and input to the ADC 135. Thereafter, the judgment value read signal SB falls, turning off the judgment value read transistor 129.

[0095] After the determination result read period P23, the reset signal RST, the switching signal FDG, and the selection signal SEL fall, and the reset transistor 123, the switching transistor 124, and the selection transistor 128 are turned off.

[0096] FIG. 10 is a diagram illustrating a first example of a circuit configuration of a comparator according to the first embodiment.

[0097] In the figure, a comparator 131 can compare a read level V1 of a pixel signal with a reference voltage VRF based on a differential input. At this time, the comparator 131 outputs a voltage corresponding to the difference between the read level V1 of the pixel signal and the reference voltage VRF. The comparator 131 includes PMOS transistors 141, 142, and 145, NMOS transistors 143 and 144, and current sources 146 and 147.

[0098] The PMOS transistor 141 and the NMOS transistor 143 are connected in series to each other. The PMOS transistor 142 and the NMOS transistor 144 are connected in series to each other. The sources of the PMOS transistors 141 and 142 are connected to the power supply potential VDD, and the gates of the PMOS transistors 141 and 142 are connected to the drain of the PMOS transistor 141. In this case, the PMOS transistors 141 and 142 can form a current mirror.

[0099] A pixel signal read level V1 is input to the gate of NMOS transistor 143. A reference voltage VRF is input to the gate of NMOS transistor 144. The sources of NMOS transistors 143 and 144 are connected to the ground potential via current source 146. The drain of NMOS transistor 144 is connected to the gate of PMOS transistor 145. The source of PMOS transistor 145 is connected to power supply potential VDD. The drain of PMOS transistor 145 is connected to the ground potential via current source 147.

[0100] The latch circuit 132 includes an NMOS transistor 151 and a capacitor 152. The drain of the NMOS transistor 151 is connected to the drain of the PMOS transistor 145. The capacitor 152 is connected between the source of the NMOS transistor 151 and the ground potential.

[0101] FIG. 11 is a diagram illustrating a second example of the circuit configuration of the comparator according to the first embodiment.

[0102] In the figure, a comparator 131A can compare a read level V1 of a pixel signal with a reference voltage VRF based on a single-ended input. At this time, the comparator 131A can invert its output based on the difference between the read level V1 of the pixel signal and the reference voltage VRF. The comparator 131A includes a PMOS transistor 161, an NMOS transistor 162, and a current source 163.

[0103] The PMOS transistor 161 is connected between the amplification transistor 125 and the current source 130. At this time, a pixel signal read level V1 is applied to the source of the PMOS transistor 161. A reference voltage VRF is applied to the gate of the PMOS transistor 161. A voltage V2 is output from the drain of the PMOS transistor 161.

[0104] The NMOS transistor 162 and the current source 163 are connected in series to each other. The gate of the NMOS transistor 162 is connected to the drain of the PMOS transistor 161. At this time, a drain voltage V2 is applied to the gate of the NMOS transistor 162. The drain of the NMOS transistor 162 is connected to the drain of the NMOS transistor 151. A drain voltage V3 is output from the drain of the NMOS transistor 162.

[0105] FIG. 12 is a diagram showing the relationship between the voltage at each part and the amount of light in the second example circuit configuration of the comparator according to the first embodiment.

[0106] In the diagram, at a, the read level V1 of the pixel signal is set based on the HCG output from the amplification transistor 125. When the light intensity is 0, the read level V1 of the pixel signal is set to the reset level RL. As the light intensity increases, the read level V1 of the pixel signal decreases and approaches VRF+Vth, where Vth is the threshold voltage of the PMOS transistor 161. At this time, as shown in the diagram at b, as the read level V1 of the pixel signal decreases, the drain voltage V2 of the PMOS transistor 161 also decreases. As shown in the diagram at c, before the read level V1 of the pixel signal matches VRF+Vth, the drain voltage V3 of the NMOS transistor 162 is set to a low level.

[0107] When the readout level V1 of the pixel signal coincides with VRF+Vth, the drain voltage V2 of the PMOS transistor 161 becomes approximately 0, as shown by b in the figure. At this time, the drain voltage V3 of the NMOS transistor 162 is inverted to a high level, as shown by c in the figure.

[0108] FIG. 13 is a diagram illustrating an example of a circuit configuration subsequent to the comparator according to the first embodiment.

[0109] 13, in this configuration, a selector 133 is connected to the subsequent stage of the comparator 131A in FIG.

[0110] The selector 133 includes NMOS transistors 171 and 172. The NMOS transistors 171 and 172 are connected in series to each other. The connection point of the NMOS transistors 171 and 172 is connected to the gate of the switching transistor 124. A determination result VCO of the readout level V1 of the pixel signal is applied to the drain of the NMOS transistor 171. A switching signal FDGi is applied to the source of the NMOS transistor 172. A switching signal FEL is applied to the gate of the NMOS transistor 171. A switching signal FELB is applied to the gate of the NMOS transistor 172. The switching signal FELB is an inverted signal of the switching signal FEL. In this case, when the switching signal FEL is at a high level, the selector 133 selects the determination result VCO of the readout level V1 of the pixel signal as the switching signal FDG, and when the switching signal FEL is at a low level, the selector 133 selects the switching signal FDGi as the switching signal FDG.

[0111] FIG. 14 is a diagram showing a second example of the circuit configuration of a pixel provided in the solid-state imaging device according to the first embodiment.

[0112] In Fig. 14, pixel PIXA has a sample and hold circuit SHA instead of the sample and hold circuit SH of Fig. 3. Other configurations of pixel PIXA are similar to those of pixel PIX of Fig. 3. The sample and hold circuit SHA has sample and hold capacitors C1A and C2A and sample and hold transistors ST1A and ST2A.

[0113] The sample and hold capacitor C1A samples and holds the D-phase level output from the amplifier transistor 125. The sample and hold capacitor C2A samples and holds the P-phase level output from the amplifier transistor 125. The sample and hold transistor ST1A sets the transfer timing of the P-phase level output from the amplifier transistor 125 and the sampling timing of the D-phase level. The sample and hold transistor ST2A sets the sampling timing of the P-phase level output from the amplifier transistor 125.

[0114] A sample and hold signal S1 is applied to the gate of the sample and hold transistor ST1A, and a sample and hold signal S2 is applied to the gate of the sample and hold transistor ST2A.

[0115] 15 is a timing chart showing an example of waveforms at various parts during global shutter operation in the second circuit configuration example of the pixel according to the first embodiment. Note that the same figure shows an example of waveforms at various parts during high illuminance during global shutter operation. The waveforms of the sample-and-hold signals S1 and S2 during low illuminance during global shutter operation are similar to the waveforms of the sample-and-hold signals S1 and S2 during high illuminance during global shutter operation.

[0116] In the figure, the global shutter operation includes a PD reset period P11A, a P-phase sampling period P12A, a charge transfer period P13A, an illuminance determination period P14A, a conversion efficiency switching period P15A, and a D-phase sampling period P16A. Note that the exposure period is omitted in the figure.

[0117] During the PD reset period P11A, the transfer signal TRG, the sample-and-hold signals S1 and S2, the active signal CM, and the switching signal FEL are set to low levels. At this time, the transfer transistor 122 and the sample-and-hold transistors ST1 and ST2 are turned off, the comparator 131 and the latch circuit 132 are deactivated, and the switching signal FDGi is selected by the selector 133. Then, the reset signal RST and the switching signal FDG rise, turning on the reset transistor 123 and the switching transistor 124. At this time, the conversion efficiency of the amplification transistor 125 is set to low conversion efficiency, and the charge of the floating diffusion FD1 is reset.

[0118] During the P-phase sampling period P12A, the reset signal RST and the switching signal FDG fall, turning off the reset transistor 123 and the switching transistor 124. At this time, the conversion efficiency of the amplifier transistor 125 is set to high. Also, the sample and hold signals S1 and S2 rise, turning on the sample and hold transistors ST1A and ST2A. At this time, a charge corresponding to the P-phase level output from the amplifier transistor 125 is held in the sample and hold capacitor C2A.

[0119] During the charge transfer period P13A, the transfer signal TRG rises, turning on the transfer transistor 122. At this time, the charge accumulated in the photodiode PD is transferred to the floating diffusion FD1. A voltage corresponding to the charge transferred to the floating diffusion FD1 is then applied to the gate of the amplification transistor 125. Then, based on the source follower operation between the amplification transistor 125 and the current source 130, a read level V1 corresponding to the voltage applied to the gate of the amplification transistor 125 is input to the comparator 131.

[0120] In an illuminance determination period P14A, an active signal CM rises, and the comparator 131 and the latch circuit 132 are activated. Then, the comparator 131 compares the read level V1 of the pixel signal with a reference voltage VRF, and the determination result VCO of the read level V1 is latched in the latch circuit 132. At high illuminance, the read level V1 of the pixel signal becomes equal to or higher than the reference voltage VRF, and the determination result VCO is set to a high level.

[0121] During the conversion efficiency switching period P15A, the switching signal FEL rises. At this time, the selector 133 selects the determination result VCO latched in the latch circuit 132 as the switching signal FDG and applies it to the gate of the switching transistor 124. At this time, under high illuminance, the determination result VCO is set to a high level. As a result, the switching signal FDG rises and the switching transistor 124 is turned on. Therefore, the conversion efficiency of the amplification transistor 125 is set to a low conversion efficiency, and the readout level V1 of the pixel signal is set to the LCG output.

[0122] During the D-phase sampling period P16A, the sample and hold signal S1 rises, turning on the sample and hold transistor ST1A. At this time, the charge corresponding to the D-phase level with low conversion efficiency output from the amplifier transistor 125 is held in the sample and hold capacitor C1A.

[0123] FIG. 16 is a diagram showing a third example of a circuit configuration of a pixel provided in the solid-state imaging device according to the first embodiment.

[0124] In Fig. 16, pixel PIXB includes a sample and hold circuit SHB instead of the sample and hold circuit SH of Fig. 3. Other configurations of pixel PIXB are similar to those of pixel PIX of Fig. 3. The sample and hold circuit SHB includes sample and hold capacitors C1B and C2B and sample and hold transistors ST1B, ST2B, and ST3.

[0125] The sample and hold capacitor C1B samples and holds the P-phase level output from the amplifier transistor 125. The sample and hold capacitor C2B samples and holds the D-phase level output from the amplifier transistor 125. The sample and hold transistor ST1B sets the sampling timing of the P-phase level output from the amplifier transistor 125. The sample and hold transistor ST2B sets the sampling timing of the D-phase level output from the amplifier transistor 125. The sample and hold transistor ST3 switches the connection between the sample and hold circuit SHB and the amplifier transistor 125.

[0126] A sample and hold signal S1 is applied to the gate of the sample and hold transistor ST1 B. A sample and hold signal S2 is applied to the gate of the sample and hold transistor ST2 B. A sample and hold signal SPH is applied to the sample and hold transistor ST3.

[0127] 17 is a timing chart showing an example of waveforms at various parts during the global shutter operation of the third circuit configuration example of the pixel according to the first embodiment. Note that the drawing shows an example of waveforms at various parts during the global shutter operation under high illuminance.

[0128] In the figure, the global shutter operation includes a PD reset period P11B, a P-phase sampling period P12B, a charge transfer period P13B, an illuminance determination period P14B, a conversion efficiency switching period P15B, and a D-phase sampling period P16B. Note that the exposure period is omitted in the figure.

[0129] During the PD reset period P11B, the transfer signal TRG, the sample and hold signals S1, S2, and SPH, the active signal CM, and the switching signal FEL are set to low levels. At this time, the transfer transistor 122 and the sample and hold transistors ST1B, ST2B, and ST3 are turned off, the comparator 131 and the latch circuit 132 are deactivated, and the switching signal FDGi is selected by the selector 133. Then, the reset signal RST and the switching signal FDG rise, turning on the reset transistor 123 and the switching transistor 124. At this time, the conversion efficiency of the amplification transistor 125 is set to low conversion efficiency, and the charge of the floating diffusion FD1 is reset.

[0130] During the P-phase sampling period P12B, the reset signal RST and the switching signal FDG fall, turning off the reset transistor 123 and the switching transistor 124. At this time, the conversion efficiency of the amplifier transistor 125 is set to high. Also, the sample and hold signals S1 and SPH rise, turning on the sample and hold transistors ST1B and ST3. At this time, a charge corresponding to the P-phase level output from the amplifier transistor 125 is held in the sample and hold capacitor C2B.

[0131] During the charge transfer period P13B, the transfer signal TRG rises, turning on the transfer transistor 122. At this time, the charge accumulated in the photodiode PD is transferred to the floating diffusion FD1. A voltage corresponding to the charge transferred to the floating diffusion FD1 is then applied to the gate of the amplification transistor 125. Then, based on the source follower operation between the amplification transistor 125 and the current source 130, a read level V1 corresponding to the voltage applied to the gate of the amplification transistor 125 is input to the comparator 131.

[0132] In an illuminance determination period P14B, an active signal CM rises, and the comparator 131 and the latch circuit 132 are activated. Then, the comparator 131 compares the read level V1 of the pixel signal with a reference voltage VRF, and the determination result VCO of the read level V1 is latched in the latch circuit 132. At high illuminance, the read level V1 of the pixel signal becomes equal to or higher than the reference voltage VRF, and the determination result VCO is set to a high level.

[0133] During the conversion efficiency switching period P15B, the switching signal FEL rises. At this time, the selector 133 selects the determination result VCO latched in the latch circuit 132 as the switching signal FDG and applies it to the gate of the switching transistor 124. At this time, under high illuminance, the determination result VCO is set to a high level. As a result, the switching signal FDG rises and the switching transistor 124 is turned on. Therefore, the conversion efficiency of the amplification transistor 125 is set to a low conversion efficiency, and the readout level V1 of the pixel signal is set to the LCG output.

[0134] During the D-phase sampling period P16B, the sample and hold signals S2 and SPH rise, turning on the sample and hold transistors ST1B and ST3A. At this time, the charge corresponding to the D-phase level with low conversion efficiency output from the amplifier transistor 125 is held in the sample and hold capacitor C1B.

[0135] FIG. 18 is a diagram showing a fourth example of a circuit configuration of a pixel provided in the solid-state imaging device according to the first embodiment.

[0136] In Fig. 18, pixel PIXC includes a sample and hold circuit SHC instead of the sample and hold circuit SH of Fig. 3. Other configurations of pixel PIXC are similar to those of pixel PIX of Fig. 3. The sample and hold circuit SHC includes sample and hold capacitors C1C and C2C and sample and hold transistors ST1C and ST2C.

[0137] The sample and hold capacitor C1C samples and holds the D-phase level output from the amplifier transistor 125. The sample and hold capacitor C2C samples and holds the P-phase level output from the amplifier transistor 125. The sample and hold transistor ST1C sets the transfer timing of the P-phase level output from the amplifier transistor 125 and the sampling timing of the D-phase level. The sample and hold transistor ST2C sets the sampling timing of the P-phase level output from the amplifier transistor 125.

[0138] A sample and hold signal S1 is applied to the gate of the sample and hold transistor ST1C, and a sample and hold signal S2 is applied to the gate of the sample and hold transistor ST2C.

[0139] The waveforms of the sample and hold signals S1 and S2 in the global shutter operation of the pixel PIXC in FIG. 18 are similar to the waveforms of the sample and hold signals S1 and S2 in the global shutter operation of the pixel PIXA in FIG.

[0140] As described above, in the first embodiment, the pixel PIX is provided with the comparator 131 that determines the readout level V1 of a pixel signal that can be sampled and held based on the global shutter operation, and the selector 133 that switches the readout level V1 of the pixel signal. This makes it possible to read out the LCG output or HCG output from the pixel PIX according to the illuminance, without reading out the LCG output and the HCG output from the pixel PIX separately. This makes it possible to generate an HDR image while suppressing an increase in the readout period RD that corresponds to the level of conversion efficiency.

[0141] Furthermore, it is possible to realize sample-and-hold of the LCG output or HCG output according to the illuminance without sample-and-holding each LCG output and HCG output. As a result, it is possible to generate HDR images without moving image distortion while suppressing an increase in the circuit scale of the global shutter period GS and the sample-and-hold circuit SH.

[0142] 2. Second Embodiment In the above-described first embodiment, the read level V1 is switched based on the determination result of the read level V1 determined within the pixel PIX, and the determination result VCO is read out via the vertical signal line 117. In this second embodiment, the read level V1 is switched based on the determination result of the read level V1 determined within the pixel PIX, and a read line is provided for outputting the determination result VCO from the pixel.

[0143] FIG. 19 is a diagram showing an example of a circuit configuration of a pixel provided in a solid-state imaging device according to the second embodiment.

[0144] In the figure, this solid-state imaging device includes a pixel PIX2 instead of the pixel PIX in Figure 3. Furthermore, this solid-state imaging device has a read line 119 added to the solid-state imaging device of the above-mentioned first embodiment. Other configurations of this solid-state imaging device are the same as those of the solid-state imaging device of the above-mentioned first embodiment.

[0145] The pixel PIX2 includes a decision value read transistor 229 instead of the decision value read transistor 129 in Fig. 3. Other configurations of the pixel PIX2 are the same as those of the pixel PIX in Fig. 3.

[0146] The decision value read transistor 229 sets the read timing of the decision result VCO latched in the latch circuit 132. The decision value read transistor 229 is connected between the output of the latch circuit 132 and the read line 119. A selection signal SEL is applied to the gate of the decision value read transistor 229.

[0147] A read line 119 is provided for each column. The read lines 119 may be arranged in parallel with the vertical signal lines 117. The read lines 119 transmit the determination results VCO in the column direction. The determination results VCO may be read from the read lines 119 via a buffer 136.

[0148] FIG. 20 is a timing chart showing an example of waveforms at various parts during a pixel readout operation according to the second embodiment.

[0149] In the same figure, this timing chart has a judgment result read period P31 instead of the judgment result read period P23 of the first embodiment described above. Also, in this timing chart, the judgment result read period P23 of the first embodiment described above is omitted. The other waveforms in this timing chart are the same as the waveforms in the timing chart of the first embodiment described above.

[0150] The judgment result read period P31 can be set to overlap with the P-phase read period P21 and the D-phase read period P22.

[0151] In a judgment result read period P31, the selection signal SEL rises, turning on the judgment value read transistor 229. At this time, a voltage according to the judgment result VCO is applied to the read line 119 and read out via the buffer 136. Thereafter, the selection signal SEL falls, turning off the judgment value read transistor 229.

[0152] In this way, in the second embodiment described above, the read level V1 is switched based on the determination result of the read level V1 determined within the pixel PIX2, and a read line 119 is provided for outputting the determination result VCO from the pixel PIX2. This makes it possible to read out the determination result VCO of the read level V1 of the pixel signal separately from the pixel signal, and alleviates restrictions on the read timing of the determination result VCO.

[0153] In the second embodiment, an example has been shown in which the sample and hold circuit SH of Fig. 3 is provided in pixel PIX2. Also in the second embodiment, instead of the sample and hold circuit SH of Fig. 3, the sample and hold circuit SHA of Fig. 14, the sample and hold circuit SHB of Fig. 16, or the sample and hold circuit SHC of Fig. 18 may be provided.

[0154] 3. Third Embodiment In the above-described first embodiment, the read level V1 is switched based on the determination result of the read level V1 determined in the pixel PIX capable of the global shutter operation. In this third embodiment, the read level V1 is switched based on the determination result of the read level V1 determined in the pixel PIX capable of the rolling shutter operation.

[0155] FIG. 21 is a diagram showing an example of a circuit configuration of a pixel provided in a solid-state imaging device according to the third embodiment.

[0156] 19, pixel PIX3 is obtained by removing the sample-and-hold circuit SH, reset transistor 126, amplifying transistor 127, and floating diffusion FD2 from pixel PIX2 in FIG. 19. Furthermore, pixel PIX3 is obtained by adding a decoupling transistor 301 to pixel PIX2 in FIG. 19. Furthermore, in pixel PIX3, a decision value read signal SB is applied to the gate of decision value read transistor 229 instead of selection signal SEL. The remaining configuration of pixel PIX3 is the same as that of pixel PIX2 in the second embodiment described above. In this case, pixel PIX3 can read out a pixel signal based on a rolling shutter operation after switching the pixel signal read level V1 based on the decision result of the pixel signal read level V1.

[0157] The disconnection transistor 301 controls the disconnection of the amplifying transistor 125 and the comparator 131 based on the active signal CM. At this time, the amplifying transistor 125 can be disconnected from the comparator 131 via the disconnection transistor 301 when a pixel signal is read out. This makes it possible to determine the readout level V1 within the pixel PIX3, while reducing the load when the pixel signal is read out. The disconnection transistor 301 is connected between the amplifying transistor 125 and the input of the readout level V1 of the comparator 131. The connection point between the disconnection transistor 301 and the amplifying transistor 125 is connected to the vertical signal line 117 via the selection transistor 128.

[0158] FIG. 22 is a flowchart showing a pixel signal readout process of the solid-state imaging device according to the third embodiment.

[0159] In the figure, the reset transistor 123 and the switching transistor 124 are turned on, and the floating diffusion FD1 is reset (step S301).

[0160] Next, the selection transistor 128 is turned on, and a P-phase level corresponding to the charge of the floating diffusion FD1 is applied to the gate of the amplification transistor 125. Then, based on the source follower operation between the amplification transistor 125 and the current source 134, the potential VSL of the vertical signal line 117 is set according to the P-phase level applied to the gate of the amplification transistor 125, and is input to the ADC 135. Then, the ADC 135 performs AD conversion on the P-phase level output from the amplification transistor 125 (step S302).

[0161] Next, the selection transistor 128 is turned off, the transfer transistor 122 is turned on, and the charge accumulated in the photodiode PD is transferred to the floating diffusion FD1 (step S303).

[0162] Next, the switching transistor 301 is turned on, and the readout level V1 of the pixel signal output from the amplification transistor 125 is input to the comparator 131 via the switching transistor 301. The comparator 131 then determines the illuminance based on the readout level V1 of the pixel signal output from the amplification transistor 125 (step S304). The illuminance determination can be performed while the switching transistor 124 is turned off and high conversion efficiency is maintained. If the illuminance is high, the switching transistor 124 is turned on and switched to low conversion efficiency (step S305). The selection transistor 128 is then turned on, and a P-phase level with low conversion efficiency corresponding to the charge in the floating diffusion FD1 is applied to the gate of the amplification transistor 125. Based on the source follower operation between the amplification transistor 125 and the current source 134, the potential VSL of the vertical signal line 117 is set according to the D-phase level with low conversion efficiency applied to the gate of the amplification transistor 125, and the potential VSL is input to the ADC 135. Then, the ADC 135 performs AD conversion on the D-phase level with low conversion efficiency output from the amplifying transistor 125 (step S306). After that, the decision value read transistor 129 is turned on, and the decision result VCO is read out via the read line 119.

[0163] On the other hand, when the illuminance is low, the switching transistor 124 is turned off to maintain high conversion efficiency. Then, the selection transistor 128 is turned on, and a high-conversion-efficiency D-phase level corresponding to the charge of the floating diffusion FD1 is applied to the gate of the amplification transistor 125. Then, based on the source-follower operation between the amplification transistor 125 and the current source 134, the potential VSL of the vertical signal line 117 is set according to the high-conversion-efficiency D-phase level applied to the gate of the amplification transistor 125, and input to the ADC 135. Then, the ADC 135 performs AD conversion on the high-conversion-efficiency D-phase level output from the amplification transistor 125 (step S306). Then, the decision value readout transistor 129 is turned on, and the decision result VCO is read out via the readout line 119.

[0164] FIG. 23 is a timing chart showing an example of waveforms at various parts during low illuminance in the rolling shutter operation of the pixel according to the third embodiment.

[0165] In the figure, the rolling shutter operation includes a PD reset period P31, a P-phase AD period P32, a charge transfer period P33, an illuminance determination period P34, a conversion efficiency switching period P35, and a D-phase AD / determination result transmission period P36. Note that the exposure period is omitted in the figure.

[0166] During the PD reset period P31, the transfer signal TRG, the decision value readout signal SB, the selection signal SEL, the active signal CM, and the switching signal FEL are set to low levels. At this time, the transfer transistor 122, the decision value readout transistor 229, and the selection transistor 128 are turned off, the comparator 131 and the latch circuit 132 are deactivated, and the switching signal FDGi is selected by the selector 133. Then, the reset signal RST and the switching signal FDG rise, turning on the reset transistor 123 and the switching transistor 124. At this time, the conversion efficiency of the amplification transistor 125 is set to low conversion efficiency, and the charge of the floating diffusion FD1 is reset.

[0167] During the P-phase AD period P32, the reset signal RST and the switching signal FDG fall, turning off the reset transistor 123 and the switching transistor 124. At this time, the conversion efficiency of the amplifier transistor 125 is set to high. Furthermore, the selection signal SEL rises, turning on the selection transistor 128A. At this time, a P-phase level corresponding to the charge of the floating diffusion FD1 is applied to the gate of the amplifier transistor 125. Based on the source-follower operation between the amplifier transistor 125 and the current source 134, the potential VSL of the vertical signal line 117 is set according to the P-phase level applied to the gate of the amplifier transistor 125, and input to the ADC 135. The ADC 135 then performs AD conversion on the P-phase level output from the amplifier transistor 125.

[0168] During the charge transfer period P33, the transfer signal TRG rises, turning on the transfer transistor 122. At this time, the charge accumulated in the photodiode PD is transferred to the floating diffusion FD1. A voltage corresponding to the charge transferred to the floating diffusion FD1 is then applied to the gate of the amplification transistor 125. Then, based on the source follower operation between the amplification transistor 125 and the current source 130, a read level V1 corresponding to the voltage applied to the gate of the amplification transistor 125 is input to the comparator 131.

[0169] In an illuminance determination period P34, an active signal CM rises, and the comparator 131 and the latch circuit 132 are activated. Then, the comparator 131 compares the read level V1 of the pixel signal with a reference voltage VRF, and the determination result VCO of the read level V1 is latched in the latch circuit 132. At low illuminance, the read level V1 of the pixel signal becomes equal to or higher than the reference voltage VRF, and the determination result VCO is set to a low level.

[0170] During the conversion efficiency switching period P35, the switching signal FEL rises. At this time, the selector 133 selects the determination result VCO latched in the latch circuit 132 as the switching signal FDG and applies it to the gate of the switching transistor 124. At this time, during low illuminance, the determination result VCO is set to a low level. Therefore, the switching signal FDG remains at a low level, and the switching transistor 124 is turned off. Therefore, the conversion efficiency of the amplification transistor 125 is set to a high conversion efficiency, and the readout level V1 of the pixel signal is set to the HCG output.

[0171] During the D-phase AD / determination result transmission period P36, the selection signal SEL and the determination value read signal SB rise, turning on the selection transistor 128 and the determination value read transistor 229. At this time, a high-conversion-efficiency D-phase level corresponding to the charge of the floating diffusion FD1 is applied to the gate of the amplifier transistor 125. Then, based on the source-follower operation between the amplifier transistor 125 and the current source 134, the potential VSL of the vertical signal line 117 is set according to the high-conversion-efficiency D-phase level applied to the gate of the amplifier transistor 125, and input to the ADC 135. Then, the ADC 135 performs AD conversion on the high-conversion-efficiency D-phase level output from the amplifier transistor 125. Furthermore, the determination result VCO indicating low illuminance is read out to the read line 119 via the determination value read transistor 129.

[0172] FIG. 24 is a timing chart showing an example of waveforms at various parts during high illuminance in the rolling shutter operation of the pixel according to the third embodiment.

[0173] In the figure, the operations during the PD reset period P31, P-phase AD period P32, charge transfer period P33, and illuminance determination period P34 at high illuminance are the same as those during the PD reset period P31, P-phase AD period P32, charge transfer period P33, and illuminance determination period P34 at low illuminance. However, at high illuminance, the readout level V1 of the pixel signal becomes lower than the reference voltage VRF, and the determination result VCO is set to a high level.

[0174] During the conversion efficiency switching period P35, the switching signal FEL rises. At this time, the selector 133 selects the determination result VCO latched in the latch circuit 132 as the switching signal FDG and applies it to the gate of the switching transistor 124. Here, during high illuminance, the determination result VCO is set to a high level. Therefore, the switching signal FDG rises, and the switching transistor 124 is turned on. Therefore, the conversion efficiency of the amplification transistor 125 is set to a low conversion efficiency, and the readout level V1 of the pixel signal is set to the LCG output.

[0175] During the D-phase AD / determination result transmission period P36, the selection signal SEL and the determination value readout signal SB rise, turning on the selection transistor 128 and the determination value readout transistor 229. At this time, a D-phase level with low conversion efficiency corresponding to the charge of the floating diffusion FD1 is applied to the gate of the amplifier transistor 125. Then, based on the source-follower operation between the amplifier transistor 125 and the current source 134, the potential VSL of the vertical signal line 117 is set according to the D-phase level with low conversion efficiency applied to the gate of the amplifier transistor 125, and input to the ADC 135. Then, the ADC 135 performs AD conversion on the D-phase level with low conversion efficiency output from the amplifier transistor 125. Furthermore, the determination result VCO indicating high illuminance is read out to the readout line 119 via the determination value readout transistor 129.

[0176] In this way, in the third embodiment described above, the readout level V1 is switched based on the determination result of the readout level V1 determined in the pixel PIX3 capable of rolling shutter operation. This makes it possible to realize readout of the LCG output or HCG output from the pixel PIX3 according to the illuminance, without performing readout from the pixel PIX3 for each LCG output and HCG output. Therefore, even in the pixel PIX3 capable of rolling shutter operation, it is possible to generate an HDR image while suppressing a decrease in frame rate.

[0177] 4. Fourth Embodiment In the above-described first embodiment, the read level V1 is switched between two levels based on the determination result of the read level V1 determined in the pixel PIX capable of performing the global shutter operation. In this fourth embodiment, the read level V1 is switched between three levels based on the determination result of the read level V1 determined in the pixel PIX capable of performing the global shutter operation.

[0178] FIG. 25 is a diagram showing an example of a circuit configuration of a pixel provided in a solid-state imaging device according to the fourth embodiment.

[0179] In the figure, pixel PIX4 has a pass transistor 401, an overflow control transistor 402, and a capacitor C4 added to the pixel PIX of Fig. 3. Also, pixel PIX4 has a decision value readout transistor 429, a latch circuit 432, and a selector 433 added to the pixel PIX of Fig. 3. Other configurations of pixel PIX4 are the same as those of pixel PIX of the first embodiment described above.

[0180] The capacitor C4 accumulates charge overflowing from the photodiode PD. The capacitor C4 may be a lateral overflow integration capacitor (LOFIC). The capacitor C4 may be light-shielded. The capacitor C4 may be a metal-insulation-metal (MIM) capacitor. The capacitor C4 may be a three-dimensional MIM capacitor. The capacitor C4 may be a high-dielectric capacitor.

[0181] The pass transistor 401 sets a path for transferring the charge stored in the capacitor C4 to the floating diffusion FD1. The overflow control transistor 402 controls the overflow of charge from the photodiode PD to the capacitor C4.

[0182] The pass transistor 401 is connected between the connection point of the overflow control transistor 402 and the capacitor C4 and the connection point of the reset transistor 123 and the switching transistor 124. The overflow control transistor 402 is connected between the photodiode PD and the capacitor C4.

[0183] A pass setting signal FCG is applied to the gate of the pass transistor 401. An overflow control voltage OFG is applied to the gate of the overflow control transistor 402. A control power supply voltage MVDD is applied to the capacitor C4. Here, by pulse-driving the capacitor C4 based on the control power supply voltage MVDD, the dark current of the capacitor C4 can be reduced.

[0184] The decision value read transistor 429 sets the read timing of the decision result VCO1 latched in the latch circuit 432. A decision value read signal SB1 is applied to the gate of the decision value read transistor 429. The decision value read transistor 129 sets the read timing of the decision result VCO0 latched in the latch circuit 132. A decision value read signal SB0 is applied to the gate of the decision value read transistor 129.

[0185] The latch circuit 432 latches the determination result VCO1 of the read level V1 of the pixel signal output from the amplification transistor 125. The latch circuit 432 is activated based on an active signal CM1. The latch circuit 132 latches the determination result VCO0 of the read level V1 of the pixel signal output from the amplification transistor 125. The latch circuit 132 is activated based on an active signal CM0.

[0186] The selector 433 switches the readout level V1 of the pixel signal output from the amplification transistor 125. At this time, the selector 433 can switch between the determination result VCO1 of the readout level V1 of the pixel signal and the pass setting signal FCGi based on the switching signal FEL1. The pass setting signal FCGi can be set to a high level when the floating diffusion FD1 is reset, thereby turning on the pass transistor 401. As a result, by turning on the reset transistor 123 when the floating diffusion FD1 is reset, the capacitor C4 can be connected to the power supply potential VDD via the reset transistor 123 and the pass transistor 401. The selector 133 can switch between the determination result VCO0 of the readout level V1 of the pixel signal and the switching signal FDGi based on the switching signal FEL0.

[0187] FIG. 26 is a flowchart showing a pixel signal readout process of the solid-state imaging device according to the fourth embodiment.

[0188] In the figure, the reset transistor 123 and the switching transistor 124 are turned on, and the floating diffusion FD1 is reset (step S401).

[0189] Next, the sample-and-hold transistor ST1 is turned on, and the P-phase level output from the amplifying transistor 125 is sampled by the sample-and-hold capacitor C1 (step S402).

[0190] Next, the transfer transistor 122 is turned on, and the charge accumulated in the photodiode PD is transferred to the floating diffusion FD1 (step S403).

[0191] Next, the comparator 131 performs a first illuminance determination based on the readout level V1 of the pixel signal output from the amplification transistor 125 (step S404). The first illuminance determination can be performed with the switching transistor 124 and the pass transistor 401 turned off and high conversion efficiency maintained. If the first illuminance determination determines that the illuminance is high, the switching transistor 124 is turned on to switch to medium conversion efficiency (step S405), and a second illuminance determination is performed (step S406).

[0192] On the other hand, if the first illuminance determination indicates low illuminance, a second illuminance determination is performed (step S406). The second illuminance determination can be performed with the switching transistor 124 turned on and the pass transistor 401 turned off, maintaining medium conversion efficiency. If the second illuminance determination indicates high illuminance, and the first illuminance determination indicates high illuminance, the switching transistor 124 and the pass transistor 401 are turned on, switching to low conversion efficiency (step S407). Then, the sample-and-hold transistor ST2 is turned on, and the D-phase level output from the amplifier transistor 125 at low conversion efficiency is sampled by the sample-and-hold capacitor C2 (step S408).

[0193] On the other hand, when the second illuminance determination indicates that the illuminance is low, and the first illuminance determination indicates that the illuminance is low, the switching transistor 124 and the pass transistor 401 are turned off to switch to high conversion efficiency. Then, the sample-and-hold transistor ST2 is turned on, and the D-phase level output from the amplification transistor 125 at high conversion efficiency is sampled by the sample-and-hold capacitor C2 (step S408).

[0194] Furthermore, when the second illuminance determination indicates low illuminance, and the first illuminance determination indicates high illuminance, the switching transistor 124 is turned on and the pass transistor 401 is turned off to maintain the medium conversion efficiency. Then, the sample-and-hold transistor ST2 is turned on, and the D-phase level output from the amplification transistor 125 at the medium conversion efficiency is sampled by the sample-and-hold capacitor C2 (step S408).

[0195] FIG. 27 is a timing chart showing an example of waveforms at various parts during low illuminance in the global shutter operation of the pixel according to the fourth embodiment.

[0196] In the figure, this global shutter operation includes a PD reset period P41, an exposure period P42, an FD reset period P43, a P-phase sampling period P44, a charge transfer period P45, illuminance determination periods P46 and P48, conversion efficiency switching periods P47 and P49, and a D-phase sampling period P50.

[0197] During the PD reset period P41, the reset signal RB, sample-and-hold signals SR and SD, active signals CM0 and CM1, and switching signals FEL0 and FEL1 are set to low levels. At this time, the reset transistor 126 and sample-and-hold transistors ST1 and ST2 are turned off, the latch circuits 132 and 432 are deactivated, and the switching signal FDGi is selected by the selectors 133 and 433. The overflow control voltage OFG is set to high level, and the overflow control transistor 402 is turned on. Then, the transfer signal TRG, reset signal RST, path setting signal FCG, and switching signal FDG rise, turning on the transfer transistor 122, reset transistor 123, path transistor 401, and switching transistor 124. At this time, the conversion efficiency of the amplifier transistor 125 is set to low, and the charges in the photodiode PD, capacitor C4, and floating diffusion FD1 are reset.

[0198] During the exposure period P42, the transfer signal TRG, the reset signal RST, the pass setting signal FCG, the overflow control voltage OFG, and the switching signal FDG fall, turning off the transfer transistor 122, the reset transistor 123, the pass transistor 401, the overflow control transistor 402, and the switching transistor 124. At this time, the conversion efficiency of the amplification transistor 125 is set to high conversion efficiency, charge is accumulated in the photodiode PD according to the amount of incident light, and the charge overflowing from the photodiode PD is accumulated in the capacitor C4.

[0199] In the FD reset period P43, the reset signal RST and the switching signal FDG rise, turning on the reset transistor 123 and the switching transistor 124. At this time, the conversion efficiency of the amplification transistor 125 is set to the medium conversion efficiency, and the charge of the floating diffusion FD1 is reset.

[0200] During the P-phase sampling period P44, the reset signal RB and the sample-and-hold signal SR rise, turning on the reset transistor 126 and the sample-and-hold transistor ST1. At this time, a charge corresponding to the P-phase level output from the amplifier transistor 125 is held in the sample-and-hold capacitor C1.

[0201] During the charge transfer period P45, the transfer signal TRG rises, turning on the transfer transistor 122. At this time, the charge accumulated in the photodiode PD is transferred to the floating diffusion FD1. A voltage corresponding to the charge transferred to the floating diffusion FD1 is then applied to the gate of the amplification transistor 125. Then, based on the source follower operation between the amplification transistor 125 and the current source 130, a read level V1 corresponding to the voltage applied to the gate of the amplification transistor 125 is input to the comparator 131.

[0202] In an illuminance determination period P46, an active signal CM0 rises, and the comparator 131 and the latch circuit 132 are activated. Then, the comparator 131 compares the read level V1 of the pixel signal with a reference voltage VRF, and the determination result VCO0 of the read level V1 is latched in the latch circuit 132. At low illuminance, the read level V1 of the pixel signal is less than the reference voltage VRF, and the determination result VCO0 is set to a low level.

[0203] During the conversion efficiency switching period P47, the switching signal FEL0 rises. At this time, the selector 133 selects the determination result VCO0 latched in the latch circuit 132 as the switching signal FDG and applies it to the gate of the switching transistor 124. At this time, during low illuminance, the determination result VCO0 is set to a low level. Therefore, the switching signal FDG remains at a low level, and the switching transistor 124 is turned off. Therefore, the conversion efficiency of the amplification transistor 125 is set to a high conversion efficiency, and the readout level V1 of the pixel signal is set to the HCG output.

[0204] In an illuminance determination period P48, an active signal CM1 rises, activating the comparator 131 and the latch circuit 432. Then, the comparator 131 compares the read level V1 of the pixel signal with the reference voltage VRF, and the determination result VCO1 of the read level V1 is latched in the latch circuit 432. At low illuminance, the read level V1 of the pixel signal becomes less than the reference voltage VRF, and the determination result VCO1 is set to a low level.

[0205] During the conversion efficiency switching period P49, the switching signal FEL1 rises. At this time, the selector 4133 selects the determination result VCO1 latched in the latch circuit 142 as the pass setting signal FCG and applies it to the gate of the pass transistor 401. At this time, during low illuminance, the determination result VCO1 is set to a low level. Therefore, the pass setting signal FCG remains at a low level, and the pass transistor 401 is turned off. Therefore, the conversion efficiency of the amplifier transistor 125 is set to a high conversion efficiency, and the readout level V1 of the pixel signal is maintained at the HCG output.

[0206] During the D-phase sampling period P50, the reset signal RB and the sample-and-hold signal SD rise, turning on the reset transistor 126 and the sample-and-hold transistor ST2. At this time, a charge corresponding to the D-phase level with high conversion efficiency output from the amplifier transistor 125 is held in the sample-and-hold capacitor C2.

[0207] FIG. 28 is a timing chart showing an example of waveforms at various parts during a global shutter operation of a pixel according to the fourth embodiment at a medium illuminance level.

[0208] In the same figure, the operations of the PD reset period P41, exposure period P42, FD reset period P43, P-phase sampling period P44, and charge transfer period P45 during medium illuminance are the same as the operations of the PD reset period P41, exposure period P42, FD reset period P43, P-phase sampling period P44, and charge transfer period P45 during medium illuminance during low illuminance.

[0209] In an illuminance determination period P46, an active signal CM0 rises, and the comparator 131 and the latch circuit 132 are activated. Then, the comparator 131 compares the read level V1 of the pixel signal with the reference voltage VRF, and the determination result VCO0 of the read level V1 is latched in the latch circuit 132. At medium illuminance, the read level V1 of the pixel signal is less than the reference voltage VRF, and the determination result VCO0 is set to a high level.

[0210] During the conversion efficiency switching period P47, the switching signal FEL0 rises. At this time, the selector 133 selects the determination result VCO0 latched in the latch circuit 132 as the switching signal FDG and applies it to the gate of the switching transistor 124. At this time, during medium illuminance, the determination result VCO0 is set to a high level. Therefore, the switching signal FDG rises and the switching transistor 124 is turned on. Therefore, the conversion efficiency of the amplification transistor 125 is set to a medium conversion efficiency, and the readout level V1 of the pixel signal is set to an MCG (Middle Conversion Gain) output.

[0211] In an illuminance determination period P48, an active signal CM1 rises, and the comparator 131 and the latch circuit 432 are activated. Then, the comparator 131 compares the read level V1 of the pixel signal with a reference voltage VRF, and the determination result VCO1 of the read level V1 is latched in the latch circuit 432. At medium illuminance, the read level V1 of the pixel signal becomes equal to or higher than the reference voltage VRF, and the determination result VCO1 is set to a low level.

[0212] During the conversion efficiency switching period P49, the switching signal FEL1 rises. At this time, the selector 4133 selects the determination result VCO1 latched in the latch circuit 142 as the pass setting signal FCG and applies it to the gate of the pass transistor 401. Here, during medium illuminance, the determination result VCO1 is set to a low level. Therefore, the pass setting signal FCG remains low, and the pass transistor 401 is turned off. Therefore, the conversion efficiency of the amplifier transistor 125 remains medium, and the readout level V1 of the pixel signal remains the MCG output.

[0213] During the D-phase sampling period P50, the reset signal RB and the sample-and-hold signal SD rise, turning on the reset transistor 126 and the sample-and-hold transistor ST2. At this time, the charge corresponding to the D-phase level of the medium conversion efficiency output from the amplifier transistor 125 is held in the sample-and-hold capacitor C2.

[0214] FIG. 29 is a timing chart showing an example of waveforms at various parts during high illuminance in the global shutter operation of the pixel according to the fourth embodiment.

[0215] In the same figure, the operations of the PD reset period P41, exposure period P42, FD reset period P43, P-phase sampling period P44, and charge transfer period P45 during high illuminance are similar to the operations of the PD reset period P41, exposure period P42, FD reset period P43, P-phase sampling period P44, and charge transfer period P45 during low illuminance.

[0216] In an illuminance determination period P46, an active signal CM0 rises, and the comparator 131 and the latch circuit 132 are activated. Then, the comparator 131 compares the read level V1 of the pixel signal with a reference voltage VRF, and the determination result VCO0 of the read level V1 is latched in the latch circuit 132. At high illuminance, the read level V1 of the pixel signal becomes less than the reference voltage VRF, and the determination result VCO0 is set to a high level.

[0217] During the conversion efficiency switching period P47, the switching signal FEL0 rises. At this time, the selector 133 selects the determination result VCO0 latched in the latch circuit 132 as the switching signal FDG and applies it to the gate of the switching transistor 124. At this time, under high illuminance, the determination result VCO0 is set to a high level. As a result, the switching signal FDG rises and the switching transistor 124 is turned on. Therefore, the conversion efficiency of the amplification transistor 125 is set to a medium conversion efficiency, and the readout level V1 of the pixel signal is set to the MCG output.

[0218] In an illuminance determination period P48, an active signal CM1 rises, activating the comparator 131 and the latch circuit 432. Then, the comparator 131 compares the read level V1 of the pixel signal with the reference voltage VRF, and the determination result VCO1 of the read level V1 is latched in the latch circuit 432. At high illuminance, the read level V1 of the pixel signal becomes less than the reference voltage VRF, and the determination result VCO1 is set to a high level.

[0219] During the conversion efficiency switching period P49, the switching signal FEL1 rises. At this time, the selector 4133 selects the determination result VCO1 latched in the latch circuit 142 as the pass setting signal FCG and applies it to the gate of the pass transistor 401. At this time, under high illuminance, the determination result VCO1 is set to a high level. Therefore, the pass setting signal FCG is set to a high level, and the pass transistor 401 is turned on. Therefore, the conversion efficiency of the amplifier transistor 125 is set to a low conversion efficiency, and the readout level V1 of the pixel signal is changed from the MCG output to the LCG output.

[0220] During the D-phase sampling period P50, the reset signal RB and the sample-and-hold signal SD rise, turning on the reset transistor 126 and the sample-and-hold transistor ST2. At this time, a charge corresponding to the D-phase level with low conversion efficiency output from the amplifier transistor 125 is held in the sample-and-hold capacitor C2.

[0221] As described above, in the fourth embodiment, the readout level V1 is switched between three levels based on the determination result of the readout level V1 determined within the pixel PIX4 capable of global shutter operation. This makes it possible to realize readout of the LCG output, MCG output, or HCG output from the pixel PIX4 according to the illuminance, without performing readout from the pixel PIX4 for each of the LCG output, MCG output, and HCG output. Therefore, even when the readout level V1 is switched between three levels, it is possible to generate an HDR image while suppressing a decrease in frame rate.

[0222] 5. Fifth Embodiment In the first embodiment described above, the pixel PIX is provided with the comparator 131 that determines the readout level V1 of a pixel signal that can be sampled and held based on the global shutter operation. In this fifth embodiment, the reset transistor 126, the amplification transistor 127, and the selection transistor 128 used in the global shutter operation are shared by multiple pixels.

[0223] FIG. 30 is a diagram showing a first example of a circuit configuration of a pixel provided in a solid-state imaging device according to the fifth embodiment.

[0224] In Fig. 30, this solid-state imaging device includes pixels PIX5A and PIX5B instead of the pixel PIX in Fig. 3. Other configurations of the first example of the solid-state imaging device of the fifth embodiment are similar to the configuration of the solid-state imaging device of the above-described first embodiment.

[0225] The pixel PIX5A can be configured in the same manner as the pixel PIX of the first embodiment described above. The pixel PIX5B is configured such that the reset transistor 126, the amplification transistor 127, and the selection transistor 128 used for the global shutter operation are removed from the pixel PIX of the first embodiment described above. Here, the drains of the sample and hold transistors ST1 and ST2 of the pixel PIX5B are connected to the floating diffusion FD2 of the pixel PIX5A. In this case, the reset transistor 126, the amplification transistor 127, and the selection transistor 128 used for the global shutter operation are shared by the pixels PIX5A and PIX5B.

[0226] FIG. 31 is a diagram showing a second example of the circuit configuration of a pixel provided in the solid-state imaging device according to the fifth embodiment.

[0227] In Fig. 31, this solid-state imaging device includes pixels PIX5C and PIX5D instead of the pixels PIX5A and PIX5B in Fig. 30. Other configurations of the second example of the solid-state imaging device of the fifth embodiment are similar to the configuration of the solid-state imaging device of the first embodiment described above.

[0228] The pixel PIX5C has a switch SW1 added to the pixel PIX5A in Fig. 30. The other configuration of the pixel PIX5C is the same as the configuration of the pixel PIX5A in Fig. 30. The pixel PIX5D has a switch SW2 added to the pixel PIX5B in Fig. 30. The other configuration of the pixel PIX5D is the same as the configuration of the pixel PIX5B in Fig. 30.

[0229] The switch SW1 is connected between the source of the amplification transistor 125 of the pixel PIX5C and the input of the comparator 131. The switch SW2 is connected between the source of the amplification transistor 125 of the pixel PIX5D and the input of the comparator 131. Here, in the pixel PIX5C, turning on the switch SW1 allows the pixel PIX5C to determine the illuminance and switch the conversion efficiency. In the pixel PIX5D, turning on the switch SW2 allows the pixel PIX5D to determine the illuminance and switch the conversion efficiency.

[0230] The output of the comparator 131 is connected to the input of the latch circuit 132 of each of the pixels PIX5C and PIX5D. In this case, not only the reset transistor 126, the amplification transistor 127, and the selection transistor 128, but also the comparator 131 used for illuminance determination are shared by the pixels PIX5C and PIX5D.

[0231] Here, in pixel PIX5C, by turning on switch SW1, it is possible to determine the illuminance and switch the conversion efficiency in pixel PIX5C, and in pixel PIX5D, by turning on switch SW2, it is possible to determine the illuminance and switch the conversion efficiency in pixel PIX5D.

[0232] FIG. 32 is a diagram showing a third example of a circuit configuration of a pixel provided in a solid-state imaging device according to the fifth embodiment.

[0233] In the figure, this solid-state imaging device includes pixels PIX5E and PIX5F instead of the pixels PIX5C and PIX5D in Figure 31. Other configurations of the third example of the solid-state imaging device of the fifth embodiment are similar to the configuration of the solid-state imaging device of the above-mentioned first embodiment.

[0234] Pixel PIX5E has a switch SW3 instead of switch SW1 in Fig. 31. Pixel PIX5E has the current source 130 removed from pixel PIX5C in Fig. 31. Other configurations of pixel PIX5E are the same as those of pixel PIX5C in Fig. 31. Pixel PIX5F has a switch SW4 instead of switch SW2 in Fig. 31. Other configurations of pixel PIX5F are the same as those of pixel PIX5D in Fig. 31.

[0235] The switch SW3 is connected between the source of the amplifier transistor 125 of the pixel PIX5E and the inputs of the sample and hold capacitors C1 and C2. The switch SW4 is connected between the source of the amplifier transistor 125 of the pixel PIX5E and the inputs of the sample and hold capacitors C1 and C2. The inputs of the sample and hold capacitors C1 and C2 of the pixels PIX5C and PIX5D are connected to the input of the comparator 131 and the current source 130. In this case, the pixels PIX5E and PIX5F share not only the reset transistor 126, amplifier transistor 127, and selection transistor 128, but also the comparator 131 and current source 130.

[0236] Here, in pixel PIX5E, by turning on switch SW3, it is possible to perform illuminance determination and switching of conversion efficiency in pixel PIX5E.In pixel PIX5F, by turning on switch SW4, it is possible to perform illuminance determination and switching of conversion efficiency in pixel PIX5F.

[0237] FIG. 33 is a diagram showing a fourth example of a circuit configuration of a pixel provided in a solid-state imaging device according to the fifth embodiment.

[0238] In the figure, in this solid-state imaging device, pixels PIX5G and PIX5H are added to the pixels PIX5A and PIX5B in Figure 30. Other configurations of the fourth example of the solid-state imaging device of the fifth embodiment are the same as those of the solid-state imaging device of the first embodiment described above.

[0239] The pixels PIX5G and PIX5H can be configured in the same manner as the pixel PIX5B. Here, the drains of the sample-and-hold transistors ST1 and ST2 of the pixels PIX5G and PIX5H are connected to the floating diffusion FD2 of the pixel PIX5A. In this case, the reset transistor 126, the amplification transistor 127, and the selection transistor 128 used for the global shutter operation are shared by the pixels PIX5A, PIX5B, PIX5G, and PIX5H.

[0240] FIG. 34 is a diagram showing a fifth example of a circuit configuration of a pixel provided in a solid-state imaging device according to the fifth embodiment.

[0241] In the figure, in this solid-state imaging device, pixels PIX5I and PIX5J are added to the pixels PIX5C and PIX5D in Figure 31. Other configurations of the fifth example of the solid-state imaging device of the fifth embodiment are similar to the configuration of the solid-state imaging device of the above-mentioned first embodiment.

[0242] The pixels PIX5I and PIX5J can be configured in the same manner as the pixel PIX5D, except that switches SW5 and SW6 are added to the pixels PIX5I and PIX5J, respectively.

[0243] The switch SW5 is connected between the source of the amplification transistor 125 of the pixel PIX5I and the input of the comparator 131. The switch SW6 is connected between the source of the amplification transistor 125 of the pixel PIX5J and the input of the comparator 131. The output of the comparator 131 is connected to the input of the latch circuit 132 of each of the pixels PIX5C, PIX5D, PIX5I, and PIX5J. In this case, not only the reset transistor 126, amplification transistor 127, and selection transistor 128, but also the comparator 131 used for illuminance determination are shared by the pixels PIX5C, PIX5D, PIX5I, and PIX5J.

[0244] Here, in pixel PIX5I, by turning on switch SW5, it is possible to determine the illuminance and switch the conversion efficiency in pixel PIX5I. In pixel PIX5J, by turning on switch SW6, it is possible to determine the illuminance and switch the conversion efficiency in pixel PIX5J.

[0245] FIG. 35 is a diagram showing a sixth example of a circuit configuration of a pixel provided in the solid-state imaging device according to the fifth embodiment.

[0246] In the figure, in this solid-state imaging device, pixels PIX5K and PIX5L are added to the pixels PIX5E and PIX5F in Fig. 32. Other configurations of the sixth example of the solid-state imaging device of the fifth embodiment are similar to the configuration of the solid-state imaging device of the above-described first embodiment.

[0247] The pixels PIX5K and PIX5L can be configured in the same manner as the pixel PIX5F, except that switches SW7 and SW8 are added to the pixels PIX5K and PIX5L, respectively.

[0248] The switch SW7 is connected between the source of the amplifier transistor 125 of the pixel PIX5K and the inputs of the sample and hold capacitors C1 and C2. The switch SW8 is connected between the source of the amplifier transistor 125 of the pixel PIX5L and the inputs of the sample and hold capacitors C1 and C2. The inputs of the sample and hold capacitors C1 and C2 of the pixels PIX5K and PIX5L are connected to the input of the comparator 131 and the current source 130. In this case, the pixels PIX5E, PIX5F, PIX5K, and PIX5L share not only the reset transistor 126, amplifier transistor 127, and selection transistor 128, but also the comparator 131 and current source 130.

[0249] Here, in pixel PIX5K, by turning on switch SW7, it is possible to perform illuminance determination and switching of conversion efficiency in pixel PIX5K. In pixel PIX5L, by turning on switch SW8, it is possible to perform illuminance determination and switching of conversion efficiency in pixel PIX5K.

[0250] As described above, in the fifth embodiment, the reset transistor 126, the amplification transistor 127, and the selection transistor 128 used for the global shutter operation are shared by multiple pixels. This makes it possible to switch the readout level V1 based on the determination result of the readout level V1 determined within the pixel while suppressing an increase in the circuit size of the pixel capable of the global shutter operation. Furthermore, by sharing the comparator 131 that determines the readout level V1 of the pixel signal among multiple pixels, it is possible to reduce the circuit size of the pixel capable of the global shutter operation while making it possible to switch the readout level V1 based on the determination result of the readout level V1 determined within the pixel.

[0251] In the fifth embodiment described above, an example was shown in which part of the circuit configuration was applied to two-pixel sharing or four-pixel sharing, but it may also be applied to eight-pixel sharing or other numbers of shared pixels.

[0252] 6. Sixth Embodiment In the first embodiment described above, the switching transistor 124 is controlled based on the determination result of the read level V1 determined in the pixel PIX capable of performing the global shutter operation. In this sixth embodiment, the sample and hold transistor ST2 is controlled based on the determination result of the read level V1 determined in the pixel PIX capable of performing the global shutter operation.

[0253] FIG. 36 is a diagram showing an example of a circuit configuration of a pixel provided in a solid-state imaging device according to the sixth embodiment.

[0254] 36, the pixel PIX6 includes a selector 633 instead of the selector 133 in FIG. 3. Other configurations of the pixel PIX6 are the same as those of the pixel PIX in FIG.

[0255] The selector 633 switches the timing for sampling and holding the read level V1 of the pixel signal output from the amplification transistor 125. The output of the selector 633 is connected to the gate of the sample and hold transistor ST2. At this time, the selector 633 can select either the high-efficiency sample and hold signal SDH or the low-efficiency sample and hold signal SDL as the sample and hold signal SD based on the determination result VCO of the read level V1.

[0256] FIG. 37 is a flowchart showing a pixel signal readout process of the solid-state imaging device according to the sixth embodiment.

[0257] In the figure, the processes from steps S601 to S604 are the same as the processes from steps S101 to S104 in the first embodiment described above.

[0258] Next, if the illuminance is determined to be low, the switching transistor 124 is turned off to maintain high conversion efficiency. Then, the sample-and-hold transistor ST2 is turned on, and the D-phase level output from the amplification transistor 125 at high conversion efficiency is sampled by the sample-and-hold capacitor C2 (step S607).

[0259] Next, the switching transistor 124 is turned on to switch to low conversion efficiency (step S605). If the illuminance is determined to be high, the sample-and-hold transistor ST2 is turned on, and the D-phase level output from the amplifying transistor 125 at low conversion efficiency is sampled by the sample-and-hold capacitor C2 (step S606).

[0260] FIG. 38 is a timing chart showing an example of an operation period assigned to one frame of the solid-state imaging device according to the sixth embodiment.

[0261] In the figure, a global shutter period GS2 and a readout period RD are allocated to one frame. During the global shutter period GS2, a global shutter operation is simultaneously performed for all pixels PIX6 arranged in the pixel array section 111. During the global shutter operation, P-phase sampling and illuminance determination are simultaneously performed for each pixel PIX arranged in the pixel array section 111. Furthermore, during the global shutter operation, high conversion efficiency D-phase sampling or low conversion efficiency D-phase sampling is simultaneously performed for each pixel PIX6 arranged in the pixel array section 111, based on the illuminance determined for each pixel PIX6.

[0262] In the readout period RD, P-phase readout and D-phase readout are performed for each row of the pixels PIX6 arranged in the pixel array section 111.

[0263] FIG. 39 is a timing chart showing an example of waveforms at various parts during low illuminance in the global shutter operation of the pixel according to the sixth embodiment.

[0264] In the figure, this global shutter operation includes a PD reset period P61, an exposure period P62, an FD reset period P63, a P-phase sampling period P64, a charge transfer period P65, an illuminance determination period P66, a high conversion efficiency D-phase sampling period P67, a conversion efficiency switching period P68, and a low conversion efficiency D-phase sampling period P69.

[0265] The high-efficiency sample-and-hold signal SDH is set to a high level during a high-conversion-efficiency D-phase sampling period P67, and the low-efficiency sample-and-hold signal SDL is set to a high level during a low-conversion-efficiency D-phase sampling period P69.

[0266] During the PD reset period P61, the reset signal RB, the sample-and-hold signals SR and SD, the active signal CM, the high-efficiency sample-and-hold signal SDH, and the low-efficiency sample-and-hold signal SDL are all set to low. At this time, the reset transistor 126 and the sample-and-hold transistors ST1 and ST2 are turned off, the comparator 131 and the latch circuit 132 are inactivated, and the output of the selector 133 is set to low. Then, the transfer signal TRG, the reset signal RST, and the switching signal FDG rise, turning on the transfer transistor 122, the reset transistor 123, and the switching transistor 124. At this time, the conversion efficiency of the amplification transistor 125 is set to low, and the charges in the photodiode PD and the floating diffusion FD1 are reset.

[0267] During the exposure period P62, the transfer signal TRG, the reset signal RST, and the switching signal FDG fall, turning off the transfer transistor 122, the reset transistor 123, and the switching transistor 124. At this time, the conversion efficiency of the amplification transistor 125 is set to high conversion efficiency, and charge is accumulated in the photodiode PD according to the amount of incident light.

[0268] In the FD reset period P63, the reset signal RST and the switching signal FDG rise, turning on the reset transistor 123 and the switching transistor 124. At this time, the conversion efficiency of the amplification transistor 125 is set to low, and the charge of the floating diffusion FD1 is reset.

[0269] During the P-phase sampling period P64, the reset signal RB and the sample-and-hold signal SR rise, turning on the reset transistor 126 and the sample-and-hold transistor ST1. At this time, a charge corresponding to the P-phase level output from the amplifier transistor 125 is held in the sample-and-hold capacitor C1.

[0270] During the charge transfer period P65, the transfer signal TRG rises, turning on the transfer transistor 122. At this time, the charge accumulated in the photodiode PD is transferred to the floating diffusion FD1. A voltage corresponding to the charge transferred to the floating diffusion FD1 is then applied to the gate of the amplification transistor 125. Then, based on the source follower operation between the amplification transistor 125 and the current source 130, a read level V1 corresponding to the voltage applied to the gate of the amplification transistor 125 is input to the comparator 131.

[0271] In an illuminance determination period P66, an active signal CM rises, and the comparator 131 and the latch circuit 132 are activated. Then, the comparator 131 compares the read level V1 of the pixel signal with a reference voltage VRF, and the determination result VCO of the read level V1 is latched in the latch circuit 132. At low illuminance, the read level V1 of the pixel signal becomes less than the reference voltage VRF, and the determination result VCO is set to a low level.

[0272] During the high conversion efficiency D-phase sampling period P67, the high efficiency sample and hold signal SDH rises. Here, because the determination result VCO is set to a low level, the high efficiency sample and hold signal SDH is selected by the selector 633. As a result, the sample and hold signal SD rises, turning on the sample and hold transistor ST2. Also, the reset signal RB rises, turning on the reset transistor 126. At this time, a charge corresponding to the high conversion efficiency D-phase level output from the amplifier transistor 125 is held in the sample and hold capacitor C2. Thereafter, the high efficiency sample and hold signal SDH, the sample and hold signal SD, and the reset signal RB fall.

[0273] In the conversion efficiency switching period P68, the switching signal FDG rises, turning on the switching transistor 124. At this time, the conversion efficiency of the amplifying transistor 125 is set to low conversion efficiency.

[0274] During the low-conversion-efficiency D-phase sampling period P69, the low-efficiency sample-and-hold signal SDL rises. Here, because the determination result VCO is set to a low level, the selector 633 does not select the low-efficiency sample-and-hold signal SDL, and the high-efficiency sample-and-hold signal SDH remains selected. Therefore, the sample-and-hold signal SD remains low, and the sample-and-hold transistor ST2 remains off. Therefore, the charge corresponding to the low-conversion-efficiency D-phase level output from the amplifier transistor 125 is not held in the sample-and-hold capacitor C2, and the charge corresponding to the high-conversion-efficiency D-phase level output from the amplifier transistor 125 remains held in the sample-and-hold capacitor C2.

[0275] FIG. 40 is a timing chart showing an example of waveforms at various parts during high illuminance in the global shutter operation of the pixel according to the sixth embodiment.

[0276] In the same figure, the operations of the PD reset period P61, exposure period P62, FD reset period P63, P-phase sampling period P64, charge transfer period P65, and illuminance determination period P66 during high illuminance are similar to the operations of the PD reset period P61, exposure period P62, FD reset period P63, P-phase sampling period P64, charge transfer period P65, and illuminance determination period P66 during low illuminance.

[0277] During the high-conversion-efficiency D-phase sampling period P67, the high-efficiency sample-and-hold signal SDH rises. Here, during the illuminance determination period P16, if the illuminance is high, the pixel signal readout level V1 is less than the reference voltage VRF, and the determination result VCO is set to a high level. At this time, during the high-conversion-efficiency D-phase sampling period P67, the high-efficiency sample-and-hold signal SDH is not selected. Therefore, the sample-and-hold signal SD remains low, and the sample-and-hold transistor ST2 remains off. Therefore, the charge corresponding to the high-conversion-efficiency D-phase level output from the amplification transistor 125 is not held in the sample-and-hold capacitor C2.

[0278] In the conversion efficiency switching period P68, the switching signal FDG rises, turning on the switching transistor 124. At this time, the conversion efficiency of the amplifying transistor 125 is set to low conversion efficiency.

[0279] During the low conversion efficiency D-phase sampling period P69, the low-efficiency sample-and-hold signal SDL rises. Here, since the determination result VCO is set to a high level, the low-efficiency sample-and-hold signal SDL is selected by the selector 633 during the low conversion efficiency D-phase sampling period P69. As a result, the sample-and-hold signal SD rises, turning on the sample-and-hold transistor ST2. Also, the reset signal RB rises, turning on the reset transistor 126. At this time, a charge corresponding to the low conversion efficiency D-phase level output from the amplification transistor 125 is held in the sample-and-hold capacitor C2. Thereafter, the low-efficiency sample-and-hold signal SDL, the sample-and-hold signal SD, and the reset signal RB fall.

[0280] In this way, in the sixth embodiment described above, the sample and hold transistor ST2 is controlled based on the determination result of the read level V1 determined in the pixel PIX6 capable of global shutter operation. This makes it possible to read out the LCG output or HCG output from the pixel PIX6 according to the illuminance, without reading out each of the LCG output and HCG output from the pixel PIX6. This makes it possible to generate an HDR image while suppressing an increase in the readout period RD according to switching of the conversion efficiency.

[0281] 7. Seventh Embodiment In the above-described first embodiment, the conversion efficiency is switched based on the determination result of the readout level V1 determined in the pixel PIX capable of global shutter operation. In this seventh embodiment, the high-sensitivity photodiode and the low-sensitivity photodiode are switched based on the determination result of the readout level V1 determined in the pixel PIX capable of global shutter operation.

[0282] FIG. 41 is a diagram showing an example of a circuit configuration of a pixel provided in a solid-state imaging device according to the seventh embodiment.

[0283] 41 , pixel PIX7 is similar to pixel PIX6 in FIG. 36 except that a low-sensitivity photodiode PD2, a transfer transistor 722, a reset transistor 723, an amplifier transistor 725, and switches SW11 and SW12 are added. Furthermore, pixel PIX7 is similar to pixel PIX6 in that the switching transistor 124 and capacitor C0 are removed from pixel PIX6. At this time, the reset transistor 123 is connected to a floating diffusion FD1. Furthermore, photodiode PD is used as high-sensitivity photodiode PD1. Furthermore, a high-sensitivity sample-and-hold signal SDHA and a low-sensitivity sample-and-hold signal SDLA are input to selector 133 instead of the high-efficiency sample-and-hold signal SDH and the low-efficiency sample-and-hold signal SDL.

[0284] In this case, the high-sensitivity photodiode PD1, the low-sensitivity photodiode PD2, the transfer transistors 122, 722, the reset transistors 123, 723, the amplification transistors 125, 725, and the switches SW11, SW12 can form an illuminance switching exposure unit PIX7A. Other configurations of the pixel PIX7 are similar to those of the pixel PIX6 in FIG.

[0285] The low-sensitivity photodiode PD2 performs photoelectric conversion and accumulates the photoelectrically converted charge. The area of ​​the light-receiving surface of the low-sensitivity photodiode PD2 can be smaller than the area of ​​the light-receiving surface of the high-sensitivity photodiode PD1. The transfer transistor 722 transfers the charge accumulated in the low-sensitivity photodiode PD2 to the floating diffusion FD3. The reset transistor 723 resets the low-sensitivity photodiode PD2 and the floating diffusion FD3. The amplification transistor 725 outputs a signal corresponding to the potential of the floating diffusion FD3.

[0286] The transfer transistor 722 is connected between the cathode of the low-sensitivity photodiode PD2 and the floating diffusion FD3. The reset transistor 723 is connected between the power supply potential VDD and the floating diffusion FD3. The gate of the amplification transistor 725 is connected to the floating diffusion FD3. A transfer signal TRG is applied to the gate of the transfer transistor 722. A reset signal RST is applied to the gate of the reset transistor 723.

[0287] The switch SW11 is connected between the source of the amplifier transistor 125 and the inputs of the sample-and-hold capacitors C1 and C2. The switch SW11 is switched based on a switching signal SL1. The switch SW12 is connected between the source of the amplifier transistor 725 and the inputs of the sample-and-hold capacitors C1 and C2. The switch SW12 is switched based on a switching signal SL2. The inputs of the sample-and-hold capacitors C1 and C2 are connected to the inputs of the comparator 131 and the current source 130.

[0288] FIG. 42 is a flowchart showing a pixel signal readout process of the solid-state imaging device according to the seventh embodiment.

[0289] In the same figure, the reset transistors 123, 723 and the transfer transistors 122, 722 are turned on, and the floating diffusions FD1, FD3 are reset (step S701). Next, the reset transistors 123, 723 and the transfer transistors 122, 722 are turned off, and the high-sensitivity photodiode PD1 and the low-sensitivity photodiode PD2 are exposed to light (step S702).

[0290] Next, the reset transistors 123 and 723 are turned on, and the floating diffusions FD1 and FD3 are reset (step S703).

[0291] Next, the switch SW11 is turned on, and the source of the amplifying transistor 125 is connected to the input of the comparator 131 and the inputs of the sample-and-hold capacitors C1 and C2 (step S704).

[0292] Next, the sample-and-hold transistor ST1 is turned on, and the P-phase level output from the amplifying transistor 125 is sampled by the sample-and-hold capacitor C1 (step S705).

[0293] Next, the transfer transistor 122 is turned on, and the charge accumulated in the high-sensitivity photodiode PD1 is transferred to the floating diffusion FD1 (step S706).

[0294] Next, the comparator 131 determines the illuminance based on the readout level V1 of the pixel signal output from the amplifying transistor 125 (step S707). If the illuminance is low, the switch SW11 is kept on, and the source of the amplifying transistor 125 is kept connected to the input of the comparator 131 and the inputs of the sample-and-hold capacitors C1 and C2. Then, the sample-and-hold transistor ST2 is turned on, and the high-sensitivity D-phase level output from the amplifying transistor 125 is sampled by the sample-and-hold capacitor C2 (step S710).

[0295] Next, the switch SW11 is turned off and the switch SW12 is turned on, connecting the source of the amplifier transistor 725 to the input of the comparator 131 and the inputs of the sample-and-hold capacitors C1 and C2 (step S708). Then, when the illuminance is high, the sample-and-hold transistor ST2 is turned on, and the low-sensitivity D-phase level output from the amplifier transistor 725 is sampled by the sample-and-hold capacitor C2 (step S709).

[0296] FIG. 43 is a timing chart showing an example of waveforms at various parts during low illuminance in the global shutter operation of the pixel according to the seventh embodiment.

[0297] In the figure, this global shutter operation includes a PD reset period P71, an exposure period P72, an FD reset period P73, a P-phase sampling period P74, a charge transfer period P75, an illuminance determination period P76, a high-sensitivity D-phase sampling period P77, an illuminance switching period P78, and a low-sensitivity D-phase sampling period P79.

[0298] The high-sensitivity sample-and-hold signal SDHA is set to a high level during the high-sensitivity D-phase sampling period P77. The low-sensitivity sample-and-hold signal SDLA is set to a high level during the low-sensitivity D-phase sampling period P79. The switch SW11 is switched based on the switching signal SL1. The switch SW12 is switched based on the switching signal SL2.

[0299] During the PD reset period P71, the reset signal RB, sample-and-hold signals SR and SD, active signal CM, high-sensitivity sample-and-hold signal SDHA, and low-sensitivity sample-and-hold signal SDLA are all set to low. At this time, the reset transistor 126 and sample-and-hold transistors ST1 and ST2 are turned off, the comparator 131 and latch circuit 132 are deactivated, and the output of the selector 133 is set to low. Then, the transfer signal TRG, reset signal RST, and switching signals SL1 and SL2 rise, turning on the transfer transistors 122 and 722, the reset transistors 123 and 723, and the switches SW11 and SW12. At this time, the charges in the high-sensitivity photodiode PD1, the low-sensitivity photodiode PD2, and the floating diffusions FD1 and FD3 are reset.

[0300] During the exposure period P72, the transfer signal TRG, the reset signal RST, and the switching signals SL1 and SL2 fall, turning off the transfer transistors 122 and 722, the reset transistors 123 and 723, and the switches SW11 and SW12. At this time, charges are accumulated in the high-sensitivity photodiode PD1 and the low-sensitivity photodiode PD2 according to the amount of incident light.

[0301] In the FD reset period P73, the reset signal RST and the switching signals SL1 and SL2 rise, turning on the reset transistors 123 and 723 and the switches SW11 and SW12. At this time, the charges in the floating diffusions FD1 and FD3 are reset.

[0302] During the P-phase sampling period P74, the switching signal SL2 falls, turning off the switch SW12. The reset signal RB and the sample-and-hold signal SR rise, turning on the reset transistor 126 and the sample-and-hold transistor ST1. At this time, a charge corresponding to the P-phase level output from the amplifier transistor 125 is held in the sample-and-hold capacitor C1.

[0303] During the charge transfer period P75, the transfer signal TRG rises, turning on the transfer transistors 122 and 722. At this time, the charge accumulated in the high-sensitivity photodiode PD1 is transferred to the floating diffusion FD1, and the charge accumulated in the low-sensitivity photodiode PD2 is transferred to the floating diffusion FD3. Voltages corresponding to the charges transferred to the floating diffusions FD1 and FD3 are applied to the gates of the amplifier transistors 125 and 725, respectively. Since the switch SW11 is on and the switch SW12 is off, a source-follower operation is performed between the amplifier transistor 125 and the current source 130. Based on the source-follower operation between the amplifier transistor 125 and the current source 130, a read level V1 corresponding to the voltage applied to the gate of the amplifier transistor 125 is input to the comparator 131.

[0304] In an illuminance determination period P76, an active signal CM rises, and the comparator 131 and the latch circuit 132 are activated. Then, the comparator 131 compares the read level V1 of the pixel signal with a reference voltage VRF, and the determination result VCO of the read level V1 is latched in the latch circuit 132. At low illuminance, the read level V1 of the pixel signal becomes less than the reference voltage VRF, and the determination result VCO is set to a low level.

[0305] During the high-sensitivity D-phase sampling period P77, the high-sensitivity sample-and-hold signal SDHA rises. Here, because the determination result VCO is set to a low level, the high-sensitivity sample-and-hold signal SDHA is selected by the selector 633. As a result, the sample-and-hold signal SD rises, turning on the sample-and-hold transistor ST2. Also, the reset signal RB rises, turning on the reset transistor 126. At this time, a charge corresponding to the high-illuminance D-phase level output from the amplification transistor 125 is held in the sample-and-hold capacitor C2. Thereafter, the switching signal SL1, the high-sensitivity sample-and-hold signal SDHA, the sample-and-hold signal SD, and the reset signal RB fall.

[0306] During the illuminance switching period P78, the switching signal SL2 rises. At this time, the switch SW12 is turned on, and a source follower operation is performed between the amplifying transistor 725 and the current source 130. Based on the source follower operation between the amplifying transistor 725 and the current source 130, a read level V1 corresponding to the voltage applied to the gate of the amplifying transistor 725 is input to the sample-and-hold capacitors C1 and C2.

[0307] During the low-sensitivity D-phase sampling period P79, the low-sensitivity sample-and-hold signal SDLA rises. Here, because the determination result VCO is set to a low level, the selector 633 does not select the low-sensitivity sample-and-hold signal SDLA as the sample-and-hold signal SD, and the sample-and-hold transistor ST2 remains off. Therefore, the charge corresponding to the low-illuminance D-phase level output from the amplifier transistor 125 is not held in the sample-and-hold capacitor C2.

[0308] FIG. 44 is a timing chart showing an example of waveforms at various parts during high illuminance in the global shutter operation of the pixel according to the seventh embodiment.

[0309] In the figure, the operations during the PD reset period P71, exposure period P72, FD reset period P73, P-phase sampling period P74, charge transfer period P75, and illuminance determination period P76 at high illuminance are the same as the operations during the D reset period P71, exposure period P72, FD reset period P73, P-phase sampling period P74, charge transfer period P75, and illuminance determination period P76 at low illuminance. However, at high illuminance, the readout level V1 of the pixel signal becomes equal to or higher than the reference voltage VRF, and the determination result VCO is set to a high level.

[0310] During the high-sensitivity D-phase sampling period P77, the high-sensitivity sample-and-hold signal SDHA rises. Here, because the determination result VCO is set to a high level, the high-sensitivity sample-and-hold signal SDHA is not selected as the sample-and-hold signal SD by the selector 633, and the sample-and-hold transistor ST2 remains off. Therefore, the charge corresponding to the high-illuminance D-phase level output from the amplifier transistor 125 is not held in the sample-and-hold capacitor C2.

[0311] During the illuminance switching period P78, the switching signal SL2 rises. At this time, the switch SW12 is turned on, and a source follower operation is performed between the amplifying transistor 725 and the current source 130. Based on the source follower operation between the amplifying transistor 725 and the current source 130, a read level V1 corresponding to the voltage applied to the gate of the amplifying transistor 725 is input to the sample-and-hold capacitors C1 and C2.

[0312] During the low-sensitivity D-phase sampling period P79, the low-sensitivity sample-and-hold signal SDLA rises. Here, because the determination result VCO is set to a high level, the low-sensitivity sample-and-hold signal SDLA is selected by the selector 633 as the sample-and-hold signal SD. As a result, the sample-and-hold signal SD rises, turning on the sample-and-hold transistor ST2. Also, the reset signal RB rises, turning on the reset transistor 126. At this time, a charge corresponding to the low-illuminance D-phase level output from the amplification transistor 725 is held in the sample-and-hold capacitor C2. Thereafter, the switching signal SL2, the low-sensitivity sample-and-hold signal SDLA, the sample-and-hold signal SD, and the reset signal RB fall.

[0313] As described above, in the seventh embodiment, the high-sensitivity photodiode PD1 and the low-sensitivity photodiode PD2 are switched based on the determination result of the readout level V1 determined in the pixel PIX7 capable of global shutter operation. This makes it possible to read from the high-sensitivity photodiode PD1 or the low-sensitivity photodiode PD2 according to the illuminance, without reading from the pixel PIX7 separately for the high-sensitivity photodiode PD1 and the low-sensitivity photodiode PD2. Therefore, even when switching of the conversion efficiency is not performed, it is possible to generate an HDR image while suppressing a decrease in frame rate.

[0314] In the seventh embodiment described above, an example has been shown in which the high-sensitivity photodiode PD1 and the low-sensitivity photodiode PD2 are switched based on the determination result of the readout level V1. In addition to this, the configuration of the seventh embodiment described above may be applied to a LOFIC pixel or a pixel with switchable conversion efficiency. The pixel with switchable conversion efficiency may be any of the pixels described in the first to sixth embodiments.

[0315] 8. Eighth Embodiment In the above-described first embodiment, the conversion efficiency is switched based on the determination result of the read level V1 determined in the pixel PIX capable of global shutter operation. In this eighth embodiment, the long exposure section and the short exposure section are switched based on the determination result of the read level V1 determined in the pixel of the illuminance switchable exposure section PIX7A capable of global shutter operation.

[0316] FIG. 45 is a diagram showing an example of a circuit configuration of a pixel provided in a solid-state imaging device according to the eighth embodiment.

[0317] 45 , pixel PIX8 includes a long-time exposure unit PIX8A and a short-time exposure unit PIX8B instead of the illuminance switching exposure unit PIX7A of the seventh embodiment described above. Furthermore, a long-time accumulation sample-and-hold signal SDHB and a short-time accumulation sample-and-hold signal SDLB are input to the selector 133 instead of the high-sensitivity sample-and-hold signal SDHA and the low-sensitivity sample-and-hold signal SDLA. Other configurations of pixel PIX8 are similar to the configuration of pixel PIX7 of the seventh embodiment described above.

[0318] The long-time exposure unit PIX8A is set to a long exposure time. The long-time exposure unit PIX8A includes photodiodes PD3 and PD4 instead of the high-sensitivity photodiode PD1 and low-sensitivity photodiode PD2 of the seventh embodiment. The sensitivities of the photodiodes PD3 and PD4 may be equal to each other.

[0319] In the long-time exposure unit PIX8A, a transfer signal TRG1 is applied to the gates of the transfer transistors 122 and 722. A reset signal RST1 is applied to the gates of the reset transistors 123 and 723. The switches SW11 and SW12 are switched based on a switching signal SL1.

[0320] The short-time exposure unit PIX8B is set to a short exposure time. The short-time exposure unit PIX8B can be configured in the same manner as the long-time exposure unit PIX8A. In this case, the exposure start time of the short-time exposure unit PIX8B can be delayed from the exposure start time of the long-time exposure unit PIX8A, thereby shortening the exposure time of the short-time exposure unit PIX8B.

[0321] In the short-time exposure unit PIX8B, a transfer signal TRG2 is applied to the gates of the transfer transistors 122 and 722. A reset signal RST2 is applied to the gates of the reset transistors 123 and 723. The switches SW11 and SW12 are switched based on a switching signal SL2.

[0322] Although the example in which two photodiodes PD3 and PD4 are provided in each of the long-time exposure unit PIX8A and the short-time exposure unit PIX8B has been shown, only one photodiode PD3 may be provided.

[0323] FIG. 46 is a flowchart showing a pixel signal readout process of the solid-state imaging device according to the eighth embodiment.

[0324] In the figure, the reset transistors 123 and 723 and the transfer transistors 122 and 722 of the long-time exposure unit PIX8A are turned on, and the floating diffusions FD1 and FD3 are reset (step S801A).

[0325] Next, the reset transistors 123 and 723 and the transfer transistors 122 and 722 of the long-time exposure unit PIX8A are turned off, and exposure of the long-time exposure unit PIX8A begins (step S802A).

[0326] Next, the reset transistors 123 and 723 and the transfer transistors 122 and 722 of the short-time exposure unit PIX8B are turned on, and the floating diffusions FD1 and FD3 are reset (step S801B).

[0327] Next, the reset transistors 123 and 723 and the transfer transistors 122 and 722 of the short-time exposure unit PIX8B are turned off, and exposure of the short-time exposure unit PIX8B starts (step S802B).

[0328] Next, the reset transistors 123 and 723 of the long-time exposure unit PIX8A and the short-time exposure unit PIX8B are turned on, and the floating diffusions FD1 and FD3 are reset (step S803).

[0329] Next, the switches SW11 and SW12 of the long exposure unit PIX8A are turned on, and the sources of the amplification transistors 125 and 725 are connected to the input of the comparator 131 and the inputs of the sample-and-hold capacitors C1 and C2 (step S804).

[0330] Next, the sample-and-hold transistor ST1 is turned on, and the P-phase level output from the amplifying transistors 125 and 725 of the long-time exposure unit PIX8A is sampled by the sample-and-hold capacitor C1 (step S805).

[0331] Next, the transfer transistors 122 and 722 of the long-time exposure unit PIX8A and the short-time exposure unit PIX8B are turned on, and the charges accumulated in the photodiodes PD3 and PD4 are transferred to the floating diffusions FD1 and FD3 (step S806).

[0332] Next, the comparator 131 determines the illuminance based on the readout level V1 of the pixel signal output from the amplifying transistors 125 and 725 of the long-time exposure unit PIX8A (step S807). If the illuminance is low, the switches SW11 and SW12 of the long-time exposure unit PIX8A are kept on, and the source of the amplifying transistor 125 is kept connected to the input of the comparator 131 and the inputs of the sample-and-hold capacitors C1 and C2. Then, the sample-and-hold transistor ST2 is turned on, and the long-accumulated D-phase level output from the amplifying transistor 125 is sampled by the sample-and-hold capacitor C2 (step S810).

[0333] Next, the switches SW11 and SW12 of the long-time exposure unit PIX8A are turned off, and the switches SW11 and SW12 of the short-time exposure unit PIX8B are turned on, so that the sources of the amplification transistors 125 and 725 of the short-time exposure unit PIX8B are connected to the inputs of the comparator 131 and the sample-and-hold capacitors C1 and C2 (step S808). Then, when the illuminance is high, the sample-and-hold transistor ST2 is turned on, and the D-phase level of the short-time accumulation output from the amplification transistors 125 and 725 of the short-time exposure unit PIX8B is sampled to the sample-and-hold capacitor C2 (step S809).

[0334] FIG. 47 is a timing chart showing an example of waveforms at various parts during low illuminance in the global shutter operation of the pixel according to the eighth embodiment.

[0335] In the figure, in this global shutter operation, a long accumulation PD reset period P81, a short accumulation PD reset period P82, an FD reset period P83, a P-phase sampling period P84, a charge transfer period P85, an illuminance determination period P86, a long accumulation D-phase sampling period P87, an exposure section switching period P88, and a short accumulation D-phase sampling period P89 are provided.

[0336] Note that the long accumulation sample hold signal SDHB is set to a high level in the long accumulation D-phase sampling period P87. The short accumulation sample hold signal SDLB is set to a high level in the short accumulation D-phase sampling period P89. The switches SW11 and SW12 of the long time exposure unit PIX8A are switched based on the switching signal SL1. The switches SW11 and SW12 of the short time exposure unit PIX8B are switched based on the switching signal SL2.

[0337] During the long-term accumulation PD reset period P81, the reset signal RB, the sample and hold signals SR and SD, the active signal CM, the long-term accumulation sample and hold signal SDHB, and the short-term accumulation sample and hold signal SDLB are set to a low level. At this time, the reset transistor 126 and the sample and hold transistors ST1 and ST2 are turned off, the comparator 131 and the latch circuit 132 are inactivated, and the output of the selector 133 is set to a low level. Then, the transfer signal TRG1, the reset signal RST1, and the switching signals SL1 and SL2 of the long-term exposure unit PIX8A rise, and the transfer transistors 122 and 722, the reset transistors 123 and 723, and the switches SW11 and SW12 are turned on. At this time, the charges of the photodiodes PD3 and PD4 and the floating diffusions FD1 and FD3 of the long-term exposure unit PIX8A are reset.

[0338] Thereafter, in the long-time exposure unit PIX8A, the transfer signal TRG1, the reset signal RST1, and the switching signals SL1 and SL2 fall, turning off the transfer transistors 122 and 722, the reset transistors 123 and 723, and the switches SW11 and SW12. At this time, charges are accumulated in the photodiodes PD3 and PD4 of the long-time exposure unit PIX8A according to the amount of incident light.

[0339] In the short-accumulation PD reset period P82, the reset signal RB, the sample and hold signals SR and SD, the active signal CM, the long-accumulation sample and hold signal SDHB, and the short-accumulation sample and hold signal SDLB are set to a low level. At this time, the reset transistor 126 and the sample and hold transistors ST1 and ST2 are turned off, the comparator 131 and the latch circuit 132 are inactivated, and the output of the selector 133 is set to a low level. Then, the transfer signal TRG2 and the reset signal RST2 of the short-accumulation unit PIX8B rise, and the transfer transistors 122 and 722 and the reset transistors 123 and 723 are turned on. At this time, the charges of the photodiodes PD3 and PD4 and the floating diffusions FD1 and FD3 of the short-accumulation unit PIX8B are reset.

[0340] Thereafter, in the short-time exposure unit PIX8B, the transfer signal TRG2 and the reset signal RST2 fall, turning off the transfer transistors 122 and 722 and the reset transistors 123 and 723. At this time, charges are accumulated in the photodiodes PD3 and PD4 of the short-time exposure unit PIX8B according to the amount of incident light.

[0341] During the FD reset period P83, the reset signals RST1, RST2 and the switching signals SL1, SL2 for the long-time exposure unit PIX8A and the short-time exposure unit PIX8B rise, turning on the reset transistor 123 and the switches SW11, SW12. At this time, the charges of the floating diffusions FD1, FD3 for the long-time exposure unit PIX8A and the short-time exposure unit PIX8B are reset.

[0342] During the P-phase sampling period P84, the switching signal SL2 of the short-time exposure unit PIX8B falls, turning off the switches SW11 and SW12. The reset signal RB and the sample-and-hold signal SR rise, turning on the reset transistor 126 and the sample-and-hold transistor ST1. At this time, a charge corresponding to the P-phase level output from the amplification transistors 125 and 725 of the long-time exposure unit PIX8A is held in the sample-and-hold capacitor C1.

[0343] During the charge transfer period P85, the transfer signals TRG1 and TRG2 for the long-time exposure unit PIX8A and the short-time exposure unit PIX8B rise, turning on the transfer transistors 122 and 722. At this time, the charges accumulated in the photodiodes PD3 and PD4 of the long-time exposure unit PIX8A and the short-time exposure unit PIX8B are transferred to the floating diffusions FD1 and FD3. Voltages corresponding to the charges transferred to the floating diffusions FD1 and FD3 of the long-time exposure unit PIX8A and the short-time exposure unit PIX8B are applied to the gates of the amplification transistors 125 and 725, respectively. Because the switches SW11 and SW12 of the long-time exposure unit PIX8A are on and the switches SW11 and SW12 of the short-time exposure unit PIX8B are off, a source-follower operation is performed between the amplification transistors 125 and 725 of the long-time exposure unit PIX8A and the current source 130. Based on the source follower operation between the amplifying transistors 125 and 725 of the long-time exposure unit PIX8A and the current source 130, a read level V1 according to the voltage applied to the gates of the amplifying transistors 125 and 725 is input to the comparator 131.

[0344] In an illuminance determination period P86, an active signal CM rises, and the comparator 131 and the latch circuit 132 are activated. Then, the comparator 131 compares the read level V1 of the pixel signal with a reference voltage VRF, and the determination result VCO of the read level V1 is latched in the latch circuit 132. At low illuminance, the read level V1 of the pixel signal becomes equal to or higher than the reference voltage VRF, and the determination result VCO is set to a low level.

[0345] In the long-term accumulation D-phase sampling period P87, the long-term accumulation sample and hold signal SDHB rises. Here, since the determination result VCO is set to the low level, the long-term accumulation sample and hold signal SDHB is selected by the selector 633. Therefore, the sample and hold signal SD rises, and the sample and hold transistor ST2 is turned on. In addition, the reset signal RB rises, and the reset transistor 126 is turned on. At this time, the charge corresponding to the D-phase level of the long-term accumulation output from the amplification transistors 125 and 725 of the long-term exposure unit PIX8A is held in the sample and hold capacitor C2. Thereafter, the switching signal SL1, the long-term accumulation sample and hold signal SDHB, the sample and hold signal SD, and the reset signal RB of the long-term exposure unit PIX8A fall.

[0346] During the illuminance switching period P88, the switching signal SL2 for the short-time exposure unit PIX8B rises. At this time, the switches SW11 and SW12 for the short-time exposure unit PIX8B are turned on, and a source-follower operation is performed between the amplifying transistors 125 and 725 and the current source 130. Then, based on the source-follower operation between the amplifying transistors 125 and 725 for the short-time exposure unit PIX8B and the current source 130, a read level V1 corresponding to the voltage applied to the gate of the amplifying transistor 125 and 725 is input to the sample-and-hold capacitors C1 and C2.

[0347] In the short accumulation D-phase sampling period P89, the short accumulation sample hold signal SDLB rises. Here, since the determination result VCO is set to the low level, the low-sensitivity sample hold signal SDLA is not selected as the sample hold signal SD by the selector 633, and the sample hold transistor ST2 is maintained off. For this reason, the charge corresponding to the D-phase level of short accumulation output from the amplification transistors 125, 725 of the short exposure unit PIX8B is not held in the sample hold capacitance C2.

[0348] FIG. 48 is a timing chart showing an example of waveforms at various parts during high illuminance in the global shutter operation of the pixel according to the eighth embodiment.

[0349] 12, the operations of the long accumulation PD reset period P81, the short accumulation PD reset period P82, the FD reset period P83, the P-phase sampling period P84, the charge transfer period P85, and the illuminance determination period P86 at the time of high illuminance are similar to the operations of the long accumulation PD reset period P81, the short accumulation PD reset period P82, the FD reset period P83, the P-phase sampling period P84, the charge transfer period P85, and the illuminance determination period P86 at the time of low illuminance. However, at the time of high illuminance, the readout level V1 of the pixel signal becomes less than the reference voltage VRF, and the determination result VCO is set to a high level.

[0350] In the long accumulation D-phase sampling period P87, the long accumulation sample and hold signal SDHB rises. Here, since the determination result VCO is set to a high level, the long accumulation sample and hold signal SDHB is not selected as the sample and hold signal SD by the selector 633, and the sample and hold transistor ST2 is maintained off. Therefore, the charge corresponding to the D-phase level of long accumulation output from the amplification transistors 125 and 725 of the long time exposure unit PIX8A is not held in the sample and hold capacitor C2.

[0351] During the illuminance switching period P88, the switching signal SL2 for the short-time exposure unit PIX8B rises. At this time, the switches SW11 and SW12 for the short-time exposure unit PIX8B are turned on, and a source-follower operation is performed between the amplifying transistors 125 and 725 and the current source 130. Then, based on the source-follower operation between the amplifying transistors 125 and 725 for the short-time exposure unit PIX8B and the current source 130, a read level V1 corresponding to the voltage applied to the gate of the amplifying transistor 125 and 725 is input to the sample-and-hold capacitors C1 and C2.

[0352] In the short accumulation D-phase sampling period P89, the short accumulation sample hold signal SDLB rises. Here, since the determination result VCO is set to a high level, the short accumulation sample hold signal SDLB is selected by the selector 633 as the sample hold signal SD. Therefore, the sample hold signal SD rises, and the sample hold transistor ST2 is turned on. In addition, the reset signal RB rises, and the reset transistor 126 is turned on. At this time, the charge according to the D-phase level of the short accumulation output from the amplification transistors 125 and 725 of the short exposure unit PIX8B is held in the sample hold capacitor C2. Thereafter, the switching signal SL2, the low-sensitivity sample hold signal SDLA, the sample hold signal SD, and the reset signal RB of the short exposure unit PIX8B fall.

[0353] As described above, in the eighth embodiment, the long-time exposure section PIX8A and the short-time exposure section PIX8B are switched based on the determination result of the readout level V1 determined within the pixel PIX8 capable of global shutter operation. This makes it possible to read from the long-time exposure section PIX8A or the short-time exposure section PIX8B according to the illuminance, without performing readout separately for the long-time exposure section PIX8A and the short-time exposure section PIX8B. Therefore, even when switching of the conversion efficiency is not performed, it is possible to generate an HDR image while suppressing a decrease in frame rate.

[0354] In the above-described eighth embodiment, an example has been shown in which the long-time exposure unit PIX8A and the short-time exposure unit PIX8B are switched based on the determination result of the readout level V1. In addition to this, the configuration of the above-described eighth embodiment may be applied to a LOFIC pixel or a pixel capable of switching conversion efficiency. The pixel capable of switching conversion efficiency may be any of the pixels in the above-described first to sixth embodiments.

[0355] 9. Ninth Embodiment In the above-described first embodiment, the conversion efficiency is switched based on the determination result of the read level V1 determined in the pixel PIX capable of performing the global shutter operation. In this ninth embodiment, the exposure time of the photodiode PD is switched based on the determination result of the read level V1 determined in the pixel PIX capable of performing the global shutter operation.

[0356] FIG. 49 is a diagram showing an example of a circuit configuration of a pixel provided in a solid-state imaging device according to the ninth embodiment.

[0357] In the figure, the pixel PIX9 has the switching transistor 124 and capacitor C0 removed from the pixel PIX6 of FIG. 36. At this time, the reset transistor 123 is connected to the floating diffusion FD1. Also, the long-exposure sample-and-hold signal SDHC and the short-exposure sample-and-hold signal SDLC are input to the selector 133 instead of the high-efficiency sample-and-hold signal SDH and the low-efficiency sample-and-hold signal SDL. Other configurations of the pixel PIX9 are the same as those of the pixel PIX6 of FIG. 36.

[0358] FIG. 50 is a flowchart showing a pixel signal readout process of the solid-state imaging device according to the ninth embodiment.

[0359] In the figure, the reset transistor 123 and the transfer transistor 122 are turned on, and the photodiode PD and the floating diffusion FD1 are reset (step S901).

[0360] Next, the reset transistor 123 and the transfer transistor 122 are turned off, and the photodiode PD is exposed to light for a long time (step S902).

[0361] Next, the reset transistor 123 is turned on, and the floating diffusion FD1 is reset (step S903).

[0362] Next, the sample-and-hold transistor ST1 is turned on, and the P-phase level of the long-time exposure output from the amplifying transistor 125 is sampled into the sample-and-hold capacitor C1 (step S904).

[0363] Next, the transfer transistor 122 is turned on, and the charge accumulated in the photodiode PD is transferred to the floating diffusion FD1 (step S905).

[0364] Next, the comparator 131 determines the illuminance based on the readout level V1 of the pixel signal output from the amplifying transistor 125 (step S906).

[0365] When the illuminance is low, the sample-and-hold transistor ST2 is turned on, and the D-phase level of the long-time exposure output from the amplifier transistor 125 is sampled by the sample-and-hold capacitor C2 (step S911).

[0366] Next, the reset transistor 123 and the transfer transistor 122 are turned on, and the floating diffusion FD1 is reset (step S907).

[0367] Next, the reset transistor 123 and the transfer transistor 122 are turned off, and the photodiode PD is exposed to light for a short time (step S908).

[0368] Next, the reset transistor 123 is turned on, and the floating diffusion FD1 is reset (step S909).

[0369] If the illuminance is high, the sample-and-hold transistor ST2 is turned on, and the D-phase level of the short-time exposure output from the amplifying transistor 725 is sampled in the sample-and-hold capacitor C2 (step S910).

[0370] FIG. 51 is a timing chart showing an example of an operation period assigned to one frame of the solid-state imaging device according to the ninth embodiment.

[0371] In the figure, a short exposure period EXS and a readout period RD are allocated to a frame FM. Furthermore, a long exposure period EXL is allocated across a plurality of frames FM. In the short exposure period EXS, short accumulation D-phase sampling is performed. In the long exposure period EXL, long accumulation P-phase sampling and illuminance determination are performed. Long accumulation D-phase sampling is performed between the long exposure period EXL and the short exposure period EXS.

[0372] In the readout period RD, P-phase readout and D-phase readout are performed for each row for the pixels PIX9 arranged in the pixel array section 111.

[0373] FIG. 52 is a timing chart showing an example of waveforms at various parts during low illuminance in the global shutter operation of the pixel according to the ninth embodiment.

[0374] In the figure, this global shutter operation includes a PD reset period P91, a long-time exposure period P92, an FD reset period P93, a P-phase sampling period P94, a charge transfer period P95, an illuminance determination period P96, a long-time exposure D-phase sampling period P97, a PD reset period P98, a short-time exposure period P99, an FD reset period P100, a charge transfer period P101, and a short-time exposure D-phase sampling period P102.

[0375] The long-time exposure sample-and-hold signal SDHC is set to a high level during the long-time exposure D-phase sampling period P97, and the short-time exposure sample-and-hold signal SDLC is set to a high level during the short-time exposure D-phase sampling period P102.

[0376] During the PD reset period P91, the reset signal RB, sample-and-hold signals SR and SD, active signal CM, long-exposure sample-and-hold signal SDHC, and short-exposure sample-and-hold signal SDLC are all set to low. At this time, the reset transistor 126 and sample-and-hold transistors ST1 and ST2 are turned off, the comparator 131 and latch circuit 132 are deactivated, and the output of the selector 133 is set to low. Then, the transfer signal TRG and reset signal RST rise, turning on the transfer transistor 122 and reset transistor 123. At this time, the charges in the photodiode PD and floating diffusion FD1 are reset.

[0377] During the long exposure period P92, the transfer signal TRG and the reset signal RST fall, turning off the transfer transistor 122 and the reset transistor 123. At this time, charges are accumulated in the photodiode PD according to the amount of incident light.

[0378] In the FD reset period P93, the reset signal RST rises, turning on the reset transistor 123. At this time, the charge of the floating diffusion FD1 is reset.

[0379] During the P-phase sampling period P94, the reset signal RB and the sample-and-hold signal SR rise, turning on the reset transistor 126 and the sample-and-hold transistor ST1. At this time, a charge corresponding to the P-phase level output from the amplifier transistor 125 is held in the sample-and-hold capacitor C1.

[0380] During the charge transfer period P95, the transfer signal TRG rises, turning on the transfer transistor 122. At this time, the charge accumulated in the photodiode PD due to the long exposure is transferred to the floating diffusion FD1. A voltage corresponding to the charge transferred to the floating diffusion FD1 is then applied to the gate of the amplification transistor 125. Then, based on the source follower operation between the amplification transistor 125 and the current source 130, a read level V1 corresponding to the voltage applied to the gate of the amplification transistor 125 is input to the comparator 131.

[0381] In an illuminance determination period P96, an active signal CM rises, and the comparator 131 and the latch circuit 132 are activated. Then, the comparator 131 compares the read level V1 of the pixel signal with a reference voltage VRF, and the determination result VCO of the read level V1 is latched in the latch circuit 132. At low illuminance, the read level V1 of the pixel signal becomes equal to or higher than the reference voltage VRF, and the determination result VCO is set to a low level.

[0382] During the long-time exposure D-phase sampling period P97, the long-time exposure sample-and-hold signal SDHC rises. Here, because the determination result VCO is set to a low level, the long-time exposure sample-and-hold signal SDHC is selected by the selector 633. As a result, the sample-and-hold signal SD rises, turning on the sample-and-hold transistor ST2. Also, the reset signal RB rises, turning on the reset transistor 126. At this time, a charge corresponding to the D-phase level of the long-time exposure output from the amplification transistor 125 is held in the sample-and-hold capacitor C2. Thereafter, the long-time exposure sample-and-hold signal SDHC, the sample-and-hold signal SD, and the reset signal RB fall.

[0383] During the PD reset period P98, the reset signal RB, sample-and-hold signals SR and SD, active signal CM, long-exposure sample-and-hold signal SDHC, and short-exposure sample-and-hold signal SDLC are set to low levels. At this time, the reset transistor 126 and sample-and-hold transistors ST1 and ST2 are turned off, the comparator 131 and latch circuit 132 are inactivated, and the output of the selector 133 is set to low level. Then, the transfer signal TRG and reset signal RST rise, turning on the transfer transistor 122 and reset transistor 123. At this time, the charges in the photodiode PD and floating diffusion FD1 are reset.

[0384] In the short-time exposure period P99, the transfer signal TRG and the reset signal RST fall, turning off the transfer transistor 122 and the reset transistor 123. At this time, charge is accumulated in the photodiode PD according to the amount of incident light.

[0385] In the FD reset period P100, the reset signal RST rises, turning on the reset transistor 123. At this time, the charge of the floating diffusion FD1 is reset.

[0386] During the charge transfer period P101, the transfer signal TRG rises, turning on the transfer transistor 122. At this time, the charge accumulated in the photodiode PD during a short exposure is transferred to the floating diffusion FD1. A voltage corresponding to the charge transferred to the floating diffusion FD1 is then applied to the gate of the amplifier transistor 125. Then, based on the source follower operation between the amplifier transistor 125 and the current source 130, a read level V1 corresponding to the voltage applied to the gate of the amplifier transistor 125 is applied to the inputs of the sample-and-hold capacitors C1 and C2.

[0387] During the short-exposure D-phase sampling period P102, the short-exposure sample-and-hold signal SDLC rises. Here, because the determination result VCO is set to a low level, the short-exposure sample-and-hold signal SDLC is not selected by the selector 633, and the long-exposure sample-and-hold signal SDHC remains selected. Therefore, the sample-and-hold signal SD remains low, and the sample-and-hold transistor ST2 remains off. Therefore, the charge corresponding to the D-phase level of the short-exposure output from the amplifier transistor 125 is not held in the sample-and-hold capacitor C2, and the charge corresponding to the D-phase level of the long-exposure output from the amplifier transistor 125 remains held in the sample-and-hold capacitor C2.

[0388] FIG. 53 is a timing chart showing an example of waveforms at various parts during high illuminance in the global shutter operation of the pixel according to the ninth embodiment.

[0389] 1, the operations of the PD reset period P91, long-time exposure period P92, FD reset period P93, P-phase sampling period P94, charge transfer period P95, illuminance determination period P96, PD reset period P98, short-time exposure period P99, and FD reset period P100 during high illuminance are the same as the operations of the PD reset period P91, long-time exposure period P92, FD reset period P93, P-phase sampling period P94, charge transfer period P95, illuminance determination period P96, PD reset period P98, short-time exposure period P99, and FD reset period P100 during low illuminance. However, during high illuminance, the readout level V1 of the pixel signal becomes less than the reference voltage VRF, and the determination result VCO is set to a high level.

[0390] During the long-exposure D-phase sampling period P97, the long-exposure sample-and-hold signal SDHC rises. Here, because the determination result VCO is set to a high level, the long-exposure sample-and-hold signal SDHC is not selected by the selector 633. As a result, the sample-and-hold signal SD remains low, and the sample-and-hold transistor ST2 remains off. As a result, the charge corresponding to the short-exposure D-phase level output from the amplification transistor 125 is not held in the sample-and-hold capacitor C2. After that, the long-exposure sample-and-hold signal SDHC, the sample-and-hold signal SD, and the reset signal RB fall.

[0391] During the charge transfer period P101, the transfer signal TRG rises, turning on the transfer transistor 122. At this time, the charge accumulated in the photodiode PD during a short exposure is transferred to the floating diffusion FD1. A voltage corresponding to the charge transferred to the floating diffusion FD1 is then applied to the gate of the amplifier transistor 125. Then, based on the source follower operation between the amplifier transistor 125 and the current source 130, a read level V1 corresponding to the voltage applied to the gate of the amplifier transistor 125 is applied to the inputs of the sample-and-hold capacitors C1 and C2.

[0392] During the short-exposure D-phase sampling period P102, the short-exposure sample-and-hold signal SDLC rises. Here, because the determination result VCO is set to a high level, the short-exposure sample-and-hold signal SDLC is selected by the selector 633. As a result, the sample-and-hold signal SD rises, turning on the sample-and-hold transistor ST2. Also, the reset signal RB rises, turning on the reset transistor 126. At this time, a charge corresponding to the short-exposure D-phase level output from the amplification transistor 125 is held in the sample-and-hold capacitor C2.

[0393] As described above, in the ninth embodiment, the exposure time of the photodiode PD is switched based on the determination result of the readout level V1 determined in the pixel PIX9 capable of global shutter operation. This makes it possible to read from the photodiode PD for which an exposure time selected according to illuminance is set, without reading from the pixel PIX9 for each exposure time of the photodiode PD. Therefore, even when switching of the conversion efficiency is not performed, it is possible to generate an HDR image while suppressing a decrease in frame rate.

[0394] In the above-described ninth embodiment, an example has been shown in which the exposure time of the photodiode PD is switched based on the determination result of the readout level V1. In addition to this, the configuration of the above-described ninth embodiment may be applied to a LOFIC pixel or a pixel with switchable conversion efficiency. The pixel with switchable conversion efficiency may be any of the pixels in the above-described first to sixth embodiments.

[0395] 10. Tenth Embodiment In the first embodiment described above, the read level V1 is switched based on the determination result of the read level V1 determined in the pixel PIX capable of performing the global shutter operation. In this tenth embodiment, semiconductor chips each having a pixel array portion in which pixels are arranged in a matrix are stacked.

[0396] Figure 54 is a perspective view showing a first stacking example of a solid-state imaging device according to the tenth embodiment, and Figure 55 is a diagram showing the division positions of pixels in the first stacking example of a solid-state imaging device according to the tenth embodiment.

[0397] 54, the solid-state imaging device includes semiconductor chips 1010 and 1020. The semiconductor chip 1010 is stacked on the semiconductor chip 1020.

[0398] An upper pixel array section 1011 is formed on the semiconductor chip 1010. In the upper pixel array section 1011, pixels are arranged in a matrix in the row and column directions.

[0399] A lower pixel array unit 1021 and a column signal processing circuit 1022 are formed on the semiconductor chip 1020. Pixels are arranged in a matrix in the row and column directions in the lower pixel array unit 1021. The column readout circuit 113 and column signal processing unit 114 shown in FIG. 2 can be formed in the column signal processing circuit 1022.

[0400] The pixels formed on the semiconductor chips 1010 and 1020 can be any of the pixels according to the first to ninth embodiments. For example, as shown in Fig. 55, the pixel PIX may be divided at the position of the line A1-A2 and allocated to the semiconductor chips 1010 and 1020. In this case, the photodiode PD can be disposed in the upper pixel array section 1011.

[0401] The semiconductor chips 1010 and 1020 may be directly bonded to each other. Hybrid bonding can be used for directly bonding the semiconductor chips 1010 and 1020. In this case, the semiconductor chips 1010 and 1020 may be electrically connected based on Cu-Cu bonding. The material of the semiconductor substrate used for the semiconductor chips 1010 and 1020 may be Si, InGaAs, or InP.

[0402] Figure 56 is a perspective view showing a second stacking example of a solid-state imaging device according to the tenth embodiment, and Figure 57 is a diagram showing the division positions of pixels in the second stacking example of a solid-state imaging device according to the tenth embodiment.

[0403] 56, the solid-state imaging device includes semiconductor chips 1110, 1120, and 1130. The semiconductor chip 1110 is stacked on the semiconductor chip 1120, and the semiconductor chip 1120 is stacked on the semiconductor chip 1130.

[0404] An upper pixel array section 1111 is formed on the semiconductor chip 1110. In the upper pixel array section 1111, some of the pixels are arranged in a matrix in the row and column directions.

[0405] A lower pixel array section 1121 is formed on the semiconductor chip 1120. In the lower pixel array section 1121, some of the pixels are arranged in a matrix in the row and column directions.

[0406] A column signal processing circuit 1131 is formed on the semiconductor chip 1130. The column readout circuit 113 and the column signal processing unit 114 shown in FIG.

[0407] The pixels formed on the semiconductor chips 1110 and 1120 can be any of the pixels according to the first to ninth embodiments. For example, as shown in Fig. 57, the pixels PIX may be allocated to the semiconductor chips 1110 and 1120 at the positions of the B1-B2 line and the C1-C2 line. In this case, the photodiode PD can be disposed in the upper pixel array section 1111.

[0408] The semiconductor chips 1110, 1120, and 1130 may be directly bonded. Hybrid bonding can be used for directly bonding the semiconductor chips 1110, 1120, and 1130. In this case, the semiconductor chips 1110, 1120, and 1130 may be electrically connected based on Cu-Cu connections. The material of the semiconductor substrate used for the semiconductor chips 1110, 1120, and 1130 may be Si, InGaAs, or InP.

[0409] In this way, in the tenth embodiment, semiconductor chips on which pixel array units are formed are stacked, which makes it possible to increase the sensitivity of the solid-state imaging device while suppressing an increase in the mounting area of ​​the semiconductor chip on which the solid-state imaging device is formed.

[0410] 11. Application Examples to Mobile Bodies The technology according to the present disclosure (the present technology) can be applied to various products. For example, the technology according to the present disclosure may be realized as a device mounted on any type of mobile body, such as an automobile, an electric vehicle, a hybrid electric vehicle, a motorcycle, a bicycle, personal mobility, an airplane, a drone, a ship, or a robot.

[0411] FIG. 58 is a block diagram showing a schematic configuration example of a vehicle control system, which is an example of a mobile object control system to which the technology of the present disclosure can be applied.

[0412] The vehicle control system 12000 includes a plurality of electronic control units connected via a communication network 12001. In the example shown in Fig. 58, the vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, an outside-vehicle information detection unit 12030, an inside-vehicle information detection unit 12040, and an integrated control unit 12050. Also shown as functional components of the integrated control unit 12050 are a microcomputer 12051, an audio / video output unit 12052, and an in-vehicle network I / F (interface) 12053.

[0413] The drivetrain control unit 12010 controls the operation of devices related to the drivetrain of the vehicle in accordance with various programs. For example, the drivetrain control unit 12010 functions as a control device for a drive force generating device for generating a drive force of the vehicle, such as an internal combustion engine or a drive motor, a drive force transmission mechanism for transmitting the drive force to the wheels, a steering mechanism for adjusting the steering angle of the vehicle, and a braking device for generating a braking force of the vehicle.

[0414] The body system control unit 12020 controls the operation of various devices equipped in the vehicle body according to various programs. For example, the body system control unit 12020 functions as a control device for a keyless entry system, a smart key system, a power window device, or various lamps such as headlamps, backup lamps, brake lamps, turn signals, and fog lamps. In this case, radio waves transmitted from a portable device that serves as a key or signals from various switches can be input to the body system control unit 12020. The body system control unit 12020 receives these radio waves or signals and controls the vehicle's door lock device, power window device, lamps, etc.

[0415] The outside-vehicle information detection unit 12030 detects information outside the vehicle equipped with the vehicle control system 12000. For example, an imaging unit 12031 is connected to the outside-vehicle information detection unit 12030. The outside-vehicle information detection unit 12030 causes the imaging unit 12031 to capture images outside the vehicle and receives the captured images. The outside-vehicle information detection unit 12030 may perform object detection processing or distance detection processing for people, cars, obstacles, signs, characters on the road surface, etc. based on the received images.

[0416] The imaging unit 12031 is an optical sensor that receives light and outputs an electrical signal corresponding to the amount of light received. The imaging unit 12031 can output the electrical signal as an image or as distance measurement information. The light received by the imaging unit 12031 may be visible light or invisible light such as infrared light.

[0417] The in-vehicle information detection unit 12040 detects information inside the vehicle. For example, a driver state detection unit 12041 that detects the state of the driver is connected to the in-vehicle information detection unit 12040. The driver state detection unit 12041 includes, for example, a camera that captures an image of the driver, and the in-vehicle information detection unit 12040 may calculate the degree of fatigue or concentration of the driver based on the detection information input from the driver state detection unit 12041, or may determine whether the driver is dozing off.

[0418] The microcomputer 12051 can calculate control target values ​​for the driving force generating device, steering mechanism, or braking device based on the information inside and outside the vehicle acquired by the outside-vehicle information detection unit 12030 or the inside-vehicle information detection unit 12040, and output control commands to the drive system control unit 12010. For example, the microcomputer 12051 can perform cooperative control aimed at realizing the functions of an ADAS (Advanced Driver Assistance System), including vehicle collision avoidance or impact mitigation, following driving based on the distance between vehicles, maintaining vehicle speed, vehicle collision warning, vehicle lane departure warning, etc.

[0419] In addition, the microcomputer 12051 can perform cooperative control for the purpose of autonomous driving, which allows the vehicle to travel autonomously without relying on driver operation, by controlling the driving force generating device, steering mechanism, braking device, etc. based on information about the surroundings of the vehicle obtained by the outside vehicle information detection unit 12030 or the inside vehicle information detection unit 12040.

[0420] Furthermore, the microcomputer 12051 can output a control command to the body system control unit 12020 based on the information outside the vehicle acquired by the outside information detection unit 12030. For example, the microcomputer 12051 can control the headlamps according to the position of a preceding vehicle or an oncoming vehicle detected by the outside information detection unit 12030, and perform cooperative control aimed at preventing glare, such as switching from high beams to low beams.

[0421] The audio / video output unit 12052 transmits at least one of audio and video output signals to an output device capable of visually or audibly notifying information to vehicle occupants or the outside of the vehicle. In the example of Fig. 58, the output devices are exemplified by an audio speaker 12061, a display unit 12062, and an instrument panel 12063. The display unit 12062 may include, for example, at least one of an on-board display and a head-up display.

[0422] FIG. 59 is a diagram showing an example of the installation position of the imaging unit 12031.

[0423] In FIG. 59, the imaging unit 12031 includes imaging units 12101, 12102, 12103, 12104, and 12105.

[0424] The imaging units 12101, 12102, 12103, 12104, and 12105 are provided, for example, at positions such as the front nose, side mirrors, rear bumper, back door, and the top of the windshield inside the vehicle cabin of the vehicle 12100. The imaging unit 12101 provided on the front nose and the imaging unit 12105 provided on the top of the windshield inside the vehicle cabin mainly acquire images of the front of the vehicle 12100. The imaging units 12102 and 12103 provided on the side mirrors mainly acquire images of the sides of the vehicle 12100. The imaging unit 12104 provided on the rear bumper or back door mainly acquires images of the rear of the vehicle 12100. The imaging unit 12105 provided on the top of the windshield inside the vehicle cabin is mainly used to detect preceding vehicles, pedestrians, obstacles, traffic lights, traffic signs, lanes, etc.

[0425] 59 shows an example of the imaging ranges of the imaging units 12101 to 12104. Imaging range 12111 indicates the imaging range of the imaging unit 12101 provided on the front nose, imaging ranges 12112 and 12113 indicate the imaging ranges of the imaging units 12102 and 12103 provided on the side mirrors, respectively, and imaging range 12114 indicates the imaging range of the imaging unit 12104 provided on the rear bumper or back door. For example, by overlaying the image data captured by the imaging units 12101 to 12104, an overhead image of the vehicle 12100 viewed from above can be obtained.

[0426] At least one of the image capturing units 12101 to 12104 may have a function of acquiring distance information. For example, at least one of the image capturing units 12101 to 12104 may be a stereo camera made up of multiple image capturing elements, or may be an image capturing element having pixels for phase difference detection.

[0427] For example, based on the distance information obtained from the imaging units 12101 to 12104, the microcomputer 12051 can calculate the distance to each three-dimensional object within the imaging ranges 12111 to 12114 and the change in this distance over time (relative speed with respect to the vehicle 12100), thereby extracting as a preceding vehicle, in particular, the three-dimensional object that is the closest three-dimensional object on the path of the vehicle 12100 and traveling in approximately the same direction as the vehicle 12100 at a predetermined speed (e.g., 0 km / h or higher). Furthermore, the microcomputer 12051 can set a vehicle-to-vehicle distance to be maintained in advance in front of the preceding vehicle, and perform automatic braking control (including follow-up stop control), automatic acceleration control (including follow-up start control), etc. In this way, cooperative control can be performed for the purpose of autonomous driving, which runs autonomously without relying on driver operation.

[0428] For example, the microcomputer 12051 classifies and extracts three-dimensional object data regarding three-dimensional objects into two-wheeled vehicles, ordinary vehicles, large vehicles, pedestrians, utility poles, and other three-dimensional objects based on distance information obtained from the imaging units 12101 to 12104, and can use the data for automatic obstacle avoidance. For example, the microcomputer 12051 distinguishes obstacles around the vehicle 12100 into obstacles that are visible to the driver of the vehicle 12100 and obstacles that are difficult to see. The microcomputer 12051 then determines a collision risk that indicates the risk of collision with each obstacle, and when the collision risk is equal to or greater than a set value and a collision is possible, the microcomputer 12051 can provide driving assistance for collision avoidance by outputting an alarm to the driver via the audio speaker 12061 or the display unit 12062, or by performing forced deceleration or avoidance steering via the drive system control unit 12010.

[0429] At least one of the image capturing units 12101 to 12104 may be an infrared camera that detects infrared rays. For example, the microcomputer 12051 can recognize a pedestrian by determining whether a pedestrian is present in the images captured by the image capturing units 12101 to 12104. Such pedestrian recognition is performed, for example, by extracting feature points from the images captured by the image capturing units 12101 to 12104 as infrared cameras and performing pattern matching on a series of feature points that indicate the outline of an object to determine whether the object is a pedestrian. When the microcomputer 12051 determines that a pedestrian is present in the images captured by the image capturing units 12101 to 12104 and recognizes the pedestrian, the audio / image output unit 12052 controls the display unit 12062 to superimpose a rectangular outline on the recognized pedestrian for emphasis. The audio / image output unit 12052 may also control the display unit 12062 to display an icon or the like indicating the pedestrian at a desired position.

[0430] An example of a vehicle control system to which the technology according to the present disclosure can be applied has been described above. The technology according to the present disclosure can be applied to the imaging unit 12031 of the above-described configuration. Specifically, for example, the imaging devices according to the first to tenth embodiments described above can be applied to the imaging unit 12031. By applying the technology according to the present disclosure to the vehicle control system 12000, it is possible to improve the dynamic range while suppressing a decrease in the frame rate of the imaging device.

[0431] Note that the above-described embodiment shows an example for realizing the present technology, and the matters in the embodiment and the matters specifying the invention in the claims correspond to each other. Similarly, the matters specifying the invention in the claims and the matters in the embodiment of the present technology with the same title correspond to each other. However, the present technology is not limited to the embodiment, and can be realized by applying various modifications to the embodiment within the scope of the gist. Furthermore, the effects described in this specification are merely examples and are not limited, and other effects may also be present.

[0432] The present technology may also be configured as follows: (1) An imaging device comprising: a pixel capable of generating pixel signals of multiple readout levels; a determination circuit that determines the readout level of the pixel signal within the pixel; and a switching circuit that switches the readout level of the pixel signal based on a determination result of the readout level of the pixel signal. (2) The imaging device described in (1), in which the pixel generates the pixel signals of the multiple readout levels based on switching of conversion efficiency. (3) The imaging device described in (1) or (2), in which the pixel comprises: a photoelectric conversion element; an amplifying transistor that amplifies the pixel signal; a floating diffusion connected to a gate of the amplifying transistor; a transfer transistor that transfers charge accumulated in the photoelectric conversion element to the floating diffusion; a selection transistor that selects the output of the pixel signal amplified by the amplifying transistor; and a switching transistor that switches the conversion efficiency of the amplifying transistor. (4) The imaging device described in (3), in which the switching circuit switches the on / off of the switching transistor based on a determination result of the readout level of the pixel signal. (5) The imaging device according to (4), wherein the pixel comprises a lateral overflow storage capacitance and a pass transistor that sets a path through which charge accumulated in the lateral overflow storage capacitance is transferred to the floating diffusion, and the switching circuit switches on and off the switching transistor and the pass transistor based on a determination result of a readout level of the pixel signal. (6) The imaging device according to (1), wherein the pixel comprises a plurality of photoelectric conversion elements having different sensitivities, and the switching circuit switches the photoelectric conversion elements used to generate the pixel signal based on a determination result of the readout level of the pixel signal. (7) The imaging device according to (1), wherein the pixel comprises a plurality of photoelectric conversion elements having different exposure times, and the switching circuit switches the photoelectric conversion elements used to generate the pixel signal based on a determination result of the readout level of the pixel signal.(8) The imaging device according to (1), wherein the pixel includes a photoelectric conversion element capable of switching an exposure time, and the switching circuit switches the exposure time for exposure by the photoelectric conversion element based on a determination result of a readout level of the pixel signal. (9) The imaging device according to any of (1) to (8), wherein the determination circuit is shared by a plurality of pixels. (10) The imaging device according to any of (1) to (9), wherein the readout level of the pixel signal is switched based on a determination result of the readout level of the pixel signal, and then the pixel signal is read out from the pixel based on a rolling shutter operation. (11) The imaging device according to any of (1) to (9), wherein the pixel includes a sample and hold circuit that samples and holds the pixel signal based on a global shutter operation. (12) The imaging device according to (11), wherein the sample and hold circuit comprises: a first sample and hold capacitor that holds a charge corresponding to a P-phase level; and a second sample and hold capacitor that holds a charge corresponding to a D-phase level; and the determination circuit determines the readout level of the pixel signal between sampling of the P-phase level and sampling of the D-phase level in one frame period. (13) The imaging device according to (12), wherein the determination circuit is disconnected from the first sample and hold capacitor and the second sample and hold capacitor when determining the readout level of the pixel signal. (14) The imaging device according to (12) or (13), wherein the imaging device comprises: a first sample and hold transistor that sets the sampling timing of the P-phase level; and a second sample and hold transistor that sets the sampling timing of the D-phase level; and the switching circuit switches the second sample and hold transistor on and off based on a determination result of the readout level of the pixel signal. (15) The imaging device according to any of (1) to (14), wherein the vertical signal line is shared between reading out the pixel signal from the pixel and reading out the determination result of the readout level of the pixel signal. (16) The imaging device according to any one of (1) to (14), further comprising: a vertical signal line used to read out pixel signals from the pixels; and a readout line used to read out a determination result of a readout level of the pixel signals.(17) An imaging method comprising: generating a pixel signal within a pixel; determining a readout level of the pixel signal within the pixel; switching the readout level of the pixel signal based on a result of determining the readout level of the pixel signal; and reading out the pixel signal from the pixel based on a rolling shutter operation after the readout level of the pixel signal has been switched. (18) The imaging method according to (17), in which the pixel signal is not read out from the pixel before determining the readout level of the pixel signal. (19) An imaging method comprising: generating the pixel signal within a pixel capable of sampling and holding a pixel signal; determining a readout level of the pixel signal within the pixel; switching the readout level of the pixel signal based on a result of determining the readout level of the pixel signal; sampling and holding the pixel signal based on a global shutter operation after the readout level of the pixel signal has been switched; and reading out the sampled and held pixel signal for each row. (20) The imaging method according to (19), in which the D-phase level of the pixel signal is not sampled and held in the pixel before determining the readout level of the pixel signal.

[0433] 100 Imaging device 101 Optical system 102 Solid-state imaging device 103 Imaging control unit 104 Image processing unit 105 Memory unit 106 Display unit 107 Operation unit 108 Bus 111 Pixel array unit 112 Vertical scanning circuit 113 Column readout circuit 114 Column signal processing unit 115 Horizontal scanning circuit 116 Control circuit 117 Vertical signal line 118 Horizontal drive line PIX Pixel PD Photodiode FD1, FD2 Floating diffusion 122 Transfer transistor 123, 126 Reset transistor 124 Switching transistor 125, 127 Amplification transistor 128 Selection transistor 129 Decision value readout transistor SH Sample and hold circuit C1, C2 Sample and hold capacitance ST1, ST2 Sample and hold transistor 130, 134 Current source 131 Comparator 132 Latch circuit 133 Selector

Claims

1. An imaging device comprising: a pixel capable of generating pixel signals of multiple readout levels; a determination circuit that determines the readout level of the pixel signal within the pixel; and a switching circuit that switches the readout level of the pixel signal based on the determination result of the readout level of the pixel signal.

2. The imaging device according to claim 1, wherein the pixels generate pixel signals of the plurality of readout levels based on switching of conversion efficiency.

3. The imaging device according to claim 1, wherein the pixel comprises: a photoelectric conversion element; an amplifying transistor that amplifies the pixel signal; a floating diffusion connected to the gate of the amplifying transistor; a transfer transistor that transfers charge accumulated in the photoelectric conversion element to the floating diffusion; a selection transistor that selects the output of the pixel signal amplified by the amplifying transistor; and a switching transistor that switches the conversion efficiency of the amplifying transistor.

4. The imaging device according to claim 3, wherein the switching circuit switches the switching transistor on and off based on the result of determination of the readout level of the pixel signal.

5. The imaging device according to claim 4, wherein the pixel comprises a horizontal overflow storage capacitance and a pass transistor that sets a path for transferring charge stored in the horizontal overflow storage capacitance to the floating diffusion, and the switching circuit switches the switching transistor and the pass transistor on and off based on the result of determining the read level of the pixel signal.

6. The imaging device according to claim 1, wherein the pixel comprises a plurality of photoelectric conversion elements having different sensitivities, and the switching circuit switches the photoelectric conversion elements used to generate the pixel signal based on the determination result of the readout level of the pixel signal.

7. The imaging device according to claim 1, wherein the pixel comprises a plurality of photoelectric conversion elements having different exposure times, and the switching circuit switches the photoelectric conversion elements used to generate the pixel signal based on the determination result of the readout level of the pixel signal.

8. An imaging device according to claim 1, wherein the pixel comprises a photoelectric conversion element capable of switching exposure time, and the switching circuit switches the exposure time for exposure by the photoelectric conversion element based on the determination result of the readout level of the pixel signal.

9. The imaging device according to claim 1, wherein the determination circuit is shared by a plurality of pixels.

10. The imaging device according to claim 1, wherein the readout level of the pixel signal is switched based on the determination result of the readout level of the pixel signal, and then the pixel signal is read out from the pixel based on a rolling shutter operation.

11. The imaging device according to claim 1, wherein the pixel comprises a sample-and-hold circuit that samples and holds the pixel signal based on a global shutter operation.

12. The imaging device described in claim 11, wherein the sample and hold circuit comprises a first sample and hold capacitor that holds a charge corresponding to a P-phase level and a second sample and hold capacitor that holds a charge corresponding to a D-phase level, and the determination circuit determines the readout level of the pixel signal between sampling of the P-phase level and sampling of the D-phase level during one frame period.

13. The imaging device according to claim 12, wherein the determination circuit is separated from the first sample-and-hold capacitor and the second sample-and-hold capacitor when determining the readout level of the pixel signal.

14. An imaging device as described in claim 12, comprising a first sample and hold transistor that sets the sampling timing of the P-phase level, and a second sample and hold transistor that sets the sampling timing of the D-phase level, wherein the switching circuit switches the second sample and hold transistor on and off based on the determination result of the readout level of the pixel signal.

15. The imaging device according to claim 1, further comprising a vertical signal line shared for reading out pixel signals from the pixels and for reading out the determination results of the readout levels of the pixel signals.

16. The imaging device according to claim 1, comprising: vertical signal lines used for reading out pixel signals from the pixels; and readout lines used for reading out determination results of readout levels of the pixel signals.

17. An imaging method comprising: a step of generating a pixel signal within a pixel; a step of determining a readout level of the pixel signal within the pixel; a step of switching the readout level of the pixel signal based on the determination result of the readout level of the pixel signal; and a step of reading out the pixel signal from the pixel based on a rolling shutter operation after the readout level of the pixel signal has been switched.

18. The imaging method according to claim 18, wherein the pixel signal is not read out from the pixel before determining the readout level of the pixel signal.

19. An imaging method comprising the steps of: generating a pixel signal within a pixel capable of sampling and holding the pixel signal; determining a readout level of the pixel signal within the pixel; switching the readout level of the pixel signal based on the determination result of the readout level of the pixel signal; sampling and holding the pixel signal based on a global shutter operation after the readout level of the pixel signal has been switched; and reading out the sampled and held pixel signal for each row.

20. The imaging method according to claim 19, wherein the D-phase level of the pixel signal is not sampled and held in the pixel before determining the readout level of the pixel signal.

Images