Semiconductor module

Abstract

This semiconductor module includes a first substrate which includes a first surface, a stacked memory chip which is provided on the first surface and which includes a stacked plurality of memory chips and a first inductor provided across the plurality of memory chips, and a first semiconductor chip which is separated from the stacked memory chip, is provided on the first surface, and includes a second inductor, wherein: the stacked memory chip includes a second surface that is parallel to the first surface and is the outermost surface on the first substrate side, and a third surface that is perpendicular to the second surface and is the outermost surface on the first semiconductor chip side; the first inductor is provided so as to be separated from the third surface, parallel to the third surface; the first semiconductor chip includes a fourth surface that is parallel to the first surface and is the outermost surface on the first substrate side, and a fifth surface that is parallel to the third surface and is the outermost surface on the stacked memory chip side; the second inductor is provided so as to be separated from the fifth surface, parallel to the fifth surface; and the first inductor communicates with the second inductor in a non-contact manner.

Description

Semiconductor Module

[0001] One embodiment of the present invention relates to a semiconductor module.

[0002] In recent years, electronic computers in data centers and the like include semiconductor modules in which a stacked memory chip in which multiple memory chips are stacked, multiple IC (Integrated Circuit) chips including an arithmetic processing circuit, multiple IC chips including an image processing circuit, and the like are mounted on a single package substrate. The semiconductor modules enable electronic computers to increase memory capacity and process large amounts of data in data communications between each IC chip and each memory chip.

[0003] For example, Patent Documents 1 to 4 and Non-Patent Document 1 disclose examples of stacked chips in which multiple chips are stacked, or methods for mounting stacked chips. Patent Documents 2, 3, and 5 disclose techniques for performing contactless communication between two chips. Furthermore, Patent Documents 1 to 4 and Non-Patent Documents 1 to 3 disclose a technique for forming wiring on the sidewalls of stacked chips as an example of a method for mounting stacked chips.

[0004] Japanese Patent Publication No. 3-501428 International Publication No. 2021 / 095083 International Publication No. 2021 / 199447 Japanese Patent Application Laid-Open No. 2012-156478 Japanese Patent Application Laid-Open No. 2017-069456

[0005] A. Agnesina et al. , “A Novel 3D DRAM Memory Cube Architecture for Space Applications,” 2018 55th ACM / ESDA / IEEE Design Automation Conference (DAC), 2018, pp. 1-6, doi: 10.1109 / DAC. 2018.8465911. R. W. Johnson, “3-D Packaging: A Technology Review,” pp. 1-70, 23 Jun 2005. https: / / nepp. nasa. gov / doculoads / EA7E7EA1-BD30-4DA4-BD615FEA1A7F5AE9 / 3D%20Packaging%20Report%20071805. pdfR. M. Lea et al. , “3-D Stacked Chip Packaging Solution for Miniaturized Massively Parallel Processing,” IEEE Trans. Adv Packag. , 22 (3), Aug 1999.

[0006] On the other hand, for example, the semiconductor module uses a plurality of through electrodes, a plurality of bumps, etc. to mount a stacked memory chip in which a plurality of memory chips are stacked, a plurality of IC chips including an arithmetic processing circuit, a plurality of IC chips including an image processing circuit, etc. on a single package substrate. Also, for example, the semiconductor module uses an interposer or a silicon bridge that enables high-density interconnect (HDI). As a result, the manufacturing cost of the semiconductor module increases, and the power consumption of the semiconductor module increases due to increased resistance and parasitic capacitance.

[0007] Furthermore, the techniques for forming wiring on the sidewalls of stacked chips disclosed in Patent Documents 1 to 4 and Non-Patent Documents 1 to 3 include a new process for forming wiring on the sidewalls of stacked chips. Therefore, Patent Documents 1 to 4 and Non-Patent Documents 1 to 3 increase the manufacturing costs of semiconductor modules due to the new process. Furthermore, the techniques described in Patent Documents 2 and 3 include a new process for forming wiring for contactless communication (e.g., wireless communication, inductor communication) on the sidewalls of stacked chips or the bottom surfaces of stacked memory chips. Therefore, the techniques described in Patent Documents 2 and 3 increase the manufacturing costs due to the new process for wireless communication. Furthermore, in the technique described in Patent Document 5, the angle between the surfaces on which the inductors of the two chips are provided is 0 degrees or 180 degrees, so inductor communication is generally performed by coupling the sides of the inductors facing each other on the two chips. Therefore, the technique described in Patent Document 5 results in lower communication quality than a configuration in which inductor communication can be performed using multiple sides of the inductor.

[0008] In view of these problems, one embodiment of the present invention has an object to provide a semiconductor module that can reduce manufacturing costs, another object of the present invention is to provide a semiconductor module that can reduce power consumption, and another object of the present invention is to provide a semiconductor module that can reduce degradation in the quality of inductor communication.

[0009] A semiconductor module according to one embodiment of the present invention includes: a first substrate including a first surface parallel to a first direction and a second direction intersecting the first direction; a stacked memory chip including a plurality of memory chips provided on the first surface along a third direction intersecting the first direction and the second direction and stacked along the third direction, and a first inductor provided across the plurality of memory chips; and a first semiconductor chip spaced apart from the stacked memory chips along the first direction and provided on the first surface, the first semiconductor chip including a second inductor, The semiconductor chip includes a second surface which faces the first substrate in parallel and is the outermost surface on the first substrate side, and a third surface which faces the first semiconductor chip in parallel to the second direction and the third direction, the first inductor is arranged parallel to the third surface and spaced apart from the third surface, the first semiconductor chip includes a fourth surface which faces the first surface in parallel and is the outermost surface on the first substrate side, and a fifth surface which faces the third surface in parallel and is the outermost surface on the stacked memory chip side, the second inductor is arranged parallel to the fifth surface and spaced apart from the fifth surface, and the first inductor communicates with the second inductor in a non-contact manner.

[0010] Another semiconductor module according to one embodiment of the present invention includes: a first substrate including a first surface parallel to a first direction and a second direction intersecting the first direction; a second surface parallel to a third direction intersecting the first direction and the second direction and being the outermost surface along the second direction; a third surface parallel to the first surface and along the third direction and being the outermost surface on the first surface side; a plurality of memory chips stacked parallel to the third surface; and a first inductor provided across the plurality of memory chips, the stacked memory chips being provided on the first surface; a fourth surface facing parallel to the first surface and being the outermost surface on the first surface side; a fifth surface opposite the fourth surface and facing the third surface and being the outermost surface on the third surface side; and a first semiconductor chip provided between the first surface and the third surface, the first inductor being provided along the third surface and being spaced apart from the third surface, the first inductor being spaced apart from the third surface, the second inductor being spaced apart from the fifth surface along the fifth surface, and the first inductor communicating with the second inductor in a non-contact manner.

[0011] The first semiconductor chip of the semiconductor module may be a stacked IC chip including a plurality of stacked IC chips, each of the plurality of IC chips including a seal ring arranged on the outer periphery of the IC chip, each wiring layer of the plurality of IC chips including the seal ring and a portion of the second inductor, and in an end view, the seal ring may extend parallel to the semiconductor substrate of the IC chip and in the second direction and be arranged on the semiconductor substrate of the IC chip, a portion of the first inductor may overlap the seal ring and be located closer to the third surface than the seal ring, and a portion of the second inductor may overlap the seal ring and be located closer to the fifth surface than the seal ring.

[0012] The first semiconductor chip of the semiconductor module may be a stacked IC chip including a plurality of stacked IC chips, and the number of stacked memory chips may be equal to or less than the number of stacked IC chips.

[0013] The first semiconductor chip of the semiconductor module may be a stacked IC chip including a plurality of stacked IC chips, the stacked memory chip may include a plurality of the first inductors, the stacked IC chip may include a plurality of the second inductors, the plurality of first inductors may be arranged in a matrix parallel to the third surface, and the plurality of second inductors may be arranged in a matrix parallel to the fifth surface.

[0014] The semiconductor module may further include a first internal wiring exposed on the third surface, a first side wiring provided on the third surface and electrically connected to the first internal wiring, a second internal wiring exposed on the fifth surface, a second side wiring provided on the fifth surface and electrically connected to the second internal wiring, and a side connection terminal provided between the third surface and the fifth surface and electrically connecting the first side wiring and the second side wiring.

[0015] The semiconductor module may further include a bump layer between the second and fourth surfaces and the first surface, the bumps having a diameter of 10 μm or more and 150 μm or less in plan view.

[0016] In a plan view of the semiconductor module, the number of the plurality of bumps provided on the second surface may be different from the number of the plurality of bumps provided on the fourth surface.

[0017] In a planar view of the semiconductor module, the length between the plurality of bumps provided on the second surface along the first direction may be less than the length between the plurality of bumps provided on the fourth surface along the first direction.

[0018] In a plan view of the semiconductor module, the diameter of each of the plurality of bumps provided on the second surface may be the same as the diameter of each of the plurality of bumps provided on the fourth surface.

[0019] In an end view of the semiconductor module, a length from the first surface to an end of the first inductor may be the same as a length from the first surface to an end of the second inductor.

[0020] In a plan view of the semiconductor module, the diameter of each of the plurality of bumps provided on the second surface may be different from the diameter of each of the plurality of bumps provided on the fourth surface, and in an end view, the length from the first surface to the end of the first inductor may be the same as the length from the first surface to the end of the second inductor.

[0021] Each of the plurality of memory chips may have a chip ID, and the first semiconductor chip may be configured to transmit the chip ID to the stacked memory chip when the contactless communication is initiated.

[0022] Each of the plurality of IC chips may have a chip ID, and the first semiconductor chip may be configured such that when the non-contact communication is initiated, the non-contact communication is performed between an IC chip among the plurality of IC chips corresponding to the chip ID and the stacked memory chip.

[0023] The stacked memory chip may include a first transceiver circuit electrically connected to the first inductor, the first semiconductor chip may include a plurality of the second inductors and a second transceiver circuit electrically connected to each of the plurality of second inductors, and the stacked memory chip may be configured to select one second inductor from the plurality of second inductors, and the first inductor may communicate with the one second inductor in a contactless manner.

[0024] The stacked memory chip may include a plurality of the first inductors and a first transceiver circuit electrically connected to each of the plurality of first inductors, the first semiconductor chip may include a second transceiver circuit electrically connected to the second inductor, and the first semiconductor chip may be configured to select one first inductor from the plurality of first inductors, and the second inductor may be configured to communicate with the one first inductor in a contactless manner.

[0025] The stacked memory chip may include a plurality of the first inductors, and the first semiconductor chip may include a plurality of the second inductors, and the first semiconductor chip may be configured to cause communication between each of the plurality of first inductors and each of the plurality of second inductors in all combinations, acquire data related to the strength of communication in all the combinations, select one first inductor from the plurality of first inductors and one second inductor from the plurality of second inductors based on the acquired data, and cause contactless communication between the one first inductor and the one second inductor.

[0026] The first semiconductor chip may be configured to communicate with each of the plurality of first inductors and each of the plurality of second inductors in all combinations, and to obtain data related to the strength of communication in all the combinations, at multiple communication speeds.

[0027] The first semiconductor chip of the semiconductor module may be a stacked IC chip including a plurality of stacked IC chips, the second inductor may be provided across the plurality of IC chips, each of the plurality of memory chips and each of the plurality of IC chips may include a semiconductor substrate and a wiring layer stacked on the semiconductor substrate, the semiconductor substrate of at least one memory chip among the plurality of memory chips may be exposed on the third surface, and the semiconductor substrate of at least one IC chip among the plurality of IC chips may be exposed on the fifth surface.

[0028] The first semiconductor chip of the other semiconductor module may be a stacked IC chip including a plurality of stacked IC chips, the second inductor may be provided on the IC chip closest to the third surface, each of the plurality of memory chips and each of the plurality of IC chips may include a semiconductor substrate and a wiring layer stacked on the semiconductor substrate, and the semiconductor substrate of at least one memory chip among the plurality of memory chips may be exposed to the third surface.

[0029] 1 is a perspective view showing the configuration of a semiconductor module according to a first embodiment of the present invention; FIG. 2 is a plan view showing the configuration of a semiconductor module according to the first embodiment of the present invention; FIG. 3 is an end view showing the end cross-sectional structure of a semiconductor module taken along line A1-A2 shown in FIG. 1; FIG. 4 is a block diagram showing the configuration of a semiconductor module according to a first embodiment of the present invention; FIG. 5 is a perspective view showing a plurality of inductors included in a stacked memory chip and a plurality of inductors included in a first semiconductor chip according to a first embodiment of the present invention; FIG. 6 is an end view showing an enlarged partial end cross-sectional structure of the stacked memory chips, first semiconductor chip, and bump layer shown in FIG. 3; FIG. 7 is an end view showing an enlarged partial end cross-sectional structure of an IC chip according to a first embodiment of the present invention; FIG. 8 is a block diagram showing the configuration of a stacked memory chip according to a first embodiment of the present invention; FIG. 9 is an end view showing an enlarged partial end cross-sectional structure of the stacked memory chips, first semiconductor chip, and bump layer of a semiconductor module according to a second embodiment of the present invention; FIG. 10 is an end view showing an enlarged portion of the end cross-sectional structure of a stacked memory chip, an adhesive layer, a third semiconductor chip, a bump layer, and a package substrate of a semiconductor module according to a fifth embodiment of the present invention. FIG. 11 is a perspective view showing a plurality of inductors included in the stacked memory chip and a plurality of inductors included in the third semiconductor chip of a semiconductor module according to a fifth embodiment of the present invention. FIG. 12 is a block diagram showing the configuration of a semiconductor module according to a fifth embodiment of the present invention. FIG. 13 is an end view showing an enlarged portion of the end cross-sectional structure of a stacked memory chip, an adhesive layer, a third semiconductor chip, a bump layer, and a package substrate of a semiconductor module according to a sixth embodiment of the present invention. FIG. 14 is an end view showing an enlarged portion of the end cross-sectional structure of a stacked memory chip, a first semiconductor chip, and a bump layer of a semiconductor module according to a seventh embodiment of the present invention. FIG. 15 is an end view showing an enlarged portion of the end cross-sectional structure of a stacked memory chip, a first semiconductor chip, and a bump layer of a semiconductor module according to an eighth embodiment of the present invention.23. FIG. 24 is an end view showing an enlarged portion of the cross-sectional end structure of the stacked memory chips, the first semiconductor chip, and the bump layer of a semiconductor module according to a ninth embodiment of the present invention. FIG. 25 is an end view showing an enlarged portion of the cross-sectional end structure of the stacked memory chips, the first semiconductor chip, and the bump layer of a semiconductor module according to a tenth embodiment of the present invention. FIG. 26 is a plan view showing the configuration of the bump layer of a semiconductor module according to a tenth embodiment of the present invention. FIG. 27 is an end view showing an enlarged portion of the cross-sectional end structure of the stacked memory chips, the first semiconductor chip, and the bump layer of a semiconductor module according to an eleventh embodiment of the present invention. FIG. 28 is a plan view showing the configuration of a seal ring and wiring according to a twelfth embodiment of the present invention, and is an end view showing the cross-sectional end structure of the seal ring and wiring taken along line E1-E2 in the plan view. FIG. 29 is a plan view showing the configuration of a seal ring and an inductor according to a thirteenth embodiment of the present invention. FIG. 29 is an end view showing the cross-sectional end structure of the seal ring and the inductor taken along line E3-E4 in FIG. 23. FIG. 29 is an end view showing the cross-sectional end structure of the inductor taken along line E5-E6 in FIG. 23. FIG. 29 is an end view showing the cross-sectional end structure of the inductor taken along line E7-E8 in FIG. 23. FIG. 29 is a plan view showing the configuration of a seal ring and an inductor according to a fourteenth embodiment of the present invention. 27 is an end view showing the end cross-sectional structure of a seal ring and an inductor taken along line E9-E10 in FIG. 27. It is an end view showing the end cross-sectional structure of a seal ring and an inductor shown in FIG. 27. It is a plan view showing the configuration of a seal ring and an inductor according to a fifteenth embodiment of the present invention. It is an end view showing the end cross-sectional structure of an inductor taken along line E11-E12 in FIG. 30. It is an end view showing the end cross-sectional structure of a seal ring and an inductor taken along line E13-E14 in FIG. 30. It is an end view showing the end cross-sectional structure of an inductor taken along line E15-E16 in FIG. It is a plan view showing the configuration of a seal ring and wiring according to a sixteenth embodiment of the present invention, and is an end view showing the end cross-sectional structure of the seal ring and wiring taken along line F1-F2 in the plan view. It is a plan view showing a manufacturing method of an inductor according to a seventeenth embodiment of the present invention, and is an end view showing the end cross-sectional structure of an inductor taken along line F3-F4 in the plan view. It is a plan view showing a manufacturing method of an inductor according to a seventeenth embodiment of the present invention, and is an end view showing the end cross-sectional structure of an inductor taken along line F5-F6 in the plan view.FIG. 18 is a perspective view showing a plurality of inductors included in a stacked memory chip of a semiconductor module according to an 18th embodiment of the present invention and a plurality of inductors included in a first semiconductor chip. FIG. 19 is a diagram showing individual identification numbers (IDs) of each chip according to an 18th embodiment of the present invention. FIG. 20 is a flowchart showing an example of an inductor communication method for a semiconductor module according to an 18th embodiment of the present invention. FIG. 21 is a flowchart showing an example of an inductor communication method for a semiconductor module according to an 18th embodiment of the present invention. FIG. 22 is a block diagram showing an example of a configuration of a first semiconductor chip according to an 18th embodiment of the present invention. FIG. 23 is a block diagram showing an example of a configuration of a semiconductor module according to a 19th embodiment of the present invention. FIG. 24 is a block diagram showing an example of a configuration of a semiconductor module according to a 20th embodiment of the present invention.

[0030] Hereinafter, embodiments of the present invention will be described with reference to the drawings. However, the present invention can be implemented in many different forms, and should not be construed as being limited to the description of the following exemplary embodiments. For clarity of explanation, the drawings may show schematic representations of the width, thickness, shape, etc. of each part compared to the actual form. However, these are merely examples and are not intended to limit the interpretation of the present invention. Furthermore, in this specification and each drawing, elements similar to those previously described with reference to the previous drawings are designated by the same reference numerals (or reference numerals with a, b, etc. suffixed thereto), and detailed descriptions may be omitted as appropriate. Furthermore, the letters "first" and "second" attached to each element are convenient labels used to distinguish each element and have no further meaning unless otherwise specified.

[0031] In one embodiment of the present invention, when a component or region is said to be "on (or under)" another component or region, unless otherwise specified, this includes not only the case where it is directly above (or directly under) the other component or region, but also the case where it is above (or under) the other component or region, i.e., the case where another component is included between the component or region and above (or under) the other component or region.

[0032] In one embodiment of the present invention, the first direction D1 intersects with the second direction D2, and the third direction D3 intersects with the first direction D1 and the second direction D2 (D1D2 plane).

[0033] In one embodiment of the present invention, when the expressions "identical" and "matching" are used, the expressions "identical" and "matching" may include a tolerance within the design range. In addition, in one embodiment of the present invention, when a tolerance within the design range is included, the expressions "approximately identical" and "approximately matching" may be used.

[0034] First Embodiment A semiconductor module 10 according to a first embodiment will be described with reference to FIGS.

[0035] <1-1. Overview of Semiconductor Module 10> First, an overview of the semiconductor module 10 will be described with reference to FIGS. 1 to 5. FIG. 1 is a perspective view showing the configuration of the semiconductor module 10. FIG. 2 is a top view showing the configuration of the semiconductor module 10. FIG. 3 is an end view showing the end cross-sectional structure of the semiconductor module 10 taken along A1-A2 shown in FIG. 2. FIG. 4 is a block diagram showing the functional block configuration of the semiconductor module. FIG. 5 is a perspective view showing a plurality of inductors 172 included in the stacked memory chip 100 and a plurality of inductors 272 included in the first semiconductor chip 200, and is a perspective view showing the configuration of the inductors 172 and 172.

[0036] 1, 2, or 3, the semiconductor module 10 includes a stacked chip group 30, a lid 40, a sealing structure 50, and a package substrate 60. The semiconductor module 10 may also include a thermally conductive sheet 80 and a metal film 90.

[0037] The stacked chip group 30 includes a first surface 32 electrically connected to the package substrate 60 in the third direction D3, a second surface 34 opposite the first surface 32 and parallel to the first surface 32, and a plurality of chips. Details will be described later, but as shown in FIG. 2 or 3 , for example, the stacked chip group 30 includes a plurality of stacked memory chips 100, a first semiconductor chip 200, a plurality of stacked DRAMs (Dynamic Random Access Memories) 300, a plurality of support substrates 400, a plurality of second semiconductor chips 600, and a bump layer 800. The bump layer 800 also includes a plurality of bumps 82, for example. The bumps 82 correspond to output terminals of the stacked chip group 30. 2 , the stacked chip group 30 includes twelve stacked memory chips 100, one first semiconductor chip 200, twelve stacked DRAMs 300, four support substrates 400, and three second semiconductor chips 600. The configuration of the stacked chip group 30 is not limited to the configuration shown in FIG. 2 . The configuration of the stacked chip group 30 can be changed as appropriate based on the application or specifications of the semiconductor module 10. Each of the stacked memory chips 100, the first semiconductor chip 200, and the second semiconductor chip 600 is electrically connected to a plurality of bumps 82 and electrically connected to the package substrate 60.

[0038] When the plurality of first semiconductor chips 200 are not distinguished from one another, the first semiconductor chip is expressed as the first semiconductor chip 200. As with the plurality of first semiconductor chips 200, when the plurality of stacked DRAMs 300, the plurality of support substrates 400, and the plurality of second semiconductor chips 600 are not distinguished from one another, no capital letter is added after the reference numeral. As with the plurality of first semiconductor chips 200, when the plurality of stacked DRAMs 300, the plurality of support substrates 400, and the plurality of second semiconductor chips 600 are distinguished from one another, a capital letter is added after the reference numeral.

[0039] The lid 40 covers the stacked chip group 30 and contacts the first surface 62 of the package substrate 60. For example, the lid 40 may include a metal material and a sealing material. For example, the metal material may include gold, nickel, tin, etc., and the sealing material may include a resin material such as epoxy, a hardener, a filler, an additive, etc. The lid 40 functions to protect the stacked chip group 30 from physical impact, contamination, or oxidation due to moisture. The lid 40 may also function as a heat spreader.

[0040] The sealing structure 50 surrounds the stacked chip group 30 and contacts the stacked chip group 30 as well as the first surface 62 of the package substrate 60. For example, the sealing structure 50 includes a sealing material. For example, the sealing material includes a resin material such as epoxy, a hardener, a filler, an additive, and the like. The sealing structure 50 has the function of fixing the stacked chip group 30 to the package substrate 60 and protecting it from physical impact.

[0041] The package substrate 60 is a printed circuit board that includes a multilayer wiring structure in which wiring and insulating layers are alternately stacked, and is capable of high-density interconnect (HDI). For example, the package substrate 60 may be an organic laminate substrate, a silicon interposer in which wiring is formed on a silicon substrate (e.g., Si-wafer), an active interposer in which active elements are added to a silicon interposer, a silicon bridge-embedded substrate in which a silicon chip with wiring is embedded in an organic substrate, a glass core substrate in which wiring is formed using glass as a core material, or an RDL (Redistribution Layer) interposer in which wiring is formed in an insulating film. The package substrate 60 may be any substrate that has a rewiring function, and is not limited to the substrate shown here. For example, the package substrate 60 according to this embodiment includes a first surface 62, a second surface 64, and multiple wiring layers 66, 68, 70, 72, and 74. The wiring layers 66, 68, 70, 72, and 74 are arranged parallel to the first direction D1 and the second direction D2 and are stacked in this order in the third direction D3. The multiple wiring layers 66 and 74 include multiple electrodes 67 and multiple electrodes 75. The multiple wiring layers 68, 70, and 72 include multiple wires 69, multiple wires 71, and multiple wires 73. The multiple electrodes 67 are exposed on the first surface 62, and the multiple electrodes 75 are exposed on the second surface 64. The electrode 67 is electrically connected to the wire 69, the wire 69 is electrically connected to the wire 71, the wire 71 is electrically connected to the wire 73, and the wire 73 is electrically connected to the electrode 75. Insulating layers alternately stacked with the wires are not shown in FIG. 3 . The number of layers in the multilayer wiring structure of the package substrate 60 is not limited to the four layers shown in FIG. 3 . The number of layers in the multilayer wiring structure of the package substrate 60 can be changed as appropriate based on the application or specifications of the semiconductor module 10.

[0042] The package substrate 60 also functions to connect the stacked memory chip 100, the first semiconductor chip 200, the stacked DRAM 300, the second semiconductor chip 600, etc., to external devices, etc. The package substrate 60 also functions to electrically connect the plurality of bumps 82 to the electrodes 75 corresponding to each bump 82. The length (pitch) between two adjacent bumps 82 is shorter than the length (pitch) between two adjacent electrodes 75. The package substrate 60 also functions to widen the pitch of the bumps 82 to the pitch of the electrodes 75. In other words, the package substrate 60 also functions to rewire the bumps 82 so that the pitch of the bumps 82 matches the pitch of the electrodes 75. As a result, the semiconductor module 10 can be easily electrically connected to a motherboard (not shown).

[0043] For example, the metal film 90 may be provided along the third direction D3 so as to be in contact with the second surface 34 of the stacked chip group 30, and the heat conduction sheet 80 may be provided so as to be in contact between the metal film 90 and the lid body 40. For example, the metal film 90 and the heat conduction sheet 80, together with the lid body 40, have the function of releasing heat generated by the semiconductor module 10 to the outside of the semiconductor module 10.

[0044] Next, the functional block configuration of the semiconductor module 10 will be described with reference to Figures 2 to 4. Configurations that are the same as or similar to those in Figures 1 to 3 will be described as necessary, and descriptions of configurations that are the same as or similar to those in Figures 1 to 3 may be omitted.

[0045] As shown in FIG. 2, FIG. 3 or FIG. 4, the semiconductor module 10 includes stacked memory chips 100A, 100B and 100C, a first semiconductor chip 200, a second semiconductor chip 600A and a stacked DRAM.

[0046] The stacked memory chips 100A, 100B, and 100C include the same configuration. In the following description, the functional block configuration of the stacked memory chip 100A will be described, and the functional block configuration of the stacked memory chip 100B will be described as needed.

[0047] The stacked memory chip 100A includes a plurality of magnetically coupled chip-to-chip interfaces (Through Chip Interface-IO (TCI-IO)) 112 and a plurality of memory modules 111. The plurality of TCI-IOs 112 are electrically connected to the memory modules 111. For example, the stacked memory chip 100 includes a function of storing received data and a function of transmitting the stored data.

[0048] The TCI-IO 112 includes an inductor 172 (first inductor), a transmitting / receiving circuit 114, and a parallel-serial conversion circuit 113. The inductor 172 is electrically connected to the transmitting / receiving circuit 114 using terminals A and B. The transmitting / receiving circuit 114 is electrically connected to the parallel-serial conversion circuit 113. The parallel-serial conversion circuit 113 is electrically connected to the memory module 111.

[0049] The inductor 172 has a function of performing contactless inductor communication with the inductor 272 (second inductor) of the first semiconductor chip 200 , and also has a function of performing contactless inductor communication with the inductor 272 of the second semiconductor chip 600 .

[0050] For example, the transmitting / receiving circuit 114 has a function of amplifying the signal (data) received by the inductor 172 and a function of removing noise from the received signal (data). Furthermore, for example, the transmitting / receiving circuit 114 has a function of transmitting a desired signal (data) converted using the parallel-to-serial conversion circuit 113 over radio waves. The signal received by the inductor 172 includes a large number of parallel signals (parallel signals) from the first semiconductor chip 200 or the second semiconductor chip 600. The desired signal includes a large number of parallel signals (parallel signals) from the memory module 111.

[0051] For example, in step 1, the parallel-serial conversion circuit 113 performs parallel-to-serial conversion on a number of parallel signals from the first semiconductor chip 200 or the second semiconductor chip 600, converting them into serial signals (serial signals). The serial signals are transferred at high speed using a single signal path (wiring). In step 2, the parallel-serial conversion circuit 113 performs serial-to-parallel conversion on the serial signals immediately before the memory module 111, converting them back into a number of parallel signals, and then transmits the parallel signals to the memory module 111. For example, when transmitting signals (data) from the memory module 111 to the first semiconductor chip 200 or the second semiconductor chip 600, the parallel-serial conversion circuit 113 performs step 1 following step 2. The parallel-serial conversion circuit 113 is called, for example, a SerDes circuit (Serialize and Deserialize Circuit).

[0052] For example, memory module 111 includes functionality for generating multiple parallel signals to transmit, and functionality for controlling and storing multiple parallel signals received in memory cell array 115 (see FIG. 8).

[0053] The first semiconductor chip 200 includes a plurality of TCI-IOs 212 and a plurality of CPUs (Central Processing Units) 220 (for example, CPU 220A, CPU 220B, CPU 220C). The plurality of TCI-IOs 212 are electrically connected to the plurality of CPUs 220.

[0054] The TCI-IO 212 includes an inductor 272, a transmitting / receiving circuit 214, and a parallel-serial conversion circuit 213. The inductor 272 is electrically connected to the transmitting / receiving circuit 214 using terminals C and D. The transmitting / receiving circuit 214 is electrically connected to the parallel-serial conversion circuit 213. For example, the parallel-serial conversion circuit 213 is electrically connected to the CPU 220A.

[0055] The configurations and functions of the inductor 272 , the transmitting / receiving circuit 214 and the parallel-serial conversion circuit 213 are similar to those of the inductor 172 , the transmitting / receiving circuit 114 and the parallel-serial conversion circuit 113 .

[0056] The CPU 220 includes a plurality of arithmetic circuits and is capable of arithmetic processing. For example, the CPU 220A has the function of reading a control program stored in the stacked DRAM 300A via the stacked memory chip 100A, expanding the control program, and executing processing based on the control program, as well as transmitting instructions (commands) to each IC chip 110 to execute processing based on the control program.

[0057] The second semiconductor chip 600 includes a plurality of TCI-IOs 612 and a plurality of GPUs (Graphics Processing Units) 620 (for example, GPU 620A, GPU 620B, and GPU 620C). The plurality of TCI-IOs 612 are electrically connected to the plurality of GPUs 620.

[0058] The TCI-IO 612 includes an inductor 672, a transmitting / receiving circuit 614, and a parallel-to-serial conversion circuit 613. The inductor 672 is electrically connected to the transmitting / receiving circuit 614 using terminals E and F. The transmitting / receiving circuit 614 is electrically connected to the parallel-to-serial conversion circuit 613. For example, the parallel-to-serial conversion circuit 613 is electrically connected to the GPU 620A.

[0059] The configurations and functions of the inductor 672 , the transmitting / receiving circuit 614 and the parallel-serial conversion circuit 613 are similar to those of the inductor 272 , the transmitting / receiving circuit 214 and the parallel-serial conversion circuit 213 .

[0060] The GPU 620 includes multiple arithmetic circuits and is capable of image processing and video processing. That is, the second semiconductor chip 600 includes a configuration similar to that of the first semiconductor chip 200 and has functions specialized for image processing and video processing. For example, the GPU 620A has the function of reading a control program stored in the stacked DRAM 300B via the stacked memory chip 100B, expanding the control program and executing processing based on the control program, as well as transmitting instructions (commands) to each IC chip 110 to execute processing based on the control program.

[0061] Next, an overview of inductor communication will be described with reference to Fig. 5. Configurations that are the same as or similar to those in Figs. 1 to 4 will be described as necessary, and descriptions of configurations that are the same as or similar to those in Figs. 1 to 4 may be omitted.

[0062] The stacked memory chip 100 includes a plurality of inductors 172 arranged parallel to a third surface 146 that is parallel to the second direction D2 and the third direction D3 and spaced apart from the third surface 146. The plurality of inductors 172 are arranged along the second direction D2. Each of the plurality of inductors 172 includes a terminal A, a terminal B, a first portion 172a, a second portion 172b, a third portion 172c, a fourth portion 172e, and a fifth portion 172d.

[0063] The fifth portion 172d extends in the second direction D2, one end of which is electrically connected to terminal A, and the other end of which is electrically connected to one end of the fourth portion 172e. The fourth portion 172e extends in the third direction D3, and the other end of which is electrically connected to one end of the first portion 172a. The first portion 172a extends in the second direction D2, and the other end of which is electrically connected to one end of the second portion 172b. The second portion 172b extends in the third direction D3, and the other end of which is electrically connected to one end of the third portion 172c. The third portion 172c extends in the second direction D2, and the other end of which is electrically connected to terminal B.

[0064] The first semiconductor chip 200 includes a plurality of inductors 272 (second inductors) that are parallel to the positions where the plurality of inductors 172 are arranged, and are parallel to and spaced apart from the third surface 206 of the first semiconductor chip 200. The plurality of inductors 272 are arranged along the second direction D2. Each of the plurality of inductors 272 includes a terminal C, a terminal D, a first portion 272a, a second portion 272b, a third portion 272c, a fourth portion 272e, and a fifth portion 272d.

[0065] The fifth portion 272d extends in the second direction D2, one end of which is electrically connected to terminal C, and the other end of which is electrically connected to one end of the fourth portion 272e. The fourth portion 272e extends in the third direction D3, and the other end of which is electrically connected to one end of the first portion 272a. The first portion 272a extends in the second direction D2, and the other end of which is electrically connected to one end of the second portion 272b. The second portion 272b extends in the third direction D3, and the other end of which is electrically connected to one end of the third portion 272c. The third portion 272c extends in the second direction D2, and the other end of which is electrically connected to terminal B.

[0066] When viewed from the first direction D1 on a plane parallel to the second direction D2 and the third direction D3, the inductors 172 and 272 are arranged parallel and facing each other. The inductor 172 is also superimposed on the inductor 272. Magnetic field coupling between one inductor 172 and one inductor 272 facing each other among the multiple inductors 172 and the multiple inductors 272 enables the inductors to communicate with each other one-to-one in a non-contact manner. For example, communication between inductors due to magnetic field coupling is called inductor communication, signal communication, data communication, etc. The shapes of the inductors 172 and 272 are not limited to rectangular shapes, and may be any shape that allows inductor communication.

[0067] For example, inductor 172 and inductor 272 are arranged parallel to each other and are capable of one-to-one communication through magnetic field coupling. In the example shown in Fig. 5, magnetic fields are generated by first portion 172a of inductor 172 and first portion 272a of inductor 272, and by fourth portion 172e of inductor 172 and fourth portion 272e of inductor 272, with magnetic fields generated by the second portion, third portion, and fifth portion of each inductor being omitted. Normal vectors of inductor 172 and inductor 272 to parallel surfaces (e.g., third surface 146 and third surface 206) coincide, and the magnetic field shown in Fig. 3 is merely an example, and the magnetic field actually generated is not limited to the magnetic field shown in Fig. 3.

[0068] The inductor 272 has the same configuration and function as the inductor 172. Note that a plane parallel to the second direction D2 and the third direction D3 viewed from the first direction D1 may be referred to as a plan view.

[0069] Furthermore, the inductor 172 of the stacked memory chip 100A and the inductor 172 of the stacked memory chip 100C may be formed parallel to the surfaces where the stacked memory chip 100A and the stacked memory chip 100C face each other. The stacked memory chip 100C is a stacked memory chip adjacent to the stacked memory chip 100A. As a result, the inductor 172 of the stacked memory chip 100A can perform inductive communication with the inductor 172 of the stacked memory chip 100C. For example, if there is sufficient time for data transfer, inductive communication may be performed between the stacked memory chip 100A and the stacked memory chip 100C, and all data may be transferred from the stacked memory chip 100A to the stacked memory chip 100C.

[0070] Each of the plurality of stacked DRAMs 300 stores, for example, a control program for controlling the plurality of stacked memory chips 100, the first semiconductor chip 200, and the plurality of second semiconductor chips 600 in the semiconductor module 10. The stacked DRAM 300 may be, for example, a high-performance DRAM capable of wideband communication known as HBM (High Bandwidth Memory).

[0071] Furthermore, the stacked DRAM 300 may include an inductor (not shown) provided across multiple DRAM chips, similar to the stacked memory chip 100. For example, similar to the stacked memory chip 100, the stacked DRAM 300 may perform inductor communication with the inductor 272 of the first semiconductor chip 200 or the inductor 672 of the second semiconductor chip 600 adjacent to the stacked DRAM 300.

[0072] As described above, the stacked memory chip 100 is electrically connected to the first semiconductor chip 200 and the second semiconductor chip 600 using the bump layer 800 and the package substrate 60, without using expensive components such as an interposer or a silicon bridge. Furthermore, the stacked memory chip 100 can transmit and receive signals to and from the first semiconductor chip 200 and the second semiconductor chip 600 using non-contact inductor communication, rather than transmitting and receiving signals via signal paths that are routed over long distances using wiring, through electrodes, bumps, and the like.

[0073] As a result, the manufacturing process of the semiconductor module 10 does not include a process of connecting the stacked memory chip 100, the first semiconductor chip 200, and the second semiconductor chip 600 with an interposer or a silicon bridge, etc., which makes it possible to reduce manufacturing costs and prevent a decrease in manufacturing yield. Furthermore, the semiconductor module 10 includes a configuration that can reduce resistance and parasitic capacitance, and inductor communication using the semiconductor module 10 can reduce the power consumption of the semiconductor module 10.

[0074] Furthermore, the inductor 172 of the stacked memory chip 100 has a normal vector that matches with the inductor 272 of the first semiconductor chip 200 and the second semiconductor chip 600. As a result, the semiconductor module 10 is a module that can improve the efficiency of signal transmission through inductor communication.

[0075] Furthermore, the inductor 172 is not exposed on the end faces (first face 142, second face 144, third face 146, etc.) of the stacked memory chip 100. Similarly to the inductor 172, the inductors 272 and 672 (see FIG. 4 ) are not exposed on the end faces of the first semiconductor chip 200 and the second semiconductor chip 600. As a result, the semiconductor module 10 can suppress corrosion or deterioration of each element in the stacked memory chip 100 due to exposure of the inductor, and can also suppress absorption of moisture and intrusion of impurities into the stacked memory chip 100 due to exposure of the inductor. In other words, the reliability of the semiconductor module 10 can be maintained without being impaired over the long term.

[0076] Furthermore, as described above, for example, the semiconductor module 10 is electrically connected to the motherboard (not shown) by bumps (not shown) electrically connected to the electrodes 75. Therefore, the semiconductor module 10 is configured to be relatively easy to remove from the motherboard. Therefore, for example, if the stacked memory chips 100 malfunction, the semiconductor module 10 can be removed from the motherboard and replaced. Furthermore, because the stacked memory chips 100 on the semiconductor module 10 are electrically connected to the package substrate 60 via the bumps 82, the stacked memory chips 100 are configured to be removable from the package substrate 60. Therefore, it is also possible to remove the malfunctioning stacked memory chip 100 from the package substrate 60 and electrically connect a new stacked memory chip 100 to the package substrate 60.

[0077] <1-2. End Cross-Sectional Structure of Stacked Chip Group 30> The end cross-sectional structure of the stacked chip group 30 will be described with reference to Figures 1 to 7. Figure 6 is an end view showing an enlarged portion of the end cross-sectional structure of the stacked memory chip 100A, first semiconductor chip 200, and bump layer 800 shown in Figure 3. Figure 7 is an end view showing an enlarged portion of the end cross-sectional structure of the IC chip 110. Configurations that are the same as or similar to those in Figures 1 to 5 will be described as necessary, and descriptions of configurations that are the same as or similar to those in Figures 1 to 5 may be omitted.

[0078] 1 to 6 . As shown in FIG. 6 , the stacked memory chip 100A includes a configuration in which multiple IC chips 110 are stacked on a package substrate 60 along the third direction D3. The stacked memory chip 100A includes a first surface 142 on the side where the package substrate 60 is disposed and parallel to the first direction D1 and the second direction D2, a second surface 144 on the side opposite to the first surface 142 with respect to the third direction D3 and parallel to the first surface 142, a third surface 146 on the side where the first semiconductor chip 200 is disposed and perpendicular to the first surface 142 and the second surface 144, and a fourth surface 148 on the side opposite to the third surface 146 with respect to the first direction D1.

[0079] The first surface 142 is the outermost surface of the lower side of the stacked memory chips 100 along the third direction D3, and the second surface 144 is the outermost surface of the upper side of the stacked memory chips 100 along the third direction D3. The third surface 146 is the outermost surface of the stacked memory chips 100 on the side where the first semiconductor chip 200 is arranged along the first direction D3, and the fourth surface 148 is the outermost surface of the stacked memory chips 100 on the side opposite the third surface 146 along the third direction D3.

[0080] The stacked memory chips 100A are electrically connected to the stacked DRAM 300A and the package substrate 60. For example, the first surface 142 of the stacked memory chips 100A is electrically connected to the plurality of bumps 82 and is electrically connected to the top of the package substrate 60 (the plurality of electrodes 75), and the second surface 144 of the stacked memory chips 100A is electrically connected to the stacked DRAM 300A by the through electrodes 131 (see FIG. 7 ).

[0081] Each of the multiple IC chips 110 includes a transistor layer 130 and a wiring layer 150. The transistor layer 130 includes a semiconductor substrate 173, but for convenience of explanation, the transistor layer 130 and the semiconductor substrate 173 are illustrated separately. Furthermore, as will be described in detail later, for example, the wiring layer 150 includes a multilayer wiring structure in which through electrodes, wiring, and insulating layers are alternately stacked. The number of layers of the multilayer wiring in the wiring layer 150 can be changed as appropriate depending on the specifications, applications, etc. of the semiconductor module 10.

[0082] When the multiple IC chips 110 are not distinguished from one another, the IC chips are expressed as IC chip 110. When the multiple IC chips 110 are distinguished from one another, the memory chips are expressed as IC chip 110n, IC chip 110n+1, IC chip 110n+2, etc.

[0083] For example, the stacked memory chip 100A includes four IC chips 110 (IC chip 110n+3, IC chip 110n+2, IC chip 110n+1, and IC chip 110n). The stacked memory chip 100A includes a configuration in which the IC chip 110n+3, IC chip 110n+2, IC chip 110n+1, and IC chip 110n are stacked in the third direction D3 in this order from the IC chip closest to the first surface 62 of the package substrate 60.

[0084] For example, the IC chip 110n is a TCI-IO chip 500A. For example, the TCI-IO chip 500A includes a part including terminals A and B of the inductor 172, the transmitting / receiving circuit 114, and the parallel-serial conversion circuit 113.

[0085] The stacked memory chip 100A also includes an inductor 172 that spans the multiple IC chips 110. The inductor 172 is arranged parallel to the third direction D3 (third surface 146) along the second direction D2 and spaced apart from the third surface 146. For example, the end 101 of the inductor 172 shown in FIG. 6 is spaced a distance L1 from the first surface 62 of the package substrate 60, and the length of the inductor 172 along the third direction D3 is L2. For example, the length L2 may be the length of each of the first portion 172a, the second portion 172b, and the fourth portion 172e, or the length of the opposite side of the first portion 172a that includes the terminal A, the terminal B, the third portion 172c, and the fifth portion 172d. For example, the length L2 may be the diameter of the inductor 172. 6 is provided across the IC chip 110n+3, the IC chip 110n+2, the IC chip 110n+1, and the IC chip 110n. As will be described in detail later, the inductor 172 is formed using a plurality of wirings, through electrodes, etc.

[0086] The IC chip 110n includes a semiconductor substrate 173n, a transistor layer 130n, and a wiring layer 150n, and the IC chip 110n+1 includes a semiconductor substrate 173n+1, a transistor layer 130n+1, and a wiring layer 150n+1. As shown in Figure 6, the IC chips 110n+3 and 110n+2 each include a corresponding semiconductor substrate 173, a transistor layer, and a wiring layer, similar to the IC chips 110n and 110n+1.

[0087] For example, techniques such as fusion bonding and silicon direct bonding (SDB) can be used to stack (bond) IC chips 110 together. Fusion bonding and silicon direct bonding are techniques used in the relevant technical field, and detailed explanations thereof will be omitted here. For example, bonding IC chips 110 together so that their wiring layers 150 face each other is called F2F bonding (face to face fusion). For example, bonding IC chips 110 together so that their semiconductor substrates 173 included in their transistor layers 130 face each other is called B2B bonding (back to back fusion). For example, bonding of IC chips 110 such that the wiring layer 150 and the semiconductor substrate 173 included in the transistor layer 130 face each other is called F2B bonding (Face to Back Fusion).

[0088] Furthermore, for example, a mounting structure in which the semiconductor substrate 173 side of the IC chip 110 is electrically connected to the package substrate 60 and the stacking direction is upward along the third direction D3 is called face-up mounting. On the other hand, for example, a mounting structure in which the wiring layer 150 side of the IC chip 110 is electrically connected to the package substrate 60 and the stacking direction is downward along the third direction D3 is called face-down mounting.

[0089] That is, the stacked memory chip 100A shown in FIG. 6 includes four IC chips 110n to 110n+3 that are F2B bonded together, and is mounted face down on a package substrate 60.

[0090] The number of layers, bonding, and mounting structure of the IC chips 110 of the stacked memory chip 100A shown in Fig. 6 are merely examples, and the number of layers, bonding, and mounting structure of the IC chips 110 of the stacked memory chip 100A are not limited to the bonding and mounting structure shown in Fig. 6. For example, the stacked memory chip 100A may include two IC chips 110n and 110n+1 bonded by F2B bonding, and may be mounted face up on the package substrate 60.

[0091] 6 , the first semiconductor chip 200, like the stacked memory chip 100A, includes a configuration in which multiple IC chips 110 are stacked on a package substrate 60 along the third direction D3. The first semiconductor chip 200 includes a first surface 202 on which the package substrate 60 is disposed and which is parallel to the first direction D1 and the second direction D2, a second surface 144 on the opposite side to the first surface 202 with respect to the third direction D3 and which is parallel to the first surface 202, a third surface 206 on which the stacked memory chip 100A is disposed and which is perpendicular to the first surface 202 and the second surface 204, and a fourth surface 208 on the opposite side to the third surface 206 with respect to the first direction D1.

[0092] The first surface 202 is the outermost surface on the bottom of the first semiconductor chip 200 along the third direction D3, and the second surface 204 is the outermost surface on the top of the first semiconductor chip 200 along the third direction D3. The third surface 206 is the outermost surface of the first semiconductor chip 200 on the side where the stacked memory chip 100A is arranged along the first direction D3, and the fourth surface 208 is the outermost surface of the first semiconductor chip 200 on the side opposite to the third surface 206 along the third direction D3.

[0093] Furthermore, the first semiconductor chip 200 is bonded to the support substrate 400B and electrically connected to the package substrate 60. For example, the first surface 202 of the first semiconductor chip 200 is electrically connected to the plurality of bumps 82 and is also electrically connected to the top of the package substrate 60 (the plurality of electrodes 75), and the second surface 204 of the first semiconductor chip 200 is bonded to the support substrate 400B by welding or direct silicon bonding.

[0094] 2, the first semiconductor chip 200 includes a plurality of CPUs 220. For example, the first semiconductor chip 200 includes three CPUs: 220A, 220B, and 220C. The CPUs 220A, 220B, and 220C have similar configurations and functions. In the following description of the first semiconductor chip 200, the first semiconductor chip 200 will be described using the CPU 220A as an example, and the CPUs 220B and 220C will be described as necessary.

[0095] The support substrate 400 has a function of supporting the first semiconductor chip 200 and the second semiconductor chip 600. Furthermore, the support substrate 400 together with the bump layer 800 may have a function of adjusting the length, parallel to the third direction D3, from the first surface 62 of the package substrate 60 to the bonding surface between the first semiconductor chip 200 and the support substrate 400. For example, the support substrate 400A supports three CPUs 220A, 220B, and 220C, and adjusts the length (height) of the first semiconductor chip 200 from the first surface 62.

[0096] For example, the first semiconductor chip 200 includes four IC chips 110 (IC chip 110n+7, IC chip 110n+6, IC chip 110n+5, and IC chip 110n+4). The stacked memory chip 100A includes a configuration in which the IC chip 110n+7, IC chip 110n+6, IC chip 110n+5, and IC chip 110n+4 are stacked in the third direction D3 in this order starting from the chip closest to the first surface 62 of the package substrate 60.

[0097] For example, IC chip 110n+7 is IO chip 700A, IC chips 110n+6 and 110n+5 are CPU 220A, and IC chip 110n+4 is TCI-IO chip 500C. The surface of IC chip 110n+7 facing wiring layer 150n+7 corresponds to first surface 202, and the surface of IC chip 110n+4 facing semiconductor substrate 173n+4 corresponds to second surface 204.

[0098] For example, the TCI-IO chip 500C includes a portion including terminals C and D of the inductor 272, the transmitter / receiver circuit 214, and the parallel-serial conversion circuit 213. For example, the IO chip 700 has a function of interfacing between the semiconductor module 10 and an external device in order to input and output control signals, a power supply voltage (voltage VDD), a ground voltage (voltage VSS), and the like between the stacked memory chip 100, the CPU 220A, and the TCI-IO chip 500C and an external device, etc. For example, the voltage VDD is a power supply voltage such as 1 V or 3 V, and the voltage VSS is 0 V, for example.

[0099] The first semiconductor chip 200 also includes an inductor 272 provided across the multiple IC chips 110. The inductor 272 is provided along the second direction D2, parallel to the third direction D3 (the third surface 206), and spaced apart from the third surface 206. For example, the end 101 of the inductor 272 shown in FIG. 6 is spaced a distance L1 from the first surface 62 of the package substrate 60, and the length of the inductor 272 along the third direction D3 is L2. For example, the length L2 may be the length of each of the first portion 272a, the second portion 272b, and the fourth portion 272e, or the length of the opposite side of the first portion 272a including the terminal C, the terminal D, the third portion 272c, and the fifth portion 272d. For example, the length L2 may be the diameter of the inductor 272. 6 is provided across the IC chip 110n+7, the IC chip 110n+6, the IC chip 110n+5, and the IC chip 110n+4. Similar to the inductor 172, the inductor 272 is formed using a plurality of wirings, through electrodes, etc.

[0100] 6, IC chip 110n+5, IC chip 110n+6, and IC chip 110n+7 each include a corresponding semiconductor substrate 173, a transistor layer, and a wiring layer, similar to IC chip 110n+4.

[0101] The first semiconductor chip 200 shown in FIG. 6 includes four IC chips 110n+4 to 110n+7 that are F2B bonded, and is mounted face down on a package substrate 60.

[0102] As with the stacked memory chip 100A, the number of stacked IC chips 110, bonding, and mounting structure of the first semiconductor chip 200 shown in Fig. 6 are merely examples, and the number of stacked IC chips 110, bonding, and mounting structure of the first semiconductor chip 200 are not limited to the bonding and mounting structure shown in Fig. 6. For example, the first semiconductor chip 200 may include a configuration in which five or more IC chips 110 are F2B bonded, or may include a configuration in which three or fewer IC chips are F2B bonded, and may be mounted face-up on the package substrate 60.

[0103] As described above, the stacked memory chip 100 includes an inductor 172 provided across the IC chips 110n, 110n+1, 110n+2, and 110n+3, and the first semiconductor chip 200 includes an inductor 272 provided across the IC chips 110n+4, 110n+5, 110n+6, and 110n+7. As a result, the diameters of the inductors in the stacked memory chip 100 and the first semiconductor chip 200 do not depend on the thickness of a single IC chip, and can therefore be larger than when an inductor is formed on a single IC chip. Therefore, the semiconductor module 10 is a module that can improve the efficiency of signal transmission through inductor communication.

[0104] Furthermore, by making the inductor 172 and the inductor 272 larger in the semiconductor module 10, the operational margin of inductor communication with respect to misalignment between the inductors can be increased compared to when the inductors are formed on a single IC chip.

[0105] Furthermore, the inductor 172 is not exposed on the third surface 146, and the inductor 272 is not exposed on the third surface 206. As a result, for example, the inductors 172 and 272 can be prevented from being damaged by electrostatic discharge (ESD), and therefore the semiconductor module 10 can prevent a decrease in the long-term reliability of the inductors 172 and 272.

[0106] The second semiconductor chip 600 has a different function from, but a similar configuration to, the first semiconductor chip 200. The semiconductor module 10 includes a configuration that enables inductive communication between the stacked memory chip 100 and the second semiconductor chip 600, and the stacked memory chip 100 and the second semiconductor chip 600 have the same effects as the stacked memory chip 100 and the first semiconductor chip 200.

[0107] 7 , the IC chip 110 includes a first surface 102 parallel to the first direction D1 and the second direction D2, a second surface 104 opposite the first surface 102 in the third direction D3, a transistor layer 130, and a wiring layer 150. The first surface 102 is the surface of the transistor layer 130 opposite to the surface on which the wiring layer 150 is disposed, and the second surface 104 is the surface of the wiring layer 150 opposite to the surface on which the transistor layer 130 is disposed.

[0108] For example, the transistor layer 130 includes a semiconductor substrate 173, an isolation region 174, an activation region 175, a transistor 176, an insulating layer 177, a portion of a wiring 178, and a through electrode 131. For example, the semiconductor substrate 173 is a Si substrate or Si-wafer, and is called a semiconductor substrate.

[0109] For example, the through electrode 131 is formed to penetrate the transistor layer 130 and is electrically connected to the wiring 178 .

[0110] As explained in "1-2-1. Overview of stacked memory chip 100," the wiring layer 150 includes a multilayer wiring structure in which wiring and insulating layers are alternately stacked. The wiring layer 150 includes, for example, a part of wiring 178, insulating layer 179, wiring 180, insulating layer 181, insulating layer 182, and wiring 183. The wiring 183 may be a through electrode.

[0111] For example, wiring 178 is provided to penetrate insulating layer 177 and is electrically connected to the source or drain of transistor 176. For example, wiring 180 is provided to penetrate insulating layer 179 and is electrically connected to wiring 178. For example, wiring 183 is provided to penetrate insulating layer 182 and is electrically connected to wiring 180. The connections of the wirings shown in FIG. 7 are merely examples, and the connections of the wirings are not limited to the configuration shown in FIG. 7. The connections of the wirings can be changed as appropriate based on the application or specifications of the semiconductor module 10. The IC chips 110 included in the stacked memory chips 100 may be called memory chips, and the IC chips 110 included other than the stacked memory chips 100 may be simply called IC chips.

[0112] <1-3. Configuration of stacked memory chip 100> The functional block configuration of the stacked memory chip 100 will be described with reference to Fig. 8. Fig. 8 is a block diagram showing the functional block configuration of the stacked memory chip 100. Configurations that are the same as or similar to those in Figs. 1 to 7 will be described as necessary, and descriptions of configurations that are the same as or similar to those in Figs. 1 to 7 may be omitted.

[0113] 8, the stacked memory chip 100 includes a plurality of memory modules 111. Each of the plurality of memory modules 111 includes a memory cell array 115.

[0114] Each of the plurality of memory modules 111 has a function of storing data included in a received signal in the memory cell array 115, and a function of reading data from the memory cell array 115 and transmitting a signal including the data. The plurality of memory modules 111 are electrically connected to a plurality of power supply wirings 164, a plurality of ground wirings 165, and a plurality of signal transmission wirings 166.

[0115] For example, the plurality of power supply wirings 164 and the plurality of ground wirings 165 are electrically connected to the plurality of bumps 82 and are electrically connected to the package substrate 60, and are supplied with a power supply voltage VDD and a voltage VSS from an external circuit. Also, for example, the plurality of signal transmission wirings 166 are electrically connected to the TCI-IO 112. The plurality of signal transmission wirings 166 are connected to the first semiconductor chip 200, the second semiconductor chip 600, and an external circuit (not shown) by inductor communication, and are supplied with control signals such as address signals and enable signals for controlling the IC chip 110, and signals including data, from the first semiconductor chip 200, the second semiconductor chip 600, and the external circuit.

[0116] The memory cell array 115 includes a plurality of memory cells (not shown). Each of the plurality of memory cell arrays 115 is, for example, a static random access memory (SRAM), and each of the plurality of memory cells is an SRAM cell. The SRAM, SRAM cells, and SRAM memory module 111 may employ technology used in the SRAM technical field. Therefore, detailed description thereof will be omitted here. The plurality of memory cell arrays 115 and the plurality of memory cells may be memory cell arrays and memory cells other than SRAM, such as a magnetoresistive random access memory (MRAM) and MRAM cells.

[0117] Second Embodiment A semiconductor module 10A according to a second embodiment will be described with reference to Fig. 9. Fig. 9 is an end view showing an enlarged view of a portion of the end cross-sectional structure of the stacked memory chip 100A, the first semiconductor chip 200, and the bump layer 800 of the semiconductor module 10A. Configurations that are the same as or similar to those in Figs. 1 to 8 will be described as necessary, and descriptions of configurations that are the same as or similar to those in Figs. 1 to 8 may be omitted.

[0118] The semiconductor module 10A differs from the semiconductor module 10 in the following configurations (1) to (3): (1) The IC chip 110n+3 of the stacked memory chip 100A is a TCI-IO chip 500A. (2) The inductor 172 is electrically connected to the transistor layer 130n+3 and the wiring layer 150n+3 of the stacked memory chip 100A. (3) An insulating film 190 is filled between the ends of the semiconductor substrates 173n+1 and 173n+2 of the stacked memory chip 100A and the third surface 146.

[0119] The configuration of the semiconductor module 10A other than the configurations shown in (1) to (3) is the same as that of the semiconductor module 10. Therefore, only the differences from the semiconductor module 10 will be explained here. Note that, like the semiconductor module 10, the number of layers of the IC chip 110, the bonding and mounting structure can be changed as appropriate depending on the specifications, applications, etc. of the semiconductor module 10A.

[0120] For example, the insulating film 190 is made of SiO ２ , SiN, SiON, SiCN, and composite films thereof can be used. The insulating film 190 may also cover insulating layers exposed on the third surface 146 (for example, insulating layers 179, 181, and 182 shown in FIG. 7).

[0121] In particular, if the insulating layer exposed on the third surface 146 includes a low dielectric constant film, there is a risk that the insulating layer exposed on the third surface 146 will be contaminated by metal, which may cause corrosion or deterioration of each element in the IC chip 110 due to moisture absorption and the intrusion of impurities, etc.

[0122] For example, the semiconductor module 10A can cover the third surface 146 with the insulating film 190. As a result, the semiconductor module 10A can prevent the semiconductor substrates 173n+1 and 173n+2 from being contaminated by metal, and can prevent corrosion and deterioration of each element in the IC chip 110 due to moisture absorption and the intrusion of impurities, etc. Therefore, the semiconductor module 10A can maintain its reliability without impairing its long-term reliability.

[0123] Furthermore, the semiconductor module 10A has the same effects as the semiconductor module 10.

[0124] Third Embodiment A semiconductor module 10B according to a third embodiment will be described with reference to Fig. 10. Fig. 10 is an end view showing an enlarged view of a portion of the end cross-sectional structure of the stacked memory chip 100A, the first semiconductor chip 200, and the bump layer 800 of the semiconductor module 10B. Configurations that are the same as or similar to those in Figs. 1 to 9 will be described as necessary, and descriptions of configurations that are the same as or similar to those in Figs. 1 to 9 may be omitted.

[0125] The semiconductor module 10B differs from the semiconductor module 10A in the following configurations (1) and (2): (1) The gap between the semiconductor substrate 173n+2 and the third surface 146 of the stacked memory chip 100B is filled with an insulating film 190. (2) The gaps between the end of the semiconductor substrate 173n+5, the end of the semiconductor substrate 173n+6, and the end of the semiconductor substrate 173n+7 of the first semiconductor chip 200 and the third surface 206 are filled with an insulating film 190.

[0126] The configuration of the semiconductor module 10B is the same as that of the semiconductor module 10A except for the configurations shown in (1) and (2). Therefore, here, differences from the semiconductor module 10A will be explained. Note that, as with the semiconductor module 10A, the number of IC chips 110 stacked, the bonding, and the mounting structure can be changed as appropriate depending on the specifications, applications, etc. of the semiconductor module 10B. Furthermore, the configuration of the semiconductor module 10B can be applied as appropriate to semiconductor modules other than the semiconductor modules 10 and 10A as long as there are no mutual contradictions.

[0127] The semiconductor module 10B has the same functions and effects as the semiconductor modules 10 and 10A.

[0128] Fourth Embodiment A semiconductor module 10C according to a fourth embodiment will be described with reference to Fig. 11. Fig. 11 is an end view showing an enlarged view of a portion of the end cross-sectional structure of the stacked memory chip 100A, the first semiconductor chip 200, and the bump layer 800 of the semiconductor module 10C. Configurations that are the same as or similar to those in Figs. 1 to 10 will be described as necessary, and descriptions of configurations that are the same as or similar to those in Figs. 1 to 10 may be omitted.

[0129] The semiconductor module 10C differs from the semiconductor module 10 in the following configurations (1) to (7): (1) The stacked memory chip 100A includes three IC chips 110 (IC chip 110n, IC chip 110n+1, and IC chip 110n+2). (2) The IC chips 110n, 110n+1, and 110n+2 of the stacked memory chip 100A are stacked in the third direction D3 in order of proximity to the first surface 62 of the package substrate 60. (3) The IC chip 110n+2 of the stacked memory chip 100A is a TCI-IO chip 500A. (4) An inductor 172 is provided across the IC chips 110n, 110n+1, and 110n+2 of the stacked memory chip 100A. (5) The inductor 172 is electrically connected to the transistor layer 130n+2 and the wiring layer 150n+2 of the stacked memory chip 100A. (6) The thickness of each of the IC chips 110n, 110n+1, and 110n+2 of the stacked memory chip 100A is thickness T1. (7) The thickness of each of the IC chips 110n+4, 110n+5, 110n+6, and 110n+7 of the first semiconductor chip 200 is thickness T2.

[0130] The configuration of the semiconductor module 10C other than the configurations shown in (1) to (7) is the same as that of the semiconductor module 10B. As with the semiconductor module 10B, the number of stacked IC chips 110, the bonding, and the mounting structure can be changed as appropriate depending on the specifications and application of the semiconductor module 10C. The configuration of the semiconductor module 10C can also be applied as appropriate to semiconductor modules other than the semiconductor modules 10, 10A, and 10B, as long as there are no mutual contradictions. The semiconductor module 10C has the same functions and effects as the semiconductor module 10.

[0131] Fifth Embodiment A semiconductor module 10D according to a fifth embodiment will be described with reference to FIGS. 12 to 14. FIG. 12 is an end view showing an enlarged portion of the end cross-sectional structure of the stacked memory chips 100A and 100D, adhesive layer 850, third semiconductor chip 900, bump layer 800 (bumps 82), and package substrate 60 of the semiconductor module 10D. FIG. 13 is a perspective view showing multiple inductors 172 included in the stacked memory chip 100A, multiple inductors 172 included in the stacked memory chip 100D, and multiple inductors 372 included in the third semiconductor chip 900. FIG. 14 is a block diagram showing the functional block configuration of the semiconductor module 10D. Configurations that are the same as or similar to those in FIGS. 1 to 11 will be described as necessary, and descriptions of configurations that are the same as or similar to those in FIGS. 1 to 11 may be omitted.

[0132] The semiconductor module 10D differs from the semiconductor module 10 in the following configurations (1) to (4): (1) It includes a third semiconductor chip 900. (2) The stacked memory chips 100A and 100D include a first surface 142 and a second surface 144 that are parallel to the third direction D3 and the second direction D2 and are the outermost surfaces along the second direction D2, a third surface 146 that is parallel to the first surface 902 of the third semiconductor chip 900 and is the outermost surface on the first surface 902 side along the third direction D3, a plurality of IC chips 110 stacked parallel to the third surface 146, and an inductor 172 that is provided across the plurality of IC chips 110, and are provided on the first surface 902. (3) The first surface 142 of the stacked memory chip 100A and the second surface 144 of the stacked memory chip 100D are F2B bonded to each other. (4) The third surface 146 of the stacked memory chip 100A and the third surface 146 (100D) of the stacked memory chip 100D are connected to the first surface 902 of the third semiconductor chip 900 by the adhesive layer 850.

[0133] The semiconductor module 10D has the same configuration as the semiconductor module 10 except for the configurations shown in (1) to (4). Therefore, only the differences from the semiconductor module 10 will be described here. As with the semiconductor module 10, the number of IC chips 110 stacked, the bonding, and the mounting structure can be changed as appropriate depending on the specifications and applications of the semiconductor module 10D. The configuration of the semiconductor module 10D can also be applied to semiconductor modules other than the semiconductor module 10 as appropriate, as long as there are no mutual contradictions. The configuration and function of the stacked memory chip 100D are the same as those of the stacked memory chip 100A, and the configuration and function of the package substrate 60 in the semiconductor module 10D are the same as those of the package substrate 60 in the semiconductor module 10. Therefore, detailed descriptions of the stacked memory chip 100D and the package substrate 60 will be omitted here.

[0134] 12 , the semiconductor module 10D will be described. The third semiconductor chip 900 includes a second surface 904 that faces parallel to the first surface 62 of the package substrate 60 and is the outermost surface on the first surface 62 side, a first surface 902 that faces the third surface 146 of the stacked memory chips 100 (100A and 100D) opposite the second surface 904 and is the outermost surface on the third surface 146 side, and an IC chip 110n+8. The third semiconductor chip 900 is connected to the third surface 146 (stacked memory chips 100A and 100D) via an adhesive layer 850, electrically connected to the first surface 902 via a plurality of bumps 82, and disposed between the first surface 902 and the third surface 146. The IC chip 110n+8 includes a transistor layer 130n+8 including a semiconductor substrate 173n+8 and a wiring layer 150n+8. For convenience of explanation, the semiconductor substrate 173n+8 shown in FIG. 12 is separated from the transistor layer 130n+8. The third semiconductor chip 900 also includes a plurality of inductors 372 arranged parallel to and spaced apart from the first surface 902. For example, the plurality of inductors 372 are arranged across the wiring layer 150n+8 and the transistor layer 130n+8. The plurality of inductors 372 can communicate with the inductors 172 and inductors 172q corresponding to each of the plurality of inductors 372. Note that, for example, if the third semiconductor chip 900 includes a plurality of IC chips 110, the inductors 372 are arranged in the IC chip 110 closest to the third surface 146.

[0135] The third semiconductor chip 900 has a configuration and function including multiple arithmetic circuits (not shown) capable of executing arithmetic processing of signals including control signals and data. The third semiconductor chip 900 also has the same configuration and function as the IO chip 700 and the TCI-IO chip. Therefore, the third semiconductor chip 900 is connected to the stacked memory chips 100A and 100D via inductor communication. The third semiconductor chip 900 is also electrically connected to the package substrate 60 (electrodes 75) via multiple bumps 82. The third semiconductor chip 900 is also electrically connected to an external circuit (not shown) provided on the package substrate 60 or an external circuit (not shown) provided outside the semiconductor module 10D. The third semiconductor chip 900 can receive control signals, such as address signals and enable signals for controlling the stacked memory chips 100A and 100D, and signals including data from the external circuit, and supply (transmit) these signals to the stacked memory chips 100A and 100D.

[0136] As described above, the first surface 902 of the third semiconductor chip 900 is connected to the adhesive layer 850. The second surface 904 of the third semiconductor chip 900 is connected to the plurality of bumps 82. Although not shown, for example, the third semiconductor chip 900 is electrically connected to the bumps 82 using the through electrodes 131 shown in FIG.

[0137] Although not shown, for example, stacked DRAM 300A (see FIG. 14) is electrically connected to through electrodes (not shown) exposed on second surface 144 of stacked memory chip 100A, and stacked DRAM 300D (see FIG. 14) is electrically connected to through electrodes (not shown) exposed on first surface 142 of stacked memory chip 100D. Furthermore, stacked DRAMs 300A and 300D are connected to third semiconductor chip 900 via adhesive layer 850, similar to stacked memory chips 100A and 100D.

[0138] <5-2. Overview of Inductor Communication in Semiconductor Module 10D> Next, an overview of inductor communication in the semiconductor module 10D will be described with reference to FIG.

[0139] The configurations of the inductor 172 and the inductor 172q are similar to the configuration of the inductor 172 according to the first embodiment, and therefore detailed description of the inductors will be omitted here.

[0140] The inductors 372 have a configuration similar to that of the inductors 172. For example, the multiple inductors 372 are provided parallel to a first surface 902 and a second surface 904 that are parallel to the first direction D1 and the second direction D2, and are spaced apart from the first surface 902 on the first surface 902 side. The multiple inductors 372 are arranged in a matrix pattern parallel to the first surface 902 and the second surface 904. Each of the multiple inductors 372 includes a terminal E, a terminal F, a first portion 372a, a second portion 372b, a third portion 372c, a fourth portion 372e, and a fifth portion 372d.

[0141] The fifth portion 372d extends in the second direction D2, one end of which is electrically connected to terminal E, and the other end of which is electrically connected to one end of the fourth portion 372e. The fourth portion 372e extends in the first direction D1, and the other end of which is electrically connected to one end of the first portion 372a. The first portion 372a extends in the second direction D2, and the other end of which is electrically connected to one end of the second portion 372b. The second portion 372b extends in the first direction D1, and the other end of which is electrically connected to one end of the third portion 372c. The third portion 372c extends in the second direction D2, and the other end of which is electrically connected to terminal F.

[0142] The inductor 172 and the inductor 372 are provided on a plane (the third surface 146 and the first surface 902) parallel to the first direction D1 and the second direction D2, and on a plane perpendicular to the third direction D3.

[0143] When a plane (e.g., the first plane 902) parallel to the first direction D1 and the second direction D2 is viewed from the third direction D3, each of the multiple inductors 172 faces a corresponding inductor 372 in parallel and overlaps with each other, enabling one-to-one communication. For example, the inductor 172 shown in FIG. 13 faces the inductor 372 in parallel and overlaps with it to perform inductor communication, and the inductor 172q shown in FIG. 13 faces the inductor 372 in parallel and overlaps with it to perform inductor communication. Note that, like the shapes of the inductors 172 and 172q, the shape of the inductor 372 is not limited to a rectangular shape and may be any shape that enables inductor communication. When a plane (e.g., the first plane 902) parallel to the first direction D1 and the second direction D2 is viewed from the third direction D3, it may be referred to as a planar view.

[0144] For example, as shown in the lower diagram of Fig. 13, inductors 172 and 372 are arranged parallel to each other and face each other, and one-to-one non-contact inductor communication is possible by magnetic field coupling. In the example shown in the lower diagram of Fig. 13, a magnetic field is generated by a first portion 172a of inductor 172 and a first portion 372a of inductor 372, and a magnetic field is generated by a second portion 172b of inductor 172 and a second portion 372b of inductor 372, and the magnetic fields generated by the third portion, fourth portion, and fifth portion of each inductor are omitted.

[0145] The normal vectors of inductor 172 and inductor 372 to parallel surfaces (e.g., third surface 146 and first surface 902) are the same, and the magnetic field shown in Figure 13 is an example, and the magnetic field actually generated is not limited to the magnetic field shown in Figure 13.

[0146] <5-3. Configuration of Semiconductor Module 10D> Next, the functional block configuration of the semiconductor module 10D will be described with reference to FIGS.

[0147] As shown in FIG. 12, FIG. 13, or FIG. 14, the semiconductor module 10D includes stacked memory chips 100A and 100D, stacked DRAMs 300A and 300D, and a third semiconductor chip 900.

[0148] The stacked memory chips 100A and stacked DRAMs 300A of the semiconductor module 10D have the same configurations and functions as the stacked memory chips 100A and stacked DRAMs 300A of the semiconductor module 10. The stacked memory chips 100D and stacked DRAMs 300D also have the same configurations and functions as the stacked memory chips 100A and stacked DRAMs 300A. Therefore, a description of the configurations and functions of the stacked memory chips 100A and 100D and stacked DRAMs 300A and 300D of the semiconductor module 10D will be omitted.

[0149] The third semiconductor chip 900 includes a plurality of TCI-IOs 312 and a logic module 910. The plurality of TCI-IOs 312 are electrically connected to the logic module 910. As described above, the third semiconductor chip 900 has a configuration and function capable of performing arithmetic processing of signals including control signals and data, a configuration and function similar to the configuration and function of the IO chip 700, and the TCI-IO. For example, the logic module 910 has a configuration and function capable of performing arithmetic processing of signals including control signals and data, and may have a configuration and function similar to at least a portion of the configuration and function of the IO chip 700 and at least a portion of the configuration and function of the TCI-IO. For example, the third semiconductor chip 900 may include a plurality of IC chips 110. For example, the plurality of TCI-IOs 312 may be formed on a first IC chip 110, the logic module 910 may be formed on another IC chip 110, and the first IC chip 110 and the other IC chip 110 may be joined by F2B bonding.

[0150] The TCI-IO 312 includes an inductor 372 (third inductor), a transmitting / receiving circuit 314, and a parallel-serial conversion circuit 313. The inductor 372 is electrically connected to the transmitting / receiving circuit 314 using terminals E and F. The transmitting / receiving circuit 314 is electrically connected to the parallel-serial conversion circuit 313. The parallel-serial conversion circuit 313 is electrically connected to the logic module 910.

[0151] The configurations and functions of the inductor 372 , the transmitting / receiving circuit 314 and the parallel-serial conversion circuit 313 are similar to the configurations and functions of the inductor 172 , the transmitting / receiving circuit 114 and the parallel-serial conversion circuit 113 of the semiconductor module 10 .

[0152] The semiconductor module 10D having the configuration and functions described above has the same effects as the semiconductor module 10.

[0153] Sixth Embodiment A semiconductor module 10E according to a sixth embodiment will be described with reference to Fig. 15. Fig. 15 is an end view showing an enlarged portion of the end cross-sectional structure of the stacked memory chips 100A and 100D, adhesive layer 850, third semiconductor chip 900, bump layer 800 (bumps 82), and package substrate 60 of the semiconductor module 10E. Configurations that are the same as or similar to those in Figs. 1 to 14 will be described as necessary, and descriptions of configurations that are the same as or similar to those in Figs. 1 to 14 may be omitted.

[0154] The semiconductor module 10E differs from the semiconductor module 10D in the following configuration (1): (1) The insulating film 190 is filled between the end of the semiconductor substrate 173n+1, the end of the semiconductor substrate 173n+2, and the end of the semiconductor substrate 173n+3 of the stacked memory chips 100A and 100D and the third surface 146.

[0155] The configuration of the semiconductor module 10E is the same as that of the semiconductor module 10D except for the configuration indicated by (1). Therefore, only the differences from the semiconductor module 10D will be described here. As with the semiconductor module 10, the number of IC chips 110 stacked, the bonding, and the mounting structure can be changed as appropriate depending on the specifications and applications of the semiconductor module 10E. Furthermore, the configuration of the semiconductor module 10E can be applied to semiconductor modules other than the semiconductor module 10 as appropriate, as long as there are no mutual contradictions.

[0156] The semiconductor module 10E has the same effects as the semiconductor modules 10B and 10D.

[0157] Seventh Embodiment A semiconductor module 10F according to a seventh embodiment will be described with reference to Fig. 16. Fig. 16 is an end view showing an enlarged view of a portion of the end cross-sectional structure of the stacked memory chip 100A, the first semiconductor chip 200, and the bump layer 800 (bumps 82) of the semiconductor module 10F. Configurations that are the same as or similar to those in Figs. 1 to 15 will be described as necessary, and descriptions of configurations that are the same as or similar to those in Figs. 1 to 15 may be omitted.

[0158] The semiconductor module 10F differs from the semiconductor module 10 in the following configurations (1) to (3): (1) The thicknesses of IC chip 110n and IC chip 110n+3 of the stacked memory chip 100A are thickness T1, IC chip 110n+1 is thickness T3, and IC chip 110n+2 is thickness T4. (2) The thicknesses of IC chip 110n+4, IC chip 110n+5, IC chip 110n+6, and IC chip n+7 of the first semiconductor chip 200 are each thickness T2. (3) For example, thickness T1 is the same as thickness T2, and thickness T1 is thinner than thickness T3 and thicker than thickness T4.

[0159] The configuration of the semiconductor module 10F other than the configurations shown in (1) to (3) is the same as that of the semiconductor module 10. Therefore, here, differences from the semiconductor module 10 will be explained. Note that, like the semiconductor module 10, the number of IC chips 110 stacked, the bonding, and the mounting structure can be changed as appropriate depending on the specifications, applications, etc. of the semiconductor module 10F. Furthermore, the configuration of the semiconductor module 10F can also be applied as appropriate to semiconductor modules other than the semiconductor module 10, as long as there are no mutual contradictions.

[0160] As described above, the semiconductor module 10F includes a plurality of IC chips 110 having different thicknesses. In the semiconductor module 10F, inductors can be provided across the plurality of IC chips 110 in accordance with the plurality of IC chips 110 having different thicknesses.

[0161] The semiconductor module 10F has the same functions and effects as the semiconductor module 10.

[0162] Eighth Embodiment A semiconductor module 10G according to an eighth embodiment will be described with reference to Fig. 17. Fig. 17 is an end view showing an enlarged view of a portion of the end cross-sectional structure of the stacked memory chip 100A, the first semiconductor chip 200, and the bump layer 800 (bumps 82) of the semiconductor module 10G. Configurations that are the same as or similar to those in Figs. 1 to 16 will be described as necessary, and descriptions of configurations that are the same as or similar to those in Figs. 1 to 16 may be omitted.

[0163] The semiconductor module 10G differs from the semiconductor module 10 in the following configuration (1): (1) Between the third surface 146 of the stacked memory chip 100A and the third surface 206 of the first semiconductor chip 200, a structure 860 is provided, which includes a material having a higher magnetic permeability than the material included in the stacked memory chip 100A and the material included in the first semiconductor chip 200.

[0164] The configuration of the semiconductor module 10G other than the configuration indicated by (1) is the same as that of the semiconductor module 10. Therefore, differences from the semiconductor module 10 will be described here. Note that, like the semiconductor module 10, the number of IC chips 110 stacked, the bonding, and the mounting structure can be changed as appropriate depending on the specifications, applications, etc. of the semiconductor module 10G. Furthermore, the configuration of the semiconductor module 10G can also be applied as appropriate to semiconductor modules other than the semiconductor module 10, as long as there are no mutual contradictions.

[0165] For example, the structure 860 may contain Ni as a material, or may contain a material having a magnetic permeability equal to or greater than that of Ni. For example, the structure 860 is applied onto the first surface 62 of the package substrate 60 between the third surface 146 of the stacked memory chips 100A and the third surface 206 of the first semiconductor chip 200 using an inkjet device or the like. For example, the width W1 between the third surface 146 of the stacked memory chips 100A and the third surface 206 of the first semiconductor chip 200 is 30 μm.

[0166] The semiconductor module 10F has the structure 860 including a material with high magnetic permeability, and can increase the Q value in inductor communication compared to a case where the semiconductor module 10F does not include the structure 860. As a result, the semiconductor module 10F can improve the efficiency of inductor communication.

[0167] Furthermore, the semiconductor module 10G has the same functions and effects as the semiconductor module 10.

[0168] Ninth Embodiment A semiconductor module 10H according to a ninth embodiment will be described with reference to Fig. 18. Fig. 18 is an end view showing an enlarged view of a portion of the end cross-sectional structure of the stacked memory chip 100A, the first semiconductor chip 200, and the bump layer 800 (bumps 82) of the semiconductor module 10H. Configurations that are the same as or similar to those in Figs. 1 to 17 will be described as necessary, and descriptions of configurations that are the same as or similar to those in Figs. 1 to 17 may be omitted.

[0169] The semiconductor module 10H differs from the semiconductor module 10 in the following configurations (1) to (3): (1) The multiple inductors 172 are aligned along the third direction D3. Although not shown, the multiple inductors 172 are also aligned in the second direction D2. (2) The multiple inductors 272 are aligned along the third direction D3. Although not shown, the multiple inductors 272 are also aligned in the second direction D2. (3) The distances between the ends of opposing inductors (e.g., ends 101 and 103) and the first surface 62 of the package substrate 60 are the same.

[0170] The configuration of the semiconductor module 10H other than the configurations shown in (1) to (3) is the same as that of the semiconductor module 10. Therefore, here, differences from the semiconductor module 10 will be explained. Note that, like the semiconductor module 10, the number of IC chips 110 stacked, the bonding and mounting structure can be changed as appropriate depending on the specifications, applications, etc. of the semiconductor module 10G. Furthermore, the configuration of the semiconductor module 10H can also be applied as appropriate to semiconductor modules other than the semiconductor module 10, as long as there are no mutual contradictions.

[0171] The inductors 172 are arranged in a matrix in the first direction D1 and the third direction D3. The inductors 172 are provided parallel to the third surface 146 and spaced apart from the third surface 146.

[0172] Similar to the multiple inductors 172, the multiple inductors 272 are arranged in a matrix in the first direction D1 and the third direction D3, and are provided parallel to and spaced apart from the third surface 206.

[0173] For example, inductor 172o is provided across IC chips 110n and 110n+1, and inductor 172p is provided across IC chips 110n+2 and 110n+3. Terminals A and B of inductor 172o and inductor 172p are provided on IC chip 110n. Furthermore, inductor 272o is provided across IC chips 110n+4 and 110n+5, and inductor 172p is provided across IC chips 110n+6 and 110n+7. Terminals C and D of inductor 271o and inductor 271p are provided on IC chip 110n+4. IC chip 110n is the TCI-IO chip 500A, and IC chip 110n+4 is the TCI-IO chip 500C.

[0174] The inductor 172p and the inductor 272p are arranged to face each other. The length L1 from the first surface 62 to the end 101 of the inductor 172p is the same as the length L1 from the first surface 62 to the end 101 of the inductor 272p. The length L3 of the inductor 172p along the third direction D3 is the same as the length L3 of the inductor 272p along the third direction D3.

[0175] Similar to the inductors 172p and 272p, the inductors 172o and 272o are arranged to face each other. The length L4 from the first surface 62 to the end 103 of the inductor 272o is the same as the length L4 from the first surface 62 to the end 103 of the inductor 272o. Furthermore, the length L3 of the inductor 172o along the third direction D3 is the same as the length L3 of the inductor 272o along the third direction D3.

[0176] The inductors 172o and 272o are magnetically coupled to each other, thereby enabling contactless communication, and the inductors 172p and 272p are magnetically coupled to each other, thereby enabling contactless communication.

[0177] As described above, the semiconductor module 10H includes a configuration in which the terminals of the multiple inductors arranged along the third direction D3 are connected to the same TCI-IO chip. That is, because the terminals of the multiple inductors in the semiconductor module 10H are all connected to the same TCI-IO chip, the semiconductor module 10H can prevent the routing of the wiring included in the multiple inductors from being dispersed within the IC chip. Furthermore, for example, the wiring (e.g., the third and fifth portions of each) connected to the terminals of adjacent inductors 172o and 172p is provided sufficiently spaced apart. Therefore, interference between the inductors is suppressed.

[0178] Furthermore, the semiconductor module 10H has the same effects as the semiconductor module 10.

[0179] Tenth Embodiment A semiconductor module 10J according to a tenth embodiment will be described with reference to FIGS. 19 and 20. FIG. 19 is an end view showing an enlarged portion of the end cross-sectional structure of the stacked memory chip 100A, the first semiconductor chip 200, and the bump layer 800 (bumps 82) of the semiconductor module 10J. FIG. 20 is a plan view showing the configuration of the bump layer 800 of the semiconductor module 10J. Configurations that are the same as or similar to those in FIGS. 1 to 18 will be described as necessary, and descriptions of configurations that are the same as or similar to those in FIGS. 1 to 18 may be omitted.

[0180] <10-1. Overview of Semiconductor Module 10J> First, an overview of the semiconductor module 10J will be described with reference to FIG.

[0181] One of the challenges of the semiconductor module 10J is to improve the efficiency of signal transmission by inductor communication by aligning the position of the inductor 172 from the first surface 62 of the package substrate 60 with the position of the inductor 272 from the first surface 62 of the package substrate 60.

[0182] As one means for solving the above problems, the semiconductor module 10J includes the following configurations (1) to (6). The following configurations (1) to (6) differ from those of the semiconductor module 10. (1) The bump layer 800 includes not only a plurality of bumps 82 but also a plurality of bumps 82A. (2) For example, the diameter of the bump 82 is length D1, and the diameter of the bump 82A is length D2, with length D1 being longer than length D2. (3) For example, the center-to-center length of two adjacent bumps 82 is the same as the center-to-center length of two adjacent bumps 82A, which is length X1. (4) The stacked memory chip 100A is electrically connected to the package substrate 60 (a plurality of electrodes 75) by a plurality of bumps 82. (5) The first semiconductor chip 200 is electrically connected to the package substrate 60 (a plurality of electrodes 75) by a plurality of bumps 82A. (6) For example, the length L6 from the first surface 62 of the package substrate 60 to the first surface 202 of the first semiconductor chip 200 is longer than the length L5 from the first surface 62 of the package substrate 60 to the first surface 142 of the stacked memory chip 100A.

[0183] The configuration of the semiconductor module 10J is the same as that of the semiconductor module 10 except for the configurations shown in (1) to (6). Therefore, only the differences from the semiconductor module 10 will be described here. Note that, like the semiconductor module 10, the number of IC chips 110 stacked, the bonding, and the mounting structure can be changed as appropriate depending on the specifications, applications, etc. of the semiconductor module 10J. Furthermore, the configuration of the semiconductor module 10J can be applied as appropriate to semiconductor modules other than the semiconductor module 10, as long as there are no mutual contradictions.

[0184] For example, the lengths X1 and X2 are parallel to the first direction D1, and the lengths L5, L6, L1, and L2 are parallel to the third direction D1. Also, for example, the lengths Y1 (see FIG. 20) and Y2 (see FIG. 20) are parallel to the second direction D2.

[0185] As described above, in order to improve the efficiency of signal transmission through inductor communication in semiconductor module 10J, length D2 of bump 82A is made longer than length D1 of bump 82, and length L5 is made longer than length L6. As a result, length L1 from first surface 62 of package substrate 60 to end 101 of inductor 172 is made the same as length L1 from first surface 62 of package substrate 60 to end 101 of inductor 272.

[0186] Therefore, the semiconductor module 10J can align the position of the inductor 172 from the first surface 62 of the package substrate 60 with the position of the inductor 272 from the first surface 62 of the package substrate 60. As a result, the normal vector of the inductor 172 of the stacked memory chip 100 coincides with the normal vectors of the inductors 272 and 672 of the first semiconductor chip 200 and the second semiconductor chip 600, and therefore the semiconductor module 10J can improve the efficiency of signal transmission through inductor communication.

[0187] Furthermore, the semiconductor module 10J has the same effects as the semiconductor module 10.

[0188] <10-2. Configuration of Bump Layer 800 of Semiconductor Module 10J> Next, the configuration of the bump layer 800 of the semiconductor module 10J will be described with reference to FIG.

[0189] For example, the stacked memory chip 100A is electrically connected to the package substrate 60 (the plurality of electrodes 75) by 16 bumps 82. Meanwhile, the first semiconductor chip 200 is electrically connected to the package substrate 60 (the plurality of electrodes 75) by 25 bumps 82A. Therefore, the number of the plurality of bumps 82 may be different from the number of the plurality of bumps 82A.

[0190] For example, length D1 may be different from length D2 and length X1 may be different from length X2. Alternatively, length D1 may be the same as length D2 and length X1 may be different from length X2. Lengths Y1 and Y2 may be the same as lengths X1 and X2.

[0191] For example, the diameter D1 of the bump 82 and the diameter D2 of the bump 82A may be 10 μm or more and 150 μm or less.

[0192] As described above, one of the objectives of the semiconductor module 10J is to align the position of the inductor 172 from the first surface 62 of the package substrate 60 with the position of the inductor 272 from the first surface 62 of the package substrate 60, and it is possible to adjust the diameter of the bumps 82 that connect the stacked memory chip 100 to the package substrate 60, the diameter of the bumps 82A that connect the first semiconductor chip 200 to the package substrate 60, as well as the center-to-center lengths of adjacent bumps 82 and adjacent bumps 82A. Therefore, the bump layer 800 of the semiconductor module 10J has a high degree of freedom.

[0193] Eleventh Embodiment A semiconductor module 10K according to an eleventh embodiment will be described with reference to FIG. 21. FIG. 21 is an end view showing an enlarged view of a portion of the end cross-sectional structure of the stacked memory chip 100A, the first semiconductor chip 200, and the bump layer 800 (bumps 82) of the semiconductor module 10K. Configurations that are the same as or similar to those in FIGS. 1 to 20 will be described as necessary, and descriptions of configurations that are the same as or similar to those in FIGS. 1 to 20 may be omitted. Note that in FIG. 21, inductors are not shown.

[0194] The semiconductor module 10K differs from the semiconductor module 10 in the following configurations (1) to (4): (1) The stacked memory chip 100A includes a side-surface power supply wiring 162, a side-surface ground wiring 163, and an insulating film 52. (2) The first semiconductor chip 200 includes a side-surface power supply wiring 262, a side-surface ground wiring 263, and an insulating film 54. (3) The semiconductor module 10K includes a plurality of bumps 84. (4) Each of the plurality of bumps 84 electrically connects the corresponding side-surface power supply wiring 162 and side-surface power supply wiring 262, and electrically connects the corresponding side-surface ground wiring 163 and side-surface ground wiring 263.

[0195] The configuration of the semiconductor module 10K other than the configurations shown in (1) to (4) is the same as that of the semiconductor module 10. Therefore, here, differences from the semiconductor module 10 will be explained. Note that, like the semiconductor module 10, the number of IC chips 110 stacked, the bonding and mounting structure can be changed as appropriate depending on the specifications, applications, etc. of the semiconductor module 10K. Furthermore, the configuration of the semiconductor module 10K can also be applied as appropriate to semiconductor modules other than the semiconductor module 10, as long as there are no mutual contradictions.

[0196] For example, the power supply wiring 164 (see FIG. 8) is exposed to the wiring layer 150n of the IC chip 110n (see FIG. 6) and the wiring layer 150n+2 of the IC chip 110n+2 (see FIG. 6), and the side power supply wiring 162 covers and electrically connects to the power supply wiring 164. The side power supply wiring 162 also contacts the third surface 146. Similar to the power supply wiring 164, for example, the ground wiring 165 (see FIG. 8) is exposed to the wiring layer 150n+1 of the IC chip 110n+1 (see FIG. 6), and the side ground wiring 163 covers and electrically connects to the ground wiring 165. The side ground wiring 163 also contacts the third surface 146.

[0197] Furthermore, the insulating film 52 is provided on the side surface power supply wiring 162, the side surface ground wiring 163, and the third surface 146 that is not in contact with the side surface power supply wiring 162 and the side surface ground wiring 163. At this time, the side surface power supply wiring 162 and the side surface ground wiring 163 are exposed from the insulating film 52.

[0198] For example, the side-surface power supply wiring 262 has a configuration similar to that of the side-surface power supply wiring 162, and covers and electrically connects to the power supply wiring (not shown) exposed from the wiring layer 150n+4 of the IC chip 110n+4 (see FIG. 6) and the wiring layer 150n+6 of the IC chip 110n+6 (see FIG. 6). The side-surface ground wiring 263 has a configuration similar to that of the side-surface ground wiring 163, and covers and electrically connects to the ground wiring (not shown) exposed from the wiring layer 150n+5 of the IC chip 110n+5 (see FIG. 6).

[0199] Furthermore, the insulating film 54 is provided on the side surface power supply wiring 262, the side surface ground wiring 263, and the third surface 206 that is not in contact with the side surface power supply wiring 262 and the side surface ground wiring 263. At this time, the side surface power supply wiring 262 and the side surface ground wiring 263 are exposed from the insulating film 54.

[0200] Of the plurality of bumps 84, the bumps 84 corresponding to the side-surface power supply wiring 162 and the side-surface power supply wiring 262 electrically connect the side-surface power supply wiring 162 and the side-surface power supply wiring 262. Also, of the plurality of bumps 84, the bumps 84 corresponding to the side-surface ground wiring 163 and the side-surface ground wiring 263 electrically connect the side-surface ground wiring 163 and the side-surface ground wiring 263.

[0201] The insulating films 52 and 54 are formed using the same material as the insulating film 190 .

[0202] As described above, the semiconductor module 10K can electrically connect adjacent chips to each other using side wiring, which allows, for example, the power supply voltages VDD and VSS supplied to the power supply wiring to be shared between adjacent chips in the semiconductor module 10K.

[0203] Furthermore, the semiconductor module 10K has the same functions and effects as the semiconductor module 10.

[0204] Twelfth Embodiment The configuration of a seal ring 160 and a signal transmission wiring 166 according to a twelfth embodiment of the present invention will be described with reference to FIG. 22. FIG. 22 is a plan view showing the configuration of the seal ring 160 and the ground wiring 165, and is an end view showing the cross-sectional structure of the end of the seal ring 160 and the signal transmission wiring 166 taken along line E1-E2 in the plan view. Configurations that are the same as or similar to those in FIGS. 1 to 21 will be described as necessary, and descriptions of configurations that are the same as or similar to those in FIGS. 1 to 21 may be omitted. Note that the configurations of the seal ring 160 and the signal transmission wiring 166 according to the twelfth embodiment can be applied as appropriate to the semiconductor modules according to each embodiment, as long as there is no mutual contradiction.

[0205] The IC chip 110 includes a seal ring 160. The seal ring 160 is provided in an outer periphery 192 and formed in the wiring layer 150. The signal transmission wiring 166 is formed so as to overlap the seal ring 160 and is formed closer to the third surface 146 than the seal ring 160. For example, the outer periphery 192 is a peripheral portion of the IC chip 110, and is a portion close to each surface (e.g., the first surface 142, the second surface 144, the third surface 146, and the fourth surface 148) of the stacked memory chip 100, the first semiconductor chip 200, and the second semiconductor chip 600. As described in "1-1. Overview of the Semiconductor Module 10," the wiring layer 150 includes a multilayer wiring structure. Note that, for example, when the signal transmission wiring 166 included in the semiconductor modules 10D and 10E is formed so as to overlap the seal ring 160, the signal transmission wiring 166 is formed closer to the first surface 902 than the seal ring 160.

[0206] For example, the wiring layer 150 includes a seven-layer (first to seventh) multilayer wiring structure from the semiconductor substrate 173a side toward the insulating layer 182. The seven-layer multilayer wiring structure includes an insulating layer 151a, a via 151b, an insulating layer 152a, a wiring 152b, an insulating layer 153a, a via 153b, an insulating layer 154a, a wiring 154b, an insulating layer 155a, a via 155b, an insulating layer 156a, a wiring 156b, an insulating layer 182, and a wiring 183. The first insulating layer 151a is formed on the transistor layer 130, and the first via 151b penetrates the insulating layer 151a and is formed on the transistor layer 130. The second insulating layer 152a is formed on the insulating layer 151a and the via 151b, and the second wiring 152b penetrates the insulating layer 152a and is formed on the via 151b. Similar to the first and second layers of the multilayer wiring structure, the third layer, insulating layer 153a and via 153b, fourth layer, insulating layer 154a and wiring 154b, fifth layer, insulating layer 155a and via 155b, sixth layer, insulating layer 156a and wiring 156b, and seventh layer, insulating layer 182 and wiring 183, are formed in this order from the semiconductor substrate 173 side toward the insulating layer 182. For example, the signal transmission wiring 166, the power supply wiring 164 (see FIG. 8 ), and the ground wiring 165 (see FIG. 8 ) are formed using the wiring 183. A part of the inductor 271, the inductor 272, the inductor 372, or the inductor 672 may be formed using the wiring 183.

[0207] For example, the insulating layers 182, 156a, 155a, and 154a are formed using an insulating material other than a material with a low dielectric constant (low-k material). The insulating material forming the insulating layers 182, 156a, 155a, and 154a is, for example, SiO ２ , SiCN, SiN, SiON, etc.

[0208] For example, the seal ring 160 has a function of suppressing moisture absorption and impurities from entering through the surfaces of the stacked memory chip 100, the first semiconductor chip 200, and the second semiconductor chip 600. As a result, the seal ring 160 in the semiconductor module according to each embodiment of the present invention can suppress corrosion and deterioration of wiring due to moisture absorption and the entry of impurities.

[0209] 13th Embodiment A seal ring 160n and an inductor 172 according to a 13th embodiment will be described with reference to FIGS. 23 to 26. FIG. 23 is a plan view showing the configuration of the seal ring 160n and the inductor 172. FIG. 24 is an end view showing the end cross-sectional structure of the seal ring 160n and the inductor 172 taken along line E3-E4 in FIG. 23. FIG. 25 is an end view showing the end cross-sectional structure of the inductor 172 taken along line E5-E6 in FIG. 23. FIG. 26 is an end view showing the end cross-sectional structure of the inductor 172 taken along line E7-E8 in FIG. 23. Configurations that are the same as or similar to those in FIGS. 1 to 22 will be described as necessary, and descriptions of configurations that are the same as or similar to those in FIGS. 1 to 22 may be omitted. The configurations of the seal ring 160n and the inductor 172 according to the 13th embodiment can be applied to the semiconductor modules according to the other embodiments as long as they are not mutually inconsistent.

[0210] 23 to 26 is an inductor having a plurality of windings formed across a plurality of IC chips 110 in end view, and is formed closer to the third surface 146 than the seal ring 160n. The inductor 172 shown in FIGS. 23 to 26 is the inductor 172 included in the semiconductor module according to each embodiment.

[0211] 23 to 26 show two turns of the inductor 172, but the number of turns of the inductor 172 is not limited to two and may be one turn, or three or more turns. The number of turns of the inductor can be selected appropriately depending on the specifications, applications, etc. of the semiconductor module according to each embodiment.

[0212] As an example, the inductor 172 formed across multiple IC chips shown in Figures 23 to 26 is in contact with the semiconductor substrate 173 and includes a through electrode 131 that penetrates the semiconductor substrate 173, but an insulating film different from the semiconductor substrate 173 may be provided between the through electrode 131 and the semiconductor substrate 173.

[0213] Also, as an example, the inductor formed across multiple IC chips shown in Figures 23 to 26 is inductor 172, but the inductor formed across multiple IC chips shown in Figures 23 to 26 may be inductor 272, inductor 372, or inductor 672.

[0214] 24 to 26, the first surface 102n of the IC chip 110n is bonded to the second surface 104n+1 of the IC chip 110n+1. As an example, the inductor 172 is provided across two IC chips (IC chips 110n and 110n+1). The inductor 172 may also be provided across three or more IC chips 110.

[0215] 25 shows a cross section (structure) of the inductor 172 when viewed in a direction from the third surface 146 toward the fourth surface 148. When viewed in a direction from the third surface 146 toward the fourth surface 148, the inductor 172 shown in FIG. 25 is an example of a two-winding inductor provided across two IC chips (IC chips 110 n and 110 n+1). Furthermore, the inductor 172 is provided parallel to the third surface 146 and the fourth surface 148 and spaced apart from the third surface 146 and the fourth surface 148.

[0216] The inductor 172 shown in FIGS. 23 to 26 includes a terminal A, a terminal B, a wiring 183j, a via 184j, a wiring 156j, a via 155j, a wiring 154j, a via 153j, a wiring 152j, a via 151j, a through electrode 131j, a wiring 196j, a wiring 183nj, a via 184nj, a wiring 156nj, a via 155nj, a wiring 154nj, a via 153nj, a wiring 152nj, a via 153nk, a wiring 154nk, a via 155nk, a wiring 156nk, a via 184nk, a wiring 183nk, a wiring 196nk, a through electrode 131k, a via 151k, a wiring 152k, a via 153k, a wiring 196nk ... 54k, via 155k, wiring 156k, via 184k, wiring 183k, via 184m, wiring 156m, via 155m, wiring 154m, via 153m, wiring 152m, via 151m, through electrode 131m, wiring 196nm, wiring 183nm, via 184nm, wiring 156nm, via 155nm, wiring 154nm, via 155no, wiring 156no, via 184no, wiring 183no, wiring 196no, through electrode 131o, via 151o, wiring 152o, via 153o, wiring 154o, via 155o, wiring 156o, via 184o, and wiring 183o.

[0217] The IC chip 110n includes wiring 196j, wiring 183nj, via 184nj, wiring 156nj, via 155nj, wiring 154nj, via 153nj, wiring 152nj, via 153nk, wiring 154nk, via 155nk, wiring 156nk, via 184nk, wiring 183nk, wiring 196nk, wiring 196nm, wiring 183nm, via 184nm, wiring 156nm, via 155nm, wiring 154nm, via 155no, wiring 156no, via 184no, wiring 183no, wiring 196no, and a seal ring 160n. The function and structure of the seal ring 160n are similar to those of the seal ring 160. The function and structure of the seal ring 160n will be described as necessary.

[0218] The wiring 152nj is formed in the same layer as the wiring 152b of the IC chip 110n, and the vias 153nj and 153nk are formed in the same layer as the via 153b of the IC chip 110n. The wiring 154nj, wiring 154nk, and wiring 154nm are formed in the same layer as the wiring 154b of the IC chip 110n. The vias 155nj, via 155nk, via 155nm, and via 155no are formed in the same layer as the via 155b of the IC chip 110n. The wiring 156nj, wiring 156nk, wiring 156nm, and wiring 156no are formed in the same layer as the wiring 156b of the IC chip 110n. The wiring 183nj, wiring 183nk, wiring 183nm, and wiring 183no are formed in the same layer.

[0219] Vias 184nj, via 184nk, via 184nm and via 184no are formed in the third direction D3 between the layer on which the insulating layer 156a, wiring 156nj, wiring 156nk, wiring 156nm and wiring 156no of the IC chip 110n are formed and the layer on which wiring 183nj, wiring 183nk, wiring 183nm and wiring 183no are formed.

[0220] The wiring 196j, the wiring 196nk, the wiring 196nm, and the wiring 196no are formed on the wiring 183nj, the wiring 183nk, the wiring 183nm, and the wiring 183no.

[0221] The IC chip 110n+1 includes a terminal A, a terminal B, a wiring 183j, a via 184j, a wiring 156j, a via 155j, a wiring 154j, a via 153j, a wiring 152j, a via 151j, a through electrode 131j, a through electrode 131k, a via 151k, a wiring 152k, a via 153k, a wiring 154k, a via 155k, a wiring 156k, a via 184k, a wiring 183k, a via 184m, a wiring 156m, a via 155m, a wiring 154m, a via 153m, a wiring 152m, a via 151m, a through electrode 131m, a through electrode 131o, a via 151o, a wiring 152o, a via 153o, a wiring 154o, a via 155o, a wiring 156o, a via 184o, a wiring 183o, and a seal ring 160n+1. The function and structure of the seal ring 160n+1 are similar to those of the seal ring 160. The function and structure of the seal ring 160n+1 will be explained as needed.

[0222] Vias 151j, via 151k, via 151m, and via 151o are formed in the same layer as via 151b of IC chip 110n+1. Wiring 152j, wiring 152k, wiring 152m, and wiring 152o are formed in the same layer as wiring 152b of IC chip 110n+1. Vias 153j, via 153k, via 153m, and via 153o are formed in the same layer as via 153b of IC chip 110n+1. Wiring 154j, wiring 154k, wiring 154m, and wiring 154o are formed in the same layer as wiring 154b of IC chip 110n+1. Vias 155j, via 155k, via 155m, and via 155o are formed in the same layer as via 155b of IC chip 110n+1. The wiring 156j, the wiring 156k, the wiring 156m, and the wiring 156o are formed in the same layer as the wiring 156b of the IC chip 110n+1. The wiring 183j, the wiring 183k, and the wiring 183o are formed in the same layer. The vias 184j, the vias 184k, the vias 184m, and the vias 184o are formed in the same layer.

[0223] The through electrodes 131j, 131k, 131m, and 131o are formed to penetrate the transistor layer 130n+1 and are connected to the vias 151j, 151k, 151m, and 151o. Furthermore, when the IC chip 110n+1 is bonded to the IC chip 110n, the through electrodes 131j, 131k, 131m, and 131o are connected to the wiring 196j, 196nk, 196nm, and 196no of the IC chip 110n.

[0224] Here, the connection of the inductor 172 will be described.

[0225] The wiring 183j extends in the first direction D1, one end of the wiring 183j is electrically connected to the terminal B, and the other end of the wiring 183j is electrically connected to the via 184j. The wiring 183j is configured to overlap the seal rings 160n and 160n+1 and to straddle the seal rings 160n and 160n+1. The via 184j, the wiring 156j, the via 155j, the wiring 154j, the via 153j, the wiring 152j, the via 151j, the through electrode 131j, the wiring 196j, the wiring 183nj, the via 184nj, the wiring 156nj, the via 155nj, the wiring 154nj, and the via 153nj extend in the third direction D3 and are electrically connected. The wiring 154nj is electrically connected to one end of the wiring 152nj. The wiring 152nj extends in the second direction D2, and the other end of the wiring 152nj is electrically connected to the via 153nk.

[0226] The via 153nk, the wiring 154nk, the via 155nk, the wiring 156nk, the via 184nk, the wiring 183nk, the wiring 196nk, the through electrode 131k, the via 151k, the wiring 152k, the via 153k, the wiring 154k, the via 155k, the wiring 156k, and the via 184k extend in the third direction D3 and are electrically connected. The via 184k is electrically connected to one end of the wiring 183k. The wiring 183k extends in the second direction D2, and the other end of the wiring 183k is electrically connected to the via 184m. The via 184m, the wiring 156m, the via 155m, the wiring 154m, the via 153m, the wiring 152m, the via 151m, the through electrode 131m, the wiring 196nm, the wiring 183nm, the via 184nm, the wiring 156nm, and the via 155nm extend in the third direction D3 and are electrically connected. The via 155nm is electrically connected to one end of the wiring 154nm. The wiring 154nm extends in the second direction D2, and the other end of the wiring 154nm is electrically connected to the via 155no.

[0227] The via 155no, the wiring 156no, the via 184no, the wiring 183no, the wiring 196no, the through electrode 131o, the via 151o, the wiring 152o, the via 153o, the wiring 154o, and the via 155o extend in the third direction D3 and are electrically connected to each other. The via 155o is electrically connected to one end of the wiring 156o. The wiring 156o extends in the second direction D2 and then bends in the first direction D1 while continuing to extend in the first direction D1.

[0228] The other end of the wiring 156o extending in the first direction D1 is electrically connected to the via 184o. The via 184o extends in the third direction D3 and is electrically connected to one end of the wiring 183o. The wiring 183o extends in the first direction D1 and has the other end electrically connected to the terminal A. The wiring 183o is configured to overlap the seal ring 160 and straddle the seal ring 160.

[0229] The wiring 183g extends in the first direction D1, overlaps the seal ring 160, and is configured to straddle the seal ring 160. After straddling the seal ring 160, the wiring 183g bends in the second direction D2 and extends in the second direction D2. After extending in the second direction D2, the wiring 183g bends in the first direction D1 and extends in the first direction D1. After straddling the seal ring 160, the wiring 183g bends in the second direction D2 and extends in the first direction D1. The wiring 183g extends in the first direction D1, overlaps the seal ring 160, and is configured to straddle the seal ring 160. After straddling the seal ring 160, the wiring 183g bends in the second direction D2 and extends in the second direction D2. The other end of the wiring 183g extending in the second direction D2 is electrically connected to the terminal A.

[0230] As shown in FIG. 23, the wiring 183j and the wiring 183o overlapping the seal ring 160 are formed on the same plane and are formed parallel to each other along the first direction D1.

[0231] As shown in FIG. 25 , the wiring 183j, the via 184j, the wiring 156j, the via 155j, the wiring 154j, the via 153j, the wiring 152j, the via 151j, the through electrode 131j, the wiring 196j, the wiring 183nj, the via 184nj, the wiring 156nj, the via 155nj, the wiring 154nj, the via 153nj, the wiring 152nj, the via 153nk, the wiring 154nk, the via 155nk, the wiring 156nk, the via 184nk, the wiring 183nk, the wiring 196nk, the through electrode 131k, the via 151k, the wiring 152k, the via 153k, the wiring 154k, the via 155k, the wiring 156 The substantial coil portion of the two-turn inductor 172 is formed by via 184k, wiring 183k, via 184m, wiring 156m, via 155m, wiring 154m, via 153m, wiring 152m, via 151m, through electrode 131m, wiring 196nm, wiring 183nm, via 184nm, wiring 156nm, via 155nm, wiring 154nm, via 155no, wiring 156no, via 184no, wiring 183no, wiring 196no, through electrode 131o, via 151o, wiring 152o, via 153o, wiring 154o, via 155o and wiring 156o.

[0232] That is, the inductor 172 is composed of a wiring 183k that overlaps the seal rings 160n and 160n+1 and is provided in the same layer as the wiring 183j and wiring 183o that are provided in the same layer, a wiring 183k that does not overlap the seal ring 160, and a plurality of wirings that are provided across the two IC chips (110n and 110n+1) and are provided in the same layer as the wirings that constitute the seal rings 160n and 160n+1.

[0233] As shown in FIGS. 23 and 25, the substantial coil portion of the two-turn inductor 172 is not exposed on the third surface 146 .

[0234] The actual coil portion of inductor 172, which is provided across two IC chips on the third surface 146 side, is formed using the wiring that constitutes seal ring 160, so that wiring 183j and wiring 183o connected to the actual coil portion of inductor 172 overlap seal rings 160n and 160n+1 and can straddle seal rings 160n and 160n+1.

[0235] As a result, the two-winding inductor 172 configured as described above is insulated from the seal rings 160n and 160n+1 by the insulating layers 151a to 182 provided on each of the two IC chips 110n and 110n+1, and does not short-circuit with the seal rings 160n and 160n+1.

[0236] 23 to 26 show one inductor 172, the IC chips 110n and 110n+1 include multiple inductors 172. For example, the multiple inductors 172 are arranged side by side along the second direction D2.

[0237] <Fourteenth Embodiment> A seal ring 160 and an inductor 172f according to a fourteenth embodiment will be described with reference to FIGS. 27 to 29. FIG. 27 is a plan view showing the configuration of the seal ring 160 and the inductor 172f. FIG. 28 is an end view showing the end cross-sectional structure of the seal ring 160 and the inductor 172f taken along line E9-E10 in FIG. 27. FIG. 29 is an end view showing the end cross-sectional structure of the seal ring 160 and the inductor 172f shown in FIG. 27 when viewed through in the depth direction from the third surface 146 to the fourth surface 148. The function and structure of the seal ring 160 according to the fourteenth embodiment are similar to those of the seal ring 160 according to the twelfth embodiment. The function and structure of the seal ring 160 according to the fourteenth embodiment will be described as needed. Configurations that are the same as or similar to those in FIGS. 1 to 26 will be described as needed, and descriptions of configurations that are the same as or similar to those in FIGS. 1 to 26 may be omitted. The configurations of the seal ring 160 and the inductor 172f according to the fourteenth embodiment can be appropriately applied to the semiconductor modules according to the other embodiments as long as there is no mutual contradiction.

[0238] The inductor 172f according to the fourteenth embodiment is formed on a single IC chip 110. The rest of the configuration is similar to that of the inductor 172. Configurations similar to those of the inductor 172 will be described as necessary. Note that, as an example, the inductor formed on a single IC chip shown in FIGS. 27 to 29 is the inductor 172f, but the inductors 272, 372, and 672 of the semiconductor modules according to each embodiment include a configuration similar to that of the inductor 172f and include a configuration capable of one-to-one contactless inductor communication with the inductor 172f.

[0239] 27 , like the inductor 172, the inductor 172f includes terminal A, terminal B, first portion 172a, second portion 172b, third portion 172c, fourth portion 172e, and fifth portion 172d. The inductor 172f is an example of a single-turn inductor when viewed through the IC chip 110 from the second surface 104 side of the IC chip 110 along the third direction D3. The fifth portion 172d extends in the second direction D2, with one end of the fifth portion 172d electrically connected to terminal B and the other end of the fifth portion 172d electrically connected to one end of the fourth portion 172e. The fourth portion 172e extends in the third direction D3, with the other end of the fourth portion 172e electrically connected to one end of the first portion 172a. The first portion 172a extends in the second direction D2, and the other end of the first portion 172a is electrically connected to one end of the second portion 172b. The second portion 172b extends in the third direction D3, and the other end of the second portion 172b is electrically connected to one end of the third portion 172c. The third portion 172c extends in the second direction D2, and the other end of the third portion 172c is electrically connected to the terminal A.

[0240] As shown in FIGS. 27 to 29 , the inductor 172f is parallel to the first surface 102 and the second surface 104. The first portion 172a of the inductor 172f corresponds to the end of the inductor 172f on the third surface 146 side. The first portion 172a is not exposed on the third surface 146. The inductor 172f is formed so as to overlap the seal ring 160 and straddle the seal ring 160. That is, the length of the seal ring 160 extending along the first direction D1 is shorter than the length of the inductor 172f extending along the first direction D1. For example, the inductor 172f is formed using the wiring 183b. For example, when the inductor 172f included in the semiconductor modules 10D and 10E is formed so as to overlap the seal ring 160, the inductor 172f is formed closer to the first surface 902 than the seal ring 160.

[0241] 29 , the inductor 172f and the seal ring 160, when viewed see-through in the depth direction from the third surface 146 to the fourth surface 148, are stacked downward in the third direction D3, from the semiconductor substrate 173 side to the wiring layer 150 side. The vias 151b, 153b, and 155b that form the seal ring 160 and the wirings 152b, 154b, and 156b that form the seal ring 160 extend in the second direction D2. The lengths of the vias 151b, 153b, and 155b and the wirings 152b, 154b, and 156b in the second direction D2 are longer than the length of the first portion 172fa of the inductor 172f in the second direction D2.

[0242] 27 to 29 show one inductor 172f, the IC chip 110 includes a plurality of inductors 172f. For example, the plurality of inductors 172f are arranged side by side along the second direction D2.

[0243] The inductor 172f is covered by the insulating layer 182 and is not exposed on the side surface of the IC chip 110. The inductor 172f also straddles the seal ring 160 and is formed shorter than the seal ring 160 when viewed from the third surface 146. As a result, the insulating layer 182 and the seal ring 160 prevent the inductor 172f from corroding or deteriorating the wiring due to moisture absorption or the intrusion of impurities.

[0244] Furthermore, by suppressing corrosion and deterioration of the wiring due to moisture absorption and the intrusion of impurities, etc., insulation between adjacent inductors 172f is ensured and short circuits between adjacent inductors 172f are suppressed. As a result, for example, it is possible to shorten the distance between adjacent inductors 172f and the distance between the inductor 172f and the inductor 272. Therefore, the semiconductor module according to each embodiment including the inductor 172f can increase the number of inductors 172f in the IC chip 110 and can improve the communication quality between the inductor 172f and the inductor 272.

[0245] Furthermore, because the inductor 172f is not exposed on each surface of the IC chip 110, the semiconductor module according to each embodiment includes a configuration that can suppress damage to the inductor 172f due to ESD. As a result, for example, an ESD protection circuit for the inductor 172f is not required. Therefore, the power consumption caused by the ESD protection circuit of the semiconductor module according to each embodiment is suppressed, and the power consumption of the semiconductor module according to each embodiment is reduced. Furthermore, signal delays caused by the ESD protection circuit are suppressed, enabling high-speed operation of the semiconductor module according to each embodiment.

[0246] Therefore, the semiconductor module according to each embodiment including the inductor having the configuration shown in FIGS. 27 to 29 can maintain its reliability without impairing its long-term reliability.

[0247] Fifteenth Embodiment A seal ring 160 and an inductor 172g according to a fifteenth embodiment will be described with reference to FIGS. 30 to 33. FIG. 30 is a plan view showing an example of the configuration of the seal ring 160 and the inductor 172g. FIG. 31 is an end view showing the cross-sectional structure of the end of the inductor 172g taken along line E11-E12 in FIG. 30. FIG. 32 is an end view showing the cross-sectional structure of the end of the seal ring 160 and the inductor 172g taken along line E13-E14 in FIG. 30. FIG. 33 is an end view showing the cross-sectional structure of the end of the inductor 172g taken along line E15-E16 in FIG. 30. The function and structure of the seal ring 160 according to the fifteenth embodiment are similar to those of the seal ring 160 according to the twelfth embodiment. The function and structure of the seal ring 160 according to the fifteenth embodiment will be described as needed. Configurations that are the same as or similar to those in FIGS. 1 to 29 will be described as needed, and descriptions of configurations that are the same as or similar to those in FIGS. 1 to 29 may be omitted. The configurations of the seal ring 160 and the inductor 172g according to the fifteenth embodiment can be appropriately applied to the semiconductor modules according to the other embodiments as long as there is no mutual contradiction.

[0248] The inductor 172g according to the fifteenth embodiment is formed on a single IC chip 110, similar to the inductor 172f according to the fourteenth embodiment. The rest of the configuration is similar to that of the inductor 172. Configurations similar to those of the inductor 172 will be described as necessary. As an example, the inductor formed on a single IC chip shown in FIGS. 30 to 33 is the inductor 172g, but the inductors 272, 372, and 672 of the semiconductor modules according to each embodiment include a configuration similar to that of the inductor 172g and include a configuration capable of one-to-one contactless inductor communication with the inductor 172g. The IC chip 110 includes a plurality of inductors 172g arranged along the second direction D2.

[0249] Inductor 172g shown in Figures 30 to 33 includes terminal A, terminal B, wiring 152c, via 153c, wiring 154c, via 155c, wiring 156c, via 184a, wiring 183c, via 184b, wiring 156d, via 155d, wiring 154d, via 155e, wiring 156e, via 184c, wiring 183d, via 184d, wiring 156f, via 155f, wiring 154e, via 155g, wiring 156g, via 184e, wiring 183e, via 184f, wiring 156h, via 184g, wiring 183f, via 184h, wiring 156i, via 184i, and wiring 183g.

[0250] The inductor 172g is an example of a three-winding inductor when viewed through the IC chip 110 from the second surface 104 side of the IC chip 110 along the third direction D3. The inductor 172g is parallel to the first surface 102 and the second surface 104 and perpendicular to the third surface 146 and the fourth surface 148.

[0251] The wiring 152c is formed in the same layer as the wiring 152b, and the via 153c is formed in the same layer as the via 153b. The wiring 154c, the wiring 154d, and the wiring 154e are formed in the same layer as the wiring 154b. The vias 155c, the vias 155d, the vias 155e, the vias 155f, and the vias 155g are formed in the same layer as the via 155b. The wiring 156c, the wiring 156d, the wiring 156e, the wiring 156f, the wiring 156g, the wiring 156h, and the wiring 156i are formed in the same layer as the wiring 156b. The wiring 183c, the wiring 183d, the wiring 183e, the wiring 183f, and the wiring 183g are formed in the same layer as the wiring 183b.

[0252] Vias 184a, via 184b, via 184c, via 184d, via 184e, via 184f, via 184g, via 184h and via 184i are formed in the third direction D3 between the layer on which insulating layer 156a and wirings 156b to 156i are formed and the layer on which wirings 183c, 183d, 183e, 183f and 183g are formed.

[0253] The wiring 152c extends in the second direction D2, one end of the wiring 152c is electrically connected to the terminal F, and the other end of the wiring 152c is electrically connected to the via 153c. The via 153c, the wiring 154c, the wiring 154c, the via 155c, the wiring 156c, and the via 184a extend in the third direction D3 and are electrically connected to each other. The via 184a is electrically connected to one end of the wiring 183c. The wiring 183c extends in the first direction D1, and the other end of the wiring 183c is electrically connected to the via 184b. The wiring 183c is configured to overlap the seal ring 160 and straddle the seal ring 160.

[0254] The via 184b, the wiring 156d, and the via 155d extend in the third direction D3 and are electrically connected to each other. The via 155d is electrically connected to one end of the wiring 154d. The wiring 154d extends in the second direction D2, and the other end of the wiring 154d is electrically connected to the via 155e. The via 155e, the wiring 156e, and the via 184c extend in the third direction D3 and are electrically connected to each other. The via 184c is electrically connected to one end of the wiring 183d. The wiring 183d extends in the first direction D1, and the other end of the wiring 183d is electrically connected to the via 184d. The wiring 183d is configured to overlap the seal ring 160 and straddle the seal ring 160.

[0255] The via 184d, the wiring 156f, and the via 155f extend in the third direction D3 and are electrically connected to each other. The via 155f is electrically connected to one end of the wiring 154e. The wiring 154e extends in the second direction D2, and the other end of the wiring 154e is electrically connected to the via 155g. The via 155g, the wiring 156g, and the via 184e extend in the third direction D3 and are electrically connected to each other. The via 184e is electrically connected to one end of the wiring 183e. The wiring 183e extends in the first direction D1, and the other end of the wiring 183e is electrically connected to the via 184f. The wiring 183e is configured to overlap the seal ring 160 and straddle the seal ring 160.

[0256] The via 184f extends in the third direction D3 and is electrically connected to one end of the wiring 156h. The wiring 156h extends in the second direction D2 and the other end of the wiring 156h is electrically connected to the via 184g. The via 184g extends in the third direction D3 and is electrically connected to one end of the wiring 183f. The wiring 183f extends in the first direction D1 and the other end of the wiring 183f is electrically connected to the via 184h. The wiring 183f is configured to overlap the seal ring 160 and straddle the seal ring 160.

[0257] The via 184h extends in the third direction D3 and is electrically connected to one end of the interconnect 156i. The interconnect 156i extends in the second direction D2 and has the other end electrically connected to the via 184i. The via 184i extends in the third direction D3 and is electrically connected to one end of the interconnect 183g.

[0258] The wiring 183g extends in the first direction D1, overlaps the seal ring 160, and is configured to straddle the seal ring 160. After straddling the seal ring 160, the wiring 183g bends in the second direction D2 and extends in the second direction D2. After extending in the second direction D2, the wiring 183g bends in the first direction D1 and extends in the first direction D1. After straddling the seal ring 160, the wiring 183g bends in the second direction D2 and extends in the first direction D1. The wiring 183g extends in the first direction D1, overlaps the seal ring 160, and is configured to straddle the seal ring 160. After straddling the seal ring 160, the wiring 183g bends in the second direction D2 and extends in the second direction D2. The other end of the wiring 183g extending in the second direction D2 is electrically connected to the terminal A.

[0259] As shown in FIG. 30, wiring 183c, wiring 183d, wiring 183e, wiring 183f and wiring 183g that overlap with seal ring 160 are formed on the same plane, and wiring 183c, wiring 183e, wiring 183d, wiring 183e, wiring 183f and portions of wiring 183g are formed parallel to each other along first direction D1.

[0260] 30 or 31 , the wiring 152c, the wiring 154e, the wiring 156i, and a portion of the wiring 183g are stacked along the third direction D3, overlap each other, and are formed in parallel along the second direction D2. The wiring 152c is formed in the same layer as the wiring 152b that constitutes the seal ring 160, the wiring 154e is formed in the same layer as the wiring 154b that constitutes the seal ring 160, and the wiring 156i is formed in the same layer as the wiring 156b that forms the seal ring 160.

[0261] 30 or 33 , the wiring 154d, the wiring 156h, and a portion of the wiring 183g are stacked and overlap each other along the third direction D3, and are formed parallel to each other along the second direction D2. The wiring 154d is formed in the same layer as the wiring 154b that constitutes the seal ring 160, and the wiring 156h is formed in the same layer as the wiring 156b that constitutes the seal ring 160.

[0262] As shown in Fig. 30, the wiring 183c and the wiring 183e face the wiring 183d and the wiring 183f. As shown in Fig. 30, 31 or 33, the wiring 154d faces the wiring 154e, and the wiring 156h faces the wiring 156i.

[0263] That is, inductor 172g is composed of wirings 183c and 183e and wirings 183d and 183f that overlap seal ring 160 and are formed in the same layer and facing each other, wirings 154d and 154e that are formed in the same layer as wiring 154b that constitutes seal ring 160 and facing each other, and wirings 156h and 156i that are formed in the same layer as wiring 156b that constitutes seal ring 160.

[0264] 30 and 33 , the wiring 183g, the wiring 156h, and the wiring 154d overlap each other and correspond to the end of the inductor 172g on the third surface 146 side. The wiring 183g, the wiring 156h, and the wiring 154d are not exposed on the third surface 146. The wiring 183g, the wiring 156i, the wiring 154e, and the wiring 152c overlap each other and correspond to the end of the inductor 172g on the side opposite to the third surface 146 side.

[0265] By forming the end of inductor 172g on the third surface 146 side and the end of inductor 172g opposite to the third surface 146 side as shown in Figures 30 and 33, wiring 183c to 183g of inductor 172g can overlap seal ring 160 and straddle seal ring 160, as shown in the cross section of Figure 32.

[0266] As a result, the three-winding inductor 172 g according to the fifteenth embodiment is insulated from the seal ring 160 by the insulating layers 151 a to 182 and does not short-circuit with the seal ring 160 .

[0267] Therefore, the semiconductor module according to each embodiment including the inductor 172g has the same effects as the semiconductor module according to each embodiment including the inductor 172f.

[0268] Sixteenth Embodiment A seal ring 160 and power wiring 165b according to a sixteenth embodiment will be described with reference to FIG. 34 . FIG. 34 is a plan view showing an example of the configuration of the seal ring 160 and power wiring 165b, and an end view showing the cross-sectional structure of the end of the seal ring 160 and power wiring 165b taken along line F1-F2 in the plan view. The function and structure of the seal ring 160 according to the sixteenth embodiment are similar to those of the seal ring 160 according to the twelfth embodiment. The function and structure of the seal ring 160 according to the sixteenth embodiment will be described as needed. Configurations that are the same as or similar to those in FIGS. 1 to 33 will be described as needed, and descriptions of configurations that are the same as or similar to those in FIGS. 1 to 33 may be omitted. The configuration of the seal ring 160 and power wiring 165b according to the sixteenth embodiment can be applied to the semiconductor modules according to each embodiment as appropriate, provided there are no mutual contradictions.

[0269] 34, power supply wiring 165b is formed using wiring 183. A portion of power supply wiring 165b is disposed outside outer periphery 192. As described in "1-1. Overview of semiconductor module 10," wiring layer 150 includes a multilayer wiring structure.

[0270] An end 165c of the power supply wiring 165b is exposed on the insulating layer 182 (third surface 146). The side surface power supply wiring 162 covers and electrically connects to the end 165c. The side surface power supply wiring 162 also contacts the third surface 146.

[0271] The insulating film 52 covers the side-surface power supply wiring 162 and is provided on the third surface 146 not in contact with the side-surface power supply wiring 162. The insulating film 52 is formed using the same material as the insulating film 190.

[0272] For example, the manufacturing method of the power supply wiring 165b according to the sixteenth embodiment includes etching the semiconductor substrate 173 and filling the gaps between the etched semiconductor substrate 173 and each surface (e.g., the third surface 146, the second surface 144, the first surface 142, and the fourth surface 148) of the stacked memory chip 100 with an insulating film 190. As a result, the semiconductor substrate 173 is covered with the insulating film 190, which suppresses contamination by metal in the stacked memory chip 100 and corrosion and deterioration of each element in the stacked memory chip 100 due to moisture absorption and intrusion of impurities, etc.

[0273] Furthermore, for example, because the semiconductor substrate 173 is covered with the insulating film 190, there is no contamination by metal in the stacked memory chips 100. As a result, short circuits between adjacent wirings in the stacked memory chips 100 and between the IC chips 110 are suppressed. Therefore, the semiconductor module according to each embodiment including the seal ring 160 and power supply wiring 165b according to the sixteenth embodiment can ensure insulation between adjacent wirings and between memory chips.

[0274] Furthermore, for example, in the semiconductor module according to each embodiment including the seal ring 160 according to the 16th embodiment and the power supply wiring 165b, the seal ring 160 can suppress corrosion and deterioration of the wiring due to moisture absorption and the intrusion of impurities, etc.

[0275] Therefore, the semiconductor module according to each embodiment including the seal ring 160 according to the sixteenth embodiment and the power supply wiring 165b can maintain its reliability without impairing its long-term reliability.

[0276] Seventeenth Embodiment

[0277] An example of a manufacturing method for the three-winding inductor 172j included in the semiconductor module 10K according to the seventeenth embodiment will be described with reference to FIGS. 35 and 36 . FIG. 35 is a plan view illustrating a manufacturing method for the inductor 172j, and an end view illustrating the cross-sectional structure of the end of the inductor 172j taken along line F3-F4 in the plan view. FIG. 36 is a plan view illustrating an example of a manufacturing method for the inductor 172j shown in FIG. 35, and an end view illustrating the cross-sectional structure of the end of the inductor taken along line F5-F6. Configurations identical or similar to those in FIGS. 1 to 34 will be described as necessary, and descriptions of configurations identical or similar to those in FIGS. 1 to 34 may be omitted. The configurations of the seal ring 160 and power supply wiring 165b according to the seventeenth embodiment can be applied to the semiconductor modules according to the other embodiments as long as they are not mutually inconsistent.

[0278] The inductor 172j according to the seventeenth embodiment, like the inductor 172 according to the thirteenth embodiment, is an inductor having a plurality of windings formed across a plurality of IC chips 110 in an end view. Other configurations are similar to those of the inductor 172. Configurations similar to those of the inductor 172 will be described as necessary. Note that, as an example, the inductor according to the seventeenth embodiment is the inductor 172j, but the inductors 272, 372, and 672 of the semiconductor modules according to the respective embodiments include a configuration similar to that of the inductor 172j and include a configuration capable of one-to-one contactless inductor communication with the inductor 172j. Note that the IC chip 110 includes a plurality of inductors 172j arranged along the second direction D2.

[0279] As shown in Figures 35 and 36, the stacked memory chip 100A includes an inductor 172j having multiple windings formed across multiple IC chips 110 (IC chip 110n, IC chip 110n+1, IC chip 110n+2, and IC chip 110n+3).

[0280] Specifically, the stacked memory chip 100A includes a three-winding inductor 172j formed on and in parallel with the third surface 146 using the side surface wiring 361d.

[0281] Although not shown in the drawings, a plurality of inductors 172j are provided along the second direction D2, as in each of the other embodiments. Furthermore, as one example, a manufacturing method for the inductor 172j according to the seventeenth embodiment includes forming two wirings 383 corresponding to the two terminals of the inductor 172j on the IC chip 110n. As another example, a manufacturing method for the inductor 172j according to the seventeenth embodiment may include forming the two wirings 383 corresponding to the two terminals of the inductor 172j on any one of the IC chips 110n+1, 110n+2, and 110n+3, or may include forming the wiring 383 corresponding to one terminal of the two wirings 383 corresponding to the two terminals of the inductor 172j on any one of the IC chips 110n+1, 110n+2, and 110n+3, and forming the wiring 383 corresponding to the remaining terminal on an IC chip different from the IC chip on which the wiring 383 corresponding to the one terminal is formed.

[0282] The manufacturing method of the inductor 172j according to the seventeenth embodiment includes forming wiring connected to the two terminals of the three-winding inductor 172j using two wirings 383 of the IC chip 110n, forming a side wiring 361d corresponding to a three-winding coil after the two wirings 383 corresponding to the two terminals of the inductor 172j are formed, and forming an insulating film 52 on the third surface 206 that covers the side wiring 361d and is not in contact with the side wiring 361d after the side wiring 361d is formed.

[0283] 35, the wiring connected to the two terminals of the three-winding inductor 172j is formed by two wirings 383 of the IC chip 110n. Therefore, the cross section of each of the two wirings 383 is exposed on the third surface 146.

[0284] 36 , after the two wirings 383 of the inductor 172j are formed, a side wiring 361d corresponding to the coil of the three-winding inductor 172j is formed on the third surface 146. That is, the side wiring 361d is formed on the third surface 146 across the multiple IC chips 110n, 110n+1, 110n+2, and 110n+3.

[0285] For example, the side wiring 361d is formed on the third surface 146 so as to overlap each of the two wirings 383 exposed on the third surface 146 corresponding to the side surfaces of the IC chip 110n, and the side wiring 361d is electrically connected to each of the cross sections of the two wirings 383.

[0286] Furthermore, for example, the side wiring 361d includes wiring with first to third turns wound from the inside to the outside. The first turn of the wiring is formed across three IC chips, IC chip 110n to IC chip 110n+2, and the second and third turns of the wiring are formed across four IC chips, IC chip 110n to IC chip 110n+3.

[0287] Similar to the inductor 172 , the side wiring 361 d around the cross section of the wiring 383 of the three-winding inductor 172 j has a wider wiring width so as to surround the cross section of the wiring 383 .

[0288] As described above, the inductor 172j is formed using the wiring 383 and the side wiring 361d that is different from the wiring 383. The side wiring 361d is formed on the third surface 146 and is covered with the insulating film 52. Therefore, the inductor 172j according to the seventeenth embodiment has the same effects as the inductor 172 according to the thirteenth embodiment.

[0289] A seal ring (e.g., seal ring 160) may be formed along the third direction D3 using wiring in a layer below the layer in which the two wirings 383 are formed. For example, the wiring in the layer below the layer in which the two wirings 383 are formed may be wiring in the wiring layer 150 of IC chip 110n, or may be wiring in IC chips 110n+1 to 110n+3.

[0290] 18th Embodiment An example of an inductor communication method for a semiconductor module 10L according to an 18th embodiment will be described with reference to FIGS. 37 to 41. FIG. 37 is a perspective view showing a plurality of inductors 172 included in the stacked memory chip 100 of the semiconductor module 10L and a plurality of inductors 272 included in the first semiconductor chip 200. FIG. 38 is a diagram showing the individual identification numbers (IDs) of each chip included in the semiconductor module 10L. FIGS. 39 and 40 are a flowchart showing an example of an inductor communication method for the semiconductor module 10L. FIG. 41 is a block diagram showing the configuration of the first semiconductor chip 200. Configurations that are the same as or similar to those in FIGS. 1 to 36 will be described as necessary, and descriptions of configurations that are the same as or similar to those in FIGS. 1 to 36 may be omitted. The inductor communication method for the semiconductor module 10L according to the 18th embodiment can be applied to the semiconductor modules according to each embodiment as long as there is no mutual contradiction.

[0291] <18-1. Overview of Semiconductor Module 10L> First, an overview of the semiconductor module 10L will be described with reference to FIGS. 37 and 38 . For example, the semiconductor module 10L differs from the semiconductor module 10 in the following configurations (1) to (3): (1) The stacked memory chip 100 includes a plurality of inductors 172 (e.g., inductors 172h, 172i, 172j, 172k, 172m, and 172n) that are parallel to the third surface 146, spaced apart from the third surface 146, and arranged in a matrix in the second direction D2 and the third direction D3. (2) The first semiconductor chip 200 includes a plurality of inductors 272 (e.g., inductors 272h, 272i, 272j, 272k, 272m, and 272n) that are parallel to the third surface 206, spaced apart from the third surface 206, and arranged in a matrix in the second direction D2 and the third direction D3. (3) Each of the inductors 172h, 172i, 172j, 172k, 172m, and 172n is capable of one-to-one non-contact inductive communication with the opposing inductors 272h, 272i, 272j, 272k, 272m, and 272n. For example, the inductor 172m is opposed to the inductor 272m, and the inductor 172m is capable of contactless inductive communication with the inductor 272m.

[0292] The semiconductor module 10L has the same configuration as the semiconductor module 10 except for the configurations shown in (1) to (3). Therefore, only the differences from the semiconductor module 10 will be described here. As with the semiconductor module 10, the number of IC chips 110 stacked, the bonding, and the mounting structure can be changed as appropriate depending on the specifications and applications of the semiconductor module 10L. The configuration of the semiconductor module 10L can also be applied to semiconductor modules other than the semiconductor module 10 as appropriate, as long as there are no mutual contradictions. For example, when the semiconductor module 10L is applied to the semiconductor modules 10D and 10E, the first semiconductor chip 200 is replaced with the third semiconductor chip 900, the inductor 272 is replaced with the inductor 372, and the inductor communication method of the semiconductor module 10L becomes an inductor communication method suited to the specifications and applications of the semiconductor modules 10D and 10E.

[0293] 38 , a semiconductor module 10L includes a configuration similar to that of the semiconductor module 10. Specifically, the semiconductor module 10L includes stacked memory chips 100A and 100B, a first semiconductor chip 200, and a second semiconductor chip 600A. The first semiconductor chip 200 includes a CPU 220A, a CPU 220B, and a CPU 220C. The second semiconductor chip 600A includes a GPU 620A and a GPU 620B. Each of the stacked memory chips 100A and 100B, the first semiconductor chip 200, and the second semiconductor chip 600A includes four IC chips 110 (IC chip 110n, IC chip 110n+1, IC chip 110n+2, and IC chip 110n+3).

[0294] As an example, each chip is associated with a chip ID as shown in Fig. 38. For example, the chip ID of the stacked memory chip 100A is 0100, and the chip ID of the IC chip 110n is 01. The chip ID of the IC chip 110n of the stacked memory chip 100A is 0100-01, which is a combination of the chip ID of the stacked memory chip 100A and the chip ID of the IC chip 110n. Therefore, each chip in the semiconductor module 10L is an individually identifiable chip.

[0295] 39 and 40, an example of an inductor communication method of the semiconductor module 10L will be described. The example of the inductor communication method of the semiconductor module 10L shows inductor communication between the first semiconductor chip 200 and the stacked memory chip 100A. Inductor communication between other chips capable of inductor communication is similar to the example of the inductor communication method of the semiconductor module 10L described here, and detailed description thereof will be omitted.

[0296] 39, when inductor communication of the semiconductor module 10L is started, the first semiconductor chip 200 executes a first command to select the plurality of inductors 172 and the plurality of inductors 272 included in each IC chip (step 11 (S11) in FIG. 39). The first command may be a command to select all the inductors included in each IC chip, or may be a command to select some of the inductors included in each IC chip.

[0297] Next, after the first command, the first semiconductor chip 200 executes a second command to perform inductor communication with the selected inductors 172 and the selected inductors 272 (step 13 (S13) in FIG. 39).

[0298] For example, the CPU 220A of the first semiconductor chip 200 transmits a first instruction and a second instruction to the CPUs 220B and 220C of the first semiconductor chip 200 and the stacked memory chip 100A so as to execute the first instruction and the second instruction. Specifically, the CPU 220A transmits a second instruction to the CPUs 220B and 220C and the stacked memory chip 100A, which causes communication between each of the inductors 272 of the IC chips 110n to 110n+3 of the CPUs 220B and 220C and each of the inductors 172 of the IC chips 110n to 110n+3 of the stacked memory chip 100A.

[0299] For example, if the inductors selected in S11 are all the inductors included in each IC chip, inductor communication is performed for all combinations of each of all inductors 172 and each of all inductors 272. Referring to Fig. 37, inductor 172h is in inductor communication with each of inductors 272h, 272i, 272j, 272k, 272m, and 272n. Similar to inductor 172h, inductors 172i, 172j, 172k, 172m, and 172n are in inductor communication with each of inductors 272h, 272i, 272j, 272k, 272m, and 272n.

[0300] Next, the first semiconductor chip 200 (CPU 220A) executes the third instruction executed in S13 to acquire the result of the inductor communication between the selected plurality of inductors 172 and the selected plurality of inductors 272 (step 15 (S15) in FIG. 39 ). For example, the result of the inductor communication may be data based on the strength of the communication (communication strength data), and more specifically, may be data on the induced current of the inductor 172 or the inductor 272, or may be data on the voltage based on the induced current of the inductor 172 or the inductor 272.

[0301] The semiconductor module 10L can align the inductors with each other and select a combination of inductors that are well-aligned by S15. For example, good alignment may indicate that the induced current is at a maximum, or that the voltage based on the induced current is at a maximum. For example, the sequence of selecting a combination of inductors that are well-aligned by S11 to S15 may be referred to as a training sequence.

[0302] For example, the CPU 220A transmits a third instruction to the CPUs 220B and 220C and the stacked memory chip 100A to execute the third instruction. Specifically, the CPU 220A transmits a third instruction to the CPUs 220B and 220C and the stacked memory chip 100A to transmit data on the induced current of each inductor when communication occurs between each inductor 272 of the IC chips 110n to 110n+3 of the CPUs 220B and 220C and each inductor 172 of the IC chips 110n to 110n+3 of the stacked memory chip 100A. For example, the CPU 220A acquires data on the induced current of each inductor.

[0303] Next, the first semiconductor chip 200 (CPU 220A) executes a fourth command using data based on the communication strength obtained in S15 to send 0100, which is the ID of the stacked memory chip 100A that includes one of the multiple inductors 172, along with 0302, which is the ID of the CPU 220B of the first semiconductor chip 200 that includes one inductor 272 corresponding to that one inductor 172, to the stacked memory chip 100A and the first semiconductor chip 200 (step 17 (S17) in Figure 39).

[0304] For example, in S17, the CPU 220A selects the combination of inductors with the largest induced current data from the data based on the communication strength acquired in S15. For example, consider a case where the combination of inductors with the largest induced current data is the combination of the inductor 172h of the IC chip 110n in the stacked memory chip 100A and the inductor 272h of the IC chip 110n of the CPU 220B in the first semiconductor chip 200. In this case, the CPU 220A transmits, to the CPUs 220B and 220C, and the stacked memory chip 100A, the ID 0100-01 of the IC chip 110n in the stacked memory chip 100A that includes one inductor 172h out of the multiple inductors 172, along with the ID 0302-01 of the IC chip 110n of the CPU 220B in the first semiconductor chip 200 that includes one inductor 272h corresponding to that one inductor 172h.

[0305] Next, for example, the first semiconductor chip 200 (CPU 220A) sends a fifth command to the stacked memory chip 100A and the first semiconductor chip 200 to perform inductor communication using the combination selected in S17 (the inductor 272h of the IC chip 110n (ID is 0302-01) of the first semiconductor chip 200 and the inductor 172h of the IC chip 110n (ID is 0100-01) of the stacked memory chip 100A) (step 19 (S19) in Figure 39).

[0306] The stacked memory chip 100A and the first semiconductor chip 200 perform inductor communication between the inductor 272h of the IC chip 110n of the first semiconductor chip 200 and the inductor 172h of the IC chip 110n of the stacked memory chip 100A.

[0307] In this manner, the semiconductor module 10L performs inductor communication between the stacked memory chip 100A and the first semiconductor chip 200.

[0308] <18-3. Example of Inductor Communication Method of Semiconductor Module 10L> Next, another example of the inductor communication method of the semiconductor module 10L will be described with reference to Fig. 40. This example of the inductor communication method of the semiconductor module 10L shows inductor communication between the first semiconductor chip 200 and the stacked memory chip 100A. Inductor communication between other chips capable of inductor communication is similar to the example of the inductor communication method of the semiconductor module 10L described here, and detailed description thereof will be omitted.

[0309] 40, when inductor communication of the semiconductor module 10L is started, the first semiconductor chip 200 executes a first command to select the multiple inductors 172 and the multiple inductors 272 included in each IC chip (step 21 (S21) in FIG. 40). S21 is similar to S11, and therefore its description will be omitted here.

[0310] Next, after the first command, the first semiconductor chip 200 executes a sixth command to communicate at multiple communication speeds with the selected multiple inductors 172 and multiple inductors 272 (step 23 (S23) in Figure 40).

[0311] For example, the CPU 220A of the first semiconductor chip 200 transmits the first instruction and the sixth instruction to the CPUs 220B and 220C of the first semiconductor chip 200 and the stacked memory chip 100A so as to execute the first instruction and the sixth instruction. Specifically, the CPU 220A transmits the sixth instruction to the CPUs 220B and 220C and the stacked memory chip 100A, which transmits the sixth instruction to perform communication at a plurality of communication speeds between the inductors 272 of the IC chips 110n to 110n+3 of the CPUs 220B and 220C and the stacked memory chip 100A.

[0312] For example, the multiple communication speeds may be the communication speed specified in the specifications of the semiconductor module 10L and two or more communication speeds different from the specified communication speed. For example, the multiple communication speeds may be the communication speed specified in the specifications of the semiconductor module 10L and a communication speed that is ±10% of the specified communication speed.

[0313] Next, the first semiconductor chip 200 (CPU 220A) executes a seventh instruction to acquire the results of the inductor communication of the selected plurality of inductors 172 and the selected plurality of inductors 272 executed at the plurality of communication speeds in S23 (step 25 (S25) in FIG. 40 ). For example, the results of the inductor communication may be data based on the strength of the communication (communication strength data), as in S15, and more specifically, may be data on the induced current of the inductor 172 or the inductor 272, or may be data on the voltage based on the induced current of the inductor 172 or the inductor 272.

[0314] In step S25, the semiconductor module 10L aligns the inductors and selects a combination of inductors that are well-aligned, and also analyzes data based on the strength of communications performed at multiple communication speeds to obtain the minimum communication speed. For example, good alignment may indicate that the induced current is at its maximum, or that the voltage based on the induced current is at its maximum. For example, the sequence of steps S21 to S25 for selecting a combination of inductors that are well-aligned may be referred to as a training sequence.

[0315] For example, the CPU 220A transmits a seventh command to the CPUs 220B and 220C and the stacked memory chip 100A to execute the seventh command. Specifically, the CPU 220A transmits a seventh command to the CPUs 220B and 220C and the stacked memory chip 100A to transmit data on the induced currents of the inductors when communication is performed at different communication speeds using the inductors 272 of the IC chips 110n to 110n+3 of the CPUs 220B and 220C and the inductors 172 of the IC chips 110n to 110n+3 of the stacked memory chip 100A. For example, the CPU 220A acquires data on the induced currents of the inductors corresponding to each of a plurality of communication speeds. The CPU 220A also analyzes the acquired data and calculates the minimum communication speed.

[0316] Next, the first semiconductor chip 200 (CPU 220A) executes a fourth command to transmit the ID of the IC chip of the stacked memory chip and the ID of the IC chip of the first semiconductor chip, which are capable of inductive communication based on the communication strength data acquired in S25, to the stacked memory chip and the first semiconductor chip (step 27 (S27) in Figure 40).

[0317] For example, in S27, the CPU 220A selects a combination of inductors that allows inductor communication at a communication speed higher than the minimum communication speed calculated in S25. For example, consider a case where the combination of inductors that allows inductor communication at a communication speed higher than the minimum communication speed is a combination of inductor 172j of IC chip 110n in stacked memory chip 100A and inductor 272j of IC chip 110n of CPU 220B in the first semiconductor chip 200. In this case, the CPU 220A transmits to CPU 220B, CPU 220C, and stacked memory chip 100A the ID 0100-01 of IC chip 110n in stacked memory chip 100A that includes inductor 172j, and the ID 0302-01 of IC chip 110n of CPU 220B in the first semiconductor chip 200 that includes inductor 272j that corresponds to that one inductor 172j.

[0318] Next, for example, the first semiconductor chip 200 (CPU 220A) sends an eighth command to the stacked memory chip 100A and the first semiconductor chip 200 to perform inductor communication at a communication speed higher than the minimum communication speed using the combination selected in S27 (the inductor 272j of the IC chip 110n (ID is 0302-01) of the first semiconductor chip 200 and the inductor 172j of the IC chip 110n (ID is 0100-01) of the stacked memory chip 100A) (step 29 (S29) in Figure 40).

[0319] The stacked memory chip 100A and the first semiconductor chip 200 perform inductor communication at a communication speed higher than the minimum communication speed between the inductor 272j of the IC chip 110n of the first semiconductor chip 200 and the inductor 172j of the IC chip 110n of the stacked memory chip 100A.

[0320] In this way, the semiconductor module 10L performs inductor communication with the stacked memory chip 100A and the first semiconductor chip 200 at a communication speed higher than the minimum communication speed.

[0321] <18-4. First Modification of the Inductor Communication Method of the Semiconductor Module 10L> Next, a first modification of the inductor communication method of the semiconductor module 10L will be described. The semiconductor module 10L can execute the first modification of the inductor communication method of the semiconductor module 10L in combination with the inductor communication method described in "18-2. Example of the Inductor Communication Method of the Semiconductor Module 10L" or the inductor communication method described in "18-3. Example of the Inductor Communication Method of the Semiconductor Module 10L."

[0322] The first modified example of the inductor communication method of the semiconductor module 10L may include performing a process to confirm that the signal containing data has been correctly received by the stacked memory chip 100 after the first semiconductor chip 200 transmits the signal containing data to the stacked memory chip 100. For example, the process to confirm that the signal containing data has been correctly received is called a verify process or the like in the technical field of memory devices.

[0323] For example, if the semiconductor module 10L simultaneously transmits signals containing data from two adjacent inductors 172 of the first semiconductor chip 200 to two inductors 272 (e.g., stacked memory chip 100) corresponding to the two adjacent inductors 172, a collision may occur.

[0324] To avoid such collisions, the semiconductor module 10L (e.g., the first semiconductor chip 200) may periodically execute a process of checking whether a communication error has occurred. The process of checking whether a communication error has occurred may be a verify process. Furthermore, if the semiconductor module 10L (e.g., the first semiconductor chip 200) checks whether a communication error has occurred, it may execute a process of retransmitting a signal including data to the stacked memory chip 100.

[0325] As a result, the semiconductor module 10L can suppress collisions, communication errors, and the like.

[0326] <18-5. Configuration of First Semiconductor Chip 200> First, the configuration of the first semiconductor chip 200 will be described with reference to Fig. 41. Fig. 41 is a block diagram showing the configuration of CPU 220A of first semiconductor chip 200. Note that CPU 220B and CPU 220C include the same configuration as CPU 220A, and therefore descriptions thereof will be omitted here.

[0327] The CPU 220A includes a register 221 and a table 223. The register 221 is a storage circuit that can set quality information (e.g., level 0, level 1, ..., level 7) of the stacked memory chip 100 according to the type of data (image data, character data, etc.) and frequency (communication speed) transmitted and received by inductor communication. The table 223 is a storage circuit that associates the quality information (register setting value) with the ID of the IC chip 110 in the stacked memory chip 100.

[0328] For example, the CPU 220A transfers data according to the set level to the IC chip 110 in the stacked memory chip 100 that corresponds to the set level.

[0329] For example, the quality information may be assigned, in the order of level 0, level 1, ..., level 7, to indicate information with increasing confidentiality, information with a large amount of data (e.g., video data, image data, etc.), or data with a high frequency (high communication speed).

[0330] Also, as an example, table 223 is a table in which IDs 0100-01, 0100-02, ..., 0200-04 are assigned to register setting values ​​in the order of level 0, level 1, ..., level 7. Each ID corresponds to a chip shown in FIG. 38. For example, level 2 is assigned to 0100-03 (IC chip 110n+2 of stacked memory chip 100A).

[0331] For example, highly confidential data and data with a lot of information such as video are sent to high-level IC chips, while simple information such as text data is sent to low-level IC chips, and data with high frequencies (high communication speeds) are sent to high-level IC chips.

[0332] Furthermore, for example, if the register 221 is a register for setting the communication speed, the communication speed is set in the register starting from the highest layer (e.g., level 7) in descending order. For example, the CPU 220A of the first semiconductor chip 200 can vary the communication speed by reading the communication speed corresponding to each level from the register 221, and transmit data to the IC chip 110 corresponding to the communication speed of each level. <Nineteenth Embodiment> The configuration of a semiconductor module 10M according to a nineteenth embodiment will be described with reference to FIG. 42. FIG. 42 is a block diagram showing the configuration of the semiconductor module 10M. Configurations that are the same as or similar to those in FIGS. 1 to 41 will be described as necessary, and descriptions of configurations that are the same as or similar to those in FIGS. 1 to 41 may be omitted. The configuration of the semiconductor module 10M according to the nineteenth embodiment can be applied to the semiconductor modules according to each embodiment as long as there is no mutual contradiction.

[0333] The semiconductor module 10M includes stacked memory chips 100 and a first semiconductor chip 200. The stacked memory chips 100 include one TCI-IO 112 and a memory module 111 electrically connected to the TCI-IO 112. The first semiconductor chip 200 includes multiple TCI-IOs 212 and a CPU 220 electrically connected to the multiple TCI-IOs 212. The configuration of each chip is similar to the configuration described in "1-1. Overview of Semiconductor Module 10," and therefore description thereof will be omitted here.

[0334] For example, a general semiconductor module does not include the configuration of the semiconductor module 10M or the semiconductor module according to each embodiment. In the circuit corresponding to the memory chip and the circuit corresponding to the first semiconductor chip in the general semiconductor module, the wiring forming the transmission coil corresponding to the inductor for communication is thick, and the circuit corresponding to the transmission / reception circuit includes a large-sized transistor.

[0335] On the other hand, the semiconductor module 10M and the semiconductor modules according to each embodiment include a configuration that enables inductor communication using, for example, small-sized inductors 172 and 272, and small-sized transistors. That is, the semiconductor module 10M has a relatively small circuit configuration in which the first semiconductor chip 200 has multiple TCI-IOs 212 for one TCI-IO 112 in the stacked memory chip 100.

[0336] For example, the semiconductor module 10M may have multiple TCI-IOs 212 for one TCI-IO 112, thereby selecting one of the multiple TCI-IOs 212 that can perform optimal inductor communication with the TCI-IO 112. For example, the semiconductor module 10M may use a communication method similar to that of the semiconductor module 10L to select the TCI-IO 212 that can perform optimal inductor communication by combining one TCI-IO 112 (inductor 172) with each of multiple TCI-IOs 212 (multiple inductors 272) using a training sequence. For example, the semiconductor module 10M may select a combination that optimizes communication speed, power (induced current or voltage), and communication quality (e.g., bit error rate within the IC chip 110).

[0337] As a result, the communication method of the semiconductor module 10M is a communication method that makes it easier to select a combination of inductors that are aligned according to the misalignment between the inductor 172 of the stacked memory chip 100 and the inductor 272 of the first semiconductor chip 200. <Twentieth Embodiment> The configuration of a semiconductor module 10N according to the twentieth embodiment will be described with reference to FIG. 43. FIG. 43 is a block diagram showing the configuration of the semiconductor module 10N. Configurations that are the same as or similar to those in FIGS. 1 to 42 will be described as necessary, and descriptions of configurations that are the same as or similar to those in FIGS. 1 to 42 may be omitted. The configuration of the semiconductor module 10N according to the twentieth embodiment can be applied to the semiconductor modules according to each embodiment as long as there is no mutual contradiction.

[0338] Like the semiconductor module 10M, the semiconductor module 10N includes stacked memory chips 100 and a first semiconductor chip 200. The stacked memory chips 100 include a plurality of TCI-IOs 112 and a memory module 111 electrically connected to the plurality of TCI-IOs 112. The first semiconductor chip 200 includes one TCI-IO 212 and a CPU 220 electrically connected to the TCI-IO 212. The configuration of each chip is the same as the configuration described in "1-1. Overview of Semiconductor Module 10," and therefore description thereof will be omitted here.

[0339] On the other hand, the semiconductor module 10N and the semiconductor modules according to each embodiment include a configuration that enables inductor communication using, for example, small-sized inductors 172 and 272, and small-sized transistors. That is, the semiconductor module 10M has a relatively small circuit configuration, with the first semiconductor chip 200 having one TCI-IO 212 and the stacked memory chip 100 having multiple TCI-IOs 112.

[0340] For example, the semiconductor module 10N may have multiple TCI-IOs 112 for one TCI-IO 212, thereby selecting one of the multiple TCI-IOs 112 that can perform optimal inductor communication with the corresponding TCI-IO 212. For example, the semiconductor module 10N may use a communication method similar to that of the semiconductor module 10L to select a TCI-IO 112 that can perform optimal inductor communication by combining multiple TCI-IOs 112 (multiple inductors 272) with one TCI-IO 212 (one inductor 272) using a training sequence. For example, the semiconductor module 10N may select a combination that optimizes communication speed, power (induced current or voltage), and communication quality (e.g., bit error rate within the IC chip 110).

[0341] As a result, the communication method of semiconductor module 10N, like the communication method of semiconductor module 10M, is a communication method that makes it easier to select a combination of inductors that are aligned depending on the misalignment between the inductor 172 of the stacked memory chip 100 and the inductor 272 of the first semiconductor chip 200.

[0342] The various configurations of the semiconductor module exemplified as embodiments of the present invention can be combined as appropriate as long as they are not mutually contradictory, and technical matters common to each embodiment are included in each embodiment even if not explicitly stated. Furthermore, semiconductor modules disclosed in this specification and drawings that have been modified by a person skilled in the art to add, delete, or modify components, or to add, omit, or change conditions as appropriate, are also included in the scope of the present invention as long as they include the gist of the present invention.

[0343] Even if there are other effects and advantages different from those brought about by the aspects of the embodiments disclosed in this specification, those that are clear from the description in this specification or that can be easily predicted by a person skilled in the art are naturally understood to be brought about by the present invention.

[0344] 10: semiconductor module, 10A: semiconductor module, 10B: semiconductor module, 10C: semiconductor module, 10D: semiconductor module, 10E: semiconductor module, 10F: semiconductor module, 10G: semiconductor module, 10H: semiconductor module, 10J: semiconductor module, 10K: semiconductor module, 10L: semiconductor module, 10M: semiconductor module, 10N: semiconductor module, 12: first semiconductor chip, 30: stacked chip group, 32: first surface, 34: second surface, 40: lid, 50: sealing structure, 52: insulating film, 54: insulating film, 60: Package substrate, 62: first surface, 64: second surface, 66: wiring layer, 67: electrode, 68: wiring layer, 69: wiring, 70: wiring layer, 71: wiring, 72: wiring layer, 73: wiring, 74: wiring layer, 75: electrode, 80: thermally conductive sheet, 82: bump, 82A: bump, 84: bump, 90: metal film, 100: stacked memory chip, 100A: stacked memory chip, 100B: stacked memory chip, 100C: stacked memory chip, 100D: stacked memory chip, 101: end, 102: first surface, 102n: first surface, 103: end, 104: second surface, 104n: second surface, 110: chip , 110n: chip, 111: memory module, 112: TCI-IO, 113: parallel-serial conversion circuit, 114: transmitter / receiver circuit, 115: memory cell array, 130: transistor layer, 130n: transistor layer, 131: through electrode, 131j: through electrode, 131k: through electrode, 131m: through electrode, 131o: through electrode, 142: first surface, 144: second surface, 146: third surface, 148: fourth surface, 150: wiring layer, 150n: wiring layer, 151a: insulating layer, 151b: via, 151j: via, 151k: via, 151m: via, 151o: via, 152a: insulating layer , 152b: wiring, 152c: wiring, 152j: wiring, 152k: wiring, 152m: wiring, 152nj: wiring, 152o: wiring, 153a: insulating layer, 153b: via, 153c: via, 153j: via, 153k: via, 153m: via, 153nj: via, 153nk: via, 153o: via, 154a: insulating layer, 154b: wiring, 154c: wiring, 154d: wiring, 154e: wiring, 154j: wiring, 154k: wiring, 154m: wiring, 154nj: wiring, 154nk: wiring, 154nm: wiring, 154o: wiring, 155a: insulating layer, 155b: via,155c: via, 155d: via, 155e: via, 155f: via, 155g: via, 155j: via, 155k: via, 155m: via, 155nj: via, 155nk: via, 155nm: via, 155no: via, 155o: via, 156a: insulating layer, 156b: wiring, 156c: wiring, 156d: wiring, 156e: wiring, 156f: wiring, 156g: wiring, 156h: wiring, 156i: wiring, 156j: wiring, 156k: wiring, 156m: wiring, 156nj: wiring, 156nk: wiring, 156nm: wiring, 156no: wiring, 156o: wiring , 160: seal ring, 160n: seal ring, 162: side power supply wiring, 163: side ground wiring, 164: power supply wiring, 165: ground wiring, 165b: power supply wiring, 165c: end portion, 166: signal transmission wiring, 172: inductor, 172a: first portion, 172b: second portion, 172c: third portion, 172d: fifth portion, 172e: fourth portion, 172f: inductor, 172fa: first portion, 172g: inductor, 172h: inductor, 172i: inductor, 172j: inductor, 172k: inductor, 172m: inductor, 172n: inductor 172o: inductor, 172p: inductor, 172q: inductor, 173: semiconductor substrate, 173n: semiconductor substrate, 174: element isolation region, 175: activation region, 176: transistor, 177: insulating layer, 178: wiring, 179: insulating layer, 180: wiring, 181: insulating layer, 182: insulating layer, 183: wiring, 183b: wiring, 183c: wiring, 183d: wiring, 183e: wiring, 183f: wiring, 183g: wiring, 183j: wiring, 183k: wiring, 183nj: wiring, 183nk: wiring, 183nm: wiring, 183no: wiring, 183o: wiring lines, 184a: vias, 184b: vias, 184c: vias, 184d: vias, 184e: vias, 184f: vias, 184g: vias, 184h: vias, 184i: vias, 184j: vias, 184k: vias, 184m: vias, 184nj: vias, 184nk: vias, 184nm: vias, 184no: vias, 184o: vias, 190: insulating film, 192: outer periphery, 196j: wiring, 196nk: wiring, 196nm: wiring, 196no: wiring, 200: first semiconductor chip, 202: first surface, 204: second surface, 206: third surface, 208: fourth surface, 212: TCI-IO,213: parallel-serial conversion circuit, 214: transmitting / receiving circuit, 221: register, 223: table, 262: side power supply wiring, 263: side ground wiring, 271: inductor, 271o: inductor, 271p: inductor, 272: inductor, 272a: first part, 272b: second part, 272c: third part, 272d: fifth part, 272e: fourth part, 272h: inductor, 272i: inductor, 272j: inductor, 272k: inductor, 272m: inductor, 272n: inductor, 272o: inductor, 272p: inductor, 300: stacked DRAM, 300A: stacked DRAM, 300B: stacked DRAM, 300D: stacked DRAM, 312: TCI-IO, 313: parallel Serial conversion circuit, 314: transmitting / receiving circuit, 361d: side wiring, 372: inductor, 372a: first portion, 372b: second portion, 372c: third portion, 372d: fifth portion, 372e: fourth portion, 372f: inductor, 383: wiring, 400: supporting substrate, 400A: supporting substrate, 500A: TCI-IO chip, 500C: TCI-IO chip, 600: second semiconductor chip, 600A: second semiconductor chip, 612: TCI-IO, 613: parallel-serial conversion circuit, 614: transmitting / receiving circuit, 672: inductor, 700: chip, 700A: chip, 800: bump layer, 850: adhesive layer, 860: structure, 900: third semiconductor chip, 902: first surface, 904: second surface, 910: logic module,

Claims

1. A stacked memory chip including a first substrate including a first surface parallel to a first direction and a second direction intersecting the first direction; a stacked memory chip including a plurality of memory chips provided on the first surface along a third direction intersecting the first and second directions and stacked along the third direction, and a first inductor provided across the plurality of memory chips; and a first semiconductor chip provided on the first surface and spaced apart from the stacked memory chips along the first direction, the stacked memory chip including a second surface facing parallel to the first surface and being the outermost surface on the first substrate side, and a third surface facing parallel to the second and third directions and being the outermost surface on the first semiconductor chip side, the first inductor being parallel to the third surface and being spaced apart from the third surface, the first semiconductor chip including a fourth surface facing parallel to the first surface and being the outermost surface on the first substrate side, and a fifth surface facing parallel to the third surface and being the outermost surface on the stacked memory chip side, the second inductor is provided parallel to the fifth surface and spaced apart from the fifth surface, and the first inductor communicates with the second inductor in a contactless manner.

2. A stacked memory chip provided on the first surface, the stacked memory chip including: a first substrate including a first surface parallel to a first direction and a second direction intersecting the first direction; a second surface parallel to a third direction intersecting the first direction and the second direction and being the outermost surface along the second direction; a third surface parallel to the first surface and along the third direction and being the outermost surface on the first surface side; a plurality of memory chips stacked parallel to the third surface; and a first inductor provided across the plurality of memory chips; and a first semiconductor chip provided between the first surface and the third surface, the first surface facing the first surface and being the outermost surface on the first surface side; a fifth surface opposite the fourth surface and facing the third surface and being the outermost surface on the third surface side; Semiconductor module.

3. The semiconductor module according to claim 1 or claim 2, wherein the first semiconductor chip is a stacked IC chip including a plurality of stacked IC chips, each of the plurality of IC chips includes a seal ring arranged on the outer periphery of the IC chip, and the wiring layer of each of the plurality of IC chips includes the seal ring and a portion of the second inductor, and in end view, the seal ring extends parallel to the semiconductor substrate of the IC chip and in the second direction and is arranged on the semiconductor substrate of the IC chip, a portion of the first inductor overlaps the seal ring and is provided on the third surface side of the seal ring, and a portion of the second inductor overlaps the seal ring and is provided on the fifth surface side of the seal ring.

4. A semiconductor module according to claim 1 or claim 2, wherein the first semiconductor chip is a stacked IC chip including a plurality of stacked IC chips, and the number of stacked memory chips is equal to or less than the number of stacked IC chips.

5. A semiconductor module according to claim 1 or claim 2, wherein the first semiconductor chip is a stacked IC chip including a plurality of stacked IC chips, the stacked memory chip includes a plurality of the first inductors, the stacked IC chip includes a plurality of the second inductors, the plurality of first inductors are arranged in a matrix parallel to the third surface, and the plurality of second inductors are arranged in a matrix parallel to the fifth surface.

6. The semiconductor module of claim 1, further comprising: a first internal wiring exposed on the third surface; a first side surface wiring provided on the third surface and electrically connected to the first internal wiring; a second internal wiring exposed on the fifth surface; a second side surface wiring provided on the fifth surface and electrically connected to the second internal wiring; and a side connection terminal provided between the third surface and the fifth surface, electrically connecting the first side surface wiring and the second side surface wiring.

7. The semiconductor module according to claim 1, further comprising a bump layer including a plurality of bumps between the second and fourth surfaces and the first surface, and wherein, in a plan view, the diameter of the bumps is 10 μm or more and 150 μm or less.

8. The semiconductor module according to claim 7, wherein, in plan view, the number of the plurality of bumps provided on the second surface is different from the number of the plurality of bumps provided on the fourth surface.

9. The semiconductor module according to claim 7, wherein, in a plan view, the distance between the plurality of bumps provided on the second surface along the first direction is equal to or less than the distance between the plurality of bumps provided on the fourth surface along the first direction.

10. The semiconductor module according to claim 7, wherein, in a plan view, the diameter of each of the plurality of bumps provided on the second surface is the same as the diameter of each of the plurality of bumps provided on the fourth surface.

11. The semiconductor module according to claim 10, wherein, in end view, the length from the first surface to an end of the first inductor is the same as the length from the first surface to the end of the second inductor.

12. The semiconductor module described in claim 7, wherein, in a plan view, the diameter of each of the plurality of bumps provided on the second surface is different from the diameter of each of the plurality of bumps provided on the fourth surface, and, in an end view, the length from the first surface to the end of the first inductor is the same as the length from the first surface to the second inductor.

13. The semiconductor module according to claim 1 or 2, wherein each of the plurality of memory chips has a chip ID, and the first semiconductor chip is configured to transmit the chip ID to the stacked memory chip when the non-contact communication is initiated.

14. A semiconductor module as described in claim 1 or claim 2, wherein each of the plurality of IC chips has a chip ID, and the first semiconductor chip is configured to, when the non-contact communication is initiated, execute the non-contact communication between an IC chip of the plurality of IC chips corresponding to the chip ID and the stacked memory chip.

15. The semiconductor module according to claim 1 or 2, wherein the stacked memory chip includes a first transmitting / receiving circuit electrically connected to the first inductor, the first semiconductor chip includes a plurality of the second inductors and a second transmitting / receiving circuit electrically connected to each of the plurality of second inductors, and the stacked memory chip is configured to select one second inductor from the plurality of second inductors, and the first inductor communicates with the one second inductor in a contactless manner.

16. The semiconductor module according to claim 1 or 2, wherein the stacked memory chip includes a plurality of the first inductors and a first transmitting / receiving circuit electrically connected to each of the plurality of first inductors, the first semiconductor chip includes a second transmitting / receiving circuit electrically connected to the second inductor, and the first semiconductor chip is configured to select one first inductor from the plurality of first inductors, and the second inductor communicates with the one first inductor in a contactless manner.

17. The semiconductor module according to claim 1 or 2, wherein the stacked memory chip includes a plurality of the first inductors; the first semiconductor chip includes a plurality of the second inductors; the first semiconductor chip is configured to: cause communication between each of the plurality of first inductors and each of the plurality of second inductors in all combinations; acquire data related to the strength of communication between all of the combinations; select one first inductor from the plurality of first inductors and one second inductor from the plurality of second inductors based on the acquired data; and cause contactless communication between the one first inductor and the one second inductor.

18. The semiconductor module according to claim 17, wherein the first semiconductor chip is configured to perform communication at multiple communication speeds between each of the plurality of first inductors and each of the plurality of second inductors in all combinations and to obtain data related to the strength of communication in all of the combinations.

19. The semiconductor module described in claim 1, wherein the first semiconductor chip is a stacked IC chip including a plurality of stacked IC chips, the second inductor is provided across the plurality of IC chips, each of the plurality of memory chips and each of the plurality of IC chips includes a semiconductor substrate and a wiring layer stacked on the semiconductor substrate, the semiconductor substrate of at least one memory chip of the plurality of memory chips is exposed on the third surface, and the semiconductor substrate of at least one IC chip of the plurality of IC chips is exposed on the fifth surface.

20. The semiconductor module described in claim 2, wherein the first semiconductor chip is a stacked IC chip including a plurality of stacked IC chips, the second inductor is provided on the IC chip closest to the third surface, each of the plurality of memory chips and each of the plurality of IC chips includes a semiconductor substrate and a wiring layer stacked on the semiconductor substrate, and the semiconductor substrate of at least one memory chip of the plurality of memory chips is exposed to the third surface.

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