Detection circuit and sensor device

Abstract

A detection circuit according to the present disclosure comprises an element, an initial setting unit, and a detection unit. The element changes in a characteristic depending on the temperature and the exposure time exposed to the temperature. The initial setting unit sets the initial state of the characteristic of the element to a first characteristic. The detection unit detects whether or not the characteristic of the element has changed from the first characteristic to a second characteristic.

Description

Detection circuit and sensor device

[0001] The present disclosure relates to a detection circuit and a sensor device.

[0002] For example, electronic devices such as computers and cameras have multiple electronic components densely packed together. Therefore, heat generated by each electronic component during operation can cause malfunctions in the electronic device. Even when the electronic device is not in operation, malfunctions can occur due to rechargeable batteries that heat up during charging or exposure to high temperatures, such as inside a car in summer.

[0003] For this reason, many electronic devices are equipped with temperature sensors that detect the temperature of electronic components, timers that detect a predetermined time, such as the exposure time to a predetermined temperature, etc. In this way, electronic devices can be equipped with various sensors, such as temperature sensors, timers, and sensors that detect magnetism.

[0004] Japanese Patent Application Laid-Open No. 2004-96073

[0005] For example, an electronic device may not always be powered on when it is desired to detect the temperature or the exposure time at that temperature, such as during charging. If a power source is required to drive a sensor (detection circuit) such as a temperature sensor that detects the temperature or a timer that detects the exposure time at a predetermined temperature, the sensor may not be able to detect the temperature or exposure time when the electronic device is not powered on.

[0006] It is desirable to be able to use sensors such as a temperature sensor and a timer to detect not only the state of an electronic device when it is turned on, but also the state when it is turned off (for example, temperature and exposure time to that temperature). In other words, it is desirable to be able to detect the state using a sensor that does not require a power source.

[0007] Therefore, the present disclosure provides a detection circuit and a sensor device that can detect the surrounding conditions without requiring a power source.

[0008] It should be noted that the above problem or object is merely one of multiple problems or objects that can be solved or achieved by multiple embodiments disclosed in this specification.

[0009] The detection circuit according to the present disclosure includes an element, an initial setting unit, and a detection unit. The element has characteristics that change depending on temperature and the exposure time of the element. The initial setting unit sets the initial state of the characteristics of the element to a first characteristic. The detection unit detects whether the characteristics of the element have changed from the first characteristic to a second characteristic.

[0010] FIG. 1 is a diagram illustrating an example of a schematic configuration of an information processing device according to a first embodiment of the present disclosure. FIG. 2 is a block diagram illustrating an example of a configuration of a sensor unit according to the first embodiment of the present disclosure. FIG. 3 is a block diagram illustrating an example of a configuration of a sensor circuit according to the first embodiment of the present disclosure. FIG. 4 is a diagram illustrating an example of a configuration of a sensor circuit according to the first embodiment of the present disclosure. FIG. 5 is a diagram illustrating an example of a memory element according to the first embodiment of the present disclosure. FIG. 6 is a diagram illustrating an example of a potential with respect to the magnetization direction of a free layer of a memory element according to the first embodiment of the present disclosure. FIG. 7 is a diagram illustrating an output of a sensor circuit when a memory element according to the first embodiment of the present disclosure is in an initial state. FIG. 8 is a diagram illustrating an output of a sensor circuit when a memory element according to the first embodiment of the present disclosure is in an inverted state. FIG. 9 is a diagram illustrating an example of a potential with respect to the magnetization direction of a free layer of a memory element according to a first modification of the first embodiment of the present disclosure. FIG. 10 is a diagram illustrating an example of a configuration of a sensor circuit using a footer-type SSR-NVFF circuit system according to a second modification of the first embodiment of the present disclosure. FIG. 11 is a diagram illustrating an example of a sensor circuit using a footer-type SSR-NVFF circuit system according to a third modification of the first embodiment of the present disclosure. FIG. 12 is a diagram illustrating an example of a configuration of a sensor circuit using a header-type SSR-NVFF circuit system with a verify function according to a fourth modification of the first embodiment of the present disclosure. FIG. 10 is a diagram showing a configuration example of a sensor circuit using a footer-type SSR-NVFF circuit system having a verify function according to a fifth modified example of the first embodiment of the present disclosure. FIG. 11 is a diagram showing a configuration example of a sensor circuit using a header-type SSR-NVFF circuit system having a verify function and a set / reset function according to a sixth modified example of the first embodiment of the present disclosure. FIG. 12 is a diagram showing another configuration example of a sensor circuit using a header-type SSR-NVFF circuit system having a verify function and a set / reset function according to a sixth modified example of the first embodiment of the present disclosure. FIG. 13 is a diagram showing an example of a sensor circuit using a footer-type SSR-NVFF circuit system having a verify function and a set / reset function according to a seventh modified example of the first embodiment of the present disclosure.FIG. 13 is a diagram showing another configuration example of a footer-type SSR-NVFF circuit type sensor circuit having a verify function and a set / reset function according to a seventh modified example of the first embodiment of the present disclosure. FIG. 14 is a diagram showing another configuration example of a header-type SSR-NVFF circuit type sensor circuit having a verify function and a set / reset function according to a seventh modified example of the first embodiment of the present disclosure. FIG. 15 is a diagram showing an example of transition of the magnetization direction of a free layer of a memory element according to an eighth modified example of the first embodiment of the present disclosure. FIG. 16 is a block diagram showing an example of a configuration example of a sensor circuit according to a second embodiment of the present disclosure. FIG. 17 is a diagram showing an example of a configuration example of a sensor circuit according to a second embodiment of the present disclosure.

[0011] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. In this specification and drawings, components having substantially the same functional configurations are designated by the same reference numerals, and redundant description will be omitted.

[0012] Furthermore, in this specification and drawings, multiple components having substantially the same functional configuration may be distinguished by adding different letters or numbers after the same reference symbol. However, if there is no particular need to distinguish between multiple components having substantially the same functional configuration, only the same reference symbol will be used.

[0013] Furthermore, although specific values ​​are sometimes used in the present specification and drawings, these values ​​are merely examples and other values ​​may also be applied.

[0014] One or more embodiments (including examples, modifications, and application examples) described below can be implemented independently. However, at least a portion of the embodiments described below may be implemented in appropriate combination with at least a portion of another embodiment. These embodiments may include novel features that are different from each other. Therefore, these embodiments may contribute to solving different purposes or problems and may produce different effects from each other.

[0015] <<1. First embodiment>> <1-1. Configuration example of information processing device> Fig. 1 is a diagram showing an example of a schematic configuration of an information processing device 100 according to a first embodiment of the present disclosure. The information processing device 100 is, for example, an electronic device such as a personal computer (PC), a tablet terminal, a smartphone, or a camera. The information processing device 100 may be of any type as long as it is equipped with a sensor device that measures at least one of the temperature around a measurement target and the exposure time for which the measurement target is exposed to that temperature.

[0016] The information processing device 100 shown in FIG. 1 includes a communication unit 110, a storage unit 120, a control unit 130, and a sensor unit 140 (an example of a sensor device).

[0017] (Communication Unit 110) The communication unit 110 is a communication interface for communicating with other communication devices. The communication unit 110 may be a network interface or a device connection interface. The communication unit 110 may be a LAN (Local Area Network) interface such as a NIC (Network Interface Card), or a Universal Serial Bus (USB) interface configured by a USB host controller or a USB port. The communication unit 110 may be a wired interface or a wireless interface. The communication unit 110 is controlled by the control unit 130.

[0018] (Storage Unit 120) The storage unit 120 is a readable and writable storage device such as a dynamic random access memory (DRAM), a static random access memory (SRAM), a flash memory, or a hard disk.

[0019] (Control Unit 130) The control unit 130 is a controller that controls each unit of the information processing device 100. The control unit 130 may be realized by a processor such as a CPU (Central Processing Unit) or an MPU (Micro Processing Unit). In particular, the control unit 130 may be realized by a processor executing various programs stored in an internal storage device of the information processing device 100 using a RAM (Random Access Memory) or the like as a work area. The control unit 130 may be realized by an integrated circuit such as an ASIC (Application Specific Integrated Circuit) or an FPGA (Field Programmable Gate Array). The control unit 130 may also be realized by a GPU (Graphics Processing Unit). A CPU, an MPU, an ASIC, an FPGA, and a GPU can all be considered controllers. The control unit 130 may be composed of multiple physically separated objects. For example, the control unit 130 may be composed of multiple semiconductor chips.

[0020] (Sensor Unit 140) The sensor unit 140 detects at least one of the ambient temperature of the measurement target and the time (exposure time) that the measurement target is exposed to that temperature. Examples of the measurement target of the sensor unit 140 include electronic components (e.g., ICs (Integrated Circuits) and rechargeable batteries) mounted on the information processing device 100.

[0021] 2 is a block diagram showing an example configuration of the sensor unit 140 according to the first embodiment of the present disclosure. The sensor unit 140 shown in FIG. 2 includes a sensor 141, an acquisition unit 142, a determination unit 143, a storage 144, and an initialization unit 145.

[0022] (Sensor 141) The sensor 141 has a plurality of sensor circuits 10 (an example of a detection circuit).

[0023] (Sensor circuit 10) Fig. 3 is a block diagram showing an example configuration of the sensor circuit 10 according to the first embodiment of the present disclosure. The sensor circuit 10 shown in Fig. 3 includes a first non-volatile element 1011 (an example of an element), a second non-volatile element 1012, a first initialization circuit 1021 (an example of an initial setting unit), a second initialization circuit 1022, and a readout circuit 1030 (an example of a detection unit).

[0024] The first nonvolatile element 1011 and the second nonvolatile element 1012 have substantially the same characteristics. Therefore, when there is no need to particularly distinguish between the first nonvolatile element 1011 and the second nonvolatile element 1012, they are also simply referred to as nonvolatile elements 1010.

[0025] The first initialization circuit 1021 and the second initialization circuit 1022 have substantially the same characteristics. Therefore, when there is no need to particularly distinguish between the first initialization circuit 1021 and the second initialization circuit 1022, they are also simply referred to as initialization circuits 1020.

[0026] (Nonvolatile element 1010) The nonvolatile element 1010 changes its characteristics (e.g., a "high resistance state" or a "low resistance state") depending on the temperature and the exposure time to that temperature. The nonvolatile element 1010 may be, for example, a magnetic tunnel junction (MTJ) element. For example, the sensor 141 may be a magnetoresistive random access memory (MRAM).

[0027] The sensor 141 is not limited to an MRAM, but may include any element that is sensitive to temperature, that is, a plurality of elements whose characteristics change depending on the temperature and the exposure time to that temperature.

[0028] The sensor 141 may be any sensor that has a temperature-sensitive memristor as the nonvolatile element 1010. Examples of nonvolatile memories that have a temperature-sensitive memristor include, in addition to MRAM, a resistive random access memory (ReRAM) and a phase-change memory (PCM). Examples of the nonvolatile element 1010 include a resistance change type, a phase change type, a separation type, and a voltage change type nonvolatile element.

[0029] The sensor circuit 10 holds and outputs a value (sensor information) according to the combination of the characteristics (e.g., "high resistance state" or "low resistance state") of the first non-volatile element 1011 and the second non-volatile element 1012.

[0030] (Initialization circuit 1020) The initialization circuit 1020 controls the nonvolatile element 1010 by passing a current through the nonvolatile element 1010 so that the nonvolatile element 1010 retains a particular characteristic (e.g., a "high resistance state" or a "low resistance state").

[0031] The initialization circuit 1020 initializes the nonvolatile element 1010 in response to an instruction from, for example, the initialization unit 145 (see FIG. 2).

[0032] (Readout Circuit 1030) The readout circuit 1030 reads out the characteristics of the first non-volatile element 1011 and the characteristics of the second non-volatile element 1012, and generates sensor information according to a combination of these characteristics. The readout circuit 1030 outputs the generated sensor information to the acquisition unit 142.

[0033] 2 , as described above, the sensor 141 includes a plurality of sensor circuits 10. An initial value (bit value) is written to the sensor 141 by an initialization unit 145, which will be described later. That is, each sensor circuit 10 of the sensor 141 is controlled by the initialization unit 145 so that it has a specific characteristic (for example, "0" or "1") as its initial state.

[0034] The initial state of each sensor circuit 10 may be the same or different from each other. The initial value of each sensor circuit 10 may be "0" (low resistance state) or "1" (high resistance state).

[0035] The nonvolatile element 1010 reverses its characteristic ("0" or "1") depending on the temperature and exposure time. When the nonvolatile element 1010 reverses, the value of the sensor circuit 10 also reverses. The number of sensor circuits 10 whose values ​​reverse varies depending on the ambient temperature of the sensor 141 and the exposure time.

[0036] Hereinafter, the ratio of the number of sensor circuits 10 that are inverted in response to the ambient temperature and exposure time to the total number of sensor circuits 10 included in the sensor 141 will be referred to as the inversion rate F of the sensor 141.

[0037] Here, the sensor circuit 10 includes a nonvolatile element 1010 whose characteristics change depending on the temperature. Therefore, the sensor circuit 10 can maintain specific characteristics (initial values) when no power is supplied to the sensor circuit 10. Furthermore, the characteristics of the sensor circuit 10 change depending on the ambient temperature and exposure time when no power is supplied. In other words, the sensor circuit 10 can detect the ambient conditions without the supply of power.

[0038] The sensor circuit 10 will be described in detail later.

[0039] 2 , the acquisition unit 142 acquires sensor information from the sensor 141. The sensor information includes information about the sensor circuit 10 whose characteristics have changed. Specifically, the sensor information includes the bit value ("0" or "1") of each sensor circuit 10.

[0040] The acquisition unit 142 outputs the sensor information to the determination unit 143 .

[0041] (Storage 144) The storage 144 is a readable / writable storage device such as a DRAM, an SRAM, a flash memory, or a hard disk. The storage 144 stores the initial values ​​of the sensor 141. The storage 144 also stores the determination result by the determination unit 143 (for example, at least one of the temperature and the exposure time).

[0042] (Initialization Unit 145) The initialization unit 145 initializes the sensor 141, for example, in accordance with an instruction from the determination unit 143. The initialization unit 145 instructs the initialization circuit 1020 of the sensor circuit 10 to control the non-volatile element 1010 to a specific state (for example, from a "high resistance state" to a "low resistance state").

[0043] For example, the determination unit 143 instructs the initialization unit 145 to initialize the sensor 141 after the acquisition unit 142 acquires the sensor information.

[0044] Alternatively, the determination unit 143 may instruct the initialization unit 145 to initialize the sensor 141 after detecting (determining) the temperature and the exposure time. Note that the timing at which the initialization unit 145 initializes the sensor 141 is not limited to the above example. For example, the initialization unit 145 may initialize the sensor 141 at various times, such as at a time instructed by the control unit 130.

[0045] (Determination Unit 143) The determination unit 143 detects at least one of the ambient temperature of the sensor 141, in other words, the measurement target, and the exposure time, based on the sensor information acquired by the acquisition unit 142.

[0046] The determination unit 143 calculates the reversal rate F based on the sensor information. For example, as described above, whether the characteristics of the sensor circuit 10 are reversed depends on the ambient temperature of the sensor circuit 10 and the exposure time of the sensor circuit 10 to this temperature. Therefore, the reversal rate of the sensor 141 changes depending on the temperature and the exposure time.

[0047] For example, when one of the temperature and the exposure time is known, the determination unit 143 can detect the other according to the reversal rate F. In this case, the determination unit 143 can obtain one of the temperature and the exposure time from another sensor (not shown).

[0048] It should be noted that the sensor unit 140 can detect both the temperature and the exposure time by including a plurality of sensors 141 having different susceptibility to changes in characteristics due to temperature and exposure time (sensitivity to temperature).

[0049] If the temperature sensitivity of each of the multiple sensors 141 differs, the reversal rate F of each sensor 141 also differs. That is, even if multiple sensors 141 are exposed to the same temperature for the same time (exposure time), the number of sensor circuits 10 whose characteristics change differs for each sensor 141 depending on its sensitivity to temperature.

[0050] The determination unit 143 calculates, for example, the reversal rates F of the sensors 141 each having a different sensitivity to temperature. The determination unit 143 can detect the temperature and exposure time according to the combination of the calculated reversal rates F.

[0051] The method for detecting the temperature and exposure time described here is merely an example. The determination unit 143 only needs to detect at least one of the temperature and exposure time using the sensor information from the sensor 141, and the method is not limited to the above example.

[0052] The determination unit 143 outputs at least one of the detected temperature and the exposure time to the control unit 130. Alternatively or in addition to this, the determination unit 143 may store at least one of the detected temperature and the exposure time in the storage 144.

[0053] 4 is a diagram showing a configuration example of the sensor circuit 10 according to the first embodiment of the present disclosure. In FIG. 4, the sensor circuit 10 employs a header-type SSR-NVFF circuit system.

[0054] The sensor circuit 10 shown in Figure 4 has a volatile memory unit 11, an initialization driver 12, a transistor 13, a transistor 14, an initialization driver 15, a transistor 16, a transistor 17, a transistor 18, a transistor 19, a non-volatile memory unit 20, an inverter 21, an inverter 22, a control driver 23, an OR circuit 24, and a transistor 25.

[0055] Here, the transistors 13 and 16 are P-channel MOSFETs, and the transistors 14, 17, 18, 19, and 25 are N-channel MOSFETs.

[0056] 4, each transistor is represented by a single element, but in reality, the transistor may be configured as a group of transistor elements in which elements of the same type are connected in parallel according to the current capacity. The same applies to the other examples of sensor circuits below.

[0057] The volatile memory unit 11 is configured as a flip-flop circuit that temporarily holds the state of a memory node, such as stored data (initial value), which is information supplied from the outside, more specifically, the voltage level corresponding to the stored data (initial value).

[0058] The volatile memory unit 11 includes an inverter 41, a transmission gate 42, a master latch 43, a transmission gate 44, a slave latch 45, and an inverter 46. The slave latch 45 is, for example, an example of the read circuit 1030 (see FIG. 3) described above.

[0059] In the above configuration of FIG. 4, the master latch 43 includes an inverter 51 , an inverter 52 and a transmission gate 53 .

[0060] The slave latch 45 also has an inverter 61, an inverter 62, a transmission gate 63, and a transistor (N-channel MOSFET) 64. The slave latch 45 also has a storage node N11 and a storage node N12.

[0061] In the volatile storage unit 11, the transmission gate 42 and the transmission gate 63 are turned on when the clock signal C falls and turned off when the clock signal C rises. In other words, the transmission gate 42 and the transmission gate 63 are turned off when the inverted clock signal CB rises and turned on when the inverted clock signal CB rises.

[0062] In contrast, the transmission gates 53 and 44 are turned off when the clock signal C falls and turned on when the clock signal C rises. In other words, the transmission gates 53 and 44 are turned on when the inverted clock signal CB rises and turned off when the inverted clock signal CB rises.

[0063] In the volatile storage unit 11 , the input side of the inverter 41 serves as the input terminal of the volatile storage unit 11 , and the output side of the inverter 41 is connected to the input side of the inverter 51 via the transmission gate 42 .

[0064] The output side of the inverter 51 is connected to the storage node N11 of the slave latch 45 via the transmission gate 44, and the output terminal of the inverter 51 is also connected to the input side of the inverter 52.

[0065] Furthermore, the output side of the inverter 52 is connected to the input side of the inverter 51 via the transmission gate 53. That is, the output side of the transmission gate 53 is connected between the inverter 51 and the transmission gate 42 via the transmission gate 53.

[0066] The slave latch 45 has storage nodes N11 and N12 that temporarily hold a voltage level corresponding to input storage data. An inverter 61 is provided between the storage nodes N11 and N12.

[0067] The storage node N12 is connected to the input terminals of the inverter 46, the inverter 62, and the initialization driver 15. The output side of the inverter 46 serves as the output terminal of the volatile storage unit 11.

[0068] The output side of the inverter 62 is connected to the storage node N11 via a transmission gate 63. A transistor 64, which is an N-channel MOSFET, is connected to both ends of the transmission gate 63. In other words, one end of the transistor 64 is connected to the input side of the transmission gate 63, and the other end of the transistor 64 is connected to the output side of the transmission gate 63. A restore (read) control signal SR1 of a predetermined voltage level is supplied to the gate of the transistor 64.

[0069] The input terminal of the initialization driver 12 is also connected to the storage node N11.

[0070] The initialization driver 12 corresponds to, for example, the second initialization circuit 1022 (see FIG. 3) described above. The initialization driver 12 shown in FIG. 4 is configured as an inverter, which is an inverting element. That is, the initialization driver 12 includes a transistor 71, which is a P-channel MOSFET, and a transistor 72, which is an N-channel MOSFET.

[0071] In the initialization driver 12, one terminal of a transistor 71 is connected to a transistor 72. The other terminal of the transistor 71 is connected to a power supply via a transistor 13.

[0072] The gate of the transistor 13 is supplied with an inverted signal of the initialization control signal SR2 via an inverter 21.

[0073] The terminal of the transistor 72 opposite to the terminal connected to the transistor 71 is connected to ground via the transistor 14. The gate of the transistor 14 is supplied with an initialization control signal SR2.

[0074] Furthermore, the output side terminal of the inverter formed by the transistor 71 and the transistor 72 is connected to the nonvolatile memory unit 20 via a node N13.

[0075] The initialization driver 15 corresponds to, for example, the first initialization circuit 1021 (see FIG. 3) described above. The initialization driver 15 shown in FIG. 4 is configured as an inverter, which is an inverting element. That is, the initialization driver 15 includes a transistor 81, which is a P-channel MOSFET, and a transistor 82, which is an N-channel MOSFET.

[0076] In the initialization driver 15, a transistor 82 is connected to one terminal of a transistor 81. The other terminal of the transistor 81 is connected to a power supply via a transistor 16.

[0077] The gate of the transistor 16 is supplied with an inverted signal of the initialization control signal SR 2 via an inverter 22 .

[0078] The terminal of the transistor 82 opposite to the terminal connected to the transistor 81 is connected to ground via the transistor 17. The gate of the transistor 17 is supplied with an initialization control signal SR2.

[0079] Furthermore, the output side terminal of the inverter formed by the transistor 81 and the transistor 82 is connected to the nonvolatile memory unit 20 via a node N14.

[0080] The nonvolatile storage unit 20 is a nonvolatile storage unit that stores data corresponding to the voltage level states of the storage nodes N11 and N12 during initialization (writing).

[0081] Furthermore, during restore (read), the stored data held in the nonvolatile memory unit 20, i.e., the state of the held voltage level, is read out to the memory nodes N11 and N12 via a path different from the path taken during initialization.

[0082] The nonvolatile memory unit 20 includes a memory element 91 and a memory element 92. The memory element 91 corresponds to, for example, the first nonvolatile element 1011 (see FIG. 3 ) described above. The memory element 92 corresponds to, for example, the second nonvolatile element 1012 described above. The example of FIG. 4 shows a case where the memory elements 91 and 92 are MTJs.

[0083] Here, the memory element 91 according to the first embodiment will be described with reference to Figures 5 and 6. Note that the memory element 92 has the same configuration as the memory element 91, and therefore description thereof will be omitted here.

[0084] Fig. 5 is a diagram illustrating an example of a memory element 91 according to the first embodiment of the present disclosure. Fig. 6 is a diagram illustrating an example of potential with respect to the magnetization direction of the free layer 912 of the memory element 91 according to the first embodiment of the present disclosure.

[0085] 5, the memory element 91 includes a fixed layer (P layer) 911, a free layer (F layer) 912, and a barrier layer 913 formed between the fixed layer 911 and the free layer 912. The memory element 91 is a nonvolatile memory element whose resistance can be changed between a high resistance state and a low resistance state by an applied voltage.

[0086] When the magnetization direction of the free layer 912 of the memory element 91 (the upward arrow of the free layer 912 on the left side of FIG. 6) is the same as (parallel to) the magnetization direction of the fixed layer 911 (the upward arrow of the fixed layer 911 in FIG. 5), the memory element 91 is in a low resistance state. When the magnetization direction of the free layer 912 of the memory element 91 (the downward arrow of the free layer 912 on the right side of FIG. 6) is opposite (anti-parallel to) the magnetization direction of the fixed layer 911 (the upward direction of the fixed layer 911 in FIG. 5), the memory element 91 is in a high resistance state.

[0087] In this embodiment, the low resistance state of the storage element 91 is also called a parallel state (hereinafter referred to as a P state), and the high resistance state is also called an anti-parallel state (hereinafter referred to as an AP state).

[0088] For example, when the memory element 91 is in a high resistance state, it corresponds to a higher voltage level, "H" level, in other words, stored data '1' ('1' state). Also, for example, when the memory element 91 is in a low resistance state, it corresponds to a lower voltage level, "L" level, in other words, stored data '0' ('0' state). In this way, the memory element 91 can store information according to its state.

[0089] In this embodiment, the memory element 91 is assumed to have an initial state (initial value) of '1' (high resistance state). The initial state (initial value) of the memory element 92 is assumed to be a '0' (low resistance state). The initial states (initial values) of the memory elements 91 and 92 are merely examples and are not limited to these. The initial state (initial value) of the memory element 91 may be a '0' (low resistance state), and the initial state (initial value) of the memory element 92 may be a '1' (high resistance state). It is sufficient that the memory elements 91 and 92 store specific initial states, and the read circuit 1030 can read changes in the initial states. For example, either the '1' (high resistance state) or the '0' (low resistance state) may be selected as the initial state of the memory elements 91 and 92, depending on an instruction from the initialization unit 145 (see FIG. 2 ).

[0090] Here, the storage element 91 in the AP state (see the black circle in FIG. 6) absorbs thermal energy k Ｂ T tries to transition to the P state, but the magnetic energy E Ｂ However, depending on the temperature and time (exposure time) to which the memory element 91 is exposed, the thermal energy k Ｂ T is magnetic energy E Ｂ , the state of the storage element 91 transitions from the AP state to the P state.

[0091] In this way, the state of the memory element 91 changes from the high resistance state, which is the initial value, to the low resistance state depending on the temperature and exposure time. The determination unit 143 detects the temperature and exposure time in response to this change in the state of the memory element 91.

[0092] Here, the potential relative to the magnetization direction of the free layer 912 of the memory element 91 according to this embodiment is lower in the low resistance state than in the high resistance state, i.e., after the memory element 91 transitions (reverses) from the high resistance state, which is the initial value, to the low resistance state depending on the temperature and exposure time, it becomes difficult for the memory element 91 to transition (reverse) from the low resistance state to the high resistance state.

[0093] That is, the memory element 91 is an element that easily switches from a high resistance state to a low resistance state in response to temperature, but does not easily switch from a low resistance state to a high resistance state in response to temperature. Such an element can be realized, for example, by changing the size of the free layer 912 (for example, the diameter of the cylindrical free layer 912).

[0094] As described above, the initial value of the memory element 92 is a low resistance state. Therefore, it is difficult for the memory element 92 to transition from a low resistance state to a high resistance state, and it is easier to maintain the initial value than the memory element 91.

[0095] Returning to FIG. 4, in the nonvolatile memory section 20, the free layer 912 of the memory element 91 is connected to the control line L11, and the opposite side of the free layer 912, that is, the fixed layer 911 of the memory element 91, is connected to the node N14.

[0096] The node N14 is connected to the output end of the initialization driver 15 and is also connected to the storage node N11 via the transistor 18.

[0097] Similarly, the free layer 912 of the memory element 92 is connected to the control line L11, and the fixed layer 911 of the memory element 92 is connected to a node N13.

[0098] The node N13 is connected to the output end of the initialization driver 12 and is also connected to the storage node N12 via the transistor 19.

[0099] The gates of the transistors 18 and 19 are supplied with a restore control signal SR1.

[0100] A control driver 23 for controlling the voltage level of the control line L11 is connected to the control line L11 connected to the storage element 91 and the storage element 92.

[0101] The control driver 23 includes an inverter, which is an inverting element, that is, a transistor 101 which is a P-channel MOSFET and a transistor 102 which is an N-channel MOSFET.

[0102] In the control driver 23, one terminal of the transistor 101 is connected to a power supply, and the other terminal of the transistor 101 is connected to the transistor 102 and the control line L11.

[0103] The terminal of the transistor 102 opposite to the terminal to which the transistor 101 and the control line L11 are connected is connected to ground via a transistor 25 .

[0104] A control signal CTRL is supplied to the input terminals of the control driver 23, that is, the gates of the transistors 101 and 102.

[0105] The gate of the transistor 25 is connected to the output terminal of the OR circuit 24, and the input terminal of the OR circuit 24 is supplied with the restore control signal SR1 and the initialization control signal SR2.

[0106] For example, one sensor circuit 10 may be one cell that constitutes the sensor 141, and multiple cells may be provided within the sensor 141. In this case, the transistor 25 in each sensor circuit 10 is set to an on state in the initialization mode and the restore mode.

[0107] In this case, as the OR circuit 24 for turning on the transistor 25, one OR circuit common to all the plurality of cells, that is, all the plurality of sensor circuits 10 may be provided.

[0108] Next, a description will be given of an example of state transitions of the sensor circuit 10 according to the first embodiment. The sensor circuit 10 operates in three modes: an initialization mode, a sensing mode, and a restore mode.

[0109] In the initialization mode, an initial value is stored in the nonvolatile memory unit 20 of the sensor circuit 10. In the sensing mode, the state of the nonvolatile memory unit 20 is inverted depending on the temperature and exposure time. In the restore mode, the state of the nonvolatile memory unit 20 is read. The sensor circuit 10 transitions through the initialization mode, sensing mode, and restore mode in this order.

[0110] The output of the sensor circuit 10 when the sensor circuit 10 is in a state where the initial value is held (initial state), and the output of the sensor circuit 10 when the memory element 91 is inverted from the initial value will be described below.

[0111] 7 is a diagram illustrating the output of the sensor circuit 10 when the memory element 91 according to the first embodiment of the present disclosure is in the initial state. As described above, the initial value of the memory element 91 is in the '1' state (High), and the initial value of the memory element 92 is in the '0' state (Low).

[0112] In this state, the storage node N11 goes high, the storage node N12 goes low, and the output Q of the inverter 46 goes high.

[0113] 8 is a diagram illustrating the output of the sensor circuit 10 when the memory element 91 according to the first embodiment of the present disclosure is in an inverted state. As described above, the initial value of the memory element 91 is in the '1' state (High), but the state of the memory element 91 is inverted depending on the ambient temperature of the sensor circuit 10 and the exposure time, and transitions from High level to Low level.

[0114] On the other hand, the initial value of the memory element 92 is in the '0' state (low). As described above, the memory elements 91 and 92 are unlikely to transition from low to high. Therefore, even if the state of the memory element 91 is inverted, the state of the memory element 92 is not necessarily inverted. Here, it is assumed that the state of the memory element 91 is inverted, but the state of the memory element 92 is not inverted.

[0115] In this embodiment, the case where the state of memory element 91 is inverted but the state of memory element 92 is not inverted is also described as the state of non-volatile memory unit 20 being inverted or the state of sensor circuit 10 being inverted.

[0116] Due to the inversion of the state of the storage element 91, the storage node N11 changes from a high level to a low level, and the output Q of the inverter 46 changes from a high level to a low level.

[0117] In this way, when the sensor circuit 10 (more specifically, the storage element 91) transitions to the restore mode while maintaining the initial value in the sensor mode, the output Q thereof becomes high level.

[0118] On the other hand, when the sensor circuit 10 (more specifically, the storage element 91) transitions to the restore mode in a state where the value of the sensor circuit 10 is inverted from the initial value in the sensor mode, the output Q thereof becomes low level.

[0119] In the initial state of the sensor circuit 10, the states (values) of the storage elements 91 and 92 are different. The output Q in this case is determined by the difference in the states of the storage elements 91 and 92. On the other hand, when the sensor circuit 10 (more specifically, the storage element 91) is inverted from its initial value, the states (values) of the storage elements 91 and 92 become the same. The output Q in this case is determined by the asymmetry of the slave latch 45.

[0120] In other words, the slave latch 45 has asymmetry, so that the output Q changes when the state of the storage element 91 and the state of the storage element 92 become the same, allowing the slave latch 45 (read circuit 1030) to detect an inversion of the initial value of the sensor circuit 10 (more specifically, the storage element 91).

[0121] In this way, because the slave latch 45 has asymmetry, the slave latch 45 can detect a reversal from the initial value of the sensor circuit 10 (more specifically, the memory element 91) even when the memory elements 91 and 92 of the sensor circuit 10 are in the same state.

[0122] The asymmetry of the slave latch 45 can be realized, for example, by varying the fan-out of the inverters 61 and 62. In addition to the difference in fan-out, the asymmetry of the slave latch 45 may also be realized by the number of constituent elements of the slave latch or the size of the elements.

[0123] In this way, the sensor unit 140 can detect whether the characteristics (initial value) of the storage element 91 have changed (reversed) according to the output Q of the sensor circuit 10 .

[0124] <1-3. Modifications> <1-3-1. First Modification> In the first embodiment described above, the potential in the magnetization direction when the free layers 912 of the memory elements 91 and 92 are in the low resistance state is lower than when they are in the high resistance state. However, the potential in the high resistance state may be lower than when they are in the low resistance state.

[0125] FIG. 9 is a diagram showing an example of the potential with respect to the magnetization direction of the free layer 912 of the memory element 91 according to the first modified example of the first embodiment of the present disclosure.

[0126] 9, the potential with respect to the magnetization direction of the free layer 912 of the memory element 91 according to this modification is lower in the high resistance state than in the low resistance state. The memory element 92 has a configuration similar to that of the memory element 91, and therefore a description thereof will be omitted here.

[0127] As described above, the initial value of the memory element 91 is a high resistance state, so the memory element 91 does not easily transition (change) from a high resistance state to a low resistance state.

[0128] On the other hand, the memory element 92 (an example of an element) has an initial state of low resistance. After the memory element 92 transitions (reverses) from the initial low resistance state to the high resistance state depending on the temperature and exposure time, the memory element 92 becomes less likely to transition (reverse) from the high resistance state to the low resistance state.

[0129] That is, the memory elements 91 and 92 are elements that easily switch from a low resistance state to a high resistance state in response to temperature, but do not easily switch from a high resistance state to a low resistance state in response to temperature. Such elements can be realized, for example, by changing the size of the free layer 912 (for example, the diameter of the cylindrical free layer 912).

[0130] In this way, in the first embodiment, the state of the memory element 91 is easily inverted, whereas in this modification, the state of the memory element 92 is easily inverted.

[0131] The output of the sensor circuit 10 when the state of the sensor circuit 10 is reversed from the initial value of the memory element 92 will be described below. Note that the output of the sensor circuit 10 when the state of the sensor circuit 10 is the same as that shown in FIG. 7 and therefore will not be described here.

[0132] 10 is a diagram illustrating the output of the sensor circuit 10 when the memory element 92 according to the first modification of the first embodiment of the present disclosure is in an inverted state. As described above, the initial value of the memory element 92 is in the '0' state (low), but the state of the memory element 92 is inverted depending on the ambient temperature of the sensor circuit 10 and the exposure time, and transitions from low level to high level.

[0133] On the other hand, the initial value of the storage element 91 is in the '1' state (High). As described above, the storage elements 91 and 92 are unlikely to transition from High to Low. Therefore, even if the state of the storage element 92 is inverted, the state of the storage element 91 is not necessarily inverted. Here, it is assumed that the state of the storage element 92 is inverted and the state of the storage element 91 is not inverted.

[0134] Due to the inversion of the state of the storage element 92, the storage node N12 changes from low level to high level, and the output Q of the inverter 46 changes from high level to low level.

[0135] In the sensor mode, when the sensor circuit 10 (more specifically, the storage element 92) transitions to the restore mode while maintaining the initial value, the output Q thereof becomes high level.

[0136] On the other hand, when the sensor circuit 10 (more specifically, the storage element 92) transitions to the restore mode in a state where the value of the sensor circuit 10 is inverted from the initial value in the sensor mode, the output Q thereof becomes low level.

[0137] In this way, the sensor unit 140 can detect whether the characteristics (initial value) of the storage element 92 have changed (reversed) according to the output Q of the sensor circuit 10 .

[0138] <1-3-2. Second Modification> In the above-described first embodiment, an example has been described in which the present technology is applied to the sensor circuit 10 employing a header-type SSR-NVFF circuit system. However, the second modification relates to a case in which the present technology is also applied to a sensor circuit employing a footer-type SSR-NVFF circuit system.

[0139] 11 is a diagram showing a configuration example of a footer-type SSR-NVFF circuit-based sensor circuit 10A according to a second modification of the first embodiment of the present disclosure. In FIG. 11, parts that are the same as those in the sensor circuit 10 in FIG. 4 are given the same reference numerals, and the descriptions thereof will be used as appropriate.

[0140] The sensor circuit 10A of the second modified example differs from the sensor circuit 10 of Figure 4 in that instead of transistor 18, transistor 19, non-volatile memory unit 20, and OR circuit 24, transistor 211, transistor 212, non-volatile memory unit 20A, and XNOR circuit 24XN are provided.

[0141] The nonvolatile memory unit 20A shown in FIG. 11 includes a memory element 221 and a memory element 222 configured as an MTJ.

[0142] In the sensor circuit 10A, a transistor 211 is provided between the storage node N11 and the node N14, and a transistor 212 is provided between the storage node N12 and the node N13. The transistors 211 and 212 are P-channel MOSFETs, and a restore control signal SR1 is supplied to the gates of the transistors 211 and 212.

[0143] Here, the fixed layer (P layer) of memory element 221 is connected to control line L11, and the free layer (F layer) of memory element 221 is connected to node N14. Furthermore, the fixed layer (P layer) of memory element 222 is connected to control line L11, and the free layer (F layer) of memory element 222 is connected to node N13.

[0144] The restore control signal SR 1 and the initialization control signal SR 2 are supplied to the input terminal of the XNOR circuit 24 XN, and the output terminal of the XNOR circuit 24 N is connected to the transistor 25 .

[0145] In this way, the sensor 141 may include the sensor circuit 10A of the footer type SSR-NVFF circuit system.

[0146] 12 is a diagram showing a configuration example of a sensor circuit 10B using a footer-type SSR-NVFF circuit system according to a third modification of the first embodiment of the present disclosure. In Fig. 12, parts that are the same as those in the sensor circuit 10A of Fig. 11 are given the same reference numerals, and the descriptions thereof will be used as appropriate.

[0147] The sensor circuit 10B of this modification differs from the sensor circuit 10A of FIG. 11 in that it includes a transistor 25A, an XOR circuit 24XA, and a control driver 23.

[0148] 12, transistor 25A is configured as a P-channel MOSFET with one terminal connected to a power supply. XOR circuit 24XA outputs a control signal to the gate of transistor 25A. In control driver 23, one terminal of transistor 101 is connected to the other terminal of transistor 25A, and one terminal of transistor 102 is connected to ground.

[0149] In this way, the sensor 141 may include the sensor circuit 10B of the footer type SSR-NVFF circuit system.

[0150] <1-3-4. Fourth Modification> In the above-described first embodiment and each modification, an example has been described in which the present technology is applied to the sensor circuits 10, 10A, 10B using a header-type or footer-type SSR-NVFF circuit system. The fourth modification is a case in which the present technology is applied to a sensor circuit using a header-type SSR-NVFF circuit system that has a verify function.

[0151] 13 is a diagram showing a configuration example of a sensor circuit 10C using a header-type SSR-NVFF circuit system having a verify function according to a fourth modification of the first embodiment of the present disclosure. In FIG. 13, parts that are the same as those in the sensor circuit 10 in FIG. 4 are given the same reference numerals, and the descriptions thereof will be used as appropriate.

[0152] The sensor circuit 10C in Fig. 13 differs from the sensor circuit 10 in Fig. 4 in that a three-input OR circuit 24A is provided instead of the OR circuit 24. The sensor circuit 10C in Fig. 13 also differs from the sensor circuit 10 in Fig. 4 in that a three-input OR circuit 24A is provided instead of the OR circuit 24.

[0153] 13 differs from the sensor circuit 10 in FIG. 4 in that it receives a restore control signal SR1, an initialization control signal SR2, and a verify restore control signal SR3 as inputs.

[0154] 13 differs from the sensor circuit 10 of FIG. 4 in that it includes a comparison unit 250 that determines whether writing has been performed correctly when the verify restore control signal SR3 is input.

[0155] The comparison unit 250 includes an inverter 251 , an inverter 252 , a transistor 253 , a transistor 254 , and an XOR circuit 255 .

[0156] The input of the inverter 251 is connected to one terminal of a transistor 253, the gate terminal of which receives the verify restore control signal SR3. The output of the inverter 251 is connected to the input terminal of an inverter 252 and one terminal of a transistor 253, the gate terminal of which receives the verify restore control signal SR3.

[0157] The output of the inverter 252 is connected to the input of the inverter 251, and works together with the inverter 251 to form a latch circuit.

[0158] The other terminal of the transistor 253 is connected to the node N14, and the other terminal of the transistor 254 is connected to the node N13.

[0159] One terminal of the XOR circuit 255 is connected to the output of the inverter 251, and the other terminal is connected to the storage node N12, and outputs an "H" level signal when the written data does not match the data actually written.

[0160] <1-3-5. Fifth Modification> In the fourth modification described above, an example has been described in which the present technology is applied to a sensor circuit 10C that uses a header-type SSR-NVFF circuit and has a verify function. The fifth modification relates to a case in which the present technology is applied to a sensor circuit that uses a footer-type SSR-NVFF circuit and has a verify function.

[0161] 14 is a diagram showing a configuration example of a footer-type SSR-NVFF circuit-based sensor circuit 10D having a verify function according to a fifth modification of the first embodiment of the present disclosure. In FIG. 14, parts that are the same as those in the sensor circuit 10C of FIG. 13 are given the same reference numerals, and the descriptions thereof will be used as appropriate.

[0162] The sensor circuit 10D in Fig. 14 differs from the sensor circuit 10C in Fig. 13 in that a three-input XNOR circuit 24XNA is provided instead of the OR circuit 24. The sensor circuit 10D in Fig. 14 also differs from the sensor circuit 10C in that it receives a restore control signal SR1, an initialization control signal SR2, and a verify restore control signal SR3.

[0163] According to these configurations, the initialization and restore operations are the same as those of the sensor circuit 10A in FIG. 11, and the verify restore operation is the same as that of the sensor circuit 10C in FIG.

[0164] 15 is a diagram showing a configuration example of a sensor circuit 10E using a header-type SSR-NVFF circuit system having a verify function and a set / reset function according to a sixth modification of the first embodiment of the present disclosure. In FIG. 15, parts that are the same as those in the sensor circuit 10 in FIG. 4 are denoted by the same reference numerals.

[0165] 15 includes a volatile memory unit 11, an initialization driver 12, a transistor 13, a transistor 14, an initialization driver 15, a transistor 16, a transistor 17, a transistor 18, and a transistor 19. The sensor circuit 10E also includes a non-volatile memory unit 20, an inverter 21, an inverter 22, a control driver 23, a three-input OR circuit 24A, a transistor 25, and a comparison unit 250A.

[0166] Here, the transistors 13 and 16 are P-channel MOSFETs, and the transistors 14, 17, 18, 19, and 25 are N-channel MOSFETs.

[0167] The volatile memory unit 11 includes an inverter 41, a transmission gate 42, a master latch 43A, a transmission gate 44, a slave latch 45A, and an inverter 46. The difference from the volatile memory unit 11 in Fig. 4 is the configuration of the master latch 43A and the slave latch 45A, so these will be explained below, and the explanation of Fig. 4 will be used for the rest.

[0168] The master latch 43A shown in FIG. 15 includes a NAND circuit 301, a NAND circuit 302, and a transmission gate 53.

[0169] The slave latch 45 A also includes a NAND circuit 303 , a NAND circuit 304 , a transmission gate 63 , and a transistor (N-channel MOSFET) 64 .

[0170] In the volatile memory unit 11, the input side of the inverter 41 serves as the input terminal of the volatile memory unit 11, and the output side of the inverter 41 is connected to one input terminal of a NAND circuit 301 via a transmission gate 42. A set signal SN is input to the other input terminal of the NAND circuit 301. The output terminal of the NAND circuit 301 is connected to a storage node N11 of a slave latch 45 via a transmission gate 44, and the output terminal of the NAND circuit 301 is connected to one input terminal of a NAND circuit 302.

[0171] A reset signal CN is input to the other input terminal of the NAND circuit 302, and the output terminal of the NAND circuit 302 is connected to one input terminal of the NAND circuit 301 via the transmission gate 53. In other words, the output of the NAND circuit 302 is connected between the NAND circuit 301 and the transmission gate 42 via the transmission gate 53.

[0172] The slave latch 45A has a storage node N11 and a storage node N12 that temporarily hold a voltage level corresponding to input storage data. A NAND circuit 303 is provided between the storage nodes N11 and N12, and the storage node N11 is connected to one input terminal of the NAND circuit 303.

[0173] The other input terminal of the NAND circuit 303 receives the reset signal CN, and the output terminal of the NAND circuit 303 is connected to the storage node N12.

[0174] The storage node N12 is connected to one input terminal of a NAND circuit 304. The set signal SN is input to the other input terminal of the NAND circuit 304, and the output terminal of the NAND circuit 304 is connected to the storage node N11 via a transmission gate 63.

[0175] In addition, a transistor 64, which is an N-channel MOSFET, is connected to both ends of the transmission gate 63. In other words, one end of the transistor 64 is connected to the input side of the transmission gate 63, and the other end of the transistor 64 is connected to the output side of the transmission gate 63. A restore control signal SR1 of a predetermined voltage level is supplied to the gate of the transistor 64.

[0176] The three-input OR circuit 24 A receives the restore control signal SR 1 , the initialization control signal SR 2 , and the verify restore control signal SR 3 , and inputs the logical sum of these signals to the gate of the transistor 25 .

[0177] The comparison unit 250A determines whether or not writing has been performed correctly when the verify restore control signal SR3 is input.

[0178] Here, the configuration of the comparison unit 250 A will be described. The comparison unit 250 A includes a NAND circuit 305 , a NAND circuit 306 , a transistor 253 , a transistor 254 , and an XOR circuit 255 .

[0179] One input terminal of the NAND circuit 305 is connected to one terminal of the transistor 253, the gate of which receives the verify restore control signal SR3. The other input terminal of the NAND circuit 305 receives the set signal SN. The output terminal of the NAND circuit 304 is connected to one input terminal of the NAND circuit 306 and one terminal of the transistor 253, the gate of which receives the verify restore control signal SR3.

[0180] The output terminal of the NAND circuit 306 is connected to one input terminal of the NAND circuit 305 .

[0181] The other terminal of the transistor 253 is connected to the node N14, and the other terminal of the transistor 254 is connected to the node N13.

[0182] One terminal of the XOR circuit 255 is connected to the output terminal of the NAND circuit 305, and the other terminal is connected to the storage node N12, and outputs an "H" level signal when the written data does not match the data actually written.

[0183] 16 is a diagram showing another configuration example of a sensor circuit 10E using a header-type SSR-NVFF circuit system having a verify function and a set / reset function according to a sixth modification of the first embodiment of the present disclosure. In Fig. 16, the same parts as those in Fig. 15 are denoted by the same reference numerals, and the detailed description thereof is to be cited.

[0184] The sensor circuit 10E in FIG. 16 differs from the sensor circuit 10E in FIG. 15 in that power gating switches 401 and 402 are provided in the NAND circuits 303 and 304 (at their high potential power supply terminals) that constitute the slave latch 45A.

[0185] 16 differs from the sensor circuit 10E of FIG. 15 in that a power gating switch 403 and a power gating switch 404 are provided in the NAND circuit 305 and the NAND circuit 305 (high potential side power supply terminal) that constitute the comparison unit 250A.

[0186] The power gating switches 401 and 402 cut off the power supply to the NAND circuits 303 and 304 when the slave latch 45A is not in use, thereby further reducing leakage current.

[0187] The power gating switches 403 and 404 cut off the power supply to the NAND circuits 305 and 306 when the comparing unit 250A is not in use, thereby further reducing the leakage current.

[0188] 17 is a diagram showing another configuration example of a sensor circuit 10E using a header-type SSR-NVFF circuit system having a verify function and a set / reset function according to a sixth modification of the first embodiment of the present disclosure. In FIG. 17, the same components as those in FIG. 16 are denoted by the same reference numerals, and the detailed description thereof is to be cited.

[0189] The sensor circuit 10E of FIG. 17 differs from the sensor circuit 10E of FIG. 16 in that one terminal of the transistor 18 is connected to the connection point between the transistor 64 and the transmission gate 63 instead of the storage node N11.

[0190] 18 is a diagram showing a configuration example of a footer-type SSR-NVFF circuit-based sensor circuit 10F having a verify function and a set / reset function according to a seventh modification of the first embodiment of the present disclosure. In FIG. 18, parts that are the same as those in the sensor circuit 10E of FIG. 15 are denoted by the same reference numerals.

[0191] The sensor circuit 10F shown in Fig. 18 differs from the sensor circuit 10E shown in Fig. 15 in that a three-input XNOR circuit 24XNA is provided instead of the three-input OR circuit 24A. The sensor circuit 10F shown in Fig. 18 also differs from the sensor circuit 10E shown in Fig. 15 in that a restore control signal SR1, an initialization control signal SR2, and a verify restore control signal SR3 are input to the sensor circuit 10F.

[0192] According to these configurations, the initialization and restore operations are the same as those of the sensor circuit 10A in FIG. 11, and the verify restore operation is the same as that of the sensor circuit 10E in FIG.

[0193] 19 is a diagram showing another configuration example of a footer-type SSR-NVFF circuit-based sensor circuit 10F having a verify function and a set / reset function according to a seventh modification of the first embodiment of the present disclosure. In Fig. 19, the same parts as those in Fig. 18 are denoted by the same reference numerals, and the detailed description thereof is to be cited.

[0194] The sensor circuit 10F of FIG. 19 differs from the sensor circuit 10F of FIG. 18 in that power gating switches 411 and 412 are provided in the NAND circuits 303 and 304 (at their low potential power supply terminals) that constitute the slave latch 45A.

[0195] In addition, the sensor circuit 10F of FIG. 19 differs from the sensor circuit 10F of FIG. 18 in that a power gating switch 413 and a power gating switch 414 are provided in the NAND circuit 305 and the NAND circuit 305 (low potential side power supply terminal) that constitute the comparison unit 250A.

[0196] The power gating switches 411 and 412 cut off the power supply to the NAND circuits 303 and 304 when the slave latch 45A is not in use, thereby further reducing leakage current.

[0197] The power gating switches 413 and 414 cut off the power supply to the NAND circuits 305 and 306 when the comparing unit 250A is not in use, thereby further reducing the leakage current.

[0198] 20 is a diagram showing another configuration example of a sensor circuit 10F using a header-type SSR-NVFF circuit system having a verify function and a set / reset function according to a seventh modification of the first embodiment of the present disclosure. In Fig. 20, the same parts as those in Fig. 19 are denoted by the same reference numerals, and the detailed description thereof is to be cited.

[0199] The sensor circuit 10F of FIG. 20 differs from the sensor circuit 10F of FIG. 19 in that one terminal of the transistor 18 is connected to the connection point between the transistor 64 and the transmission gate 63 instead of the storage node N11, thereby changing the current path during restoration.

[0200] <1-3-8. Eighth Modification> As described above, in the first embodiment, the initial values ​​stored in the nonvolatile memory unit 20 are determined in advance. For example, in the sensor circuit 10 of FIG. 4, the initial value (initial state) of the memory element 91 is '1' (high resistance state). Also, the initial value (initial state) of the memory element 92 is '0' (low resistance state).

[0201] 21 is a diagram showing an example of transition of the magnetization direction of the free layer 912 of the memory element 91 according to the eighth modification of the first embodiment of the present disclosure. Note that the memory element 92 has a configuration similar to that of the memory element 91, and therefore a description thereof will be omitted here.

[0202] 21, a storage element 91, which is an MTJ, stores information (for example, "0" or "1") according to the magnetization direction of a free layer 912. The magnetization direction of the free layer 912 transitions between a P state and an AP state according to the information to be stored.

[0203] The magnetization direction of the free layer 912 changes when a voltage is applied, in other words, when a current flows through the memory element 91. As shown in Fig. 21 , a larger current is required for the memory element 91 to change from the P state (low resistance state) to the AP state (high resistance state) than when the memory element 91 changes from the AP state (high resistance state) to the P state (low resistance state) (large current).

[0204] On the other hand, for the memory element 91 to transition from the AP state (high resistance state) to the P state (low resistance state), a smaller current is required (small current) than when transitioning from the P state (low resistance state) to the AP state (high resistance state).

[0205] Similarly, for the memory element 92 to transition from the P state (low resistance state) to the AP state (high resistance state), a larger current is required than when transitioning from the AP state (high resistance state) to the P state (low resistance state).

[0206] On the other hand, for the memory element 92 to transition from the AP state (high resistance state) to the P state (low resistance state), a smaller current (small current) is required than when transitioning from the P state (low resistance state) to the AP state (high resistance state).

[0207] In the above-described embodiment, the initial values ​​of the memory elements 91 and 92 can be '1' (high resistance state) or '0' (low resistance state) according to an instruction from the initialization unit 145. In this modification, the initial value of the memory element 91 is '1' (high resistance state), and the initial value of the memory element 92 is '0' (low resistance state). By fixing the initial values ​​of the memory elements 91 and 92 to constant values ​​in this way, the size of the initialization driver 12 can be made smaller than that of the initialization driver 15.

[0208] As described above, in this modification, the initial value of the memory element 91 is '1' (high resistance state). Therefore, for example, when the memory element 91 is in a low resistance state and the initialization driver 12 writes an initial value, the initialization driver 12 needs to pass a large current through the memory element 91.

[0209] On the other hand, the initial value of the memory element 92 is '0' (low resistance state). Therefore, for example, when the memory element 92 is in a high resistance state and the initialization driver 15 writes an initial value, the initialization driver 15 only needs to pass a small current through the memory element 92, and does not need to pass a large current.

[0210] In this way, the initialization driver 15 of the sensor circuit 10 drives the memory element 92 to put it into the '0' state (low resistance state), but does not drive it to put it into the '1' state (high resistance state). In other words, the initialization driver 12 only needs to drive the memory element 92 so as to pass a small current through it. Therefore, the circuit size of the initialization driver 12 can be made smaller than that of the initialization driver 15.

[0211] The configuration of the sensor circuit 10 according to this modified example is the same as that of the sensor circuit 10 according to the first embodiment (see Figures 3 and 4) except for the initial values ​​of the memory elements 91 and 92 and the circuit size of the initialization driver 12, and therefore will not be illustrated or described here.

[0212] Note that the circuit whose size can be reduced is not limited to initialization driver 12, which corresponds to second initialization circuit 1022 (see FIG. 3). In addition to initialization driver 12, the size of elements that sensor circuit 10 has for initializing memory element 92 (e.g., transistor 13, transistor 14, inverter 21, etc. in FIG. 4) and elements that sensor circuit 10 has for initializing memory element 91 (e.g., transistor 16, transistor 17, inverter 22, etc. in FIG. 4) can also be reduced.

[0213] Note that the second initialization circuit 1022 may include elements (for example, the transistor 13, the transistor 14, the inverter 21, and the like in FIG. 4) included in the sensor circuit 10 for initializing the memory element 92.

[0214] In this way, the sensor circuit 10 writes a predetermined initial value to the nonvolatile memory unit 20, and therefore it is possible to reduce the circuit size of the second initialization circuit 1022 that initializes the memory element 92 whose initial value is '0.' This allows the circuit size of the sensor circuit 10 to be reduced.

[0215] Although the circuit size of the second initialization circuit 1022 of the sensor circuit 10 is reduced here, the circuit size of the first initialization circuit 1021 may be reduced instead of the second initialization circuit 1022 .

[0216] For example, when the initial value of the storage element 91 is '0', the size of the initialization driver 15 for initializing the storage element 91 can be made smaller than that of the initialization driver 12 .

[0217] In addition to the initialization driver 15, the elements that the sensor circuit 10 has for initializing the memory element 91 (e.g., transistor 16, transistor 17, inverter 22, etc. in Figure 4) can also be made smaller in size compared to the elements that the sensor circuit 10 has for initializing the memory element 92 (e.g., transistor 13, transistor 14, inverter 21, etc. in Figure 4).

[0218] Note that the first initialization circuit 1021 may include elements (for example, the transistor 16, the transistor 17, the inverter 22, and the like in FIG. 4) included in the sensor circuit 10 for initializing the memory element 91.

[0219] As described above, the sensor circuit 10 according to this modification has different sizes for the first initialization circuit 1021 and the second initialization circuit 1022. In other words, the sensor circuit 10 has an asymmetric shape.

[0220] Here, the size of the circuit for initializing the memory element 91 or memory element 92 (hereinafter also referred to as the initialization circuit) of the sensor circuit 10 according to the first embodiment is reduced. However, the ability to reduce the size of the circuit for initializing the memory element 91 or memory element 92 is not limited to the sensor circuit 10. The size of the circuit for initializing the memory element 91 or memory element 92 can also be reduced in the sensor circuits 10A to 10F according to the second to seventh modifications described above.

[0221] <<2. Second embodiment>> The sensor unit 140 according to the first embodiment detects the inversion of the memory element 91 (or memory element 92) included in the sensor circuit 10, thereby detecting the temperature around the sensor circuit 10 and the exposure time for which the sensor circuit 10 is exposed to this temperature.

[0222] In this way, the sensor unit 140 only needs to detect the inversion of the storage element 91 (or storage element 92) of the sensor circuit 10, and the storage element 92 (or storage element 91) that does not detect the inversion may be omitted.

[0223] 22 is a block diagram showing an example configuration of a sensor circuit 10G according to a second embodiment of the present disclosure. Note that an information processing device 100 (not shown) according to the second embodiment is the same as the information processing device 100 in FIG. 1 except that it includes a sensor circuit 10G instead of the sensor circuit 10, and therefore description thereof will be omitted.

[0224] The sensor circuit 10G shown in FIG. 22 includes a nonvolatile element 1010 (an example of an element), an initialization circuit 1020 (an example of an initial setting unit), and a readout circuit 1030 (an example of a detection unit).

[0225] The sensor circuit 10G is the same as the sensor circuit 10 shown in FIG. 3 except that it includes one nonvolatile element 1010 and one initialization circuit 1020, and therefore the description thereof will be used.

[0226] 23 is a diagram showing a configuration example of a sensor circuit 10G according to the second embodiment of the present disclosure, which is a header-type SSR-NVFF circuit type sensor circuit 10G.

[0227] In FIG. 23, the same components as those in the sensor circuit 10 in FIG. 4 are denoted by the same reference numerals, and the description thereof will be used where appropriate.

[0228] The sensor circuit 10G of FIG. 22 differs from the sensor circuit 10 in that it does not include the memory element 92, the initialization driver 12, the transistor 13, the transistor 14, and the inverter 21.

[0229] The transistor 19 (an example of a resistance unit) is used to detect whether the state of the memory element 91 has been inverted from its initial value. The resistance value of the transistor 19 is determined according to the resistance values ​​of the memory element 91 (a first resistance value in a high resistance state and a second resistance value in a low resistance state).

[0230] More specifically, the resistance value R of the transistor 19 ＳＲ１ is the first resistance value R of the memory element 91 in the high resistance state Ｈ and the second resistance value R Ｌ or more (R Ｈ <R ＳＲ１ ≦R Ｌ ).

[0231] Resistance value R of transistor 19 ＳＲ１ The desired value can be achieved by, for example, adjusting (for example, reducing) the gate width W of the transistor 19 .

[0232] The resistance value R between the storage node N12 and the control line L11 ＮＬ is the first resistance value R of the memory element 91 in the high resistance state. Ｈ and the second resistance value R Ｌ As shown in FIG. 23, the resistance value R of the transistor 19 ＳＲ１The resistance R between the storage node N12 and the control line L11 is ＮＬ is R Ｈ <R ＮＬ ≦R Ｌ Alternatively, other elements (such as resistors not shown) may be used to set the resistance value R ＮＬ may be adjusted to a desired value.

[0233] As described above, according to the second embodiment, the sensor unit 140 can detect at least one of the temperature and the exposure time using the sensor circuit 10G that omits the memory element 92, the initialization driver 12, the transistors 13 and 14, the inverter 22, etc. This allows the circuit size of the sensor circuit 10G to be reduced, and the sensor unit 140 to be miniaturized.

[0234] Although the sensor circuit 10G in which the memory element 92 is omitted has been described above, the memory element 91 may be omitted instead of the memory element 92. A sensor circuit 10H in which the memory element 91 is omitted is shown in FIG.

[0235] 24 is a diagram showing a configuration example of a sensor circuit 10H according to the second embodiment of the present disclosure, which is a header-type SSR-NVFF circuit type sensor circuit 10H.

[0236] In FIG. 24, the same components as those in the sensor circuit 10 in FIG. 4 are denoted by the same reference numerals, and the description thereof will be used where appropriate.

[0237] The sensor circuit 10H in FIG. 24 differs from the sensor circuit 10 in that it does not include the memory element 91, the initialization driver 15, the transistor 16, the transistor 17, and the inverter 22.

[0238] The transistor 18 (an example of a resistor) is used to detect whether the state of the memory element 92 has been inverted from its initial value. The resistance value of the transistor 18 is determined according to the resistance values ​​of the memory element 92 (a first resistance value in a high resistance state and a second resistance value in a low resistance state).

[0239] More specifically, the resistance value R of the transistor 18 ＳＲ２ is the first resistance value R of the memory element 92 in the high resistance state Ｈand the second resistance value R Ｌ or more (R Ｈ <R ＳＲ２ ≦R Ｌ ).

[0240] Resistance value R of transistor 18 ＳＲ２ The desired value can be achieved by, for example, adjusting (for example, reducing) the gate width W of the transistor 18 .

[0241] The resistance R between the storage node N11 and the control line L11 Ｎ１Ｌ is the first resistance value R of the memory element 92 in the high resistance state. Ｈ and the second resistance value R Ｌ As shown in FIG. 24, the resistance value R of the transistor 18 ＳＲ２ The resistance R between the storage node N11 and the control line L11 is ＮＬ is R Ｈ <R Ｎ１Ｌ ≦R Ｌ Alternatively, other elements (such as resistors not shown) may be used to set the resistance value R Ｎ１Ｌ may be adjusted to a desired value.

[0242] As described above, even when the sensor circuit 10H is used, which omits the memory element 91, the initialization driver 15, the transistor 16, the transistor 17, and the inverter 22, it is possible to detect at least one of the temperature and the exposure time, similar to the sensor circuit 10G.

[0243] <<3. Summary>> Although the embodiments of the present disclosure have been described above, the technical scope of the present disclosure is not limited to the above-described embodiments, and various modifications are possible without departing from the gist of the present disclosure. Furthermore, components of the embodiments and modifications may be combined as appropriate.

[0244] Furthermore, the effects of each embodiment described in this specification are merely examples and are not intended to be limiting, and other effects may also be obtained.

[0245] The present disclosure may also be configured as follows: (1) A detection circuit comprising: an element whose characteristics change depending on temperature and the exposure time of the element; an initial setting unit that sets the initial state of the characteristic of the element to a first characteristic; and a detection unit that detects whether the characteristic of the element has changed from the first characteristic to a second characteristic. (2) The detection circuit described in (1), further comprising: a second element whose characteristics change depending on the temperature and the exposure time of the element; and a second initial setting unit that sets the initial state of the characteristic of the second element to the second characteristic. (3) The detection circuit described in (2), in which the initial setting unit and the second initial setting unit include elements of different sizes. (4) The detection circuit described in (3), in which the element included in the second initial setting unit is smaller than the element included in the initial setting unit. (5) The detection circuit described in any one of (2) to (4), in which the first characteristic of the element is a state in which the resistance value is higher than the second characteristic of the second element. (6) The detection circuit according to any one of (2) to (4), wherein the first characteristic of the element is a state in which the resistance value is lower than the second characteristic of the second element. (7) The detection circuit according to any one of (2) to (6), wherein the element and the second element are less likely to change from the first characteristic to the second characteristic than when they change from the second characteristic to the first characteristic. (8) The detection circuit according to (1), further comprising a resistor unit having a resistance value according to the first characteristic and the second characteristic. (9) The detection circuit according to (8), wherein the resistor unit includes a transistor having a resistance value according to the first characteristic and the second characteristic. (10) A sensor device comprising: an element whose characteristics change depending on temperature and exposure time exposed to the temperature; an initial setting unit that sets the initial state of the characteristic of the element to a first characteristic; a detection unit that detects whether the characteristic of the element has changed from the first characteristic to a second characteristic; and a determination unit that determines at least one of the temperature and the exposure time depending on the number of detection circuits in which the characteristic of the element has changed from the first characteristic to the second characteristic.

[0246] 10, 10A, 10B, 10C, 10D, 10E, 10F, 10G Sensor circuit 100 Information processing device 110 Communication unit 120 Memory unit 130 Control unit 140 Sensor unit 141 Sensor 142 Acquisition unit 143 Determination unit 144 Storage 145 Initialization unit 911 Fixed layer 912 Free layer 913 Barrier layer 1010 Nonvolatile element 1011 First nonvolatile element 1012 Second nonvolatile element 1020 Initialization circuit 1021 First initialization circuit 1022 Second initialization circuit 1030 Readout circuit

Claims

1. A detection circuit comprising: an element whose characteristics change depending on temperature and the exposure time of said temperature; an initial setting unit that sets the initial state of the characteristics of said element to a first characteristic; and a detection unit that detects whether the characteristics of said element have changed from the first characteristic to a second characteristic.

2. The detection circuit according to claim 1, further comprising: a second element whose characteristics change depending on the temperature and the exposure time of the second element; and a second initial setting unit that sets the initial state of the characteristics of the second element to the second characteristics.

3. The detection circuit according to claim 2, wherein the initial setting section and the second initial setting section include elements of different sizes.

4. The detection circuit according to claim 3, wherein the element included in the second initial setting unit is smaller than the element included in the first initial setting unit.

5. The detection circuit of claim 2, wherein the first characteristic of the element is a state in which the resistance is higher than the second characteristic of the second element.

6. The detection circuit of claim 2, wherein the first characteristic of the element is a state in which the resistance value is lower than the second characteristic of the second element.

7. The detection circuit of claim 2, wherein the element and the second element are less likely to change from the first characteristic to the second characteristic than they are to change from the second characteristic to the first characteristic.

8. The detection circuit according to claim 1, further comprising a resistor section having a resistance value according to said first characteristic and said second characteristic.

9. The detection circuit according to claim 8, wherein the resistor section includes a transistor having a resistance value according to the first characteristic and the second characteristic.

10. A sensor device comprising: an element whose characteristics change depending on temperature and the exposure time of exposure to said temperature; an initial setting unit that sets the initial state of the characteristic of said element to a first characteristic; a detection unit that detects whether the characteristic of said element has changed from the first characteristic to a second characteristic; and a plurality of detection circuits; and a determination unit that determines at least one of the temperature and the exposure time depending on the number of detection circuits in which the characteristic of said element has changed from the first characteristic to the second characteristic.

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