Multilayer ceramic capacitor

Abstract

Provided is a highly reliable multilayer ceramic capacitor that is capable of dispersing external stress applied to the multilayer ceramic capacitor while suppressing generation of squeaking generated therein, and that has a fixing force between an external electrode and bump portions and a fixing force between the bump portions and a mounting substrate on which the multilayer ceramic capacitor is mounted. A first bump portion (71) of the multilayer ceramic capacitor (1) comprises a first region (201), a second region (202), and a third region (203) interposed between the first region (201) and the second region (202). A second bump portion (72) comprises a fourth region (204), a fifth region (205), and a sixth region (206) interposed between the fourth region (204) and the fifth region (205). The porosity in the first region (201) and the second region (202) is lower than that in the third region (203), and the porosity in the fourth region (204) and the fifth region (205) is lower than that in the sixth region (206).

Description

Multilayer ceramic capacitors

[0001] The present invention relates to a multilayer ceramic capacitor.

[0002] When a voltage is applied between the external electrodes of a multilayer ceramic capacitor, dielectric polarization occurs where adjacent internal electrodes face each other. The capacitance caused by this dielectric polarization can be extracted through the external electrodes. The dielectric, which contributes to the formation of capacitance due to the opposing internal electrodes as described above, undergoes electric-field-induced distortion in response to the applied voltage. When a multilayer ceramic capacitor is surface-mounted on a substrate, this electric-field-induced distortion causes the multilayer ceramic capacitor to deform the substrate, generating a sound known as "ringing" depending on the frequency of this deformation. When this "ringing" becomes louder, it can cause noise problems.

[0003] In order to effectively reduce the above-mentioned problem of "squeak," for example, Patent Document 1 proposes a technology for forming bumps on the mounting surface of a multilayer ceramic capacitor. Fig. 13 is a diagram showing a conventional multilayer ceramic capacitor 501. Patent Document 1 proposes a multilayer ceramic capacitor 501 including a laminate 502 in which a plurality of ceramic layers 520 are stacked in the thickness direction, a plurality of first internal electrodes 511 and second internal electrodes 512 arranged in the laminate 502 so as to be alternately exposed on both end surfaces of the laminate 502 via the ceramic layers 520, a first external electrode 521 and a second external electrode 522 formed so as to cover both end portions of the laminate 502, and a first bump portion 531 and a second bump portion 532 formed on the mounting surface where the first external electrode 521 and the second external electrode 522 are exposed, respectively, as shown in Fig. 13.

[0004] Japanese Patent Application Laid-Open No. 2015-204451

[0005] However, the first bump portion 531 and the second bump portion 532 described in Patent Document 1 are formed by electroplating the mounting surface where the first external electrode 521 and the second external electrode 522 are exposed. Therefore, the first bump portion 531 and the second bump portion 532 are filled with metal, and have a dense structure.

[0006] As a result, when stress is applied to the first bump portion 531 and the second bump portion 532 due to an impact when mounting the multilayer ceramic capacitor 501 on the surface of the substrate during surface mounting or when stress is applied from the outside to the substrate on which the multilayer ceramic capacitor 501 is surface mounted, the stress may not be dispersed. As a result, there is a risk of cracks occurring in the first bump portion 531 and the second bump portion 532.

[0007] If a crack that has occurred in the first bump portion 531 and the second bump portion 532 reaches the internal electrode via the first external electrode 521 and the second external electrode 522, moisture may flow into the laminate 502 from the outside via the crack. This moisture may increase the incidence of short circuits. Furthermore, if the crack extends to the interface between the first bump portion 531 and the second bump portion 532 and the first external electrode 521 and the second external electrode 522, or to the interface between the first bump portion 531 and the second bump portion 532 and the mounting substrate, peeling that occurs cannot be suppressed, resulting in a problem of reduced reliability of the multilayer ceramic capacitor 501.

[0008] Therefore, an object of the present invention is to provide a highly reliable multilayer ceramic capacitor that can disperse external stress applied to the multilayer ceramic capacitor while suppressing the occurrence of acoustic noise in the multilayer ceramic capacitor, and that has sufficient adhesive strength between the external electrodes and the bump portions, and between the bump portions and a mounting substrate on which the multilayer ceramic capacitor is mounted.

[0009] The multilayer ceramic capacitor of the present invention is a multilayer ceramic capacitor comprising: a laminate including a plurality of laminated ceramic layers and a plurality of internal electrodes laminated on the ceramic layers, the laminate including first and second main surfaces opposing each other in a thickness direction, first and second side surfaces opposing each other in a width direction perpendicular to the thickness direction, and first and second end surfaces opposing each other in a length direction perpendicular to the thickness direction and the width direction; first external electrodes disposed on at least the first end surfaces and the first main surfaces of the laminate; second external electrodes disposed on at least the second end surfaces and the first main surfaces of the laminate; first bump portions connected to the first external electrodes; and second bump portions connected to the second external electrodes, wherein the first bump portions are surfaces located on the side of the first external electrodes. the second bump has a third bump main surface which is a surface located on the second external electrode side, and a fourth bump main surface which is opposite to the third bump main surface in the thickness direction T; the first bump has a first region having a gap on the first bump main surface side, a second region having a gap on the second bump main surface side, and a third region sandwiched between the first and second regions; the second bump has a fourth region having a gap on the third bump main surface side, a fifth region having a gap on the fourth bump main surface side, and a sixth region sandwiched between the fourth and fifth regions; the porosity in the first and second regions is lower than that in the third region, and the porosity in the fourth and fifth regions is lower than that in the sixth region.

[0010] According to the present invention, it is possible to provide a highly reliable multilayer ceramic capacitor that can disperse external stress applied to the multilayer ceramic capacitor while suppressing the occurrence of acoustic noise in the multilayer ceramic capacitor, and that has sufficient adhesive strength between the external electrodes and the bump portions, and between the bump portions and the mounting substrate on which the multilayer ceramic capacitor is mounted.

[0011] FIG. 1 is an external perspective view of a multilayer ceramic capacitor according to an embodiment of the present disclosure. FIG. 2 is a cross-sectional view taken along line 101-101 in FIG. 1 . FIG. 3 is a cross-sectional view taken along line 102-102 in FIG. 1 . FIG. 4 is a cross-sectional view taken along line 103-103 in FIG. 1 . FIG. 5A is a view corresponding to the cross-sectional view taken along line 101-101 in FIG. 1 , showing another configuration of a multilayer ceramic capacitor according to the present disclosure. FIG. 5B is a view corresponding to the cross-sectional view taken along line 101-101 in FIG. 1 , showing another configuration of a multilayer ceramic capacitor according to the present disclosure. FIG. 5C is a view corresponding to the cross-sectional view taken along line 101-101 in FIG. 1 , showing another configuration of a multilayer ceramic capacitor according to the present disclosure. FIG. 6 is an enlarged view of the box 160 in FIG. 2 . FIG. 7 is a view showing a schematic configuration of a sound pressure measuring device. FIG. 8 is a view showing an outline of a terminal electrode fixing strength test. FIG. 9 is a view showing an outline of a stress dispersion test. FIG. 10 is a view showing the results of Experimental Example 1. FIG. 11 is a view showing the results of Experimental Example 2. FIG. 12 is a view showing the results of Experimental Example 3. FIG. 13 is an external perspective view of a conventional multilayer ceramic capacitor.

[0012] (Multilayer Ceramic Capacitor) A multilayer ceramic capacitor 1 according to an embodiment of the present disclosure will be described with reference to the drawings. Fig. 1 is an external perspective view of a multilayer ceramic capacitor 1 according to an embodiment of the present disclosure.

[0013] As shown in Fig. 1, the multilayer ceramic capacitor 1 has a substantially rectangular parallelepiped shape. The multilayer ceramic capacitor 1 includes a laminate 2 having a substantially rectangular parallelepiped shape and a pair of external electrodes spaced apart from each other at both ends of the laminate 2. The external electrodes include a first external electrode 41 and a second external electrode 42, which will be described later. The multilayer ceramic capacitor 1 also includes a pair of bump portions. The bump portions include a first bump portion 71 and a second bump portion 72, which will be described later.

[0014] The arrow T in Fig. 1 indicates the thickness direction T of the multilayer ceramic capacitor 1 and the laminate 2. The arrow W indicates the width direction W of the multilayer ceramic capacitor 1 and the laminate 2. The width direction W is a direction perpendicular to the thickness direction T. The arrow L indicates the length direction L of the multilayer ceramic capacitor 1 and the laminate 2. The length direction L is a direction perpendicular to the thickness direction T and the width direction W. The thickness direction T, the width direction W, and the length direction L are perpendicular to one another. In figures other than Fig. 1, the arrows T, W, and L each indicate the same directions as those described above.

[0015] Of the pair of external electrodes, one external electrode is provided at one end of the laminate 2 in the length direction L, and the other external electrode is provided at the other end of the laminate 2 in the length direction L. One external electrode is referred to as a first external electrode 41. The other external electrode is referred to as a second external electrode 42.

[0016] (1) Laminate The laminate 2 will be described with reference to Figures 2, 3, and 4 in addition to Figure 1. Figure 2 is a cross-sectional view taken along line 101-101 of Figure 1. Figure 3 is a cross-sectional view taken along line 102-102 of Figure 1. Figure 4 is a cross-sectional view taken along line 103-103 of Figure 1. As shown in Figure 2, the laminate 2 includes a plurality of laminated ceramic layers 20 and a plurality of internal electrodes. The internal electrodes include a first internal electrode 31 and a second internal electrode 32, which will be described later.

[0017] The two surfaces of the laminate 2 facing each other in the thickness direction T are called the first main surface 3 and the second main surface 4. The two surfaces of the laminate 2 facing each other in the width direction W are called the first side surface 5 and the second side surface 6. The two surfaces of the laminate 2 facing each other in the length direction L are called the first end surface 7 and the second end surface 8.

[0018] The corners and ridges of the rectangular parallelepiped laminate 2 are preferably rounded. A corner is a portion where three faces of the laminate 2 intersect, and a ridge is a portion where two faces of the laminate 2 intersect. Concaves or the like may be formed on some or all of the main surface, side surface, and end surface.

[0019] (Ceramic Layers) The total number of ceramic layers 20 included in the laminate 2 is preferably 15 to 700. The total number refers to the sum of the number of ceramic layers 20 included in the effective layer portion 10 (described later) and the number of ceramic layers 20 included in the outer layer portion.

[0020] The ceramic material contained in the ceramic layer 20 is, for example, BaTiO ３ , CaTiO ３ , SrTiO ３ , CaZrO ３ Furthermore, ceramic materials containing these main components and additionally containing subcomponents such as Mn compounds, Fe compounds, Cr compounds, Co compounds, Ni compounds, and Mg compounds may also be used.

[0021] The multilayer ceramic capacitor 1 of this embodiment is an example of a multilayer ceramic electronic component. When a piezoelectric ceramic is used in the laminate, the multilayer ceramic electronic component functions as a ceramic piezoelectric element. Specific examples of piezoelectric ceramic materials include PZT (lead zirconate titanate) ceramic materials.

[0022] Furthermore, when a semiconducting ceramic is used in the laminate, the laminated ceramic electronic component functions as a thermistor element.Specific examples of semiconducting ceramic materials include spinel ceramic materials.

[0023] Furthermore, when magnetic ceramic is used for the laminate, the laminated ceramic electronic component functions as an inductor element.

[0024] When the ceramic material functions as an inductor element, the internal electrodes are coiled conductors.Specific examples of magnetic ceramic materials include ferrite ceramic materials.

[0025] The thickness of each ceramic layer 20 is preferably 0.3 μm or more and 10 μm or less.

[0026] There are no particular limitations on the dimensions of the laminate 2. For example, it is preferable that the dimension of the laminate 2 in the length direction L is 0.5 mm or more and 2.1 mm or less, the dimension of the laminate 2 in the width direction W is 0.2 mm or more and 1.2 mm or less, and the dimension of the laminate 2 in the thickness direction T is 0.2 mm or more and 1.2 mm or less.

[0027] (2) Internal Electrodes The internal electrodes will now be described. The internal electrodes include a plurality of first internal electrodes 31 and a plurality of second internal electrodes 32. The first internal electrodes 31 are internal electrodes exposed at the first end face 7. The second internal electrodes 32 are internal electrodes exposed at the second end face 8. Figure 3 shows the first internal electrodes 31.

[0028] The first internal electrode 31 has a first opposing portion 33 opposing the second internal electrode 32 and a first lead portion 35 extending from the first opposing portion 33 to the first end face 7. The second internal electrode 32 has a second opposing portion 34 opposing the first internal electrode 31 and a second lead portion 36 extending from the second opposing portion 34 to the second end face 8.

[0029] The shape of the first opposing portion 33 of the first internal electrode 31 is not particularly limited, but is preferably rectangular. However, the corners may be rounded or angled (tapered). Alternatively, the corners may be tapered, with an inclination in either direction.

[0030] Similarly, the shape of the second opposing portion 34 of the second internal electrode 32 is preferably rectangular, although not particularly limited thereto. However, the corners may be rounded or angled (tapered). Alternatively, the corners may be tapered, with an inclination in either direction.

[0031] The shape of the first lead portion 35 of the first internal electrode 31 is not particularly limited, but is preferably rectangular. However, the corners may be rounded or angled (tapered). Alternatively, the first lead portion 35 may be tapered, with a slope increasing in either direction.

[0032] Similarly, the shape of the second lead portion 36 of the second internal electrode 32 is preferably rectangular, although not particularly limited thereto. However, the corners may be rounded or angled (tapered). Alternatively, the second lead portion 36 may be tapered, with a slope increasing in either direction.

[0033] In the above description, the corner portion refers to a portion located at a corner of the outer shape of the internal electrode when the internal electrode is viewed in a cross section parallel to the length direction L and width direction W of the laminate 2.

[0034] The width in the width direction W of the first opposing portion 33 of the first internal electrode 31 and the width in the width direction W of the first lead portion 35 of the first internal electrode 31 may be the same, or one of the widths may be formed narrower. Similarly, the width in the width direction W of the second opposing portion 34 of the second internal electrode 32 and the width in the width direction W of the second lead portion 36 of the second internal electrode 32 may be the same, or one of the widths may be formed narrower.

[0035] The configuration of the multilayer ceramic capacitor 1 is not limited to the configuration shown in Figures 1 to 4. Figures 5A, 5B, and 5C are cross-sectional views taken along line 101-101 in Figure 1, showing other configurations of the multilayer ceramic capacitor 1 of the present disclosure. Figure 5A shows a multilayer ceramic capacitor 1 with a double structure. Figure 5B shows a multilayer ceramic capacitor 1 with a triple structure. Figure 5C shows a multilayer ceramic capacitor 1 with a quadruple structure.

[0036] A floating internal electrode that is not drawn out to either the first end face 7 or the second end face 8 may be provided for the first internal electrode 31 and the second internal electrode 32. By providing a floating internal electrode, the opposing portion may be divided into multiple parts.

[0037] The double-structure multilayer ceramic capacitor 1 shown in Fig. 5A includes, in addition to the first internal electrode 31 and the second internal electrode 32, a first floating internal electrode 351 that is not extended to either the first end face 7 or the second end face 8. The triple-structure multilayer ceramic capacitor 1 shown in Fig. 5B includes, as floating internal electrodes, a second floating internal electrode 353 and a third floating internal electrode 354. The quadruple-structure multilayer ceramic capacitor 1 shown in Fig. 5C includes, as floating internal electrodes, a fourth floating internal electrode 356, a fifth floating internal electrode 357, and a sixth floating internal electrode 358.

[0038] By providing floating internal electrodes in this manner, the multilayer ceramic capacitor 1 has a structure in which the opposing portions are divided into multiple sections. This results in multiple capacitor components being formed between the opposing internal electrodes. These capacitor components are then connected in series. This reduces the voltage applied to each capacitor component, thereby enabling the multilayer ceramic capacitor 1 to withstand a high voltage. It goes without saying that the multilayer ceramic capacitor 1 of this embodiment may have a multiple-connection structure of five or more capacitors.

[0039] The first internal electrode 31 and the second internal electrode 32 can be made of an appropriate conductive material, for example, a metal such as Ni, Cu, Ag, Pd, or Au, or an alloy containing at least one of these metals, such as an Ag-Pd alloy.

[0040] In the multilayer ceramic capacitor 1 of this embodiment, capacitance is formed by opposing portions of the internal electrodes facing each other via the ceramic layer 20. This allows the multilayer ceramic capacitor 1 to exhibit capacitor characteristics.

[0041] The thickness of each of the first internal electrode 31 and the second internal electrode 32 is preferably, for example, about 0.2 μm or more and 2.0 μm or less.

[0042] The total number of the first internal electrodes 31 and the second internal electrodes 32 is preferably 15 or more and 700 or less.

[0043] (Effective Layer Portion and Outer Layer Portion) The division of the laminate 2 will be described. First, the division in the thickness direction T of the laminate 2 will be described. As shown in Figures 2 and 4, the laminate 2 can be divided into an effective layer portion 10, a first outer layer portion 12, and a second outer layer portion 13 in the thickness direction T.

[0044] The effective layer portion 10 is the portion of the laminate 2 included between the position of the internal electrode closest to the first main surface 3 and the position of the internal electrode closest to the second main surface 4 in the thickness direction T.

[0045] The first outer layer portion 12 is a portion of the laminate 2 that is included between the first main surface 3 and the position of the internal electrode that is closest to the first main surface 3 in the thickness direction T. In other words, the first outer layer portion 12 is a part of the laminate 2 that is included between the effective layer portion 10 and the first main surface 3. The first outer layer portion 12 is located on the first main surface 3 side of the laminate 2, and is an assembly of multiple ceramic layers 20 that are located between the first main surface 3 and the position of the internal electrode that is closest to the first main surface 3.

[0046] The second outer layer portion 13 refers to a portion of the laminate 2 that is included between the second main surface 4 and the position of the internal electrode that is closest to the second main surface 4 in the thickness direction T. In other words, the second outer layer portion 13 is a part of the laminate 2 that is included between the effective layer portion 10 and the second main surface 4. The second outer layer portion 13 is located on the second main surface 4 side of the laminate 2, and is an assembly of multiple ceramic layers 20 that are located between the second main surface 4 and the position of the internal electrode that is closest to the second main surface 4.

[0047] As described above, the region sandwiched between the first outer layer portion 12 and the second outer layer portion 13 is the effective layer portion 10. In the effective layer portion 10, the internal electrodes face each other in the thickness direction T connecting the first main surface 3 and the second main surface 4. The first outer layer portion 12 and the second outer layer portion 13 are collectively referred to as the outer layer portion.

[0048] (Core Portion and Side Gap Portion) Next, the division of the laminate 2 in the width direction W will be described. As shown in FIGS. 3 and 4 , the laminate 2 can be divided into a core portion 25, a first side gap portion 15, and a second side gap portion 16 in the width direction W. The core portion 25 refers to the portion of the laminate 2 in which internal electrodes are provided in the width direction W. The first side gap portion 15 is the portion of the laminate 2 between the core portion 25 and the first side surface 5. The second side gap portion 16 is the portion of the laminate 2 between the core portion 25 and the second side surface 6. The first side gap portion 15 and the second side gap portion 16 do not have internal electrodes, and only have ceramic layers 20 provided therein. The first side gap portion 15 and the second side gap portion 16 are collectively referred to as the side gap portion. The side gap portion is also called a W gap.

[0049] (External Electrodes) The external electrodes include a first external electrode 41 and a second external electrode 42. The first external electrode 41 is connected to the first internal electrode 31 and is disposed on the first end face 7. The first external electrode 41 may also be disposed on a portion of the first main surface 3 and a portion of the second main surface 4, as well as a portion of the first side surface 5 and a portion of the second side surface 6. In this embodiment, the first external electrode 41 is formed to extend from the first end face 7 to a portion of the first main surface 3 and a portion of the second main surface 4, as well as a portion of the first side surface 5 and a portion of the second side surface 6.

[0050] The second external electrode 42 is connected to the second internal electrode 32 and is disposed on the second end face 8. The second external electrode 42 may also be disposed on a portion of the first main surface 3 and a portion of the second main surface 4, a portion of the first side surface 5 and a portion of the second side surface 6. In this embodiment, the second external electrode 42 is formed to extend from the second end face 8 to a portion of the first main surface 3 and a portion of the second main surface 4, a portion of the first side surface 5 and a portion of the second side surface 6.

[0051] The first external electrode 41 and the second external electrode 42 preferably have an underlying electrode layer and a plating layer. The underlying electrode layer included in the first external electrode 41 is referred to as a first underlying electrode layer 51, and the underlying electrode layer included in the second external electrode 42 is referred to as a second underlying electrode layer 52.

[0052] (Base Electrode Layer) The base electrode layer will be described below. The base electrode layer includes at least one selected from a baked layer, a conductive resin layer, a thin film layer, and the like.

[0053] (Baking Layer) First, a case where the base electrode layer is a baking layer will be described. The baking layer contains a glass component and a metal. The glass component of the baking layer contains at least one element selected from, for example, B, Si, Ba, Mg, Al, and Li. The metal of the baking layer contains at least one element selected from, for example, Cu, Ni, Ag, Pd, an Ag—Pd alloy, and Au.

[0054] The baked layer may be formed in multiple layers. The baked layer is formed by applying a conductive paste containing a glass component and a metal to the laminate and baking it. The baked layer may be co-fired with the internal electrodes and ceramic layers, or may be baked after the internal electrodes are baked. When the baked layer is co-fired with the internal electrodes and ceramic layers, it is preferable to form the baked layer by adding a dielectric material instead of the glass component.

[0055] At the center position in the thickness direction T connecting the first main surface 3 and the second main surface 4 of the baking layer located at the first end surface 7 and the second end surface 8, the thickness in the length direction L connecting the first end surface 7 and the second end surface 8 of the baking layer is preferably, for example, approximately 2 μm or more and 40 μm or less.

[0056] Furthermore, when a baked layer is provided as a base electrode layer on a portion of the first main surface 3 and a portion of the second main surface 4, as well as on a portion of the first side surface 5 and a portion of the second side surface 6, the thickness in the thickness direction T connecting the first main surface 3 and the second main surface 4 at the center of the length direction L connecting the first end surface 7 and the second end surface 8 of the base electrode layer located on the first main surface 3 and the second main surface 4, and the first side surface 5 and the second side surface 6, is preferably, for example, approximately 2 μm or more and 40 μm or less.

[0057] (Conductive Resin Layer) Next, a case where the base electrode layer is a conductive resin layer will be described. When the base electrode layer is a conductive resin layer, the conductive resin layer may be a multi-layer structure. Furthermore, the conductive resin layer may be disposed on the baked layer so as to cover the baked layer, or may be disposed directly on the laminate 2.

[0058] The conductive resin layer contains a thermosetting resin and a metal. Because the conductive resin layer contains a thermosetting resin, it is more flexible than a conductive layer made of, for example, a plating film or a fired conductive paste. Therefore, even when the ceramic electronic component is subjected to a physical impact or an impact due to a thermal cycle, the conductive resin layer functions as a buffer layer. As a result, the occurrence of cracks in the ceramic electronic component can be suppressed.

[0059] Examples of metals contained in the conductive resin layer include Ag, Cu, Ni, Sn, Bi, and alloys containing these. Alternatively, metal powders whose surfaces are coated with Ag can be used. When using Ag-coated metal powders, it is preferable to use Cu, Ni, Sn, Bi, or alloy powders thereof as the metal powder.

[0060] The reason for using Ag conductive metal powder as the conductive metal is that Ag has the lowest resistivity of all metals, making it suitable as an electrode material, and Ag is a noble metal, so it does not oxidize and has high resistance.The reason for using metal powder with an Ag coating on the surface is that it allows the base metal to be made inexpensive while maintaining the above-mentioned properties of Ag.

[0061] Furthermore, the metal contained in the conductive resin layer may be Cu or Ni that has been subjected to an anti-oxidation treatment.

[0062] The metal contained in the conductive resin layer may be a metal powder whose surface is coated with Sn, Ni, or Cu. When using a metal powder whose surface is coated with Sn, N, or Cu, it is preferable to use Ag, Cu, Ni, Sn, Bi, or an alloy powder thereof as the metal powder.

[0063] The preferred amount of metal contained in the conductive resin layer is 35 vol % or more and 75 vol % or less with respect to the volume of the entire conductive resin.

[0064] The shape of the metal contained in the conductive resin layer, i.e., the conductive filler, is not particularly limited. The shape of the conductive filler may be spherical, flat, or the like. Furthermore, the average particle size of the metal contained in the conductive resin layer is not particularly limited. The average particle size of the conductive filler may be, for example, about 0.3 μm or more and 10 μm or less.

[0065] The metal contained in the conductive resin layer is mainly responsible for the electrical conductivity of the conductive resin layer. Specifically, contact between conductive fillers forms an electrical path inside the conductive resin layer. The metal contained in the conductive resin layer can be spherical, flat, or the like. However, it is preferable to use a mixture of spherical metal powder and flat metal powder.

[0066] The resin contained in the conductive resin layer may be any of various known thermosetting resins, such as epoxy resin, phenoxy resin, phenol resin, urethane resin, silicone resin, polyimide resin, etc. Among these, epoxy resin is one of the most suitable resins, as it has excellent heat resistance, moisture resistance, and adhesiveness.

[0067] The amount of resin contained in the conductive resin layer is preferably 25 vol % or more and 65 vol % or less with respect to the total volume of the conductive resin.

[0068] The conductive resin layer preferably contains a curing agent together with the thermosetting resin. When an epoxy resin is used as the base resin, various known compounds such as phenol-based, amine-based, acid anhydride-based, imidazole-based, active ester-based, and amide-imide-based compounds can be used as the curing agent.

[0069] The thickness of the conductive resin layer located at the center in the thickness direction T of the laminate 2, which is located at the first end face 7 and the second end face 8, is preferably, for example, about 2 μm or more and 40 μm or less. Furthermore, when conductive resin layers are also provided on the first main surface 3 and the second main surface 4 and the first side surface 5 and the second side surface 6, the thickness of the conductive resin layer located at the center in the length direction L of the conductive resin layer located at the first main surface 3 and the second main surface 4 and the first side surface 5 and the second side surface 6 is preferably, for example, about 2 μm or more and 40 μm or less.

[0070] (Thin Film Layer) Next, a case where the base electrode layer is a thin film layer will be described. The thin film layer can be formed by a thin film formation method such as sputtering or vapor deposition, and can be a layer of 1 μm or less in thickness where metal particles are deposited.

[0071] (Plating Layer) Next, the plating layer will be described. The plating layer includes a first plating layer and a second plating layer. The first plating layer is a plating layer included in the first external electrode 41. The second plating layer is a plating layer included in the second external electrode 42.

[0072] The plating layer may be formed of multiple layers. In this embodiment, the first plating layer and the second plating layer each include two plating layers. When the plating layer has a two-layer structure, preferably, one layer is a Ni plating layer and the other layer is a Sn plating layer. In this embodiment, each plating layer includes a Ni plating layer and a Sn plating layer.

[0073] The Ni plating layer included in the first plating layer is the first Ni plating layer 63, and the Ni plating layer included in the second plating layer is the second Ni plating layer 64. The Sn plating layer included in the first plating layer is the first Sn plating layer 65, and the Sn plating layer included in the second plating layer is the second Sn plating layer 66.

[0074] The first Ni plating layer 63 is disposed so as to cover the first base electrode layer 51. The second Ni plating layer 64 is disposed so as to cover the second base electrode layer 52. The first Sn plating layer 65 is disposed so as to cover the first Ni plating layer 63. The second Sn plating layer 66 is disposed so as to cover the second Ni plating layer 64.

[0075] The Ni plating layer can prevent the base electrode layer from being eroded by solder when mounting the ceramic electronic component. The Sn plating layer improves the wettability of the solder when mounting the ceramic electronic component, allowing for easier mounting. Therefore, it is preferable that the plating layers be Ni plating layer and Sn plating layer in order from the plating layer in contact with the base electrode layer. Note that the number of plating layers may be three or more, and the plating layers may be mainly composed of metal species other than Ni and Sn.

[0076] The material constituting the plating layer is not limited to the above examples, and may include at least one selected from the group consisting of Cu, Ni, Sn, Ag, Pd, an Ag—Pd alloy, and Au.

[0077] The thickness of each plating layer is preferably 2 μm or more and 15 μm or less.

[0078] (When no base electrode layer is provided) The external electrodes may be formed using only plating layers, without providing a base electrode layer. A structure in which only plating layers are provided without providing a base electrode layer will be described below. The first external electrode 41 and the second external electrode 42 may each have a plating layer formed directly on the surface of the laminate, without providing a base electrode layer. That is, the multilayer ceramic capacitor 1 may have a structure including a plating layer that is directly and electrically connected to the first internal electrode or the second internal electrode. When the external electrodes have such a structure, a catalyst may be disposed on the surface of the laminate as a pretreatment before plating, and then the plating layer may be formed.

[0079] The plating layer preferably includes a lower-layer plating electrode formed on the surface of the laminate and an upper-layer plating electrode formed on the surface of the lower-layer plating electrode. The lower-layer plating electrode and the upper-layer plating electrode each preferably include at least one metal selected from, for example, Cu, Ni, Sn, Pb, Au, Ag, Pd, Bi, and Zn, or an alloy containing such a metal. The lower-layer plating electrode is preferably formed using Ni, which has solder barrier properties. The upper-layer plating electrode is preferably formed using Sn or Au, which have good solder wettability.

[0080] Furthermore, for example, when the first internal electrode and the second internal electrode are formed using Ni, it is preferable that the lower-layer plated electrode be formed using Cu, which has good bonding properties with Ni. Note that the upper-layer plated electrode may be formed as needed, and the first external electrode 41 and the second external electrode 42 may each be composed of only the lower-layer plated electrode. The upper-layer plated electrode may be the outermost layer of the plating layer, or another plated electrode may be formed on the surface of the upper-layer plated electrode.

[0081] The thickness of each plating layer disposed without a base electrode layer is preferably 1 μm or more and 15 μm or less. The plating layer preferably does not contain glass. The metal content per unit volume of the plating layer is preferably 99% by volume or more.

[0082] (Bump portion) The bump portion will be described. The multilayer ceramic capacitor 1 of this embodiment includes a bump portion. As shown in FIGS. 1 and 2 , the bump portion includes a first bump portion 71 and a second bump portion 72. The first bump portion 71 is disposed on at least a portion of the first external electrode 41 that is disposed on the first main surface 3 (mounting surface). The second bump portion 72 is disposed on at least a portion of the second external electrode 42 that is disposed on the first main surface 3. The first bump portion 71 and the second bump portion 72 may extend to other surfaces of the laminate 2.

[0083] The first bump portion 71 and the second bump portion 72 are primarily composed of an intermetallic compound containing at least one high-melting-point metal selected from Cu and Ni and Sn as a low-melting-point metal. The intermetallic compound is preferably an intermetallic compound formed by the reaction of Sn with a Cu-Ni alloy. Such an intermetallic compound has the advantages of a fast reaction rate and minimal change in shape during its formation. Ag may also be included as a high-melting-point metal constituting the intermetallic compound.

[0084] (Dimensions of Bump Portions) The first bump portion 71 and the second bump portion 72 have a predetermined dimension in the thickness direction T on the mounting surface, measured in a direction perpendicular to the mounting surface. To more reliably exert the effect of reducing "squeak," the dimension in the thickness direction T of each of the first bump portion 71 and the second bump portion 72 is preferably 100 μm or more and 1200 μm or less. Furthermore, the dimension in the width direction W of each of the first bump portion 71 and the second bump portion 72 is preferably 100 μm or more and 1200 μm or less. Furthermore, the dimension in the length direction L of each of the first bump portion 71 and the second bump portion 72 is preferably 100 μm or more and 700 μm or less.

[0085] By making the dimensions of the first bump portion 71 and the second bump portion 72 in the thickness direction T 100 μm or more, the dimensions in the width direction W 100 μm or more, and the dimensions in the length direction L 100 μm or more, it is possible to prevent the solder from wetting up between the end faces when the multilayer ceramic capacitor 1 is mounted on a mounting board, thereby making it possible to suppress squeal.

[0086] By making the dimensions of the first bump portion 71 and the second bump portion 72 in the thickness direction T 1200 μm or less, the dimensions in the width direction W 1200 μm or less, and the dimensions in the length direction L 700 μm or less, it becomes possible to ensure stability when the multilayer ceramic capacitor 1 is mounted on a mounting substrate, and it becomes possible to mount the multilayer ceramic capacitor 1 stably on the mounting substrate.

[0087] On the other hand, if the dimensions of the first bump portion 71 and the second bump portion 72 in the thickness direction T are less than 100 μm, the dimensions in the width direction W are less than 100 μm, and the dimensions in the length direction L are less than 100 μm, it may not be possible to sufficiently prevent the solder from wetting up between the end faces when the multilayer ceramic capacitor 1 is mounted on a mounting board, and noise may not be sufficiently suppressed.

[0088] Furthermore, if the dimension in the thickness direction T of the first bump portion 71 and the second bump portion 72 exceeds 1200 μm, if the dimension in the width direction W exceeds 1200 μm, or if the dimension in the length direction L exceeds 700 μm, the thickness of the first bump portion 71 and the second bump portion 72 will be too large, and it may not be possible to sufficiently ensure stability when the multilayer ceramic capacitor 1 is mounted on a mounting substrate, and it may not be possible to sufficiently mount the capacitor on the mounting substrate.

[0089] 2 , the first bump portion 71 is connected to the first external electrode 41, and the second bump portion 72 is connected to the second external electrode 42. Specifically, the first bump portion 71 has a portion that contacts the first external electrode 41, and is further positioned in the length direction L of the laminate 2 so as to cover the first main surface 3 of the laminate 2. Note that the first bump portion 71 positioned in the length direction L of the laminate 2 may or may not contact the laminate 2.

[0090] The second bump portion 72 has a portion that contacts the second external electrode 42, and is located in the length direction L of the laminate 2 so as to cover the first main surface 3 of the laminate 2. The second bump portion 72 located in the length direction L of the laminate 2 may or may not contact the laminate 2.

[0091] Therefore, when the multilayer ceramic capacitor 1 is viewed in the thickness direction T, the first bump portion 71 is arranged so as to extend from a portion of the first external electrode 41 to a portion of the first main surface 3 of the laminate 2. Moreover, the second bump portion 72 is arranged so as to extend from a portion of the second external electrode 42 to a portion of the first main surface 3 of the laminate 2. By arranging the first bump portion 71 and the second bump portion 72 in this manner, it is possible to further improve the acoustic noise suppression effect while ensuring stability when the multilayer ceramic capacitor 1 is mounted on a mounting board.

[0092] (Bump portion main surface) The bump portion main surface will now be described. As shown in Fig. 2, the first bump portion 71 has a first bump portion main surface 81 which is the surface located on the first external electrode 41 side, and a second bump portion main surface 82 which faces the first bump portion main surface 81 in the thickness direction T. The first bump portion main surface 81 is the surface located on the first external electrode 41 side, and is also the surface located on the first main surface 3 side.

[0093] The same applies to the second bump portion 72. The second bump portion 72 has a third bump portion main surface 83 which is the surface located on the second external electrode 42 side, and a fourth bump portion main surface 84 which faces the third bump portion main surface 83 in the thickness direction T. The third bump portion main surface 83 is the surface located on the second external electrode 42 side, and is also the surface located on the first main surface 3 side.

[0094] (External electrode connection surface) The external electrode connection surface will now be described. The external electrode connection surface is the surface of the external electrode that connects to the bump portion. The external electrode connection surface includes a first external electrode connection surface 74 and a second external electrode connection surface 75. The first external electrode connection surface 74 is the surface of the first external electrode 41 that contacts the first bump portion 71 and is parallel to the first main surface 3. Similarly, the second external electrode connection surface 75 is the surface of the second external electrode 42 that contacts the second bump portion 72 and is parallel to the first main surface 3.

[0095] The first bump portion main surface 81 may be in contact with only the first external electrode connecting surface 74, or may be in contact with the first external electrode connecting surface 74 and the first main surface 3. Similarly, the third bump portion main surface 83 may be in contact with only the second external electrode connecting surface 75, or may be in contact with the second external electrode connecting surface 75 and the first main surface 3.

[0096] 2, the division of the first bump portion 71 will be described. The first bump portion 71 has a first region 201 having a gap on the first bump portion main surface 81 side, a second region 202 having a gap on the second bump portion main surface 82 side, and a third region 203 sandwiched between the first region 201 and the second region 202.

[0097] The same applies to the second bump portion 72. The second bump portion 72 has a fourth region 204 having a gap on the third bump portion main surface 83 side, a fifth region 205 having a gap on the fourth bump portion main surface 84 side, and a sixth region 206 sandwiched between the fourth region 204 and the fifth region 205.

[0098] The following describes the characteristics of the bump portion, mainly using the first bump portion 71 as an example. The matters described for the first bump portion 71 also apply to the second bump portion 72. The first region 201, second region 202, and third region 203 of the first bump portion 71 correspond to the fourth region 204, fifth region 205, and sixth region 206 of the second bump portion 72, respectively.

[0099] (First Bump Portion) The first bump portion 71 will be described with reference to Fig. 6 in addition to Fig. 2. Fig. 6 is an enlarged view of the enclosed area 160 in Fig. 2. Fig. 6 shows a cross section of the first bump portion 71 in a plane parallel to the length direction L and the thickness direction T.

[0100] The first bump portion 71 includes a void 90. The void 90 is not shown in FIG. 2 but is shown in FIG. 6. The void 90 in the first bump portion 71 can absorb solder when mounting the multilayer ceramic capacitor 1. It is known that when the solder height is high, noise is more likely to occur. By having the void 90 in the first bump portion 71 absorb the solder, the solder height can be reduced, and noise can be reduced.

[0101] (Porosity) The porosity of the first region 201 is lower than that of the third region 203. Therefore, the first region 201 contains more metal than the third region 203. Therefore, the connection area of ​​the first region 201 that contacts the first external electrode 41 increases, making it easier for the first region 201 to be firmly connected to the external electrode and the laminate 2. As a result, it becomes possible to ensure that the first bump portion 71 has a strong adhesive force to the first external electrode 41.

[0102] The porosity of the second region 202 is lower than that of the third region 203. Therefore, the second region 202 contains more metal than the third region 203. This increases the connection area of ​​the second region 202 that contacts the mounting substrate, making it easier to firmly connect the mounting substrate and the second region 202. As a result, it becomes possible to ensure that the first bump portion 71 has sufficient adhesive strength to the mounting substrate.

[0103] The porosity of the third region 203 is higher than the porosity of the first region 201 and the second region 202. Therefore, the voids 90 in the third region 203 can disperse external stress that is not dispersed by the first region 201 and the second region 202. By dispersing stress through the voids 90 in the third region 203, it is possible to prevent cracks from reaching the internal electrodes via the external electrodes. This can prevent an increase in the incidence of short circuits due to moisture entering from the outside via cracks, and can also prevent peeling caused by cracks extending to the interfaces between the first bump portion 71 and the second bump portion 72 and the first external electrode 41 and the second external electrode 42, or to the interfaces between the first bump portion 71 and the second bump portion 72 and the mounting substrate. As a result, the risk of the first bump portion 71 and the second bump portion 72 peeling off from the first external electrode 41 and the second external electrode 42 or the mounting substrate is reduced.

[0104] Such a structure of the first bump portion 71 makes it possible to disperse external stress applied to the multilayer ceramic capacitor 1 while suppressing the occurrence of acoustic noise in the multilayer ceramic capacitor 1. It also makes it possible to realize a multilayer ceramic capacitor 1 that has sufficient adhesive strength between the first external electrode 41 and the first bump portion 71, and between the first bump portion 71 and a mounting substrate on which the multilayer ceramic capacitor 1 is mounted.

[0105] On the other hand, when the porosity of the first region 201 and the second region 202 is the same as or higher than that of the third region 203, the first region 201 and the second region 202 contain less metal than the third region 203. This reduces the connection area of ​​the first region 201 that contacts the first external electrode 41 and the laminate 2, and the connection area of ​​the second region 202 that contacts the mounting substrate. This makes it difficult for the first region 201 and the second region 202 to be firmly connected to the first external electrode 41 and the mounting substrate, and there is a possibility that sufficient bonding strength cannot be ensured.

[0106] If sufficient adhesive strength cannot be ensured, there is a risk that the first bump portion 71 will peel off from the first external electrode 41 and the mounting substrate due to external stress generated by an external impact when mounting the multilayer ceramic capacitor 1 on the mounting substrate, or external stress generated by external stress being applied to the substrate on which the multilayer ceramic capacitor 1 is mounted. As a result, even if a voltage is applied to the multilayer ceramic capacitor 1 from the outside, the voltage that should be applied may not be sufficient, and the multilayer ceramic capacitor 1 may not function properly.

[0107] Even if the porosity of either the first region 201 or the second region 202 is higher than that of the third region 203, one of the above defects may occur, and therefore the first bump portion 71 may peel off from the first external electrode 41 and the mounting substrate. As a result, even if a voltage is applied to the multilayer ceramic capacitor 1 from the outside, the voltage that should be applied may not be sufficient, and the multilayer ceramic capacitor 1 may not function properly.

[0108] The size of the voids 90 is not particularly limited. However, it is preferable that the circle-equivalent diameter D50 of the voids 90 in a cross section parallel to the length direction L and the thickness direction T is 5 μm or more and 50 μm or less. This makes it possible to more reliably achieve the above-mentioned adhesive force and stress dispersion function.

[0109] (Range of Regions) The length of each region in the thickness direction T will be described with reference to FIG. 6 . Note that the lengths shown in FIG. 6 do not accurately reflect the actual lengths. Line 121 shown in FIG. 6 indicates the first external electrode connecting surface 74. Line 121 corresponds to the portion of the first bump portion main surface 81 that contacts the first external electrode connecting surface 74. Line 124 indicates the second bump portion main surface 82. Line 122 indicates the boundary between the first region 201 and the third region 203. Line 123 indicates the boundary between the second region 202 and the third region 203.

[0110] The first region 201 can be a region extending from the first bump portion main surface 81 to a range extending 10% inward toward the second bump portion main surface 82. Specifically, by forming the first region 201 in the range extending 10% inward toward the second bump portion main surface 82 from the portion of the first bump portion main surface 81 that contacts the first external electrode connecting surface 74, it is possible to ensure the adhesive strength with the first external electrode 41. In other words, the length 141 can be set to 10% of the length 145.

[0111] Second region 202 can be an area extending 10% from second bump portion main surface 82 toward first bump portion main surface 81. More specifically, by forming second region 202 in an area extending 10% from second bump portion main surface 82 toward the portion of first bump portion main surface 81 that contacts first external electrode connecting surface 74, it is possible to ensure adhesive strength to the mounting substrate. In other words, length 143 can be set to 10% of length 145.

[0112] The third region 203 is a region of the first bump portion 71 other than the first region 201 and the second region 202. The length 142 is the value obtained by subtracting the lengths 141 and 143 from the length 145.

[0113] Furthermore, it is more preferable that the porosity of the first region 201 and the second region 202 is 0.5% or more and 18% or less. When the porosity of the first region 201 is 0.5% or more and 18% or less, the first region 201 contains a larger amount of metal. This increases the connection area of ​​the first region 201 that contacts the first external electrode 41, making it easier for the first region 201 to be more firmly connected to the external electrode and the laminate. As a result, it is possible to ensure a stronger adhesive force between the first bump portion 71 and the first external electrode 41.

[0114] Furthermore, since the porosity of the second region 202 is 0.5% or more and 18% or less, the second region 202 contains a larger amount of metal. This increases the connection area of ​​the second region 202 that contacts the mounting substrate, making it easier for the second region 202 to be more firmly connected to the mounting substrate. As a result, it becomes possible to ensure a stronger adhesive force of the first bump portion 71 to the mounting substrate.

[0115] The porosity of the third region 203 is more preferably 5% or more and 25% or less. By setting the porosity of the third region 203 to 5% or more and 25% or less, the voids in the third region 203 more effectively disperse external stress. This effectively prevents cracks from reaching the internal electrodes via the external electrodes. As a result, it is possible to effectively prevent an increase in the incidence of short circuits caused by moisture entering from the outside via cracks, and to prevent peeling caused by cracks extending to the interfaces between the first bump portion 71 and the second bump portion 72 and the first external electrode 41 and the second external electrode 42, and / or the interfaces between the first bump portion 71 and the second bump portion 72 and the mounting substrate. This reduces the risk of the first bump portion 71 and the second bump portion 72 peeling off from the first external electrode 41 and the second external electrode 42 or the mounting substrate.

[0116] To be more specific, even if the external stress applied from the first bump portion main surface 81 or the second bump portion main surface 82 reaches the third region 203 without being sufficiently dispersed by the porosity of the first region 201 or the second region 202, the voids in the third region 203 make it possible to further disperse the external stress.

[0117] Such a structure of the first bump portion 71 makes it possible to disperse external stress applied to the multilayer ceramic capacitor 1 while suppressing the occurrence of acoustic noise in the multilayer ceramic capacitor 1. As a result, it is possible to realize a multilayer ceramic capacitor 1 that has a stronger adhesive strength between the first external electrode 41 and the first bump portion 71, and a stronger adhesive strength between the first bump portion 71 and the mounting substrate on which the multilayer ceramic capacitor 1 is mounted.

[0118] On the other hand, when the porosity of the first region 201 is less than 0.5%, the first region 201 has a dense structure containing a large amount of metal. Therefore, the connection area of ​​the first region 201 that contacts the first external electrode 41 increases, and the first region 201 is more likely to be connected firmly to the external electrode and the laminate. As a result, the first bump portion 71 can be more firmly fixed to the first external electrode 41.

[0119] However, because the first region 201 has a dense structure containing a large amount of metal, the stress dispersion effect of the voids 90 in the first region 201 may be insufficient when external stress is applied. In such a case, even if the porosity of the third region 203 is 5% or more and 25% or less, the stress may not be sufficiently dispersed. As a result, if a crack occurs in the first bump portion 71 and extends to the interface with the first external electrode 41, there is a risk that the first bump portion 71 will peel off from the first external electrode 41.

[0120] Furthermore, when the porosity of the second region 202 is less than 0.5%, the second region 202 has a dense structure containing a large amount of metal. This increases the contact area of ​​the second region 202 that contacts the mounting substrate, making it easier to firmly connect the mounting substrate and the second region 202. As a result, it becomes possible to ensure sufficient adhesion of the first bump portion 71 to the mounting substrate.

[0121] However, because the second region 202 has a dense structure containing a large amount of metal, when external stress is applied, the stress dispersion effect of the voids 90 in the second region 202 may be insufficient. In such a case, even if the porosity of the third region 203 is 5% or more and 25% or less, the stress may not be sufficiently dispersed. As a result, if a crack occurs in the first bump portion 71 and the crack extends to the interface with the first external electrode 41, there is a risk of peeling off from the first external electrode 41.

[0122] When the porosity of the first region 201 exceeds 18%, the first region 201 contains less metal and has a structure with many voids 90. As a result, the connection area of ​​the first region 201 in contact with the first external electrode 41 is reduced, making it difficult for the first region 201 to be firmly connected to the first external electrode 41, and there is a possibility that the adhesive strength of the first region 201 to the first external electrode 41 will be reduced. If the adhesive strength of the first region 201 to the first external electrode 41 and the adhesive strength of the second region 202 to the mounting substrate of the multilayer ceramic capacitor 1 are reduced, cracks caused by external stress generated by an external impact when mounting the multilayer ceramic capacitor 1 on the mounting substrate or external stress generated by external stress applied to the substrate on which the multilayer ceramic capacitor 1 is mounted may extend to the interface between the first region 201 and the first external electrode 41, and the first bump portion 71 may peel off from the first external electrode 41. As a result, even if a voltage is applied to the multilayer ceramic capacitor 1 from the outside, the voltage that should be applied may not be sufficient, and the multilayer ceramic capacitor 1 may not function properly.

[0123] When the porosity of the second region 202 exceeds 18%, the second region 202 contains less metal and has a structure with many voids 90. As a result, the connection area of ​​the second region 202 in contact with the mounting substrate is reduced, making it difficult for the second region 202 to be firmly connected to the mounting substrate, which may result in a weakened adhesive strength of the second region 202 to the mounting substrate. If the adhesive strength of the second region 202 to the mounting substrate of the multilayer ceramic capacitor 1 is weakened, cracks caused by external stresses, such as those generated by external impacts when mounting the multilayer ceramic capacitor 1 on the mounting substrate, or external stresses applied to the substrate on which the multilayer ceramic capacitor 1 is mounted, may extend to the interface between the second region 202 and the mounting substrate, potentially causing the first bump portion 71 to peel off from the mounting substrate. As a result, even if a voltage is applied to the multilayer ceramic capacitor 1 from the outside, the voltage that should be applied may not be sufficient, potentially causing the multilayer ceramic capacitor 1 to malfunction.

[0124] When the porosity of the third region 203 is less than 5%, the third region 203 has a dense structure containing a large amount of metal. Therefore, when external stress generated by an external impact when mounting the multilayer ceramic capacitor 1 on a mounting substrate or external stress generated by external stress applied to the substrate on which the multilayer ceramic capacitor 1 is mounted is applied to the third region 203 through the first region 201 and the second region 202, the external stress may not be sufficiently dispersed. As a result, it becomes difficult to prevent cracks from reaching the internal electrodes via the external electrodes, increase the incidence of short circuits due to moisture entering from the outside via the cracks, and prevent peeling caused by cracks extending to the interfaces between the first bump portion 71 and the second bump portion 72 and the first external electrode 41 and the second external electrode 42, or to the interfaces between the first bump portion 71 and the second bump portion 72 and the mounting substrate.

[0125] When the porosity of the third region 203 exceeds 25%, the third region 203 has a structure in which the metal content is small and the voids are large. Therefore, when an external stress generated by an external impact when mounting the multilayer ceramic capacitor 1 on a mounting substrate or an external stress generated by the application of an external stress to the substrate on which the multilayer ceramic capacitor 1 is mounted passes through the first region 201 and the second region 202 and is applied to the third region 203, the external stress can be sufficiently dispersed.

[0126] However, if there are many voids in the third region 203, the adhesive strength between the first region 201 and the second region 202 will be reduced, causing the first region 201 and the second region 202 to peel off from the third region 203, resulting in insufficient formation of the first bump portion 71, and there is a risk that the desired first bump portion 71 will not be obtained.

[0127] (Seventh and Eighth Regions, Ninth and Tenth Regions) The third region 203 has a seventh region 207 arranged on the first end face 7 side of the multilayer ceramic capacitor 1, and an eighth region 208 extending from the seventh region 207 toward the second end face 8 side. Similarly, the sixth region 206 has a ninth region 209 arranged on the second end face 8 side of the multilayer ceramic capacitor 1, and a tenth region 210 extending from the ninth region 209 toward the first end face 7 side.

[0128] The following description will mainly focus on the seventh and eighth regions. The matters described for the seventh region also apply to the ninth region. The matters described for the eighth region also apply to the tenth region.

[0129] The seventh region 207 can be a region closer to the first external electrode 41 than the center of the third region 203 in the length direction L, and the eighth region 208 can be a region closer to the second external electrode 42 than the center of the third region 203 in the length direction L. In other words, the seventh region 207 is a region located closer to the first external electrode 41 than a half position in the length direction L of the first bump portion 71, and the eighth region 208 is a region located closer to the second external electrode 42 than a half position in the length direction L of the first bump portion 71.

[0130] The porosity of the seventh region 207 is preferably higher than that of the eighth region 208. Furthermore, the porosity of the seventh region 207 is more preferably 10% or more and 25% or less.

[0131] Since the porosity of the seventh region 207 is 10% or more and 25% or less, if an external stress is applied to the seventh region 207 from the first bump portion main surface 81 side due to an external impact when mounting the multilayer ceramic capacitor 1 on a mounting substrate, the external stress may be applied to the seventh region 207, including the thickness of the first external electrode 41. However, since the porosity of the seventh region 207 is higher than the porosity of the eighth region 208, the voids in the seventh region 207 can further disperse the external stress. Furthermore, since the porosity of the seventh region 207 is 10% or more and 25% or less, the connection area between the first region 201 and the second region 202 is increased, making it possible to ensure adhesive strength.

[0132] Therefore, even if the external stress applied from the first bump portion main surface 81 reaches the seventh region 207 without being sufficiently dispersed by the porosity of the first region 201, the porosity of the seventh region 207 is higher than that of the eighth region 208, so the applied external stress can be dispersed, including the thickness of the first external electrode 41, and a balance in the adhesive force between the first region 201 and the second region 202 can be ensured.

[0133] As a result, it is possible to obtain the desired first bump portion 71 and second bump portion 72. This reduces the possibility that cracks will extend to the interfaces between the first bump portion 71 and the second bump portion 72 and the first external electrode 41 and the second external electrode 42, or to the interfaces between the first bump portion 71 and the second bump portion 72 and the mounting substrate.

[0134] Such a structure of the first bump portion 71 makes it possible to disperse external stress applied to the multilayer ceramic capacitor 1 while suppressing the occurrence of acoustic noise in the multilayer ceramic capacitor 1. As a result, it is possible to realize a multilayer ceramic capacitor 1 that has a stronger adhesive strength between the first external electrode 41 and the first bump portion 71, and a stronger adhesive strength between the first bump portion 71 and the mounting substrate on which the multilayer ceramic capacitor 1 is mounted.

[0135] On the other hand, if the porosity in the seventh region 207 is lower than that in the eighth region 208 and the porosity of the seventh region 207 is less than 10%, when an external stress is applied from the first bump portion main surface 81 side due to an external impact when mounting the multilayer ceramic capacitor 1 on a mounting substrate, the voids 90 in the seventh region 207 may not be able to sufficiently disperse the external stress.

[0136] Furthermore, the porosity of the seventh region 207 is lower than that of the eighth region 208, and when the porosity of the seventh region 207 exceeds 25%, the number of voids present in the seventh region 207 is large. Therefore, the connection area between the first region 201 and the second region 202 located on the seventh region 207 is reduced in the seventh region 207, and the adhesive strength between the first region 201 and the second region 202 in the seventh region 207 may be reduced. Therefore, the first region 201 and the second region 202 may peel off from the seventh region 207, resulting in insufficient formation of the first bump portion 71, and it may not be possible to obtain the desired first bump portion 71.

[0137] In FIG. 2 , line 101 indicates the position of the end of the first bump portion 71 on the first end face 7 side in the longitudinal direction L. Line 103 indicates the position of the end of the first bump portion 71 on the second end face 8 side in the longitudinal direction L. Line 102 indicates the position 131 of the end of the first external electrode 41 on the first main surface 3 on the second end face 8 side in the longitudinal direction L. The seventh region 207 can be the region between line 101 and line 102. The region of the first bump portion 71 between line 101 and line 102 is a portion to which external stress is likely to be applied from the first external electrode 41. By designing this region as the seventh region 207 with a predetermined porosity, external stress can be more efficiently dispersed. In this case, the eighth region 208 can be the region between line 102 and line 103.

[0138] The same applies to the second bump portion 72. Line 104 in FIG. 2 indicates the position of the end of the second bump portion 72 on the second end face 8 side in the longitudinal direction L. Line 106 indicates the position of the end of the second bump portion 72 on the first end face 7 side in the longitudinal direction L. Line 105 indicates the position 132 of the end of the second external electrode 42 on the first main surface 3 on the first end face 7 side in the longitudinal direction L. The ninth region 209 can be the region between lines 104 and 105. The region of the second bump portion 72 between lines 104 and 105 is a portion to which external stress is likely to be applied from the second external electrode 42. By making this region the ninth region 209 with a predetermined porosity, external stress can be more efficiently dispersed. In this case, the tenth region 210 can be the region between lines 105 and 106.

[0139] (Porosity Measurement Method) A method for measuring the porosity of the first bump portion 71 and the second bump portion 72 of the multilayer ceramic capacitor 1 will be described. First, a cross section of the multilayer ceramic capacitor 1 is exposed. Specifically, cross-section polishing is performed from the first side surface 5 or the second side surface 6 of the multilayer ceramic capacitor 1 to the center of the width direction W of the multilayer ceramic capacitor 1 to expose a cross section parallel to the length direction L and the thickness direction T. The cross section parallel to the length direction L and the thickness direction T is called the LT cross section. Next, the first bump portion 71 and the second bump portion 72 of the exposed LT cross section are observed and photographed using a digital microscope (VHX-8000) manufactured by KEYENCE Corporation. The observation and photographing conditions are a magnification of 400x and a field of view of 750 μm × 750 μm. Portions in which no metal or glass is detected are considered to be voids. In this way, the void areas are identified, and image analysis software is used to divide the areas into first area 201, second area 202, and third area 203, and then the specific porosity of each area is measured.

[0140] The porosity of the first region 201 was determined as an average porosity calculated by adding the porosity of the first region 201 of the first bump portion 71 and the porosity of the fourth region 204 of the second bump portion 72. The porosity of the second region 202 was determined as an average porosity calculated by adding the porosity of the second region 202 of the first bump portion 71 and the porosity of the fifth region 205 of the second bump portion 72. The porosity of the third region 203 was determined as an average porosity calculated by adding the porosity of the third region 203 of the first bump portion 71 and the porosity of the sixth region 206 of the second bump portion 72.

[0141] The circle-equivalent D50 diameter of the voids 90 can also be determined by analyzing the image of the LT cross section using image analysis software in the same manner as in the measurement of the void ratio.

[0142] (Dimensions of the Multilayer Ceramic Capacitor) The dimension in the length direction L of the multilayer ceramic capacitor 1, including the laminate 2 and the external electrodes, is defined as dimension L. The dimension L is preferably 0.6 mm or more and 2.1 mm or less. The dimension in the thickness direction T of the multilayer ceramic capacitor 1, including the laminate 2 and the external electrodes, is defined as dimension T. The dimension T is preferably 0.3 mm or more and 1.3 mm or less. The dimension in the width direction W of the multilayer ceramic capacitor 1, including the laminate 2 and the external electrodes, is defined as dimension W. The dimension W is preferably 0.3 mm or more and 1.3 mm or less.

[0143] (Method for manufacturing a multilayer ceramic capacitor) A method for manufacturing a multilayer ceramic capacitor will be described. (1) A dielectric sheet and a conductive paste for an internal electrode are prepared. The conductive paste for the dielectric sheet and the internal electrode contains a binder and a solvent. Known binders and solvents can be used.

[0144] (2) Prepare a dielectric sheet on which no internal electrode pattern is formed, and a dielectric sheet on which a first internal electrode pattern and a second internal electrode pattern are formed by printing a conductive paste for internal electrodes in a predetermined pattern on the dielectric sheet by, for example, screen printing or gravure printing.

[0145] (3) A predetermined number of dielectric sheets on which no internal electrode pattern is printed are stacked to form a portion that will become the outer layer portion on the first main surface side, and a dielectric sheet on which a first internal electrode pattern is printed and a dielectric sheet on which a second internal electrode pattern is printed are stacked in this order on top of that to form a portion that will become the effective layer portion, and further a predetermined number of dielectric sheets on which no internal electrode pattern is printed are stacked on top of the portion that will become the effective layer portion to form a portion that will become the outer layer portion on the second main surface side, thereby producing a laminated sheet.

[0146] (4) The laminated sheet is pressed in the thickness direction by means of a hydrostatic press or the like to produce a laminated block. At this time, the corners and ridges of the laminated block may be rounded by barrel polishing or the like.

[0147] (5) The laminated block is cut into a predetermined size corresponding to the dimensions of the laminated chip, thereby manufacturing the laminated chip.

[0148] (6) The laminated chip is fired to produce a laminate. The firing temperature is preferably 900° C. or higher and 1400° C. or lower, although this depends on the materials of the dielectric and internal electrodes.

[0149] (Base Electrode Layer) (7) A conductive paste for the external electrodes is applied to both end surfaces of the laminate and baked to form baked layers for the external electrodes. The baked layers function as base electrode layers. The baking temperature is preferably 700°C or higher and 900°C or lower.

[0150] (8) If necessary, the surface of the baked layer is plated.

[0151] (Conductive Resin Layer) When the base electrode layer is formed of a conductive resin layer, the conductive resin layer can be formed by the following method. The conductive resin layer may be formed on the surface of the baking layer, or the conductive resin layer may be formed directly on the laminate without forming a baking layer. The conductive resin layer is formed by applying a conductive resin paste containing a thermosetting resin and a metal component onto the baking layer or the laminate, and then performing a heat treatment at a temperature of 250°C to 550°C to thermally cure the resin and form a conductive resin layer. The atmosphere during this heat treatment is preferably a nitrogen gas atmosphere. In addition, to prevent the resin from scattering and the various metal components from oxidizing, it is preferable to keep the oxygen concentration below 100 ppm.

[0152] (Thin Film Layer) When the base electrode layer is formed as a thin film layer, the base electrode layer can be formed by a thin film formation method such as sputtering or vapor deposition. The base electrode layer formed as a thin film layer is a layer of metal particles deposited to a thickness of 1 μm or less.

[0153] (Plating Electrode) Furthermore, a plating layer may be provided on the exposed portion of the internal electrode of the laminate without providing a base electrode layer. In this case, it can be formed by the following method. A plating process is performed on the first end face and the second end face of the laminate to form a base plating film on the exposed portion of the internal electrode. Either electrolytic plating or electroless plating may be used for the plating process. Electroless plating has the disadvantage of requiring pretreatment using a catalyst or the like to improve the plating deposition rate, which complicates the process. Therefore, electrolytic plating is usually preferred. Barrel plating is preferably used as the plating method. If necessary, an upper layer plating electrode may be formed on the surface of the lower layer plating electrode in the same manner.

[0154] (9) Then, a plating layer is formed on the surface of the base electrode layer, the surface of the conductive resin layer, the surface of the base plating layer, or the surface of the top plating layer. In this embodiment, a Ni plating layer and a Sn plating layer are formed on the baked layer. The Ni plating layer and the Sn plating layer are formed sequentially, for example, by barrel plating. In this manner, the multilayer ceramic capacitor 1 body is obtained.

[0155] (Method for Forming First and Second Bumps) As a method for forming the first and second bumps, a pattern for manufacturing the first and second bumps by applying a coating three times will be described. (10) A method for forming a first bump 71 and a second bump 72 on one main surface of a Sn-plated layer after forming a plating electrode (plating layer) will be described. First, multilayer ceramic capacitors 1 before the formation of bumps are arranged in a predetermined position using a suction nozzle. Hereinafter, the multilayer ceramic capacitor 1 before the formation of bumps may be referred to as the multilayer ceramic capacitor 1 for convenience. The holding substrate is a substrate that can hold the multilayer ceramic capacitor 1 and has heat resistance. The holding substrate is, for example, an alumina plate to which a metal material paste does not bond under reflow conditions, with polyimide double-sided tape attached.

[0156] Next, a conductive metal material paste containing at least one high-melting-point metal selected from Cu and Ni and Sn as a low-melting-point metal is prepared to form the first bump portion 71 and the second bump portion 72. The porosity can be increased by increasing the content of flux in the conductive metal paste.

[0157] Then, a conductive metal material paste is applied multiple times using a squeegee by screen printing to the multilayer ceramic capacitors 1 aligned on the holding substrate, forming a desired pattern. For this purpose, for example, a masking jig is prepared and placed on the multilayer ceramic capacitors 1 aligned on the holding substrate. The masking jig includes, for example, a mask plate having a rectangular shape in a plan view. The mask plate has a plurality of through holes penetrating from one main surface to the other main surface. Each of the through holes has a rectangular shape in a plan view. The size of this rectangular shape in a plan view determines the dimensions of the first bump portion 71 and the second bump portion 72.

[0158] The conductive metal material paste is then formed so as to cover a portion of the first external electrode 41 and the second external electrode 42 of the multilayer ceramic capacitor 1. Note that a method for forming bump portions in a desired pattern using the conductive metal material paste can also be formed by applying the paste in a predetermined pattern using a dispenser by a dispensing method or the like.

[0159] In this embodiment, when forming the first bump portion 71, a conductive metal material paste that will become the first region 201 and the fourth region 204 is applied, and then a reflow process is performed to form the first region 201 and the fourth region 204. Next, a conductive metal material paste that will become the third region 203 and the sixth region 206 is applied onto the first region 201 and the fourth region 204, and then a reflow process is performed to form the third region 203 and the sixth region 206. Then, a conductive metal material paste that will become the second region 202 and the fifth region 205 is applied onto the third region 203 and the sixth region 206, and then a reflow process is performed to form the second region 202 and the fifth region 205.

[0160] In this way, multiple conductive metal material pastes are applied in multiple steps to form first bump portions 71 and second bump portions 72 joined to the first external electrodes 41 and second external electrodes 42 of the multilayer ceramic capacitor 1 body 131, thereby manufacturing the multilayer ceramic capacitor 1. The multilayer ceramic capacitor 1 is then separated from the holding substrate. By the above method, the multilayer ceramic capacitor 1 having the first bump portions 71 and second bump portions 72 is manufactured.

[0161] (Porosity Adjustment Method) Next, a method for adjusting the porosity will be described using the first bump portion 71 as an example. As described above, the matters described using the first bump portion 71 as an example also apply to the second bump portion 72. Specific methods for adjusting the porosity of the first region 201, the second region 202, and the third region 203 will be described below in order.

[0162] (Three-Coat Pattern) (First Region of First Bump Portion) An example of a method for adjusting the porosity of the first region 201 is to adjust the flux content of the conductive metal material paste applied to the Sn plating layer to be lower than the flux content of the conductive metal material paste used for the third region 203. Alternatively, the alloy ratio in the conductive metal material paste is adjusted so that the melting point of the conductive metal material paste for the first region 201 is higher than those of the second region 202 and the third region 203. The first region 201 can be formed by setting the heat treatment temperature in the reflow process for forming the first region 201 to a higher temperature than those of the second region 202 and the third region 203. In this way, the porosity of the first region 201 can be adjusted by adjusting the flux content, alloy ratio, and reflow process temperature contained in the conductive metal material paste for the first region 201.

[0163] (Third Region) The porosity of the third region 203 is adjusted by adjusting the flux content in the conductive metal material paste that will become the third region 203 so that it is greater than the flux content in the conductive metal material paste that will become the first region 201 and the second region 202, and further adjusting the porosity of the seventh region 207 in the third region 203 so that it is greater than the porosity of the eighth region 208, and then applying the paste onto the first region 201.

[0164] Furthermore, the alloy ratio within the conductive metal material paste that becomes the third region 203 is adjusted so that the melting point of the conductive metal material paste is higher than that of the second region 202 and lower than that of the first region 201. The heat treatment temperature in the reflow process for forming the third region 203 is lower than that of the first region 201 and higher than that of the second region 202, thereby forming the third region 203. In this way, the porosity of the third region 203 can be adjusted by adjusting the flux content and alloy ratio contained in the conductive metal material paste that becomes the third region 203, and the treatment temperature in the reflow process.

[0165] (Second Region) The porosity of the second region 202 is adjusted by adjusting the flux content of the conductive metal material paste that will become the second region 202 to be the same as the flux content of the conductive metal material paste that will become the first region 201 but less than the flux content of the conductive metal material paste that will become the third region 203, and then applying the resulting paste onto the third region 203. The alloy ratio in the conductive metal paste that will become the second region 202 is adjusted so that the melting point of the conductive metal paste is lower than those of the first region 201 and the third region 203. The porosity of the second region 202 can be adjusted by performing the heat treatment temperature in the reflow process to form the second region 202 at a lower temperature than those of the first region 201 and the third region 203. The same applies to specific methods for adjusting the porosity of the fourth region 204, fifth region 205, and sixth region 206 of the second bump portion 72.

[0166] (Pattern for manufacturing first bump portion and second bump portion by four coatings) Next, a description will be given of another method for forming the first bump portion 71 and the second bump portion 72. In this other method for forming the first bump portion 71 and the second bump portion 72, the methods for forming the first region 201 and the second region 202 of the first bump portion 71 and the fourth region 204 and the fifth region 205 of the second bump portion 72 are the same as those described above, but the methods for forming the third region 203 and the sixth region 206 are different.

[0167] In the third region 203, a conductive metal material paste corresponding to the seventh region 207 is applied, and then a reflow process is performed to form the seventh region 207. Thereafter, a conductive metal material paste corresponding to the eighth region 208 is applied, and then a reflow process is performed to form the eighth region 208, and ultimately the third region 203. In the sixth region 206, a conductive metal paste corresponding to the ninth region 209 is applied, and then a reflow process is performed to form the ninth region 209. Thereafter, a conductive metal material paste corresponding to the tenth region 210 is applied, and then a reflow process is performed to form the tenth region 210, and ultimately the sixth region 206.

[0168] In this case, by adjusting the flux content of the conductive metal paste corresponding to the seventh region 207 and the eighth region 208, and the conductive metal paste corresponding to the ninth region 209 and the tenth region 210 so that the seventh region 207 and the ninth region 209 have a higher flux content, the porosity of the seventh region 207 can be made higher than that of the eighth region 208, and the porosity of the tenth region 210 can be made higher than that of the ninth region 209.

[0169] Then, the conductive metal material paste corresponding to the second region 202 is applied onto the third region 203, and the conductive metal material paste corresponding to the fifth region 205 is applied onto the sixth region 206, and the heat treatment temperature of the reflow process is performed under the same conditions as for the three-coat pattern, thereby forming the second region 202 and the fifth region 205.

[0170] In this way, multiple conductive metal material pastes are applied in multiple steps, and the first bump portions 71 and second bump portions 72 are formed by joining to the first external electrodes 41 and second external electrodes 42 of the multilayer ceramic capacitor 1 through a reflow process, thereby manufacturing the multilayer ceramic capacitor 1. The multilayer ceramic capacitor 1 is then separated from the holding substrate. By the above method, the multilayer ceramic capacitor 1 having the first bump portions 71 and second bump portions 72 is manufactured.

[0171] Experimental Example 1 Next, Experimental Example 1 will be described, which was conducted to confirm the acoustic noise reduction effect achieved by the multilayer ceramic capacitor 1 according to this embodiment, the stress dispersion effect of the first bump portion 71 and the second bump portion 72, and the adhesive strength between the external electrodes and the bumps and between the mounting substrate and the bumps. First, the methods for each evaluation will be described in order.

[0172] (1) Sound Pressure Measuring Device (Confirmation of the Effect of Reducing "Crystalline Noise") First, a sound pressure measuring device 401 will be described with reference to FIG. 7. FIG. 7 is a diagram showing a schematic configuration of the sound pressure measuring device 401. FIG. 7 shows the sound pressure measuring device 401 for measuring the sound pressure level of noise generated due to "crystalline noise" of a multilayer ceramic capacitor 1. As shown in FIG. 7, a mounting board 403 on which a chip-type electronic component, i.e., a multilayer ceramic capacitor 1, is mounted is placed in an anechoic box 405. A sound-collecting microphone 407 is disposed opposite the mounting board 403. An AC voltage having a frequency of 3 kHz and a voltage of 1 Vpp, for example, is applied to the multilayer ceramic capacitor 1. This causes the multilayer ceramic capacitor 1 to deform the mounting board 403 at the above frequency, generating a "crystalline noise." This noise is collected by a sound collecting microphone 407, and the output of the sound collecting microphone 407 is input to an FFT (Fast Fourier Transform) analyzer 411 via a sound collection meter 409, where the sound pressure level is analyzed. It was determined that squeals at a sound pressure level of 61 dB or less on average were suppressed.

[0173] (2) Terminal Electrode Adhesion Strength Test After measurement using the sound pressure measuring device, a terminal electrode adhesion strength test is performed in accordance with Section 9 of EIAJET-7403. FIG. 8 is a diagram illustrating an outline of the terminal electrode adhesion strength test. FIG. 8 shows the terminal electrode adhesion strength test as viewed from a plane parallel to the length direction L and width direction W. As shown in FIG. 8, a force of 5.0 N is applied to the multilayer ceramic capacitor 1 mounted on the mounting substrate 403 by the first pressing jig 422 in the direction of arrow F for 60 seconds. Thereafter, it is confirmed whether the first bump portion 71 and the second bump portion 72 have peeled off from the first external electrode 41 and the second external electrode 42, and whether the multilayer ceramic capacitor 1 has peeled off from the test jig (mounting substrate 403).

[0174] After the terminal electrode adhesive strength test, samples that did not experience peeling were determined to have adhesive strength between the first external electrode 41 and the second external electrode 42 and the mounting substrate 403. "Not peeled" means that the first bump portion 71 and the second bump portion 72 were not completely separated and peeled from the first external electrode 41 and the second external electrode 42 and the mounting substrate 403, and a capacitance within ±10% of the standard capacitance was maintained. "Peeled" means that the first bump portion 71 and the second bump portion 72 were completely separated and peeled from the first external electrode 41 and the second external electrode 42 and the mounting substrate 403, and a capacitance within ±10% of the standard capacitance was not maintained.

[0175] (3) Stress Dispersion Test The stress dispersion test will be described with reference to FIG. 9 . FIG. 9 is a diagram illustrating an outline of the stress dispersion test. FIG. 9 illustrates the stress dispersion test as viewed from a plane parallel to the length direction L and the thickness direction T. After the terminal electrode fixing strength test, the stress dispersion test is performed on the first external electrode 41 and the second external electrode 42 that have adhesive strength to the mounting substrate 403. Specifically, the central surface (surface center) of the first external electrode 41 on the second main surface 4 side is pressed in the direction of arrow G with a second pressing jig 432 having a radius of 0.5 mm at 5.0 N for 60 seconds. Then, the central surface (surface center) of the mounting substrate 403 is pressed from the rear surface 436 side of the mounting substrate 403 with a third pressing jig 434 having a radius of 0.5 mm at 5.0 N for 60 seconds.

[0176] After the pressing by the second pressing jig 432 and the third pressing jig 434 is completed, the multilayer ceramic capacitor 1 is observed and imaged using a scanning electron microscope (SEM) and a wavelength dispersive X-ray analyzer (WDX). The conditions for observation and imaging using the SEM are a magnification of 50x and a field of view of 6000 μm × 6000 μm. The conditions for observation and imaging using the WDX are a magnification of 50x, an acceleration voltage of 15 kV, and a field of view of 6000 μm × 6000 μm.

[0177] (4) Measurement of Short Circuit Rate Measurement of the short circuit rate will now be described. After the stress dispersion test, the short circuit rate of the multilayer ceramic capacitor 1 was measured. The measurement method was to apply a rated voltage of 6 V to the multilayer ceramic capacitor 1 and then measure the resistance value using a multimeter. Samples with a resistance value of 10 kΩ or less were determined to have short circuits. The proportion of samples determined to have short circuits out of 20 samples for each test was calculated as the short circuit rate.

[0178] In addition, the areas around the first bump portion 71 and the second bump portion 72 were observed using images taken by SEM and WDX, and those in which no cracks had occurred on the exterior or inside of the first bump portion 71 or the second bump portion 72, including the internal electrodes, and no short circuits had occurred, were determined to have a stress dispersion effect.

[0179] (5) Specifications of Samples in Experimental Example 1 The specifications of the samples used in Experimental Example 1 will be described. According to the manufacturing method of the multilayer ceramic capacitor 1 described above, a multilayer ceramic capacitor 1 having the following specifications was manufactured. The size of the multilayer ceramic capacitor 1, L dimension (length direction) × W dimension (width direction) × T dimension (thickness direction), is as follows: L dimension [mm]: 1.0, W dimension [mm]: 0.5, T dimension [mm]: 0.5

[0180] The thickness of the internal electrodes was 0.58 μm, the thickness of the ceramic layers was 1.5 μm, the number of laminated layers was 250, the dielectric constant was 2500 F / m, and the capacitance was 2.2 μF.

[0181] The external electrodes each include a base electrode layer and a plating layer, the base electrode layer being made of Cu, and the plating layer having a two-layer structure of a Ni plating layer and a Sn plating layer, and the thickness of the external electrodes was 35 μm.

[0182] The conductive metal paste used to form the bump portion was Cu-10 wt % with a D50 of 5 μm, Ni powder-31.5 wt %, Sn-3 wt % with a D50 of 5 μm, Ag-0.5 wt %, and solder powder with a Cu composition-58.5 wt %.

[0183] The flux content of the conductive metal paste that forms the first region 201 to the sixth region 206 is adjusted, and the reflow temperature in the reflow process is also adjusted. At this time, the flux content and reflow temperature are adjusted so that the first region 201 and the second region 202 are formed within a range of 10% from the first bump portion main surface 81 toward the second bump portion main surface 82. Similarly, the flux content and reflow temperature are adjusted so that the fourth region 204 and the sixth region 206 are formed within a range of 10% from the second bump portion main surface 82 toward the first bump portion main surface 81.

[0184] In this way, the first bump portion 71 and the second bump portion 72 were formed, with the porosity of the first region 201 to the sixth region 206 of each sample being obtained. The shapes of the first bump portion 71 and the second bump portion 72 after the reflow process were approximately rectangular parallelepiped, and the dimensions of the first bump portion 71 and the second bump portion 72 in the length direction L were 350 μm, and the dimensions of the first bump portion 71 and the second bump portion 72 in the width direction W were 500 μm. The thickness of each of the first bump portion 71 and the second bump portion 72, i.e., the length in the thickness direction T, was 100 μm.

[0185] In the example, the porosity of the first region 201 and the second region 202 of the first bump portion 71 is lower than that of the third region 203, and the porosity of the third region 203 is higher than that of the first region 201 and the second region 202. In addition, the porosity of the fourth region 204 and the fifth region 205 of the second bump portion 72 is lower than that of the sixth region 206, and the porosity of the sixth region 206 is higher than that of the fourth region 204 and the fifth region 205.

[0186] Comparative Example 1 In Comparative Example 1, the porosity of the first region 201 and the second region 202 of the first bump portion 71 is higher than the porosity of the third region 203, and the porosity of the third region 203 is lower than the porosity of the first region 201 and the second region 202. Furthermore, the porosity of the fourth region 204 and the fifth region 205 of the second bump portion 72 is higher than the porosity of the sixth region 206, and the porosity of the sixth region 206 is lower than the porosity of the fourth region 204 and the fifth region 205.

[0187] Comparative Example 2 In Comparative Example 2, the porosity of the first region 201 of the first bump portion 71 is higher than the porosity of the second region 202 and the third region 203, and the porosity of the second region 202 and the third region 203 is lower than the porosity of the first region 201. Furthermore, the porosity of the fourth region 204 of the second bump portion 72 is higher than the porosity of the fifth region 205 and the sixth region 206, and the porosity of the fourth region 204 and the sixth region 206 is lower than the porosity of the fourth region 204.

[0188] Comparative Example 3 In Comparative Example 3, the porosity of the first region 201 and the third region 203 of the first bump portion 71 is higher than the porosity of the second region 202, and the porosity of the second region 202 is lower than the porosity of the first region 201 and the third region 203. The porosity of the fourth region 204 and the sixth region 206 of the second bump portion 72 is higher than the porosity of the fifth region 205, and the porosity of the fifth region 205 is lower than the porosity of the fourth region 204 and the sixth region 206.

[0189] Comparative Example 4 In Comparative Example 4, similarly to Patent Document 1, the first bump portion 71 and the second bump portion 72 were formed by electroplating.

[0190] Comparative Example 5 Comparative Example 5 has a higher porosity than Example 1 from the first region 201 to the sixth region 206 .

[0191] (Results of Experimental Example 1) Fig. 10 shows the measurement results of sound pressure level, stress dispersion effect, and adhesive strength for samples in which the porosity in the first bump portion 71 and the second bump portion 72 was changed in Experimental Example 1. As shown in Fig. 10, it was confirmed that Example 1 was a multilayer ceramic capacitor 1 having an acoustic suppression effect, stress dispersion effect, and adhesive strength.

[0192] In all of Comparative Examples 1 to 3, the effect of suppressing noise was confirmed, but it was confirmed that sufficient adhesive strength was not obtained because the porosity of the first region 201, the second region 202, the fourth region 204, and the fifth region 205, which are close to the first external electrode 41 and the second external electrode 42 and the mounting substrate, was higher than or the same as that of the third region 203 and the sixth region 206.

[0193] In Comparative Example 4, the structure was dense and no voids were present in either the first bump 71 or the second bump 72. As a result, it was confirmed that the stress dispersion effect was insufficient and many cracks occurred.

[0194] In Comparative Example 5, the porosity was higher in all regions of the first bump portion 71 than in Example 1, and it was confirmed that sufficient adhesion strength was not obtained between the first external electrode 41 and the second external electrode 42 and the mounting substrate.

[0195] Experimental Example 2 will now be described, which was conducted to confirm the acoustic reduction effect of the multilayer ceramic capacitor 1 according to this embodiment, the stress dispersion effect of the first bump portion 71 and the second bump portion 72, and the adhesive strength between the external electrodes and the bumps and between the mounting substrate and the bumps. The table shown in FIG. 11 is a table showing the results of Experimental Example 2.

[0196] In Experimental Example 2, the specifications of the samples used were the same as in Experimental Example 1 except for the porosity of each region, and the experiment was conducted by adjusting the porosity within the first bump portion 71 and the second bump portion 72 to be different, as shown in Figure 11. The test methods used in Experimental Example 2 were the same as those used in Experimental Example 1. In Experimental Example 2, out of 20 samples, 17 or more samples that exhibited all of the effects of suppressing squeal, increasing adhesion, and dispersing stress were evaluated as "Good", 10 to 17 samples were evaluated as "Good", and 10 or less samples were evaluated as "Poor".

[0197] As shown in Figure 11, experimental example 2 confirmed that in examples 4 to 8, the porosity of the first region 201, the second region 202, the fourth region 204, and the fifth region 205 was 0.5% to 18%, thereby providing better noise suppression, adhesion, and stress dispersion effects.

[0198] Furthermore, in Examples 2 and 3, although the noise suppression effect and adhesive strength were obtained, it was confirmed that the stress dispersion effect was not obtained because the porosity of the third region 203 and the sixth region 206 was very low and external stress could not be sufficiently dispersed.

[0199] In Examples 9 and 10, it was confirmed that although the effects of suppressing squeal and dispersing stress were obtained, sufficient adhesive strength was not obtained.

[0200] Experimental Example 3 Next, another Experimental Example 3 will be described, which was conducted to confirm the acoustic reduction effect achieved by the multilayer ceramic capacitor 1 according to this embodiment, the stress dispersion effect of the first bump portion 71 and the second bump portion 72, and the adhesive strength between the external electrodes and the bumps and between the mounting substrate and the bumps. The table shown in FIG. 12 is a table showing the results of Experimental Example 3.

[0201] In Experimental Example 3, as shown in Figure 12, the porosity of the seventh region 207 and the eighth region 208 in the third region 203 of Example 4, and the porosity of the ninth region 209 and the tenth region 210 in the sixth region 206 were adjusted, and an experiment was conducted.

[0202] As shown in Figure 12, in Examples 12 to 15, the porosity of the seventh region 207 and the tenth region 210 was higher than the porosity of the eighth region 208 and the ninth region 209, and was between 10% and 25%, thereby achieving a greater stress dispersion effect.

[0203] In Example 11, the difference between the porosity of the seventh region 207 and the tenth region 210 and the porosity of the eighth region 208 and the ninth region 209 was small, so the stress dispersion effect was not sufficient.

[0204] In Example 16, the porosity of the seventh region 207 and the tenth region 210 was greater than the porosity of the eighth region 208 and the ninth region 209, so adhesion between the first region 201 and the second region 202, and between the fourth region 204 and the fifth region 205 could not be ensured, and the stress dispersion effect was not sufficiently obtained.

[0205] As described above, in the multilayer ceramic capacitor of this embodiment, the first bump portion 71 has a first region 201 having a void 90 on the first bump portion main surface 81 side, a second region 202 having a void 90 on the second bump portion main surface 82 side, and a third region 203 sandwiched between the first region 201 and the second region 202. The second bump portion 72 has a fourth region 204 having a void 90 on the third bump portion main surface 83 side, a fifth region 205 having a void 90 on the fourth bump portion main surface 84 side, and a sixth region 206 sandwiched between the third region 203 and the fourth region 204. The porosity in the first region 201 and the second region 202 is lower than that in the third region 203, and the first region 201 and the second region 202 are filled with more metal than the third region 203.

[0206] Therefore, the connection area of ​​the first region 201 with respect to the first external electrode 41 increases, and the first region 201 is more likely to be firmly connected to the first external electrode 41. As a result, the first bump portion 71 can securely adhere to the first external electrode 41 with sufficient strength.

[0207] Furthermore, the porosity of the second region 202 is lower than that of the third region 203, and the second region 202 is filled with more metal than the third region 203. This increases the connection area of ​​the second region 202 with respect to the mounting substrate, making it easier to firmly connect the mounting substrate and the second region 202. As a result, it is possible to ensure sufficient adhesive strength of the first bump portion 71 to the mounting substrate.

[0208] The porosity of the third region 203 is higher than the porosity of the first region 201 and the second region 202. Therefore, the voids in the third region 203 can disperse external stress that has not been dispersed in the first region 201 and the second region 202.

[0209] The voids in the third region 203 allow external stress to be dispersed, thereby preventing cracks from reaching the internal electrode via the external electrode, thereby preventing an increase in the incidence of short circuits caused by moisture flowing in from the outside via the cracks, and preventing peeling caused by cracks extending to the interface between the first bump portion 71 and the first external electrode 41 and the interface between the first bump portion 71 and the mounting substrate.

[0210] As a result, the first bump portion 71 can suppress the occurrence of squealing noise in the multilayer ceramic capacitor 1 while dispersing external stress applied to the multilayer ceramic capacitor 1, and a multilayer ceramic capacitor 1 can be obtained that has both a strong adhesive force between the first external electrode 41 and the first bump portion 71 and a strong adhesive force between the bump and the mounting substrate on which the multilayer ceramic capacitor 1 is mounted.

[0211] The same applies to the second bump portion 72 and the second external electrode.

[0212] Although the embodiments of the present invention have been disclosed above, the present invention is not limited thereto. In other words, various modifications can be made to the above-described embodiments in terms of mechanism, shape, material, quantity, position, arrangement, etc., without departing from the scope of the technical idea and purpose of the present invention, and such modifications are included in the present invention.

[0213] <1> A multilayer ceramic capacitor comprising: a laminate including a plurality of laminated ceramic layers and a plurality of internal electrodes laminated on the ceramic layers, the laminate including first and second main surfaces opposing each other in a thickness direction, first and second side surfaces opposing each other in a width direction perpendicular to the thickness direction, and first and second end surfaces opposing each other in a length direction perpendicular to the thickness direction and the width direction; first external electrodes arranged on at least the first end surfaces and the first main surfaces of the laminate; second external electrodes arranged on at least the second end surfaces and the first main surfaces of the laminate; a first bump portion connected to the first external electrode; and a second bump portion connected to the second external electrode, wherein the first bump portion has a first bump main surface located on the side of the first external electrode and a second bump main surface opposing the first bump main surface in a thickness direction T, the second bump portion has a third bump portion main surface which is located on the second external electrode side, and a fourth bump portion main surface which faces the third bump portion main surface in the thickness direction T; the first bump portion has a first region having a gap on the first bump portion main surface side, a second region having a gap on the second bump portion main surface side, and a third region sandwiched between the first region and the second region; the second bump portion has a fourth region having a gap on the third bump portion main surface side, a fifth region having a gap on the fourth bump portion main surface side, and a sixth region sandwiched between the fourth region and the fifth region; the porosity in the first region and the second region is lower than that in the third region, and the porosity in the fourth region and the fifth region is lower than that in the sixth region.

[0214] <2> The multilayer ceramic capacitor according to <1>, wherein the porosity of the first region and the second region is 0.5% or more and 18% or less, the porosity of the fourth region and the fifth region is 0.5% or more and 18% or less, and the porosity of the third region and the sixth region is 5% or more and 25% or less.

[0215] <3> The multilayer ceramic capacitor according to <1> or <2>, wherein the third region has a seventh region arranged on a first end face side of the multilayer ceramic capacitor and an eighth region arranged from the seventh region to the second end face side; the sixth region has a ninth region arranged on a second end face side of the multilayer ceramic capacitor and a tenth region arranged from the ninth region to the first end face side; the porosity of the seventh region is higher than that of the eighth region, and the porosity of the tenth region is higher than that of the ninth region; and the porosities of the seventh region and the tenth region are 10% or more and 25% or less.

[0216] <4> The multilayer ceramic capacitor according to any one of <1> to <3>, wherein a circle-equivalent D50 diameter of the void in a cross section parallel to the length direction and the thickness direction is 5 μm or more and 50 μm or less.

[0217] REFERENCE SIGNS LIST 1 Multilayer ceramic capacitor 2 Laminate 3 First main surface 4 Second main surface 5 First side surface 6 Second side surface 7 First end surface 8 Second end surface 10 Effective layer portion 12 First outer layer portion 13 Second outer layer portion 15 First side gap portion 16 Second side gap portion 20 Ceramic layer 25 Core portion 31 First internal electrode 32 Second internal electrode 33 First opposing portion 34 Second opposing portion 41 First external electrode 42 Second external electrode 51 First base electrode layer 52 Second base electrode layer 71 First bump portion 72 Second bump portion 74 First external electrode connecting surface 75 Second external electrode connecting surface 81 First bump portion main surface 82 Second bump portion main surface 83 Third bump portion main surface 84 Fourth bump main surface 90: gap 201: first region 202: second region 203: third region 204: fourth region 205: fifth region 206: sixth region 207: seventh region 208: eighth region 209: ninth region 210: tenth region L: length direction T: thickness direction W: width direction

Claims

1. A multilayer ceramic capacitor comprising: a laminate including a plurality of laminated ceramic layers and a plurality of internal electrodes laminated on the ceramic layers, the laminate including first and second main surfaces opposing each other in a thickness direction, first and second side surfaces opposing each other in a width direction perpendicular to the thickness direction, and first and second end surfaces opposing each other in a length direction perpendicular to the thickness direction and the width direction; first external electrodes disposed on at least the first end surfaces and the first main surfaces of the laminate; second external electrodes disposed on at least the second end surfaces and the first main surfaces of the laminate; a first bump portion connected to the first external electrode; and a second bump portion connected to the second external electrode, wherein the first bump portion has a first bump main surface located on the side of the first external electrode, and a second bump main surface opposing the first bump main surface in the thickness direction T, the second bump portion has a third bump portion main surface which is located on the second external electrode side, and a fourth bump portion main surface which faces the third bump portion main surface in the thickness direction T; the first bump portion has a first region having a gap on the first bump portion main surface side, a second region having a gap on the second bump portion main surface side, and a third region sandwiched between the first region and the second region; the second bump portion has a fourth region having a gap on the third bump portion main surface side, a fifth region having a gap on the fourth bump portion main surface side, and a sixth region sandwiched between the fourth region and the fifth region; the porosity in the first region and the second region is lower than that in the third region, and the porosity in the fourth region and the fifth region is lower than that in the sixth region.

2. The multilayer ceramic capacitor according to claim 1, wherein the porosity of the first region and the second region is 0.5% or more and 18% or less, the porosity of the fourth region and the fifth region is 0.5% or more and 18% or less, and the porosity of the third region and the sixth region is 5% or more and 25% or less.

3. The multilayer ceramic capacitor according to claim 1 or 2, wherein the third region has a seventh region arranged on the first end face side of the multilayer ceramic capacitor and an eighth region arranged from the seventh region to the second end face side, the sixth region has a ninth region arranged on the second end face side of the multilayer ceramic capacitor and a tenth region arranged from the ninth region to the first end face side, the porosity of the seventh region is higher than that of the eighth region and the porosity of the tenth region is higher than that of the ninth region, and the porosity of the seventh region and the tenth region is 10% or more and 25% or less.

4. A multilayer ceramic capacitor according to any one of claims 1 to 3, wherein the circle-equivalent D50 diameter of the void in a cross section parallel to the length direction and the thickness direction is 5 µm or more and 50 µm or less.

Images