High precision analog-to-digital signal conversion using frequency alignment

Abstract

Methods, systems, and apparatus, including computer programs encoded on computer storage media, for performing high-precision analog-to-digital signal conversion According to one aspect, there is provided a circuit that includes an analog-to-digital converter (ADC) circuit and a voltage reference device configured to provide a reference signal to the ADC circuit, wherein: the voltage reference device generates the reference signal with a time-varying fluctuation; the ADC circuit has a sampling period and is configured to determine an estimated voltage after a conversion phase of each sampling period; and the sampling period of the ADC circuit corresponds to a frequency of the time-varying fluctuation.

Description

[0001] HIGH PRECISION ANALOG-TO-DIGITAL SIGNAL CONVERSION USING

[0002] FREQUENCY ALIGNMENT

[0003] BACKGROUND

[0004] This specification relates to analog-to-digital signal conversion.

[0005] Analog-to-digital converter (ADC) circuits convert analog signals to digital signals by measuring and quantizing values (e.g., voltages) of the analog signals. Examples of ADC circuits include successive approximation register (SAR) ADC circuits. SAR ADC circuits can convert analog signals to digital signals by comparing voltages of the analog signals to reference signals generated with a known voltage.

[0006] SUMMARY

[0007] This specification describes a circuit that can perform high-precision analog-to- digital signal conversion. In particular, this specification describes a circuit that uses frequency alignment between a sampling frequency of an ADC circuit and a fluctuation frequency of a reference signal for the ADC circuit to reduce errors caused by fluctuations of the reference signal.

[0008] According to one aspect, a circuit includes an analog-to-digital converter (ADC) circuit and a voltage reference device configured to provide a reference signal to the ADC circuit, wherein: (i) the voltage reference device generates the reference signal with a time-varying fluctuation; (ii) the ADC circuit has a sampling period and is configured to determine an estimated voltage at a convergence interval at each sampling period; and (iii) the sampling period of the ADC circuit corresponds to a frequency of the timevarying fluctuation.

[0009] Particular embodiments of the subject matter described in this specification can be implemented so as to realize one or more of the following advantages.

[0010] ADC circuits rely on low-noise signals to perform accurate analog-to-digital signal conversion. Mechanisms such as chopping amplifiers, dynamic element matching, and so on, can reduce or compensate for signal noise in ADC circuits, but can also introduce periodic fluctuations to the signals. In conventional ADC systems, these periodic fluctuations may be removed by adding filters (e g., capacitors), but adding such components increases the size and complexity of the ADC circuits.

[0011] Conventional ADC systems can include error correcting mechanisms to compensate for errors that may occur during signal conversion, such as digital-to-analog (DAC) settling errors resulting from the lengths of time needed for voltages within the ADC system to change values. As an example, SAR ADC circuits can use redundant voltage comparisons to perform error correction. Conventional ADC systems are therefore configured to use error correcting mechanisms to compensate for physical limitations of the ADC circuits themselves.

[0012] By using frequency alignment between the sampling rate of the ADC circuit and the frequency of periodic fluctuations (e.g., as introduced by chopping amplifiers, dynamic element matching, etc.) within the reference signal for the ADC circuit, the systems and techniques described in this specification can use error correcting mechanisms of the ADC circuit (e g., redundancy in an SAR ADC) to compensate for the periodic fluctuations within the reference signal. The described systems can compensate for the periodic fluctuations within the reference signal without using filters dedicated to removing the periodic fluctuations. The described systems can therefore perform high- precision analog-to-digital signal conversion using fewer components and using a smaller silicon area compared to conventional methods.

[0013] The details of one or more embodiments of the subject matter of this specification are set forth in the accompanying drawings and the description below. Other features, aspects, and advantages of the subj ect matter will become apparent from the description, the drawings, and the claims.

[0014] BRIEF DESCRIPTION OF THE DRAWINGS

[0015] FIG. 1 is a diagram that illustrates a frequency aligned analog-to-digital converter (ADC) circuit.

[0016] FIG. 2 is a flowchart of an example process for converting an analog input signal to a digital output signal during a sampling period.

[0017] FIG. 3A illustrates an example periodic fluctuation of a reference signal as aligned with a sampling period.

[0018] FIG. 3B illustrates an estimation error during a sampling period for an example ADC circuit using error correction.

[0019] FIG. 3C illustrates estimating a voltage for an analog input signal using an SAR ADC circuit during a sampling period for the SAR ADC circuit.

[0020] FIG. 3D illustrates a reduction of estimation error resulting from error correction by an example frequency aligned ADC circuit. FIG. 4A illustrates an example frequency spectrum of a digital output signal generated by an ADC circuit without frequency alignment.

[0021] FIG. 4B illustrates an example frequency spectrum of a digital output signal generated by an ADC circuit with frequency alignment.

[0022] Like reference numbers and designations in the various drawings indicate like elements.

[0023] DETAILED DESCRIPTION

[0024] FIG. 1 is a diagram that illustrates a frequency aligned analog-to-digital converter (ADC) circuit 100. The circuit 100 can receive an analog signal 102 and generate a digital signal 104 representing the analog signal 102. The circuit 100 generates the digital signal 104 by quantizing voltage values of the analog signal 102.

[0025] The circuit 100 includes an ADC circuit 106 that can process the analog signal 102 to generate the digital signal 104. As part of generating the digital signal 104, the ADC circuit 106 can compare the analog signal 102 with a time-varying reference signal 108. As described in more detail below, the circuit 100 is configured to align a sampling period of the ADC circuit 106 to correspond with a frequency of fluctuations of the timevarying reference signal 108, which enables the circuit 100 to accurately generate the digital signal 108 without filtering the fluctuations from the lime-varying reference signal 108.

[0026] During each sampling period of the ADC circuit 106, the circuit 106 can generate the digital signal 104 by: (i) receiving, during a first portion of the sampling period (e.g., during a signal tracking and acquisition phase of the sampling period), a voltage value of the analog signal 102 for the sampling period, (ii) estimating, during a second portion of the sampling period (e.g., during a conversion phase of the sampling period), the voltage value of the analog signal 102 for the sampling period, and (iii) outputting, at the end of the sampling period, a multi -bit digital value of the digital signal 104 for the sampling period that represents the estimated voltage value for the sampling period.

[0027] As an example, the ADC circuit 106 can be a Successive Approximation Register (SAR) ADC circuit and can estimate the voltage value of the analog signal 102 for each sampling period by iteratively comparing the voltage value of the analog signal 102 for the sampling period with voltages of the time- var ing reference signal 108. Examples of SAR ADC circuits are described by Murmann in “On the Use of Redundancy in Successive Approximation A / D Converters”, by Boyacigiller et al. in “An Error-correcting 14b / 20 [is CMOS A / D Converter’, and by Kraemer in ‘‘High- Resolution SAR A / D Converters with Loop-Embedded Input Buffer”.

[0028] The accuracy with which the ADC circuit 106 estimates and quantizes voltages of the analog signal 102 depends at least partly on how much the time-varying reference signal 108 fluctuates from a target voltage for the signal 108. In general, the circuit 100 can include a variety of noise reduction and noise compensation mechanisms to increase the accuracy of the generated digital signal 104.

[0029] As an example, the ADC circuit 106 can utilize error correction during each sampling period that can correct for errors in estimating the voltage value of the analog signal 102 caused by settling errors within the ADC circuit (e g., DAC settling errors). As a further example, when the ADC circuit 106 is an SAR ADC circuit, the circuit 106 can perform one or more error correcting redundant voltage comparisons during each sampling period. Examples of SAR ADC circuits with redundancy are described by Murmann in “On the Use of Redundancy in Successive Approximation A / D Converters”, by Boyacigiller et al. in “An Error-correcting 14b / 20 ps CMOS A / D Converter”, and by Kraemer in “High-Resolution SAR A / D Converters with Loop-Embedded Input Buffer”.

[0030] The circuit 100 includes a voltage reference system 110 that can generate the time-vary ing reference signal 108. In particular, to generate a stable and low-noise reference signal 108. the voltage reference system 110 can generate the reference signal 108 using a bandgap reference circuit. The voltage reference system 110 can include a chopper amplifier. The chopper amplifier can perform noise shaping to attenuate noise (e.g., 1 / / noise) within the reference signal 108. In some implementations, the voltage reference system 110 can utilize dynamic element matching to reduce noise within the reference signal 108.

[0031] The mechanisms by which the circuit 100 reduces and compensates for noise in the reference signal 108 can introduce periodic fluctuations within the time-varying reference signal 108. As an example, when the voltage reference system 110 includes a chopping amplifier, the chopping amplifier can introduce a chopping ripple into the reference signal 108 at a chopping frequency of the chopping amplifier. As another example, the voltage reference system 110 utilizes dynamic element matching, the dynamic element matching can introduce a ripple into the reference signal 108 at a switching frequency of the dynamic element matching. By aligning the sampling period of the ADC circuit 106 with the periodic fluctuations of the time-varying reference signal 108, the circuit 100 can compensate for the estimation errors caused by the periodic fluctuations without filtering the reference signal 108 to remove the periodic fluctuations. In particular, the circuit 100 can be configured (e.g., by tuning or selecting the sampling period of the ADC circuit 106, the chopping period of the voltage reference system 110, etc.) to align the periodic fluctuations of the time-varying reference signal 108 with the sampling period of the ADC circuit 106 and enable error correction by the ADC circuit 106 to correct for voltage estimation errors caused by the periodic fluctuation during each sampling period. An example alignment of the sampling period of the ADC circuit 106 with the periodic fluctuations of the time-varying reference signal 108 is described in more detail below with reference to FIG. 3 A and FIG. 3B.

[0032] When configured as described within this specification, the circuit 100 can perform high-precision analog-to-digital conversion without filtering periodic fluctuations (e.g., chopping ripples) of the reference signal 108.

[0033] FIG. 2 is a flowchart of an example process 200 for converting an analog input signal to a digital output signal during a sampling period. The process 200 can be performed by an analog-to-digital conversion system, e.g., the frequency aligned ADC circuit 102 of FIG. 1, at each sampling period of the system.

[0034] At the start of the sampling period, the system can receive the analog input signal for the sampling period (step 202). As part of receiving the analog input signal, the system can fix a voltage value of the analog input signal for voltage comparisons throughout the sampling period. For example, the system can fix the voltage value of the analog input signal using a sample and hold mechanism.

[0035] The system can determine an initial estimate of the analog input signal for the sampling period by comparing the analog input signal with a reference signal (step 204). For example, the system can include a SAR ADC that can iteratively compare the analog input signal with the reference signal to generate the initial estimate for the sampling period.

[0036] The system can generate the reference signal using a voltage reference device. In some implementations, to generate a stable and low-noise reference signal, the system can generate the reference signal using a bandgap reference device. The system can process the reference signal to further reduce or remove noise from the reference signal. As one example, the voltage reference device can include a chopping amplifier that can perform noise shaping of the reference signal. As another example, the system can utilize dynamic element matching to reduce effects of component variability within the system.

[0037] The reference signal can include a time-varying fluctuation. In particular, the reference signal can include periodic fluctuations (e.g., voltage ripples) introduced when the system processes the reference signal to remove noise from the reference signal. For example, when the voltage reference device generates the reference signal using a chopping amplifier, the time-varying fluctuation can be a chopping ripple of the chopping amplifier.

[0038] At the end of the sampling period, the system can determine a final estimate of the analog input signal by performing error correction (step 206). As an example, when the system includes an SAR ADC. the system can perform error correction by performing one or more redundant voltage comparisons using the SAR ADC.

[0039] The error correction can be associated with a convergence interval, during which an expected error of the final estimated voltage falls below an error threshold. For example, when the system performs one or more redundant voltage comparisons using the SAR ADC, the convergence interval can be the time interval in which the system performs the redundant voltage comparisons.

[0040] The system can be configured to align the sampling period with the time-vary ing fluctuation of the reference signal (e g., by aligning the sampling period to correspond to a frequency of the time-varying fluctuation). In particular, the system can be configured to align zeros of the time-varying fluctuation with the error correction convergence interval. As described in more detail below with reference to FIG. 3A and FIG. 3B, by aligning the time-varying fluctuation of the reference signal with the error correction convergence interval, the system can accurately estimate the analog input signal without filtering the reference signal to remove the time-varying fluctuation.

[0041] As an example, the system can be configured (e.g., by7tuning or selecting a sampling period of the ADC circuit, a chopping period of the voltage reference system, etc.), to align the sampling period with a period of the time-varying fluctuation of the reference signal. As an example, the sampling period of the system can be the fluctuation period of the reference signal. As another example, the sampling period of the system can be an integer multiple of the fluctuation period of the reference signal. As another example, the fluctuation period of the reference signal can be an integer multiple of the sampling period of the system. The system can then output the final estimate of the analog input signal as the value of the digital output signal for the sampling period (step 208).

[0042] FIG. 3A illustrates a fluctuation voltage 302 over time 304 for an example periodic fluctuation 306 of a reference signal as aligned with a sampling period. The periodic fluctuation 306 can, for example, be a chopping ripple of a chopping amplifier used to generate the reference signal.

[0043] As described above, the sampling period is aligned with a period of the fluctuation 306 to enable error correction of an ADC circuit to compensate for the fluctuation 306. The sampling period and fluctuation period can be aligned such that the fluctuation 306 has consistent voltages at the start 308 and end 310 of each sampling period. In particular, the sampling period and the fluctuation period can be aligned such that zeros 312 of the periodic fluctuation (e.g., times at which the fluctuation contributes no error to the reference signal) occur at or near the ends 310 of sampling periods.

[0044] For illustrative purposes, the period of the fluctuation 306 is depicted in FIG. 3A as being the sampling period. Other alignments of the fluctuation period with the sampling period are also possible, such as the sampling period being an integer multiple of the fluctuation period, the fluctuation period being an integer multiple of the sampling period, and so on.

[0045] FIG. 3B illustrates an expected error 314 over time 304 during a sampling period for an example ADC circuit estimating a voltage of an analog input signal using error correction. Throughout the sampling period, the ADC circuit can estimate the voltage of the analog input signal by iteratively comparing the analog input signal with a reference signal. In general, the expected error of the voltage estimated by the ADC circuit decreases from the start 308 of the sampling period to the end 310 of the sampling period.

[0046] During a signal tracking and acquisition phase 316 of the sampling period, the ADC circuit can receive and fix a voltage of the analog input signal for the for the sampling period. During a conversion phase 318 of the sampling period, the ADC circuit can generate and refine an estimate for the voltage of the analog input signal for the sampling period. At the start of the conversion phase 318, the ADC circuit can determine an approximate initial estimate for the voltage of the analog input signal. At the end of the conversion phase 318, the ADC circuit can perform error correction to generate a final estimate for the voltage of the analog signal. For example, the ADC circuit can be an SAR ADC circuit with redundancy and can determine a final estimate for the voltage of the input signal during the conversion phase 318 by performing one or more redundant comparisons.

[0047] Towards the end 310 of the sampling period, the expected error 314 of the voltage estimated by the ADC circuit can fall below a threshold value 320. The threshold value 320 can represent a desired precision for the ADC circuit.

[0048] Aligning the zero 312 of the fluctuation 306 of the reference signal to the ADC circuit with the end 310 of sampling periods places the zero 312 within convergence interval 318. At the end of the conversion phase 318, the error contributed by the fluctuation 306 to the reference signal decreases to zero. This enables the error correction of the ADC circuit to correct for estimation errors caused by the fluctuation 306 throughout the rest of the sampling period.

[0049] FIG. 3C illustrates estimating a voltage for an analog input signal using an SAR ADC circuit during a sampling period for the SAR ADC circuit.

[0050] During a signal tracking and acquisition phase 316 of the sampling period, the SAR ADC circuit can receive and fix an acquired voltage 322 of the analog input signal for the for the sampling period. During a conversion phase 318 of the sampling penod, the SAR ADC circuit can determine a final estimated voltage 324 of the analog input signal by performing one or more comparisons (e.g., including redundant comparisons to perform error correction) between the acquired voltage 322 and the estimated voltage 324. At the end 310 of the sampling period, the SAR ADC circuit can output a digital signal representing the final estimated voltage 324 of the analog input signal for the sampling period.

[0051] FIG. 3D illustrates a reduction of estimation error resulting from error correction by an example frequency aligned ADC circuit.

[0052] As described above, the frequency aligned ADC circuit aligns a sampling period of the ADC circuit with a period of a fluctuation 306 of a reference signal of the ADC circuit to enable error correction of an ADC circuit to compensate for the fluctuation 306. During a conversion phase 318 of the sampling period, the ADC circuit estimates a voltage of an analog input signal using the error correction to compensate for estimation errors. For example, an SAR ADC circuit with redundance can estimate the voltage of an analog input signal for the sampling period by performing a series of voltage comparisons (e.g., including redundant comparisons for error correction) during the conversion phase 318. For illustrative purposes, the sampling period of the example frequency aligned ADC circuit is depicted as including 12 voltage comparisons, however a frequency aligned ADC circuit can estimate the voltage of an analog input signal for the sampling period by performing other numbers of voltage comparisons.

[0053] Throughout the conversion phase 318, the error correction mechanism of the frequency aligned ADC circuit has a time-varying correction tolerance 326. At any given time during the conversion phase 318, the correction tolerance 326 at the given time determines a maximal estimation error of the current estimated voltage (e.g., the current estimated voltage as of the given time) that the error correction mechanism can remove. If the estimation error of the estimated voltage exceeds the correction tolerance 326 during the conversion phase 318, the final estimated voltage for the sampling phase can include a remaining estimation error, l -emain|, that is not removed by the error correction mechanism. By aligning the sampling period of the ADC circuit with the period of the fluctuation 306, the frequency aligned ADC circuit can reduce the remaining estimation error caused by the fluctuation 306 of the reference signal and can therefore reduce or minimize a quantization error of the ADC circuit.

[0054] For example, without frequency alignment between ADC sampling and the fluctuations, a root-mean-square quantization error, EQ rms, for an n-bit ADC circuit can be:

[0055] Where is a magnitude of the voltage fluctuation 306 of the reference signal for the ADC circuit and VLSBis a least significant bit voltage difference for the ADC circuit.

[0056] However, with frequency alignment between ADC sampling and the fluctuations, the root-mean-square quantization error, EQ rms, for an n-bit frequency aligned ADC circuit can be reduced to:

[0057] As the frequency alignment and error correction of the frequency aligned ADC ensures that I

[0058] FIG. 4A illustrates an example frequency spectrum of a digital output signal generated by an ADC circuit without frequency alignment between ADC sampling and reference fluctuations. The digital output signal represented by the spectrum of FIG. 4A is generated by performing analog-to-digital conversion of an analog input signal utilizing a reference signal processed by a chopping amplifier. Processing the reference signal using the chopping amplifier introduces a ripple current into the reference signal. As illustrated, the digital output signal generated by the ADC circuit without frequency alignment includes a digital conversion of the input signal 402 and a higher-frequency fluctuation due the ripple current 404.

[0059] FIG. 4B illustrates an example frequency spectrum of a digital output signal generated by an ADC circuit with frequency alignment between ADC sampling and reference fluctuations as described above. The digital output signal represented by the spectrum of FIG. 4B is generated by performing analog-to-digital conversion of an analog input signal utilizing a reference signal processed by a chopping amplifier. Processing the reference signal using the chopping amplifier introduces a ripple current into the reference signal. As illustrated, the digital output signal generated by the ADC circuit with frequency alignment includes a digital conversion of the input signal 402.

[0060] The ADC circuit with frequency alignment attenuates the ripple current 404 of FIG. 4A without using a filter to remove the output fluctuations caused by the ripple current 404. As with the ADC circuit without frequency alignment illustrated in FIG. 4A, the ADC circuit with frequency alignment generates the digital output using reference signal that has fluctuations from the ripple current 404. However, the frequency alignment allows the ADC circuit with frequency alignment to remove the output fluctuations caused by the ripple current 404 using error correcting mechanisms of the ADC circuit.

[0061] Because the output fluctuations caused by the ripple current 404 can degrade the output signal (e.g., by decreasing a signal to noise ratio of the output signal), the ADC circuit with frequency alignment improves the output signal by removing the output fluctuations caused by the ripple current 404. With frequency alignment, the ADC circuit achieves a 7 dB signal to noise distortion ratio (SNDR) improvement without using additional components (e.g., additional filters).

[0062] Embodiments of the subject matter and the functional operations described in this specification can be implemented in digital electronic circuitry, in tangibly-embodied computer software or firmware, in computer hardware, including the structures disclosed in this specification and their structural equivalents, or in combinations of one or more of them. Embodiments of the subject matter described in this specification can be implemented as one or more computer programs, i.e., one or more modules of computer program instructions encoded on a tangible non-transitory storage medium for execution by, or to control the operation of, data processing apparatus. The computer storage medium can be a machine-readable storage device, a machine-readable storage substrate, a random or serial access memory device, or a combination of one or more of them. Alternatively or in addition, the program instructions can be encoded on an artificially -generated propagated signal, e.g., a machine-generated electrical, optical, or electromagnetic signal, that is generated to encode information for transmission to suitable receiver apparatus for execution by a data processing apparatus.

[0063] The term “data processing apparatus” refers to data processing hardware and encompasses all kinds of apparatus, devices, and machines for processing data, including by way of example a programmable processor, a computer, or multiple processors or computers. The apparatus can also be, or further include, special purpose logic circuitry, e.g., an FPGA (field programmable gate array) or an ASIC (application-specific integrated circuit). The apparatus can optionally include, in addition to hardware, code that creates an execution environment for computer programs, e.g., code that constitutes processor firmware, a protocol stack, a database management system, an operating system, or a combination of one or more of them.

[0064] A computer program which may also be referred to or described as a program, software, a software application, an app. a module, a software module, a script, or code) can be written in any form of programming language, including compiled or interpreted languages, or declarative or procedural languages, and it can be deployed in any form, including as a stand-alone program or as a module, component, subroutine, or other unit suitable for use in a computing environment. A program may, but need not, correspond to a file in a file system. A program can be stored in a portion of a file that holds other programs or data, e.g., one or more scripts stored in a markup language document, in a single file dedicated to the program in question, or in multiple coordinated files, e.g., files that store one or more modules, sub-programs, or portions of code. A computer program can be deployed to be executed on one computer or on multiple computers that are located at one site or distributed across multiple sites and interconnected by a data communication network.

[0065] For a system of one or more computers to be configured to perform particular operations or actions means that the system has installed on it software, firmware, hardware, or a combination of them that in operation cause the system to perform the operations or actions. For one or more computer programs to be configured to perform particular operations or actions means that the one or more programs include instructions that, when executed by data processing apparatus, cause the apparatus to perform the operations or actions.

[0066] As used in this specification, an “engine,” or “software engine,” refers to a software implemented input / output system that provides an output that is different from the input. An engine can be an encoded block of functionality, such as a library, a platform, a software development kit (“SDK”), or an object. Each engine can be implemented on any appropriate ty pe of computing device, e.g., servers, mobile phones, tablet computers, notebook computers, music players, e-book readers, laptop or desktop computers, PDAs, smart phones, or other stationary or portable devices, that includes one or more processors and computer readable media. Additionally, two or more of the engines may be implemented on the same computing device, or on different computing devices.

[0067] The processes and logic flows described in this specification can be performed by one or more programmable computers executing one or more computer programs to perform functions by operating on input data and generating output. The processes and logic flows can also be performed by special purpose logic circuitry, e.g., an FPGA or an ASIC, or by a combination of special purpose logic circuitry7and one or more programmed computers.

[0068] Computers suitable for the execution of a computer program can be based on general or special purpose microprocessors or both, or any other kind of central processing unit. Generally, a central processing unit will receive instructions and data from a read-only memory7or a random access memory7or both. The essential elements of a computer are a central processing unit for performing or executing instructions and one or more memory devices for storing instructions and data. The central processing unit and the memory can be supplemented by, or incorporated in, special purpose logic circuitry7. Generally, a computer will also include, or be operatively coupled to receive data from or transfer data to, or both, one or more mass storage devices for storing data, e.g., magnetic, magneto-optical disks, or optical disks. However, a computer need not have such devices. Moreover, a computer can be embedded in another device, e.g., a mobile telephone, a personal digital assistant (PDA), a mobile audio or video player, a game console, a Global Positioning System (GPS) receiver, or a portable storage device, e.g., a universal serial bus (USB) flash drive, to name just a few. Computer-readable media suitable for storing computer program instructions and data include all forms of non-volatile memory, media and memory devices, including by way of example semiconductor memory devices, e.g., EPROM, EEPROM, and flash memory devices; magnetic disks, e.g., internal hard disks or removable disks; magneto-optical disks; and CD-ROM and DVD-ROM disks.

[0069] To provide for interaction with a user, embodiments of the subject matter described in this specification can be implemented on a computer having a display device, e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor, for displaying information to the user and a keyboard and pointing device, e.g, a mouse, trackball, or a presence sensitive display or other surface by which the user can provide input to the computer. Other kinds of devices can be used to provide for interaction with a user as well; for example, feedback provided to the user can be any form of sensory feedback, e.g., visual feedback, auditory feedback, or tactile feedback; and input from the user can be received in any form, including acoustic, speech, or tactile input. In addition, a computer can interact with a user by sending documents to and receiving documents from a device that is used by the user; for example, by sending web pages to a web browser on a user’s device in response to requests received from the web browser. Also, a computer can interact with a user by sending text messages or other forms of message to a personal device, e.g., a smartphone, running a messaging application, and receiving responsive messages from the user in return.

[0070] Embodiments of the subject matter described in this specification can be implemented in a computing system that includes a back-end component, e.g., as a data server, or that includes a middleware component, e.g., an application server, or that includes a front-end component, e.g., a client computer having a graphical user interface, a web browser, or an app through which a user can interact with an implementation of the subject matter described in this specification, or any combination of one or more such back-end, middleware, or front-end components. The components of the system can be interconnected by any form or medium of digital data communication, e.g.. a communication network. Examples of communication networks include a local area network (LAN) and a wide area network (WAN), e.g., the Internet.

[0071] The computing system can include clients and servers. A client and server are generally remote from each other and typically interact through a communication network. The relationship of client and server arises by virtue of computer programs running on the respective computers and having a client-server relationship to each other. In some embodiments, a server transmits data, e.g., an HTML page, to a user device, e.g., for purposes of displaying data to and receiving user input from a user interacting with the device, which acts as a client. Data generated at the user device, e.g., a result of the user interaction, can be received at the server from the device.

[0072] In addition to the embodiments described above, the following embodiments are also innovative:

[0073] Embodiment 1 is a circuit, comprising: an analog-to-digital converter (ADC) circuit, and a voltage reference device configured to provide a reference signal to the ADC circuit; wherein the voltage reference device generates the reference signal with a timevarying fluctuation, wherein the ADC circuit has a sampling period and is configured to determine an estimated voltage after a conversion phase of each sampling period, and wherein the sampling period of the ADC circuit corresponds to a frequency of the timevarying fluctuation.

[0074] Embodiment 2 is the circuit of embodiment 1 , wherein the convergence phase is defined to be a particular length of time before the end of the sampling period.

[0075] Embodiment 3 is the circuit of embodiment 1 or embodiment 2, wherein the sampling period of the ADC circuit corresponds to a zero of the time-varying fluctuation.

[0076] Embodiment 4 is the circuit of any one of embodiments 1-3, wherein the time-varying fluctuation has a fluctuation period and wherein the sampling period of the ADC circuit is an integer multiple of the fluctuation period.

[0077] Embodiment 5 is the circuit of embodiment 4, wherein the sampling period of the ADC circuit is the fluctuation period.

[0078] Embodiment 6 is the circuit of any one of embodiments 1-5, wherein: the voltage reference device is a bandgap reference device comprising a chopping amplifier that generates the reference signal; and the time-varying fluctuation comprises a chopping ripple of the chopping amplifier.

[0079] Embodiment 7 is the circuit of any one of embodiments 1 -6, wherein the ADC circuit is configured to perform error correction for the estimated voltage during some or all of the conversion phase of each sampling period.

[0080] Embodiment 8 is the circuit of any one of embodiments 1 -7, wherein the ADC circuit is a Successive Approximation Register (SAR) ADC circuit.

[0081] Embodiment 9 is the circuit of embodiment 8, wherein the ADC circuit is an SAR ADC circuit with redundancy, configured to perform to perform one or more redundant voltage comparisons during the conversion phase of each sampling period. Embodiment 10 is the circuit of any one of embodiments 1-9, wherein the voltage reference device uses dynamic element matching.

[0082] Embodiment 11 is the circuit of any one of embodiments 1-10, wherein the ADC circuit is configured to convert an analog signal into a digital signal with at least ten bits.

[0083] Embodiment 12 is a method performed by an analog-to-digital converter (ADC) circuit, comprising: during a sampling period of the ADC circuit: receiving an analog input signal for the sampling period; receiving a reference signal from a voltage reference device, wherein the voltage reference device generates the reference signal with a timevarying fluctuation; determining an estimated voltage for the analog input signal for the sampling period after a conversion phase of each sampling period; and outputting a digital output signal representing the estimated voltage for the analog input signal for the sampling period; and wherein the sampling period of the ADC circuit corresponds to a frequency of the time-varying fluctuation.

[0084] Embodiment 13 is the method of embodiment 12, wherein the convergence phase is defined to be a particular length of time before the end of the sampling period.

[0085] Embodiment 14 is the method of embodiment 12 or embodiment 13, wherein the sampling period of the ADC circuit corresponds to a zero of the time-varying fluctuation.

[0086] Embodiment is the method of any one of embodiments 12-14, wherein the timevarying fluctuation has a fluctuation period and wherein the sampling period of the ADC circuit is an integer multiple of the fluctuation period.

[0087] Embodiment 16 is the method of embodiment 15, wherein the sampling period of the ADC circuit is the fluctuation period.

[0088] Embodiment 17 is the method of any one of embodiments 12-16, wherein: the voltage reference device is a bandgap reference device comprising a chopping amplifier that generates the reference signal; and the time-varying fluctuation comprises a chopping ripple of the chopping amplifier.

[0089] Embodiment 18 is the method of any one of embodiments 12-17, further comprising, during some or all of the conversion phase of the sampling period: performing error correction for the estimated voltage.

[0090] Embodiment 19 is the method of any one of embodiments 12-18, wherein the ADC circuit is a Successive Approximation Register (SAR) ADC circuit.

[0091] Embodiment 20 is the method of embodiment 19, wherein: the ADC circuit is an SAR ADC circuit with redundancy; and performing error correction for the estimated voltage comprises performing one or more redundant voltage comparisons during the conversion phase of the sampling period.

[0092] Embodiment 21 is the method of any one of embodiments 12-20, wherein the voltage reference device uses dynamic element matching.

[0093] Embodiment 22 is the method of any one of embodiments 12-22, wherein the digital output signal comprises at least ten bits.

[0094] While this specification contains many specific implementation details, these should not be construed as limitations on the scope of any invention or on the scope of what may be claimed, but rather as descriptions of features that may be specific to particular embodiments of particular inventions. Certain features that are described in this specification in the context of separate embodiments can also be implemented in combination in a single embodiment. Conversely, various features that are described in the context of a single embodiment can also be implemented in multiple embodiments separately or in any suitable subcombination. Moreover, although features may be described above as acting in certain combinations and even initially be claimed as such, one or more features from a claimed combination can in some cases be excised from the combination, and the claimed combination may be directed to a subcombination or variation of a subcombination.

[0095] Similarly, while operations are depicted in the drawings in a particular order, this should not be understood as requiring that such operations be performed in the particular order shown or in sequential order, or that all illustrated operations be performed, to achieve desirable results. In certain circumstances, multitasking and parallel processing may be advantageous. Moreover, the separation of various system modules and components in the embodiments described above should not be understood as requiring such separation in all embodiments, and it should be understood that the described program components and systems can generally be integrated together in a single software product or packaged into multiple software products.

[0096] Particular embodiments of the subject matter have been described. Other embodiments are within the scope of the following claims. For example, the actions recited in the claims can be performed in a different order and still achieve desirable results. As one example, the processes depicted in the accompanying figures do not necessarily require the particular order shown, or sequential order, to achieve desirable results. In certain implementations, multitasking and parallel processing may be advantageous.

Claims

CLAIMS1 . A circuit, comprising: an analog-to-digital converter (ADC) circuit, and a voltage reference device configured to provide a reference signal to the ADC circuit; wherein the voltage reference device generates the reference signal with a timevarying fluctuation, wherein the ADC circuit has a sampling period and is configured to determine an estimated voltage after a conversion phase of each sampling period, and wherein the sampling period of the ADC circuit corresponds to a frequency of the time-varying fluctuation.

2. The circuit of claim 1, wherein the convergence phase is defined to be a particular length of time before the end of the sampling period.

3. The circuit of claim 1 or claim 2, wherein the sampling period of the ADC circuit corresponds to a zero of the time-varying fluctuation.

4. The circuit of any preceding claim, wherein the time-varying fluctuation has a fluctuation period and wherein the sampling period of the ADC circuit is an integer multiple of the fluctuation period.

5. The circuit of claim 4, wherein the sampling period of the ADC circuit is the fluctuation period.

6. The circuit of any preceding claim, wherein: the voltage reference device is a bandgap reference device comprising a chopping amplifier that generates the reference signal; and the time-varying fluctuation comprises a chopping ripple of the chopping amplifier.

7. The circuit of any preceding claim, wherein the ADC circuit is configured to perform error correction for the estimated voltage during some or all of the conversion phase of each sampling period.

8. The circuit of any preceding claim, wherein the ADC circuit is a Successive Approximation Register (SAR) ADC circuit.

9. The circuit of claim 8, wherein the ADC circuit is an SAR ADC circuit with redundancy, configured to perform to perform one or more redundant voltage comparisons during the conversion phase of each sampling period.

10. The circuit of any preceding claim, wherein the voltage reference device uses dynamic element matching.1 1. The circuit of any preceding claim, wherein the ADC circuit is configured to convert an analog signal into a digital signal with at least ten bits.

12. A method performed by an analog-to-digital converter (ADC) circuit, comprising: during a sampling period of the ADC circuit: receiving an analog input signal for the sampling period; receiving a reference signal from a voltage reference device, wherein the voltage reference device generates the reference signal with a time- varying fluctuation; determining an estimated voltage for the analog input signal for the sampling period after a conversion phase of each sampling period; and outputting a digital output signal representing the estimated voltage for the analog input signal for the sampling period; and wherein the sampling period of the ADC circuit corresponds to a frequency of the time-varying fluctuation.

13. The method of claim 12, wherein the convergence phase is defined to be a particular length of time before the end of the sampling period.

14. The method of claim 12 or claim 13, wherein the sampling period of the ADC circuit corresponds to a zero of the time-varying fluctuation.

15. The method of any one of claims 12-14, wherein the time-varying fluctuation has a fluctuation period and wherein the sampling period of the ADC circuit is an integer multiple of the fluctuation period.

16. The method of claim 15, wherein the sampling period of the ADC circuit is the fluctuation period.

17. The method of any one of claims 12-16, wherein: the voltage reference device is a bandgap reference device comprising a chopping amplifier that generates the reference signal; and the time-varying fluctuation comprises a chopping ripple of the chopping amplifier.

18. The method of any one of claims 12-17, further comprising, during some or all of the conversion phase of the sampling period: performing error correction for the estimated voltage.

19. The method of any one of claims 12-18, wherein the ADC circuit is a Successive Approximation Register (SAR) ADC circuit.

20. The method of claim 19, wherein: the ADC circuit is an SAR ADC circuit with redundancy; and performing error correction for the estimated voltage comprises performing one or more redundant voltage comparisons during the conversion phase of the sampling period.

21. The method of any one of claims 12-20, wherein the voltage reference device uses dynamic element matching.

22. The method of any one of claims 12-21, wherein the digital output signal comprises at least ten bits.

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