FPGA-based circuit system for balancing clock skew and control method

Abstract

The present invention provides an FPGA-based circuit system for balancing clock skew and a control method. The system comprises: a hard core circuit module comprising a clock source unit, a delay control unit and a first interaction unit, wherein the clock source unit generates a source clock, and the delay control unit generates a delay clock and an in-phase signal on the basis of the source clock and an in-core source clock; and an FPGA module comprising a clock dedicated wire unit and a second interaction unit, wherein the clock dedicated wire unit generates the in-core source clock on the basis of the delay clock, the first interaction unit transmits and receives data under the control of the source clock and the in-phase signal, and the second interaction unit transmits and receives data under the control of the in-core source clock and the in-phase signal. In this way, the delay control unit is used to balance clock skew between a register at a clock source end and a register on an FPGA, so that the FPGA module can effectively reduce the clock skew without increasing hardware resources, thereby solving the problem of how to effectively balance the clock skew without increasing FPGA hardware resources.

Description

Circuit system and control method for balancing clock skew based on FPGA

[0001] Cross-reference to related applications

[0002] This application claims priority to Chinese application No. 202410754856.1, filed on June 12, 2024. The contents of the aforementioned application are hereby incorporated by reference. TECHNICAL FIELD

[0003] The present application relates to the technical field of integrated circuits, in particular to a circuit system and control method for balancing clock skew based on FPGA. TECHNICAL BACKGROUND

[0004] FPGA (Field Programmable Gate Array) is a product further developed on the basis of PAL (Programmable Array Logic), GAL (Generic Array Logic) and other programmable devices. It is a semi-custom circuit in the field of ASIC (Application Specific Integrated Circuit) and solves the shortcomings of custom circuits and overcomes the limitation of the number of gate circuits of the original programmable devices.

[0005] With the deepening of the process, the logic capacity of FPGA devices is getting larger and larger, and the signal wiring is getting more and more complex, especially for the clock wiring of FPGA. Generally, the modules in the FPGA core need to be wired with a dedicated clock wiring to ensure that each point on the clock wiring has a relatively small clock skew. However, the dedicated clock wiring requires a long clock path delay, which results in a large clock skew between the register at the clock source end and the register on the FPGA, and further causes the timing violation between the registers and makes it difficult to repair, resulting in low running efficiency of the FPGA and thus reducing the performance of the FPGA.

[0006] In order to solve the clock skew between the register at the clock source end and the register on the FPGA, a phase-locked loop (PLL) is usually used to correct the phase of the source clock at the clock source end and the core-in source clock at the FPGA, thereby reducing the clock skew; or, a first-in-first-out (FIFO) memory is used to cache data to compensate for the clock skew. TECHNICAL PROBLEM

[0007] Since the phase-locked loop is an analog circuit, the area is large, if the phase-locked loop is set for each module in the FPGA, the area of the FPGA will be increased, which is not conducive to the miniaturization design of the FPGA; in addition, whether the phase-locked loop can be phase-locked depends on the reference clock, so an additional reference clock needs to be introduced, which will waste the input and output (IO) resources of the FPGA. The use of FIFO will increase the data delay, and when the clock frequency is deviated, the error code will be introduced, thereby causing the system confusion. Therefore, the existing two solutions to solve the clock skew are not conducive to practical application. Technical solutions

[0008] The purpose of the present application is to provide a FPGA-based balanced clock skew circuit system and control method to at least solve the problem of how to effectively balance the clock skew without increasing the FPGA hardware resources.

[0009] To solve the above technical problems, the present application provides a FPGA-based balanced clock skew circuit system, comprising:

[0010] The hard core circuit module comprises a clock source unit, a delay control unit and a first interaction unit; the clock source unit is used to generate a source clock; the delay control unit is used to generate a delay clock according to the source clock, and is also used to generate a phase-identical signal according to the source clock and the in-core source clock; the first interaction unit is used to transmit and receive data with the second interaction unit under the control of the source clock and the phase-identical signal;

[0011] The FPGA module comprises a clock dedicated wiring unit and a second interaction unit; the clock dedicated wiring unit is used to generate the in-core source clock according to the delay clock; the second interaction unit is used to transmit and receive data with the first interaction unit under the control of the in-core source clock and the phase-identical signal.

[0012] Optionally, in the FPGA-based balanced clock skew circuit system, the delay control unit comprises a delay controller and a delay clock generator; the delay controller is used to generate a delay code and a phase-identical signal according to the source clock and the in-core source clock; the delay clock generator is used to delay the source clock according to the delay code to obtain the delay clock.

[0013] Optionally, in the FPGA-based balanced clock skew circuit system, the delay controller comprises a digital phase discriminator and an encoder; the digital phase discriminator is used to detect whether the phases of the source clock and the in-core source clock are consistent, and outputs a phase discrimination signal according to the detection result; the encoder is used to output a phase-identical signal and / or a delay code signal according to the phase discrimination signal under the control of the source clock.

[0014] Optionally, in the circuit system for balancing clock skew based on FPGA, the digital phase detector is a register; a CK terminal of the register is connected to the source clock, a D terminal is connected to the in-core source clock, and a Q terminal outputs a phase detection signal, so as to sample the in-core source clock by taking the source clock as a sampling clock, and to obtain the phase of the in-core source clock at the rising edge of the source clock.

[0015] Optionally, in the circuit system for balancing clock skew based on FPGA, the delay clock generator comprises a plurality of buffers and a multiplexer, the number of the buffers is consistent with the number of input terminals of the multiplexer, and the output terminal of each buffer is connected to one input terminal of the multiplexer in one-to-one correspondence; the output terminal of each buffer is connected to the input terminal of the next buffer, and the input terminal of the first buffer receives the source clock; the multiplexer is used for switching the corresponding input terminal according to the delay code to output the delay clock.

[0016] Optionally, in the circuit system for balancing clock skew based on FPGA, the first interaction unit comprises a first transmitter and a first receiver; the first transmitter and the first receiver each comprise a first register, an interaction logic controller and a second register; the clock terminals of the first register and the second register are connected to the source clock, and the enable terminals of the interaction logic controllers are connected to the phase same signal;

[0017] the output terminal of the first register in the first transmitter is connected to the input terminal of the interaction logic controller in the first transmitter, the output terminal of the interaction logic controller in the first transmitter is connected to the input terminal of the second register in the first transmitter, and the output terminal of the second register in the first transmitter is connected to the second interaction unit, so as to realize the transmission of data;

[0018] the input terminal of the first register in the first receiver is connected to the second interaction unit, the output terminal is connected to the input terminal of the interaction logic controller in the first receiver, the output terminal of the interaction logic controller in the first receiver is connected to the input terminal of the second register in the first receiver, so as to realize the reception of data.

[0019] Optionally, in the circuit system for balancing clock skew based on FPGA, the second interaction unit comprises a second transmitter and a second receiver; the second transmitter and the second receiver each comprise a third register and a user logic controller; the clock terminals of the third register and the clock terminals of the user logic controllers are connected to the in-core source clock, and the enable terminals of the user logic controllers are connected to the phase same signal.

[0020] An output end of the third register in the second transmitter is connected with an input end of the first register in the first receiver, and an input end of the third register in the second transmitter is connected with an output end of the user logic controller in the second transmitter, so as to realize data transmission.

[0021] An input end of the third register in the second receiver is connected with an output end of the second register in the first transmitter, and an output end of the third register in the second receiver is connected with an input end of the user logic controller in the second receiver, so as to realize data reception.

[0022] Optionally, in the circuit system for balancing clock skew based on FPGA, the first register, the second register and the third register are all D flip-flops, the CK end of the D flip-flop is a clock end, the D end is an input end, and the Q end is an output end.

[0023] To solve the above technical problems, the application further provides a circuit system control method applied to the circuit system for balancing clock skew based on FPGA, and the circuit system control method comprises the following steps of:

[0024] a source clock is provided by a clock source unit, and an internal source clock is provided by a clock dedicated wiring unit;

[0025] a delay clock and a phase same signal are generated according to the source clock and the internal source clock by using a delay control unit;

[0026] the delay clock is sent into the clock dedicated wiring unit, the source clock is used as a clock signal of a first interaction unit, the internal source clock is used as a clock signal of a second interaction unit, and the phase same signal is used as an enable signal of the first interaction unit and the second interaction unit;

[0027] data transmission and reception between the first interaction unit and the second interaction unit are realized according to the clock signal and the enable signal.

[0028] Optionally, in the circuit system control method, the delay control unit comprises a delay controller and a delay clock generator, the delay controller comprises a digital phase discriminator and an encoder, and the method for generating the delay clock and the phase same signal according to the source clock and the internal source clock comprises the following steps of:

[0029] the source clock and the internal source clock are simultaneously sent into the digital phase discriminator;

[0030] the internal source clock is sampled by using the source clock in the digital phase discriminator;

[0031] the phase same signal and a delay encoding signal are generated according to a sampling result by using the encoder;

[0032] The delayed clock signal is sent to a delay clock generator to obtain a delayed clock.

[0033] Optionally, in the circuit system control method, the method of generating the phase-identical signal and the delayed clock signal according to the sampling result comprises:

[0034] The digital phase detector continuously samples regardless of the sampling result, and the encoder generates a corresponding delayed clock signal, wherein the delayed clock signal generated after each sampling is not completely identical;

[0035] Or, if the phase of the source clock and the in-core source clock is consistent, the encoder outputs a high-level phase-identical signal, and stops sampling when the phase signal output by the digital phase detector after sampling appears a rising edge, and the encoder generates a corresponding delayed clock signal. Advantages

[0036] The circuit system and the control method for balancing clock skew based on the FPGA provided by the application balance the clock skew between the register at the clock source end and the register on the FPGA by using the delay control unit, so that the FPGA module can effectively reduce the clock skew without increasing the hardware resources, and the problem of how to effectively balance the clock skew without increasing the FPGA hardware resources is solved. BRIEF DESCRIPTION OF DRAWINGS

[0037] Fig. 1 is a structural block diagram of the circuit system for balancing clock skew based on the FPGA provided by the embodiment;

[0038] Fig. 2 is a structural schematic diagram of the delay control unit provided by the embodiment;

[0039] Fig. 3 is a structural schematic diagram of the delay controller provided by the embodiment;

[0040] Fig. 4 is a structural schematic diagram of the digital phase detector provided by the embodiment;

[0041] Fig. 5 is a structural schematic diagram of the delay clock generator provided by the embodiment;

[0042] Fig. 6 is a detailed structural schematic diagram of the circuit system for balancing clock skew based on the FPGA provided by the embodiment;

[0043] Fig. 7 is a flow chart of the circuit system control method provided by the embodiment. Embodiment of the application

[0044] The circuit system for balancing clock skew based on FPGA and the control method are further described in detail below in combination with the drawings and specific embodiments. It should be noted that the drawings are very simplified and non-precise in proportion, and are only used for the purpose of conveniently and clearly assisting in the description of the embodiments of the present application. In addition, the structures shown in the drawings are often a part of the actual structures. In particular, different proportions are sometimes used in the drawings to show different focuses.

[0045] It should be noted that "first", "second", and the like in the description, claims, and drawings of the present application are used to distinguish similar objects in order to describe the embodiments of the present application, and are not intended to describe a specific order or sequence. It should be understood that the structures used in this way can be interchanged under appropriate circumstances. In addition, the terms "include" and "have" and any variations thereof are intended to cover non-exclusive inclusion, for example, a process, method, system, product, or device that includes a series of steps or units does not have to be limited to those steps or units clearly listed, but can include other steps or units that are not clearly listed or inherent to these processes, methods, products, or devices.

[0046] The embodiment provides a circuit system for balancing clock skew based on FPGA, as shown in FIG. 1, which comprises:

[0047] The hard core circuit module comprises a clock source unit, a delay control unit, and a first interaction unit; the clock source unit is used for generating a source clock; the delay control unit is used for generating a delay clock according to the source clock, and is also used for generating a phase-same signal according to the source clock and the core-in source clock; and the first interaction unit is used for performing data transmission and reception with the second interaction unit under the control of the source clock and the phase-same signal.

[0048] The FPGA module comprises a clock dedicated wiring unit and a second interaction unit; the clock dedicated wiring unit is used for generating the core-in source clock according to the delay clock; and the second interaction unit is used for performing data transmission and reception with the first interaction unit under the control of the core-in source clock and the phase-same signal.

[0049] The circuit system for balancing clock skew based on FPGA provided by the embodiment generates a delay clock and a phase-same signal according to the source clock and the core-in source clock through the delay control unit arranged in the hard core circuit module, and realizes data interaction between the second interaction unit in the FPGA module and the first interaction unit in the hard core circuit module through the delay clock and the phase-same signal. In this way, the clock skew between the register at the clock source end and the register on the FPGA is balanced by using the delay control unit, so that the FPGA module can effectively reduce the clock skew without increasing hardware resources, thereby solving the problem of how to effectively balance the clock skew without increasing FPGA hardware resources.

[0050] Further, in the embodiment, as shown in FIG. 2, the delay control unit comprises a delay controller and a delay clock generator; the delay controller is configured to generate a delay code and a phase same signal according to the source clock and the in-core source clock; and the delay clock generator is configured to delay the source clock according to the delay code to obtain a delay clock.

[0051] Specifically, in the embodiment, as shown in FIG. 3, the delay controller comprises a digital phase detector and an encoder; the digital phase detector is configured to detect whether the phases of the source clock and the in-core source clock are consistent, and output a phase detection signal according to the detection result; and the encoder is configured to output a phase same signal and / or a delay code signal according to the phase detection signal under the control of the source clock. In the embodiment, when the digital phase detector detects that the phases of the source clock and the in-core source clock are consistent, the output phase detection signal is high, otherwise, the output phase detection signal is low; and the phase same signal output by the encoder is consistent with the phase detection signal, that is, when the phase detection signal is high, the phase same signal is high.

[0052] In actual application, the digital phase detector can be a register, for example, a D flip-flop (DFF). As shown in FIG. 4, the CK end of the register is connected to the source clock, the D end is connected to the in-core source clock, and the Q end outputs the phase detection signal, so as to sample the in-core source clock by taking the source clock as a sampling clock to obtain the phase of the in-core source clock at the rising edge of the source clock.

[0053] Further, in the embodiment, as shown in FIG. 5, the delay clock generator comprises a multiplexer and a plurality of cascaded buffers, the number of the buffers is consistent with the number of the input ends of the multiplexer, and the output end of each buffer is connected to one input end of the multiplexer in one-to-one correspondence; the output end of each buffer is connected to the input end of the next buffer, and the input end of the first buffer receives the source clock; and the multiplexer is configured to connect the corresponding input end according to the delay code to output the delay clock.

[0054] In actual application, the delay of each buffer is about 50 ps, that is, the signal obtained by the No. 0 port of the multiplexer after being delayed by the first buffer Buff0 is delayed by about 50 ps compared with the source clock; the signal obtained by the No. 1 port of the multiplexer after being delayed by the first buffer Buff0 and the second buffer Buff1 is delayed by about 100 ps compared with the source clock; in this way, the signal obtained by the next port is delayed by the delay time of the buffer connected by the previous port, so that the signals obtained by each port are different in delay. When the delay code is input to the multiplexer, the signal on the corresponding port of the multiplexer is selected, so that the signal delayed for a certain time compared with the source clock, that is, the delay clock, is obtained. The delay clock is only different from the source clock in delay, and the logic is completely the same.

[0055] In the embodiment, the delay of the buffer of each stage is consistent. Of course, in other embodiments, the delay of the buffer of each stage can also be different, or the number of buffers connected to each port of the multiplexer can also be different, and a multiplexer with more port numbers and a corresponding number of buffers can be selected according to actual needs, and the present application does not limit this. However, in order to ensure that the actual delay between the delay clock and the source clock is within a controllable range, it is necessary to ensure that the delay precision of the buffer is 20-50 ps.

[0056] Further, in the embodiment, the first interaction unit includes a first transmitter and a first receiver; the first transmitter and the first receiver each include a first register, an interaction logic controller, and a second register; the clock terminals of the first register and the second register are each connected to a source clock, and the enable terminals of the interaction logic controllers are each connected to a phase-same signal.

[0057] Specifically, as shown in FIG. 6, the output terminal Q of the first register DFF11 in the first transmitter is connected to the input terminal of the interaction logic controller in the first transmitter, the output terminal of the interaction logic controller in the first transmitter is connected to the input terminal D of the second register DFF12 in the first transmitter, and the output terminal Q of the second register DFF12 in the first transmitter is connected to the second interaction unit to realize data transmission. The input terminal D of the first register DFF21 in the first receiver is connected to the second interaction unit, the output terminal Q is connected to the input terminal of the interaction logic controller in the first receiver, the output terminal of the interaction logic controller in the first receiver is connected to the input terminal D of the second register DFF22 in the first receiver, to realize data reception.

[0058] In addition, in the embodiment, the second interaction unit includes a second transmitter and a second receiver; the second transmitter and the second receiver each include a third register and a user logic controller; the clock terminals of the third register and the clock terminals of the user logic controllers are each connected to an in-core source clock, and the enable terminals of the user logic controllers are connected to a phase-same signal.

[0059] Specifically, as shown in FIG. 6, the output end Q of the third register DFF3 in the second transmitter is connected with the input end D of the first register DFF21 in the first receiver, and the input end D of the third register DFF3 in the second transmitter is connected with the output end of the user logic controller in the second transmitter, so as to realize the transmission of data. The input end D of the third register DFF4 in the second receiver is connected with the output end Q of the second register DFF12 in the first transmitter, and the output end Q of the third register DFF4 in the second receiver is connected with the input end of the user logic controller in the second receiver, so as to realize the reception of data.

[0060] Thus, in the hard core circuit module, the first register DFF11 and the second register DFF12 in the first transmitter, the first register DFF21 and the second register DFF22 in the first receiver, and the delay controller and the delay clock generator all receive the same source clock (the source clock received by each device in the hard core circuit module has the same delay length), so as to ensure that the clock skew between each register in the hard core circuit module is very small. In the FPGA module, the clock dedicated wiring unit generates the in-core source clock according to the delay clock provided by the delay clock generator, and provides the in-core source clock to the third register DFF3 and the user logic controller in the second transmitter, and to the third register DFF4 and the user logic controller in the second receiver (the in-core source clock received by each device in the FPGA module has the same delay length), so as to ensure that the clock skew between each register in the FPGA module is very small. At the same time, the clock dedicated wiring unit in the FPGA module is controlled by the delay clock, that is, the phase adjustment of the clock is realized through the delay control unit in the hard core circuit module, so that the clock skew between the registers in the hard core circuit module and the registers in the FPGA module is very small.

[0061] In actual application, the first register, the second register and the third register can all be D flip-flops. The CK end of the D flip-flop is the clock end, the D end is the input end, and the Q end is the output end.

[0062] The embodiment also provides a circuit system control method, which is applied to the circuit system for balancing clock skew based on FPGA as described above, as shown in FIG. 7, the circuit system control method comprises the following steps:

[0063] S1, providing a source clock by a clock source unit, and providing an in-core source clock by a clock dedicated wiring unit;

[0064] S2, generating a delay clock and a phase same signal according to the source clock and the in-core source clock by a delay control unit;

[0065] S3, sending the delay clock into the clock dedicated trace unit, taking the source clock as the clock signal of the first interaction unit, taking the in-core source clock as the clock signal of the second interaction unit, and taking the phase same signal as the enable signal of the first interaction unit and the second interaction unit;

[0066] S4, realizing the data transceiving between the first interaction unit and the second interaction unit according to the clock signal and the enable signal.

[0067] Further, in the embodiment, the delay control unit comprises a delay controller and a delay clock generator, and the delay controller comprises a digital phase detector and an encoder. The method for generating the delay clock and the phase same signal according to the source clock and the in-core source clock comprises:

[0068] S21, sending the source clock and the in-core source clock into the digital phase detector at the same time.

[0069] S22, sampling the in-core source clock using the source clock in the digital phase detector.

[0070] S23, generating the phase same signal and the delay encoding signal according to the sampling result using the encoder.

[0071] Specifically, in the embodiment, the digital phase detector continuously samples regardless of the sampling result, and the encoder generates the corresponding delay encoding signal, wherein the delay encoding signal generated after each sampling is not completely the same.

[0072] Or, if the phases of the source clock and the in-core source clock are consistent, the encoder outputs the phase same signal with high level, and when the phase detection signal output after the sampling of the digital phase detector appears the rising edge, the sampling is stopped, and the encoder generates the corresponding delay encoding signal.

[0073] S24, sending the delay encoding signal into the delay clock generator to obtain the delay clock.

[0074] At this time, the encoder stops running, and the phase same signal outputs high level, enabling the interaction logic controller of the hard core circuit module and the user logic controller of the FPGA module, so as to realize the data transceiving of the two. Under the logic control provided in the embodiment, the clock skew between the registers in the system can be ensured to be almost 0.

[0075] The circuit system and control method for balancing clock skew based on FPGA provided in the embodiment balance the interface problem between FPGA and hard core circuit by adding a delay control unit in the hard core circuit module, and improve the performance of FPGA; the circuit system for balancing clock skew based on FPGA is realized by all-digital circuit, so the overall power consumption is much lower than the scheme using phase-locked loop; the circuit system and control method for balancing clock skew based on FPGA can realize clock phase adjustment through source clock and in-core source clock, without introducing an additional reference clock, so it does not increase the cycle consumption, and the data waiting time is short; the circuit system and control method for balancing clock skew based on FPGA has a simple operation mechanism, without confirming the accurate delay of each stage, and without complex logic control, only through the digital phase discriminator, encoder and delay clock generator of the delay control unit, the delay can be pushed to the same phase as the source clock.

[0076] It should be noted that each embodiment in the specification is described in a progressive manner, and each embodiment focuses on the difference from other embodiments. The same or similar parts of each embodiment can be referred to each other. In addition, the different parts of each embodiment can also be used with each other, and the application is not limited in this regard.

[0077] The circuit system and control method for balancing clock skew based on FPGA provided in the application comprise: a hard core circuit module comprising a clock source unit, a delay control unit and a first interaction unit; the clock source unit is used to generate a source clock; the delay control unit is used to generate a delay clock according to the source clock, and is also used to generate a phase same signal according to the source clock and an in-core source clock; the first interaction unit is used to perform data transmission and reception with a second interaction unit under the control of the source clock and the phase same signal; an FPGA module comprising a clock dedicated wiring unit and a second interaction unit; the clock dedicated wiring unit is used to generate the in-core source clock according to the delay clock; the second interaction unit is used to perform data transmission and reception with the first interaction unit under the control of the in-core source clock and the phase same signal. The delay control unit provided in the hard core circuit module generates a delay clock and a phase same signal according to the source clock and the in-core source clock, and realizes data interaction between the second interaction unit in the FPGA module and the first interaction unit in the hard core circuit module through the delay clock and the phase same signal. In this way, the delay control unit is used to balance the clock skew between the register of the clock source end and the register on the FPGA, so that the FPGA module can effectively reduce the clock skew without increasing hardware resources, and solve the problem of how to effectively balance the clock skew without increasing FPGA hardware resources.

[0078] The above description is only a description of the preferred embodiments of the present application, and is not any limitation on the scope of the present application, and any modification or change made by the person skilled in the art according to the above disclosure is within the protection scope of the claims. Industrial applicability

[0079] The circuit system and control method for balancing clock skew based on FPGA provided in the embodiment balance the interface problem between FPGA and hard core circuit, and improve the performance of FPGA by adding a delay control unit in the hard core circuit module;

[0080] The circuit system for balancing clock skew based on FPGA provided in the embodiment is implemented by all-digital circuit, so the overall power consumption is much lower than the scheme using phase-locked loop;

[0081] The circuit system and control method for balancing clock skew based on FPGA provided in the embodiment can realize the adjustment of clock phase by source clock and core-in source clock, without introducing an additional reference clock, so that the period consumption is not additionally increased, and the waiting time of data is short;

[0082] The circuit system and control method for balancing clock skew based on FPGA provided in the embodiment have a simple operation mechanism, without the need to confirm the accurate delay of each stage, and without the need for complex logic control, but only through the digital phase discriminator, encoder and delay clock generator of the delay control unit to push the delay to the same phase as the source clock.

Claims

1. A circuit system for balancing clock skew based on FPGA, characterized in that, The application relates to a hard core circuit module, an FPGA module and a method for generating a delay clock. The hard core circuit module comprises a clock source unit, a delay control unit and a first interaction unit; the clock source unit is used for generating a source clock; The delay control unit is used for generating a delay clock according to the source clock and generating a phase-identical signal according to the source clock and the in-core source clock; and the first interaction unit is used for transmitting and receiving data with a second interaction unit under the control of the source clock and the phase-identical signal. The FPGA module comprises a clock special-purpose wiring unit and the second interaction unit; the clock special-purpose wiring unit is used for generating an in-core source clock according to the delay clock; and the second interaction unit is used for transmitting and receiving data with the first interaction unit under the control of the in-core source clock and the phase-identical signal.

2. The FPGA-based circuitry to balance clock skew of claim 1, wherein, The delay control unit comprises a delay controller and a delay clock generator; the delay controller is used for generating a delay code and a phase-identical signal according to the source clock and the in-core source clock; and the delay clock generator is used for delaying the source clock according to the delay code to obtain the delay clock.

3. The FPGA-based circuitry to balance clock skew of claim 2, wherein, The delay controller comprises a digital phase discriminator and an encoder; the digital phase discriminator is used for detecting whether the phases of the source clock and the in-core source clock are identical and outputting a phase discrimination signal according to a detection result; and the encoder is used for outputting the phase-identical signal and / or a delay code signal according to the phase discrimination signal under the control of the source clock.

4. The FPGA-based circuitry to balance clock skew of claim 3, wherein, The digital phase discriminator is a register; a CK end of the register is connected with the source clock, a D end of the register is connected with the in-core source clock, and a Q end of the register outputs the phase discrimination signal; the source clock is used as a sampling clock to sample the in-core source clock, and the phase of the in-core source clock at the rising edge of the source clock is obtained.

5. The FPGA-based circuitry to balance clock skew of claim 2, wherein, The delay clock generator comprises a multiplexer and a plurality of cascaded buffers; the number of the buffers is consistent with the number of input ends of the multiplexer, and the output end of each buffer is connected with one input end of the multiplexer in one-to-one correspondence; the output end of each buffer is connected with the input end of a next-stage buffer, and the input end of the first-stage buffer receives the source clock; and the multiplexer is used for connecting the corresponding input end according to the delay code to output the delay clock.

6. The FPGA-based circuitry to balance clock skew of claim 1, wherein, The first interaction unit comprises a first transmitter and a first receiver; the first transmitter and the first receiver each comprise a first register, an interaction logic controller and a second register; the clock ends of the first register and the second register are connected with the source clock, and the enable ends of the interaction logic controllers are connected with the phase-identical signal; The output end of the first register in the first transmitter is connected with the input end of the interaction logic controller in the first transmitter, the output end of the interaction logic controller in the first transmitter is connected with the input end of the second register in the first transmitter, the output end of the second register in the first transmitter is connected with the second interaction unit, and data transmission is realized. An input end of a first register in the first receiver is connected with the second interaction unit, and an output end of the first register is connected with an input end of an interaction logic controller in the first receiver. An output end of the interaction logic controller in the first receiver is connected with an input end of a second register in the first receiver to realize data receiving.

7. The FPGA-based circuitry to balance clock skew of claim 6, wherein, The second interaction unit comprises a second transmitter and a second receiver. The second transmitter and the second receiver each comprise a third register and a user logic controller. A clock end of the third register and a clock end of the user logic controller are connected with an internal source clock. An enable end of the user logic controller is connected with a same-phase signal. An output end of the third register in the second transmitter is connected with an input end of the first register in the first receiver. An input end of the third register in the second transmitter is connected with an output end of the user logic controller in the second transmitter to realize data sending. An input end of the third register in the second receiver is connected with an output end of the second register in the first transmitter. An output end of the third register in the second receiver is connected with an input end of the user logic controller in the second receiver to realize data receiving. The first register, the second register and the third register are all D flip-flops. A CK end of the D flip-flop is a clock end, a D end is an input end, and a Q end is an output end.

8. The FPGA-based circuitry to balance clock skew of claim 7, wherein, The circuit system control method comprises:

9. A circuit system control method applied to the circuit system for balancing clock skew based on FPGA according to any one of claims 1-8, characterized in that, providing a source clock by a clock source unit and providing an internal source clock by a clock dedicated wire unit; generating a delay clock and a same-phase signal according to the source clock and the internal source clock by a delay control unit; sending the delay clock into the clock dedicated wire unit, taking the source clock as a clock signal of a first interaction unit, taking the internal source clock as a clock signal of a second interaction unit, and taking the same-phase signal as an enable signal of the first interaction unit and the second interaction unit; realizing data transmission and reception between the first interaction unit and the second interaction unit according to the clock signal and the enable signal. The delay control unit comprises a delay controller and a delay clock generator. The delay controller comprises a digital phase discriminator and an encoder. The method of generating the delay clock and the same-phase signal according to the source clock and the internal source clock comprises:

10. The circuit system control method according to claim 9, wherein sending the source clock and the internal source clock into the digital phase discriminator at the same time; sampling the internal source clock by using the source clock in the digital phase discriminator; generating the same-phase signal and a delay encoding signal according to a sampling result by using the encoder; and sending the delay encoding signal into the delay clock generator to obtain the delay clock. The method of generating the same-phase signal and the delay encoding signal according to the sampling result comprises:

11. The circuit system control method according to claim 10, wherein the digital phase discriminator continuously samples regardless of the sampling result, and the encoder generates a corresponding delay encoding signal, wherein the delay encoding signal generated after each sampling is not completely the same; or, if the phases of the source clock and the internal source clock are consistent, the encoder outputs the same-phase signal at a high level, and when a phase signal output by the digital phase discriminator after sampling appears at a rising edge, the sampling is stopped, and the encoder generates a corresponding delay encoding signal. ​

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