Semiconductor device, integrated circuit, electronic apparatus, and preparation method for semiconductor device

Abstract

Embodiments of the present application relate to the technical field of electronic devices, and provide a semiconductor device, an integrated circuit, an electronic apparatus, and a preparation method for the semiconductor device. The semiconductor device comprises a substrate, a first electrode, a second electrode, a channel layer, and a gate. A first groove is provided in the substrate. The first electrode and the second electrode are provided on the substrate and are respectively provided on two sides of the first groove in a first direction, and the first direction is parallel to the substrate. At least a portion of the channel layer is provided on the inner wall of the first groove and on opposite side surfaces of the first electrode and the second electrode. At least a portion of the gate fills the first groove. In the semiconductor device, by sequentially providing the channel layer and the gate in the first groove, and respectively providing the first electrode and the second electrode on two sides of an opening of the first groove, the length of a channel is increased, thereby reducing the influence of a short-channel effect on the semiconductor device and optimizing the electrical performance of the semiconductor device.

Description

Semiconductor device, integrated circuit, electronic device and method for manufacturing semiconductor device

[0001] The present application claims priority to the Chinese patent application No. 202410765631.6, filed on June 13, 2024, and entitled "Semiconductor device, integrated circuit, electronic device and method for manufacturing semiconductor device", the content of which is incorporated herein by reference in its entirety. TECHNICAL FIELD

[0002] The present application relates to the technical field of electronic devices, and in particular to a semiconductor device, an integrated circuit, an electronic device and a method for manufacturing a semiconductor device. BACKGROUND

[0003] With the continuous development of advanced process technology nodes along Moore's law, the size of the semiconductor device and the area of the standard cell (STD CELL for short) are continuously miniaturized, thereby realizing the benefits of reducing cost, reducing power consumption, improving performance and miniaturized design.

[0004] However, with the continuous miniaturization and increasing integration of semiconductor devices, various defects have appeared in the semiconductor devices, for example, the contact area between the source (or drain) and the channel layer in the semiconductor device gradually decreases, resulting in a decrease in the on-current of the semiconductor device and a decrease in the response speed. At the same time, with the continuous miniaturization of the semiconductor device, the distance between the source and the drain in the semiconductor device gradually decreases, which aggravates the short channel effect of the semiconductor device, for example, it is easy to cause a leakage problem between the source and the drain. SUMMARY

[0005] Embodiments of the present application provide a semiconductor device, an integrated circuit, an electronic device and a method for manufacturing a semiconductor device, which aims to increase the contact area between the source (or drain) and the channel layer in the semiconductor device, reduce the contact resistance, thereby increasing the on-current of the semiconductor device, improving the response speed of the semiconductor device, in addition, it can also reduce the influence of the short channel effect on the semiconductor device, and optimize the electrical performance of the semiconductor device.

[0006] To achieve the above-mentioned purpose, the embodiments of the present application adopt the following technical solutions:

[0007] In a first aspect, a semiconductor device is provided, the semiconductor device comprising a substrate, a first electrode, a second electrode, a channel layer and a gate.

[0008] The substrate is provided with a first groove. The first electrode and the second electrode are arranged on the substrate and are arranged on two sides of the first groove along a first direction, wherein the first direction is parallel to the substrate. At least part of the channel layer is arranged on the inner wall of the first groove and the opposite side of the first electrode and the second electrode. At least part of the gate is filled in the first groove.

[0009] In the semiconductor device provided by the embodiment of the present application, by arranging the first groove in the substrate and sequentially arranging the channel layer and the gate on the inner wall of the first groove, and arranging the source electrode and the drain electrode on the slot of the first groove, the path of the channel formed in the channel layer can extend along the inner wall of the first groove. Compared with the case that the path of the channel extends along the straight line distance between the source electrode and the drain electrode, the length of the path of the channel extending along the inner wall of the first groove is longer, thereby effectively reducing the probability of the leakage problem between the source electrode and the drain electrode, reducing the influence of the short channel effect on the semiconductor device, and improving the electrical performance of the semiconductor device.

[0010] In addition, by arranging part of the channel layer on the opposite side of the first electrode and the second electrode, while realizing the electrical contact (for example, ohmic contact) between the channel layer and the source electrode and the drain electrode, the channel layer vertically attached to the side of the first electrode and the second electrode can greatly increase the contact area between the channel layer and the source electrode (and the channel layer and the drain electrode), thereby reducing the contact resistance, improving the on-current of the semiconductor device, and improving the response speed of the semiconductor device.

[0011] In a possible implementation of the first aspect, the gate comprises a first sub-portion and a second sub-portion arranged integrally, the first sub-portion is filled in the first groove, and the second sub-portion is filled between the first electrode and the second electrode.

[0012] That is, not only the surface of the part of the channel layer located in the first groove is covered with the gate, but also the surface of the part of the channel layer located on the opposite side of the first electrode and the second electrode can be covered with the gate, thereby ensuring that the gate and the channel layer have sufficient facing area, thereby enhancing the control ability of the gate to the channel in the channel layer, further reducing the probability of the leakage problem between the source electrode and the drain electrode, and optimizing the electrical performance of the semiconductor device.

[0013] In a possible implementation of the first aspect, the surface of the gate away from the bottom of the first groove is closer to the bottom of the first groove than the surface of the first electrode and the second electrode facing the substrate.

[0014] That is, the gate can be filled only in the first groove, avoiding the gate and the first electrode and the second electrode having facing area, thereby avoiding the problem that the parasitic capacitance is generated between the gate and the first electrode or between the gate and the second electrode, resulting in the performance of the semiconductor device being damaged.

[0015] In a possible implementation of the first aspect, the semiconductor device further includes an insulating portion. The insulating portion is arranged at a side of the gate away from the bottom of the first recess, and at least part of the insulating portion is filled between the first electrode and the second electrode.

[0016] The insulating portion can protect the surface of the gate away from the bottom of the first recess from damage, and avoid unintended electrical connection between the first electrode, the second electrode and the gate.

[0017] In a possible implementation of the first aspect, the substrate further includes a second recess arranged at the bottom of the first recess. Part of the channel layer is further arranged on the inner wall of the second recess, and part of the gate is further filled in the second recess.

[0018] That is, the channel layer covers not only the inner wall of the first recess but also the inner wall of the second recess, and the inner wall of the second recess is used to increase the contact area of the gate and the channel layer, thereby improving the control ability of the gate over the channel and further optimizing the electrical performance of the semiconductor device.

[0019] In a possible implementation of the first aspect, the two opposite sidewalls of the first recess are recessed in directions away from each other in the first direction. Thus, the area of the inner wall of the first recess is increased, and the area of the channel layer attached to the inner wall of the first recess is also increased, further increasing the path length of the channel formed in the channel layer and optimizing the electrical performance of the semiconductor device.

[0020] In a possible implementation of the first aspect, the semiconductor device includes a plurality of transistors, each transistor including a substrate, a first electrode, a second electrode, a channel layer and a gate. The plurality of transistors are arranged in a first direction and a second direction. The second direction is parallel to the substrate and intersects the first direction.

[0021] At least two transistors arranged adjacent to each other in the first direction share the second electrode.

[0022] The plurality of transistors arranged in multiple directions can increase the capacity of the semiconductor device, and the two transistors arranged adjacent to each other in the first direction share the second electrode, which can reduce the design space occupied by the transistors and facilitate improving the integration of the semiconductor device.

[0023] In a possible implementation of the first aspect, the semiconductor device further includes a first partition portion. The first partition portion is arranged between two transistors arranged adjacent to each other in the second direction. The gates of at least two transistors arranged adjacent to each other in the second direction penetrate the first partition portion and are electrically connected to each other, and the channel layers, the first electrodes and the second electrodes of the at least two transistors arranged adjacent to each other in the second direction are electrically insulated by the first partition portion, so as to achieve isolation between the two transistors arranged adjacent to each other in the second direction and avoid unintended electrical connection between the two transistors.

[0024] In a possible implementation manner of the first aspect, the first partition portion includes a third groove, the third groove is arranged between two first grooves arranged adjacent in the second direction, and the third groove is in communication with the first grooves; a groove bottom of the third groove is closer to the side surface of the substrate away from the first electrode than a groove bottom of the first grooves. A part of the gate is also filled in the third groove, and the gates in at least two transistors arranged adjacent in the second direction pass through the first partition portion through the third groove; a part of the channel layer is also arranged on two side walls of the third groove opposite in the second direction.

[0025] By arranging the third groove and arranging the channel layer on the side walls of the third groove, the width (perpendicular to the path length of the channel) of the channel layer is increased by the side walls of the third groove on the first partition portion, the on-off ratio of the semiconductor device is improved, and the contact area of the gate and the channel layer is also increased, so that the control ability of the gate to the channel is improved, and the electrical performance of the semiconductor device is further optimized.

[0026] In a possible implementation manner of the first aspect, the first electrode and the second electrode each include a conductive layer and a conductive portion. The upper surface of the substrate, the first partition portion, and the channel layer enclose a first cavity, the conductive portion is filled in the first cavity, and the conductive layer is arranged between the inner wall of the first cavity and the conductive portion.

[0027] By surrounding the conductive layer around the multiple surfaces of the conductive portion, the contact area between the part for contacting the channel layer and the part for realizing the external connection of the source electrode or the drain electrode in the first electrode or the second electrode is increased, so that the two have a better electrical connection effect, and the electrical performance of the semiconductor device can also be optimized.

[0028] In a second aspect, a preparation method of a semiconductor device is provided, and the preparation method includes the following steps.

[0029] A sacrificial layer is covered on a substrate. A first slot is formed; the first slot extends in a second direction, and a side wall of the first slot extends from a surface of the sacrificial layer away from the substrate into the substrate; the first slot divides the sacrificial layer into a first sacrificial portion and a second sacrificial portion, and a part of the first slot in the substrate is a first groove; the first sacrificial portion and the second sacrificial portion are arranged on two sides of the first groove in a first direction; the first direction and the second direction are parallel to the substrate, and the first direction intersects the second direction. A channel layer and a gate are sequentially formed in the first slot; at least a part of the channel layer is arranged on an inner wall of the first groove and opposite side surfaces of the first sacrificial portion and the second sacrificial portion; and at least a part of the gate is filled in the first groove. The first sacrificial portion is replaced by a first electrode, and the second sacrificial portion is replaced by a second electrode.

[0030] The technical effects brought by the preparation method in the second aspect can refer to the technical effects brought by the design of the semiconductor device in the first aspect, which will not be repeated here.

[0031] In a possible implementation manner of the second aspect, after the substrate is covered with the sacrificial layer and before the first slot is formed, the method further includes: opening a second slot and filling the first partition portion in the second slot; the first partition portion extends along the first direction, and the first partition portion breaks at least part of the sacrificial layer and at least part of the substrate. The first slot also breaks at least part of the first partition portion, and the part of the first slot in the first partition portion is a third groove.

[0032] After the channel layer and the gate are sequentially formed in the first slot, the method further includes: removing the first partition portion and part of the channel layer exposed after the first partition portion is removed. The first partition portion is filled again.

[0033] Through this embodiment, a semiconductor device with multiple transistors can be prepared, and in particular, multiple transistors arranged in the second direction and sharing a gate can be prepared.

[0034] In a possible implementation manner of the second aspect, after the first slot is formed and before the channel layer and the gate are sequentially formed in the first slot, the method further includes: continuing to etch the part of the first slot that belongs to the first partition portion, so that the groove bottom of the third groove is closer to the side surface of the substrate away from the first sacrificial portion than the groove bottom of the first groove.

[0035] Through this embodiment, in the semiconductor device prepared, the channel layer not only adheres to the inner wall of the first groove, but also adheres to the side wall of the third groove, thereby increasing the width (the path length perpendicular to the channel) of the channel layer, improving the on-off ratio of the semiconductor device, and also increasing the contact area between the gate and the channel layer, thereby improving the control ability of the gate on the channel and further optimizing the electrical performance of the semiconductor device.

[0036] In a possible implementation manner of the second aspect, before the substrate is covered with the sacrificial layer, the method further includes: forming a second partition portion in the substrate; the second partition portion extends along the first direction and breaks at least part of the substrate. After the sacrificial layer is formed, the sacrificial layer covers the second partition portion. The first slot also breaks at least part of the second partition portion, and the part of the first slot in the second partition portion is a second groove.

[0037] After the first slot is formed and before the channel layer and the gate are sequentially formed in the first slot, the method further includes: continuing to etch the part of the first slot that belongs to the second partition portion, so that the groove bottom of the second groove is closer to the side surface of the substrate away from the first sacrificial portion than the groove bottom of the first groove.

[0038] Through the embodiment, the channel layer can be attached to the inner wall of the first recess and the sidewall of the second recess in the prepared semiconductor device, so that the width (perpendicular to the length of the channel path) of the channel layer can be increased, the on-off ratio of the semiconductor device can be improved, the contact area between the gate and the channel layer can be increased, the control ability of the gate to the channel can be improved, and the electrical performance of the semiconductor device can be further optimized.

[0039] In a possible implementation of the second aspect, the first electrode and the second electrode each include a conductive layer and a conductive part. Replacing the first sacrificial part with the first electrode and replacing the second sacrificial part with the second electrode includes:

[0040] The first sacrificial part and the second sacrificial part are removed to form a plurality of first cavities; the upper surface of the substrate, the first partition part, and the channel layer enclose the first cavities. The conductive layer is formed on the inner wall of the first cavities. The conductive part is formed; the conductive part is filled in the first cavities, and the conductive layer is arranged between the inner wall of the first cavities and the conductive part.

[0041] Through the embodiment, the conductive layer can surround the plurality of surfaces of the conductive part, so that the contact area between the part (that is, the conductive layer) for contacting the channel layer and the part (that is, the conductive part) for realizing the external connection of the source or the drain in the first electrode or the second electrode can be increased, so that the two parts have better electrical connection effect, and the electrical performance of the semiconductor device can be further optimized.

[0042] In a third aspect, an integrated circuit is provided, which includes an electronic device and the semiconductor device provided in any one of the embodiments of the first aspect. The electronic device is electrically connected to the semiconductor device.

[0043] In a fourth aspect, an electronic device is provided, which includes a circuit board and the integrated circuit provided in the embodiments of the third aspect. The integrated circuit is arranged on the circuit board and is electrically connected to the circuit board.

[0044] The technical effects brought by the integrated circuit in the third aspect and the electronic device in the fourth aspect can refer to the technical effects brought by the design of the semiconductor device in the first aspect, which will not be described herein again. BRIEF DESCRIPTION OF DRAWINGS

[0045] FIG. 1 is a structural schematic diagram of an electronic device provided in an embodiment of the present application;

[0046] FIG. 2 is a structural schematic diagram of a semiconductor device provided in an embodiment of the present application;

[0047] FIG. 3 is a sectional view along the section line A-A' in FIG. 2;

[0048] FIG. 4 is a relationship curve diagram of the contact area of the channel layer and the source and the on current provided in an embodiment of the present application;

[0049] FIG. 5 is another structural schematic diagram of a semiconductor device provided by an embodiment of the present application;

[0050] FIG. 6 is another structural schematic diagram of a semiconductor device provided by an embodiment of the present application;

[0051] FIG. 7 is a sectional view along the section line B-B' in FIG. 6;

[0052] FIG. 8 is another structural schematic diagram of a semiconductor device provided by an embodiment of the present application;

[0053] FIG. 9 is a sectional view along the section line C-C' in FIG. 8;

[0054] FIG. 10 is another sectional view along the section line C-C' in FIG. 8;

[0055] FIG. 11 is a front view of a semiconductor device provided by an embodiment of the present application;

[0056] FIGS. 12-15 are flow charts of preparation of a semiconductor device provided by an embodiment of the present application;

[0057] FIGS. 16-31 are structural diagrams corresponding to respective preparation steps of a semiconductor device. DETAILED DESCRIPTION

[0058] The technical solutions in some embodiments of the present application will be described clearly and completely below with reference to the drawings. Obviously, the described embodiments are only some of the embodiments of the present application, but not all the embodiments. Based on the embodiments provided by the present application, all other embodiments obtained by those skilled in the art belong to the scope of protection of the present application.

[0059] In the description of the present application, it should be understood that the terms "center", "upper", "lower", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", and the like indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, and are only for the purpose of facilitating the description of the present application and simplifying the description, and therefore cannot be understood as indicating or implying that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as a limitation on the present application.

[0060] Unless otherwise required by context, as used herein, the term "include" is to be construed as open-ended, i.e., the inclusion of elements, components, or steps that are not listed is permitted. When the specification states a component, feature, structure, or characteristic, that might be included in "one embodiment" or "some embodiments," this is intended to mean that this component, feature, structure, or characteristic is included in at least one embodiment or some embodiments of the present application. Thus, the appearances of such phrases in various places in the specification are not necessarily intended to be referring to the same embodiment or embodiments. Further, the particular features, structures, materials, or characteristics can be combined in any suitable manner in one or more embodiments or examples.

[0061] Hereinafter, the terms "first", "second", and the like are used only for the purpose of description, and are not to be construed as indicating or implying relative importance or implying the number of the technical features indicated. Therefore, the features defined with "first", "second" can explicitly or implicitly include one or more of the features. In the description of the embodiments of the present application, the meaning of "a plurality of" is two or more, unless otherwise specified.

[0062] Connection / connection: can refer to a mechanical connection relationship or a physical connection relationship, that is, A and B are connected or A and B are connected, which means that there is a fastening component (such as a screw, a bolt, a rivet, etc.) between A and B, or A and B are in contact with each other and A and B are difficult to separate, wherein A and B can be fixedly connected, or detachably connected, or integrated; it can be directly connected, or indirectly connected through an intermediate medium.

[0063] Coupling: can be understood as direct coupling and / or indirect coupling, and "coupling connection" can be understood as direct coupling connection and / or indirect coupling connection. Direct coupling can also be referred to as "electrical connection", which is understood as that the components are directly or indirectly in physical contact and electrically conductive, for example, in the form of connection between different components in a circuit structure through an entity circuit such as a copper foil or a wire of a printed circuit board (PCB) that can transmit electrical signals; "indirect coupling" can be understood as that two conductors are electrically conductive in a spaced / untouched manner. In an embodiment, indirect coupling can also be referred to as capacitive coupling, for example, signal transmission is realized by forming an equivalent capacitor through the coupling between the gap between two conductive parts.

[0064] "A, B, and C at least one of" has the same meaning as "A, B, or C at least one of", and includes the following combinations of A, B, and C: only A, only B, only C, a combination of A and B, a combination of A and C, a combination of B and C, and a combination of A, B, and C.

[0065] "A and / or B" includes the following three combinations: only A, only B, and a combination of A and B.

[0066] As used herein, "parallel," "perpendicular," "equal" include the recited condition and conditions that approximate the recited condition to an extent that is within an acceptable range of deviation, as determined by one of ordinary skill in the art taking into account the measurements at issue and the error associated with the measurement of the particular quantity (i.e., the limitations of the measurement system). For example, "parallel" includes absolute parallel and near parallel, where near parallel can be within an acceptable range of deviation of, for example, 5°; "perpendicular" includes absolute perpendicular and near perpendicular, where near perpendicular can also be within an acceptable range of deviation of, for example, 5°. "Equal" includes absolute equality and near equality, where near equality can be within an acceptable range of deviation of, for example, less than or equal to 5% of either of the two quantities being compared.

[0067] Exemplary embodiments are described herein with reference to cross-sectional and / or plan view illustrations that are schematic illustrations of idealized embodiments. In the drawings, the thickness of layers and regions are exaggerated for clarity. Accordingly, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and / or tolerances, are to be expected. Thus, the exemplary embodiments should not be construed as limited to the particular shapes of regions as illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. The regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of the exemplary embodiments.

[0068] In addition, the scenarios described in the embodiments of the present application are for more clearly illustrating the technical solutions of the embodiments of the present application, and do not constitute a limitation on the technical solutions provided by the embodiments of the present application. It can be known by those skilled in the art that, as new scenarios appear, the technical solutions provided by the embodiments of the present application are also applicable to similar technical problems.

[0069] The electronic device provided by the embodiments of the present application may, for example, be a mobile phone, a tablet computer, a personal digital assistant, a television, a smart wearable product (for example, a smart watch, a smart bracelet), a virtual reality terminal device, an augmented reality terminal device, a charging household small appliance (for example, a soybean milk machine, a sweeping robot), a drone, a radar, an aerospace device, a vehicle-mounted device, a vehicle, or a terminal device of different types of user equipment or the like; the electronic device may, for example, also be a network device such as a base station. The embodiments of the present application do not specially limit the specific form of the electronic device.

[0070] FIG. 1 is a structural schematic diagram of an electronic device according to an example of the present application. As shown in FIG. 1, the electronic device 1000 includes an integrated circuit 100 and a circuit board 200, and the integrated circuit 100 can be disposed on the circuit board 200.

[0071] For example, the circuit board 200 can be a printed circuit board (PCB).

[0072] It should be understood that the structure of the electronic device 1000 shown in FIG. 1 does not constitute a specific limitation on the electronic device 1000, and the electronic device 1000 can include more or fewer components than those shown in FIG. 1, or can combine some of the components shown in FIG. 1, or can be arranged differently from the components shown in FIG. 1.

[0073] An example of the present application also provides an integrated circuit 100.

[0074] For example, as shown in FIG. 1, the integrated circuit 100 can include a logic circuit 101, an analog circuit 102, a storage circuit 103, and an input / output circuit 104, etc.

[0075] It should be understood that the integrated circuit 100 includes but is not limited to the logic circuit 101, the analog circuit 102, the storage circuit 103, and the input / output circuit 104. For example, in addition to the aforementioned four circuits, the integrated circuit 100 can also include other types or functions of circuits, or discrete devices.

[0076] In addition, the integrated circuit 100 can include one or more of the logic circuit 101, the analog circuit 102, the storage circuit 103, and the input / output circuit 104.

[0077] On this basis, the number of the logic circuit 101, the analog circuit 102, the storage circuit 103, and the input / output circuit 104 included in the integrated circuit 100 can be set as needed. The integrated circuit 100 can include one or more logic circuits 101. The integrated circuit 100 can also include one or more analog circuits 102. The integrated circuit 100 can also include one or more storage circuits 103. The integrated circuit 100 can also include one or more input / output circuits 104.

[0078] As shown in FIG. 1, the integrated circuit 100 can include a semiconductor device 10 and some electronic devices 20. The electronic devices 20 are electrically connected to the semiconductor device 10.

[0079] For example, referring to FIG. 1, the semiconductor device 10 and the electronic device 20 can be integrated in a logic circuit 101, and the semiconductor device 10 and the electronic device 20 in the logic circuit 101 cooperate with each other to realize the functions such as AND, OR, and NOT in the logic circuit 101.

[0080] For example, the electronic device 20 can be a resistor, a capacitor, or the like.

[0081] For example, the semiconductor device 10 and the electronic device 20 can also be disposed in other circuits, for example, can be disposed in a memory circuit 103, and the present application does not make specific limitations in this regard.

[0082] The present application also provides a semiconductor device 10.

[0083] For example, the semiconductor device 10 can be a transistor, for example, can be an oxide thin-film transistor (TFT) or a metal-oxide-semiconductor field-effect transistor (MOSFET).

[0084] For example, the semiconductor device 10 can also be a memory, for example, can be a dynamic random access memory (DRAM), for example, can be a part belonging to a transistor in a 1T1C architecture DRAM.

[0085] FIG. 2 is a structural schematic diagram of a semiconductor device 10 provided by an embodiment of the present application, and FIG. 3 is a sectional view along the section line A-A’ in FIG. 2.

[0086] In some embodiments, as shown in FIG. 2, the semiconductor device 10 includes a substrate 11, a first electrode 21, a second electrode 22, a channel layer 3, and a gate 4.

[0087] The substrate 11 serves as a carrier plate for carrying the first electrode 21, the second electrode 22, the channel layer 3, and the gate 4, so as to facilitate the preparation of the above-mentioned structures in the semiconductor device 10.

[0088] For example, the material of the substrate 11 can include at least one of single crystal silicon (Si), single crystal germanium (Ge), gallium arsenide (GaAs), indium phosphide (InP), a III-V compound semiconductor material, a II-VI compound semiconductor material, or other semiconductor materials known in the art, or can also be made of non-conductive materials such as glass, plastic, or sapphire wafer.

[0089] Referring to FIG. 2 and FIG. 3, the substrate 11 is provided with a first recess U1.

[0090] For example, referring to FIG. 2 and FIG. 3, the first recess U1 can be formed by etching the upper surface of the substrate 11 (in the orientation of FIG. 3) downward, and the bottom U1' of the first recess U1 is located inside the substrate 11, and the opening of the first recess U1 faces upward in the orientation of FIG. 3.

[0091] It can be understood that the cross-sectional view in FIG. 3 only shows the bottom U1' of the first recess U1, and the sidewall of the first recess U1 extends upward from the bottom U1' in FIG. 3.

[0092] For example, the bottom U1' of the first recess U1 can be a flat surface, or can also be a curved surface (see FIG. 2), and the embodiments of the present application do not limit this.

[0093] For example, the first recess U1 can be a rectangular recess, an elliptical recess, a circular recess, or a recess with other irregular shapes, and the embodiments of the present application do not limit this.

[0094] Referring to FIG. 2, the first electrode 21 and the second electrode 22 are disposed on the substrate 11, and the first electrode 21 and the second electrode 22 are disposed on the two sides of the first recess U1 along the first direction X. For example, referring to FIG. 2, the first electrode 21 and the second electrode 22 are disposed at the opening of the first recess U1 and are disposed on the two sides of the opening.

[0095] Wherein, the first direction X is parallel to the substrate 11, for example, referring to FIG. 2 and FIG. 3, the first direction X is parallel to the bottom surface of the substrate 11.

[0096] For example, referring to FIG. 2, the opposite two sides of the first electrode 21 and the second electrode 22 can be tangent to (for example, substantially located in the same plane as) the sidewall of the first recess U1. For example, referring to FIG. 2, the first electrode 21 is disposed on the left side of the first recess U1, and the side of the first electrode 21 facing the second electrode 22 is tangent to the sidewall on the left side of the first recess U1. Similarly, the second electrode 22 is disposed on the right side of the first recess U1, and the side of the second electrode 22 facing the first electrode 21 is tangent to the sidewall on the right side of the first recess U1, thereby facilitating the synchronous preparation of the first recess U1 and the two electrodes (the first electrode 21 and the second electrode 22).

[0097] Alternatively, for example, the opposite two sides of the first electrode 21 and the second electrode 22 can also have a certain distance from the slot of the first recess U1, for example, the side of the first electrode 21 facing the second electrode 22 can be farther away from the second electrode 22 relative to the left side wall of the first recess U1 (i.e. arranged more to the left), and the side of the second electrode 22 facing the first electrode 21 can be farther away from the first electrode 21 relative to the right side wall of the first recess U1 (i.e. arranged more to the right).

[0098] The first electrode 21 and the second electrode 22 are used as the source and the drain in the semiconductor device 10, and have electrical conductivity.

[0099] For example, the materials of the first electrode 21 and the second electrode 22 can be metal materials, for example, can include tungsten (W), titanium (Ti), copper (Cu), molybdenum (Mo), gold (Au), silver (Ag), aluminum (Al), ruthenium (Ru) or other metals or alloy materials with electrical conductivity.

[0100] Alternatively, for example, the materials of the first electrode 21 and the second electrode 22 can also be semiconductor materials, for example, can include silicon (Si), titanium nitride (TiN), indium tin oxide (ITO) or other semiconductor materials, at this time, the first electrode 21 and the second electrode 22 can be highly doped to improve their electrical conductivity.

[0101] Referring to FIG. 2, at least part of the aforementioned channel layer 3 is arranged on the inner wall of the first recess U1 (including the bottom U1' of the first recess U1 and the side wall of the first recess U1), and the opposite sides of the first electrode 21 and the second electrode 22.

[0102] It can be understood that here "the opposite sides of the first electrode 21 and the second electrode 22" refers to the sides of the first electrode 21 and the second electrode 22 facing each other, i.e. the side of the first electrode 21 close to the second electrode 22 and the side of the second electrode 22 close to the first electrode 21.

[0103] The material of the channel layer 3 is a semiconductor material, i.e. a channel (carrier) can be formed in the channel layer 3, so as to have electrical conductivity, realize the conduction between the source and the drain in the semiconductor device 10, and thus realize the opening of the semiconductor device 10. In the case where no channel is formed in the channel layer 3, the channel layer 3 has electrical insulation, so as to realize the electrical insulation between the source and the drain in the semiconductor device 10, and thus realize the closing of the semiconductor device 10.

[0104] For example, the material of the channel layer 3 can include at least one of single crystal silicon (Si), polycrystalline silicon (poly-Si), amorphous silicon (amorphous-Si), indium gallium zinc oxide (In-Ga-Zn-O, IGZO for short), single crystal germanium (Ge), zinc oxide (ZnO), indium tin oxide (ITO), titanium dioxide (TiO2), molybdenum disulfide (MoS2), gallium arsenide (GaAs), indium phosphide (InP), a III-V compound semiconductor material, a II-VI compound semiconductor material, or other semiconductor materials known in the art.

[0105] Referring to FIG. 2, the channel layer 3 is in contact with the first electrode 21 and the second electrode 22 at both ends, respectively, and in the case of forming a channel in the channel layer 3, the channel layer 3 has electrical conductivity, so that the conduction between the first electrode 21 and the second electrode 22 can be realized, that is, the conduction between the source and the drain in the semiconductor device 10 is realized, and the opening of the semiconductor device 10 is realized.

[0106] Exemplarily, the channel layer 3 can be doped, for example, can be high-concentration doped, so that the channel layer 3 can form an ohmic contact with the source and the drain (i.e., the first electrode 21 and the second electrode 22) in the semiconductor device 10, and the transmission performance of the electrical signal between the source (e.g., the first electrode 21), the channel layer 3, and the drain (e.g., the second electrode 22) in the semiconductor device 10 is improved.

[0107] Referring to FIG. 2, the middle part of the channel layer 3 is attached to the inner wall of the first recess U1, and in the process of opening the semiconductor device 10, the channel needs to pass through the part of the channel layer 3 located on the inner wall of the first recess U1, so that the conduction between the first electrode 21 and the second electrode 22 can be realized, that is, the transmission path of the channel formed in the semiconductor device 10 is not a straight-line distance between the source and the drain (i.e., between the first electrode 21 and the second electrode 22), but is arranged in a curve along the shape of the channel layer 3, for example, the transmission path of the channel includes the part of the channel layer 3 in contact with the first electrode 21, the part of the channel layer 3 in contact with the inner wall of the first recess U1, and the part of the channel layer 3 in contact with the second electrode 22.

[0108] Compared with the channel with a straight-line distance between the source and the drain, the transmission path of the curved channel of the semiconductor device 10 provided in the embodiment of the present application is longer, which can avoid the occurrence of leakage current between the source and the drain, and improve the electrical performance of the semiconductor device 10.

[0109] Exemplarily, the control of the length of the channel path formed in the channel layer 3 can be realized by controlling the depth of the first recess U1, for example, the deeper the depth of the first recess U1 is, the larger the area of the inner wall is, and the longer the length of the channel layer 3 is, and the longer the transmission path of the channel formed therein is.

[0110] Referring to FIG. 2, at least part of the gate 4 is filled in the first recess U1.

[0111] The gate 4, as a control electrode of the transistor T, is used to control the formation of a channel in the channel layer 3, so as to control the conduction between the first electrode 21 and the second electrode 22 electrically connected to both ends of the channel layer 3, or control the non-formation of a channel in the channel layer 3, so as to control the disconnection between the first electrode 21 and the second electrode 22 electrically connected to both ends of the channel layer 3, that is, to control the opening and closing of the semiconductor device 10.

[0112] Exemplarily, the gate 4 has electrical conductivity, and the material of the gate 4 can be a metal material or other conductive material, for example, the material of the gate 4 can include at least one of titanium nitride (TiN), titanium (Ti), gold (Au), tungsten (W), molybdenum (Mo), indium tin oxide (ITO), aluminum (Al), copper (Cu), ruthenium (Ru), silver (Ag).

[0113] Referring to FIG. 2, by filling the gate 4 in the first recess U1 and arranging the channel layer 3 on the inner wall of the first recess U1, the gate 4 covers the part of the channel layer 3 on the inner wall of the first recess U1, that is, the channel layer 3 and the gate 4 have a facing area, so as to facilitate the control of the channel in the channel layer 3 by the gate 4, so as to realize the opening and closing of the semiconductor device 10.

[0114] Exemplarily, referring to FIG. 2 and FIG. 3, the semiconductor device 10 further includes a gate oxide layer 5 arranged between the gate 4 and the channel layer 3.

[0115] For example, the channel layer 3 is attached to the inner wall of the first recess U1, the gate oxide layer 5 can be attached to the side of the channel layer 3 away from the inner wall of the first recess U1, the gate 4 is arranged on the gate oxide layer 5 and fills the first recess U1, so as to avoid the direct electrical contact between the gate 4 and the channel layer 3, so that the gate 4 can control the channel in the channel layer 3, and realize the opening and closing of the semiconductor device 10.

[0116] Exemplarily, the gate oxide layer 5 has electrical insulation properties, for example, the material of the gate oxide layer 5 can include one or more of insulating materials such as silicon dioxide (SiO2), aluminum oxide (Al2O3), hafnium disulfide (HfO2), zirconium dioxide (ZrO2), titanium dioxide (TiO2), yttrium oxide (Y2O3), and silicon nitride (Si3N4).

[0117] In the semiconductor device 10 provided by the embodiments of the present application, by opening the first recess U1 in the substrate 11 and sequentially arranging the channel layer 3 and the gate 4 (and the gate oxide layer 5 between the channel layer 3 and the gate 4) on the inner wall of the first recess U1, the source and the drain (i.e. the first electrode 21 and the second electrode 22) are arranged at the slot opening of the first recess U1, so that the path of the channel formed in the channel layer 3 can extend along the inner wall of the first recess U1, for example, the channel path can extend from one side of the slot opening of the first recess U1, pass through the inner wall of the first recess U1, and extend to the other side of the slot opening of the first recess U1. Compared with the case where the channel path extends along the straight line distance between the source and the drain, the length of the channel path extending along the inner wall of the first recess U1 is longer, so that the probability of leakage between the source and the drain can be effectively reduced, the influence of the short channel effect on the semiconductor device 10 can be reduced, and the electrical performance of the semiconductor device 10 can be improved.

[0118] In addition, by arranging part of the channel layer 3 on the opposite sides of the first electrode 21 and the second electrode 22, while realizing the electrical contact (e.g. ohmic contact) between the channel layer 3 and the source and the drain, the channel layer 3 vertically attached on the side of the first electrode 21 and the second electrode 22 can greatly increase the contact area between the channel layer 3 and the source (and the channel layer 3 and the drain), so as to reduce the contact resistance, improve the on-current of the semiconductor device 10, and improve the response speed of the semiconductor device 10.

[0119] FIG. 4 and Table 1 below show the corresponding relationship between the size of the contact area between the source (or the drain) and the channel layer 3 in the semiconductor device 10 and the on-current of the semiconductor device 10:

[0120] Table 1

[0121] In FIG. 4 and Table 1, the contact area between the channel layer 3 and the source (or the drain) refers to the product of the width and the length of the contact area, for example, which can be the area of the side of the first electrode 21 facing the second electrode 22.

[0122] In addition, referring to FIG. 4 and Table 1, the on-current of the semiconductor device 10 is analyzed and detected under the condition that the voltage is 2V.

[0123] As shown in FIG. 4 and Table 1, with the increase of the contact area, the on-current of the semiconductor device 10 also gradually increases. For example, according to the parameters of the first point (N1x), when the contact area is 440 nm2, the on-current of the semiconductor device 10 is 1.43e-5; according to the parameters of the second point (N25), when the contact area is 1280 nm2, the on-current of the semiconductor device 10 is 2.33e-5. That is, when the contact area increases from 440 nm2 to 1280 nm2, the on-current is greatly improved, and the performance of the semiconductor device 10 is greatly improved.

[0124] The semiconductor device 10 provided by the embodiments of the present application has a regular structure, and the stacking of the structure in multiple directions can be easily realized. The specific stacking manner can be referred to the following embodiments.

[0125] In some embodiments, as shown in FIG. 2, the semiconductor device 10 can include a plurality of transistors T, each transistor T including the substrate 11, the first electrode 21, the second electrode 22, the channel layer 3, and the gate 4.

[0126] As shown in FIG. 2, the plurality of transistors T can be arranged along the first direction X, or the plurality of transistors T can be arranged along the second direction Y, or as shown in FIG. 2, the plurality of transistors T can be arranged along the first direction X and the second direction Y.

[0127] That is, the semiconductor device 10 can include a plurality of transistors T that can be stacked in multiple directions, so that the semiconductor device 10 has different capacities to be suitable for different application scenarios. For example, when the semiconductor device 10 is used for information storage, the semiconductor device 10 with multiple transistors T stacked in different directions can have a larger storage capacity.

[0128] The first direction X and the second direction Y are parallel to the substrate 11, the first direction X can be the arrangement direction of the first electrode 21 and the second electrode 22, and the second direction Y intersects the first direction X, for example, the second direction Y is perpendicular to the first direction X.

[0129] In some embodiments, as shown in FIG. 2, at least two transistors T arranged adjacent along the first direction X can share the second electrode 22, so as to improve the integration of the semiconductor device 10.

[0130] For example, as shown in FIG. 2, the two transistors T can also be symmetrically arranged with the second electrode 22 as the symmetry axis, so as to realize the regular stacking of the plurality of transistors T in the first direction X.

[0131] In some embodiments, as shown in FIG. 2 and FIG. 3, the semiconductor device 10 further includes a first partition 71.

[0132] Referring to FIG. 2, the first partition part 71 is arranged between two transistors T arranged adjacent to each other along the second direction Y, so as to realize insulation between the two transistors T arranged adjacent to each other along the second direction Y, and avoid unintended electrical connection between the two transistors T.

[0133] For example, referring to FIG. 2, the gates 4 in at least two transistors T arranged adjacent to each other along the second direction Y can be electrically connected to each other after penetrating through the first partition part 71. For example, referring to FIG. 3, the gates 4 corresponding to the two transistors T can be integrally arranged, that is, a plurality of transistors T arranged along the second direction Y can share the gates 4, so as to facilitate formation of a word line (abbreviated as WL) and realize synchronous transmission of control signals of the plurality of transistors T.

[0134] For example, referring to FIG. 2 and FIG. 3, the channel layers 3 in at least two transistors T arranged adjacent to each other along the second direction Y are electrically insulated by the first partition part 71. Similarly, referring to FIG. 2, the first electrodes 21 in two transistors T arranged adjacent to each other along the second direction Y are electrically insulated by the first partition part 71, and the second electrodes 22 are also electrically insulated by the first partition part 71.

[0135] That is, referring to FIG. 3, the two channel layers 3 corresponding to two transistors T arranged adjacent to each other along the second direction Y are disconnected, and similarly, the two first electrodes 21 corresponding to two transistors T arranged adjacent to each other along the second direction Y are disconnected, and the two second electrodes 22 are also disconnected.

[0136] For example, referring to FIG. 2, the first partition part 71 can be embedded in the substrate 11, and the bottom surface of the first partition part 71 can be located in the substrate 11. For example, referring to FIG. 2 and FIG. 3, the bottom surface of the first partition part 71 can be flush with the groove bottom U1’ of the first groove U1, so that the two channel layers 3 corresponding to two transistors T arranged adjacent to each other along the second direction Y, the two first electrodes 21, and the two second electrodes 22 can be disconnected from each other.

[0137] Alternatively, for example, referring to FIG. 6, the bottom of the first partition part 71 can also be flush with the bottom surface of the substrate 11, that is, the first partition part 71 can divide the substrate 11 into two parts, so as to ensure that the two channel layers 3 corresponding to two transistors T arranged adjacent to each other along the second direction Y, the two first electrodes 21, and the two second electrodes 22 can be fully disconnected.

[0138] The foregoing embodiments can realize improvement of electrical performance of the semiconductor device 10 through superposition of the number of transistors T, and in addition, can realize improvement of electrical performance of the semiconductor device 10 through deformation of structures such as the gate 4. For specific deformation modes of the structures, please refer to the following embodiments.

[0139] FIG. 5 and FIG. 6 are schematic structural diagrams of the semiconductor device 10 according to some embodiments of the present application.

[0140] In some embodiments, referring to FIG. 5, the gate 4 includes a first sub-portion 41 and a second sub-portion 42, the first sub-portion 41 is filled in the first recess U1, and the second sub-portion 42 is filled between the first electrode 21 and the second electrode 22.

[0141] That is, part of the gate 4 is not only filled in the first recess U1, but also part of the gate 4 is arranged between the first electrode 21 and the second electrode 22, that is, referring to FIG. 5, not only the surface of the part of the channel layer 3 located in the first recess U1 is covered by the gate 4 (it can be understood that there is a gate oxide layer 5 between the channel layer 3 and the gate 4), but also the surface of the part of the channel layer 3 located on the side opposite to the first electrode 21 and the second electrode 22 can be covered by the gate 4, so as to ensure that the gate 4 and the channel layer 3 have sufficient facing area, thereby enhancing the control ability of the gate 4 on the channel in the channel layer 3, further reducing the probability of leakage between the source and the drain, and optimizing the electrical performance of the semiconductor device 10.

[0142] In some other embodiments, referring to FIG. 2 and FIG. 6, the gate 4 can be filled only in the first recess U1, that is, the surface of the gate 4 away from the bottom U1' of the first recess U1 is closer to the bottom U1' of the first recess U1 relative to the surface of the first electrode 21 and the second electrode 22 facing the substrate 11, that is, the distance d1 (referring to FIG. 6) between the surface of the gate 4 away from the bottom U1' of the first recess U1 and the surface of the first electrode 21 and the second electrode 22 facing the substrate 11 is greater than or equal to 0 nm, so as to avoid the gate 4 and the first electrode 21 and the second electrode 22 having facing area, thereby avoiding the gate 4 and the first electrode 21, or the gate 4 and the second electrode 22 generating parasitic capacitance, and causing the performance of the semiconductor device 10 to be damaged.

[0143] For example, referring to FIG. 6, in the case that the surface of the gate 4 away from the bottom U1' of the first recess U1 is closer to the bottom U1' of the first recess U1 relative to the surface of the first electrode 21 and the second electrode 22 facing the substrate 11, the gate 4 and the first electrode 21, and the gate 4 and the second electrode 22 are staggered relative to each other, thereby avoiding generating parasitic capacitance.

[0144] For example, the distance d1 can be greater than or equal to 2 nm, for example, can be 2 nm, 4.5 nm, 8.743 nm or 11 nm, etc.

[0145] In some embodiments, referring to FIG. 2 and FIG. 6, the semiconductor device 10 further comprises an insulating portion 6, the gate 4 is filled in the first recess U1, the insulating portion 6 is arranged at a side of the gate 4 away from the bottom U1' of the first recess U1, and at least part of the insulating portion 6 is filled between the first electrode 21 and the second electrode 22.

[0146] For example, referring to FIG. 6, in the case that the surface of the gate 4 away from the bottom U1' of the first recess U1 has a spacing d1 with the surface of the first electrode 21 and the second electrode 22 facing the substrate 11, part of the insulating portion 6 is filled in the first recess U1 in addition to the part filled between the first electrode 21 and the second electrode 22.

[0147] The insulating portion 6 has electrical insulation, and the material thereof can refer to the material of the aforementioned gate oxide layer 5 or other material capable of achieving electrical insulation.

[0148] By arranging the insulating portion 6, the top of the gate 4 can be kept insulated, and the gate 4 can be prevented from being electrically connected unexpectedly, and the insulating portion 6 arranged between the first electrode 21 and the second electrode 22 can prevent the first electrode 21 and the second electrode 22 from being directly electrically connected.

[0149] FIG. 7 is a sectional view along the section line B-B' in FIG. 6.

[0150] In some embodiments, referring to FIG. 7, in the case that the semiconductor device 10 comprises a first partition portion 71, the first partition portion 71 can be provided with a third recess U3, and the gate 4 of at least two transistors T arranged adjacently along the second direction Y can pass through the first partition portion 71 through the third recess U3.

[0151] Referring to FIG. 2 and FIG. 7, the third recess U3 is arranged between the two first recesses U1 corresponding to the two transistors T arranged adjacently along the second direction Y, and communicates with the first recess U1.

[0152] It can be understood that only the bottom U1' of the first recess U1 and the bottom U3' of the third recess U3 can be shown in FIG. 7, and the wall of the first recess U1 extends from the bottom U1' of the first recess U1 towards the top in FIG. 7, and the wall of the third recess U3 is the same.

[0153] For example, referring to FIG. 2, the bottom U3' of the third recess U3 can be flush with the bottom U1' of the first recess U1, and the third recess U3 can also meet the requirement that the gate 4 passes through the first partition portion 71.

[0154] Alternatively, referring to FIG. 7, the bottom U3' of the third recess U3 can also be closer to the side surface of the substrate 11 away from the first electrode 21 relative to the bottom U1' of the first recess U1, i.e., the depth of the third recess U3 can be deeper than the depth of the first recess U1, so that the inner wall of the first recess U1 and the inner wall of the third recess U3 form a step, increasing the inner wall area of the cavity formed by the first recess U1 and the third recess U3.

[0155] Referring to FIGS. 6 and 7, the bottom surface of the first partition 71 is lower than the bottom U1' of the first recess U1, so as to reserve space for the third recess U3 with a deeper depth formed on the first partition 71, for example, referring to FIG. 6, the bottom surface of the first partition 71 can be flush with the bottom surface of the substrate 11, or in other embodiments, the bottom surface of the first partition 71 can be located at any position lower than the bottom U1' of the first recess U1.

[0156] Referring to FIG. 7, part of the channel layer 3 is also arranged on the two opposite side walls of the third recess U3 in the second direction Y, i.e., the channel layer 3 is also arranged on the inner wall of the third recess U3, except for the bottom U3', so that the two channel layers 3 corresponding to the two transistors T arranged adjacently in the second direction Y are disconnected from each other, referring to FIG. 7, the parts of the two channel layers 3 located in the third recess U3 are disconnected by the first partition 71.

[0157] Referring to FIG. 7, part of the gate 4 is also filled in the third recess U3, so that the gate 4 in at least two transistors T arranged adjacently in the second direction Y penetrates the first partition 71 through the third recess U3, and in addition, the part of the gate 4 filled in the third recess U3 is also used to control the channel layer 3 attached to the side wall of the third recess U3 to form a channel.

[0158] In this embodiment, by arranging the third recess U3 and the channel layer 3 on the side wall of the third recess U3, the width (perpendicular to the path length of the channel) of the channel layer 3 is increased by the side wall of the third recess U3 on the first partition 71, which improves the on-off ratio of the semiconductor device 10, and at the same time, increases the contact area between the gate 4 and the channel layer 3, thereby improving the control ability of the gate 4 on the channel, and further optimizing the electrical performance of the semiconductor device 10.

[0159] FIG. 8 is another structural schematic diagram of the semiconductor device 10 provided in the embodiments of the present application, FIG. 9 is a cross-sectional view along the section line C-C' in FIG. 8, and FIG. 10 is another cross-sectional view along the section line C-C' in FIG. 8.

[0160] In some embodiments, referring to FIG. 9, the substrate 11 further includes a second recess U2, which is arranged at the bottom U1' of the first recess U1.

[0161] For example, the second recess U2 can be etched from the bottom U1' of the first recess U1 downwards (for example, in the orientation of FIGS. 9 and 10), so that the inner walls of the first recess U1 and the second recess U2 are stepped, and the area of the inner wall of the cavity formed by the first recess U1 and the second recess U2 is increased.

[0162] For example, referring to FIG. 8, in order to facilitate the formation of the second recess U2, the semiconductor device 10 can further include a second partition 72 embedded in the substrate 11, the second partition 72 being located below the first electrode 21 and the second electrode 22, and the aforementioned second recess U2 can be formed in the second partition 72.

[0163] For example, referring to FIGS. 9 and 10, the length (dimension in the second direction Y) of the second recess U2 is less than the length of the first recess U1, so as to facilitate the formation of the stepped structure between the sidewalls of the first recess U1 and the second recess U2.

[0164] Referring to FIGS. 9 and 10, part of the channel layer 3 is further disposed on the inner wall of the second recess U2, and part of the gate 4 is further filled in the second recess U2.

[0165] That is, the channel layer 3 not only covers the inner wall of the first recess U1, but also covers the inner wall of the second recess U2, and the contact area between the gate 4 and the channel layer 3 is increased by the inner wall of the second recess U2 on the second partition 72, so as to improve the control ability of the gate 4 on the channel, and further optimize the electrical performance of the semiconductor device 10.

[0166] In some embodiments, referring to FIG. 10, the second recess U2 and the third recess U3 can exist in the semiconductor device 10 at the same time, so as to realize the superposition of the performance optimization of the semiconductor device 10. The features of the second recess U2 and the features of the third recess U3 in this embodiment can refer to the aforementioned embodiments, which will not be described herein.

[0167] FIG. 11 is a front view of the aforementioned FIG. 2, FIG. 6, or FIG. 8.

[0168] In some embodiments, referring to FIG. 11, the two opposite sidewalls of the first recess U1 in the first direction X are recessed towards directions away from each other.

[0169] That is, the sidewalls of the first recess U1 can be arc-shaped, so as to increase the area of the inner wall of the first recess U1, and the area of the channel layer 3 attached to the inner wall of the first recess U1 is increased accordingly, further increasing the path length of the channel formed in the channel layer 3, and optimizing the electrical performance of the semiconductor device 10.

[0170] In some embodiments, referring to FIG. 6, the first electrode 21 and the second electrode 22 each include the conductive layer 2A and the conductive part 2B. That is, the first electrode 21 can include the conductive layer 2A and the conductive part 2B, and the second electrode 22 can also include the conductive layer 2A and the conductive part 2B.

[0171] The upper surface of the substrate 11, the first partition part 71, and the channel layer 3 can enclose a first cavity Q1, and the conductive part 2B is filled in the first cavity Q1, and the conductive layer 2A is arranged between the inner wall of the first cavity Q1 and the conductive part 2B.

[0172] That is, the conductive layer 2A is used to adhere to the surface of the first cavity Q1, and the conductive part 2B is arranged on the side of the conductive layer 2A away from the surface of the first cavity Q1.

[0173] For example, the conductive layer 2A has high conductivity to facilitate Ohmic contact with the channel layer 3 and improve the electrical performance of the semiconductor device 10.

[0174] The conductive part 2B is used to externally connect the entire source or drain to the outside to facilitate the smooth access of the source signal or the drain signal to the semiconductor device 10.

[0175] In this embodiment, the first cavity Q1 enclosed by the upper surface of the substrate 11, the first partition part 71, and the channel layer 3 is used to first adhere the conductive layer 2A for contacting the channel layer 3 to the surface of the first cavity Q1, and then fill the conductive part 2B for electrical connection with the outside in the first cavity Q1, so that the conductive layer 2A can surround the multiple surfaces of the conductive part 2B, thereby increasing the contact area between the part (i.e., the conductive layer 2A) of the first electrode 21 or the second electrode 22 for contacting the channel layer 3 and the part (i.e., the conductive part 2B) for externally connecting the source or the drain, so that the two have better electrical connection effect, and the electrical performance of the semiconductor device 10 can also be optimized.

[0176] The present application also provides a preparation method of the semiconductor device 10.

[0177] FIGS. 12, 13, 14, and 15 are some preparation flowcharts of the semiconductor device 10 provided by the present application, and FIGS. 16-31 are cross-sectional views corresponding to each preparation step of the semiconductor device 10.

[0178] As shown in FIG. 12, the preparation method includes the following steps S1-S4.

[0179] S1: Referring to FIG. 16, a sacrificial layer B is covered on the substrate 11.

[0180] The sacrificial layer B is used to reserve space for the subsequent conductive structures (the first electrode 21 and the second electrode 22), so that the conductive structures are not arranged in advance, and the conductive structures are not damaged in the preparation process of other structures, and the conductive material of the conductive structures does not diffuse in the preparation process of other structures, thereby affecting the electrical performance of other structures.

[0181] S2: Referring to FIG. 18, a first slot K1 is formed.

[0182] Referring to FIG. 18, the first slot K1 extends along the second direction Y, and the sidewall of the first slot K1 extends from the surface of the sacrificial layer B away from the substrate 11 into the substrate 11, that is, the first slot K1 breaks the sacrificial layer B, and continues to etch the substrate 11.

[0183] Referring to FIG. 18, the first slot K1 is used to break the sacrificial layer B into a first sacrificial part B1 and a second sacrificial part B2, and is used to remove at least part of the substrate 11. It can be understood that the part of the first slot K1 in the substrate 11 is a first recess U1.

[0184] Referring to FIG. 18, the first sacrificial part B1 and the second sacrificial part B2 are arranged on both sides of the first recess U1 along the first direction X, and are used to be replaced by the first electrode 21 and the second electrode 22 in the subsequent process.

[0185] The first direction X and the second direction Y are parallel to the substrate 11, and the first direction X and the second direction Y intersect.

[0186] S3: Referring to FIG. 19, a channel layer 3 and a gate 4 are sequentially formed in the first slot K1.

[0187] Exemplarily, it can be understood that in this step S3, referring to FIG. 19, a gate oxide layer 5 is also formed, which is arranged between the gate 4 and the channel layer 3, that is, the channel layer 3, the gate oxide layer 5 and the gate 4 are sequentially formed in the first slot K1.

[0188] Referring to FIG. 19, at least part of the gate 4 is filled in the first recess U1.

[0189] Exemplarily, referring to FIG. 19, in this step S3, the formed gate 4 can be filled only in the first recess U1 (the part of the first slot K1 in the substrate 11), and an insulating part 6 is formed above the gate 4, so that the gate 4 and the insulating part 6 jointly fill the first slot K1.

[0190] Alternatively, exemplarily, the gate 4 can also completely fill the first slot K1, which can be specifically referred to the corresponding FIG. 5 of the foregoing embodiment, and will not be described here.

[0191] Referring to FIG. 19, the channel layer 3 is attached to the inner wall of the first groove K1, i.e., at least part of the channel layer 3 is arranged on the inner wall of the first groove U1, and the opposite sides of the first sacrificial part B1 and the second sacrificial part B2.

[0192] It can be understood that, herein, the "opposite sides of the first sacrificial part B1 and the second sacrificial part B2" refer to the side of the first sacrificial part B1 facing the second sacrificial part B2, and the side of the second sacrificial part B2 facing the first sacrificial part B1.

[0193] S4: Referring to FIGS. 22-25, the first sacrificial part B1 is replaced by the first electrode 21, and the second sacrificial part B2 is replaced by the second electrode 22.

[0194] Exemplarily, referring to FIG. 23, the first electrode 21 can be a conductive structure arranged as a whole, and the second electrode 22 is the same.

[0195] Alternatively, exemplarily, referring to FIG. 25, the first electrode 21 and the second electrode 22 can each include a conductive part 2B and a conductive layer 2A partially surrounding the conductive part 2B.

[0196] Through the above steps S1-S4, the at least one semiconductor device 10 described in the foregoing embodiments, which has a longer channel path and a larger contact area between the source (or drain) and the channel layer 3, can be prepared, and the technical effects corresponding to the preparation steps can be referred to the effect description of the semiconductor device 10 in the foregoing embodiments, which will not be described here again.

[0197] In some embodiments, the foregoing step S4 can include the following steps S41 and S44:

[0198] S41: Referring to FIG. 22, the first sacrificial part B1 and the second sacrificial part B2 are removed to form a plurality of first cavities Q1.

[0199] Referring to FIG. 22, the first cavity Q1 is surrounded by the upper surface of the substrate 11, the first partition part 71, and the channel layer 3.

[0200] S44: Referring to FIG. 23, a conductive structure is filled in the first cavity Q1 to form the first electrode 21 and the second electrode 22.

[0201] Alternatively, in some embodiments, as shown in FIG. 13, the foregoing step S4 can include the following steps S41-S43:

[0202] S41: Referring to FIG. 22, the first sacrificial part B1 and the second sacrificial part B2 are removed to form a plurality of first cavities Q1.

[0203] S42: Referring to FIG. 24, a conductive layer 2A is formed on the inner wall of the first cavity Q1.

[0204] S43: Referring to FIG. 25, the conductive part 2B is formed.

[0205] Referring to FIG. 25, the conductive part 2B is filled in the first cavity Q1, and the conductive layer 2A is arranged between the inner wall of the first cavity Q1 and the conductive part 2B.

[0206] Through this embodiment, the conductive layer 2A can surround the multiple surfaces of the conductive part 2B, thereby increasing the contact area between the part (i.e., the conductive layer 2A) of the first electrode 21 or the second electrode 22 used for contacting the channel layer 3 and the part (i.e., the conductive part 2B) used for realizing the external connection of the source or the drain, so that the two parts have better electrical connection effect, and the electrical performance of the semiconductor device 10 can also be optimized.

[0207] In some embodiments, as shown in FIG. 14, after step S1 and before step S2, the preparation method further comprises:

[0208] S5: Referring to FIG. 17, the second slot K2 is opened, and the first partition part 71 is filled in the second slot K2.

[0209] Referring to FIG. 17, the first partition part 71 extends along the first direction X, and the first partition part 71 can break the sacrificial layer B.

[0210] For example, referring to FIG. 17, the first partition part 71 is used to break the sacrificial layer B into two parts, which are respectively used to form the first electrode 21 and the second electrode 22 in different transistors T (see FIG. 23).

[0211] The first partition part 71 is also used to realize the insulation between the transistors T arranged adjacent to each other along the second direction Y in the subsequent steps.

[0212] Referring to FIG. 17, the first partition part 71 also breaks at least part of the substrate 11.

[0213] For example, the first partition part 71 can completely break the substrate 11 (see FIG. 17), or can also break the substrate 11 to the target position of the substrate 11, for example, the bottom surface of the first partition part 71 can be to the position of the groove bottom of the first groove U1 formed subsequently, and the embodiments of the present application only exemplarily illustrate the structure of the first partition part 71 which completely breaks the substrate 11, and are not limited to the formation of the structure.

[0214] For example, the material of the first partition part 71 has electrical insulation.

[0215] For example, the material of the first partition part 71 is different from the material of the substrate 11, so that the first partition part 71 and the substrate 11 can be etched respectively subsequently.

[0216] Exemplarily, referring to FIG. 14, after step S5, step S2 and step S3 can be continued, referring to FIG. 18, in the case of setting the first partition 71, in step S2, the first slot K1 further disconnects at least part of the first partition 71, and the part of the first slot K1 located in the first partition 71 is the third groove U3.

[0217] As shown in FIG. 14, after step S3, the preparation method further comprises the following steps S6 and S7:

[0218] S6: referring to FIG. 20, removing the first partition 71 and the part of the channel layer 3 exposed after removing the first partition 71, so as to disconnect the two channel layers 3 corresponding to the two transistors T arranged adjacent along the second direction Y.

[0219] Exemplarily, the first partition 71 can be removed first, so as to expose the part of the channel layer 3 between the two transistors T arranged adjacent along the second direction Y, and then the part of the channel layer 3 is removed, so as to achieve the disconnection of the channel layers 3 of the two transistors T.

[0220] S7: referring to FIG. 21, filling the first partition 71 again, so as to achieve the electrical insulation between the two transistors T arranged adjacent along the second direction Y.

[0221] It can be understood that, referring to FIG. 21, in this step S7, the gate 4 and the gate oxide layer 5 are not disconnected, and the gate 4 and the gate oxide layer 5 pass through the first partition 71, so that the two transistors T arranged adjacent along the second direction Y can share the gate 4.

[0222] Through this embodiment, the semiconductor device 10 with multiple transistors T can be prepared, and in particular, multiple transistors T arranged in the second direction Y and sharing the gate 4 can be prepared.

[0223] In some embodiments, as shown in FIG. 14, in the case of setting the first partition 71, after step S2 and before step S3, the preparation method can further comprise:

[0224] S8: referring to FIGS. 26 and 27, continuing to etch the part of the first slot K1 belonging to the first partition 71, so that the groove bottom U3' (referring to FIG. 27) of the third groove U3 is closer to the side surface (i.e. bottom surface) of the substrate 11 away from the first sacrifice part B1, relative to the groove bottom U1' (referring to FIG. 27) of the first groove U1.

[0225] In the figure 27, the first sacrifice part B1, the part of the substrate 11 used for forming the side wall of the first recess U1, and the first partition part 71 are schematically shown in the form of a dashed line box in the orthographic projection on the section, for the purpose of showing the relative position relationship. It can be understood that the structure shown in the dashed line box is hollowed out at the position, and the whole hollowed out part is used for forming the first slot K1.

[0226] The figure 28 is a sectional view corresponding to the figure 27 after filling the trench layer 3 and the gate 4 and the like (i.e. step S4) on the basis of the figure 27 after adding the step S8.

[0227] Referring to the figure 28, through the embodiment, the prepared semiconductor device 10 can be made such that the trench layer 3 not only adheres to the inner wall of the first recess U1, but also adheres to the side wall of the third recess U3, so as to increase the width (the length perpendicular to the path of the trench) of the trench layer 3, improve the on-off ratio of the semiconductor device 10, and at the same time, increase the contact area between the gate 4 and the trench layer 3, so as to improve the control ability of the gate 4 to the trench, and further optimize the electrical performance of the semiconductor device 10.

[0228] In some embodiments, as shown in the figure 15, before the step S1, the preparation method can further include:

[0229] S9: Referring to the figure 29, a second partition part 72 is formed in the substrate 11.

[0230] That is, before covering the sacrifice layer B, the second partition part 72 is embedded in the substrate 11, so that after the step S1 (referring to the figure 29), the sacrifice layer B can cover the second partition part 72, avoiding the second partition part 72 from disconnecting the sacrifice layer B like the first partition part 71.

[0231] Referring to the figure 29, the second partition part 72 extends along the first direction X and disconnects at least part of the substrate 11. In the figure, the second partition part 72 is schematically shown by taking the example that the second partition part 72 completely disconnects the substrate 11.

[0232] Exemplarily, the material of the second partition part 72 can be consistent with the material of the first partition part 71.

[0233] Exemplarily, referring to the figure 15, the step S2 and the step S3 can be continued after the step S1. In the case of setting the second partition part 72, in the step S2, the first slot K1 also disconnects at least part of the second partition part 72, and the part of the first slot K1 in the second partition part 72 is a second recess U2. The structure of the second partition part 72 is similar to the structure of the first partition part 71, and can refer to the foregoing description and the schematic diagram of the first partition part 71, which will not be described herein again.

[0234] On this basis, as shown in FIG. 15, after step S2 and before step S3, the preparation method can further include:

[0235] S10: Referring to FIG. 30, the etching of the part of the first groove K1 belonging to the second partition part 72 is continued, so that the groove bottom U2' of the second groove U2 is closer to the side surface (i.e. the bottom surface) of the substrate 11 away from the first sacrifice part B1 relative to the groove bottom U1' of the first groove U1.

[0236] It can be understood that FIG. 30 is a cross-sectional view of the same position as FIG. 27, and the features related to FIG. 30 can refer to the description of FIG. 26 and FIG. 27, which will not be repeated here.

[0237] FIG. 31 is a cross-sectional view corresponding to the structure after filling the channel layer 3 and the gate 4 (i.e. step S4) on the basis of FIG. 30 after adding step S9 and step S10.

[0238] Referring to FIG. 31, through this embodiment, the channel layer 3 of the prepared semiconductor device 10 can be attached not only to the inner wall of the first groove U1 but also to the side wall of the second groove U2, so that the width (length perpendicular to the channel path) of the channel layer 3 can also be increased, and the on-off ratio of the semiconductor device 10 can also be improved. At the same time, the contact area between the gate 4 and the channel layer 3 is also increased, the control ability of the gate 4 to the channel is improved, and the electrical performance of the semiconductor device 10 is further optimized.

[0239] For example, some of the preparation steps shown in FIG. 14 and FIG. 15 can be performed synchronously, for example, step S8 can be performed synchronously with step S10, i.e. the etching of the second groove U2 and the third groove U3 is continued synchronously, so that the second groove U2 with a relatively deep depth (relative to the depth of the first groove U1) and the third groove U3 with a relatively deep depth can be formed, thereby realizing the accumulation of the optimization of the electrical performance of the semiconductor device 10.

[0240] Of course, it can be understood that the steps shown in FIG. 15 can also be performed alone to form a semiconductor device 10 with the structure shown in FIG. 9 as described above.

[0241] For example, the preparation method can further include other steps, for example, after step S2, the part of the substrate 11 belonging to the side wall of the first groove U1 is etched again, so that the side wall of the first groove U1 is recessed towards the direction away from each other, forming a semiconductor device 10 as shown in FIG. 11, further optimizing the electrical performance of the semiconductor device 10.

[0242] The above merely provides the specific implementation of the present application, but the protection scope of the present application is not limited to this. Any person skilled in the art can think of the changes or replacements within the technical range disclosed by the present application, and the changes or replacements should be covered in the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

Claims

1. A semiconductor device, characterized by, The substrate is provided with a first recess; A first electrode and a second electrode are arranged on the substrate and are arranged on opposite sides of the first recess along a first direction; The first direction is parallel to the substrate; A channel layer is arranged at least partially on the inner wall of the first recess and on the opposite sides of the first electrode and the second electrode; A gate is arranged at least partially in the first recess. The gate comprises a first sub-portion and a second sub-portion arranged integrally, the first sub-portion is arranged in the first recess, and the second sub-portion is arranged between the first electrode and the second electrode.

2. The semiconductor device according to claim 1, wherein The surface of the gate away from the bottom of the first recess is closer to the bottom of the first recess than the surface of the first electrode and the second electrode facing the substrate.

3. The semiconductor device of claim 1, wherein Further comprising:

4. The semiconductor device according to claim 3, wherein An insulating portion is arranged on the side of the gate away from the bottom of the first recess, and at least part of the insulating portion is arranged between the first electrode and the second electrode. The substrate further comprises a second recess arranged at the bottom of the first recess; 5. The semiconductor device according to any one of Claims 1 to 4, wherein Part of the channel layer is further arranged on the inner wall of the second recess; and part of the gate is further arranged in the second recess. The two side walls of the first recess opposite in the first direction are recessed in directions away from each other.

6. The semiconductor device according to any one of Claims 1 to 5, wherein The substrate further comprises a plurality of transistors, each transistor comprising the substrate, the first electrode, the second electrode, the channel layer and the gate; the plurality of transistors are arranged in an array along the first direction and a second direction; the second direction is parallel to the substrate and intersects the first direction; 7. The semiconductor device according to any one of Claims 1 to 6, wherein At least two transistors arranged adjacent along the first direction share the second electrode. Further comprising:

8. The semiconductor device of claim 7, wherein, A first partition portion is arranged between two transistors arranged adjacent along the second direction; The gates of at least two transistors arranged adjacent along the second direction penetrate the first partition portion and are electrically connected to each other, and the channel layers, the first electrodes and the second electrodes of at least two transistors arranged adjacent along the second direction are electrically insulated by the first partition portion. The first partition portion comprises a third recess arranged between two first recesses arranged adjacent along the second direction and communicating with the first recess; the bottom of the third recess is closer to the side surface of the substrate away from the first electrode than the bottom of the first recess; 9. The semiconductor device of claim 8, wherein, Part of the gate is further arranged in the third recess, and the gates of at least two transistors arranged adjacent along the second direction penetrate the first partition portion through the third recess; part of the channel layer is further arranged on the two side walls opposite in the second direction of the third recess. The first electrode and the second electrode each comprise a conductive layer and a conductive portion; 10. The semiconductor device according to claim 8 or 9, characterized by The upper surface of the substrate, the first partition portion and the channel layer form a first cavity, the conductive portion is arranged in the first cavity, and the conductive layer is arranged between the inner wall of the first cavity and the conductive portion. Covering a sacrificial layer on a substrate; 11. A method of manufacturing a semiconductor device, characterized by, Forming a first recess; ​ ​ The first slot extends along a second direction, and a sidewall of the first slot extends from a surface of the sacrificial layer away from the substrate into the substrate; the first slot separates the sacrificial layer into a first sacrificial part and a second sacrificial part, and a portion of the first slot in the substrate is a first recess; the first sacrificial part and the second sacrificial part are located on two sides of the first recess along a first direction; the first direction and the second direction are parallel to the substrate, and the first direction intersects the second direction; A channel layer and a gate are sequentially formed in the first slot; at least part of the channel layer is arranged on an inner wall of the first recess, and opposite sides of the first sacrificial part and the second sacrificial part; at least part of the gate is filled in the first recess; The first sacrificial part is replaced by a first electrode, and the second sacrificial part is replaced by a second electrode.

12. The method of claim 11, wherein, After covering the substrate with the sacrificial layer and before forming the first slot, the method further comprises: A second slot is formed, and a first partition part is filled in the second slot; the first partition part extends along the first direction, and the first partition part separates the sacrificial layer and at least part of the substrate; The first slot also separates at least part of the first partition part, and a portion of the first slot in the first partition part is a third recess; After sequentially forming the channel layer and the gate in the first slot, the method further comprises: Removing the first partition part and a portion of the channel layer exposed after removing the first partition part; The first partition part is filled again.

13. The method of claim 12, wherein, After forming the first slot and before sequentially forming the channel layer and the gate in the first slot, the method further comprises: Continuing to etch the portion of the first slot belonging to the first partition part, so that a bottom of the third recess is closer to a side surface of the substrate away from the first sacrificial part than a bottom of the first recess.

14. The production method according to any one of claims 11 to 13, characterized by, Before covering the substrate with the sacrificial layer, the method further comprises: A second partition part is formed in the substrate; the second partition part extends along the first direction and separates at least part of the substrate; After forming the sacrificial layer, the sacrificial layer covers the second partition part; the first slot also separates at least part of the second partition part, and a portion of the first slot in the second partition part is a second recess; After forming the first slot and before sequentially forming the channel layer and the gate in the first slot, the method further comprises: Continuing to etch the portion of the first slot belonging to the second partition part, so that a bottom of the second recess is closer to a side surface of the substrate away from the first sacrificial part than a bottom of the first recess.

15. The production method according to any one of claims 12 to 14, characterized by, The first electrode and the second electrode each comprise a conductive layer and a conductive part; The replacing the first sacrificial part with the first electrode and the replacing the second sacrificial part with the second electrode comprises: Removing the first sacrificial part and the second sacrificial part to form a plurality of first cavities; an upper surface of the substrate, the first partition part, and the channel layer enclose the first cavities; forming the conductive layer on an inner wall of the first chamber; forming the conductive portion; the conductive portion is filled in the first chamber, and the conductive layer is arranged between the inner wall of the first chamber and the conductive portion.

16. An integrated circuit, comprising: comprising: the semiconductor device according to any one of claims 1 to 10; an electronic device electrically connected to the semiconductor device.

17. An electronic device, comprising: comprising: the integrated circuit according to claim 16; a circuit board on which the integrated circuit is disposed.

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