Gallium nitride power device and preparation method therefor
By alternating compressive and tensile dielectric layers in GaN HEMT devices, the electric field distribution is adjusted, which solves the problem of excessively high electric field strength near the drain edge of the gate, improves the breakdown voltage of the device, and reduces the on-resistance.
Patent Information
- Application Number
- PCT/CN2024/100403
- Authority / Receiving Office
- WO · WO
- Patent Type
- Applications
- Current Assignee / Owner
- Filing Date
- 2024-06-20
- Publication Date
- 2025-12-26
AI Technical Summary
In existing GaN HEMT devices, the electric field strength near the drain edge of the gate is too high, which causes the device to break down and limits its application in high-voltage fields.
In GaN HEMT devices, a dielectric layer structure is adopted with alternating compressive and tensile dielectric layers. The width of the compressive dielectric layer gradually decreases, while the width of the tensile dielectric layer gradually increases, and they are connected at the junction to adjust the electric field distribution in the drift region.
It effectively reduces the electric field strength near the drain edge of the gate, improves the breakdown voltage of the device, and can reduce or increase the on-resistance of the device without increasing or decreasing it.
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Figure CN2024100403_26122025_PF_FP_ABST
Abstract
Description
Gallium nitride power devices and their fabrication methods Technical Field
[0001] This application relates to the field of semiconductor technology, specifically to a gallium nitride power device and its fabrication method. Background Technology
[0002] Gallium nitride (GaN) has attracted widespread attention in the field of high-voltage power devices due to its wide bandgap and high electron mobility. However, one of the important factors limiting the application of GaN HEMT (High Electron Mobility Transistor) devices in high-voltage fields is the device breakdown phenomenon caused by excessively high electric field strength near the drain edge of the gate.
[0003] Therefore, how to reduce the peak electric field near the drain edge of the gate in GaN HEMT devices without increasing the on-resistance of the devices, thereby improving the breakdown voltage of the devices, is an urgent problem to be solved. Technical solutions
[0004] The gallium nitride power device and its fabrication method provided in this application can solve the problem of device breakdown caused by excessively high electric field strength near the drain edge of the gate in existing GaN HEMT devices.
[0005] To address the aforementioned technical problems, this application provides a gallium nitride power device, comprising:
[0006] Substrate;
[0007] An epitaxial layer is disposed on one side of the substrate;
[0008] A gate structure, a source, and a drain are disposed at intervals on the side of the epitaxial layer away from the substrate, and the source and the drain are located on opposite sides of the gate structure; wherein, the epitaxial layer located between the gate structure and the drain is defined as a first region of the epitaxial layer, and the epitaxial layer located between the gate structure and the source is defined as a second region of the epitaxial layer;
[0009] A first dielectric layer is disposed on the side of the epitaxial layer away from the substrate and located in the first region, wherein the first dielectric layer includes a compressive stress dielectric layer and a tensile stress dielectric layer disposed in the same layer and extending along a first direction;
[0010] In the first direction, the width of the compressive stress dielectric layer gradually decreases, and the width of the tensile stress dielectric layer gradually increases; in the second direction, the compressive stress dielectric layer is connected to the tensile stress dielectric layer, the first direction is the direction from the gate structure to the drain, and the second direction intersects with the first direction.
[0011] To address the aforementioned technical problems, another technical solution provided in this application is: a method for fabricating a gallium nitride power device, comprising:
[0012] Provide substrate;
[0013] An epitaxial layer is formed on one side of the substrate; wherein the epitaxial layer defines a gate structure region, a source region, and a drain region, and the source region and the drain region are located on both sides of the gate structure region; and the epitaxial layer located between the gate structure region and the drain region is defined as a first region of the epitaxial layer, and the epitaxial layer located between the gate structure region and the source region is defined as a second region of the epitaxial layer;
[0014] A first dielectric layer is formed on the side of the epitaxial layer opposite to the substrate corresponding to the first region. The first dielectric layer includes a compressive stress dielectric layer and a tensile stress dielectric layer disposed in the same layer and extending along a first direction. In the first direction, the width of the compressive stress dielectric layer gradually decreases, and the width of the tensile stress dielectric layer gradually increases. In a second direction, the compressive stress dielectric layer is in contact with the tensile stress dielectric layer. The first direction is the direction from the gate structure region to the drain region, and the second direction intersects with the first direction. Beneficial effects
[0015] The beneficial effects of this application are as follows: Unlike existing technologies, the gallium nitride power device and its fabrication method provided in this application include a substrate, an epitaxial layer, a gate structure, a source electrode, a drain electrode, and a first dielectric layer. The epitaxial layer is disposed on one side of the substrate. The gate structure, source electrode, and drain electrode are spaced apart on the side of the epitaxial layer facing away from the substrate. The epitaxial layer located between the gate structure and the drain electrode is defined as a first region of the epitaxial layer, and the epitaxial layer located between the gate structure and the source electrode is defined as a second region of the epitaxial layer. The first dielectric layer is disposed on the side of the epitaxial layer facing away from the substrate and is located in the first region. The first dielectric layer includes a compressive stress dielectric layer and a tensile stress dielectric layer disposed in the same layer and extending along a first direction. The device has a multilayer structure. In the first direction from the gate structure to the drain, the width of the compressive dielectric layer gradually decreases, while the width of the tensile dielectric layer gradually increases. In the second direction intersecting the first direction, the compressive dielectric layer and the tensile dielectric layer are connected. This results in a wider width occupied by the compressive dielectric in the drift region at the gate edge, leading to a lower 2DEG concentration below the gate edge. This effectively reduces the peak electric field, thus solving the problem of excessively high electric field strength near the drain edge, which can easily cause device breakdown. In the drift region at the drain edge, the tensile dielectric occupies a wider width, resulting in a higher 2DEG concentration below the drain edge. This achieves the effect of not increasing or even reducing the overall on-resistance of the device. Attached Figure Description
[0016] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0017] Figure 1 is a partial structural schematic diagram of the gallium nitride power device provided in the first embodiment of this application from a first perspective;
[0018] Figure 2 is a partial structural schematic diagram of the gallium nitride power device provided in the first embodiment of this application after omitting the passivation layer, from a second perspective.
[0019] Figure 3 is a partial structural cross-sectional view of the first embodiment of this application along line AA in Figure 2;
[0020] Figure 4 is a partial structural cross-sectional view of the first embodiment of this application along line BB in Figure 2;
[0021] Figure 5 is a partial structural schematic diagram of the gallium nitride power device provided in the second embodiment of this application from a second perspective;
[0022] Figure 6 is a partial structural schematic diagram of the gallium nitride power device provided in the third embodiment of this application from a second perspective;
[0023] Figure 7 is a partial structural schematic diagram of the gallium nitride power device provided in the fourth embodiment of this application from a second perspective;
[0024] Figure 8 is a schematic flowchart of a method for fabricating a gallium nitride power device according to an embodiment of this application;
[0025] Figure 9 is a flowchart illustrating an embodiment of step S3 in Figure 8;
[0026] Figure 10 is a schematic diagram of the intermediate product of the gallium nitride power device after step S1 in Figure 8;
[0027] Figure 11 is a schematic diagram of the intermediate product of the gallium nitride power device after step S2 in Figure 8;
[0028] Figure 12 is a schematic diagram of an intermediate product of a gallium nitride power device fabricated after step S2 and before step S3 in Figure 8, showing the gate structure, source, and drain.
[0029] Figure 13 is a schematic diagram of the intermediate product of the gallium nitride power device after step S31 in Figure 9;
[0030] Figure 14 is a schematic diagram of the intermediate product of the gallium nitride power device after step S32 in Figure 9;
[0031] Figure 15 is a schematic diagram of the intermediate product of the gallium nitride power device after step S33 in Figure 9;
[0032] Figure 16 is a schematic diagram of the gallium nitride power device after step S34 in Figure 9.
[0033] Icon labels:
[0034] Substrate-10; Base-11; Transition layer-12; Epitaxial layer-20; First semiconductor layer-21; Second semiconductor layer-22; Gate structure-30; Capping layer-31; Gate-32; First dielectric layer-60; Compressive stress dielectric layer-61; Tensile stress dielectric layer-62; Second dielectric layer-70; Passivation layer-80;
[0035] Tensile stress medium material layer-601; Compressive stress medium material layer-602;
[0036] First region - A1; Second region - A2; Gate structure region - B1; Source region - B2; Drain region - B3. Embodiments of the present invention
[0037] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of the embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this application.
[0038] In the following description, specific details such as particular system architectures, interfaces, and technologies are presented for illustrative purposes rather than for limiting purposes, in order to provide a thorough understanding of this application.
[0039] The terms "first," "second," and "third" in this application are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Therefore, a feature defined as "first," "second," or "third" may explicitly or implicitly include at least one of the stated features. All directional indications (such as up, down, left, right, front, back, etc.) in the embodiments of this application are only used to explain the relative positional relationships and movement of components in a specific posture (as shown in the accompanying drawings). If the specific posture changes, the directional indications will also change accordingly. The terms "comprising" and "having," and any variations thereof, in the embodiments of this application are intended to cover non-exclusive inclusion.
[0040] In this document, the term "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of this phrase in various places in the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment that is mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.
[0041] The present application will now be described in detail with reference to the accompanying drawings and embodiments.
[0042] Referring to Figures 1-7, Figure 1 is a partial structural schematic diagram of the gallium nitride power device provided in the first embodiment of this application from a first perspective; Figure 2 is a partial structural schematic diagram of the gallium nitride power device provided in the first embodiment of this application after omitting the passivation layer from a second perspective; Figure 3 is a partial structural cross-sectional view of the first embodiment of this application along line AA in Figure 2; Figure 4 is a partial structural cross-sectional view of the first embodiment of this application along line BB in Figure 2; Figure 5 is a partial structural schematic diagram of the gallium nitride power device provided in the third embodiment of this application from a second perspective; Figure 6 is a partial structural schematic diagram of the gallium nitride power device provided in the fourth embodiment of this application from a second perspective; and Figure 7 is a partial structural schematic diagram of the gallium nitride power device provided in the fourth embodiment of this application from a second perspective.
[0043] Specifically, the gallium nitride power device provided in this application includes a substrate 10, an epitaxial layer 20, a gate structure 30, a source 40, a drain 50, and a first dielectric layer 60.
[0044] In one embodiment, the substrate 10 includes a base 11 and a transition layer 12. Silicon (Si) or sapphire (Al₂O₃) can be used as the base 11; AlGaN can be used as the transition layer 12.
[0045] In other embodiments, substrate 10 may also consist of only base 11.
[0046] The epitaxial layer 20 includes a first semiconductor layer 21 and a second semiconductor layer 22. The first semiconductor layer 21 is disposed on one side of the substrate 10 as a buffer layer of the device, and the second semiconductor layer 22 is disposed on the side of the first semiconductor layer 21 away from the substrate 10 as a barrier layer of the device.
[0047] A two-dimensional electron gas (2DEG) is formed between the interface of the first semiconductor layer 21 and the second semiconductor layer 22 to serve as the channel layer of the device.
[0048] In the embodiments of this application, the material of the first semiconductor layer 21 includes GaN; the material of the second semiconductor layer 22 includes AlGaN.
[0049] The gate structure 30, source 40, and drain 50 are spaced apart on the side of the epitaxial layer 20 away from the substrate 10, and are specifically disposed on the surface of the second semiconductor layer 22 away from the first semiconductor layer 21. The source 40 and drain 50 are located on opposite sides of the gate structure 30.
[0050] In one embodiment, referring to Figure 3 or Figure 4, the gate structure 30 includes a capping layer 31 and a gate 32. The capping layer 31 is disposed between the gate 32 and the second semiconductor layer 22. Taking a gallium nitride power device as an enhancement-mode device as an example, the capping layer 31 serves as a p-type nitride gate layer. The capping layer 31 is also used to deplete the 2DEG under the gate structure 30 to form an enhancement-mode device. Specifically, the material of the capping layer 31 includes, but is not limited to, p-GaN, p-AlGaN, p-InGaN, or p-InAlGaN, etc., and is not limited here.
[0051] The gate 32, source 40, and drain 50 are formed of conductive metal material and are used for electrical connection with external circuits. In some embodiments, the conductive metal system of the gate 32, source 40, and drain 50 includes, but is not limited to, Ti, Al, Ni, Au, or Ta, as well as alloys or compounds containing the above metal systems.
[0052] Referring to Figures 1, 2, and 5-7, in this embodiment, the epitaxial layer 20 located between the gate structure 30 and the drain 50 is defined as the first region A1 of the epitaxial layer 20, and the epitaxial layer 20 located between the gate structure 30 and the source 40 is defined as the second region A2 of the epitaxial layer 20. A first dielectric layer 60 is disposed on the side of the epitaxial layer 20 facing away from the substrate 10 and located in the first region A1. The first dielectric layer 60 includes a compressive stress dielectric layer 61 and a tensile stress dielectric layer 62 disposed on the same layer and extending along a first direction from the gate structure 30 to the drain 50. In the first direction, the width of the compressive stress dielectric layer 61 gradually decreases, and the width of the tensile stress dielectric layer 62 gradually increases. In a second direction intersecting the first direction, the compressive stress dielectric layer 61 and the tensile stress dielectric layer 62 are connected.
[0053] The first direction can be understood as the length direction, and the second direction can be understood as the width direction.
[0054] In this application, "gradually decreasing" means decreasing linearly or decreasing stepwise; "gradually increasing" means increasing linearly or increasing stepwise.
[0055] In this application, "compressive stress medium layer 61 and tensile stress medium layer 62 are in contact" means that the edges of the compressive stress medium layer 61 and the tensile stress medium layer 62 are in contact with each other and there is no gap between them.
[0056] In some embodiments, the compressive stress medium layer 61 is made of one or a combination of silicon nitride, silicon oxide, and silicon oxynitride, and is used to generate compressive stress on the underlying film layer. The tensile stress medium layer 62 is made of one or a combination of silicon nitride, silicon oxide, and silicon oxynitride, and is used to generate tensile stress on the underlying film layer.
[0057] Specifically, the 2DEG concentration is closely related to the polarization intensity. The compressive stress dielectric layer 61 counteracts the tensile stress on the barrier layer, thereby reducing piezoelectric polarization. Consequently, the 2DEG concentration below the compressive stress dielectric layer 61 decreases, increasing the device's threshold voltage. Simultaneously, because the 2DEG concentration decreases, the depletion region formed in the device's off-state is larger, the electric field strength decreases, and the peak electric field near the drain 50 edge of the gate 32 also decreases. Since the device's current collapse is closely related to the electric field strength, the stronger the electric field, the more severe the current collapse. Therefore, the compressive stress dielectric layer 61 can improve the device's current collapse. On the other hand, the tensile stress dielectric layer 62 can enhance piezoelectric polarization, thereby increasing the 2DEG concentration and reducing the channel resistance. Therefore, the gallium nitride device provided in this application can more effectively adjust the electric field distribution of the drift region by setting a compressive stress dielectric layer 61 and a tensile stress dielectric layer 62 with gradually increasing or decreasing widths along the first direction on the first region A1, thereby improving the breakdown voltage of the device. Furthermore, by adjusting the widths of the compressive stress dielectric layer 61 and the tensile stress dielectric layer 62, the on-resistance of the device can be reduced or even increased.
[0058] Understandably, in the first direction, the width of the compressive stress dielectric layer 61 gradually decreases, while the width of the tensile stress dielectric layer 62 gradually increases. In the second direction, which intersects with the first direction, the compressive stress dielectric layer 61 and the tensile stress dielectric layer 62 are connected. This results in a wider width occupied by the compressive stress dielectric in the drift region at the edge of the gate 32, leading to a lower 2DEG concentration below the edge of the gate 32. This effectively reduces the peak electric field, thus solving the problem of excessively high electric field strength near the drain 50 edge of the gate 32, which can easily cause device breakdown. In the drift region at the edge of the drain 50, the tensile stress dielectric occupies a wider width, resulting in a higher 2DEG concentration below the edge of the drain 50. This achieves the effect of not increasing or even reducing the overall on-resistance of the device.
[0059] In one embodiment, the stress value of the compressive stress medium layer 61 ranges from -0.1 to -2 GPa (where "-" indicates compressive stress). For example, the stress value of the compressive stress medium layer 61 may be -0.1 GPa, -0.5 GPa, -1 GPa, -1.5 GPa, or -2 GPa, etc., which are not limited here and can be selected according to the actual situation.
[0060] In one embodiment, the tensile stress of the tensile stress medium layer 62 ranges from 0.1 to 2 GPa. For example, the stress value of the tensile stress medium layer 62 may be 0.1 GPa, 0.5 GPa, 1 GPa, 1.5 GPa, or 2 GPa, etc., which are not limited here and can be selected according to the actual situation.
[0061] In some embodiments, the number of compressive stress medium layer 61 and tensile stress medium layer 62 may be one or more.
[0062] For example, referring to Figure 5, the number of compressive stress medium layer 61 and tensile stress medium layer 62 can both be one.
[0063] Alternatively, referring to Figure 6, the number of compressive stress medium layers 61 can be one, and the number of tensile stress medium layers 62 can be two, with the two tensile stress medium layers 62 located on both sides of the compressive stress medium layer 61 and in contact with the compressive stress medium layer 61.
[0064] Alternatively, referring to Figure 7, the number of tensile stress medium layers 62 can be one, and the number of compressive stress medium layers 61 can be two, with the two compressive stress medium layers 61 located on both sides of the tensile stress medium layer 62 and in contact with the tensile stress medium layer 62.
[0065] Alternatively, referring to Figure 2, there are multiple compressive stress medium layers 61 and multiple tensile stress medium layers 62, and the multiple compressive stress medium layers 61 and multiple tensile stress medium layers 62 are alternately arranged and connected along a second direction perpendicular to the first direction.
[0066] The shape of each compressive stress medium layer 61 and each tensile stress medium layer 62 can be trapezoidal (isosceles trapezoid, right trapezoid) or triangular (such as isosceles triangle, right triangle). The illustration in this application uses a trapezoid as an example.
[0067] Specifically, the alternating arrangement of multiple compressive stress dielectric layers 61 and multiple tensile stress dielectric layers 62 enables the 2DEG in the drift region between the gate structure 30 and the drain 50 to be uniformly distributed in the second direction, resulting in a lower electric field peak.
[0068] This application uses the example of multiple compressive stress medium layers 61 and tensile stress medium layers 62 to illustrate the concept.
[0069] Specifically, referring to Figure 2, in the second direction, adjacent compressive stress dielectric layers 61 and tensile stress dielectric layers 62 are contacted and there is no gap between them. Compared to the scheme where there is a gap between the compressive stress dielectric layer 61 and the tensile stress dielectric layer 62, the embodiment of this application does not require etching the barrier layer (second semiconductor layer 22) corresponding to the gap region, thus providing a better process window. Furthermore, it allows for the utilization of more drift regions in the device.
[0070] Furthermore, in this application, at one end near the gate structure 30, the total width of the plurality of compressive stress dielectric layers 61 along the second direction is the first total width, and the total width of the plurality of tensile stress dielectric layers 62 along the second direction is the second total width, with the first total width being greater than the second total width. This results in a wider width occupied by the compressive stress dielectric in the drift region at the edge of the gate structure 30, thus reducing the 2DEG concentration below the edge of the gate 32 and effectively lowering the peak electric field. This solves the problem of excessively high electric field strength near the drain 50 edge of the gate 32, which can easily lead to device breakdown.
[0071] Near the drain 50, the total width of the multiple tensile dielectric layers 62 along the second direction is the third total width, and the total width of the multiple compressive dielectric layers 61 along the second direction is the fourth total width, with the third total width being greater than the fourth total width. This results in a wider width occupied by the tensile dielectric in the drift region at the edge of the drain 50, leading to a high 2DEG concentration below the edge of the drain 50, achieving the effect of not increasing or even reducing the overall on-resistance of the device.
[0072] The following description takes as an example that the width of the compressive stress medium layer 61 decreases linearly in the first direction, while the width of the tensile stress medium layer 62 increases linearly.
[0073] Specifically, referring to Figure 2, since the width of the compressive stress dielectric layer 61 gradually decreases and the width of the tensile stress dielectric layer 62 gradually increases in the first direction, and the compressive stress dielectric layer 61 and the tensile stress dielectric layer 62 are connected in the second direction intersecting the first direction, when there are multiple compressive stress dielectric layers 61 and tensile stress dielectric layers 62 that are alternate and connected, at the end near the gate structure 30, each compressive stress dielectric layer 61 has the same width and is a first width w1, and each tensile stress dielectric layer 62 has the same width and is a second width w2; the first width w1 is greater than the second width w2; the distance between two adjacent compressive stress dielectric layers 61 is equal to the second width w2, and the distance between two adjacent tensile stress dielectric layers 62 is equal to the first width w1. At the end near the drain electrode 50, each compressive stress medium layer 61 has the same width and is the third width w3, and each tensile stress medium layer 62 has the same width and is the fourth width w4, the fourth width w4 being greater than the third width w3; the distance between two adjacent compressive stress medium layers 61 is equal to the fourth width w4; the distance between two adjacent tensile stress medium layers 62 is equal to the third width w3.
[0074] And understandably, the first width w1 is equal to the fourth width w4, and the second width w2 is equal to the third width w3.
[0075] It should be noted that, since the compressive stress dielectric layer 61 shown in Figure 2 is an isosceles trapezoid, due to the device structure design, the compressive stress dielectric layer 61 located at the device edge is not complete along the width direction. Specifically, the width of the end of the compressive stress dielectric layer 61 located at the device edge near the edge of the gate structure 30 is less than the first width w1, and the width of the end of the compressive stress dielectric layer 61 located at the device edge near the edge of the drain 50 is less than or equal to the third width w3. Similarly, the width of the end of the tensile stress dielectric layer 62 located at the device edge near the edge of the gate structure 30 is less than or equal to the second width w2, and the width of the end of the tensile stress dielectric layer 62 located at the device edge near the edge of the drain 50 is less than the fourth width w4.
[0076] Furthermore, it is understandable that when the compressive stress medium layer 61 is in the shape of a right trapezoid or a right triangle, setting the right-angled side of the right trapezoid or right triangle to be located at the edge of the device can avoid the above situation.
[0077] In one embodiment, the first width w1 and the fourth width w4 are both in the range of 0.1µm to 1mm. The second width w2 and the third width w3 are both in the range of 0 to 1mm.
[0078] For example, the first width w1 and the fourth width w4 are the same and are both 0.1um, 5um, 50um, 200um, 500um, 700um, or 1mm, etc. The second width w2 and the third width w3 are the same and are both 0um (triangle), 0.1um, 5um, 50um, 200um, 500um, 700um, or 1mm, etc. There are no restrictions here, as long as the first total width is greater than the second total width, and the third total width is greater than the fourth total width.
[0079] Specifically, by adjusting the parameters of the first width w1, the second width w2, the third width w3, and the fourth width w4, the electric field distribution in the drift region can be adjusted more effectively, thereby improving the device breakdown voltage and achieving the effect of not increasing or even reducing the device's on-resistance.
[0080] In one embodiment, the compressive stress medium layer 61 and the tensile stress medium layer 62 have the same thickness and have a first thickness H1, wherein the first thickness H1 ranges from 10 to 1000 nm. For example, the first thickness H1 can be 10 nm, 100 nm, 300 nm, 500 nm, 700 nm or 1000 nm, etc., and is not limited here. It is set according to the actual situation.
[0081] Specifically, if the first thickness H1 is too thin, the passivation effect of the dielectric layer will be poor; if the first thickness H1 is too thick, the field plate metal subsequently deposited on the dielectric layer will be too far from the 2DEG, resulting in a poor adjustment effect on the 2DEG.
[0082] In one embodiment, referring to Figures 1, 3, and 4, the gallium nitride power device further includes a second dielectric layer 70, which is disposed on the side of the epitaxial layer 20 away from the substrate 10 and located in the second region A2. The second dielectric layer 70 is a tensile dielectric layer, which can be made of the same material as the tensile dielectric layer 62. Specifically, setting the second dielectric layer 70 as a tensile dielectric layer can increase the 2DEG concentration between the source and gate, and reduce the on-resistance.
[0083] Furthermore, the area surrounding the gate structure 30 and within a certain range is defined as the gate structure region. The gate structure region has a passivation layer 80 that surrounds the gate structure 30, and the material of the passivation layer 80 is the same as the material of the tensile stress dielectric layer 62, thereby increasing the 2DEG concentration below the gate structure 30 and reducing the on-resistance.
[0084] Specifically, the gallium nitride power device provided in this application has the following characteristics: in the first direction, the width of the compressive stress dielectric layer 61 in the first dielectric layer 60 gradually decreases, while the width of the tensile stress dielectric layer 62 gradually increases. In the second direction intersecting the first direction, the compressive stress dielectric layer 61 and the tensile stress dielectric layer 62 are connected. This results in a wider width occupied by the compressive stress dielectric in the drift region at the edge of the gate 32, thus reducing the 2DEG concentration below the edge of the gate 32 and effectively lowering the peak electric field. This solves the problem of excessively high electric field strength near the drain 50 edge of the gate 32, which can easily lead to device breakdown. In the drift region at the edge of the drain 50, the tensile stress dielectric occupies a wider width, thus increasing the 2DEG concentration below the edge of the drain 50. This achieves the effect of not increasing or even reducing the overall on-resistance of the device.
[0085] Referring to Figures 8-16, Figure 8 is a flowchart illustrating a method for fabricating a gallium nitride power device according to an embodiment of this application; Figure 9 is a flowchart illustrating an embodiment of step S3 in Figure 8; Figure 10 is an intermediate product diagram of the gallium nitride power device after step S1 in Figure 8; Figure 11 is an intermediate product diagram of the gallium nitride power device after step S2 in Figure 8; Figure 12 is an intermediate product diagram of the gallium nitride power device in Figure 8 with gate structure, source, and drain prepared after step S2 and before step S3; Figure 13 is an intermediate product diagram of the gallium nitride power device after step S31 in Figure 9; Figure 14 is an intermediate product diagram of the gallium nitride power device after step S32 in Figure 9; Figure 15 is an intermediate product diagram of the gallium nitride power device after step S33 in Figure 9; and Figure 16 is a product diagram of the gallium nitride power device after step S34 in Figure 9.
[0086] Specifically, this application also provides a method for fabricating a gallium nitride power device, comprising:
[0087] Step S1: Provide substrate 10.
[0088] In one embodiment, specifically referring to FIG10, the substrate 10 includes a base 11 and a transition layer 12. Silicon (Si) or sapphire (Al2O3) can be used as the base 11; AlGaN can be used as the transition layer 12.
[0089] In other embodiments, substrate 10 may also consist of only base 11.
[0090] Step S2: An epitaxial layer 20 is formed on one side of the substrate 10; wherein the epitaxial layer 20 defines a gate structure region B1, a source region B2, and a drain region B3, and the source region B2 and the drain region B3 are located on both sides of the gate structure region B1; and the epitaxial layer 20 located between the gate structure region B1 and the drain region B3 is defined as the first region A1 of the epitaxial layer 20, and the epitaxial layer 20 located between the gate structure region B1 and the source region B2 is defined as the second region A2 of the epitaxial layer 20.
[0091] Referring specifically to Figure 11, the epitaxial layer 20 includes a first semiconductor layer 21 and a second semiconductor layer 22. The first semiconductor layer 21 is disposed on one side of the substrate 10, serving as a buffer layer for the device, while the second semiconductor layer 22 is disposed on the side of the first semiconductor layer 21 facing away from the substrate 10, serving as a barrier layer for the device. Specifically, a two-dimensional electron gas (2DEG) is also formed between the interface of the first semiconductor layer 21 and the second semiconductor layer 22, serving as a channel layer for the device.
[0092] In the embodiments of this application, the material of the first semiconductor layer 21 includes GaN; the material of the second semiconductor layer 22 includes AlGaN.
[0093] Step S3: A first dielectric layer 60 is formed on the side of the epitaxial layer 20 opposite to the substrate 10 corresponding to the first region A1. The first dielectric layer 60 includes a compressive stress dielectric layer 61 and a tensile stress dielectric layer 62 disposed in the same layer and extending along a first direction. In the first direction, the width of the compressive stress dielectric layer 61 gradually decreases and the width of the tensile stress dielectric layer 62 gradually increases. In the second direction, the compressive stress dielectric layer 61 and the tensile stress dielectric layer 62 are connected.
[0094] The first direction is the direction from the gate structure region B1 to the drain region B3, and the second direction intersects with the first direction. The first direction can be understood as the length direction, and the second direction as the width direction.
[0095] In some embodiments, the number of compressive stress medium layer 61 and tensile stress medium layer 62 can be one or more, which will not be elaborated here. For details, please refer to Figures 2, 5-7.
[0096] This application uses the example of multiple compressive stress medium layers 61 and tensile stress medium layers 62 for illustration.
[0097] In this design, near the end of the gate structure 30, the total width of the multiple compressive stress dielectric layers 61 along the second direction is the first total width, and the total width of the multiple tensile stress dielectric layers 62 along the second direction is the second total width. The first total width is greater than the second total width. This results in a wider width occupied by the compressive stress dielectric in the drift region at the edge of the gate structure 30, leading to a lower 2DEG concentration below the edge of the gate 32. This effectively reduces the peak electric field, thus solving the problem of excessively high electric field strength near the drain 50 edge of the gate 32, which can easily cause device breakdown.
[0098] Near the drain 50, the total width of the multiple tensile dielectric layers 62 along the second direction is the third total width, and the total width of the multiple compressive dielectric layers 61 along the second direction is the fourth total width, with the third total width being greater than the fourth total width. This results in a wider width occupied by the tensile dielectric in the drift region at the edge of the drain 50, leading to a high 2DEG concentration below the edge of the drain 50, achieving the effect of not increasing or even reducing the overall on-resistance of the device.
[0099] Specifically, the 2DEG concentration is closely related to the polarization intensity. The compressive stress dielectric layer 61 counteracts the tensile stress on the barrier layer, thereby reducing piezoelectric polarization. Consequently, the 2DEG concentration below the compressive stress dielectric layer 61 decreases, increasing the device's threshold voltage. Simultaneously, due to the reduced 2DEG concentration, the depletion region formed in the device's off-state is larger, the electric field strength decreases, and the peak electric field near the drain 50 edge of the gate 32 also decreases. Since the device's current collapse is closely related to the electric field strength—the stronger the electric field, the more severe the current collapse—the compressive stress dielectric layer 61 can improve the device's current collapse. On the other hand, the tensile stress dielectric layer 62 can enhance piezoelectric polarization, thereby increasing the 2DEG concentration and reducing the channel resistance.
[0100] Therefore, in the fabrication method provided in this application, the width of the compressive stress dielectric layer 61 gradually decreases in the first direction, while the width of the tensile stress dielectric layer 62 gradually increases. Furthermore, in the second direction intersecting the first direction, the compressive stress dielectric layer 61 and the tensile stress dielectric layer 62 are connected. This results in a wider width occupied by the compressive stress dielectric in the drift region at the edge of the gate 32, leading to a lower 2DEG concentration below the edge of the gate 32. This effectively reduces the peak electric field, thereby solving the problem of excessively high electric field strength near the drain 50 edge of the gate 32, which can easily cause device breakdown. In the drift region at the edge of the drain 50, the tensile stress dielectric occupies a wider width, resulting in a higher 2DEG concentration below the edge of the drain 50. This achieves the effect of not increasing or even reducing the overall on-resistance of the device.
[0101] In one embodiment, referring to FIG12, before the first dielectric layer 60 is formed on the side of the epitaxial layer 20 opposite to the substrate 10 corresponding to the first region A1, a gate structure 30 is formed on the surface of the epitaxial layer 20 opposite to the substrate 10 corresponding to the gate structure region B1.
[0102] Of course, in other embodiments, not shown in the figures, a first dielectric layer 60 may be formed on the side of the epitaxial layer 20 opposite to the substrate 10 corresponding to the first region A1, and then a gate structure 30 may be formed on the surface of the epitaxial layer 20 opposite to the substrate 10 corresponding to the gate structure region B1. This is not a limitation.
[0103] The gate structure 30 includes a capping layer 31 and a gate 32. Taking a gallium nitride power device as an enhancement-mode device as an example, the capping layer 31 is also used to deplete the 2DEG under the gate structure 30 to form an enhancement-mode device. Specifically, the material of the capping layer 31 includes p-GaN, p-AlGaN, p-InGaN, or p-InAlGaN, etc., and is not limited here.
[0104] In this structure, the gate 32, source 40, and drain 50 are all made of conductive metal materials, used for electrical connection between the device and external circuits. Therefore, the source 40 and drain 50 can be formed in the same step as the gate 32 in the gate structure 30. For example, before or after the formation of the first dielectric layer 60 on the side of the epitaxial layer 20 facing away from the substrate 10 corresponding to the first region A1, the gate structure 30 is formed on the surface of the epitaxial layer 20 facing away from the substrate 10 corresponding to the gate structure region B1, and simultaneously the source 40 is formed on the surface of the epitaxial layer 20 facing away from the substrate 10 corresponding to the source region B2, and the drain 50 is formed on the surface of the epitaxial layer 20 facing away from the substrate 10 corresponding to the drain region B3. This simplifies the process.
[0105] In other embodiments, before the first dielectric layer 60 is formed on the side of the epitaxial layer 20 corresponding to the first region A1 that is away from the substrate 10, a gate structure 30 may be formed on the surface of the epitaxial layer 20 corresponding to the gate structure region B1 that is away from the substrate 10. After the first dielectric layer 60 is formed on the side of the epitaxial layer 20 corresponding to the first region A1 that is away from the substrate 10, a source 40 may be formed on the surface of the epitaxial layer 20 corresponding to the source region B2 that is away from the substrate 10, and a drain 50 may be formed on the surface of the epitaxial layer 20 corresponding to the drain region B3 that is away from the substrate 10.
[0106] Alternatively, before forming the first dielectric layer 60 on the side of the epitaxial layer 20 opposite to the substrate 10 corresponding to the first region A1, a source 40 is formed on the surface of the epitaxial layer 20 opposite to the substrate 10 corresponding to the source region B2, and a drain 50 is formed on the surface of the epitaxial layer 20 opposite to the substrate 10 corresponding to the drain region B3. After forming the first dielectric layer 60 on the side of the epitaxial layer 20 opposite to the substrate 10 corresponding to the first region A1, a gate structure 30 is formed on the surface of the epitaxial layer 20 opposite to the substrate 10 corresponding to the gate structure region B1. The specific choice can be made according to the actual device design and is not limited here.
[0107] The conductive metal systems of the gate 32, source 40, and drain 50 include, but are not limited to, Ti, Al, Ni, Au, or Ta, as well as alloys or compounds containing the above metal systems.
[0108] In one embodiment, the first region A1 includes a compressive stress dielectric layer region (not shown) and a tensile stress dielectric layer region (not shown); a first dielectric layer 60 is formed on the surface of the epitaxial layer 20 opposite to the substrate 10 corresponding to the first region A1, including:
[0109] Step S31: A tensile stress dielectric material layer 601 is grown on the entire side of the epitaxial layer 20 away from the substrate 10.
[0110] See Figure 13 for details, where the tensile stress medium material layer 601 can be formed using methods such as MOCVD / LPCVD / PECVD.
[0111] The tensile stress medium material layer 601 can be made of one or a combination of silicon nitride, silicon oxide, and silicon oxynitride.
[0112] The tensile stress of the tensile stress medium material layer 601 ranges from 0.1 to 2 GPa. For example, the stress value of the tensile stress medium material layer 601 can be 0.1 GPa, 0.5 GPa, 1 GPa, 1.5 GPa, or 2 GPa, etc., which are not limited here and can be selected according to the actual situation.
[0113] In one embodiment, the thickness of the tensile stress medium material layer 601 ranges from 10 to 1000 nm. For example, 10 nm, 100 nm, 300 nm, 500 nm, 700 nm, or 1000 nm, etc., are not limited here, and are set according to the actual situation.
[0114] Step S32: Pattern the tensile stress medium material layer 601 to remove the tensile stress medium material layer 601 in the corresponding compressive stress medium layer region, and retain the tensile stress medium material layer 601 in the corresponding tensile stress medium layer region to form a tensile stress medium layer 62 in the first region A1.
[0115] Referring specifically to Figure 14, at the end near the gate structure 30, each tensile dielectric layer 62 has the same width, which is the second width w2; the distance between two adjacent tensile dielectric layers 62 is equal to the first width w1. At the end near the drain 50, each tensile dielectric layer 62 has the same width, which is the fourth width w4; the distance between two adjacent tensile dielectric layers 62 is equal to the third width w3.
[0116] In one embodiment, after patterning etching of the tensile stress dielectric material layer 601, the tensile stress dielectric material layer 601 on the second region A2 and the gate structure region B1 is retained to form a second dielectric layer 70 on the second region A2 and a passivation layer 80 on the gate structure 30.
[0117] It is understandable that since the tensile stress medium layer 62, the second medium layer 70 and the passivation layer 80 are formed by etching the tensile stress medium material layer 601, the tensile stress medium layer 62, the second medium layer 70 and the passivation layer 80 have the same property parameters as the tensile stress medium material layer 601, and will not be elaborated here.
[0118] Specifically, the second dielectric layer 70 and the passivation layer 80 are tensile stress dielectric layers, which can increase the 2DEG concentration between the source and gate and reduce the on-resistance.
[0119] Step S33: Continue to grow a compressive stress dielectric material layer 602 on the side of the epitaxial layer 20 away from the substrate 10.
[0120] See Figure 15 for details, where the compressive stress medium material layer 602 can be formed using methods such as MOCVD / LPCVD / PECVD.
[0121] In some embodiments, the material of the compressive stress medium material layer 602 may be one or a combination of silicon nitride, silicon oxide, and silicon oxynitride.
[0122] In one embodiment, the stress value of the compressive stress medium material layer 602 ranges from -0.1 to -2 GPa (where "-" indicates compressive stress). For example, the stress value of the compressive stress medium material layer 602 may be -0.1 GPa, -0.5 GPa, -1 GPa, -1.5 GPa, or -2 GPa, etc., which are not limited here and can be selected according to the actual situation.
[0123] In one embodiment, the thickness of the compressive stress medium material layer 602 is the same as the thickness of the tensile stress medium material layer 601, and the thickness ranges from 10 to 1000 nm. For example, 10 nm, 100 nm, 300 nm, 500 nm, 700 nm, or 1000 nm, etc., are not limited here, and are set according to the actual situation.
[0124] Step S34: Pattern the compressive stress medium material layer 602 or perform chemical mechanical polishing to remove the compressive stress medium material layer 602 in the corresponding tensile stress medium layer region, while retaining the compressive stress medium material layer 602 in the corresponding compressive stress medium layer region, so as to form a compressive stress medium layer 61 in the first region A1.
[0125] Referring specifically to Figure 16, at the end near the gate structure 30, each compressive stress dielectric layer 61 has the same width, which is a first width w1; the distance between two adjacent compressive stress dielectric layers 61 is equal to a second width w2. At the end near the drain 50, each compressive stress dielectric layer 61 has the same width, which is a third width w3; the distance between two adjacent compressive stress dielectric layers 61 is equal to a fourth width w4.
[0126] In other embodiments, steps S33 and S34 may be located before steps S31 and S32, and this is not limited here. That is, a compressive stress dielectric material layer 602 may be grown and formed on the side of the epitaxial layer 20 away from the substrate 10 first, and then a compressive stress dielectric layer 61 may be patterned to form it. Then, a tensile stress dielectric material layer 602 may be grown and formed on the side of the epitaxial layer 20 away from the substrate 10 after the compressive stress dielectric layer 61 is formed, and then a tensile stress dielectric layer 62, a second dielectric layer 70, and a passivation layer 80 may be patterned to form it.
[0127] The above are merely embodiments of this application and do not limit the scope of this patent application. Any equivalent structural or procedural changes made using the content of this application's specification and drawings, or direct or indirect applications in other related technical fields, are similarly included within the scope of patent protection of this application.
Claims
1. A gallium nitride power device, characterized in that, include: Substrate; An epitaxial layer is disposed on one side of the substrate; A gate structure, a source, and a drain are disposed at intervals on the side of the epitaxial layer away from the substrate, and the source and the drain are located on opposite sides of the gate structure; wherein, the epitaxial layer located between the gate structure and the drain is defined as a first region of the epitaxial layer, and the epitaxial layer located between the gate structure and the source is defined as a second region of the epitaxial layer; A first dielectric layer is disposed on the side of the epitaxial layer away from the substrate and located in the first region, wherein the first dielectric layer includes a compressive stress dielectric layer and a tensile stress dielectric layer disposed in the same layer and extending along a first direction; In the first direction, the width of the compressive stress dielectric layer gradually decreases, and the width of the tensile stress dielectric layer gradually increases; in the second direction, the compressive stress dielectric layer is connected to the tensile stress dielectric layer, the first direction is the direction from the gate structure to the drain, and the second direction intersects with the first direction.
2. The gallium nitride power device according to claim 1, characterized in that, The stress value of the compressive stress medium layer ranges from -0.1 to -2 GPa; The stress value of the tensile stress medium layer ranges from 0.1 to 2 GPa.
3. The gallium nitride power device according to claim 1 or 2, characterized in that, The number of the compressive stress medium layer and the tensile stress medium layer are both multiple, and the multiple compressive stress medium layers and the multiple tensile stress medium layers are alternately arranged and connected along the second direction.
4. The gallium nitride power device according to claim 3, characterized in that, In the first direction, the width of the compressive stress medium layer decreases linearly, and the width of the tensile stress medium layer increases linearly. At one end near the gate structure, each of the compressive stress dielectric layers has the same width and is a first width, and each of the tensile stress dielectric layers has the same width and is a second width, wherein the first width is greater than the second width; the distance between two adjacent compressive stress dielectric layers is equal to the second width, and the distance between two adjacent tensile stress dielectric layers is equal to the first width; At the end near the drain electrode, each of the compressive stress dielectric layers has the same width and is a third width, and each of the tensile stress dielectric layers has the same width and is a fourth width, wherein the fourth width is greater than the third width; the distance between two adjacent compressive stress dielectric layers is equal to the fourth width; and the distance between two adjacent tensile stress dielectric layers is equal to the third width.
5. The gallium nitride power device according to claim 4, characterized in that, The first width and the fourth width are both in the range of 0.1um to 1mm; the second width and the third width are both in the range of 0 to 1mm.
6. The gallium nitride power device according to claim 4, characterized in that, The compressive stress medium layer has the same thickness as the tensile stress medium layer and has a first thickness, which ranges from 10 to 1000 nm.
7. The gallium nitride power device according to claim 1, characterized in that, The gallium nitride power device also includes: The second dielectric layer is disposed on the side of the epitaxial layer away from the substrate and located in the second region. The second dielectric layer is a tensile stress dielectric layer.
8. A method for fabricating a gallium nitride power device, characterized in that, include: Provide substrate; An epitaxial layer is formed on one side of the substrate; wherein the epitaxial layer defines a gate structure region, a source region, and a drain region, and the source region and the drain region are located on both sides of the gate structure region; and the epitaxial layer located between the gate structure region and the drain region is defined as a first region of the epitaxial layer, and the epitaxial layer located between the gate structure region and the source region is defined as a second region of the epitaxial layer; A first dielectric layer is formed on the side of the epitaxial layer opposite to the substrate corresponding to the first region. The first dielectric layer includes a compressive stress dielectric layer and a tensile stress dielectric layer disposed in the same layer and extending along a first direction. In the first direction, the width of the compressive stress dielectric layer gradually decreases, and the width of the tensile stress dielectric layer gradually increases. In a second direction, the compressive stress dielectric layer is in contact with the tensile stress dielectric layer. The first direction is the direction from the gate structure region to the drain region, and the second direction intersects with the first direction.
9. The preparation method according to claim 8, characterized in that, The first region includes a compressive stress medium layer region and a tensile stress medium layer region; The formation of a first dielectric layer on the surface of the epitaxial layer opposite to the substrate in the first region includes: A tensile stress dielectric material layer is grown on the entire side of the epitaxial layer away from the substrate; The tensile stress medium material layer is patterned and etched to remove the tensile stress medium material layer corresponding to the compressive stress medium layer region, while retaining the tensile stress medium material layer corresponding to the tensile stress medium layer region, so as to form the tensile stress medium layer in the first region; Continue growing a compressive stress dielectric material layer on the side of the epitaxial layer opposite to the substrate; The compressive stress medium material layer is patterned by etching or chemical mechanical polishing to remove the compressive stress medium material layer corresponding to the tensile stress medium layer region, while retaining the compressive stress medium material layer corresponding to the compressive stress medium layer region, so as to form the compressive stress medium layer in the first region.
10. The preparation method according to claim 8, characterized in that, Before forming the first dielectric layer on the side of the epitaxial layer opposite to the substrate corresponding to the first region, the method further includes: A gate structure is formed on the surface of the epitaxial layer opposite to the substrate, corresponding to the gate structure region; Alternatively, after forming the first dielectric layer on the side of the epitaxial layer opposite to the substrate corresponding to the first region, the method further includes: A gate structure is formed on the surface of the epitaxial layer opposite to the substrate, corresponding to the gate structure region.
Citation Information
Patent Citations
Semiconductor device and preparation method thereof
CN117855268A
Compound semiconductor device and method for fabricating the same
US20040144991A1
Compound semiconductor device, manufacturing method for compound semiconductor device, and amplifier
US20200251585A1
Semiconductor device
US20200365717A1