CMOS-based compact radio frequency transmit-receive change-over switch

Abstract

The present application discloses a CMOS-based compact radio frequency transmit-receive change-over switch. The compact radio frequency transmit-receive change-over switch comprises a voltage source V1 and a radio frequency transmit-receive change-over switch circuit. The radio frequency transmit-receive change-over switch circuit comprises an antenna port pin1, a transmitting path port pin2, and a receiving path port pin3. A first n-order lumped inductor-capacitor equivalent network is provided between the antenna port pin1 and the transmitting path port pin2; and a switch formed by an NMOS transistor NM1 is provided at the transmitting path port pin2 and connected in parallel to a GND. A second n-order lumped inductor-capacitor equivalent network is provided between the antenna port pin1 and the receiving path port pin3; and a switch formed by a PMOS transistor PM1 is provided at the receiving path port pin3 and connected in parallel to the GND. For the radio frequency transmit-receive change-over switch circuit, the ground level is GND, and the power supply voltage is VDD. In the present application, the chip area of the switch is decreased, the insertion loss caused by a radio frequency signal passing through the transmit-receive change-over switch is reduced, and the linearity of the switch in a transmitting mode is improved.

Description

A compact cmos-based radio frequency transceiver switch

[0001] Cross-reference to Related Applications

[0002] This application claims priority to the Chinese Patent Application No. 202410798365.7, filed on June 20, 2024, entitled “A Compact Cmos-Based Radio Frequency Transceiver Switch”, which is incorporated by reference herein in its entirety. TECHNICAL FIELD

[0003] The present application belongs to the field of CMOS radio frequency integrated circuit design, and particularly relates to a compact CMOS-based radio frequency transceiver switch. BACKGROUND

[0004] For a time division duplex radio frequency communication system, a transceiver switch is a key device for switching the receiving and transmitting functions of the radio frequency system. As shown in FIG. 1, the transceiver switch is a three-port device, which is composed of a transmitting branch switch and a receiving branch switch, wherein pin1 is an antenna port, pin2 is a transmitting path port, and pin3 is a receiving path port. In normal operation, the transmitting branch switch and the receiving branch switch have and only have one switch in the on state and the other switch in the off state. When the radio frequency communication system works in the transmitting mode, the transmitting branch switch is on and the receiving branch switch is off, so that the signal of the transmitting channel can be transmitted to the antenna end through the on transmitting branch switch, and the off receiving branch can prevent the signal from entering the receiving channel. When the radio frequency communication system works in the receiving mode, the receiving branch switch is on and the transmitting branch switch is off, so that the signal received by the antenna end can be transmitted to the receiving channel through the on receiving branch switch, and the off transmitting branch can prevent the signal from entering the transmitting channel.

[0005] In order to improve energy efficiency and reduce interference, the communication system usually needs to use a transceiver switch with low loss and high isolation. In the following analysis, the port impedance of pin1, pin2 and pin3 is assumed to be 50 ohms. Specifically, in the receiving mode: since the receiving path side pays more attention to low noise and suppression performance of the transmitting leakage signal, it is required to realize as low insertion loss as possible between pin1 and pin3, as high isolation as possible between pin1 and pin2, and good port standing wave performance of pin1 and pin3. In the transmitting mode: since the transmitting path side pays more attention to high linearity and high output power, it is required to realize as high linearity as possible and as low insertion loss as possible between pin1 and pin2, and good port standing wave performance of pin1 and pin2.

[0006] The radio frequency transceiver switch designed by using cheap CMOS process can improve system integration, reduce the size of communication system and reduce production cost. Based on CMOS process, there is a kind of transceiver switch with transmission line-parallel switch structure. As shown in Fig. 2, pin1 and pin2 are separated by 1 / 4λ transmission line T1, the characteristic impedance of transmission line T1 is 50 ohms, a switch composed of NMOS tube NM1 is added in parallel to GND at pin2, the drain of NM1 is connected with pin2, the source of NM1 is connected with the ground, and the gate of NM1 is controlled by the level of node A; pin1 and pin3 are separated by 1 / 4λ transmission line T2, the characteristic impedance of transmission line T2 is 50 ohms, a switch composed of NMOS tube NM2 is added in parallel to GND at pin3, the drain of NM2 is connected with pin3, the source of NM2 is connected with the ground, and the gate of NM2 is controlled by the level of node B; the ground level of the circuit=GND, and the supply voltage=VDD. In the following analysis, the port impedance of pin1, pin2 and pin3 are all assumed to be standard 50 ohms. In the receiving mode: the level of node A=VDD, NM1 works in deep linear region, the switch composed of NM1 is in the open state, and the on-resistance of NM1 is close to 0 ohm, and through the impedance transformation of 1 / 4λ transmission line T1, the impedance from pin1 to pin2 tends to infinity, so that the radio frequency signal is prevented from flowing from pin1 into transmission line T1; the level of node B=GND, NM2 works in the cutoff region, and the switch composed of NM2 is in the off state; the radio frequency signal can be transmitted from pin1 to pin3 through transmission line T2. In the transmitting mode: the level of node B=VDD, NM2 works in deep linear region, the switch composed of NM2 is in the open state, and the on-resistance of NM2 is close to 0 ohm, and through the impedance transformation of 1 / 4λ transmission line T2, the impedance from pin1 to pin3 theoretically tends to infinity, so that the radio frequency signal is prevented from flowing from pin1 into transmission line T2; the level of node A=GND, NM1 works in the cutoff region, and the switch composed of NM1 is in the off state; the radio frequency signal can be transmitted from pin2 to pin1 through transmission line T1.

[0007] The above scheme has the following problems:

[0008] 1) The 1 / 4λ transmission line based on CMOS process is long, resulting in high loss and large area occupation.

[0009] 2) In the transmitting mode, NMOS NM1 should always work in the cut-off region, but due to the existence of the parasitic capacitance between the drain of NM1 and the gate of NM1, when the transmitting signal increases to a certain extent, the transient voltage generated by the transmitting signal leakage to the gate will make the working region of NM1 change to the linear region, so that the on-resistance of NM1 changes from high resistance to low resistance; with the further increase of the transmitting signal, a larger and larger proportion of the transmitting signal at pin2 will be shunted to GND through NM1, resulting in the phenomenon of gain compression of the transmitting signal, which limits the high linearity performance of the transmitting path.

[0010] 3) In the transmitting mode, although the gate voltage threshold that can make NM1 work in the linear region can be increased by adding a static level switching port to the drain and source of NM1, thereby alleviating the gain compression phenomenon when the transmitting signal increases, and improving the linearity performance of the switch in the transmitting mode, in order to ensure the normal work of NM2, a DC blocking capacitor in series in the signal path needs to be added in the transmitting branch, which will bring additional loss and increase the chip area.

[0011] SUMMARY

[0012] The purpose of the present application is to overcome the problems of the prior art, and the present application discloses a compact CMOS-based radio frequency transceiving switch. The chip area of the switch is reduced, the insertion loss introduced when the radio frequency signal passes through the transceiving switch is reduced, and the linearity performance of the switch in the transmitting mode is improved.

[0013] The purpose of the present application is achieved by the following technical solutions:

[0014] A compact CMOS-based radio frequency transceiving switch, comprising: a voltage source V1 and a radio frequency transceiving switch circuit;

[0015] The negative electrode of the voltage source V1 is connected with the ground end GND, and the positive electrode of the voltage source V1 is connected with the power supply end VDD;

[0016] The radio frequency transceiving switch circuit comprises: an antenna port pin1, a transmitting path port pin2, and a receiving path port pin3,

[0017] A first n-stage lumped inductance-capacitance equivalent network is arranged between the antenna port pin1 and the transmitting path port pin2, and a switch-through capacitor C1 composed of an NMOS NM1 is connected in parallel to GND at the transmitting path port pin2, wherein the drain of the NMOS NM1 is connected with the transmitting path port pin2, the source of the NMOS NM1 is connected with the ground through the capacitor C1, and the gate of the NMOS NM1 is controlled by the level of node A;

[0018] A second n-stage lumped inductance-capacitance equivalent network is arranged between the antenna port pin1 and the receiving path port pin3, and a switch capacitor C6 is connected in parallel to GND through a PMOS transistor PM1 arranged at the receiving path port pin3, the drain of the PMOS transistor PM1 is connected to the receiving path port pin3, the drain of the PMOS transistor PM1 is connected to the ground through the capacitor C6, and the gate of the PMOS transistor PM1 is controlled by the level of node B.

[0019] The ground level of the radio frequency transceiver switching circuit is GND, and the supply voltage is the power supply end VDD.

[0020] According to a preferred embodiment, the source of the NMOS transistor NM1 and the drain of the PMOS transistor PM1 are respectively provided with static level switching ports D and E.

[0021] According to a preferred embodiment, the first n-stage lumped inductance-capacitance equivalent network and the second n-stage lumped inductance-capacitance equivalent network are 3-stage lumped inductance-capacitance equivalent networks. The unit inductance value of the 3-stage lumped inductance-capacitance equivalent network is L0, and the unit capacitance value is C0.

[0022] According to a preferred embodiment, the antenna port pin1 is connected to the center tap end of the inductor L2 and one end of the capacitor Cp2, and the inductance value of the inductor L2 is 2L0.

[0023] The other end of the capacitor Cp2 is connected to the center tap end of the inductor L2 and the antenna port pin1, and the capacitance value of the capacitor Cp2 is the parasitic capacitance from the port pad of the antenna port pin1 to the GND, which is the unit capacitance value C0.

[0024] According to a preferred embodiment, the first n-stage lumped inductance-capacitance equivalent network includes a capacitor Cp1, a capacitor C2, a capacitor C3, and an inductor L1, and a capacitor Cp2 and an inductor L2 shared with the second n-stage lumped inductance-capacitance equivalent network.

[0025] The other end of the capacitor C3 is connected to the inductor L2 and the inductor L1.

[0026] The other end of the capacitor C2 is connected to the center tap end of the inductor L1.

[0027] The other end of the capacitor Cp1 is connected to the drain of the NMOS transistor NM1 and the transmitting path port pin2.

[0028] According to a preferred embodiment, the capacitance of the capacitor Cp1 is C0 / 2, which is the sum of the parasitic capacitance from the port pad of the transmitting path port pin2 to GND and the parasitic capacitance from the drain of the NMOS transistor NM1 to GND;

[0029] The inductance of the inductor L1 is 2L0; the capacitance of the capacitor C2 is C0 / 2; and the capacitance of the capacitor C3 is C0 / 2.

[0030] According to a preferred embodiment, the second n-order lumped inductance-capacitance equivalent network comprises a capacitor Cp3, a capacitor C4, a capacitor C5, and an inductor L3, and the capacitor Cp2 and the inductor L2 shared by the first n-order lumped inductance-capacitance equivalent network;

[0031] The one end of the capacitor C4 is connected to GND, and the other end is connected to the inductor L2 and the inductor L3.

[0032] The one end of the capacitor C5 is connected to GND, and the other end is connected to the center tap end of the inductor L3.

[0033] The one end of the capacitor Cp3 is connected to GND, and the other end is connected to the source of the PMOS transistor PM1 and the receiving path port pin3.

[0034] According to a preferred embodiment, the capacitance of the capacitor Cp3 is C0 / 2, which is the sum of the parasitic capacitance from the port pad of the receiving path port pin3 to GND and the parasitic capacitance from the source of the PMOS transistor PM1 to GND.

[0035] The inductance of the inductor L3 is 2L0; the capacitance of the capacitor C4 is C0 / 2; and the capacitance of the capacitor C5 is C0 / 2.

[0036] According to a preferred embodiment, the radio frequency transceiving switch circuit further comprises a capacitor C1, a capacitor C6, a resistor R1, a resistor R2, and a resistor R3.

[0037] The one end of the capacitor C1 is connected to GND, and the other end is connected to the source of the NMOS transistor NM1 and R2, for blocking the direct current path between the source of the NMOS transistor NM1 and GND, and for providing an alternating current path of radio frequency signals between the source of the NMOS transistor NM1 and GND.

[0038] The one end of the capacitor C6 is connected to GND, and the other end is connected to the drain of the PMOS transistor PM1 and R3, for blocking the direct current path between the drain of the PMOS transistor PM1 and GND, and for providing an alternating current path of radio frequency signals between the drain of the PMOS transistor PM1 and GND.

[0039] The resistance R1 is connected with the inductor L1, the inductor L2 and the capacitor C3 at one end, and is connected with the node C at the other end, for preventing the radio frequency signal from shunting to the C point, and for providing the direct current level to the drain of the NMOS tube NM1 and the source of the PMOS tube PM1 through the C point;

[0040] The resistance R2 is connected with the node D at one end, and is connected with the source of the NMOS tube NM1 and the blocking capacitor C1 at the other end, for preventing the radio frequency signal from shunting to the D point from the drain of the NMOS tube NM1, and for providing the direct current level to the source of the NMOS tube NM1 through the D point;

[0041] The resistance R3 is connected with the node E at one end, and is connected with the drain of the PMOS tube PM1 and the blocking capacitor C6 at the other end, for preventing the radio frequency signal from shunting to the E point from the drain of the PMOS tube PM1, and for providing the direct current level to the drain of the PMOS tube PM1 through the E point.

[0042] The foregoing main scheme and each further selected scheme of the present application can be freely combined to form multiple schemes, all of which are the schemes that can be adopted and claimed by the present application. Those skilled in the art can understand that there are multiple combinations according to the prior art and common knowledge after understanding the schemes of the present application, all of which are the technical schemes claimed by the present application, and thus are not listed exhaustively.

[0043] The beneficial effects of the present application: the present application improves the transmit-receive switching switch structure based on the transmission line-parallel switch type structure of CMOS process, reduces the chip area of the switch, reduces the insertion loss introduced when the radio frequency signal passes through the transmit-receive switching switch, and improves the linearity performance of the switch in the transmit mode.

[0044] Specifically, the present application uses an n-order lumped inductance-capacitance equivalent network composed of a tapped inductor and a capacitor to replace the 1 / 4λ transmission line to reduce the insertion loss, and the tapped inductor can further save the chip area compared with the ordinary inductor; the NMOS tube NM2 of the receiving branch is replaced by the PMOS tube PM1, and the drain and the source of the NM1 and the PM1 are provided with a static level switching port, in the transmit mode, the gate voltage threshold that can make the working area of the NM1 change to the linear region is improved, so as to alleviate the gain compression phenomenon when the transmit signal increases, and improve the linearity performance of the switch in the transmit mode, and after the switching level, the PM1 can also work normally, avoiding the extra loss and occupying extra chip area caused by the series blocking capacitor introduced in the signal path. BRIEF DESCRIPTION OF DRAWINGS

[0045] Fig. 1 is a schematic diagram of the position of the transmit-receive switching switch in the radio frequency communication system;

[0046] Fig. 2 is a schematic diagram of the transmit-receive switching switch structure using the transmission line-parallel switch type structure;

[0047] Fig. 3 is a schematic diagram showing the relationship between a ¼ λ transmission line and an inductance-capacitance equivalent network of an n-stage band-tap;

[0048] Fig. 4 is a schematic diagram showing the structure of a CMOS-based compact RF transceiver switch according to the present application. DETAILED DESCRIPTION

[0049] The advantages and effects of the present application can be easily understood by those skilled in the art from the description of the embodiments. The present application can also be implemented or applied in other different embodiments, and the details in the description can be modified or changed based on different views and applications without departing from the spirit of the present application. It should be noted that the following embodiments and features in the embodiments can be combined with each other without conflict.

[0050] It should be noted that similar reference numerals and letters refer to similar items throughout the accompanying drawings, and once an item is defined in one drawing, it need not be further defined and explained in subsequent drawings.

[0051] In the description of the present application, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", and the like indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, or the orientation or positional relationship in which the product of the present application is usually placed, and are only for the convenience of describing the present application and simplifying the description, and therefore cannot be understood as indicating or implying that the indicated device or element must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as limiting the present application. In addition, the terms "first", "second", "third", and the like are only used to distinguish the description and cannot be understood as indicating or implying relative importance.

[0052] In addition, the terms "horizontal", "vertical", "overhang", and the like do not mean that the components must be absolutely horizontal or overhanging, but can be slightly inclined. For example, "horizontal" only means that it is more horizontal relative to "vertical", and does not mean that the structure must be completely horizontal, but can be slightly inclined.

[0053] In the description of the present application, it should also be noted that unless otherwise explicitly specified and limited, the terms "provided", "mounted", "connected", "linked" should be understood broadly, for example, can be fixedly connected, can be detachably connected, or integrally connected; can be mechanically connected, or electrically connected; can be directly connected, or indirectly connected through an intermediate medium; can be internal communication of two elements. For those skilled in the art, the specific meaning of the above terms in the present application can be understood according to the specific circumstances.

[0054] In addition, it is pointed out in the present application that, if specific structures, connection relationships, position relationships, power source relationships, etc. are not particularly written in the present application, the structures, connection relationships, position relationships, power source relationships, etc. involved in the present application are all known by those skilled in the art on the basis of the prior art without creative labor.

[0055] Embodiment 1

[0056] As shown in FIG. 3, a 3-order lumped inductance-capacitance equivalent network composed of a tapped inductor and a capacitor is used to replace the 1 / 4λ transmission line in the transmitting branch switch circuit and the receiving branch switch circuit; in actual application, a 5-order or other odd high-order lumped inductance-capacitance equivalent network can also be used. The relationship between the unit inductance value L0 and the unit capacitance value C0 of the 1 / 4λ transmission line and the n-order lumped inductance-capacitance equivalent network is determined by the following relationship:

[0057] where TD is the transmission delay of the 1 / 4λ transmission line, f0 is the characteristic frequency of the 1 / 4λ transmission line, and Z0 is the characteristic impedance of the 1 / 4λ transmission line.

[0058] where TD is the transmission delay of the 1 / 4λ transmission line, f0 is the characteristic frequency of the 1 / 4λ transmission line, and Z0 is the characteristic impedance of the 1 / 4λ transmission line.

[0059] As shown in FIG. 4, the present application discloses a compact radio frequency transceiving switch based on CMOS, comprising: a voltage source, a radio frequency transceiving switch circuit. The negative electrode of the voltage source V1 is connected with the ground end GND, and the positive electrode of the voltage source V1 is connected with the power supply end VDD.

[0060] The radio frequency transceiving switch circuit comprises:

[0061] A receiving channel signal port pin3 connected with the source electrode of the PM1 and one end of the L3.

[0062] The source electrode is connected with the pin3, the gate electrode is connected with the node B, and the drain electrode is connected with the PMOS tube PM1 having one end connected with the R3 and one end of the DC blocking capacitor C6.

[0063] The resistance R3 having one end connected with the node E and the other end connected with the drain electrode of the PM1 and the DC blocking capacitor C6, which functions to prevent the radio frequency signal from being shunted from the drain electrode of the PM1 to the node E, and simultaneously provides a DC level for the drain electrode of the PM1 through the node E.

[0064] The DC blocking capacitor C6 having one end connected with the GND and the other end connected with the drain electrode of the PM1 and the R3, which functions to block the DC path between the drain electrode of the PM1 and the GND, and simultaneously provides an AC path for the radio frequency signal between the drain electrode of the PM1 and the GND.

[0065] Capacitor Cp3 connected to GND at one end and to pin3 and PM1 source at the other end, the capacitor Cp3 is not an independent device, but the sum of the parasitic capacitance from pin3 port pad to GND and the parasitic capacitance from PM1 source to GND, under the premise of the size of the port pad is determined, by reasonably selecting the size of PMOS PM1, so that the Cp3 capacitor value = 1 / 2 * unit capacitance value Co.

[0066] Tapped inductor L3 connected to pin3 and PM1 source at one end, and to one end of C4 and one end of L2 at the other end, and to one end of C5 at the center tap, the L3 inductance value = 2 * unit inductance value Lo.

[0067] Capacitor C4 connected to GND at one end and to L2 and inductor L3 at the other end, the capacitor C4 capacitance value = 1 / 2 * unit capacitance value Co.

[0068] Capacitor C5 connected to GND at one end and to the center tap of L3 at the other end, the capacitor C5 capacitance value = 1 / 2 * unit capacitance value Co.

[0069] Inductor L2 connected to one end of L3 and one end of C4 at one end, and to L1, resistor R1 and C3 at the other end, and to pin1 at the center tap, the L2 inductance value = 2 * unit inductance value Lo.

[0070] Capacitor Cp2 connected to GND at one end and to the center tap of L2 and pin1 at the other end, the capacitor Cp2 is not an independent device, but the parasitic capacitance from pin1 port pad to GND, the Cp2 capacitance value = unit capacitance value Co.

[0071] Emission channel signal port pin2 connected to NM1 drain and one end of L1.

[0072] NMOS NM1 with drain connected to pin2 and one end of L1, gate connected to node A, and source connected to R2 and DC blocking capacitor C1.

[0073] Resistor R2 connected to node D at one end and to NM1 source and DC blocking capacitor C1 at the other end, which prevents RF signals from NM1 drain from shunting to D point, and at the same time provides DC level to the source of NM1 through D point.

[0074] DC blocking capacitor C1 connected to GND at one end and to NM1 source and resistor R2 at the other end, which blocks the DC path between NM1 source and GND, while providing an AC path for RF signals between NM1 source and GND.

[0075] The one end of the capacitor Cp1 is connected with the GND, and the other end is connected with the drain of the NM1. The capacitor Cp1 is not an independent device, but the sum of the parasitic capacitor from the pin2 port pad to the GND and the parasitic capacitor from the drain of the NM1 to the GND. Under the premise that the size of the port pad is determined, by reasonably selecting the size of the NMOS tube NM1, the Cp1 capacitor value = 1 / 2*unit capacitance value Co.

[0076] The one end of the tapped inductor L1 is connected with the pin2 and the drain of the NM1, and the other end is connected with the resistor R1, the inductor L2 and the capacitor C3. The center tap end is connected with the C2. The L1 inductor value = 2*unit inductance value Lo.

[0077] The one end of the capacitor C2 is connected with the GND, and the other end is connected with the center tap end of the L1. The C2 capacitor value = 1 / 2*unit capacitance value Co.

[0078] The one end of the capacitor C3 is connected with the inductor L1, the inductor L2 and the resistor R1, and the other end is connected with the node C. The C3 capacitor value = 1 / 2*unit capacitance value Co.

[0079] The one end of the resistor R1 is connected with the inductor L1, the inductor L2 and the capacitor C3, and the other end is connected with the node C. The function of the resistor R1 is to prevent the RF signal from being shunted to the C point, and at the same time to provide a DC level to the drain of the M1 through the C point.

[0080] The antenna signal port pin1 is connected with the center tap end of the L2.

[0081] Based on the above circuit structure, the working mechanism of the RF transceiver switching switch of the application is as follows:

[0082] In the following analysis, the blocking capacitor C1 and C6 have a large value, which is equivalent to a short circuit for RF; the port impedance of pin1, pin2 and pin3 is 50 ohms by default.

[0083] In the receiving mode: the level of node A = VDD, the level of node C = GND, the level of node D = GND, NM1 works in the deep linear region, and the switch formed thereby is in the open state. The on-resistance of M1 is close to 0 ohms. Through the impedance transformation of the three-order lumped inductance-capacitance network equivalent to 1 / 4λ transmission line composed of Cp1, L1, C2, C3, L2 and Cp2, the impedance from pin1 to pin2 tends to infinity, thereby preventing the RF signal from flowing from pin1 to pin2; the level of node B = VDD, the level of node E = GND, PM1 works in the cutoff region, and the switch formed thereby is in the off state; the RF signal can be transmitted from pin1 to pin3 through the equivalent 1 / 4λ transmission line composed of Cp2, L2, C4, L3, C5 and Cp3.

[0084] In the transmitting mode: the level of node B=GND, the level of node C=VDD, the level of node E=VDD, PM1 works in the deep linear region, the switch composed of PM1 is in the on state, the on resistance of PM1 is close to 0 ohm, and the impedance transformation of the third-order lumped inductance-capacitance network composed of Cp2, L2, C4, L3, C5 and Cp3 equivalent to 1 / 4λ transmission line makes the impedance from pin1 to pin3 theoretically tend to infinity, thereby preventing the radio frequency signal from flowing from pin1 to pin3; the level of node A=GND, the level of node D=VDD, NM1 works in the cut-off region, and the switch composed of NM1 is in the off state; the radio frequency signal can be transmitted from pin2 to pin1 through the equivalent 1 / 4λ transmission line composed of Cp1, L1, C2, C3, L2 and Cp2.

[0085] The n-order lumped inductance-capacitance equivalent network composed of tapped inductors and capacitors is used to replace the 1 / 4λ transmission line to reduce the insertion loss, and the tapped inductor can further save the chip area compared with the ordinary inductor;

[0086] The NMOS tube NM2 of the receiving branch is replaced by the PMOS tube PM1, and the drain and source of NM1 and PM1 are provided with static level switching ports, in the transmitting mode, the gate voltage threshold that can make the working region of NM1 change to the linear region is improved, thereby relieving the gain compression phenomenon when the transmitting signal increases, and the linearity performance of the switch in the transmitting mode is improved, and the PM1 can also work normally after the level is switched, thereby avoiding the extra loss caused by the series DC blocking capacitor introduced in the signal path and occupying the extra chip area.

[0087] The above only describes the preferred embodiments of the present application and is not used to limit the present application, any modification, equivalent replacement and improvement within the scope of the present application shall be included in the protection scope of the present application.

Claims

1. A compact radio frequency transceiving switch based on CMOS, the compact radio frequency transceiving switch comprising: A voltage source V1 and a radio frequency transceiver switching circuit; The negative electrode of the voltage source V1 is connected with the ground terminal GND, and the positive electrode of the voltage source V1 is connected with the power supply terminal VDD. The radio frequency transceiver switching circuit comprises an antenna port pin1, a transmitting path port pin2 and a receiving path port pin3. A first n-stage lumped inductance-capacitance equivalent network is arranged between the antenna port pin1 and the transmitting path port pin2, and a switch-through capacitor C1 is connected to GND in parallel through an NMOS transistor NM1 arranged at the transmitting path port pin2, wherein the drain electrode of the NMOS transistor NM1 is connected with the transmitting path port pin2, the source electrode of the NMOS transistor NM1 is connected with the ground through the capacitor C1, and the gate electrode of the NMOS transistor NM1 is controlled by the level of node A. A second n-stage lumped inductance-capacitance equivalent network is arranged between the antenna port pin1 and the receiving path port pin3, and a switch-through capacitor C1 is connected to GND in parallel through a PMOS transistor PM1 arranged at the receiving path port pin3, wherein the drain electrode of the PMOS transistor PM1 is connected with the receiving path port pin3, the source electrode of the PMOS transistor PM1 is connected with the ground through the capacitor C1, and the gate electrode of the PMOS transistor PM1 is controlled by the level of node B. The ground level of the radio frequency transceiver switching circuit is GND, and the supply voltage is the power supply terminal VDD.

2. The compact radio frequency transmit receive switch of claim 1, wherein, The source electrode of the NMOS transistor NM1 and the drain electrode of the PMOS transistor PM1 are respectively provided with static level switching ports D and E.

3. The compact radio frequency transmit receive switch of claim 1, wherein, The first n-stage lumped inductance-capacitance equivalent network and the second n-stage lumped inductance-capacitance equivalent network are 3-stage lumped inductance-capacitance equivalent networks. The unit inductance value of the 3-stage lumped inductance-capacitance equivalent network is L0, and the unit capacitance value is C0.

4. The compact radio frequency transmit receive switch of claim 3, wherein, The antenna port pin1 is connected with the center tap end of the inductor L2 and one end of the capacitor Cp2, and the inductance value of the inductor L2 is 2L0. One end of the capacitor Cp2 is connected with the ground, and the other end is connected with the center tap end of the inductor L2 and the antenna port pin1, and the capacitance value of the capacitor Cp2 is the parasitic capacitance from the port pad of the antenna port pin1 to the ground, which is the unit capacitance value C0.

5. The compact radio frequency transmit receive switch of claim 4, wherein, The first n-stage lumped inductance-capacitance equivalent network comprises a capacitor Cp1, a capacitor C2, a capacitor C3 and an inductor L1, and a capacitor Cp2 and an inductor L2 which are shared by the second n-stage lumped inductance-capacitance equivalent network. One end of the capacitor C3 is connected with the ground, and the other end is connected with the inductor L2 and the inductor L1. One end of the capacitor C2 is connected with the ground, and the other end is connected with the center tap end of the inductor L1. One end of the capacitor Cp1 is connected with the ground, and the other end is connected with the drain electrode of the NMOS transistor NM1 and the transmitting path port pin2.

6. The compact radio frequency transmit receive switch of claim 5, wherein, The capacitance value of the capacitor Cp1 is the sum of the parasitic capacitance from the port pad of the transmitting path port pin2 to the ground and the parasitic capacitance from the drain electrode of the NMOS transistor NM1 to the ground, which is C0 / 2. The inductance value of the inductor L1 is 2L0, the capacitance value of the capacitor C2 is C0 / 2, and the capacitance value of the capacitor C3 is C0 / 2.

7. The compact RF transmit-receive switch of claim 4, wherein, The second n-order lumped inductance-capacitance equivalent network comprises a capacitor C4, a capacitor C5 and an inductor L3; One end of the capacitor C4 is connected with the GND, and the other end is connected with the inductor L2 and the inductor L3; One end of the capacitor C5 is connected with the GND, and the other end is connected with the center tap end of the inductor L3; One end of the capacitor Cp3 is connected with the GND, and the other end is connected with the source of the PMOS tube PM1 The receiving path port pin3 is connected.

8. The compact radio frequency transmit receive switch of claim 7 wherein, The capacitance value of the capacitor Cp3 is the sum of the parasitic capacitance from the port pad of the receiving path port pin3 to the GND and the parasitic capacitance from the source of the PMOS tube PM1 to the GND, which is C0 / 2; The inductance value of the inductor L3 is 2L0; the capacitance value of the capacitor C4 is C0 / 2; and the capacitance value of the capacitor C5 is C0 / 2.

9. The compact RF transmit-receive switch of claim 1, wherein, The radio frequency transceiving switch circuit further comprises a capacitor C1, a capacitor C6, a resistor R1, a resistor R2 and a resistor R3; One end of the capacitor C1 is connected with the GND, and the other end is connected with the source of the NMOS tube NM1 and the R2, for blocking the direct current path between the source of the NMOS tube NM1 and the GND, and simultaneously providing an alternating current path of the radio frequency signal between the source of the NMOS tube NM1 and the GND; One end of the capacitor C6 is connected with the GND, and the other end is connected with the drain of the PMOS tube PM1 and the R3, for blocking the direct current path between the drain of the PMOS tube PM1 and the GND, and simultaneously providing an alternating current path of the radio frequency signal between the drain of the PMOS tube PM1 and the GND; One end of the resistor R1 is connected with the inductor L1, the inductor L2 and the capacitor C3, and the other end is connected with the node C, for preventing the radio frequency signal from being shunted to the C point, and simultaneously providing a direct current level to the drain of the NMOS tube NM1 and the source of the PMOS tube PM1 through the C point; One end of the resistor R2 is connected with the node D, and the other end is connected with the source of the NMOS tube NM1 and the blocking capacitor C1, for preventing the radio frequency signal from being shunted from the drain of the NMOS tube NM1 to the D point, and simultaneously providing a direct current level to the source of the NMOS tube NM1 through the D point; One end of the resistor R3 is connected with the node E, and the other end is connected with the drain of the PMOS tube PM1 and the blocking capacitor C6, for preventing the radio frequency signal from being shunted from the drain of the PMOS tube PM1 to the E point, and simultaneously providing a direct current level to the drain of the PMOS tube PM1 through the E point.

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