Display substrate and display apparatus

Abstract

A display substrate and a display apparatus. The display substrate comprises a base substrate (11), a driving circuit layer (12), a pixel definition layer (PDL), an isolation column layer and a light-emitting material layer (14), wherein the driving circuit layer (12) is arranged on the base substrate (11) and comprises a plurality of conductive patterns; the PDL is arranged on the side of the driving circuit layer (12) away from the base substrate (11) and comprises a plurality of sub-pixel openings (P0); the isolation column layer is arranged on the side of the PDL away from the base substrate (11) and comprises at least one conductive isolation column (16); and the light-emitting material layer (14) is at least arranged in the plurality of sub-pixel openings (P0) and disconnected at the at least one conductive isolation column (16), and the at least one conductive isolation column (16) is electrically connected to at least one of the plurality of conductive patterns by means of a via hole. The conductive isolation column (16) of the display substrate may transmit electrical signals, such that the circuit layout of the display substrate is simpler, and higher-resolution display can be achieved.

Description

Display substrate and display device

[0001] This application claims priority to Chinese Patent Application No. 202410813715.2, filed on June 21, 2024, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0002] Embodiments of this disclosure relate to a display substrate and a display device. Background Technology

[0003] Organic light-emitting diode (OLED) display devices have a series of advantages such as self-illumination, high contrast, high definition, wide viewing angle, low power consumption, fast response speed, and low manufacturing cost. As a result, they have become one of the key development directions for next-generation display devices and have therefore received increasing attention.

[0004] Summary of the Invention

[0005] At least one embodiment of this disclosure provides a display substrate, which includes a substrate, a driving circuit layer, a pixel defining layer, an isolation pillar layer, and a light-emitting material layer. The driving circuit layer is disposed on the substrate and includes a plurality of conductive patterns. The pixel defining layer is disposed on the side of the driving circuit layer away from the substrate and includes a plurality of sub-pixel openings. The isolation pillar layer is disposed on the side of the pixel defining layer away from the substrate and includes at least one conductive isolation pillar. The light-emitting material layer is disposed at least in the plurality of sub-pixel openings and is disconnected at the at least one conductive isolation pillar. The at least one conductive isolation pillar is electrically connected to at least one of the plurality of conductive patterns through a via.

[0006] For example, in a display substrate provided in at least one embodiment of this disclosure, the light-emitting material layer includes a first light-emitting pattern and a second light-emitting pattern, the first light-emitting pattern and the second light-emitting pattern are arranged adjacent to each other and emit different colors, and at least one conductive isolation pillar is disposed between the first light-emitting pattern and the second light-emitting pattern to interrupt the first light-emitting pattern and the second light-emitting pattern.

[0007] For example, in a display substrate provided in at least one embodiment of this disclosure, there are multiple first light-emitting patterns arranged in a row along a first direction, multiple second light-emitting patterns arranged in a row along the first direction, and at least one conductive isolation pillar extending between the multiple first light-emitting patterns and the multiple second light-emitting patterns along the first direction.

[0008] For example, in at least one embodiment of the display substrate provided in this disclosure, the light-emitting material layer further includes a third light-emitting pattern, the third light-emitting pattern having a different light-emitting color from the first light-emitting pattern and the second light-emitting pattern, the first light-emitting pattern and the second light-emitting pattern being adjacent in a first direction, the first light-emitting pattern and the third light-emitting pattern being adjacent in a second direction, the second direction being different from the first direction, and the planar shape of the at least one conductive isolation pillar being mesh-like, so as to be respectively disposed between the first light-emitting pattern and the second light-emitting pattern and between the first light-emitting pattern and the third light-emitting pattern.

[0009] For example, in a display substrate provided in at least one embodiment of this disclosure, the driving circuit layer includes a transistor, a storage capacitor, and multiple signal lines. The transistor includes a gate and a source / drain electrode, the storage capacitor includes a first capacitor electrode and a second capacitor electrode, and the multiple conductive patterns include the gate, the source / drain electrode, the first capacitor electrode, the second capacitor electrode, and the multiple signal lines.

[0010] For example, in a display substrate provided in at least one embodiment of this disclosure, the driving circuit layer has a first conductive layer, a second conductive layer and a third conductive layer stacked sequentially in a direction away from the substrate. The gate and the first capacitor electrode are disposed in the first conductive layer, the second capacitor electrode is disposed in the second conductive layer, the source and drain electrodes are disposed in the third conductive layer, and the plurality of signal lines are respectively disposed in at least one of the first conductive layer, the second conductive layer and the third conductive layer.

[0011] For example, in a display substrate provided in at least one embodiment of this disclosure, the driving circuit layer has a first conductive layer, a second conductive layer, a third conductive layer and a fourth conductive layer stacked sequentially in a direction away from the substrate. The gate and the first capacitor electrode are disposed in the first conductive layer, the second capacitor electrode is disposed in the second conductive layer, the source and drain electrodes are disposed in the third conductive layer, and the plurality of signal lines are respectively disposed in at least one of the first conductive layer, the second conductive layer, the third conductive layer and the fourth conductive layer.

[0012] For example, in a display substrate provided in at least one embodiment of this disclosure, the plurality of conductive patterns include a reset voltage terminal, and the at least one conductive isolation pillar is electrically connected to the reset voltage terminal through a via to serve as a reset voltage line.

[0013] For example, at least one embodiment of the present disclosure provides a display substrate that further includes: an electrode material layer disposed on the side of the light-emitting material layer away from the substrate, and at least disposed in the plurality of sub-pixel openings, wherein the electrode material layer is disconnected at at least one conductive isolation pillar and is in contact with the at least one conductive isolation pillar.

[0014] For example, in a display substrate provided in at least one embodiment of this disclosure, the plurality of conductive patterns include a first power terminal, and the at least one conductive isolation pillar is electrically connected to the first power terminal through a via to act as a first power line.

[0015] For example, at least one embodiment of the present disclosure provides a display substrate that further includes: an electrode material layer disposed on the side of the light-emitting material layer away from the substrate, and at least disposed in the plurality of sub-pixel openings, wherein the portions of the light-emitting material layer and the electrode material layer located in the plurality of sub-pixel openings are insulated from the at least one conductive isolation pillar.

[0016] For example, in a display substrate provided in at least one embodiment of this disclosure, the at least one conductive isolation pillar is electrically connected to at least one of the plurality of signal lines through a via, so as to reduce the resistance of the at least one signal line.

[0017] For example, in a display substrate provided in at least one embodiment of the present disclosure, each of the at least one conductive isolation pillar includes a first isolation pattern and a second isolation pattern stacked sequentially in a direction away from the substrate, wherein the orthographic projection of the first isolation pattern on the substrate is located within the orthographic projection of the second isolation pattern on the substrate.

[0018] For example, in a display substrate provided in at least one embodiment of this disclosure, each of the at least one conductive isolation pillar further includes a third isolation pattern disposed on the side of the first isolation pattern near the substrate, wherein the orthographic projection of the first isolation pattern on the substrate is located within the orthographic projection of the third isolation pattern on the substrate.

[0019] For example, in a display substrate provided in at least one embodiment of this disclosure, the longitudinal section of each of the at least one conductive isolation pillar is V-shaped.

[0020] At least one embodiment of this disclosure also provides a display device, which includes the display substrate provided in the embodiments of this disclosure. Attached Figure Description

[0021] To more clearly illustrate the technical solutions of the embodiments of this disclosure, the accompanying drawings of the embodiments will be briefly described below. Obviously, the drawings described below only relate to some embodiments of this disclosure and are not intended to limit this disclosure.

[0022] Figure 1 is a cross-sectional schematic diagram of a display substrate provided in at least one embodiment of the present disclosure;

[0023] Figure 2 is a circuit diagram of a pixel driving circuit of a display substrate provided in at least one embodiment of the present disclosure;

[0024] Figure 3 is a timing diagram of the pixel driving circuit of a display substrate provided in at least one embodiment of the present disclosure;

[0025] Figure 4 is a cross-sectional schematic diagram of a display substrate provided in at least one embodiment of the present disclosure;

[0026] Figure 5 is a cross-sectional schematic diagram of another display substrate provided in at least one embodiment of the present disclosure;

[0027] Figure 6 is a schematic diagram of the planar arrangement of the light-emitting pattern and the conductive isolation pillars in a display substrate provided in at least one embodiment of the present disclosure;

[0028] Figure 7 is a schematic diagram of the planar arrangement of the light-emitting pattern and the conductive isolation pillars in another display substrate provided in at least one embodiment of the present disclosure;

[0029] Figure 8 is a cross-sectional schematic diagram of another display substrate provided in at least one embodiment of the present disclosure;

[0030] Figure 9 is a cross-sectional schematic diagram of another display substrate provided in at least one embodiment of the present disclosure;

[0031] Figure 10 is a cross-sectional schematic diagram of a conductive isolation pillar in a display substrate provided in at least one embodiment of the present disclosure;

[0032] Figure 11 is a schematic diagram of the signal line arrangement of a display substrate;

[0033] Figure 12 is a schematic diagram of the signal line arrangement in a display substrate provided in at least one embodiment of the present disclosure; and

[0034] Figure 13 is a schematic diagram of the signal line arrangement in another display substrate provided in at least one embodiment of the present disclosure. Detailed Implementation

[0035] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the described embodiments of this disclosure without creative effort are within the scope of protection of this disclosure.

[0036] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as “comprising” or “including” mean that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. Terms such as “connected” or “linked” are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. Terms such as “upper,” “lower,” “left,” and “right” are used only to indicate relative positional relationships, and these relative positional relationships may change accordingly when the absolute position of the described objects changes.

[0037] For example, FIG1 shows a cross-sectional schematic diagram of a display substrate provided in at least one embodiment of the present disclosure. As shown in FIG1, the display substrate has a plurality of sub-pixels for display. Two adjacent sub-pixels are shown in FIG1, namely the first sub-pixel SP1 and the second sub-pixel SP2 as examples. The display substrate also includes functional layers such as a substrate 11, a driving circuit layer 12, a light-emitting device layer M, an isolation pillar layer, and an encapsulation layer EN.

[0038] For example, as shown in FIG1, the driving circuit layer 12 is disposed on the substrate 11 and includes pixel driving circuits for multiple sub-pixels. Each pixel driving circuit includes multiple transistors and storage capacitors, etc. (described in detail later). The light-emitting device layer M is disposed on the side of the driving circuit layer 12 away from the substrate 11 and includes light-emitting devices for multiple sub-pixels. For example, each sub-pixel includes a pixel driving circuit located in the driving circuit layer 12 and a light-emitting device located in the light-emitting device layer M. The pixel driving circuit is used to drive the light-emitting device to emit light.

[0039] For example, as shown in Figure 1, each light-emitting device includes a first electrode 13, a light-emitting material layer 14, and a second electrode 15. Under the voltage drive of the first electrode 13 and the second electrode 15, the light-emitting material layer 14 can emit light and achieve the corresponding grayscale. For example, the first electrode 13 can be an anode, electrically connected to the pixel driving circuit through a via, for transmitting a high-level voltage, and the second electrode 15 can be a cathode, for transmitting a low-level voltage.

[0040] For example, to achieve full-color display, multiple sub-pixels can emit light of different colors, such as red, green, and blue. In Figure 1, the first sub-pixel SP1 and the second sub-pixel SP2 are used to emit light of different colors. Therefore, the light-emitting material layers 14 of the first sub-pixel SP1 and the second sub-pixel SP2 are different to make them emit different colors. To isolate the light-emitting material layers 14 of different colors in adjacent sub-pixels, an isolation pillar layer can be provided on the display substrate. The isolation pillar layer includes at least one isolation pillar 16. The isolation pillar 16 is disposed at least between sub-pixels that emit different colors. The isolation pillar 16 has a concave sidewall structure so that the formed light-emitting material layers 14 can be sufficiently broken at the isolation pillar 16, thereby isolating the light-emitting material layers 14 of different colors in adjacent sub-pixels.

[0041] For example, the encapsulation layer EN is placed above the light-emitting device to encapsulate the light-emitting device layer M.

[0042] For example, the second electrode 15 and the encapsulation layer EN are also disconnected at the isolation post 16, and the second electrode 15 is in contact with the isolation post 16. In some embodiments, the isolation post 16 is a conductive isolation post, for example, formed of a conductive material. In this case, the isolation post 16 electrically connects the second electrodes 15 of adjacent sub-pixels, so that the isolation post 16 transmits the electrical signal of the second electrode 15 and makes the electrical signals transmitted by the second electrodes 15 of multiple sub-pixels the same.

[0043] For example, as shown in Figure 1, an insulating layer 17 can be provided on the isolation post 16 to shield the electrical signals transmitted in the isolation post 16. For example, it can prevent the electrical signals transmitted in the isolation post 16 from affecting other electrical signals transmitted above it, such as touch signals. For example, the insulating layer 17 can be made of inorganic materials such as silicon oxide, silicon nitride, or silicon oxynitride.

[0044] For example, Figure 2 is a schematic diagram of the circuit structure of a pixel driving circuit provided in at least one embodiment of the present disclosure. As shown in Figure 2, the pixel driving circuit includes: a first transistor T1, a second transistor T2, a driving transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, and a storage capacitor C. In this case, the pixel driving circuit is formed as a 7T1C structure.

[0045] For example, as shown in Figure 2, the first transistor T1 can be the first reset transistor T1, the second transistor T2 can be the threshold compensation transistor T2, the third transistor T3 can be the drive transistor T3, the fourth transistor T4 can be the data writing transistor T4, the fifth transistor T5 can be the second light-emitting control transistor T5, the sixth transistor T6 can be the first light-emitting control transistor T6, and the seventh transistor T7 can be the second reset control transistor T7.

[0046] For example, the first terminal of the first transistor T1 is connected to node N1, which is electrically connected to the gate of the driving transistor T3. The second terminal of the first transistor T1 is connected to the first initial signal terminal Vinit1, which is electrically connected to the first reset voltage line to receive the reset voltage. The gate of the first transistor T1 is connected to the first reset signal terminal Re1, which is electrically connected to the reset control signal line to receive the reset control signal.

[0047] The first terminal of the second transistor T2, which is also the threshold compensation transistor, is connected to node N1, that is, electrically connected to the gate of the driving transistor T3. The second terminal of the second transistor T2 is connected to the second terminal of the driving transistor T3. The gate of the second transistor T2 is connected to the first gate drive signal terminal G1 to receive the compensation control signal.

[0048] The gate of the driving transistor T3 is connected to node N1, so as to be connected to the first capacitor electrode of the storage capacitor C, the first electrode of the first transistor T1, and the first electrode of the second transistor T2.

[0049] The first terminal of the fourth transistor T4, which is also the data write transistor, is connected to the data signal terminal Data to receive the data signal. The second terminal of the fourth transistor T4 is connected to the first terminal of the drive transistor T3. The gate of the fourth transistor T4 is connected to the second gate drive signal terminal G2 to receive the scan signal.

[0050] The first terminal of the fifth transistor T5, which is also the second light-emitting control transistor, is connected to the first power supply terminal VDD to receive the first power supply signal. The second terminal of the fifth transistor T5 is connected to the first terminal of the driving transistor T3. The gate of the fifth transistor T5 is connected to the light-emitting control signal terminal EM to receive the light-emitting control signal.

[0051] The first terminal of the sixth transistor T6, which is also the first light-emitting control transistor, is connected to the second terminal of the driving transistor T3. The second terminal of the sixth transistor T6 is connected to the first terminal of the seventh transistor T7. The gate of the sixth transistor T6 is connected to the light-emitting control signal terminal EM to receive the light-emitting control signal.

[0052] The second terminal of the seventh transistor T7 is connected to the second initial signal terminal Vinit2, which is electrically connected to the second reset voltage signal line to receive the reset voltage. The gate of the seventh transistor T7 is connected to the second reset signal terminal Re2, which is electrically connected to the reset control signal line to receive the reset control signal.

[0053] The first capacitor electrode of the storage capacitor C is connected to node N1 and electrically connected to the gate of the driving transistor T3. The second capacitor electrode of the storage capacitor C is connected to the first power supply terminal VDD, that is, connected to the first power supply signal line.

[0054] The pixel driving circuit can be connected to a light-emitting device, which can be an organic light-emitting diode (OLED). The pixel driving circuit is used to drive the light-emitting device to emit light. The light-emitting device can be connected between the second electrode of the sixth transistor T6 and the second power supply terminal VSS. For example, the anode of the light-emitting device is connected to the second electrode of the sixth transistor T6, and the cathode of the light-emitting device is connected to the second power supply terminal VSS, that is, connected to the second power supply signal line.

[0055] For example, the first power signal line mentioned above refers to the signal line for the output voltage signal VDD, which can be connected to a voltage source to output a constant voltage signal, such as a high-level voltage signal. The second power signal line mentioned above refers to the signal line for the output voltage signal VSS, which can be connected to a voltage source to output a constant voltage signal, such as a low-level voltage signal.

[0056] For example, the scan signal and the compensation control signal can be the same; that is, the gate of the data write transistor T4 and the gate of the threshold compensation transistor T2 can be electrically connected to the same signal line to receive the same signal, thereby reducing the number of signal lines. Alternatively, the gate of the data write transistor T4 and the gate of the threshold compensation transistor T2 can be electrically connected to different signal lines; that is, the gate of the data write transistor T4 is electrically connected to the second scan signal line (second gate line), and the gate of the threshold compensation transistor T2 is electrically connected to the first scan signal line (first gate line). The signals transmitted by the first scan signal line and the second scan signal line can be the same or different, thus allowing the gates of the data write transistor T4 and the threshold compensation transistor T2 to be controlled separately, thereby increasing the flexibility of controlling the pixel driving circuit.

[0057] For example, the first light-emitting control transistor T6 and the second light-emitting control transistor T5 can receive the same light-emitting control signal. That is, the gates of the first light-emitting control transistor T6 and the second light-emitting control transistor T5 can be electrically connected to the same signal line to receive the same signal, reducing the number of signal lines. Alternatively, the gates of the first light-emitting control transistor T6 and the second light-emitting control transistor T5 can be electrically connected to different light-emitting control signal lines. In this case, the signals transmitted by the different light-emitting control signal lines can be the same or different.

[0058] For example, the reset control signals input to the second reset transistor T7 and the first reset transistor T1 can be the same; that is, the gates of the second reset transistor T7 and the first reset transistor T1 can be electrically connected to the same signal line to receive the same signal, reducing the number of signal lines. Alternatively, the gates of the second reset transistor T7 and the first reset transistor T1 can be electrically connected to different reset control signal lines, in which case the signals on the different reset control signal lines can be the same or different.

[0059] For example, the first transistor T1 and the second transistor T2 can be N-type transistors. For example, the first transistor T1 and the second transistor T2 can be N-type metal-oxide transistors. N-type metal-oxide transistors have smaller leakage current, thus avoiding leakage current through the N1 node during the light-emitting stage. Meanwhile, the driving transistors T3, T4, T5, T6, and T7 can be P-type transistors. For example, the driving transistors T3, T4, T5, T6, and T7 can be P-type low-temperature polysilicon transistors. P-type low-temperature polysilicon transistors have higher carrier mobility, which is beneficial for achieving display panels with high resolution, high response speed, high pixel density, and high aperture ratio. The first initial signal terminal Vinit1 and the second initial signal terminal Vinit2 can output the same or different voltage signals depending on the actual situation.

[0060] For example, the first transistor T1 to the seventh transistor T7 can be various types of transistors such as thin-film transistors and field-effect transistors, and the embodiments of this disclosure do not specifically limit them. For example, the first and second electrodes of each transistor are the source and drain electrodes of the transistor, and are structurally indistinguishable, and therefore can be interchanged.

[0061] For example, Figure 3 is a timing diagram of the driving method of the pixel driving circuit in Figure 2. For example, in Figure 3, G1 represents the timing of the first gate driving signal terminal G1, G2 represents the timing of the second gate driving signal terminal G2, Re1 represents the timing of the first reset signal terminal Re1, Re2 represents the timing of the second reset signal terminal Re2, EM represents the timing of the light emission control signal terminal EM, and Data represents the timing of the data signal terminal Data.

[0062] For example, the driving method of the pixel driving circuit may include a first reset stage t1, a compensation stage t2, a second reset stage t3, and a light emission stage t4.

[0063] In the first reset phase t1: the first reset signal terminal Re1 outputs a high-level signal, the first transistor T1 is turned on, and the first initial signal terminal Vinit1 inputs an initial signal to node N1.

[0064] During the compensation phase t2: the first gate drive signal terminal G1 outputs a high-level signal, the second gate drive signal terminal G2 outputs a low-level signal, the fourth transistor T4 and the second transistor T2 are turned on, and at the same time the data signal terminal Data outputs a drive signal to write a voltage Vdata+Vth (i.e., the sum of voltages Vdata and Vth) to node N1, where Vdata is the voltage of the drive signal and Vth is the threshold voltage of the drive transistor T3.

[0065] In the second reset phase t3: the second reset signal terminal Re2 outputs a low-level signal, the seventh transistor T7 is turned on, and the second initial signal terminal Vinit2 inputs an initial signal to the second terminal of the sixth transistor T6.

[0066] During the light-emitting stage t4: the light-emitting control signal terminal EM outputs a low-level signal, the sixth transistor T6 and the fifth transistor T5 are turned on, and the driving transistor T3 emits light under the action of the voltage Vdata+Vth stored in the storage capacitor C.

[0067] It should be noted that, in the embodiments of this disclosure, each pixel driving circuit can be a 7T1C (i.e., seven transistors and one capacitor) structure as shown in Figure 2, or it can be a structure including other numbers of transistors, such as a 7T2C structure, a 6T1C structure, a 6T2C structure, an 8T1C structure, or a 9T2C structure. The embodiments of this disclosure do not limit this.

[0068] The layout of the aforementioned pixel driving circuit requires a certain amount of space. Referring to Figure 1, in order to ensure the stability of signal transmission and the high sub-pixel density to achieve high resolution, it is necessary to rationally design the layout pattern of the pixel driving circuit on the substrate.

[0069] At least one embodiment of this disclosure provides a display substrate and a display device. The display substrate includes a substrate, a driving circuit layer, a pixel defining layer, an isolation pillar layer, and a light-emitting material layer. The driving circuit layer is disposed on the substrate and includes multiple conductive patterns. The pixel defining layer is disposed on the side of the driving circuit layer away from the substrate and includes multiple sub-pixel openings. The isolation pillar layer is disposed on the side of the pixel defining layer away from the substrate and includes at least one conductive isolation pillar. The light-emitting material layer is disposed in at least one of the multiple sub-pixel openings and is disconnected at at least one conductive isolation pillar. The at least one conductive isolation pillar is electrically connected to at least one of the multiple conductive patterns through a via.

[0070] In the display substrate provided in this embodiment, at least one conductive isolation post is electrically connected to at least one of a plurality of conductive patterns through a via, thereby enabling the transmission of electrical signals of the conductive patterns connected thereto, replacing signal lines connected to the conductive patterns to simplify circuit layout. Alternatively, the at least one conductive isolation post can reduce the resistance of the conductive patterns connected thereto to improve the accuracy of signal transmission.

[0071] The display substrate and display device provided in the embodiments of this disclosure are described below through several specific examples.

[0072] This disclosure provides a display substrate in at least one embodiment. FIG4 shows a cross-sectional schematic diagram of the display substrate. As shown in FIG4, the display substrate has a plurality of sub-pixels. Two adjacent sub-pixels are shown in the figure, namely the first sub-pixel SP1 and the second sub-pixel SP2 as examples. The display substrate also includes a substrate 11, a driving circuit layer 12, a pixel delimiting layer PDL, an isolation pillar layer, and a light-emitting device layer M, etc.

[0073] As shown in Figure 4, a driving circuit layer 12 is disposed on a substrate 11 and includes multiple conductive patterns (e.g., reference numerals 101-103, which will be described in detail later). A pixel defining layer PDL is disposed on the side of the driving circuit layer 12 away from the substrate 11 and includes multiple sub-pixel openings P0 for forming multiple sub-pixels. An isolation pillar layer is disposed on the side of the pixel defining layer PDL away from the substrate 11 and includes at least one conductive isolation pillar 16.

[0074] For example, as shown in FIG4, the light-emitting device layer M may include a plurality of first electrodes 13, a light-emitting material layer 14 disposed on the side of the plurality of first electrodes 13 away from the substrate 11, and an electrode material layer 15 disposed on the side of the light-emitting material layer 14 away from the substrate 11. The light-emitting material layer 14 is disposed in at least a plurality of sub-pixel openings P0. For example, in some embodiments, the light-emitting material layer 14 further extends outside the sub-pixel openings P0 and is disconnected at at least one conductive isolation pillar 16.

[0075] As shown in Figure 4, at least one conductive isolation post 16 is electrically connected to at least one of a plurality of conductive patterns (shown as signal line 101 in the figure) through vias (e.g., V1 and V2, described in detail later). Thus, the conductive isolation post 16 can transmit electrical signals of the conductive pattern to which it is connected, replacing the signal line connected to the conductive pattern to simplify circuit layout; or, the conductive isolation post can reduce the resistance of the conductive pattern (e.g., signal line 101) to which it is connected, thereby improving the accuracy of signal transmission.

[0076] For example, in some embodiments, as shown in FIG4, the driving circuit layer 12 includes a transistor 102, a storage capacitor 103, and multiple signal lines 101. The transistor 103 includes an active layer 1021, a gate 1022, and source / drain electrodes 1023 / 1024. The storage capacitor 103 includes a first capacitor electrode 1031 and a second capacitor electrode 1032. The multiple signal lines 101 may include various signal lines mentioned in FIG2, such as scan lines, data lines, reset voltage lines, power lines, etc. For example, the multiple conductive patterns mentioned above include the gate 1022, source / drain electrodes 1023 / 1024, first capacitor electrode 1031, second capacitor electrode 1032, and multiple signal lines 101 of each transistor. In this case, the conductive isolation pillar 16 connected by vias can be one or more of the various patterns mentioned above, as long as signal crosstalk does not occur.

[0077] For example, as shown in FIG4, the driving circuit layer 12 has a first conductive layer M1, a second conductive layer M2, and a third conductive layer M3 stacked sequentially in a direction away from the substrate 11. A gate electrode 1022 and a first capacitor electrode 1031 are disposed in the first conductive layer M1, a second capacitor electrode 1032 is disposed in the second conductive layer M2, and source / drain electrodes 1023 / 1024 are disposed in the third conductive layer M3. Multiple signal lines 101 are respectively disposed in at least one of the first conductive layer M1, the second conductive layer M2, and the third conductive layer M3. In the cross-sectional view shown in FIG4, the signal line 101 shown is located in the third conductive layer M3. In other cross-sections, different signal lines 101 may be located in different conductive layers, which will not be elaborated here.

[0078] For example, in some embodiments, the driving circuit layer 12 may include more conductive layers. For instance, FIG5 shows a cross-sectional schematic diagram of another display substrate provided in at least one embodiment of the present disclosure. As shown in FIG5, the driving circuit layer 12 has a first conductive layer M1, a second conductive layer M2, a third conductive layer M3, and a fourth conductive layer M4 stacked sequentially in a direction away from the substrate 11. A gate 1022 and a first capacitor electrode 1031 are disposed in the first conductive layer M1, a second capacitor electrode 1032 is disposed in the second conductive layer M2, and source / drain electrodes 1023 / 1024 are disposed in the third conductive layer M3. The fourth conductive layer M4 may include, for example, a connection electrode CL connecting the first electrode 13 and the pixel driving circuit, or may also include other signal lines. Multiple signal lines 101 are respectively disposed in at least one of the first conductive layer M1, the second conductive layer M2, the third conductive layer M3, and the fourth conductive layer M4.

[0079] For example, as shown in Figures 4 and 5, the display substrate may further include a barrier layer B1 and a buffer layer B2 disposed on the substrate 11. The barrier layer B1 and the buffer layer B2 can prevent impurities in the substrate 11 from entering the multiple functional layers on the display substrate, thereby providing protection. For example, the barrier layer B1 and the buffer layer B2 may be one or more inorganic insulating materials such as silicon oxide, silicon nitride, or silicon oxynitride.

[0080] For example, as shown in Figures 4 and 5, the display substrate may further include a first gate insulating layer GI1 disposed on the side of the active layer 1021 away from the substrate 11, a second gate insulating layer GI2 disposed on the side of the gate electrode 1022 and the first capacitor electrode 1031 away from the substrate 11, and an interlayer insulating layer IDL disposed on the side of the second capacitor electrode 1032 away from the substrate 11. For example, the first gate insulating layer GI1, the second gate insulating layer GI2, and the interlayer insulating layer IDL may be one or more inorganic insulating materials such as silicon oxide, silicon nitride, or silicon oxynitride.

[0081] For example, as shown in Figures 4 and 5, the display substrate may further include a planarization layer PLN disposed on the side of the source / drain electrodes 1023 / 1024 away from the substrate 11. The planarization layer PLN can planarize the pixel driving circuit, thereby forming a relatively flat surface to facilitate the placement of the light-emitting device layer M. For example, as shown in Figure 5, if the display substrate also includes a fourth conductive layer M4 or more conductive layers, the display substrate may further include an additional planarization layer PLN1 to provide a flat surface. For example, each planarization layer may be made of an organic insulating material such as polyimide or resin.

[0082] For example, as shown in Figures 4 and 5, the encapsulation layer EN can be an inorganic encapsulation layer, which can be one or more inorganic insulating materials such as silicon oxide, silicon nitride, or silicon oxynitride. Further encapsulation layers can be formed on the encapsulation layer EN, such as organic and inorganic encapsulation layers (not shown), to form a composite encapsulation layer, wherein the organic encapsulation layer can be one or more organic insulating materials such as resin or polyimide.

[0083] For example, the pixel defining layer (PDL) can be one or more of inorganic insulating materials such as silicon oxide, silicon nitride, or silicon oxynitride; or, in other embodiments, the pixel defining layer (PDL) can also be one or more of organic insulating materials such as resin or polyimide.

[0084] For example, in some embodiments, as shown in Figures 4 and 5, the light-emitting material layer 14 includes a first light-emitting pattern 141 and a second light-emitting pattern 142, the first light-emitting pattern 141 and the second light-emitting pattern 142 are arranged adjacent to each other and emit different colors, and at least one conductive isolation post 16 is disposed between the first light-emitting pattern 141 and the second light-emitting pattern 142 to interrupt the first light-emitting pattern 141 and the second light-emitting pattern 142 to prevent color crosstalk.

[0085] For example, in some embodiments, as shown in FIG6, there are multiple first light-emitting patterns 141, which are arranged in a row along the first direction R1; there are multiple second light-emitting patterns 142, which are arranged in a row along the first direction R1; and at least one conductive isolation post 16 extends along the first direction R1 between the multiple first light-emitting patterns 141 and the multiple second light-emitting patterns 142 to completely interrupt the multiple first light-emitting patterns 141 and the multiple second light-emitting patterns 142.

[0086] For example, in some embodiments, as shown in FIG6, the light-emitting material layer 14 may further include a third light-emitting pattern 143. The number of third light-emitting patterns 143 is multiple, and these multiple third light-emitting patterns 143 are arranged in a row along a first direction R1. At least one conductive isolation pillar 16 includes multiple isolation pillars 16, which extend along the first direction R1 between multiple first light-emitting patterns 141 and multiple second light-emitting patterns 142, between multiple second light-emitting patterns 142 and multiple third light-emitting patterns 143, and / or between multiple first light-emitting patterns 141 and multiple third light-emitting patterns 143, respectively. Thus, the multiple isolation pillars 16 can completely interrupt the multiple first light-emitting patterns 141, multiple second light-emitting patterns 142, and multiple third light-emitting patterns 143.

[0087] For example, in some other embodiments, the light-emitting patterns can be arranged in different ways. Figure 7 shows another arrangement of the light-emitting patterns. As shown in Figure 7, the light-emitting material layer 14 includes a first light-emitting pattern 141, a second light-emitting pattern 142, and a third light-emitting pattern 143. The light-emitting colors of the first light-emitting pattern 141, the second light-emitting pattern 142, and the third light-emitting pattern 143 are different from each other. The first light-emitting pattern 141 and the second light-emitting pattern 142 are adjacent in the first direction R1. The first light-emitting pattern 141 and the third light-emitting pattern 143 are adjacent in the second direction R2, which is different from the first direction R1. In this case, at least one conductive isolation pillar 16 has a mesh-like planar shape and is respectively disposed between the first light-emitting pattern 141 and the second light-emitting pattern 142 and between the first light-emitting pattern 141 and the third light-emitting pattern 143. For example, it is also disposed between the second light-emitting pattern 142 and the third light-emitting pattern 143 to interrupt any two adjacent ones of the first light-emitting pattern 141, the second light-emitting pattern 142, and the third light-emitting pattern 143.

[0088] For example, in some embodiments, multiple conductive patterns include a reset voltage terminal (or initial signal terminal, such as Vinit1 and Vinit2 in FIG2), and at least one conductive isolation pillar 16 is electrically connected to the reset voltage terminal through a via to act as a reset voltage line. For example, the reset voltage terminal can be the second electrode (source / drain electrode) of the first transistor T1 and the second electrode (source / drain electrode) of the seventh transistor T7 in FIG2. For example, FIG8 shows a partial cross-sectional schematic diagram of the display substrate in this case. As shown in FIG8, the transistor 102 shown can be the first transistor T1 or the seventh transistor T7 in FIG2, and the source / drain electrode 1024 can be the second electrode of the first transistor T1 or the second electrode of the seventh transistor T7. In this case, the isolation pillar 16 can be electrically connected to the second electrode of the first transistor T1 or the second electrode of the seventh transistor T7, which serves as the reset voltage terminal, through via V1 in the pixel defining layer PDL and via V2 in the planarization layer PLN / PLN1 to act as a reset voltage line.

[0089] For example, Figure 8 shows a display substrate including a first conductive layer M1 to a fourth conductive layer M4. In other embodiments, the display substrate may include more or fewer conductive layers, such as the case shown in Figure 4. The embodiments disclosed herein do not specifically limit this.

[0090] Therefore, the above design can save the original reset voltage lines in the display substrate, thereby reducing the arrangement of reset voltage lines in the pixel driving circuit layer. This saves the original space for the arrangement of reset voltage lines, making the arrangement of conductive patterns in the pixel driving circuit layer simpler, which is beneficial to further improve the resolution of the display substrate or improve the light transmittance of the display substrate.

[0091] For example, in a conventional display substrate, the reset voltage line is a signal line periodically arranged along the row direction of the sub-pixels. It can be located in the second conductive layer M2 or other suitable conductive layer of the display substrate, with one reset voltage line corresponding to each row of sub-pixels. The design provided by the embodiments of this disclosure saves the arrangement space of one reset voltage line per row of sub-pixels, thereby significantly reducing the number of signal lines in the pixel circuit layer 102 and simplifying the arrangement of conductive patterns in the pixel driving circuit layer.

[0092] For example, Figure 11 shows a schematic diagram of the arrangement of multiple signal lines corresponding to a sub-pixel in a conventional display substrate. As shown in Figure 11, the multiple signal lines include at least a reset voltage line Vint extending along the row direction, scan lines G1 / G2, light emission control lines EM, reset signal lines Re1 / Re2, and a first part of the first power line VDD1; the multiple signal lines also include a data line Data extending along the column direction and a second part of the first power line VDD2. The first part of the first power line VDD1 and the second part of the first voltage line VDD2 can be electrically connected through vias to form a mesh of first power lines.

[0093] By utilizing the above design of the embodiments of this disclosure, and using the isolation pillar 16 as the reset voltage line Vint, the arrangement of the reset voltage line Vint can be reduced. As shown in FIG12, the reset voltage line Vint arranged along the row direction is omitted. This significantly reduces the number of signal lines in the pixel circuit layer 102, making the arrangement of conductive patterns in the pixel driving circuit layer simpler.

[0094] For example, in the above embodiment, as shown in FIG8, the display substrate further includes an electrode material layer 15. The electrode material layer 15 is disposed on the side of the light-emitting material layer 14 away from the substrate 11, and is disposed in at least one of the plurality of sub-pixel openings P0. The electrode material layer 15 is disconnected at at least one conductive isolation pillar 16 and is in contact with at least one conductive isolation pillar 16. At this time, the electrode material layer 15 is electrically connected to the conductive isolation pillar 16, so that the electrode material layer 15, the conductive isolation pillar 16 and the reset voltage terminal transmit the same electrical signal, such as a low-level signal, such as a -3V low-level signal.

[0095] For example, in some embodiments, the first electrode 13 is the anode, the electrode material layer 15 is the cathode, and the electrode material layers 15 of different sub-pixels are electrically connected through conductive isolation pillars 16, thereby transmitting the same low-level signal.

[0096] For example, in other embodiments, multiple conductive patterns include a first power terminal, and at least one conductive isolation pillar 16 is electrically connected to the first power terminal through a via to act as a first power line. For example, the first power terminal can be the first electrode of the fifth transistor T5 in FIG2 and the second capacitor electrode of the storage capacitor C, used to transmit the first power signal VDD. For example, FIG9 shows a partial cross-sectional schematic diagram of the display substrate in this case. As shown in FIG9, the transistor 102 shown can be the fifth transistor T5 in FIG2, and the source / drain electrode 1024 can be the first electrode of the fifth transistor T5. In this case, the isolation pillar 16 can be electrically connected to the first electrode of the fifth transistor T5, which serves as the first power terminal, through vias V1 in the pixel defining layer PDL and vias V2 in the planarization layer PLN / PLN1 to act as a first power line. For example, the first power line is used to transmit a high-level voltage of about 4V to 5V.

[0097] For example, the first electrode of the fifth transistor T5 and the second capacitor electrode 1032 of the storage capacitor C can be electrically connected at other locations, not shown in the figure.

[0098] Similarly, Figure 9 shows a display substrate including a first conductive layer M1 to a fourth conductive layer M4. In other embodiments, the display substrate may include more or fewer conductive layers, such as the case shown in Figure 4. The embodiments of this disclosure do not specifically limit this.

[0099] For example, as shown in FIG9, the display substrate further includes an electrode material layer 15, which is disposed on the side of the light-emitting material layer 14 away from the substrate 11, and is disposed at least in a plurality of sub-pixel openings P0. The portions of the light-emitting material layer 14 and the electrode material layer 15 located in the plurality of sub-pixel openings P0 are insulated from at least one conductive isolation pillar 16.

[0100] For example, in some embodiments, as shown in FIG9, the portion A of the light-emitting material layer 14 and the electrode material layer 15 located between the sub-pixel opening P0 and the conductive isolation pillar 16 is etched away to isolate the portion of the light-emitting material layer 14 and the electrode material layer 15 located at the sub-pixel opening P0 from the portion of the light-emitting material layer 14 and the electrode material layer 15 in contact with the conductive isolation pillar 16. This insulates the portions of the light-emitting material layer 14 and the electrode material layer 15 located at multiple sub-pixel openings P0 from at least one conductive isolation pillar 16. This avoids crosstalk between the electrical signals transmitted by the electrode material layer 15 and the electrical signals transmitted by the conductive isolation pillar 16.

[0101] Therefore, the above design can save at least some of the original first power lines in the display substrate, thereby reducing the arrangement of the first power lines in the pixel driving circuit layer. This can save the original arrangement space of at least some of the first power lines, making the arrangement of conductive patterns in the pixel driving circuit layer simpler, which is conducive to further improving the resolution of the display substrate or improving the light transmittance of the display substrate.

[0102] For example, in a conventional display substrate, the first power line is a signal line periodically arranged along the column direction of the sub-pixel or along both the row and column directions. It can be located in the third conductive layer M2 and / or the fourth conductive layer of the display substrate, with each column of sub-pixels corresponding to at least one first power line. Through the design provided by the embodiments of this disclosure, at least one vertically arranged first power line can be saved for each column of sub-pixels, thereby significantly reducing the number of signal lines in the pixel circuit layer 102 and simplifying the arrangement of conductive patterns in the pixel driving circuit layer.

[0103] For example, as shown in Figure 13, with the above design, the isolation pillar 16 can be used as the second part VDD2 of the first power supply trace in Figure 11. Compared with Figure 11, the second part VDD2 of the first power supply trace arranged along the column direction can be reduced. This significantly reduces the number of signal lines in the pixel circuit layer 102, making the arrangement of conductive patterns in the pixel driving circuit layer simpler.

[0104] For example, in some embodiments, as shown in Figures 4 and 5, at least one conductive isolation pillar 16 is electrically connected to at least one of the multiple signal lines 101 through vias (e.g., via V1 in the pixel defining layer PDL and via V2 in the planarization layer PLN / PLN1) to reduce the resistance of at least one signal line. In this case, it is equivalent to connecting the conductive isolation pillar 16 in parallel to the signal line 101, thereby reducing the resistance of the signal line 101 and improving the accuracy of the electrical signals transmitted by the signal line 101, thus improving the display effect of the display substrate. For example, the multiple signal lines 101 may include various signal lines mentioned in Figure 2, such as individual scan lines, data lines, reset voltage lines, power lines, etc.

[0105] For example, in some embodiments, the display substrate may further include a gate-on-array (GAO) circuit disposed on the driving circuit layer 12. This GAO circuit also includes structures such as transistors and storage capacitors, as well as multiple connection traces, such as signal output lines. In embodiments of this disclosure, the multiple conductive patterns that can be connected to the isolation pillar 16 also include various conductive patterns of the gate-on-array circuit described above, which will not be repeated here.

[0106] For example, Figure 10 shows a cross-sectional schematic diagram of a conductive isolation pillar in a display substrate provided in at least one embodiment of the present disclosure. As shown in Figure 10, in some embodiments, the conductive isolation pillar 16 includes a first isolation pattern 16A and a second isolation pattern 16B stacked sequentially along a direction away from the substrate 11. The orthographic projection of the first isolation pattern 16A on the substrate 11 lies within the orthographic projection of the second isolation pattern 16B on the substrate 11. Thus, the conductive isolation pillar 16 forms a structure that is larger at the top and smaller at the bottom, so as to effectively isolate the light-emitting material layer 14.

[0107] For example, in some embodiments, the conductive isolation pillar 16 further includes a third isolation pattern 16C disposed on the side of the first isolation pattern 16A near the substrate 11, wherein the orthographic projection of the first isolation pattern 16A on the substrate 11 lies within the orthographic projection of the third isolation pattern 16C on the substrate 11. Thus, the conductive isolation pillar 16 forms a structure with concave sidewalls to effectively isolate the light-emitting material layer 14.

[0108] For example, in some embodiments, the orthographic projection of the second isolation pattern 16B on the substrate 11 lies within the orthographic projection of the third isolation pattern 16C on the substrate 11. Thus, the third isolation pattern 16C has a larger area, which can improve the bonding strength of the conductive isolation pillars 16 on the substrate 11.

[0109] For example, the first isolation pattern 16A, the second isolation pattern 16B, and the third isolation pattern 16C can adopt a three-layer metal structure such as titanium / aluminum / titanium or molybdenum / aluminum / molybdenum. During the preparation process, the three-layer metal structure can be formed in sequence by deposition, sputtering, or other methods to form three metal layers. Then, the three metal layers are etched as a whole. During etching, the etching rate of the material in the middle is lower than that of the materials on the top and bottom sides, so as to form a concave structure on the sidewall of the conductive isolation pillar 16, thereby achieving a sufficient isolation effect.

[0110] For example, as shown in Figure 10, the longitudinal section of the conductive isolation pillar 16 is generally V-shaped. For example, the bottom of the V-shape near the substrate 11 has a flat portion to ensure the connection stability between the conductive isolation pillar 16 and the conductive pattern it is connected to, but overall, the longitudinal section of the conductive isolation pillar 16 is still V-shaped.

[0111] For example, in some embodiments, as shown in FIG4, the display substrate may further include an insulating layer 17 disposed on the side of the conductive isolation pillar 16 away from the substrate 11. The insulating layer 17 can shield the electrical signals transmitted in the conductive isolation pillar 16, for example, preventing the electrical signals transmitted in the isolation pillar 16 from affecting other electrical signals transmitted above it, such as touch signals. For example, the insulating layer 17 may be made of inorganic materials such as silicon oxide, silicon nitride, or silicon oxynitride.

[0112] For example, in some embodiments, as shown in FIG4, a light-emitting material layer 14 and an electrode material layer 15 are also formed on the side of the conductive isolation pillar 16 away from the substrate 11. For example, in some embodiments, an encapsulation layer EN is also formed on the side of the conductive isolation pillar 16 away from the substrate 11. In this case, the light-emitting material layer 14, the electrode material layer 15, and the encapsulation layer EN are completely disconnected at the conductive isolation pillar 16.

[0113] For example, in embodiments of this disclosure, the substrate 11 can be a rigid substrate such as glass or quartz, or a flexible substrate such as polyimide or resin. The active layer 1021 of each transistor can be a semiconductor layer of various forms, such as an amorphous silicon layer, a polycrystalline silicon layer, or a metal oxide semiconductor layer. For example, the polycrystalline silicon can be high-temperature polycrystalline silicon or low-temperature polycrystalline silicon, and the oxide semiconductor can be indium gallium zinc oxide (IGZO), indium zinc oxide (IZO), zinc oxide (ZnO), or gallium zinc oxide (GZO), etc.

[0114] For example, the gate 1022 of each transistor can be made of metal materials or alloy materials such as copper (Cu), aluminum (Al), and titanium (Ti), and can be formed as a single-layer metal layer structure or a multi-layer metal layer structure, such as a titanium / aluminum / titanium multi-layer metal layer structure. The source / drain electrodes 1023 / 1024 of each transistor can be made of metal materials or alloy materials such as copper (Cu), aluminum (Al), and titanium (Ti), and can be formed as a single-layer metal layer structure or a multi-layer metal layer structure, such as a titanium / aluminum / titanium multi-layer metal layer structure.

[0115] For example, the material of the first electrode 13 can be a transparent metal oxide such as indium tin oxide (ITO), indium zinc oxide (IZO), or gallium zinc oxide (GZO), and the electrode material layer 15 can be a metal material such as lithium (Li), aluminum (Al), magnesium (Mg), or silver (Ag). The embodiments of this disclosure do not specifically limit the materials of each structure.

[0116] At least one embodiment of this disclosure also provides a display device, which includes the display substrate provided in the embodiments of this disclosure. For example, the display device can be any product or component with display function, such as a mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigator.

[0117] The display device provided in this disclosure can achieve higher resolution or higher light transmittance, thereby having a better display effect.

[0118] The following points also need to be explained:

[0119] (1) The accompanying drawings of the embodiments of this disclosure only involve the structures involved in the embodiments of this disclosure. Other structures can be referred to the general design.

[0120] (2) For clarity, the thickness of layers or regions is enlarged or reduced in the drawings used to describe embodiments of the present disclosure, i.e., these drawings are not drawn to actual scale. It will be understood that when an element such as a layer, film, region or substrate is referred to as being “above” or “below” another element, the element may be “directly” located “above” or “below” the other element or there may be intermediate elements.

[0121] (3) Where there is no conflict, the embodiments of this disclosure and the features in the embodiments can be combined with each other to obtain new embodiments.

[0122] The above are merely specific embodiments of this disclosure, but the scope of protection of this disclosure is not limited thereto. The scope of protection of this disclosure shall be determined by the scope of the claims.

Claims

1. A display substrate, comprising: a substrate, a drive circuit layer disposed on the substrate and comprising a plurality of conductive patterns, a pixel defining layer disposed on a side of the drive circuit layer distal to the substrate and comprising a plurality of sub-pixel openings, an isolation column layer disposed on a side of the pixel defining layer distal to the substrate and comprising at least one conductive isolation column, a light emitting material layer disposed in at least the plurality of sub-pixel openings and broken at the at least one conductive isolation column, wherein the at least one conductive isolation column is electrically connected to at least one of the plurality of conductive patterns via a via. 2.The display substrate of claim 1, wherein, the light emitting material layer comprises a first light emitting pattern and a second light emitting pattern, the first light emitting pattern and the second light emitting pattern are adjacently disposed and have different light emitting colors, the at least one conductive isolation column is disposed between the first light emitting pattern and the second light emitting pattern to interrupt the first light emitting pattern and the second light emitting pattern. 3.The display substrate of claim 2, wherein, a number of the first light emitting patterns is a plurality, the plurality of first light emitting patterns are arranged in a row along a first direction, a number of the second light emitting patterns is a plurality, the plurality of second light emitting patterns are arranged in a row along the first direction, the at least one conductive isolation column extends between the plurality of first light emitting patterns and the plurality of second light emitting patterns along the first direction. 4.The display substrate of claim 2, wherein, the light emitting material layer further comprises a third light emitting pattern, the third light emitting pattern has a light emitting color different from the first light emitting pattern and the second light emitting pattern, the first light emitting pattern and the second light emitting pattern are adjacent in a first direction, the first light emitting pattern and the third light emitting pattern are adjacent in a second direction, the second direction is different from the first direction, a planar shape of the at least one conductive isolation column is mesh-shaped to be respectively disposed between the first light emitting pattern and the second light emitting pattern and between the first light emitting pattern and the third light emitting pattern. the drive circuit layer comprises a transistor, a storage capacitor, and a plurality of signal lines, the transistor comprises a gate and a source-drain electrode, the storage capacitor comprises a first capacitor electrode and a second capacitor electrode, 5.The display substrate according to any one of claims 1-4, wherein, the plurality of conductive patterns comprises the gate, the source-drain electrode, the first capacitor electrode, the second capacitor electrode, and the plurality of signal lines. the drive circuit layer has a first conductive layer, a second conductive layer, and a third conductive layer stacked in sequence in a direction distal to the substrate, 6.The display substrate of claim 5, wherein, the gate and the first capacitor electrode are disposed in the first conductive layer, the second capacitor electrode is disposed in the second conductive layer, the source-drain electrode is disposed in the third conductive layer, the plurality of signal lines are respectively disposed in at least one of the first conductive layer, the second conductive layer, and the third conductive layer. the drive circuit layer has a first conductive layer, a second conductive layer, a third conductive layer, and a fourth conductive layer stacked in sequence in a direction distal to the substrate, 7.The display substrate of claim 5, wherein, the gate and the first capacitor electrode are disposed in the first conductive layer, the second capacitor electrode is disposed in the second conductive layer, the source-drain electrode is disposed in the third conductive layer, ​ The plurality of signal lines are arranged in at least one of the first conductive layer, the second conductive layer, the third conductive layer and the fourth conductive layer respectively. 8.The display substrate according to any one of claims 1-7, wherein, The plurality of conductive patterns include a reset voltage terminal, The at least one conductive isolation column is electrically connected with the reset voltage terminal through a via to serve as a reset voltage line.

9. The display substrate of claim 8, further comprising: an electrode material layer arranged on a side of the light emitting material layer away from the substrate, and arranged in at least the plurality of sub-pixel openings, wherein the electrode material layer is broken at the at least one conductive isolation column and in contact with the at least one conductive isolation column.

10. The display substrate according to any one of claims 1-7, wherein, The plurality of conductive patterns include a first power terminal, The at least one conductive isolation column is electrically connected with the first power terminal through a via to serve as a first power line.

11. The display substrate of claim 10, further comprising: an electrode material layer arranged on a side of the light emitting material layer away from the substrate, and arranged in at least the plurality of sub-pixel openings, wherein the light emitting material layer and the electrode material layer are insulated from the at least one conductive isolation column. 12.The display substrate of claim 5, wherein, The at least one conductive isolation column is electrically connected with at least one of the plurality of signal lines through a via to reduce the resistance of the at least one signal line.

13. The display substrate according to any one of claims 1-12, wherein, Each of the at least one conductive isolation column includes a first isolation pattern and a second isolation pattern stacked in sequence in a direction away from the substrate, a projection of the first isolation pattern on the substrate is located within a projection of the second isolation pattern on the substrate. 14.The display substrate of claim 13, wherein, Each of the at least one conductive isolation column further includes a third isolation pattern arranged on a side of the first isolation pattern close to the substrate, a projection of the first isolation pattern on the substrate is located within a projection of the third isolation pattern on the substrate.

15. The display substrate according to any one of claims 1-14, wherein, The longitudinal section of each of the at least one conductive isolation column is V-shaped as a whole.

16. A display device comprising the display substrate of any one of claims 1-15.

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