Analog-to-digital conversion circuit, chip and electronic device

Abstract

Provided in the present application are an analog-to-digital conversion circuit, a chip and an electronic device. The analog-to-digital conversion circuit comprises a first digital-to-analog conversion module and a first analog-to-digital conversion module, wherein the first digital-to-analog conversion module is configured to output quantization noise on the basis of a first conversion code value, a first reference voltage and an input voltage; and the first analog-to-digital conversion module comprises a shared quantization unit, and the shared quantization unit is configured to output the first conversion code value within a first time period on the basis of the input voltage and a third reference voltage and to output a second conversion code value within a second time period on the basis of a first analog voltage and a fourth reference voltage. The present application uses the shared quantization unit to respectively output the first conversion code value and the second conversion code value within different time periods of the same measurement period, thereby reusing a quantizer of a first-stage analog-to-digital converter and a second-stage analog-to-digital converter in a multi-stage noise shaping analog-to-digital converter, and finally reducing the circuit area of the multi-stage noise shaping analog-to-digital converter.

Description

Analog-to-digital conversion circuit, chip and electronic device

[0001] The present application claims priority to the Chinese patent application No. 202410812223.1, filed on June 21, 2024, and entitled "Analog-to-digital conversion circuit, chip and electronic device", the content of which is incorporated herein by reference in its entirety. TECHNICAL FIELD

[0002] The present application relates to the technical field of detection, in particular to an analog-to-digital conversion circuit, chip and electronic device. BACKGROUND

[0003] At present, a multi-stage noise shaping (MASH) analog-to-digital converter is a hybrid analog-to-digital converter composed of multiple analog-to-digital converters, which is commonly used in high-speed and high-precision analog-to-digital conversion scenarios. In the working process of the multi-stage noise shaping analog-to-digital converter, the first-stage analog-to-digital converter coarsely quantizes the input voltage and outputs the quantized noise, and the second-stage analog-to-digital converter further quantizes the noise output by the first-stage analog-to-digital converter with high precision, so that a high-precision conversion result of the input voltage can be obtained according to the conversion code values output by the first-stage analog-to-digital converter and the second-stage analog-to-digital converter. However, since the multi-stage noise shaping analog-to-digital converter includes multiple analog-to-digital converters, this leads to the problem of excessive circuit area of the multi-stage noise shaping analog-to-digital converter. TECHNICAL SOLUTION

[0004] In view of the above problems, the embodiments of the present application provide an analog-to-digital conversion circuit, chip and electronic device to solve the above technical problems.

[0005] In a first aspect, the embodiments of the present application provide an analog-to-digital conversion circuit, comprising:

[0006] A first digital-to-analog conversion module, configured to output quantization noise according to a first conversion code value, a first reference voltage and an input voltage;

[0007] A first analog-to-digital conversion module, configured to output a second conversion code value according to the quantization noise and a second reference voltage;

[0008] The first analog-to-digital conversion module comprises an analog voltage output unit and a shared quantization unit, the analog voltage output unit is configured to output a first analog voltage according to the quantization noise and the second reference voltage;

[0009] The shared quantization unit is configured to output the first conversion code value according to the input voltage and a third reference voltage in a first time period, and output the second conversion code value according to the first analog voltage and a fourth reference voltage in a second time period;

[0010] The first time period and the second time period are different time periods in a same measurement cycle.

[0011] In a second aspect, an embodiment of the present application provides a chip, comprising the analog-to-digital conversion circuit according to the first aspect.

[0012] In a third aspect, an embodiment of the present application provides an electronic device, comprising the chip according to the second aspect. BRIEF DESCRIPTION OF DRAWINGS

[0013] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed in the embodiment description will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative effort.

[0014] FIG. 1 shows a schematic diagram of a multi-stage noise shaping analog-to-digital converter in the related art.

[0015] FIG. 2 shows a schematic diagram of an analog-to-digital conversion circuit in an embodiment of the present application.

[0016] FIG. 3 shows a working sequence schematic diagram of a shared quantization unit in an embodiment of the present application.

[0017] FIG. 4 shows another schematic diagram of an analog-to-digital conversion circuit in an embodiment of the present application.

[0018] FIG. 5 shows a schematic diagram of a shared quantization unit in an embodiment of the present application.

[0019] FIG. 6 shows a working schematic diagram of a shared quantization unit in a first time period in an embodiment of the present application.

[0020] FIG. 7 shows a working schematic diagram of a shared quantization unit in a second time period in an embodiment of the present application.

[0021] FIG. 8 shows another working schematic diagram of a shared quantization unit in a second time period in an embodiment of the present application.

[0022] FIG. 9 shows another schematic diagram of a shared quantization unit in an embodiment of the present application.

[0023] FIG. 10 shows another working schematic diagram of a shared quantization unit in a first time period in an embodiment of the present application.

[0024] FIG. 11 shows another working schematic diagram of a shared quantization unit in a second time period in an embodiment of the present application.

[0025] FIG. 12 shows another schematic diagram of an analog-to-digital conversion circuit in an embodiment of the present application.

[0026] Fig. 13 shows another schematic diagram of the analog-to-digital conversion circuit according to an embodiment of the present application.

[0027] Fig. 14 shows another schematic diagram of the analog-to-digital conversion circuit according to an embodiment of the present application.

[0028] Fig. 15 shows another schematic diagram of the analog-to-digital conversion circuit according to an embodiment of the present application.

[0029] Fig. 16 shows another schematic diagram of the analog-to-digital conversion circuit according to an embodiment of the present application.

[0030] Fig. 17 shows another schematic diagram of the analog-to-digital conversion circuit according to an embodiment of the present application.

[0031] Fig. 18 shows another schematic diagram of the analog-to-digital conversion circuit according to an embodiment of the present application.

[0032] wherein 10 is a first digital-to-analog conversion module, 20 is a first analog-to-digital conversion module, 21 is an analog voltage output unit, 211 is a digital-to-analog converter, 212 is an integrator, 22 is a shared quantization unit, 221 is a comparator, 222 is an analog operation subunit; VI is an input voltage, D1 is a first conversion code value, D2 is a second conversion code value, E1 is quantization noise, VO1 is a first analog voltage, V1 is a first reference voltage, V2 is a second reference voltage, V3 is a third reference voltage, V4 is a fourth reference voltage, V01 is a first voltage signal, V02 is a second voltage signal, Qrf is a feedback charge signal; S0 is a first total switch, S01 is a first sub-switch, S02 is a second sub-switch, C1 is a first capacitor, S03 is a third sub-switch, S04 is a fourth sub-switch, C2 is a second capacitor, S05 is a fifth sub-switch, C3 is a third capacitor, S06 is a sixth sub-switch, S07 is a seventh sub-switch; OP is an operational amplifier, CI is a first integration capacitor, S1 is a first switch, S2 is a second switch, S3 is a third switch, S4 is a fourth switch, CF is a first feedback capacitor, S5 is a fifth switch, S6 is a sixth switch, S7 is a seventh switch, CS is a first sampling capacitor, CL is a first quantization capacitor.

[0033] Embodiments of the present application

[0034] Embodiments of the present application are described in detail below with reference to the attached drawings, wherein the same or similar components have the same or similar designations throughout the various figures. The embodiments described below are exemplary and are not intended to be limiting of the present application, unless otherwise explicitly indicated herein.

[0035] In the following, the technical solutions in the embodiments of the present application will be described clearly and completely in conjunction with the drawings in the embodiments of the present application, so that those skilled in the art can better understand the solutions in the present application. Obviously, the described embodiments are only some of the embodiments of the present application, but not all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work fall within the scope of protection of the present application.

[0036] It should be noted that in the embodiments of the present application, in this document, the terms such as first and second are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply there is any such actual relationship or order between these entities or operations.

[0037] Moreover, the terms "comprising", "containing", or any other variant thereof are intended to cover a non-exclusive inclusion, so that a process, method, article, or apparatus that comprises a list of elements not only includes those elements, but also includes other elements not explicitly listed, or further includes elements inherent in such process, method, article, or apparatus. Without more limitations, the element defined by the phrase "comprising a" does not exclude the presence of additional identical elements in the process, method, article, or apparatus that includes the element.

[0038] In the description of the embodiments of the present application, the words "example" or "for example" are used to mean serving as an example, instance, or illustration. Any embodiment or design solution described as "example" or "for example" in the embodiments of the present application is not to be construed as being more preferred than another embodiment or design solution. The use of the words "example" or "for example" is intended to present clearly relative concepts in a clear manner.

[0039] In addition, "multiple" in the embodiments of the present application means two or more, and therefore "multiple" in the embodiments of the present application can also be understood as "at least two". "At least one" can be understood as one or more, for example, as one, two or more. For example, including at least one means including one, two or more, and does not limit which ones are included, for example, including at least one of A, B and C means including A, B, C, A and B, A and C, B and C, or A and B and C.

[0040] It should be noted that "connection" in the embodiments of the present application can be understood as electrical connection, and the connection between two electrical elements can be direct or indirect connection between the two electrical elements. For example, A is connected to B, which can be direct connection between A and B, or indirect connection between A and B through one or more other electrical elements.

[0041] Currently, a multi-stage noise-shaping (MASH) analog-to-digital converter is a hybrid analog-to-digital converter composed of multiple analog-to-digital converters, which is commonly used in high-speed and high-precision analog-to-digital conversion scenarios. Referring to FIG. 1, FIG. 1 shows a schematic diagram of a multi-stage noise-shaping analog-to-digital converter in the related art, wherein the multi-stage noise-shaping analog-to-digital converter includes a Flash ADC composed of a quantizer 1 and a digital-to-analog converter DAC1, and a Sigma-Delta ADC composed of an integrator, a quantizer 2, and a digital-to-analog converter DAC2.

[0042] In each measurement period of the multi-stage noise-shaping analog-to-digital converter, the quantizer 1 coarsely quantizes the input voltage Vin and obtains a conversion code value D01, and then outputs an analog voltage Vdac corresponding to the conversion code value D01 through the digital-to-analog converter DAC1 to obtain a quantization error E01 = Vin-Vdac, and then the Sigma-Delta ADC further quantizes the quantization error E01 and outputs a conversion code value D02, and finally obtains a conversion code value of the input voltage Vin according to the conversion code value D01 and the conversion code value D02.

[0043] For example, the size of the input voltage Vin is 3.32V, in the first measurement period, the conversion code value D01 output by the Flash ADC to the input voltage Vin is 011 (representing 3V), and the quantization error E01 input to the Sigma-Delta ADC is 0.32V, the integration result of the integrator in the first measurement period is 0.32V, and the conversion code value D02 output by the quantizer 2 is 011 (representing 0.3V), and the analog voltage Vdac2 fed back by the digital-to-analog converter DAC2 is -0.8V (here it is assumed that the reference voltage fed back by the Sigma-Delta ADC is 0.8V).

[0044] In the second measurement period, the conversion code value D01 output by the Flash ADC to the input voltage Vin is 011 (representing 3V), and the quantization error E01 input to the Sigma-Delta ADC is 0.32V, the integration result of the integrator in the second measurement period is -0.8+0.32+0.32=-0.16V, the conversion code value D02 output by the quantizer 2 is 000 (representing 0V), and the analog voltage Vdac2 fed back by the digital-to-analog converter DAC2 is +0.8V.

[0045] In the third measurement period, the conversion code value D01 output by the Flash ADC for the input voltage Vin is 011 (representing 3V), and the quantization error E01 input into the Sigma-Delta ADC is 0.32V. The integral result of the integrator in the second measurement period is 0.8-0.16+0.32=0.96V, the conversion code value D02 output by the quantizer 2 is 111 (representing 0.7V), and the analog voltage Vdac2 fed back by the analog-digital converter DAC2 is -0.8V;

[0046] In the fourth measurement period, the conversion code value D01 output by the Flash ADC for the input voltage Vin is 011 (representing 3V), and the quantization error E01 input into the Sigma-Delta ADC is 0.32V. The integral result of the integrator in the second measurement period is -0.8+0.96+0.32=0.48V, the conversion code value D02 output by the quantizer 2 is 100 (representing 0.4V), and the analog voltage Vdac fed back by the analog-digital converter DAC2 is -0.8V, and so on.

[0047] After four measurement periods, the conversion code value D01 output by the Flash ADC is all 011 (representing 3V), and the conversion code value D02 output by the Sigma-Delta ADC is 011 (representing 0.3V), 000 (representing 0V), 111 (representing 0.7V), and 100 (representing 0.4V) respectively. Therefore, the voltage value corresponding to the conversion code value can be calculated according to the following formula:

[0048] Vout=(3+0.3+3+3+0.7+3+0.4) / 4=3.35V

[0049] As can be seen, after multiple measurement periods, the voltage value corresponding to the conversion code value is closer to the input voltage Vin, so that the multi-stage noise shaping analog-digital converter can perform high-precision analog-digital conversion on the input voltage. However, since the multi-stage noise shaping analog-digital converter includes multiple analog-digital converters, this leads to the problem of excessive circuit area of the multi-stage noise shaping analog-digital converter.

[0050] Therefore, the present application provides an analog-digital conversion circuit, a chip and an electronic device. Please refer to FIG. 2, which shows a schematic diagram of an analog-digital conversion circuit in an embodiment of the present application. The analog-digital conversion circuit includes a first digital-analog conversion module 10 and a first analog-digital conversion module 20.

[0051] Specifically, the first digital-to-analog conversion module 10 is configured to output a quantization noise E1 according to the first conversion code value D1, the first reference voltage V1 and the input voltage VI. For example, the first conversion code value D1 is 011, the first reference voltage V1 is 8V, at this time the analog voltage corresponding to the first conversion code value D1 is 3V, if the input voltage VI is 3.4V, then the first digital-to-analog conversion module 10 can output a quantization noise E1 of 0.4V. For another example, the first conversion code value D1 is 011, the first reference voltage V1 is 7V, at this time the analog voltage corresponding to the first conversion code value D1 is 3V, if the input voltage VI is 3.2V, then the first digital-to-analog conversion module 10 can output a quantization noise E1 of 0.2V.

[0052] Exemplarily, the first digital-to-analog conversion module 10 can include but is not limited to a capacitance type digital-to-analog converter, a resistance type digital-to-analog converter, a current type digital-to-analog converter, etc., so as to convert the first conversion code value D1 into a corresponding analog signal according to the first reference voltage V1 by the analog-to-digital converter.

[0053] The first analog-to-digital conversion module 20 is configured to output a second conversion code value D2 according to the quantization noise E1 and the second reference voltage V2. For example, the first digital-to-analog conversion module 10 outputs a quantization noise E1 of 0.4V, the first analog-to-digital conversion module 20 can convert the quantization noise E1 of 0.4V into a second conversion code value D2 of 100, and the high-precision input voltage VI analog-to-digital conversion process can be realized by combining the first conversion code value D1. For another example, the first digital-to-analog conversion module 10 outputs a quantization noise E1 of 0.05V, the first analog-to-digital conversion module 20 can convert the quantization noise E1 of 0.05V into a second conversion code value D2 of 001, and the high-precision input voltage VI analog-to-digital conversion process can be realized by combining the first conversion code value D1.

[0054] Exemplarily, the first analog-to-digital conversion module 20 can include but is not limited to a successive approximation register analog-to-digital converter (SAR ADC), a sigma-delta analog-to-digital converter (SD-ADC), a flash analog-to-digital converter (FLASH ADC), etc.

[0055] The first analog-to-digital conversion module 20 includes an analog voltage output unit 21 and a shared quantization unit 22, the analog voltage output unit 21 is configured to output a first analog voltage VO according to the quantization noise E1 and the second reference voltage V2, so that the shared quantization unit 22 quantizes the first analog voltage VO and outputs the second conversion code value D2.

[0056] In some embodiments of the present application, for example, for the embodiment in which the first analog-to-digital conversion module 20 comprises a successive approximation analog-to-digital converter, the analog voltage output unit 21 can refer to a digital-to-analog converter in the successive approximation analog-to-digital converter, the first analog voltage VO can refer to an analog voltage output by the digital-to-analog converter in the successive approximation analog-to-digital converter, and the shared quantization unit 22 can refer to one or more comparators in the successive approximation analog-to-digital converter.

[0057] In some other embodiments of the present application, for example, for the embodiment in which the first analog-to-digital conversion module 20 comprises a sigma-delta analog-to-digital converter, the analog voltage output unit 21 can refer to a digital-to-analog converter and an integrator 212 in the sigma-delta analog-to-digital converter, the first analog voltage VO can refer to a voltage signal output by the integrator in the sigma-delta analog-to-digital converter, and the shared quantization unit 22 can refer to one or more comparators in the sigma-delta analog-to-digital converter.

[0058] In the embodiments of the present application, the shared quantization unit 22 outputs a first conversion code value D1 according to the input voltage VI and a third reference voltage V3 in a first time period and outputs a second conversion code value D2 according to the first analog voltage VO and a fourth reference voltage V4 in a second time period, wherein the first time period and the second time period are different time periods in a same measurement cycle. For example, FIG. 3 shows a schematic diagram of a working sequence of the shared quantization unit 22 in the embodiments of the present application. In a time period in which a clock signal is at a high level, the shared quantization unit 22 outputs the first conversion code value D1 according to the input voltage VI and the third reference voltage V3, and in a time period in which the clock signal is at a low level, the shared quantization unit 22 outputs the second conversion code value D2 according to the first analog voltage VO and the fourth reference voltage V4, so that the shared quantization unit 22 not only functions as a quantizer of the first-stage analog-to-digital converter to coarsely quantize the input voltage VI and output the first conversion code value D1, but also functions as a quantizer of the second-stage analog-to-digital converter to further quantize the quantization noise E1 and output the second conversion code value D2.

[0059] That is, the present application multiplexes the quantizers of the first-stage analog-to-digital converter and the second-stage analog-to-digital converter in the multi-stage noise shaping analog-to-digital converter, and utilizes the shared quantization unit 22 to output the first conversion code value D1 and the second conversion code value D2 in different time periods in a same measurement cycle, so as to complete the multi-stage noise shaping analog-to-digital conversion process. Compared with the prior art, the present application does not need to respectively set quantizers for the first-stage analog-to-digital converter and the second-stage analog-to-digital converter, thereby being conducive to reducing the circuit area of the multi-stage noise shaping analog-to-digital converter.

[0060] It should be noted that, unless otherwise specified, each voltage and signal (e.g., input voltage VI, first reference voltage V1, second reference voltage V2, third reference voltage V3, fourth reference voltage V4, quantization noise E1, first analog voltage VO, etc.) in the present application can be a single-ended signal or a differential signal, and the present application does not make a specific limitation. When a certain circuit diagram shows that a voltage / signal is a single-ended signal, those skilled in the art can make adaptive modifications to obtain a circuit diagram corresponding to a differential signal according to the diagram.

[0061] In some embodiments of the present application, the shared quantization unit 22 includes at least one comparator 221; in a first time period, the input terminals of the comparator 221 are connected to the input voltage VI and the third reference voltage V3; in a second time period, the input terminals of the comparator 221 are connected to the first analog voltage VO and the fourth reference voltage V4.

[0062] For example, referring to FIG. 4, FIG. 4 shows another schematic diagram of an analog-to-digital conversion circuit in an embodiment of the present application. In a first time period, switches s1 and s3 are closed, switches s2 and s4 are open, the non-inverting input terminal of the comparator 221 is connected to the input voltage VI, and the inverting input terminal of the comparator 221 is connected to the third reference voltage V3. When the input voltage VI is greater than the third reference voltage V3, the comparator 221 outputs a first conversion code value D1 of “1”; otherwise, when the input voltage VI is less than the third reference voltage V3, the comparator 221 outputs a first conversion code value D1 of “0”.

[0063] In a second time period, switches s1 and s3 are open, switches s2 and s4 are closed, the non-inverting input terminal of the comparator 221 is connected to the first analog voltage VO, and the inverting input terminal of the comparator 221 is connected to the fourth reference voltage V4. When the input voltage VI is greater than the fourth reference voltage V4, the comparator 221 outputs a second conversion code value D2 of “1”; otherwise, when the input voltage VI is less than the fourth reference voltage V4, the comparator 221 outputs a second conversion code value D2 of “0”.

[0064] It can be seen that, by controlling the voltages connected to the input terminals of the comparator 221, the above-mentioned embodiments can achieve the purpose of outputting the first conversion code value D1 in the first time period and outputting the second conversion code value D2 in the second time period, respectively.

[0065] In some embodiments of the present application, referring to FIG. 5, FIG. 5 shows a schematic diagram of a shared quantization unit 22 in an embodiment of the present application. The shared quantization unit 22 includes at least one analog operator unit 222 and at least one comparator 221. The analog operator unit 222 can output a voltage signal after converting (e.g., subtracting) a plurality of voltage signals, so that the comparator 221 can determine the size relationship between the plurality of voltage signals by judging the positive and negative of the voltage signal output by the analog operator unit 222.

[0066] For example, referring to FIG. 6, FIG. 6 shows a working schematic diagram of the shared quantization unit 22 in the first time period in the embodiment of the present application, in the first time period, the analog operator unit 222 accesses the input voltage VI and the third reference voltage V3 and outputs a first voltage signal V01, the size of the first voltage signal V01 satisfies the following formula:

[0067] V01 = VI - V3

[0068] That is, the size of the first voltage signal V01 is equal to the difference between the input voltage VI and the third reference voltage V3, so the comparator 221 can compare the size of the input voltage VI and the third reference voltage V3 by judging the positive and negative of the first voltage signal V01, and finally make the comparator 221 output the first conversion code value D1 according to the first voltage signal V01.

[0069] For another example, referring to FIG. 7, FIG. 7 shows a working schematic diagram of the shared quantization unit 22 in the second time period in the embodiment of the present application, in the second time period, the analog operator unit 222 accesses the first analog voltage VO and the fourth reference voltage V4 and outputs a second voltage signal V02, the size of the second voltage signal V02 satisfies:

[0070] V02 = VO - V4

[0071] That is, the size of the second voltage signal V02 is equal to the difference between the first analog voltage VO and the fourth reference voltage V4, so the comparator 221 can compare the size of the first analog voltage VO and the fourth reference voltage V4 by judging the positive and negative of the second voltage signal V02, and finally make the comparator 221 output the second conversion code value D2 according to the second voltage signal V02.

[0072] It should be noted that, since the first-stage analog-to-digital converter in the multi-stage noise shaping analog-to-digital converter is coarse quantization, and the second-stage analog-to-digital converter is fine quantization, the third reference voltage V3 is usually large, and the fourth reference voltage V4 is usually small, which leads to the need to configure third reference voltage V3 and fourth reference voltage V4 with different sizes in the shared quantization unit 22, and the corresponding circuit is needed to generate the third reference voltage V3 and the fourth reference voltage V4, which also leads to the phenomenon of increasing the circuit area of the multi-stage noise shaping analog-to-digital converter. To solve this technical problem, please refer to the following content:

[0073] In some embodiments of the present application, referring to FIG. 8, FIG. 8 shows another working schematic diagram of the shared quantization unit 22 in the second time period in the embodiments of the present application, in the second time period, the analog operator unit 222 accesses the input voltage VI, the first analog voltage VO and the fourth reference voltage V4 and outputs the second voltage signal V02, and the size of the second voltage signal V02 satisfies the following formula:

[0074] V02 = VO + VI - V4

[0075] Compared with the embodiment in which the second voltage signal satisfies the relationship V02 = VO - V4, this is equivalent to the comparator 221 comparing the size of VI - V4 with the first analog voltage VO, in order to ensure that VI - V4 corresponds to the smaller first analog voltage VO, therefore, the fourth reference voltage V4 can be appropriately increased, when the third reference voltage V3 and the fourth reference voltage V4 are equal in size, then the shared quantization unit 22 can access only one reference voltage, thereby being beneficial to further reducing the circuit area and power consumption of the analog-to-digital conversion circuit.

[0076] It should be noted that the voltages shown in the above FIGS. 6 to 8 are all single-ended signals, which are only exemplary embodiments, but are not limited thereto, in fact, the voltages can also be differential signals, for example, referring to FIG. 9, FIG. 9 shows another schematic diagram of the shared quantization unit 22 in the embodiments of the present application, the input voltage VI includes differential signals VIp and VIn, the third reference voltage V3 includes differential signals V3p and V3n, the first analog voltage VO includes differential signals VOp and VOn, and the fourth reference voltage V4 includes differential signals V4p and V4n, one analog operator unit 222 outputs a differential signal processed by analog operation according to the differential signals VIp, V3p, VOp and V4p, and another analog operator unit 222 outputs another differential signal processed by analog operation according to the differential signals VIn, V3n, VOn and V4n.

[0077] For example, referring to FIG. 10, FIG. 10 shows another working schematic diagram of the shared quantization unit 22 in the first time period in the embodiments of the present application, the first voltage signal V01 includes differential signals V01p and V01n, and V01p and V01n satisfy the following formula:

[0078] At this time, the voltage difference between the non-inverting input terminal and the inverting input terminal of the comparator 221 is:

[0079] It can be seen that the comparator 221 is actually judging the size of the differential voltage corresponding to the input voltage VI and the third reference voltage V3 at this time, and thus the comparator 221 can also output the first conversion code value D1 according to the input voltage VI and the third preset reference in the first time period.

[0080] Referring to FIG. 11, FIG. 11 shows another working schematic diagram of the shared quantization unit 22 in the second time period in the embodiment of the present application. The second voltage signal V02 includes the differential signals V02p and V02n, and V02p and V02n satisfy the following formulae: V02p = VOp + VIp - V4p V01n = VOn + VIn - V4n

[0081] At this time, the voltage difference between the non-inverting input terminal and the inverting input terminal of the comparator 221 is: ΔV02 = (VIp - VIn) + (VIp - VIn) - (V3p - V3n)

[0082] It can be seen that the comparator 221 is actually judging the positive and negative of VO + VI - V4 at this time, and thus the comparator 221 can also output the second conversion code value D2 according to the first analog voltage VO, the input voltage VI and the fourth reference voltage V4 in the second time period.

[0083] In some embodiments of the present application, referring to FIG. 12, FIG. 12 shows another schematic diagram of the analog-digital conversion circuit in the embodiment of the present application. The analog operation sub-unit 222 includes a first total switch S0, a first sub-switch S01, a second sub-switch S02, a first capacitor C1, a third sub-switch S03, a fourth sub-switch S04, a second capacitor C2, a fifth sub-switch S05 and a third capacitor C3. The first plates of the first capacitor C1, the second capacitor C2 and the third capacitor C3 are connected to each other. One end of the first total switch S0 is connected to the input terminal of the comparator 221, and the other end is connected to the first plate of the first capacitor C1. One end of the first sub-switch S01 is connected to the third reference voltage V3 or the fourth reference voltage V4, and the other end is connected to the second plate of the first capacitor C1. One end of the second sub-switch S02 is connected to the common-mode voltage VCM, and the other end is connected to the second plate of the first capacitor C1. One end of the third sub-switch S03 is connected to the first analog voltage VO, and the other end is connected to the second plate of the second capacitor C2. One end of the fourth sub-switch S04 is connected to the common-mode voltage VCM, and the other end is connected to the second plate of the second capacitor C2. One end of the fifth sub-switch S05 is connected to the input voltage VI, and the other end is connected to the second plate of the third capacitor C3. One end of the sixth sub-switch S06 is connected to the common-mode voltage VCM, and the other end is connected to the first plate of the third capacitor C3. One end of the seventh sub-switch S07 is connected to the common-mode voltage VCM, and the other end is connected to the second plate of the third capacitor C3.

[0084] It should be noted that, in the first period, when the first total switch S0, the second sub-switch S02, the third sub-switch S03, the fourth sub-switch S04, the fifth sub-switch S05, the seventh sub-switch S07 are opened, the first sub-switch S01, the sixth sub-switch S06 are closed, at this time, the charge accumulated by the first capacitor C1, the second capacitor C2 and the third capacitor C3 is: Q = (V3-VCM)*C

[0085] Wherein, △V is the voltage difference between the two ends of the first capacitor C1, C is the capacitance value of the first capacitor C1, the second capacitor C2 and the third capacitor C3.

[0086] And in the first period, when the first sub-switch S01, the third sub-switch S03, the fourth sub-switch S04, the sixth sub-switch S06, the seventh sub-switch S07 are opened, the first total switch S0, the second sub-switch S02, the fifth sub-switch S05 are closed, because the charge amount of the first capacitor C1 is unchanged, it can be known that: (V3-VCM)*C = (VCM-VX)*C + (VI-VX)*C

[0087] Wherein, VX is the voltage of the first plate of the first capacitor C1.

[0088] Taking VCM = 0V as an example, the voltage of the first plate of the first capacitor C1 (that is, the voltage of the non-inverting input terminal of the comparator) is: Vx = (VI-V3) / 2

[0089] It can be seen that, through the above switch control process, the comparator 221 is judging the positive and negative of VI-V3 at this time, and finally the first conversion code value D1 can be output according to the comparison result.

[0090] In the second period, when the first total switch S0, the second sub-switch S02, the third sub-switch S03, the fourth sub-switch S04, the fifth sub-switch S05, the seventh sub-switch S07 are opened, the first sub-switch S01, the sixth sub-switch S06 are closed, the charge amount accumulated by the first capacitor C1, the second capacitor C2 and the third capacitor C3 is: Q = (V3-VCM)*C

[0091] In the second period, when the first sub-switch S01, the fourth sub-switch S04, the fifth sub-switch S05, the sixth sub-switch S06, the seventh sub-switch S07 are opened, the first total switch S0, the second sub-switch S02, the third sub-switch S03, the fifth sub-switch S05 are closed, according to the charge conservation, it can be known that: (V3-VCM)*C = (VCM-VX)*C + (VI-VX)*C + (VO-VX)*C

[0092] Wherein, VX is the voltage of the first plate of the first capacitor C1.

[0093] Taking VCM=0V as an example, the voltage of the plate of the in-phase input end of the comparator 221 is: Vx=(VO+VI-V3) / 3

[0094] It can be seen that, through the above switch control process, the comparator 221 is currently judging the positive and negative of VO+VI-V3, and finally the comparison result can output the second conversion code value D2.

[0095] It can be understood that the above embodiment is exemplarily described by taking a single-ended signal and a common differential circuit as an example, and for the implementation for a differential signal, the above FIG. 12 can be modified into a fully differential circuit structure as shown in FIG. 13.

[0096] In some embodiments of the present application, for example, for the embodiment in which the first analog-digital conversion module 20 comprises a Σ-Δ analog-digital converter, referring to FIG. 14, FIG. 14 shows another schematic diagram of an analog-digital conversion circuit in an embodiment of the present application, the analog voltage output unit 21 comprises a digital-analog converter 211 and an integrator 212; the digital-analog converter 211 is used to output a feedback charge signal Qrf according to the second reference voltage V2 and the second conversion code value D2 output by the shared quantization unit 22 in the second time period of the last measurement period; the integrator 212 is used to integrate the quantization noise E1 and the feedback charge signal Qrf, so as to output the first analog voltage VO after completing the integration.

[0097] It should be noted that, since the shared quantization unit 22 performs negative feedback control on the digital-analog converter, the first analog voltage VO output by the integrator 212 always fluctuates around the fourth reference voltage V4 (or the third reference voltage V3), for example, when the second conversion code value D2 output by the shared quantization unit 22 in a measurement period is “1”, the digital-analog converter 211 will output a feedback charge signal Qrf with positive electricity to the integrator 212, so that the first analog voltage VO output by the integrator 212 decreases; on the contrary, when the second conversion code value D2 output by the shared quantization unit 22 in a measurement period is “0”, the digital-analog converter 211 will output a feedback charge signal Qrf with negative electricity to the integrator 212, so that the first analog voltage VO output by the integrator 212 increases.

[0098] After a plurality of measurement periods, the first analog voltage VO output by the integrator 212 relative to the total amount of its integration can be ignored, and therefore, according to the charge conservation, the following formula can be obtained: E1*C0*(X+Y)=V2*C0*X-V2*C0*Y

[0099] Wherein, C0 is a unit capacitance, X is the number of times that the digital-analog converter 211 outputs a feedback charge signal Qrf with positive electricity to the integrator 212, and Y is the number of times that the digital-analog converter 211 outputs a feedback charge signal Qrf with negative electricity to the integrator 212.

[0100] Finally, the quantization noise E1 can be measured after a plurality of cycles as follows: E1 = V2 * (X - Y) / (X + Y)

[0101] It can be seen that, since X is the number of code values 1 (or 0) in the second conversion code value D2, and Y is the number of code values 0 (or 1) in the second conversion code value D2, the quantization noise E1 can be quantized by the second conversion code value D2 output by the shared quantization unit 22 in the second period, and in combination with the first conversion code value D1 output by the shared quantization unit 22 in the first period, to finally obtain a high-precision conversion result of the input voltage VI.

[0102] In some embodiments of the present application, the integrator 212 can output the first analog voltage VO in the second period of each measurement cycle, so that the shared quantization unit 22 can output the second conversion code value D2 according to the first analog voltage VO in the second period. In some embodiments of the present application, the integrator 212 can output the first analog voltage VO in the first period of each measurement cycle, that is, the integrator 212 can output the first analog voltage VO in advance, so that the shared quantization unit 22 can immediately output the second conversion code value D2 according to the first analog voltage VO after entering the second period, so as to shorten the length of the measurement cycle of the analog-digital conversion circuit, thereby improving the conversion rate of the analog-digital conversion circuit.

[0103] Similarly, in some embodiments of the present application, the first digital-analog conversion module 10 can output the quantization noise E1 in the second period, so that the integrator 212 can integrate the quantization noise E1 in the second period. In some embodiments of the present application, the first digital-analog conversion module 10 can output the quantization noise E1 in the first period, so that the integrator 212 can integrate the quantization noise E1 in the first period / or the second period and output the first analog voltage VO, and when the integrator 212 integrates the quantization noise E1 in the second period, it is beneficial to improve the conversion rate of the analog-digital conversion circuit.

[0104] In some embodiments of the present application, the integrator 212 includes an operational amplifier OP and a first integration capacitor CI; a first plate of the first integration capacitor CI is connected to an input terminal of the operational amplifier OP, and a second plate of the first integration capacitor CI is connected to an output terminal of the operational amplifier OP. For example, taking a common differential circuit as an example, referring to FIG. 15, FIG. 15 shows another schematic diagram of the analog-digital conversion circuit; the first plate of the first integration capacitor CI is connected to a non-inverting input terminal of the operational amplifier OP, the second plate of the first integration capacitor CI is connected to the output terminal of the operational amplifier OP, and an inverting input terminal of the operational amplifier OP is connected to a common-mode voltage VCM, so that the first integration capacitor CI and the operational amplifier OP form an integrator 212 in a common differential form.

[0105] In some embodiments of the present application, referring to FIG. 16, FIG. 16 shows another schematic diagram of the analog-to-digital conversion circuit in the embodiments of the present application, wherein the digital-to-analog converter 211 comprises a first switch S1, a second switch S2, a third switch S3, a fourth switch S4, and a first feedback capacitor CF; one end of the first switch S1 is connected to the second reference voltage V2, and the other end is connected to a first plate of the feedback capacitor; one end of the second switch S2 is connected to the common-mode voltage VCM, and the other end is connected to the first plate of the feedback capacitor; one end of the third switch S3 is connected to a second plate of the feedback capacitor, and the other end is connected to the common-mode voltage VCM; one end of the fourth switch S4 is connected to the second plate of the feedback capacitor, and the other end is connected to an input end of the integrator 212.

[0106] It should be noted that when the second switch S2 and the third switch S3 are in the closed state, and the first switch S1 and the fourth switch S4 are in the open state, the amount of charge accumulated by the first feedback capacitor CF is 0; and when the second switch S2 and the third switch S3 are switched to the open state, and the first switch S1 and the fourth switch S4 are switched to the closed state, the amount of charge accumulated by the second plate of the first feedback capacitor CF is -(V2-VCM)*C0, which is equivalent to the second plate of the first feedback capacitor CF releasing a positive feedback charge signal Qrf with a charge amount of (V2-VCM)*C0, thereby achieving the purpose of the digital-to-analog converter outputting a positive feedback charge signal Qrf.

[0107] Conversely, when the first switch S1 and the third switch S3 are in the closed state, and the second switch S2 and the fourth switch S4 are in the open state, the amount of charge accumulated by the second plate of the first feedback capacitor CF is -(V2-VCM)*C0; and when the first switch S1 and the third switch S3 are switched to the open state, and the second switch S2 and the fourth switch S4 are switched to the closed state, the amount of charge accumulated by the second plate of the first feedback capacitor CF is 0, which is equivalent to the second plate of the first feedback capacitor CF releasing a negative feedback charge signal Qrf with a charge amount of -(V2-VCM)*C0, thereby achieving the purpose of the digital-to-analog converter outputting a negative feedback charge signal Qrf.

[0108] It can be seen that through the above switch control process, the digital-to-analog converter can output a positive / negative feedback charge signal Qrf, so as to make the first analog voltage VO output by the integrator 212 always fluctuate around the fourth reference voltage V4 (or the third reference voltage V3).

[0109] In some embodiments of the present application, referring to FIG. 17, FIG. 17 shows another schematic diagram of the analog-to-digital conversion circuit in the embodiments of the present application, wherein the first digital-to-analog conversion module 10 comprises a fifth switch S5, a sixth switch S6, a seventh switch S7, an eighth switch, a first sampling capacitor CS and a first quantization capacitor CL; one end of the fifth switch S5 is connected to the input voltage VI, and the other end is connected to a first plate of the first sampling capacitor CS; one end of the sixth switch S6 is connected to a second plate of the first sampling capacitor CS, and the other end is connected to the analog voltage output unit 21; one end of the seventh switch S7 is connected to the second plate of the first sampling capacitor CS, and the other end is connected to the common-mode voltage VCM; one end of the eighth switch is connected to the first reference voltage V1, and the other end is connected to a first plate of the first quantization capacitor CL, and a second plate of the first quantization capacitor CL is connected to the second plate of the first sampling capacitor CS.

[0110] It should be noted that when the fifth switch S5 is closed, and the sixth switch S6, the seventh switch S7 and the eighth switch are opened, the amount of charge accumulated by the first sampling capacitor CS is QE1=(VI-VCM)*C0, and when the sixth switch S6, the seventh switch S7 and the eighth switch are closed, and the fifth switch S5 is opened, the amount of charge released by the second plate of the first sampling capacitor CS is equal to QE=(VI-VCM)*C0-D1*V1*C0.

[0111] It can be seen that the first conversion code value D1 controls the amount of charge released by the second plate of the first sampling capacitor CS, and thus the quantization noise E1 can be finally output according to the input voltage VI, the first reference voltage V1 and the first conversion code value D1, so that the first analog-to-digital conversion module 20 quantizes the quantization noise E1.

[0112] It can be understood that in the above description, details are listed for the purpose of explanation. It should be understood that those skilled in the art can realize the present application without using these specific details. In other examples, well-known structures and processes will not be described in detail to avoid unnecessary details making the description of the present application obscure, for example, a reset switch can also be provided for each capacitor (such as the first capacitor C1, the first sampling capacitor CS, the first quantization capacitor CL, etc.), and the reset switch is connected to the two plates of the capacitor respectively, and the amount of charge accumulated by the capacitor is reset through the reset switch.

[0113] Meanwhile, it is worth noting that the above content about the analog-to-digital conversion circuit is intended to clearly illustrate the implementation and verification process of the embodiments of the present application, and those skilled in the art can also make equivalent modifications and designs under the guidance of the present application, for example, FIG. 16 and FIG. 17 take single-ended signal and ordinary differential circuit as an example for illustrative description, and for the implementation of differential signal, those skilled in the art can also modify the above circuit diagram to the full differential circuit structure as shown in FIG. 18.

[0114] The embodiment of the present application further provides a chip, which comprises the analog-to-digital conversion circuit. The chip (IC) can be a SOC (System on Chip) chip, a SIP (system in package) chip, but is not limited to the above. Since the chip has the analog-to-digital conversion circuit described in the above embodiment, the chip has all the beneficial effects of the analog-to-digital conversion circuit described in the above embodiment, which will not be repeated here.

[0115] The embodiment of the present application further provides an electronic device, which comprises a device main body and the chip as described above arranged in the device main body. The electronic device can be, but is not limited to, a body weight scale, a body fat scale, a nutrition scale, an infrared electronic thermometer, a pulse oximeter, a human body composition analyzer, a mobile power supply, a wireless charger, a fast charger, a vehicle charger, an adapter, a display, a USB (Universal Serial Bus) docking station, a touch pen, a true wireless earphone, a car control panel, a car, a smart wearable device, a mobile terminal, a smart home device. The smart wearable device includes, but is not limited to, a smart watch, a smart bracelet, a cervical vertebra massage instrument. The mobile terminal includes, but is not limited to, a smart phone, a notebook computer, a tablet computer, a POS (point of sales terminal) machine. The smart home device includes, but is not limited to, a smart socket, a smart rice cooker, a smart sweeper, a smart lamp.

[0116] The above is only a preferred embodiment of the present application, and does not limit the present application in any form. Although the present application has been disclosed as the preferred embodiment, it is not intended to limit the present application. Any person skilled in the art can make some changes or modifications to the above disclosed technical content to obtain equivalent embodiments with equivalent changes, without departing from the scope of the technical solution of the present application. Any modification, change and modification of the above embodiment according to the technical essence of the present application, as long as it does not deviate from the technical solution of the present application, is still within the scope of the technical solution of the present application.

Claims

1. An analog-to-digital converter circuit, characterized in that, include: A first digital-to-analog converter module is used to output quantized noise based on a first conversion code value, a first reference voltage, and an input voltage. A first analog-to-digital conversion module is configured to output a second conversion code value based on the quantization noise and the second reference voltage. The first analog-to-digital conversion module includes an analog voltage output unit and a shared quantization unit. The analog voltage output unit is used to output a first analog voltage based on the quantization noise and the second reference voltage. The shared quantization unit is used to output the first conversion code value according to the input voltage and the third reference voltage in a first time period, and to output the second conversion code value according to the first analog voltage and the fourth reference voltage in a second time period; The first time period and the second time period are time periods with the same measurement cycle but different time periods.

2. The analog-to-digital converter circuit as described in claim 1, characterized in that, The shared quantization unit includes at least one comparator; During the first time period, the input terminal of the comparator is connected to the input voltage and the third reference voltage; During the second time period, the input of the comparator is connected to the first analog voltage and the fourth reference voltage.

3. The analog-to-digital converter circuit as described in claim 1, characterized in that, The shared quantization unit includes at least one analog operation subunit and at least one comparator; During the first time period, the analog operation subunit receives the input voltage and the third reference voltage and outputs a first voltage signal, and the comparator outputs the first conversion code value according to the first voltage signal; During the second time period, the analog operation subunit receives the input voltage, the first analog voltage, and the fourth reference voltage and outputs a second voltage signal. The comparator outputs the second conversion code value based on the second voltage signal.

4. The analog-to-digital converter circuit as described in claim 3, characterized in that, The third reference voltage is equal in magnitude to the fourth reference voltage.

5. The analog-to-digital converter circuit as described in claim 3, characterized in that, The analog operation subunit includes a first master switch, a first sub-switch, a second sub-switch, a first capacitor, a third sub-switch, a fourth sub-switch, a second capacitor, a fifth sub-switch, a third capacitor, a sixth sub-switch, and a seventh sub-switch; The first plates of the first capacitor, the second capacitor, and the third capacitor are connected to each other. One end of the first main switch is connected to the input terminal of the comparator, and the other end is connected to the first plate of the first capacitor. One end of the first sub-switch is connected to the third reference voltage or the fourth reference voltage, and the other end is connected to the second plate of the first capacitor; One end of the second sub-switch is connected to a common-mode voltage, and the other end is connected to the second plate of the first capacitor; One end of the third sub-switch is connected to the first analog voltage, and the other end is connected to the second plate of the second capacitor; One end of the fourth sub-switch is connected to the common-mode voltage, and the other end is connected to the second plate of the second capacitor; One end of the fifth sub-switch is connected to the input voltage, and the other end is connected to the second plate of the third capacitor; One end of the sixth sub-switch is connected to the common-mode voltage, and the other end is connected to the first plate of the third capacitor; One end of the seventh sub-switch is connected to the common-mode voltage, and the other end is connected to the second plate of the third capacitor.

6. The analog-to-digital converter circuit as described in claim 1, characterized in that, The analog voltage output unit includes a digital-to-analog converter and an integrator; The digital-to-analog converter is used to output a feedback charge signal based on the second reference voltage and the second conversion code value output by the shared quantization unit in the second time period of the previous measurement cycle; The integrator is used to integrate the quantization noise and the feedback charge signal to output the first analog voltage after integration is completed.

7. The analog-to-digital converter circuit as described in claim 6, characterized in that, The integrator outputs the first analog voltage during the second time period of each measurement cycle; or The integrator outputs the first analog voltage during the first time period of each measurement cycle.

8. The analog-to-digital converter circuit as described in claim 6, characterized in that, The integrator includes an operational amplifier and a first integrating capacitor; The first plate of the first integrating capacitor is connected to the input terminal of the operational amplifier, and the second plate of the first integrating capacitor is connected to the output terminal of the operational amplifier.

9. The analog-to-digital converter circuit as described in claim 6, characterized in that, The digital-to-analog converter includes a first switch, a second switch, a third switch, a fourth switch, and a first feedback capacitor; One end of the first switch is connected to the second reference voltage, and the other end is connected to the first plate of the feedback capacitor; One end of the second switch is connected to a common-mode voltage, and the other end is connected to the first plate of the feedback capacitor; One end of the third switch is connected to the second plate of the feedback capacitor, and the other end is connected to the common-mode voltage; One end of the fourth switch is connected to the second plate of the feedback capacitor, and the other end is connected to the input terminal of the integrator.

10. The analog-to-digital converter circuit as described in claim 1, characterized in that, The first digital-to-analog converter module outputs the quantization noise during the first time period; or The first digital-to-analog conversion module outputs the quantization noise during the second time period.

11. The analog-to-digital converter circuit as described in claim 1, characterized in that, The first digital-to-analog conversion module includes a fifth switch, a sixth switch, a seventh switch, an eighth switch, a first sampling capacitor, and a first quantization capacitor; One end of the fifth switch is connected to the input voltage, and the other end is connected to the first plate of the first sampling capacitor; One end of the sixth switch is connected to the second plate of the first sampling capacitor, and the other end is connected to the analog voltage output unit. One end of the seventh switch is connected to the first plate of the first sampling capacitor, and the other end is connected to a common-mode voltage. One end of the eighth switch is connected to the first reference voltage, and the other end is connected to the first plate of the first quantization capacitor. The second plate of the first quantization capacitor is connected to the second plate of the first sampling capacitor.

12. A chip, characterized in that, Includes the analog-to-digital conversion circuit as described in any one of claims 1 to 11.

13. An electronic device, characterized in that, Including the chip as described in claim 12.

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